1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/pcs/pcs-mtk-lynxi.h> 18 #include <linux/phylink.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/reset.h> 22 #include <linux/gpio/consumer.h> 23 #include <linux/gpio/driver.h> 24 #include <net/dsa.h> 25 26 #include "mt7530.h" 27 28 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 29 { 30 return container_of(pcs, struct mt753x_pcs, pcs); 31 } 32 33 /* String, offset, and register size in bytes if different from 4 bytes */ 34 static const struct mt7530_mib_desc mt7530_mib[] = { 35 MIB_DESC(1, 0x00, "TxDrop"), 36 MIB_DESC(1, 0x04, "TxCrcErr"), 37 MIB_DESC(1, 0x08, "TxUnicast"), 38 MIB_DESC(1, 0x0c, "TxMulticast"), 39 MIB_DESC(1, 0x10, "TxBroadcast"), 40 MIB_DESC(1, 0x14, "TxCollision"), 41 MIB_DESC(1, 0x18, "TxSingleCollision"), 42 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 43 MIB_DESC(1, 0x20, "TxDeferred"), 44 MIB_DESC(1, 0x24, "TxLateCollision"), 45 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 46 MIB_DESC(1, 0x2c, "TxPause"), 47 MIB_DESC(1, 0x30, "TxPktSz64"), 48 MIB_DESC(1, 0x34, "TxPktSz65To127"), 49 MIB_DESC(1, 0x38, "TxPktSz128To255"), 50 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 51 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 52 MIB_DESC(1, 0x44, "Tx1024ToMax"), 53 MIB_DESC(2, 0x48, "TxBytes"), 54 MIB_DESC(1, 0x60, "RxDrop"), 55 MIB_DESC(1, 0x64, "RxFiltering"), 56 MIB_DESC(1, 0x68, "RxUnicast"), 57 MIB_DESC(1, 0x6c, "RxMulticast"), 58 MIB_DESC(1, 0x70, "RxBroadcast"), 59 MIB_DESC(1, 0x74, "RxAlignErr"), 60 MIB_DESC(1, 0x78, "RxCrcErr"), 61 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 62 MIB_DESC(1, 0x80, "RxFragErr"), 63 MIB_DESC(1, 0x84, "RxOverSzErr"), 64 MIB_DESC(1, 0x88, "RxJabberErr"), 65 MIB_DESC(1, 0x8c, "RxPause"), 66 MIB_DESC(1, 0x90, "RxPktSz64"), 67 MIB_DESC(1, 0x94, "RxPktSz65To127"), 68 MIB_DESC(1, 0x98, "RxPktSz128To255"), 69 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 70 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 71 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 72 MIB_DESC(2, 0xa8, "RxBytes"), 73 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 74 MIB_DESC(1, 0xb4, "RxIngressDrop"), 75 MIB_DESC(1, 0xb8, "RxArlDrop"), 76 }; 77 78 /* Since phy_device has not yet been created and 79 * phy_{read,write}_mmd_indirect is not available, we provide our own 80 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 81 * to complete this function. 82 */ 83 static int 84 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 85 { 86 struct mii_bus *bus = priv->bus; 87 int value, ret; 88 89 /* Write the desired MMD Devad */ 90 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 91 if (ret < 0) 92 goto err; 93 94 /* Write the desired MMD register address */ 95 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 96 if (ret < 0) 97 goto err; 98 99 /* Select the Function : DATA with no post increment */ 100 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 101 if (ret < 0) 102 goto err; 103 104 /* Read the content of the MMD's selected register */ 105 value = bus->read(bus, 0, MII_MMD_DATA); 106 107 return value; 108 err: 109 dev_err(&bus->dev, "failed to read mmd register\n"); 110 111 return ret; 112 } 113 114 static int 115 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 116 int devad, u32 data) 117 { 118 struct mii_bus *bus = priv->bus; 119 int ret; 120 121 /* Write the desired MMD Devad */ 122 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 123 if (ret < 0) 124 goto err; 125 126 /* Write the desired MMD register address */ 127 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 128 if (ret < 0) 129 goto err; 130 131 /* Select the Function : DATA with no post increment */ 132 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 133 if (ret < 0) 134 goto err; 135 136 /* Write the data into MMD's selected register */ 137 ret = bus->write(bus, 0, MII_MMD_DATA, data); 138 err: 139 if (ret < 0) 140 dev_err(&bus->dev, 141 "failed to write mmd register\n"); 142 return ret; 143 } 144 145 static void 146 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 147 { 148 struct mii_bus *bus = priv->bus; 149 150 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 151 152 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 153 154 mutex_unlock(&bus->mdio_lock); 155 } 156 157 static void 158 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 159 { 160 struct mii_bus *bus = priv->bus; 161 u32 val; 162 163 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 164 165 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 166 val &= ~mask; 167 val |= set; 168 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 169 170 mutex_unlock(&bus->mdio_lock); 171 } 172 173 static void 174 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 175 { 176 core_rmw(priv, reg, 0, val); 177 } 178 179 static void 180 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 181 { 182 core_rmw(priv, reg, val, 0); 183 } 184 185 static int 186 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 187 { 188 struct mii_bus *bus = priv->bus; 189 u16 page, r, lo, hi; 190 int ret; 191 192 page = (reg >> 6) & 0x3ff; 193 r = (reg >> 2) & 0xf; 194 lo = val & 0xffff; 195 hi = val >> 16; 196 197 /* MT7530 uses 31 as the pseudo port */ 198 ret = bus->write(bus, 0x1f, 0x1f, page); 199 if (ret < 0) 200 goto err; 201 202 ret = bus->write(bus, 0x1f, r, lo); 203 if (ret < 0) 204 goto err; 205 206 ret = bus->write(bus, 0x1f, 0x10, hi); 207 err: 208 if (ret < 0) 209 dev_err(&bus->dev, 210 "failed to write mt7530 register\n"); 211 return ret; 212 } 213 214 static u32 215 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 216 { 217 struct mii_bus *bus = priv->bus; 218 u16 page, r, lo, hi; 219 int ret; 220 221 page = (reg >> 6) & 0x3ff; 222 r = (reg >> 2) & 0xf; 223 224 /* MT7530 uses 31 as the pseudo port */ 225 ret = bus->write(bus, 0x1f, 0x1f, page); 226 if (ret < 0) { 227 dev_err(&bus->dev, 228 "failed to read mt7530 register\n"); 229 return ret; 230 } 231 232 lo = bus->read(bus, 0x1f, r); 233 hi = bus->read(bus, 0x1f, 0x10); 234 235 return (hi << 16) | (lo & 0xffff); 236 } 237 238 static void 239 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 240 { 241 struct mii_bus *bus = priv->bus; 242 243 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 244 245 mt7530_mii_write(priv, reg, val); 246 247 mutex_unlock(&bus->mdio_lock); 248 } 249 250 static u32 251 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 252 { 253 return mt7530_mii_read(p->priv, p->reg); 254 } 255 256 static u32 257 _mt7530_read(struct mt7530_dummy_poll *p) 258 { 259 struct mii_bus *bus = p->priv->bus; 260 u32 val; 261 262 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 263 264 val = mt7530_mii_read(p->priv, p->reg); 265 266 mutex_unlock(&bus->mdio_lock); 267 268 return val; 269 } 270 271 static u32 272 mt7530_read(struct mt7530_priv *priv, u32 reg) 273 { 274 struct mt7530_dummy_poll p; 275 276 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 277 return _mt7530_read(&p); 278 } 279 280 static void 281 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 282 u32 mask, u32 set) 283 { 284 struct mii_bus *bus = priv->bus; 285 u32 val; 286 287 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 288 289 val = mt7530_mii_read(priv, reg); 290 val &= ~mask; 291 val |= set; 292 mt7530_mii_write(priv, reg, val); 293 294 mutex_unlock(&bus->mdio_lock); 295 } 296 297 static void 298 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 299 { 300 mt7530_rmw(priv, reg, 0, val); 301 } 302 303 static void 304 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 305 { 306 mt7530_rmw(priv, reg, val, 0); 307 } 308 309 static int 310 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 311 { 312 u32 val; 313 int ret; 314 struct mt7530_dummy_poll p; 315 316 /* Set the command operating upon the MAC address entries */ 317 val = ATC_BUSY | ATC_MAT(0) | cmd; 318 mt7530_write(priv, MT7530_ATC, val); 319 320 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 321 ret = readx_poll_timeout(_mt7530_read, &p, val, 322 !(val & ATC_BUSY), 20, 20000); 323 if (ret < 0) { 324 dev_err(priv->dev, "reset timeout\n"); 325 return ret; 326 } 327 328 /* Additional sanity for read command if the specified 329 * entry is invalid 330 */ 331 val = mt7530_read(priv, MT7530_ATC); 332 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 333 return -EINVAL; 334 335 if (rsp) 336 *rsp = val; 337 338 return 0; 339 } 340 341 static void 342 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 343 { 344 u32 reg[3]; 345 int i; 346 347 /* Read from ARL table into an array */ 348 for (i = 0; i < 3; i++) { 349 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 350 351 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 352 __func__, __LINE__, i, reg[i]); 353 } 354 355 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 356 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 357 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 358 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 359 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 360 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 361 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 362 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 363 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 364 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 365 } 366 367 static void 368 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 369 u8 port_mask, const u8 *mac, 370 u8 aging, u8 type) 371 { 372 u32 reg[3] = { 0 }; 373 int i; 374 375 reg[1] |= vid & CVID_MASK; 376 reg[1] |= ATA2_IVL; 377 reg[1] |= ATA2_FID(FID_BRIDGED); 378 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 379 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 380 /* STATIC_ENT indicate that entry is static wouldn't 381 * be aged out and STATIC_EMP specified as erasing an 382 * entry 383 */ 384 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 385 reg[1] |= mac[5] << MAC_BYTE_5; 386 reg[1] |= mac[4] << MAC_BYTE_4; 387 reg[0] |= mac[3] << MAC_BYTE_3; 388 reg[0] |= mac[2] << MAC_BYTE_2; 389 reg[0] |= mac[1] << MAC_BYTE_1; 390 reg[0] |= mac[0] << MAC_BYTE_0; 391 392 /* Write array into the ARL table */ 393 for (i = 0; i < 3; i++) 394 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 395 } 396 397 /* Set up switch core clock for MT7530 */ 398 static void mt7530_pll_setup(struct mt7530_priv *priv) 399 { 400 /* Disable PLL */ 401 core_write(priv, CORE_GSWPLL_GRP1, 0); 402 403 /* Set core clock into 500Mhz */ 404 core_write(priv, CORE_GSWPLL_GRP2, 405 RG_GSWPLL_POSDIV_500M(1) | 406 RG_GSWPLL_FBKDIV_500M(25)); 407 408 /* Enable PLL */ 409 core_write(priv, CORE_GSWPLL_GRP1, 410 RG_GSWPLL_EN_PRE | 411 RG_GSWPLL_POSDIV_200M(2) | 412 RG_GSWPLL_FBKDIV_200M(32)); 413 } 414 415 /* Setup TX circuit including relevant PAD and driving */ 416 static int 417 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 418 { 419 struct mt7530_priv *priv = ds->priv; 420 u32 ncpo1, ssc_delta, trgint, i, xtal; 421 422 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 423 424 if (xtal == HWTRAP_XTAL_20MHZ) { 425 dev_err(priv->dev, 426 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 427 __func__); 428 return -EINVAL; 429 } 430 431 switch (interface) { 432 case PHY_INTERFACE_MODE_RGMII: 433 trgint = 0; 434 break; 435 case PHY_INTERFACE_MODE_TRGMII: 436 trgint = 1; 437 if (priv->id == ID_MT7621) { 438 /* PLL frequency: 150MHz: 1.2GBit */ 439 if (xtal == HWTRAP_XTAL_40MHZ) 440 ncpo1 = 0x0780; 441 if (xtal == HWTRAP_XTAL_25MHZ) 442 ncpo1 = 0x0a00; 443 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 444 if (xtal == HWTRAP_XTAL_40MHZ) 445 ncpo1 = 0x0c80; 446 if (xtal == HWTRAP_XTAL_25MHZ) 447 ncpo1 = 0x1400; 448 } 449 break; 450 default: 451 dev_err(priv->dev, "xMII interface %d not supported\n", 452 interface); 453 return -EINVAL; 454 } 455 456 if (xtal == HWTRAP_XTAL_25MHZ) 457 ssc_delta = 0x57; 458 else 459 ssc_delta = 0x87; 460 461 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 462 P6_INTF_MODE(trgint)); 463 464 if (trgint) { 465 /* Lower Tx Driving for TRGMII path */ 466 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 467 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 468 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 469 470 /* Disable MT7530 core and TRGMII Tx clocks */ 471 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, 472 REG_GSWCK_EN | REG_TRGMIICK_EN); 473 474 /* Setup the MT7530 TRGMII Tx Clock */ 475 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 476 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 477 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 478 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 479 core_write(priv, CORE_PLL_GROUP4, 480 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 481 RG_SYSPLL_BIAS_LPF_EN); 482 core_write(priv, CORE_PLL_GROUP2, 483 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 484 RG_SYSPLL_POSDIV(1)); 485 core_write(priv, CORE_PLL_GROUP7, 486 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 487 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 488 489 /* Enable MT7530 core and TRGMII Tx clocks */ 490 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 491 REG_GSWCK_EN | REG_TRGMIICK_EN); 492 } else { 493 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 494 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 495 RD_TAP_MASK, RD_TAP(16)); 496 } 497 498 return 0; 499 } 500 501 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 502 { 503 u32 val; 504 505 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 506 507 return (val & PAD_DUAL_SGMII_EN) != 0; 508 } 509 510 static int 511 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 512 { 513 return 0; 514 } 515 516 static void 517 mt7531_pll_setup(struct mt7530_priv *priv) 518 { 519 u32 top_sig; 520 u32 hwstrap; 521 u32 xtal; 522 u32 val; 523 524 if (mt7531_dual_sgmii_supported(priv)) 525 return; 526 527 val = mt7530_read(priv, MT7531_CREV); 528 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 529 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 530 if ((val & CHIP_REV_M) > 0) 531 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 532 HWTRAP_XTAL_FSEL_25MHZ; 533 else 534 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 535 536 /* Step 1 : Disable MT7531 COREPLL */ 537 val = mt7530_read(priv, MT7531_PLLGP_EN); 538 val &= ~EN_COREPLL; 539 mt7530_write(priv, MT7531_PLLGP_EN, val); 540 541 /* Step 2: switch to XTAL output */ 542 val = mt7530_read(priv, MT7531_PLLGP_EN); 543 val |= SW_CLKSW; 544 mt7530_write(priv, MT7531_PLLGP_EN, val); 545 546 val = mt7530_read(priv, MT7531_PLLGP_CR0); 547 val &= ~RG_COREPLL_EN; 548 mt7530_write(priv, MT7531_PLLGP_CR0, val); 549 550 /* Step 3: disable PLLGP and enable program PLLGP */ 551 val = mt7530_read(priv, MT7531_PLLGP_EN); 552 val |= SW_PLLGP; 553 mt7530_write(priv, MT7531_PLLGP_EN, val); 554 555 /* Step 4: program COREPLL output frequency to 500MHz */ 556 val = mt7530_read(priv, MT7531_PLLGP_CR0); 557 val &= ~RG_COREPLL_POSDIV_M; 558 val |= 2 << RG_COREPLL_POSDIV_S; 559 mt7530_write(priv, MT7531_PLLGP_CR0, val); 560 usleep_range(25, 35); 561 562 switch (xtal) { 563 case HWTRAP_XTAL_FSEL_25MHZ: 564 val = mt7530_read(priv, MT7531_PLLGP_CR0); 565 val &= ~RG_COREPLL_SDM_PCW_M; 566 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 567 mt7530_write(priv, MT7531_PLLGP_CR0, val); 568 break; 569 case HWTRAP_XTAL_FSEL_40MHZ: 570 val = mt7530_read(priv, MT7531_PLLGP_CR0); 571 val &= ~RG_COREPLL_SDM_PCW_M; 572 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 573 mt7530_write(priv, MT7531_PLLGP_CR0, val); 574 break; 575 } 576 577 /* Set feedback divide ratio update signal to high */ 578 val = mt7530_read(priv, MT7531_PLLGP_CR0); 579 val |= RG_COREPLL_SDM_PCW_CHG; 580 mt7530_write(priv, MT7531_PLLGP_CR0, val); 581 /* Wait for at least 16 XTAL clocks */ 582 usleep_range(10, 20); 583 584 /* Step 5: set feedback divide ratio update signal to low */ 585 val = mt7530_read(priv, MT7531_PLLGP_CR0); 586 val &= ~RG_COREPLL_SDM_PCW_CHG; 587 mt7530_write(priv, MT7531_PLLGP_CR0, val); 588 589 /* Enable 325M clock for SGMII */ 590 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 591 592 /* Enable 250SSC clock for RGMII */ 593 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 594 595 /* Step 6: Enable MT7531 PLL */ 596 val = mt7530_read(priv, MT7531_PLLGP_CR0); 597 val |= RG_COREPLL_EN; 598 mt7530_write(priv, MT7531_PLLGP_CR0, val); 599 600 val = mt7530_read(priv, MT7531_PLLGP_EN); 601 val |= EN_COREPLL; 602 mt7530_write(priv, MT7531_PLLGP_EN, val); 603 usleep_range(25, 35); 604 } 605 606 static void 607 mt7530_mib_reset(struct dsa_switch *ds) 608 { 609 struct mt7530_priv *priv = ds->priv; 610 611 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 612 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 613 } 614 615 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 616 { 617 return mdiobus_read_nested(priv->bus, port, regnum); 618 } 619 620 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 621 u16 val) 622 { 623 return mdiobus_write_nested(priv->bus, port, regnum, val); 624 } 625 626 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 627 int devad, int regnum) 628 { 629 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 630 } 631 632 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 633 int regnum, u16 val) 634 { 635 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 636 } 637 638 static int 639 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 640 int regnum) 641 { 642 struct mii_bus *bus = priv->bus; 643 struct mt7530_dummy_poll p; 644 u32 reg, val; 645 int ret; 646 647 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 648 649 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 650 651 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 652 !(val & MT7531_PHY_ACS_ST), 20, 100000); 653 if (ret < 0) { 654 dev_err(priv->dev, "poll timeout\n"); 655 goto out; 656 } 657 658 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 659 MT7531_MDIO_DEV_ADDR(devad) | regnum; 660 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 661 662 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 663 !(val & MT7531_PHY_ACS_ST), 20, 100000); 664 if (ret < 0) { 665 dev_err(priv->dev, "poll timeout\n"); 666 goto out; 667 } 668 669 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 670 MT7531_MDIO_DEV_ADDR(devad); 671 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 672 673 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 674 !(val & MT7531_PHY_ACS_ST), 20, 100000); 675 if (ret < 0) { 676 dev_err(priv->dev, "poll timeout\n"); 677 goto out; 678 } 679 680 ret = val & MT7531_MDIO_RW_DATA_MASK; 681 out: 682 mutex_unlock(&bus->mdio_lock); 683 684 return ret; 685 } 686 687 static int 688 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 689 int regnum, u16 data) 690 { 691 struct mii_bus *bus = priv->bus; 692 struct mt7530_dummy_poll p; 693 u32 val, reg; 694 int ret; 695 696 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 697 698 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 699 700 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 701 !(val & MT7531_PHY_ACS_ST), 20, 100000); 702 if (ret < 0) { 703 dev_err(priv->dev, "poll timeout\n"); 704 goto out; 705 } 706 707 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 708 MT7531_MDIO_DEV_ADDR(devad) | regnum; 709 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 710 711 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 712 !(val & MT7531_PHY_ACS_ST), 20, 100000); 713 if (ret < 0) { 714 dev_err(priv->dev, "poll timeout\n"); 715 goto out; 716 } 717 718 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 719 MT7531_MDIO_DEV_ADDR(devad) | data; 720 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 721 722 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 723 !(val & MT7531_PHY_ACS_ST), 20, 100000); 724 if (ret < 0) { 725 dev_err(priv->dev, "poll timeout\n"); 726 goto out; 727 } 728 729 out: 730 mutex_unlock(&bus->mdio_lock); 731 732 return ret; 733 } 734 735 static int 736 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 737 { 738 struct mii_bus *bus = priv->bus; 739 struct mt7530_dummy_poll p; 740 int ret; 741 u32 val; 742 743 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 744 745 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 746 747 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 748 !(val & MT7531_PHY_ACS_ST), 20, 100000); 749 if (ret < 0) { 750 dev_err(priv->dev, "poll timeout\n"); 751 goto out; 752 } 753 754 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 755 MT7531_MDIO_REG_ADDR(regnum); 756 757 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 758 759 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 760 !(val & MT7531_PHY_ACS_ST), 20, 100000); 761 if (ret < 0) { 762 dev_err(priv->dev, "poll timeout\n"); 763 goto out; 764 } 765 766 ret = val & MT7531_MDIO_RW_DATA_MASK; 767 out: 768 mutex_unlock(&bus->mdio_lock); 769 770 return ret; 771 } 772 773 static int 774 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 775 u16 data) 776 { 777 struct mii_bus *bus = priv->bus; 778 struct mt7530_dummy_poll p; 779 int ret; 780 u32 reg; 781 782 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 783 784 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 785 786 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 787 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 788 if (ret < 0) { 789 dev_err(priv->dev, "poll timeout\n"); 790 goto out; 791 } 792 793 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 794 MT7531_MDIO_REG_ADDR(regnum) | data; 795 796 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 797 798 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 799 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 800 if (ret < 0) { 801 dev_err(priv->dev, "poll timeout\n"); 802 goto out; 803 } 804 805 out: 806 mutex_unlock(&bus->mdio_lock); 807 808 return ret; 809 } 810 811 static int 812 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 813 { 814 struct mt7530_priv *priv = bus->priv; 815 816 return priv->info->phy_read_c22(priv, port, regnum); 817 } 818 819 static int 820 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 821 { 822 struct mt7530_priv *priv = bus->priv; 823 824 return priv->info->phy_read_c45(priv, port, devad, regnum); 825 } 826 827 static int 828 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 829 { 830 struct mt7530_priv *priv = bus->priv; 831 832 return priv->info->phy_write_c22(priv, port, regnum, val); 833 } 834 835 static int 836 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 837 u16 val) 838 { 839 struct mt7530_priv *priv = bus->priv; 840 841 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 842 } 843 844 static void 845 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 846 uint8_t *data) 847 { 848 int i; 849 850 if (stringset != ETH_SS_STATS) 851 return; 852 853 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 854 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 855 ETH_GSTRING_LEN); 856 } 857 858 static void 859 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 860 uint64_t *data) 861 { 862 struct mt7530_priv *priv = ds->priv; 863 const struct mt7530_mib_desc *mib; 864 u32 reg, i; 865 u64 hi; 866 867 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 868 mib = &mt7530_mib[i]; 869 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 870 871 data[i] = mt7530_read(priv, reg); 872 if (mib->size == 2) { 873 hi = mt7530_read(priv, reg + 4); 874 data[i] |= hi << 32; 875 } 876 } 877 } 878 879 static int 880 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 881 { 882 if (sset != ETH_SS_STATS) 883 return 0; 884 885 return ARRAY_SIZE(mt7530_mib); 886 } 887 888 static int 889 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 890 { 891 struct mt7530_priv *priv = ds->priv; 892 unsigned int secs = msecs / 1000; 893 unsigned int tmp_age_count; 894 unsigned int error = -1; 895 unsigned int age_count; 896 unsigned int age_unit; 897 898 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 899 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 900 return -ERANGE; 901 902 /* iterate through all possible age_count to find the closest pair */ 903 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 904 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 905 906 if (tmp_age_unit <= AGE_UNIT_MAX) { 907 unsigned int tmp_error = secs - 908 (tmp_age_count + 1) * (tmp_age_unit + 1); 909 910 /* found a closer pair */ 911 if (error > tmp_error) { 912 error = tmp_error; 913 age_count = tmp_age_count; 914 age_unit = tmp_age_unit; 915 } 916 917 /* found the exact match, so break the loop */ 918 if (!error) 919 break; 920 } 921 } 922 923 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 924 925 return 0; 926 } 927 928 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 929 { 930 struct mt7530_priv *priv = ds->priv; 931 u8 tx_delay = 0; 932 int val; 933 934 mutex_lock(&priv->reg_mutex); 935 936 val = mt7530_read(priv, MT7530_MHWTRAP); 937 938 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 939 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 940 941 switch (priv->p5_intf_sel) { 942 case P5_INTF_SEL_PHY_P0: 943 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 944 val |= MHWTRAP_PHY0_SEL; 945 fallthrough; 946 case P5_INTF_SEL_PHY_P4: 947 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 948 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 949 950 /* Setup the MAC by default for the cpu port */ 951 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 952 break; 953 case P5_INTF_SEL_GMAC5: 954 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 955 val &= ~MHWTRAP_P5_DIS; 956 break; 957 case P5_DISABLED: 958 interface = PHY_INTERFACE_MODE_NA; 959 break; 960 default: 961 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 962 priv->p5_intf_sel); 963 goto unlock_exit; 964 } 965 966 /* Setup RGMII settings */ 967 if (phy_interface_mode_is_rgmii(interface)) { 968 val |= MHWTRAP_P5_RGMII_MODE; 969 970 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 971 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 972 973 /* Don't set delay in DSA mode */ 974 if (!dsa_is_dsa_port(priv->ds, 5) && 975 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 976 interface == PHY_INTERFACE_MODE_RGMII_ID)) 977 tx_delay = 4; /* n * 0.5 ns */ 978 979 /* P5 RGMII TX Clock Control: delay x */ 980 mt7530_write(priv, MT7530_P5RGMIITXCR, 981 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 982 983 /* reduce P5 RGMII Tx driving, 8mA */ 984 mt7530_write(priv, MT7530_IO_DRV_CR, 985 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 986 } 987 988 mt7530_write(priv, MT7530_MHWTRAP, val); 989 990 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 991 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 992 993 priv->p5_interface = interface; 994 995 unlock_exit: 996 mutex_unlock(&priv->reg_mutex); 997 } 998 999 static int 1000 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1001 { 1002 struct mt7530_priv *priv = ds->priv; 1003 int ret; 1004 1005 /* Setup max capability of CPU port at first */ 1006 if (priv->info->cpu_port_config) { 1007 ret = priv->info->cpu_port_config(ds, port); 1008 if (ret) 1009 return ret; 1010 } 1011 1012 /* Enable Mediatek header mode on the cpu port */ 1013 mt7530_write(priv, MT7530_PVC_P(port), 1014 PORT_SPEC_TAG); 1015 1016 /* Disable flooding by default */ 1017 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK, 1018 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); 1019 1020 /* Set CPU port number */ 1021 if (priv->id == ID_MT7621) 1022 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1023 1024 /* CPU port gets connected to all user ports of 1025 * the switch. 1026 */ 1027 mt7530_write(priv, MT7530_PCR_P(port), 1028 PCR_MATRIX(dsa_user_ports(priv->ds))); 1029 1030 /* Set to fallback mode for independent VLAN learning */ 1031 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1032 MT7530_PORT_FALLBACK_MODE); 1033 1034 return 0; 1035 } 1036 1037 static int 1038 mt7530_port_enable(struct dsa_switch *ds, int port, 1039 struct phy_device *phy) 1040 { 1041 struct dsa_port *dp = dsa_to_port(ds, port); 1042 struct mt7530_priv *priv = ds->priv; 1043 1044 mutex_lock(&priv->reg_mutex); 1045 1046 /* Allow the user port gets connected to the cpu port and also 1047 * restore the port matrix if the port is the member of a certain 1048 * bridge. 1049 */ 1050 if (dsa_port_is_user(dp)) { 1051 struct dsa_port *cpu_dp = dp->cpu_dp; 1052 1053 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1054 } 1055 priv->ports[port].enable = true; 1056 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1057 priv->ports[port].pm); 1058 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1059 1060 mutex_unlock(&priv->reg_mutex); 1061 1062 return 0; 1063 } 1064 1065 static void 1066 mt7530_port_disable(struct dsa_switch *ds, int port) 1067 { 1068 struct mt7530_priv *priv = ds->priv; 1069 1070 mutex_lock(&priv->reg_mutex); 1071 1072 /* Clear up all port matrix which could be restored in the next 1073 * enablement for the port. 1074 */ 1075 priv->ports[port].enable = false; 1076 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1077 PCR_MATRIX_CLR); 1078 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1079 1080 mutex_unlock(&priv->reg_mutex); 1081 } 1082 1083 static int 1084 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1085 { 1086 struct mt7530_priv *priv = ds->priv; 1087 struct mii_bus *bus = priv->bus; 1088 int length; 1089 u32 val; 1090 1091 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1092 * largest MTU of the slave ports. Because the switch only has a global 1093 * RX length register, only allowing CPU port here is enough. 1094 */ 1095 if (!dsa_is_cpu_port(ds, port)) 1096 return 0; 1097 1098 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 1099 1100 val = mt7530_mii_read(priv, MT7530_GMACCR); 1101 val &= ~MAX_RX_PKT_LEN_MASK; 1102 1103 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1104 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1105 if (length <= 1522) { 1106 val |= MAX_RX_PKT_LEN_1522; 1107 } else if (length <= 1536) { 1108 val |= MAX_RX_PKT_LEN_1536; 1109 } else if (length <= 1552) { 1110 val |= MAX_RX_PKT_LEN_1552; 1111 } else { 1112 val &= ~MAX_RX_JUMBO_MASK; 1113 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1114 val |= MAX_RX_PKT_LEN_JUMBO; 1115 } 1116 1117 mt7530_mii_write(priv, MT7530_GMACCR, val); 1118 1119 mutex_unlock(&bus->mdio_lock); 1120 1121 return 0; 1122 } 1123 1124 static int 1125 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1126 { 1127 return MT7530_MAX_MTU; 1128 } 1129 1130 static void 1131 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1132 { 1133 struct mt7530_priv *priv = ds->priv; 1134 u32 stp_state; 1135 1136 switch (state) { 1137 case BR_STATE_DISABLED: 1138 stp_state = MT7530_STP_DISABLED; 1139 break; 1140 case BR_STATE_BLOCKING: 1141 stp_state = MT7530_STP_BLOCKING; 1142 break; 1143 case BR_STATE_LISTENING: 1144 stp_state = MT7530_STP_LISTENING; 1145 break; 1146 case BR_STATE_LEARNING: 1147 stp_state = MT7530_STP_LEARNING; 1148 break; 1149 case BR_STATE_FORWARDING: 1150 default: 1151 stp_state = MT7530_STP_FORWARDING; 1152 break; 1153 } 1154 1155 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1156 FID_PST(FID_BRIDGED, stp_state)); 1157 } 1158 1159 static int 1160 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1161 struct switchdev_brport_flags flags, 1162 struct netlink_ext_ack *extack) 1163 { 1164 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1165 BR_BCAST_FLOOD)) 1166 return -EINVAL; 1167 1168 return 0; 1169 } 1170 1171 static int 1172 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1173 struct switchdev_brport_flags flags, 1174 struct netlink_ext_ack *extack) 1175 { 1176 struct mt7530_priv *priv = ds->priv; 1177 1178 if (flags.mask & BR_LEARNING) 1179 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1180 flags.val & BR_LEARNING ? 0 : SA_DIS); 1181 1182 if (flags.mask & BR_FLOOD) 1183 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1184 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1185 1186 if (flags.mask & BR_MCAST_FLOOD) 1187 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1188 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1189 1190 if (flags.mask & BR_BCAST_FLOOD) 1191 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1192 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1193 1194 return 0; 1195 } 1196 1197 static int 1198 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1199 struct dsa_bridge bridge, bool *tx_fwd_offload, 1200 struct netlink_ext_ack *extack) 1201 { 1202 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1203 struct dsa_port *cpu_dp = dp->cpu_dp; 1204 u32 port_bitmap = BIT(cpu_dp->index); 1205 struct mt7530_priv *priv = ds->priv; 1206 1207 mutex_lock(&priv->reg_mutex); 1208 1209 dsa_switch_for_each_user_port(other_dp, ds) { 1210 int other_port = other_dp->index; 1211 1212 if (dp == other_dp) 1213 continue; 1214 1215 /* Add this port to the port matrix of the other ports in the 1216 * same bridge. If the port is disabled, port matrix is kept 1217 * and not being setup until the port becomes enabled. 1218 */ 1219 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1220 continue; 1221 1222 if (priv->ports[other_port].enable) 1223 mt7530_set(priv, MT7530_PCR_P(other_port), 1224 PCR_MATRIX(BIT(port))); 1225 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); 1226 1227 port_bitmap |= BIT(other_port); 1228 } 1229 1230 /* Add the all other ports to this port matrix. */ 1231 if (priv->ports[port].enable) 1232 mt7530_rmw(priv, MT7530_PCR_P(port), 1233 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1234 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1235 1236 /* Set to fallback mode for independent VLAN learning */ 1237 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1238 MT7530_PORT_FALLBACK_MODE); 1239 1240 mutex_unlock(&priv->reg_mutex); 1241 1242 return 0; 1243 } 1244 1245 static void 1246 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1247 { 1248 struct mt7530_priv *priv = ds->priv; 1249 bool all_user_ports_removed = true; 1250 int i; 1251 1252 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1253 * bridge. Don't set standalone ports to fallback mode. 1254 */ 1255 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1256 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1257 MT7530_PORT_FALLBACK_MODE); 1258 1259 mt7530_rmw(priv, MT7530_PVC_P(port), 1260 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1261 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1262 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1263 MT7530_VLAN_ACC_ALL); 1264 1265 /* Set PVID to 0 */ 1266 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1267 G0_PORT_VID_DEF); 1268 1269 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1270 if (dsa_is_user_port(ds, i) && 1271 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1272 all_user_ports_removed = false; 1273 break; 1274 } 1275 } 1276 1277 /* CPU port also does the same thing until all user ports belonging to 1278 * the CPU port get out of VLAN filtering mode. 1279 */ 1280 if (all_user_ports_removed) { 1281 struct dsa_port *dp = dsa_to_port(ds, port); 1282 struct dsa_port *cpu_dp = dp->cpu_dp; 1283 1284 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1285 PCR_MATRIX(dsa_user_ports(priv->ds))); 1286 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1287 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1288 } 1289 } 1290 1291 static void 1292 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1293 { 1294 struct mt7530_priv *priv = ds->priv; 1295 1296 /* Trapped into security mode allows packet forwarding through VLAN 1297 * table lookup. 1298 */ 1299 if (dsa_is_user_port(ds, port)) { 1300 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1301 MT7530_PORT_SECURITY_MODE); 1302 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1303 G0_PORT_VID(priv->ports[port].pvid)); 1304 1305 /* Only accept tagged frames if PVID is not set */ 1306 if (!priv->ports[port].pvid) 1307 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1308 MT7530_VLAN_ACC_TAGGED); 1309 1310 /* Set the port as a user port which is to be able to recognize 1311 * VID from incoming packets before fetching entry within the 1312 * VLAN table. 1313 */ 1314 mt7530_rmw(priv, MT7530_PVC_P(port), 1315 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1316 VLAN_ATTR(MT7530_VLAN_USER) | 1317 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1318 } else { 1319 /* Also set CPU ports to the "user" VLAN port attribute, to 1320 * allow VLAN classification, but keep the EG_TAG attribute as 1321 * "consistent" (i.o.w. don't change its value) for packets 1322 * received by the switch from the CPU, so that tagged packets 1323 * are forwarded to user ports as tagged, and untagged as 1324 * untagged. 1325 */ 1326 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1327 VLAN_ATTR(MT7530_VLAN_USER)); 1328 } 1329 } 1330 1331 static void 1332 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1333 struct dsa_bridge bridge) 1334 { 1335 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1336 struct dsa_port *cpu_dp = dp->cpu_dp; 1337 struct mt7530_priv *priv = ds->priv; 1338 1339 mutex_lock(&priv->reg_mutex); 1340 1341 dsa_switch_for_each_user_port(other_dp, ds) { 1342 int other_port = other_dp->index; 1343 1344 if (dp == other_dp) 1345 continue; 1346 1347 /* Remove this port from the port matrix of the other ports 1348 * in the same bridge. If the port is disabled, port matrix 1349 * is kept and not being setup until the port becomes enabled. 1350 */ 1351 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1352 continue; 1353 1354 if (priv->ports[other_port].enable) 1355 mt7530_clear(priv, MT7530_PCR_P(other_port), 1356 PCR_MATRIX(BIT(port))); 1357 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); 1358 } 1359 1360 /* Set the cpu port to be the only one in the port matrix of 1361 * this port. 1362 */ 1363 if (priv->ports[port].enable) 1364 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1365 PCR_MATRIX(BIT(cpu_dp->index))); 1366 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); 1367 1368 /* When a port is removed from the bridge, the port would be set up 1369 * back to the default as is at initial boot which is a VLAN-unaware 1370 * port. 1371 */ 1372 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1373 MT7530_PORT_MATRIX_MODE); 1374 1375 mutex_unlock(&priv->reg_mutex); 1376 } 1377 1378 static int 1379 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1380 const unsigned char *addr, u16 vid, 1381 struct dsa_db db) 1382 { 1383 struct mt7530_priv *priv = ds->priv; 1384 int ret; 1385 u8 port_mask = BIT(port); 1386 1387 mutex_lock(&priv->reg_mutex); 1388 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1389 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1390 mutex_unlock(&priv->reg_mutex); 1391 1392 return ret; 1393 } 1394 1395 static int 1396 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1397 const unsigned char *addr, u16 vid, 1398 struct dsa_db db) 1399 { 1400 struct mt7530_priv *priv = ds->priv; 1401 int ret; 1402 u8 port_mask = BIT(port); 1403 1404 mutex_lock(&priv->reg_mutex); 1405 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1406 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1407 mutex_unlock(&priv->reg_mutex); 1408 1409 return ret; 1410 } 1411 1412 static int 1413 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1414 dsa_fdb_dump_cb_t *cb, void *data) 1415 { 1416 struct mt7530_priv *priv = ds->priv; 1417 struct mt7530_fdb _fdb = { 0 }; 1418 int cnt = MT7530_NUM_FDB_RECORDS; 1419 int ret = 0; 1420 u32 rsp = 0; 1421 1422 mutex_lock(&priv->reg_mutex); 1423 1424 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1425 if (ret < 0) 1426 goto err; 1427 1428 do { 1429 if (rsp & ATC_SRCH_HIT) { 1430 mt7530_fdb_read(priv, &_fdb); 1431 if (_fdb.port_mask & BIT(port)) { 1432 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1433 data); 1434 if (ret < 0) 1435 break; 1436 } 1437 } 1438 } while (--cnt && 1439 !(rsp & ATC_SRCH_END) && 1440 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1441 err: 1442 mutex_unlock(&priv->reg_mutex); 1443 1444 return 0; 1445 } 1446 1447 static int 1448 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1449 const struct switchdev_obj_port_mdb *mdb, 1450 struct dsa_db db) 1451 { 1452 struct mt7530_priv *priv = ds->priv; 1453 const u8 *addr = mdb->addr; 1454 u16 vid = mdb->vid; 1455 u8 port_mask = 0; 1456 int ret; 1457 1458 mutex_lock(&priv->reg_mutex); 1459 1460 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1461 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1462 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1463 & PORT_MAP_MASK; 1464 1465 port_mask |= BIT(port); 1466 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1467 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1468 1469 mutex_unlock(&priv->reg_mutex); 1470 1471 return ret; 1472 } 1473 1474 static int 1475 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1476 const struct switchdev_obj_port_mdb *mdb, 1477 struct dsa_db db) 1478 { 1479 struct mt7530_priv *priv = ds->priv; 1480 const u8 *addr = mdb->addr; 1481 u16 vid = mdb->vid; 1482 u8 port_mask = 0; 1483 int ret; 1484 1485 mutex_lock(&priv->reg_mutex); 1486 1487 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1488 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1489 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1490 & PORT_MAP_MASK; 1491 1492 port_mask &= ~BIT(port); 1493 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1494 port_mask ? STATIC_ENT : STATIC_EMP); 1495 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1496 1497 mutex_unlock(&priv->reg_mutex); 1498 1499 return ret; 1500 } 1501 1502 static int 1503 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1504 { 1505 struct mt7530_dummy_poll p; 1506 u32 val; 1507 int ret; 1508 1509 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1510 mt7530_write(priv, MT7530_VTCR, val); 1511 1512 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1513 ret = readx_poll_timeout(_mt7530_read, &p, val, 1514 !(val & VTCR_BUSY), 20, 20000); 1515 if (ret < 0) { 1516 dev_err(priv->dev, "poll timeout\n"); 1517 return ret; 1518 } 1519 1520 val = mt7530_read(priv, MT7530_VTCR); 1521 if (val & VTCR_INVALID) { 1522 dev_err(priv->dev, "read VTCR invalid\n"); 1523 return -EINVAL; 1524 } 1525 1526 return 0; 1527 } 1528 1529 static int 1530 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1531 struct netlink_ext_ack *extack) 1532 { 1533 struct dsa_port *dp = dsa_to_port(ds, port); 1534 struct dsa_port *cpu_dp = dp->cpu_dp; 1535 1536 if (vlan_filtering) { 1537 /* The port is being kept as VLAN-unaware port when bridge is 1538 * set up with vlan_filtering not being set, Otherwise, the 1539 * port and the corresponding CPU port is required the setup 1540 * for becoming a VLAN-aware port. 1541 */ 1542 mt7530_port_set_vlan_aware(ds, port); 1543 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1544 } else { 1545 mt7530_port_set_vlan_unaware(ds, port); 1546 } 1547 1548 return 0; 1549 } 1550 1551 static void 1552 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1553 struct mt7530_hw_vlan_entry *entry) 1554 { 1555 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1556 u8 new_members; 1557 u32 val; 1558 1559 new_members = entry->old_members | BIT(entry->port); 1560 1561 /* Validate the entry with independent learning, create egress tag per 1562 * VLAN and joining the port as one of the port members. 1563 */ 1564 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1565 VLAN_VALID; 1566 mt7530_write(priv, MT7530_VAWD1, val); 1567 1568 /* Decide whether adding tag or not for those outgoing packets from the 1569 * port inside the VLAN. 1570 * CPU port is always taken as a tagged port for serving more than one 1571 * VLANs across and also being applied with egress type stack mode for 1572 * that VLAN tags would be appended after hardware special tag used as 1573 * DSA tag. 1574 */ 1575 if (dsa_port_is_cpu(dp)) 1576 val = MT7530_VLAN_EGRESS_STACK; 1577 else if (entry->untagged) 1578 val = MT7530_VLAN_EGRESS_UNTAG; 1579 else 1580 val = MT7530_VLAN_EGRESS_TAG; 1581 mt7530_rmw(priv, MT7530_VAWD2, 1582 ETAG_CTRL_P_MASK(entry->port), 1583 ETAG_CTRL_P(entry->port, val)); 1584 } 1585 1586 static void 1587 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1588 struct mt7530_hw_vlan_entry *entry) 1589 { 1590 u8 new_members; 1591 u32 val; 1592 1593 new_members = entry->old_members & ~BIT(entry->port); 1594 1595 val = mt7530_read(priv, MT7530_VAWD1); 1596 if (!(val & VLAN_VALID)) { 1597 dev_err(priv->dev, 1598 "Cannot be deleted due to invalid entry\n"); 1599 return; 1600 } 1601 1602 if (new_members) { 1603 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1604 VLAN_VALID; 1605 mt7530_write(priv, MT7530_VAWD1, val); 1606 } else { 1607 mt7530_write(priv, MT7530_VAWD1, 0); 1608 mt7530_write(priv, MT7530_VAWD2, 0); 1609 } 1610 } 1611 1612 static void 1613 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1614 struct mt7530_hw_vlan_entry *entry, 1615 mt7530_vlan_op vlan_op) 1616 { 1617 u32 val; 1618 1619 /* Fetch entry */ 1620 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1621 1622 val = mt7530_read(priv, MT7530_VAWD1); 1623 1624 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1625 1626 /* Manipulate entry */ 1627 vlan_op(priv, entry); 1628 1629 /* Flush result to hardware */ 1630 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1631 } 1632 1633 static int 1634 mt7530_setup_vlan0(struct mt7530_priv *priv) 1635 { 1636 u32 val; 1637 1638 /* Validate the entry with independent learning, keep the original 1639 * ingress tag attribute. 1640 */ 1641 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1642 VLAN_VALID; 1643 mt7530_write(priv, MT7530_VAWD1, val); 1644 1645 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1646 } 1647 1648 static int 1649 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1650 const struct switchdev_obj_port_vlan *vlan, 1651 struct netlink_ext_ack *extack) 1652 { 1653 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1654 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1655 struct mt7530_hw_vlan_entry new_entry; 1656 struct mt7530_priv *priv = ds->priv; 1657 1658 mutex_lock(&priv->reg_mutex); 1659 1660 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1661 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1662 1663 if (pvid) { 1664 priv->ports[port].pvid = vlan->vid; 1665 1666 /* Accept all frames if PVID is set */ 1667 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1668 MT7530_VLAN_ACC_ALL); 1669 1670 /* Only configure PVID if VLAN filtering is enabled */ 1671 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1672 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1673 G0_PORT_VID_MASK, 1674 G0_PORT_VID(vlan->vid)); 1675 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1676 /* This VLAN is overwritten without PVID, so unset it */ 1677 priv->ports[port].pvid = G0_PORT_VID_DEF; 1678 1679 /* Only accept tagged frames if the port is VLAN-aware */ 1680 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1681 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1682 MT7530_VLAN_ACC_TAGGED); 1683 1684 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1685 G0_PORT_VID_DEF); 1686 } 1687 1688 mutex_unlock(&priv->reg_mutex); 1689 1690 return 0; 1691 } 1692 1693 static int 1694 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1695 const struct switchdev_obj_port_vlan *vlan) 1696 { 1697 struct mt7530_hw_vlan_entry target_entry; 1698 struct mt7530_priv *priv = ds->priv; 1699 1700 mutex_lock(&priv->reg_mutex); 1701 1702 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1703 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1704 mt7530_hw_vlan_del); 1705 1706 /* PVID is being restored to the default whenever the PVID port 1707 * is being removed from the VLAN. 1708 */ 1709 if (priv->ports[port].pvid == vlan->vid) { 1710 priv->ports[port].pvid = G0_PORT_VID_DEF; 1711 1712 /* Only accept tagged frames if the port is VLAN-aware */ 1713 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1714 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1715 MT7530_VLAN_ACC_TAGGED); 1716 1717 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1718 G0_PORT_VID_DEF); 1719 } 1720 1721 1722 mutex_unlock(&priv->reg_mutex); 1723 1724 return 0; 1725 } 1726 1727 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1728 { 1729 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1730 MIRROR_PORT(val); 1731 } 1732 1733 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1734 { 1735 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1736 MIRROR_PORT(val); 1737 } 1738 1739 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1740 struct dsa_mall_mirror_tc_entry *mirror, 1741 bool ingress, struct netlink_ext_ack *extack) 1742 { 1743 struct mt7530_priv *priv = ds->priv; 1744 int monitor_port; 1745 u32 val; 1746 1747 /* Check for existent entry */ 1748 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1749 return -EEXIST; 1750 1751 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1752 1753 /* MT7530 only supports one monitor port */ 1754 monitor_port = mt753x_mirror_port_get(priv->id, val); 1755 if (val & MT753X_MIRROR_EN(priv->id) && 1756 monitor_port != mirror->to_local_port) 1757 return -EEXIST; 1758 1759 val |= MT753X_MIRROR_EN(priv->id); 1760 val &= ~MT753X_MIRROR_MASK(priv->id); 1761 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1762 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1763 1764 val = mt7530_read(priv, MT7530_PCR_P(port)); 1765 if (ingress) { 1766 val |= PORT_RX_MIR; 1767 priv->mirror_rx |= BIT(port); 1768 } else { 1769 val |= PORT_TX_MIR; 1770 priv->mirror_tx |= BIT(port); 1771 } 1772 mt7530_write(priv, MT7530_PCR_P(port), val); 1773 1774 return 0; 1775 } 1776 1777 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1778 struct dsa_mall_mirror_tc_entry *mirror) 1779 { 1780 struct mt7530_priv *priv = ds->priv; 1781 u32 val; 1782 1783 val = mt7530_read(priv, MT7530_PCR_P(port)); 1784 if (mirror->ingress) { 1785 val &= ~PORT_RX_MIR; 1786 priv->mirror_rx &= ~BIT(port); 1787 } else { 1788 val &= ~PORT_TX_MIR; 1789 priv->mirror_tx &= ~BIT(port); 1790 } 1791 mt7530_write(priv, MT7530_PCR_P(port), val); 1792 1793 if (!priv->mirror_rx && !priv->mirror_tx) { 1794 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1795 val &= ~MT753X_MIRROR_EN(priv->id); 1796 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1797 } 1798 } 1799 1800 static enum dsa_tag_protocol 1801 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1802 enum dsa_tag_protocol mp) 1803 { 1804 return DSA_TAG_PROTO_MTK; 1805 } 1806 1807 #ifdef CONFIG_GPIOLIB 1808 static inline u32 1809 mt7530_gpio_to_bit(unsigned int offset) 1810 { 1811 /* Map GPIO offset to register bit 1812 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1813 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1814 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1815 * [14:12] port 3 LED 0..2 as GPIO 9..11 1816 * [18:16] port 4 LED 0..2 as GPIO 12..14 1817 */ 1818 return BIT(offset + offset / 3); 1819 } 1820 1821 static int 1822 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1823 { 1824 struct mt7530_priv *priv = gpiochip_get_data(gc); 1825 u32 bit = mt7530_gpio_to_bit(offset); 1826 1827 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1828 } 1829 1830 static void 1831 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1832 { 1833 struct mt7530_priv *priv = gpiochip_get_data(gc); 1834 u32 bit = mt7530_gpio_to_bit(offset); 1835 1836 if (value) 1837 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1838 else 1839 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1840 } 1841 1842 static int 1843 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1844 { 1845 struct mt7530_priv *priv = gpiochip_get_data(gc); 1846 u32 bit = mt7530_gpio_to_bit(offset); 1847 1848 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1849 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1850 } 1851 1852 static int 1853 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1854 { 1855 struct mt7530_priv *priv = gpiochip_get_data(gc); 1856 u32 bit = mt7530_gpio_to_bit(offset); 1857 1858 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1859 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1860 1861 return 0; 1862 } 1863 1864 static int 1865 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1866 { 1867 struct mt7530_priv *priv = gpiochip_get_data(gc); 1868 u32 bit = mt7530_gpio_to_bit(offset); 1869 1870 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1871 1872 if (value) 1873 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1874 else 1875 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1876 1877 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1878 1879 return 0; 1880 } 1881 1882 static int 1883 mt7530_setup_gpio(struct mt7530_priv *priv) 1884 { 1885 struct device *dev = priv->dev; 1886 struct gpio_chip *gc; 1887 1888 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1889 if (!gc) 1890 return -ENOMEM; 1891 1892 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1893 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1894 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1895 1896 gc->label = "mt7530"; 1897 gc->parent = dev; 1898 gc->owner = THIS_MODULE; 1899 gc->get_direction = mt7530_gpio_get_direction; 1900 gc->direction_input = mt7530_gpio_direction_input; 1901 gc->direction_output = mt7530_gpio_direction_output; 1902 gc->get = mt7530_gpio_get; 1903 gc->set = mt7530_gpio_set; 1904 gc->base = -1; 1905 gc->ngpio = 15; 1906 gc->can_sleep = true; 1907 1908 return devm_gpiochip_add_data(dev, gc, priv); 1909 } 1910 #endif /* CONFIG_GPIOLIB */ 1911 1912 static irqreturn_t 1913 mt7530_irq_thread_fn(int irq, void *dev_id) 1914 { 1915 struct mt7530_priv *priv = dev_id; 1916 bool handled = false; 1917 u32 val; 1918 int p; 1919 1920 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1921 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1922 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1923 mutex_unlock(&priv->bus->mdio_lock); 1924 1925 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1926 if (BIT(p) & val) { 1927 unsigned int irq; 1928 1929 irq = irq_find_mapping(priv->irq_domain, p); 1930 handle_nested_irq(irq); 1931 handled = true; 1932 } 1933 } 1934 1935 return IRQ_RETVAL(handled); 1936 } 1937 1938 static void 1939 mt7530_irq_mask(struct irq_data *d) 1940 { 1941 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1942 1943 priv->irq_enable &= ~BIT(d->hwirq); 1944 } 1945 1946 static void 1947 mt7530_irq_unmask(struct irq_data *d) 1948 { 1949 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1950 1951 priv->irq_enable |= BIT(d->hwirq); 1952 } 1953 1954 static void 1955 mt7530_irq_bus_lock(struct irq_data *d) 1956 { 1957 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1958 1959 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1960 } 1961 1962 static void 1963 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1964 { 1965 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1966 1967 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1968 mutex_unlock(&priv->bus->mdio_lock); 1969 } 1970 1971 static struct irq_chip mt7530_irq_chip = { 1972 .name = KBUILD_MODNAME, 1973 .irq_mask = mt7530_irq_mask, 1974 .irq_unmask = mt7530_irq_unmask, 1975 .irq_bus_lock = mt7530_irq_bus_lock, 1976 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 1977 }; 1978 1979 static int 1980 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 1981 irq_hw_number_t hwirq) 1982 { 1983 irq_set_chip_data(irq, domain->host_data); 1984 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 1985 irq_set_nested_thread(irq, true); 1986 irq_set_noprobe(irq); 1987 1988 return 0; 1989 } 1990 1991 static const struct irq_domain_ops mt7530_irq_domain_ops = { 1992 .map = mt7530_irq_map, 1993 .xlate = irq_domain_xlate_onecell, 1994 }; 1995 1996 static void 1997 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 1998 { 1999 struct dsa_switch *ds = priv->ds; 2000 int p; 2001 2002 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2003 if (BIT(p) & ds->phys_mii_mask) { 2004 unsigned int irq; 2005 2006 irq = irq_create_mapping(priv->irq_domain, p); 2007 ds->slave_mii_bus->irq[p] = irq; 2008 } 2009 } 2010 } 2011 2012 static int 2013 mt7530_setup_irq(struct mt7530_priv *priv) 2014 { 2015 struct device *dev = priv->dev; 2016 struct device_node *np = dev->of_node; 2017 int ret; 2018 2019 if (!of_property_read_bool(np, "interrupt-controller")) { 2020 dev_info(dev, "no interrupt support\n"); 2021 return 0; 2022 } 2023 2024 priv->irq = of_irq_get(np, 0); 2025 if (priv->irq <= 0) { 2026 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 2027 return priv->irq ? : -EINVAL; 2028 } 2029 2030 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2031 &mt7530_irq_domain_ops, priv); 2032 if (!priv->irq_domain) { 2033 dev_err(dev, "failed to create IRQ domain\n"); 2034 return -ENOMEM; 2035 } 2036 2037 /* This register must be set for MT7530 to properly fire interrupts */ 2038 if (priv->id != ID_MT7531) 2039 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2040 2041 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2042 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2043 if (ret) { 2044 irq_domain_remove(priv->irq_domain); 2045 dev_err(dev, "failed to request IRQ: %d\n", ret); 2046 return ret; 2047 } 2048 2049 return 0; 2050 } 2051 2052 static void 2053 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2054 { 2055 int p; 2056 2057 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2058 if (BIT(p) & priv->ds->phys_mii_mask) { 2059 unsigned int irq; 2060 2061 irq = irq_find_mapping(priv->irq_domain, p); 2062 irq_dispose_mapping(irq); 2063 } 2064 } 2065 } 2066 2067 static void 2068 mt7530_free_irq_common(struct mt7530_priv *priv) 2069 { 2070 free_irq(priv->irq, priv); 2071 irq_domain_remove(priv->irq_domain); 2072 } 2073 2074 static void 2075 mt7530_free_irq(struct mt7530_priv *priv) 2076 { 2077 mt7530_free_mdio_irq(priv); 2078 mt7530_free_irq_common(priv); 2079 } 2080 2081 static int 2082 mt7530_setup_mdio(struct mt7530_priv *priv) 2083 { 2084 struct dsa_switch *ds = priv->ds; 2085 struct device *dev = priv->dev; 2086 struct mii_bus *bus; 2087 static int idx; 2088 int ret; 2089 2090 bus = devm_mdiobus_alloc(dev); 2091 if (!bus) 2092 return -ENOMEM; 2093 2094 ds->slave_mii_bus = bus; 2095 bus->priv = priv; 2096 bus->name = KBUILD_MODNAME "-mii"; 2097 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2098 bus->read = mt753x_phy_read_c22; 2099 bus->write = mt753x_phy_write_c22; 2100 bus->read_c45 = mt753x_phy_read_c45; 2101 bus->write_c45 = mt753x_phy_write_c45; 2102 bus->parent = dev; 2103 bus->phy_mask = ~ds->phys_mii_mask; 2104 2105 if (priv->irq) 2106 mt7530_setup_mdio_irq(priv); 2107 2108 ret = devm_mdiobus_register(dev, bus); 2109 if (ret) { 2110 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2111 if (priv->irq) 2112 mt7530_free_mdio_irq(priv); 2113 } 2114 2115 return ret; 2116 } 2117 2118 static int 2119 mt7530_setup(struct dsa_switch *ds) 2120 { 2121 struct mt7530_priv *priv = ds->priv; 2122 struct device_node *dn = NULL; 2123 struct device_node *phy_node; 2124 struct device_node *mac_np; 2125 struct mt7530_dummy_poll p; 2126 phy_interface_t interface; 2127 struct dsa_port *cpu_dp; 2128 u32 id, val; 2129 int ret, i; 2130 2131 /* The parent node of master netdev which holds the common system 2132 * controller also is the container for two GMACs nodes representing 2133 * as two netdev instances. 2134 */ 2135 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2136 dn = cpu_dp->master->dev.of_node->parent; 2137 /* It doesn't matter which CPU port is found first, 2138 * their masters should share the same parent OF node 2139 */ 2140 break; 2141 } 2142 2143 if (!dn) { 2144 dev_err(ds->dev, "parent OF node of DSA master not found"); 2145 return -EINVAL; 2146 } 2147 2148 ds->assisted_learning_on_cpu_port = true; 2149 ds->mtu_enforcement_ingress = true; 2150 2151 if (priv->id == ID_MT7530) { 2152 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2153 ret = regulator_enable(priv->core_pwr); 2154 if (ret < 0) { 2155 dev_err(priv->dev, 2156 "Failed to enable core power: %d\n", ret); 2157 return ret; 2158 } 2159 2160 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2161 ret = regulator_enable(priv->io_pwr); 2162 if (ret < 0) { 2163 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2164 ret); 2165 return ret; 2166 } 2167 } 2168 2169 /* Reset whole chip through gpio pin or memory-mapped registers for 2170 * different type of hardware 2171 */ 2172 if (priv->mcm) { 2173 reset_control_assert(priv->rstc); 2174 usleep_range(1000, 1100); 2175 reset_control_deassert(priv->rstc); 2176 } else { 2177 gpiod_set_value_cansleep(priv->reset, 0); 2178 usleep_range(1000, 1100); 2179 gpiod_set_value_cansleep(priv->reset, 1); 2180 } 2181 2182 /* Waiting for MT7530 got to stable */ 2183 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2184 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2185 20, 1000000); 2186 if (ret < 0) { 2187 dev_err(priv->dev, "reset timeout\n"); 2188 return ret; 2189 } 2190 2191 id = mt7530_read(priv, MT7530_CREV); 2192 id >>= CHIP_NAME_SHIFT; 2193 if (id != MT7530_ID) { 2194 dev_err(priv->dev, "chip %x can't be supported\n", id); 2195 return -ENODEV; 2196 } 2197 2198 /* Reset the switch through internal reset */ 2199 mt7530_write(priv, MT7530_SYS_CTRL, 2200 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2201 SYS_CTRL_REG_RST); 2202 2203 mt7530_pll_setup(priv); 2204 2205 /* Enable port 6 */ 2206 val = mt7530_read(priv, MT7530_MHWTRAP); 2207 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2208 val |= MHWTRAP_MANUAL; 2209 mt7530_write(priv, MT7530_MHWTRAP, val); 2210 2211 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2212 2213 /* Enable and reset MIB counters */ 2214 mt7530_mib_reset(ds); 2215 2216 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2217 /* Disable forwarding by default on all ports */ 2218 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2219 PCR_MATRIX_CLR); 2220 2221 /* Disable learning by default on all ports */ 2222 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2223 2224 if (dsa_is_cpu_port(ds, i)) { 2225 ret = mt753x_cpu_port_enable(ds, i); 2226 if (ret) 2227 return ret; 2228 } else { 2229 mt7530_port_disable(ds, i); 2230 2231 /* Set default PVID to 0 on all user ports */ 2232 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2233 G0_PORT_VID_DEF); 2234 } 2235 /* Enable consistent egress tag */ 2236 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2237 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2238 } 2239 2240 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2241 ret = mt7530_setup_vlan0(priv); 2242 if (ret) 2243 return ret; 2244 2245 /* Setup port 5 */ 2246 priv->p5_intf_sel = P5_DISABLED; 2247 interface = PHY_INTERFACE_MODE_NA; 2248 2249 if (!dsa_is_unused_port(ds, 5)) { 2250 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2251 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 2252 if (ret && ret != -ENODEV) 2253 return ret; 2254 } else { 2255 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 2256 for_each_child_of_node(dn, mac_np) { 2257 if (!of_device_is_compatible(mac_np, 2258 "mediatek,eth-mac")) 2259 continue; 2260 2261 ret = of_property_read_u32(mac_np, "reg", &id); 2262 if (ret < 0 || id != 1) 2263 continue; 2264 2265 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2266 if (!phy_node) 2267 continue; 2268 2269 if (phy_node->parent == priv->dev->of_node->parent) { 2270 ret = of_get_phy_mode(mac_np, &interface); 2271 if (ret && ret != -ENODEV) { 2272 of_node_put(mac_np); 2273 of_node_put(phy_node); 2274 return ret; 2275 } 2276 id = of_mdio_parse_addr(ds->dev, phy_node); 2277 if (id == 0) 2278 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2279 if (id == 4) 2280 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2281 } 2282 of_node_put(mac_np); 2283 of_node_put(phy_node); 2284 break; 2285 } 2286 } 2287 2288 #ifdef CONFIG_GPIOLIB 2289 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2290 ret = mt7530_setup_gpio(priv); 2291 if (ret) 2292 return ret; 2293 } 2294 #endif /* CONFIG_GPIOLIB */ 2295 2296 mt7530_setup_port5(ds, interface); 2297 2298 /* Flush the FDB table */ 2299 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2300 if (ret < 0) 2301 return ret; 2302 2303 return 0; 2304 } 2305 2306 static int 2307 mt7531_setup(struct dsa_switch *ds) 2308 { 2309 struct mt7530_priv *priv = ds->priv; 2310 struct mt7530_dummy_poll p; 2311 struct dsa_port *cpu_dp; 2312 u32 val, id; 2313 int ret, i; 2314 2315 /* Reset whole chip through gpio pin or memory-mapped registers for 2316 * different type of hardware 2317 */ 2318 if (priv->mcm) { 2319 reset_control_assert(priv->rstc); 2320 usleep_range(1000, 1100); 2321 reset_control_deassert(priv->rstc); 2322 } else { 2323 gpiod_set_value_cansleep(priv->reset, 0); 2324 usleep_range(1000, 1100); 2325 gpiod_set_value_cansleep(priv->reset, 1); 2326 } 2327 2328 /* Waiting for MT7530 got to stable */ 2329 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2330 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2331 20, 1000000); 2332 if (ret < 0) { 2333 dev_err(priv->dev, "reset timeout\n"); 2334 return ret; 2335 } 2336 2337 id = mt7530_read(priv, MT7531_CREV); 2338 id >>= CHIP_NAME_SHIFT; 2339 2340 if (id != MT7531_ID) { 2341 dev_err(priv->dev, "chip %x can't be supported\n", id); 2342 return -ENODEV; 2343 } 2344 2345 /* all MACs must be forced link-down before sw reset */ 2346 for (i = 0; i < MT7530_NUM_PORTS; i++) 2347 mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); 2348 2349 /* Reset the switch through internal reset */ 2350 mt7530_write(priv, MT7530_SYS_CTRL, 2351 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2352 SYS_CTRL_REG_RST); 2353 2354 mt7531_pll_setup(priv); 2355 2356 if (mt7531_dual_sgmii_supported(priv)) { 2357 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2358 2359 /* Let ds->slave_mii_bus be able to access external phy. */ 2360 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2361 MT7531_EXT_P_MDC_11); 2362 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2363 MT7531_EXT_P_MDIO_12); 2364 } else { 2365 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2366 } 2367 dev_dbg(ds->dev, "P5 support %s interface\n", 2368 p5_intf_modes(priv->p5_intf_sel)); 2369 2370 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2371 MT7531_GPIO0_INTERRUPT); 2372 2373 /* Let phylink decide the interface later. */ 2374 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2375 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2376 2377 /* Enable PHY core PLL, since phy_device has not yet been created 2378 * provided for phy_[read,write]_mmd_indirect is called, we provide 2379 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2380 * function. 2381 */ 2382 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2383 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2384 val |= MT7531_PHY_PLL_BYPASS_MODE; 2385 val &= ~MT7531_PHY_PLL_OFF; 2386 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2387 CORE_PLL_GROUP4, val); 2388 2389 /* BPDU to CPU port */ 2390 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2391 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, 2392 BIT(cpu_dp->index)); 2393 break; 2394 } 2395 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 2396 MT753X_BPDU_CPU_ONLY); 2397 2398 /* Enable and reset MIB counters */ 2399 mt7530_mib_reset(ds); 2400 2401 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2402 /* Disable forwarding by default on all ports */ 2403 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2404 PCR_MATRIX_CLR); 2405 2406 /* Disable learning by default on all ports */ 2407 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2408 2409 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2410 2411 if (dsa_is_cpu_port(ds, i)) { 2412 ret = mt753x_cpu_port_enable(ds, i); 2413 if (ret) 2414 return ret; 2415 } else { 2416 mt7530_port_disable(ds, i); 2417 2418 /* Set default PVID to 0 on all user ports */ 2419 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2420 G0_PORT_VID_DEF); 2421 } 2422 2423 /* Enable consistent egress tag */ 2424 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2425 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2426 } 2427 2428 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2429 ret = mt7530_setup_vlan0(priv); 2430 if (ret) 2431 return ret; 2432 2433 ds->assisted_learning_on_cpu_port = true; 2434 ds->mtu_enforcement_ingress = true; 2435 2436 /* Flush the FDB table */ 2437 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2438 if (ret < 0) 2439 return ret; 2440 2441 return 0; 2442 } 2443 2444 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2445 struct phylink_config *config) 2446 { 2447 switch (port) { 2448 case 0 ... 4: /* Internal phy */ 2449 __set_bit(PHY_INTERFACE_MODE_GMII, 2450 config->supported_interfaces); 2451 break; 2452 2453 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2454 phy_interface_set_rgmii(config->supported_interfaces); 2455 __set_bit(PHY_INTERFACE_MODE_MII, 2456 config->supported_interfaces); 2457 __set_bit(PHY_INTERFACE_MODE_GMII, 2458 config->supported_interfaces); 2459 break; 2460 2461 case 6: /* 1st cpu port */ 2462 __set_bit(PHY_INTERFACE_MODE_RGMII, 2463 config->supported_interfaces); 2464 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2465 config->supported_interfaces); 2466 break; 2467 } 2468 } 2469 2470 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2471 { 2472 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2473 } 2474 2475 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2476 struct phylink_config *config) 2477 { 2478 struct mt7530_priv *priv = ds->priv; 2479 2480 switch (port) { 2481 case 0 ... 4: /* Internal phy */ 2482 __set_bit(PHY_INTERFACE_MODE_GMII, 2483 config->supported_interfaces); 2484 break; 2485 2486 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2487 if (mt7531_is_rgmii_port(priv, port)) { 2488 phy_interface_set_rgmii(config->supported_interfaces); 2489 break; 2490 } 2491 fallthrough; 2492 2493 case 6: /* 1st cpu port supports sgmii/8023z only */ 2494 __set_bit(PHY_INTERFACE_MODE_SGMII, 2495 config->supported_interfaces); 2496 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2497 config->supported_interfaces); 2498 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2499 config->supported_interfaces); 2500 2501 config->mac_capabilities |= MAC_2500FD; 2502 break; 2503 } 2504 } 2505 2506 static int 2507 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2508 { 2509 struct mt7530_priv *priv = ds->priv; 2510 2511 return priv->info->pad_setup(ds, state->interface); 2512 } 2513 2514 static int 2515 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2516 phy_interface_t interface) 2517 { 2518 struct mt7530_priv *priv = ds->priv; 2519 2520 /* Only need to setup port5. */ 2521 if (port != 5) 2522 return 0; 2523 2524 mt7530_setup_port5(priv->ds, interface); 2525 2526 return 0; 2527 } 2528 2529 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2530 phy_interface_t interface, 2531 struct phy_device *phydev) 2532 { 2533 u32 val; 2534 2535 if (!mt7531_is_rgmii_port(priv, port)) { 2536 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2537 port); 2538 return -EINVAL; 2539 } 2540 2541 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2542 val |= GP_CLK_EN; 2543 val &= ~GP_MODE_MASK; 2544 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2545 val &= ~CLK_SKEW_IN_MASK; 2546 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2547 val &= ~CLK_SKEW_OUT_MASK; 2548 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2549 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2550 2551 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2552 if (!phydev || phy_driver_is_genphy(phydev)) { 2553 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2554 switch (interface) { 2555 case PHY_INTERFACE_MODE_RGMII: 2556 val |= TXCLK_NO_REVERSE; 2557 val |= RXCLK_NO_DELAY; 2558 break; 2559 case PHY_INTERFACE_MODE_RGMII_RXID: 2560 val |= TXCLK_NO_REVERSE; 2561 break; 2562 case PHY_INTERFACE_MODE_RGMII_TXID: 2563 val |= RXCLK_NO_DELAY; 2564 break; 2565 case PHY_INTERFACE_MODE_RGMII_ID: 2566 break; 2567 default: 2568 return -EINVAL; 2569 } 2570 } 2571 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2572 2573 return 0; 2574 } 2575 2576 static bool mt753x_is_mac_port(u32 port) 2577 { 2578 return (port == 5 || port == 6); 2579 } 2580 2581 static int 2582 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2583 phy_interface_t interface) 2584 { 2585 struct mt7530_priv *priv = ds->priv; 2586 struct phy_device *phydev; 2587 struct dsa_port *dp; 2588 2589 if (!mt753x_is_mac_port(port)) { 2590 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2591 return -EINVAL; 2592 } 2593 2594 switch (interface) { 2595 case PHY_INTERFACE_MODE_RGMII: 2596 case PHY_INTERFACE_MODE_RGMII_ID: 2597 case PHY_INTERFACE_MODE_RGMII_RXID: 2598 case PHY_INTERFACE_MODE_RGMII_TXID: 2599 dp = dsa_to_port(ds, port); 2600 phydev = dp->slave->phydev; 2601 return mt7531_rgmii_setup(priv, port, interface, phydev); 2602 case PHY_INTERFACE_MODE_SGMII: 2603 case PHY_INTERFACE_MODE_NA: 2604 case PHY_INTERFACE_MODE_1000BASEX: 2605 case PHY_INTERFACE_MODE_2500BASEX: 2606 /* handled in SGMII PCS driver */ 2607 return 0; 2608 default: 2609 return -EINVAL; 2610 } 2611 2612 return -EINVAL; 2613 } 2614 2615 static int 2616 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2617 const struct phylink_link_state *state) 2618 { 2619 struct mt7530_priv *priv = ds->priv; 2620 2621 return priv->info->mac_port_config(ds, port, mode, state->interface); 2622 } 2623 2624 static struct phylink_pcs * 2625 mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port, 2626 phy_interface_t interface) 2627 { 2628 struct mt7530_priv *priv = ds->priv; 2629 2630 switch (interface) { 2631 case PHY_INTERFACE_MODE_TRGMII: 2632 return &priv->pcs[port].pcs; 2633 case PHY_INTERFACE_MODE_SGMII: 2634 case PHY_INTERFACE_MODE_1000BASEX: 2635 case PHY_INTERFACE_MODE_2500BASEX: 2636 return priv->ports[port].sgmii_pcs; 2637 default: 2638 return NULL; 2639 } 2640 } 2641 2642 static void 2643 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2644 const struct phylink_link_state *state) 2645 { 2646 struct mt7530_priv *priv = ds->priv; 2647 u32 mcr_cur, mcr_new; 2648 2649 switch (port) { 2650 case 0 ... 4: /* Internal phy */ 2651 if (state->interface != PHY_INTERFACE_MODE_GMII) 2652 goto unsupported; 2653 break; 2654 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2655 if (priv->p5_interface == state->interface) 2656 break; 2657 2658 if (mt753x_mac_config(ds, port, mode, state) < 0) 2659 goto unsupported; 2660 2661 if (priv->p5_intf_sel != P5_DISABLED) 2662 priv->p5_interface = state->interface; 2663 break; 2664 case 6: /* 1st cpu port */ 2665 if (priv->p6_interface == state->interface) 2666 break; 2667 2668 mt753x_pad_setup(ds, state); 2669 2670 if (mt753x_mac_config(ds, port, mode, state) < 0) 2671 goto unsupported; 2672 2673 priv->p6_interface = state->interface; 2674 break; 2675 default: 2676 unsupported: 2677 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2678 __func__, phy_modes(state->interface), port); 2679 return; 2680 } 2681 2682 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2683 mcr_new = mcr_cur; 2684 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2685 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2686 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2687 2688 /* Are we connected to external phy */ 2689 if (port == 5 && dsa_is_user_port(ds, 5)) 2690 mcr_new |= PMCR_EXT_PHY; 2691 2692 if (mcr_new != mcr_cur) 2693 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2694 } 2695 2696 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2697 unsigned int mode, 2698 phy_interface_t interface) 2699 { 2700 struct mt7530_priv *priv = ds->priv; 2701 2702 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2703 } 2704 2705 static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs, 2706 unsigned int mode, 2707 phy_interface_t interface, 2708 int speed, int duplex) 2709 { 2710 if (pcs->ops->pcs_link_up) 2711 pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex); 2712 } 2713 2714 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2715 unsigned int mode, 2716 phy_interface_t interface, 2717 struct phy_device *phydev, 2718 int speed, int duplex, 2719 bool tx_pause, bool rx_pause) 2720 { 2721 struct mt7530_priv *priv = ds->priv; 2722 u32 mcr; 2723 2724 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2725 2726 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2727 * variants. 2728 */ 2729 if (interface == PHY_INTERFACE_MODE_TRGMII || 2730 (phy_interface_mode_is_8023z(interface))) { 2731 speed = SPEED_1000; 2732 duplex = DUPLEX_FULL; 2733 } 2734 2735 switch (speed) { 2736 case SPEED_1000: 2737 mcr |= PMCR_FORCE_SPEED_1000; 2738 break; 2739 case SPEED_100: 2740 mcr |= PMCR_FORCE_SPEED_100; 2741 break; 2742 } 2743 if (duplex == DUPLEX_FULL) { 2744 mcr |= PMCR_FORCE_FDX; 2745 if (tx_pause) 2746 mcr |= PMCR_TX_FC_EN; 2747 if (rx_pause) 2748 mcr |= PMCR_RX_FC_EN; 2749 } 2750 2751 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { 2752 switch (speed) { 2753 case SPEED_1000: 2754 mcr |= PMCR_FORCE_EEE1G; 2755 break; 2756 case SPEED_100: 2757 mcr |= PMCR_FORCE_EEE100; 2758 break; 2759 } 2760 } 2761 2762 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2763 } 2764 2765 static int 2766 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2767 { 2768 struct mt7530_priv *priv = ds->priv; 2769 phy_interface_t interface; 2770 int speed; 2771 int ret; 2772 2773 switch (port) { 2774 case 5: 2775 if (mt7531_is_rgmii_port(priv, port)) 2776 interface = PHY_INTERFACE_MODE_RGMII; 2777 else 2778 interface = PHY_INTERFACE_MODE_2500BASEX; 2779 2780 priv->p5_interface = interface; 2781 break; 2782 case 6: 2783 interface = PHY_INTERFACE_MODE_2500BASEX; 2784 2785 priv->p6_interface = interface; 2786 break; 2787 default: 2788 return -EINVAL; 2789 } 2790 2791 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2792 speed = SPEED_2500; 2793 else 2794 speed = SPEED_1000; 2795 2796 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2797 if (ret) 2798 return ret; 2799 mt7530_write(priv, MT7530_PMCR_P(port), 2800 PMCR_CPU_PORT_SETTING(priv->id)); 2801 mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED, 2802 interface, speed, DUPLEX_FULL); 2803 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2804 speed, DUPLEX_FULL, true, true); 2805 2806 return 0; 2807 } 2808 2809 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 2810 struct phylink_config *config) 2811 { 2812 struct mt7530_priv *priv = ds->priv; 2813 2814 /* This switch only supports full-duplex at 1Gbps */ 2815 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2816 MAC_10 | MAC_100 | MAC_1000FD; 2817 2818 /* This driver does not make use of the speed, duplex, pause or the 2819 * advertisement in its mac_config, so it is safe to mark this driver 2820 * as non-legacy. 2821 */ 2822 config->legacy_pre_march2020 = false; 2823 2824 priv->info->mac_port_get_caps(ds, port, config); 2825 } 2826 2827 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 2828 unsigned long *supported, 2829 const struct phylink_link_state *state) 2830 { 2831 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 2832 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 2833 phy_interface_mode_is_8023z(state->interface)) 2834 phylink_clear(supported, Autoneg); 2835 2836 return 0; 2837 } 2838 2839 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, 2840 struct phylink_link_state *state) 2841 { 2842 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2843 int port = pcs_to_mt753x_pcs(pcs)->port; 2844 u32 pmsr; 2845 2846 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2847 2848 state->link = (pmsr & PMSR_LINK); 2849 state->an_complete = state->link; 2850 state->duplex = !!(pmsr & PMSR_DPX); 2851 2852 switch (pmsr & PMSR_SPEED_MASK) { 2853 case PMSR_SPEED_10: 2854 state->speed = SPEED_10; 2855 break; 2856 case PMSR_SPEED_100: 2857 state->speed = SPEED_100; 2858 break; 2859 case PMSR_SPEED_1000: 2860 state->speed = SPEED_1000; 2861 break; 2862 default: 2863 state->speed = SPEED_UNKNOWN; 2864 break; 2865 } 2866 2867 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2868 if (pmsr & PMSR_RX_FC) 2869 state->pause |= MLO_PAUSE_RX; 2870 if (pmsr & PMSR_TX_FC) 2871 state->pause |= MLO_PAUSE_TX; 2872 } 2873 2874 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode, 2875 phy_interface_t interface, 2876 const unsigned long *advertising, 2877 bool permit_pause_to_mac) 2878 { 2879 return 0; 2880 } 2881 2882 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 2883 { 2884 } 2885 2886 static const struct phylink_pcs_ops mt7530_pcs_ops = { 2887 .pcs_validate = mt753x_pcs_validate, 2888 .pcs_get_state = mt7530_pcs_get_state, 2889 .pcs_config = mt753x_pcs_config, 2890 .pcs_an_restart = mt7530_pcs_an_restart, 2891 }; 2892 2893 static int mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val) 2894 { 2895 struct mt7530_priv *priv = context; 2896 2897 *val = mt7530_read(priv, reg); 2898 return 0; 2899 }; 2900 2901 static int mt7530_regmap_write(void *context, unsigned int reg, unsigned int val) 2902 { 2903 struct mt7530_priv *priv = context; 2904 2905 mt7530_write(priv, reg, val); 2906 return 0; 2907 }; 2908 2909 static int mt7530_regmap_update_bits(void *context, unsigned int reg, 2910 unsigned int mask, unsigned int val) 2911 { 2912 struct mt7530_priv *priv = context; 2913 2914 mt7530_rmw(priv, reg, mask, val); 2915 return 0; 2916 }; 2917 2918 static const struct regmap_bus mt7531_regmap_bus = { 2919 .reg_write = mt7530_regmap_write, 2920 .reg_read = mt7530_regmap_read, 2921 .reg_update_bits = mt7530_regmap_update_bits, 2922 }; 2923 2924 #define MT7531_PCS_REGMAP_CONFIG(_name, _reg_base) \ 2925 { \ 2926 .name = _name, \ 2927 .reg_bits = 16, \ 2928 .val_bits = 32, \ 2929 .reg_stride = 4, \ 2930 .reg_base = _reg_base, \ 2931 .max_register = 0x17c, \ 2932 } 2933 2934 static const struct regmap_config mt7531_pcs_config[] = { 2935 MT7531_PCS_REGMAP_CONFIG("port5", MT7531_SGMII_REG_BASE(5)), 2936 MT7531_PCS_REGMAP_CONFIG("port6", MT7531_SGMII_REG_BASE(6)), 2937 }; 2938 2939 static int 2940 mt753x_setup(struct dsa_switch *ds) 2941 { 2942 struct mt7530_priv *priv = ds->priv; 2943 struct regmap *regmap; 2944 int i, ret; 2945 2946 /* Initialise the PCS devices */ 2947 for (i = 0; i < priv->ds->num_ports; i++) { 2948 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 2949 priv->pcs[i].priv = priv; 2950 priv->pcs[i].port = i; 2951 } 2952 2953 ret = priv->info->sw_setup(ds); 2954 if (ret) 2955 return ret; 2956 2957 ret = mt7530_setup_irq(priv); 2958 if (ret) 2959 return ret; 2960 2961 ret = mt7530_setup_mdio(priv); 2962 if (ret && priv->irq) 2963 mt7530_free_irq_common(priv); 2964 2965 if (priv->id == ID_MT7531) 2966 for (i = 0; i < 2; i++) { 2967 regmap = devm_regmap_init(ds->dev, 2968 &mt7531_regmap_bus, priv, 2969 &mt7531_pcs_config[i]); 2970 priv->ports[5 + i].sgmii_pcs = 2971 mtk_pcs_lynxi_create(ds->dev, regmap, 2972 MT7531_PHYA_CTRL_SIGNAL3, 0); 2973 } 2974 2975 return ret; 2976 } 2977 2978 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 2979 struct ethtool_eee *e) 2980 { 2981 struct mt7530_priv *priv = ds->priv; 2982 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 2983 2984 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 2985 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 2986 2987 return 0; 2988 } 2989 2990 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 2991 struct ethtool_eee *e) 2992 { 2993 struct mt7530_priv *priv = ds->priv; 2994 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 2995 2996 if (e->tx_lpi_timer > 0xFFF) 2997 return -EINVAL; 2998 2999 set = SET_LPI_THRESH(e->tx_lpi_timer); 3000 if (!e->tx_lpi_enabled) 3001 /* Force LPI Mode without a delay */ 3002 set |= LPI_MODE_EN; 3003 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3004 3005 return 0; 3006 } 3007 3008 static const struct dsa_switch_ops mt7530_switch_ops = { 3009 .get_tag_protocol = mtk_get_tag_protocol, 3010 .setup = mt753x_setup, 3011 .get_strings = mt7530_get_strings, 3012 .get_ethtool_stats = mt7530_get_ethtool_stats, 3013 .get_sset_count = mt7530_get_sset_count, 3014 .set_ageing_time = mt7530_set_ageing_time, 3015 .port_enable = mt7530_port_enable, 3016 .port_disable = mt7530_port_disable, 3017 .port_change_mtu = mt7530_port_change_mtu, 3018 .port_max_mtu = mt7530_port_max_mtu, 3019 .port_stp_state_set = mt7530_stp_state_set, 3020 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3021 .port_bridge_flags = mt7530_port_bridge_flags, 3022 .port_bridge_join = mt7530_port_bridge_join, 3023 .port_bridge_leave = mt7530_port_bridge_leave, 3024 .port_fdb_add = mt7530_port_fdb_add, 3025 .port_fdb_del = mt7530_port_fdb_del, 3026 .port_fdb_dump = mt7530_port_fdb_dump, 3027 .port_mdb_add = mt7530_port_mdb_add, 3028 .port_mdb_del = mt7530_port_mdb_del, 3029 .port_vlan_filtering = mt7530_port_vlan_filtering, 3030 .port_vlan_add = mt7530_port_vlan_add, 3031 .port_vlan_del = mt7530_port_vlan_del, 3032 .port_mirror_add = mt753x_port_mirror_add, 3033 .port_mirror_del = mt753x_port_mirror_del, 3034 .phylink_get_caps = mt753x_phylink_get_caps, 3035 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs, 3036 .phylink_mac_config = mt753x_phylink_mac_config, 3037 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3038 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3039 .get_mac_eee = mt753x_get_mac_eee, 3040 .set_mac_eee = mt753x_set_mac_eee, 3041 }; 3042 3043 static const struct mt753x_info mt753x_table[] = { 3044 [ID_MT7621] = { 3045 .id = ID_MT7621, 3046 .pcs_ops = &mt7530_pcs_ops, 3047 .sw_setup = mt7530_setup, 3048 .phy_read_c22 = mt7530_phy_read_c22, 3049 .phy_write_c22 = mt7530_phy_write_c22, 3050 .phy_read_c45 = mt7530_phy_read_c45, 3051 .phy_write_c45 = mt7530_phy_write_c45, 3052 .pad_setup = mt7530_pad_clk_setup, 3053 .mac_port_get_caps = mt7530_mac_port_get_caps, 3054 .mac_port_config = mt7530_mac_config, 3055 }, 3056 [ID_MT7530] = { 3057 .id = ID_MT7530, 3058 .pcs_ops = &mt7530_pcs_ops, 3059 .sw_setup = mt7530_setup, 3060 .phy_read_c22 = mt7530_phy_read_c22, 3061 .phy_write_c22 = mt7530_phy_write_c22, 3062 .phy_read_c45 = mt7530_phy_read_c45, 3063 .phy_write_c45 = mt7530_phy_write_c45, 3064 .pad_setup = mt7530_pad_clk_setup, 3065 .mac_port_get_caps = mt7530_mac_port_get_caps, 3066 .mac_port_config = mt7530_mac_config, 3067 }, 3068 [ID_MT7531] = { 3069 .id = ID_MT7531, 3070 .pcs_ops = &mt7530_pcs_ops, 3071 .sw_setup = mt7531_setup, 3072 .phy_read_c22 = mt7531_ind_c22_phy_read, 3073 .phy_write_c22 = mt7531_ind_c22_phy_write, 3074 .phy_read_c45 = mt7531_ind_c45_phy_read, 3075 .phy_write_c45 = mt7531_ind_c45_phy_write, 3076 .pad_setup = mt7531_pad_setup, 3077 .cpu_port_config = mt7531_cpu_port_config, 3078 .mac_port_get_caps = mt7531_mac_port_get_caps, 3079 .mac_port_config = mt7531_mac_config, 3080 }, 3081 }; 3082 3083 static const struct of_device_id mt7530_of_match[] = { 3084 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], }, 3085 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], }, 3086 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], }, 3087 { /* sentinel */ }, 3088 }; 3089 MODULE_DEVICE_TABLE(of, mt7530_of_match); 3090 3091 static int 3092 mt7530_probe(struct mdio_device *mdiodev) 3093 { 3094 struct mt7530_priv *priv; 3095 struct device_node *dn; 3096 3097 dn = mdiodev->dev.of_node; 3098 3099 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 3100 if (!priv) 3101 return -ENOMEM; 3102 3103 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 3104 if (!priv->ds) 3105 return -ENOMEM; 3106 3107 priv->ds->dev = &mdiodev->dev; 3108 priv->ds->num_ports = MT7530_NUM_PORTS; 3109 3110 /* Use medatek,mcm property to distinguish hardware type that would 3111 * casues a little bit differences on power-on sequence. 3112 */ 3113 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 3114 if (priv->mcm) { 3115 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 3116 3117 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 3118 if (IS_ERR(priv->rstc)) { 3119 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3120 return PTR_ERR(priv->rstc); 3121 } 3122 } 3123 3124 /* Get the hardware identifier from the devicetree node. 3125 * We will need it for some of the clock and regulator setup. 3126 */ 3127 priv->info = of_device_get_match_data(&mdiodev->dev); 3128 if (!priv->info) 3129 return -EINVAL; 3130 3131 /* Sanity check if these required device operations are filled 3132 * properly. 3133 */ 3134 if (!priv->info->sw_setup || !priv->info->pad_setup || 3135 !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || 3136 !priv->info->mac_port_get_caps || 3137 !priv->info->mac_port_config) 3138 return -EINVAL; 3139 3140 priv->id = priv->info->id; 3141 3142 if (priv->id == ID_MT7530) { 3143 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 3144 if (IS_ERR(priv->core_pwr)) 3145 return PTR_ERR(priv->core_pwr); 3146 3147 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 3148 if (IS_ERR(priv->io_pwr)) 3149 return PTR_ERR(priv->io_pwr); 3150 } 3151 3152 /* Not MCM that indicates switch works as the remote standalone 3153 * integrated circuit so the GPIO pin would be used to complete 3154 * the reset, otherwise memory-mapped register accessing used 3155 * through syscon provides in the case of MCM. 3156 */ 3157 if (!priv->mcm) { 3158 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 3159 GPIOD_OUT_LOW); 3160 if (IS_ERR(priv->reset)) { 3161 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3162 return PTR_ERR(priv->reset); 3163 } 3164 } 3165 3166 priv->bus = mdiodev->bus; 3167 priv->dev = &mdiodev->dev; 3168 priv->ds->priv = priv; 3169 priv->ds->ops = &mt7530_switch_ops; 3170 mutex_init(&priv->reg_mutex); 3171 dev_set_drvdata(&mdiodev->dev, priv); 3172 3173 return dsa_register_switch(priv->ds); 3174 } 3175 3176 static void 3177 mt7530_remove(struct mdio_device *mdiodev) 3178 { 3179 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3180 int ret = 0, i; 3181 3182 if (!priv) 3183 return; 3184 3185 ret = regulator_disable(priv->core_pwr); 3186 if (ret < 0) 3187 dev_err(priv->dev, 3188 "Failed to disable core power: %d\n", ret); 3189 3190 ret = regulator_disable(priv->io_pwr); 3191 if (ret < 0) 3192 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 3193 ret); 3194 3195 if (priv->irq) 3196 mt7530_free_irq(priv); 3197 3198 dsa_unregister_switch(priv->ds); 3199 3200 for (i = 0; i < 2; ++i) 3201 mtk_pcs_lynxi_destroy(priv->ports[5 + i].sgmii_pcs); 3202 3203 mutex_destroy(&priv->reg_mutex); 3204 } 3205 3206 static void mt7530_shutdown(struct mdio_device *mdiodev) 3207 { 3208 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3209 3210 if (!priv) 3211 return; 3212 3213 dsa_switch_shutdown(priv->ds); 3214 3215 dev_set_drvdata(&mdiodev->dev, NULL); 3216 } 3217 3218 static struct mdio_driver mt7530_mdio_driver = { 3219 .probe = mt7530_probe, 3220 .remove = mt7530_remove, 3221 .shutdown = mt7530_shutdown, 3222 .mdiodrv.driver = { 3223 .name = "mt7530", 3224 .of_match_table = mt7530_of_match, 3225 }, 3226 }; 3227 3228 mdio_module_driver(mt7530_mdio_driver); 3229 3230 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3231 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3232 MODULE_LICENSE("GPL"); 3233