1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 #include <net/pkt_cls.h> 25 26 #include "mt7530.h" 27 28 #define MT7530_STATS_POLL_INTERVAL (1 * HZ) 29 #define MT7530_STATS_RATE_LIMIT (HZ / 10) 30 31 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 32 { 33 return container_of(pcs, struct mt753x_pcs, pcs); 34 } 35 36 /* String, offset, and register size in bytes if different from 4 bytes */ 37 static const struct mt7530_mib_desc mt7530_mib[] = { 38 MIB_DESC(1, MT7530_PORT_MIB_TX_DROP, "TxDrop"), 39 MIB_DESC(1, MT7530_PORT_MIB_TX_CRC_ERR, "TxCrcErr"), 40 MIB_DESC(1, MT7530_PORT_MIB_TX_COLLISION, "TxCollision"), 41 MIB_DESC(1, MT7530_PORT_MIB_RX_DROP, "RxDrop"), 42 MIB_DESC(1, MT7530_PORT_MIB_RX_FILTERING, "RxFiltering"), 43 MIB_DESC(1, MT7530_PORT_MIB_RX_CRC_ERR, "RxCrcErr"), 44 MIB_DESC(1, MT7530_PORT_MIB_RX_CTRL_DROP, "RxCtrlDrop"), 45 MIB_DESC(1, MT7530_PORT_MIB_RX_INGRESS_DROP, "RxIngressDrop"), 46 MIB_DESC(1, MT7530_PORT_MIB_RX_ARL_DROP, "RxArlDrop"), 47 }; 48 49 static void 50 mt7530_mutex_lock(struct mt7530_priv *priv) 51 { 52 if (priv->bus) 53 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 54 } 55 56 static void 57 mt7530_mutex_unlock(struct mt7530_priv *priv) 58 { 59 if (priv->bus) 60 mutex_unlock(&priv->bus->mdio_lock); 61 } 62 63 static void 64 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 65 { 66 struct mii_bus *bus = priv->bus; 67 int ret; 68 69 mt7530_mutex_lock(priv); 70 71 /* Write the desired MMD Devad */ 72 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 73 MII_MMD_CTRL, MDIO_MMD_VEND2); 74 if (ret < 0) 75 goto err; 76 77 /* Write the desired MMD register address */ 78 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 79 MII_MMD_DATA, reg); 80 if (ret < 0) 81 goto err; 82 83 /* Select the Function : DATA with no post increment */ 84 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 85 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); 86 if (ret < 0) 87 goto err; 88 89 /* Write the data into MMD's selected register */ 90 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 91 MII_MMD_DATA, val); 92 err: 93 if (ret < 0) 94 dev_err(&bus->dev, "failed to write mmd register\n"); 95 96 mt7530_mutex_unlock(priv); 97 } 98 99 static void 100 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 101 { 102 struct mii_bus *bus = priv->bus; 103 u32 val; 104 int ret; 105 106 mt7530_mutex_lock(priv); 107 108 /* Write the desired MMD Devad */ 109 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 110 MII_MMD_CTRL, MDIO_MMD_VEND2); 111 if (ret < 0) 112 goto err; 113 114 /* Write the desired MMD register address */ 115 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 116 MII_MMD_DATA, reg); 117 if (ret < 0) 118 goto err; 119 120 /* Select the Function : DATA with no post increment */ 121 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 122 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); 123 if (ret < 0) 124 goto err; 125 126 /* Read the content of the MMD's selected register */ 127 val = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 128 MII_MMD_DATA); 129 val &= ~mask; 130 val |= set; 131 /* Write the data into MMD's selected register */ 132 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 133 MII_MMD_DATA, val); 134 err: 135 if (ret < 0) 136 dev_err(&bus->dev, "failed to write mmd register\n"); 137 138 mt7530_mutex_unlock(priv); 139 } 140 141 static void 142 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 143 { 144 core_rmw(priv, reg, 0, val); 145 } 146 147 static void 148 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 149 { 150 core_rmw(priv, reg, val, 0); 151 } 152 153 static int 154 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 155 { 156 int ret; 157 158 ret = regmap_write(priv->regmap, reg, val); 159 160 if (ret < 0) 161 dev_err(priv->dev, 162 "failed to write mt7530 register\n"); 163 164 return ret; 165 } 166 167 static u32 168 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 169 { 170 int ret; 171 u32 val; 172 173 ret = regmap_read(priv->regmap, reg, &val); 174 if (ret) { 175 WARN_ON_ONCE(1); 176 dev_err(priv->dev, 177 "failed to read mt7530 register\n"); 178 return 0; 179 } 180 181 return val; 182 } 183 184 static void 185 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 186 { 187 mt7530_mutex_lock(priv); 188 189 mt7530_mii_write(priv, reg, val); 190 191 mt7530_mutex_unlock(priv); 192 } 193 194 static u32 195 _mt7530_read(struct mt7530_dummy_poll *p) 196 { 197 u32 val; 198 199 mt7530_mutex_lock(p->priv); 200 201 val = mt7530_mii_read(p->priv, p->reg); 202 203 mt7530_mutex_unlock(p->priv); 204 205 return val; 206 } 207 208 static u32 209 mt7530_read(struct mt7530_priv *priv, u32 reg) 210 { 211 struct mt7530_dummy_poll p; 212 213 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 214 return _mt7530_read(&p); 215 } 216 217 static void 218 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 219 u32 mask, u32 set) 220 { 221 mt7530_mutex_lock(priv); 222 223 regmap_update_bits(priv->regmap, reg, mask, set); 224 225 mt7530_mutex_unlock(priv); 226 } 227 228 static void 229 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 230 { 231 mt7530_rmw(priv, reg, val, val); 232 } 233 234 static void 235 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 236 { 237 mt7530_rmw(priv, reg, val, 0); 238 } 239 240 static int 241 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 242 { 243 u32 val; 244 int ret; 245 246 /* Set the command operating upon the MAC address entries */ 247 val = ATC_BUSY | ATC_MAT(0) | cmd; 248 mt7530_write(priv, MT7530_ATC, val); 249 250 mt7530_mutex_lock(priv); 251 252 ret = regmap_read_poll_timeout(priv->regmap, MT7530_ATC, val, 253 !(val & ATC_BUSY), 20, 20000); 254 if (!ret) 255 ret = regmap_read(priv->regmap, MT7530_ATC, &val); 256 257 mt7530_mutex_unlock(priv); 258 259 if (ret < 0) { 260 dev_err(priv->dev, "reset timeout\n"); 261 return ret; 262 } 263 264 /* Additional sanity for read command if the specified 265 * entry is invalid 266 */ 267 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 268 return -EINVAL; 269 270 if (rsp) 271 *rsp = val; 272 273 return 0; 274 } 275 276 static void 277 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 278 { 279 u32 reg[3]; 280 int i; 281 282 /* Read from ARL table into an array */ 283 for (i = 0; i < 3; i++) { 284 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 285 286 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 287 __func__, __LINE__, i, reg[i]); 288 } 289 290 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 291 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 292 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 293 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 294 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 295 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 296 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 297 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 298 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 299 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 300 } 301 302 static void 303 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 304 u8 port_mask, const u8 *mac, 305 u8 aging, u8 type) 306 { 307 u32 reg[3] = { 0 }; 308 int i; 309 310 reg[1] |= vid & CVID_MASK; 311 reg[1] |= ATA2_IVL; 312 reg[1] |= ATA2_FID(FID_BRIDGED); 313 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 314 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 315 /* STATIC_ENT indicate that entry is static wouldn't 316 * be aged out and STATIC_EMP specified as erasing an 317 * entry 318 */ 319 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 320 reg[1] |= mac[5] << MAC_BYTE_5; 321 reg[1] |= mac[4] << MAC_BYTE_4; 322 reg[0] |= mac[3] << MAC_BYTE_3; 323 reg[0] |= mac[2] << MAC_BYTE_2; 324 reg[0] |= mac[1] << MAC_BYTE_1; 325 reg[0] |= mac[0] << MAC_BYTE_0; 326 327 /* Write array into the ARL table */ 328 for (i = 0; i < 3; i++) 329 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 330 } 331 332 /* Set up switch core clock for MT7530 */ 333 static void mt7530_pll_setup(struct mt7530_priv *priv) 334 { 335 /* Disable core clock */ 336 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 337 338 /* Disable PLL */ 339 core_write(priv, CORE_GSWPLL_GRP1, 0); 340 341 /* Set core clock into 500Mhz */ 342 core_write(priv, CORE_GSWPLL_GRP2, 343 RG_GSWPLL_POSDIV_500M(1) | 344 RG_GSWPLL_FBKDIV_500M(25)); 345 346 /* Enable PLL */ 347 core_write(priv, CORE_GSWPLL_GRP1, 348 RG_GSWPLL_EN_PRE | 349 RG_GSWPLL_POSDIV_200M(2) | 350 RG_GSWPLL_FBKDIV_200M(32)); 351 352 udelay(20); 353 354 /* Enable core clock */ 355 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 356 } 357 358 /* If port 6 is available as a CPU port, always prefer that as the default, 359 * otherwise don't care. 360 */ 361 static struct dsa_port * 362 mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) 363 { 364 struct dsa_port *cpu_dp = dsa_to_port(ds, 6); 365 366 if (dsa_port_is_cpu(cpu_dp)) 367 return cpu_dp; 368 369 return NULL; 370 } 371 372 /* Setup port 6 interface mode and TRGMII TX circuit */ 373 static void 374 mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) 375 { 376 struct mt7530_priv *priv = ds->priv; 377 u32 ncpo1, ssc_delta, xtal; 378 379 /* Disable the MT7530 TRGMII clocks */ 380 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 381 382 if (interface == PHY_INTERFACE_MODE_RGMII) { 383 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 384 P6_INTF_MODE(0)); 385 return; 386 } 387 388 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1)); 389 390 xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK; 391 392 if (xtal == MT7530_XTAL_25MHZ) 393 ssc_delta = 0x57; 394 else 395 ssc_delta = 0x87; 396 397 if (priv->id == ID_MT7621) { 398 /* PLL frequency: 125MHz: 1.0GBit */ 399 if (xtal == MT7530_XTAL_40MHZ) 400 ncpo1 = 0x0640; 401 if (xtal == MT7530_XTAL_25MHZ) 402 ncpo1 = 0x0a00; 403 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 404 if (xtal == MT7530_XTAL_40MHZ) 405 ncpo1 = 0x0c80; 406 if (xtal == MT7530_XTAL_25MHZ) 407 ncpo1 = 0x1400; 408 } 409 410 /* Setup the MT7530 TRGMII Tx Clock */ 411 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 412 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 413 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 414 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 415 core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | 416 RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); 417 core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL | 418 RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1)); 419 core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG | 420 RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 421 422 /* Enable the MT7530 TRGMII clocks */ 423 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 424 } 425 426 static void 427 mt7531_pll_setup(struct mt7530_priv *priv) 428 { 429 enum mt7531_xtal_fsel xtal; 430 u32 top_sig; 431 u32 hwstrap; 432 u32 val; 433 434 val = mt7530_read(priv, MT7531_CREV); 435 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 436 hwstrap = mt7530_read(priv, MT753X_TRAP); 437 if ((val & CHIP_REV_M) > 0) 438 xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ : 439 MT7531_XTAL_FSEL_25MHZ; 440 else 441 xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ : 442 MT7531_XTAL_FSEL_40MHZ; 443 444 /* Step 1 : Disable MT7531 COREPLL */ 445 val = mt7530_read(priv, MT7531_PLLGP_EN); 446 val &= ~EN_COREPLL; 447 mt7530_write(priv, MT7531_PLLGP_EN, val); 448 449 /* Step 2: switch to XTAL output */ 450 val = mt7530_read(priv, MT7531_PLLGP_EN); 451 val |= SW_CLKSW; 452 mt7530_write(priv, MT7531_PLLGP_EN, val); 453 454 val = mt7530_read(priv, MT7531_PLLGP_CR0); 455 val &= ~RG_COREPLL_EN; 456 mt7530_write(priv, MT7531_PLLGP_CR0, val); 457 458 /* Step 3: disable PLLGP and enable program PLLGP */ 459 val = mt7530_read(priv, MT7531_PLLGP_EN); 460 val |= SW_PLLGP; 461 mt7530_write(priv, MT7531_PLLGP_EN, val); 462 463 /* Step 4: program COREPLL output frequency to 500MHz */ 464 val = mt7530_read(priv, MT7531_PLLGP_CR0); 465 val &= ~RG_COREPLL_POSDIV_M; 466 val |= 2 << RG_COREPLL_POSDIV_S; 467 mt7530_write(priv, MT7531_PLLGP_CR0, val); 468 usleep_range(25, 35); 469 470 switch (xtal) { 471 case MT7531_XTAL_FSEL_25MHZ: 472 val = mt7530_read(priv, MT7531_PLLGP_CR0); 473 val &= ~RG_COREPLL_SDM_PCW_M; 474 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 475 mt7530_write(priv, MT7531_PLLGP_CR0, val); 476 break; 477 case MT7531_XTAL_FSEL_40MHZ: 478 val = mt7530_read(priv, MT7531_PLLGP_CR0); 479 val &= ~RG_COREPLL_SDM_PCW_M; 480 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 481 mt7530_write(priv, MT7531_PLLGP_CR0, val); 482 break; 483 } 484 485 /* Set feedback divide ratio update signal to high */ 486 val = mt7530_read(priv, MT7531_PLLGP_CR0); 487 val |= RG_COREPLL_SDM_PCW_CHG; 488 mt7530_write(priv, MT7531_PLLGP_CR0, val); 489 /* Wait for at least 16 XTAL clocks */ 490 usleep_range(10, 20); 491 492 /* Step 5: set feedback divide ratio update signal to low */ 493 val = mt7530_read(priv, MT7531_PLLGP_CR0); 494 val &= ~RG_COREPLL_SDM_PCW_CHG; 495 mt7530_write(priv, MT7531_PLLGP_CR0, val); 496 497 /* Enable 325M clock for SGMII */ 498 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 499 500 /* Enable 250SSC clock for RGMII */ 501 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 502 503 /* Step 6: Enable MT7531 PLL */ 504 val = mt7530_read(priv, MT7531_PLLGP_CR0); 505 val |= RG_COREPLL_EN; 506 mt7530_write(priv, MT7531_PLLGP_CR0, val); 507 508 val = mt7530_read(priv, MT7531_PLLGP_EN); 509 val |= EN_COREPLL; 510 mt7530_write(priv, MT7531_PLLGP_EN, val); 511 usleep_range(25, 35); 512 } 513 514 static void 515 mt7530_mib_reset(struct dsa_switch *ds) 516 { 517 struct mt7530_priv *priv = ds->priv; 518 519 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 520 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 521 } 522 523 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 524 { 525 return mdiobus_read_nested(priv->bus, port, regnum); 526 } 527 528 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 529 u16 val) 530 { 531 return mdiobus_write_nested(priv->bus, port, regnum, val); 532 } 533 534 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 535 int devad, int regnum) 536 { 537 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 538 } 539 540 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 541 int regnum, u16 val) 542 { 543 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 544 } 545 546 static int 547 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 548 int regnum) 549 { 550 u32 reg, val; 551 int ret; 552 553 mt7530_mutex_lock(priv); 554 555 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 556 !(val & MT7531_PHY_ACS_ST), 20, 100000); 557 if (ret < 0) { 558 dev_err(priv->dev, "poll timeout\n"); 559 goto out; 560 } 561 562 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 563 MT7531_MDIO_DEV_ADDR(devad) | regnum; 564 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 565 566 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 567 !(val & MT7531_PHY_ACS_ST), 20, 100000); 568 if (ret < 0) { 569 dev_err(priv->dev, "poll timeout\n"); 570 goto out; 571 } 572 573 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 574 MT7531_MDIO_DEV_ADDR(devad); 575 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 576 577 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 578 !(val & MT7531_PHY_ACS_ST), 20, 100000); 579 if (ret < 0) { 580 dev_err(priv->dev, "poll timeout\n"); 581 goto out; 582 } 583 584 ret = val & MT7531_MDIO_RW_DATA_MASK; 585 out: 586 mt7530_mutex_unlock(priv); 587 588 return ret; 589 } 590 591 static int 592 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 593 int regnum, u16 data) 594 { 595 u32 val, reg; 596 int ret; 597 598 mt7530_mutex_lock(priv); 599 600 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 601 !(val & MT7531_PHY_ACS_ST), 20, 100000); 602 if (ret < 0) { 603 dev_err(priv->dev, "poll timeout\n"); 604 goto out; 605 } 606 607 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 608 MT7531_MDIO_DEV_ADDR(devad) | regnum; 609 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 610 611 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 612 !(val & MT7531_PHY_ACS_ST), 20, 100000); 613 if (ret < 0) { 614 dev_err(priv->dev, "poll timeout\n"); 615 goto out; 616 } 617 618 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 619 MT7531_MDIO_DEV_ADDR(devad) | data; 620 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 621 622 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 623 !(val & MT7531_PHY_ACS_ST), 20, 100000); 624 if (ret < 0) { 625 dev_err(priv->dev, "poll timeout\n"); 626 goto out; 627 } 628 629 out: 630 mt7530_mutex_unlock(priv); 631 632 return ret; 633 } 634 635 static int 636 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 637 { 638 int ret; 639 u32 val; 640 641 mt7530_mutex_lock(priv); 642 643 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 644 !(val & MT7531_PHY_ACS_ST), 20, 100000); 645 if (ret < 0) { 646 dev_err(priv->dev, "poll timeout\n"); 647 goto out; 648 } 649 650 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 651 MT7531_MDIO_REG_ADDR(regnum); 652 653 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 654 655 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 656 !(val & MT7531_PHY_ACS_ST), 20, 100000); 657 if (ret < 0) { 658 dev_err(priv->dev, "poll timeout\n"); 659 goto out; 660 } 661 662 ret = val & MT7531_MDIO_RW_DATA_MASK; 663 out: 664 mt7530_mutex_unlock(priv); 665 666 return ret; 667 } 668 669 static int 670 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 671 u16 data) 672 { 673 int ret; 674 u32 reg; 675 676 mt7530_mutex_lock(priv); 677 678 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, reg, 679 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 680 if (ret < 0) { 681 dev_err(priv->dev, "poll timeout\n"); 682 goto out; 683 } 684 685 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 686 MT7531_MDIO_REG_ADDR(regnum) | data; 687 688 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 689 690 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, reg, 691 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 692 if (ret < 0) { 693 dev_err(priv->dev, "poll timeout\n"); 694 goto out; 695 } 696 697 out: 698 mt7530_mutex_unlock(priv); 699 700 return ret; 701 } 702 703 static int 704 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 705 { 706 struct mt7530_priv *priv = bus->priv; 707 708 return priv->info->phy_read_c22(priv, port, regnum); 709 } 710 711 static int 712 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 713 { 714 struct mt7530_priv *priv = bus->priv; 715 716 return priv->info->phy_read_c45(priv, port, devad, regnum); 717 } 718 719 static int 720 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 721 { 722 struct mt7530_priv *priv = bus->priv; 723 724 return priv->info->phy_write_c22(priv, port, regnum, val); 725 } 726 727 static int 728 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 729 u16 val) 730 { 731 struct mt7530_priv *priv = bus->priv; 732 733 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 734 } 735 736 static void 737 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 738 uint8_t *data) 739 { 740 int i; 741 742 if (stringset != ETH_SS_STATS) 743 return; 744 745 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 746 ethtool_puts(&data, mt7530_mib[i].name); 747 } 748 749 static void 750 mt7530_read_port_stats(struct mt7530_priv *priv, int port, 751 u32 offset, u8 size, uint64_t *data) 752 { 753 u32 val, reg = MT7530_PORT_MIB_COUNTER(port) + offset; 754 755 val = mt7530_read(priv, reg); 756 *data = val; 757 758 if (size == 2) { 759 val = mt7530_read(priv, reg + 4); 760 *data |= (u64)val << 32; 761 } 762 } 763 764 static void 765 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 766 uint64_t *data) 767 { 768 struct mt7530_priv *priv = ds->priv; 769 const struct mt7530_mib_desc *mib; 770 int i; 771 772 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 773 mib = &mt7530_mib[i]; 774 775 mt7530_read_port_stats(priv, port, mib->offset, mib->size, 776 data + i); 777 } 778 } 779 780 static int 781 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 782 { 783 if (sset != ETH_SS_STATS) 784 return 0; 785 786 return ARRAY_SIZE(mt7530_mib); 787 } 788 789 static void mt7530_get_eth_mac_stats(struct dsa_switch *ds, int port, 790 struct ethtool_eth_mac_stats *mac_stats) 791 { 792 struct mt7530_priv *priv = ds->priv; 793 794 /* MIB counter doesn't provide a FramesTransmittedOK but instead 795 * provide stats for Unicast, Broadcast and Multicast frames separately. 796 * To simulate a global frame counter, read Unicast and addition Multicast 797 * and Broadcast later 798 */ 799 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1, 800 &mac_stats->FramesTransmittedOK); 801 802 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_SINGLE_COLLISION, 1, 803 &mac_stats->SingleCollisionFrames); 804 805 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTIPLE_COLLISION, 1, 806 &mac_stats->MultipleCollisionFrames); 807 808 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1, 809 &mac_stats->FramesReceivedOK); 810 811 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2, 812 &mac_stats->OctetsTransmittedOK); 813 814 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_ALIGN_ERR, 1, 815 &mac_stats->AlignmentErrors); 816 817 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DEFERRED, 1, 818 &mac_stats->FramesWithDeferredXmissions); 819 820 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_LATE_COLLISION, 1, 821 &mac_stats->LateCollisions); 822 823 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION, 1, 824 &mac_stats->FramesAbortedDueToXSColls); 825 826 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2, 827 &mac_stats->OctetsReceivedOK); 828 829 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1, 830 &mac_stats->MulticastFramesXmittedOK); 831 mac_stats->FramesTransmittedOK += mac_stats->MulticastFramesXmittedOK; 832 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1, 833 &mac_stats->BroadcastFramesXmittedOK); 834 mac_stats->FramesTransmittedOK += mac_stats->BroadcastFramesXmittedOK; 835 836 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1, 837 &mac_stats->MulticastFramesReceivedOK); 838 mac_stats->FramesReceivedOK += mac_stats->MulticastFramesReceivedOK; 839 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1, 840 &mac_stats->BroadcastFramesReceivedOK); 841 mac_stats->FramesReceivedOK += mac_stats->BroadcastFramesReceivedOK; 842 } 843 844 static const struct ethtool_rmon_hist_range mt7530_rmon_ranges[] = { 845 { 0, 64 }, 846 { 65, 127 }, 847 { 128, 255 }, 848 { 256, 511 }, 849 { 512, 1023 }, 850 { 1024, MT7530_MAX_MTU }, 851 {} 852 }; 853 854 static void mt7530_get_rmon_stats(struct dsa_switch *ds, int port, 855 struct ethtool_rmon_stats *rmon_stats, 856 const struct ethtool_rmon_hist_range **ranges) 857 { 858 struct mt7530_priv *priv = ds->priv; 859 860 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNDER_SIZE_ERR, 1, 861 &rmon_stats->undersize_pkts); 862 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_OVER_SZ_ERR, 1, 863 &rmon_stats->oversize_pkts); 864 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_FRAG_ERR, 1, 865 &rmon_stats->fragments); 866 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_JABBER_ERR, 1, 867 &rmon_stats->jabbers); 868 869 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_64, 1, 870 &rmon_stats->hist[0]); 871 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127, 1, 872 &rmon_stats->hist[1]); 873 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255, 1, 874 &rmon_stats->hist[2]); 875 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511, 1, 876 &rmon_stats->hist[3]); 877 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023, 1, 878 &rmon_stats->hist[4]); 879 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX, 1, 880 &rmon_stats->hist[5]); 881 882 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_64, 1, 883 &rmon_stats->hist_tx[0]); 884 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127, 1, 885 &rmon_stats->hist_tx[1]); 886 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255, 1, 887 &rmon_stats->hist_tx[2]); 888 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511, 1, 889 &rmon_stats->hist_tx[3]); 890 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023, 1, 891 &rmon_stats->hist_tx[4]); 892 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX, 1, 893 &rmon_stats->hist_tx[5]); 894 895 *ranges = mt7530_rmon_ranges; 896 } 897 898 static void mt7530_read_port_stats64(struct mt7530_priv *priv, int port, 899 struct rtnl_link_stats64 *storage) 900 { 901 uint64_t data; 902 903 /* MIB counter doesn't provide a FramesTransmittedOK but instead 904 * provide stats for Unicast, Broadcast and Multicast frames separately. 905 * To simulate a global frame counter, read Unicast and addition Multicast 906 * and Broadcast later 907 */ 908 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1, 909 &storage->rx_packets); 910 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1, 911 &storage->multicast); 912 storage->rx_packets += storage->multicast; 913 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1, 914 &data); 915 storage->rx_packets += data; 916 917 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1, 918 &storage->tx_packets); 919 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1, 920 &data); 921 storage->tx_packets += data; 922 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1, 923 &data); 924 storage->tx_packets += data; 925 926 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2, 927 &storage->rx_bytes); 928 929 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2, 930 &storage->tx_bytes); 931 932 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_DROP, 1, 933 &storage->rx_dropped); 934 935 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DROP, 1, 936 &storage->tx_dropped); 937 938 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_CRC_ERR, 1, 939 &storage->rx_crc_errors); 940 } 941 942 static void mt7530_stats_refresh(struct mt7530_priv *priv) 943 { 944 struct rtnl_link_stats64 stats = {}; 945 struct dsa_port *dp; 946 int port; 947 948 dsa_switch_for_each_user_port(dp, priv->ds) { 949 port = dp->index; 950 951 mt7530_read_port_stats64(priv, port, &stats); 952 953 spin_lock_bh(&priv->stats_lock); 954 priv->ports[port].stats = stats; 955 priv->stats_last = jiffies; 956 spin_unlock_bh(&priv->stats_lock); 957 } 958 } 959 960 static void mt7530_stats_poll(struct work_struct *work) 961 { 962 struct mt7530_priv *priv = container_of(work, struct mt7530_priv, 963 stats_work.work); 964 965 mt7530_stats_refresh(priv); 966 schedule_delayed_work(&priv->stats_work, 967 MT7530_STATS_POLL_INTERVAL); 968 } 969 970 static void mt7530_get_stats64(struct dsa_switch *ds, int port, 971 struct rtnl_link_stats64 *storage) 972 { 973 struct mt7530_priv *priv = ds->priv; 974 bool refresh; 975 976 if (priv->bus) { 977 spin_lock_bh(&priv->stats_lock); 978 *storage = priv->ports[port].stats; 979 refresh = time_after(jiffies, priv->stats_last + 980 MT7530_STATS_RATE_LIMIT); 981 spin_unlock_bh(&priv->stats_lock); 982 if (refresh) 983 mod_delayed_work(system_percpu_wq, 984 &priv->stats_work, 0); 985 } else { 986 mt7530_read_port_stats64(priv, port, storage); 987 } 988 } 989 990 static void mt7530_get_eth_ctrl_stats(struct dsa_switch *ds, int port, 991 struct ethtool_eth_ctrl_stats *ctrl_stats) 992 { 993 struct mt7530_priv *priv = ds->priv; 994 995 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PAUSE, 1, 996 &ctrl_stats->MACControlFramesTransmitted); 997 998 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PAUSE, 1, 999 &ctrl_stats->MACControlFramesReceived); 1000 } 1001 1002 static int 1003 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 1004 { 1005 struct mt7530_priv *priv = ds->priv; 1006 unsigned int secs = msecs / 1000; 1007 unsigned int tmp_age_count; 1008 unsigned int error = -1; 1009 unsigned int age_count; 1010 unsigned int age_unit; 1011 1012 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds. 1013 * The DSA core has already validated the range using 1014 * ds->ageing_time_min and ds->ageing_time_max. 1015 * 1016 * Iterate through all possible age_count values to find the closest 1017 * pair. Start from 1 because the per-entry aging counter is 1018 * initialized to AGE_CNT and a value of 0 means the entry will 1019 * never be aged out. 1020 */ 1021 for (tmp_age_count = 1; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 1022 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 1023 1024 if (tmp_age_unit <= AGE_UNIT_MAX) { 1025 unsigned int tmp_error = secs - 1026 (tmp_age_count + 1) * (tmp_age_unit + 1); 1027 1028 /* found a closer pair */ 1029 if (error > tmp_error) { 1030 error = tmp_error; 1031 age_count = tmp_age_count; 1032 age_unit = tmp_age_unit; 1033 } 1034 1035 /* found the exact match, so break the loop */ 1036 if (!error) 1037 break; 1038 } 1039 } 1040 1041 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 1042 1043 return 0; 1044 } 1045 1046 static const char *mt7530_p5_mode_str(unsigned int mode) 1047 { 1048 switch (mode) { 1049 case MUX_PHY_P0: 1050 return "MUX PHY P0"; 1051 case MUX_PHY_P4: 1052 return "MUX PHY P4"; 1053 default: 1054 return "GMAC5"; 1055 } 1056 } 1057 1058 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 1059 { 1060 struct mt7530_priv *priv = ds->priv; 1061 u8 tx_delay = 0; 1062 int val; 1063 1064 mutex_lock(&priv->reg_mutex); 1065 1066 val = mt7530_read(priv, MT753X_MTRAP); 1067 1068 val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE; 1069 1070 switch (priv->p5_mode) { 1071 /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ 1072 case MUX_PHY_P0: 1073 val |= MT7530_P5_PHY0_SEL; 1074 fallthrough; 1075 1076 /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ 1077 case MUX_PHY_P4: 1078 /* Setup the MAC by default for the cpu port */ 1079 mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); 1080 break; 1081 1082 /* GMAC5: P5 -> SoC MAC or external PHY */ 1083 default: 1084 val |= MT7530_P5_MAC_SEL; 1085 break; 1086 } 1087 1088 /* Setup RGMII settings */ 1089 if (phy_interface_mode_is_rgmii(interface)) { 1090 val |= MT7530_P5_RGMII_MODE; 1091 1092 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 1093 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 1094 1095 /* Don't set delay in DSA mode */ 1096 if (!dsa_is_dsa_port(priv->ds, 5) && 1097 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 1098 interface == PHY_INTERFACE_MODE_RGMII_ID)) 1099 tx_delay = 4; /* n * 0.5 ns */ 1100 1101 /* P5 RGMII TX Clock Control: delay x */ 1102 mt7530_write(priv, MT7530_P5RGMIITXCR, 1103 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 1104 1105 /* reduce P5 RGMII Tx driving, 8mA */ 1106 mt7530_write(priv, MT7530_IO_DRV_CR, 1107 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 1108 } 1109 1110 mt7530_write(priv, MT753X_MTRAP, val); 1111 1112 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, 1113 mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); 1114 1115 mutex_unlock(&priv->reg_mutex); 1116 } 1117 1118 /* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL) 1119 * of the Open Systems Interconnection basic reference model (OSI/RM) are 1120 * described; the medium access control (MAC) and logical link control (LLC) 1121 * sublayers. The MAC sublayer is the one facing the physical layer. 1122 * 1123 * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A 1124 * Bridge component comprises a MAC Relay Entity for interconnecting the Ports 1125 * of the Bridge, at least two Ports, and higher layer entities with at least a 1126 * Spanning Tree Protocol Entity included. 1127 * 1128 * Each Bridge Port also functions as an end station and shall provide the MAC 1129 * Service to an LLC Entity. Each instance of the MAC Service is provided to a 1130 * distinct LLC Entity that supports protocol identification, multiplexing, and 1131 * demultiplexing, for protocol data unit (PDU) transmission and reception by 1132 * one or more higher layer entities. 1133 * 1134 * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC 1135 * Entity associated with each Bridge Port is modeled as being directly 1136 * connected to the attached Local Area Network (LAN). 1137 * 1138 * On the switch with CPU port architecture, CPU port functions as Management 1139 * Port, and the Management Port functionality is provided by software which 1140 * functions as an end station. Software is connected to an IEEE 802 LAN that is 1141 * wholly contained within the system that incorporates the Bridge. Software 1142 * provides access to the LLC Entity associated with each Bridge Port by the 1143 * value of the source port field on the special tag on the frame received by 1144 * software. 1145 * 1146 * We call frames that carry control information to determine the active 1147 * topology and current extent of each Virtual Local Area Network (VLAN), i.e., 1148 * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration 1149 * Protocol Data Units (MVRPDUs), and frames from other link constrained 1150 * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and 1151 * Link Layer Discovery Protocol (LLDP), link-local frames. They are not 1152 * forwarded by a Bridge. Permanently configured entries in the filtering 1153 * database (FDB) ensure that such frames are discarded by the Forwarding 1154 * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail: 1155 * 1156 * Each of the reserved MAC addresses specified in Table 8-1 1157 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be 1158 * permanently configured in the FDB in C-VLAN components and ERs. 1159 * 1160 * Each of the reserved MAC addresses specified in Table 8-2 1161 * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently 1162 * configured in the FDB in S-VLAN components. 1163 * 1164 * Each of the reserved MAC addresses specified in Table 8-3 1165 * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in 1166 * TPMR components. 1167 * 1168 * The FDB entries for reserved MAC addresses shall specify filtering for all 1169 * Bridge Ports and all VIDs. Management shall not provide the capability to 1170 * modify or remove entries for reserved MAC addresses. 1171 * 1172 * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of 1173 * propagation of PDUs within a Bridged Network, as follows: 1174 * 1175 * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no 1176 * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN) 1177 * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward. 1178 * PDUs transmitted using this destination address, or any other addresses 1179 * that appear in Table 8-1, Table 8-2, and Table 8-3 1180 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can 1181 * therefore travel no further than those stations that can be reached via a 1182 * single individual LAN from the originating station. 1183 * 1184 * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an 1185 * address that no conformant S-VLAN component, C-VLAN component, or MAC 1186 * Bridge can forward; however, this address is relayed by a TPMR component. 1187 * PDUs using this destination address, or any of the other addresses that 1188 * appear in both Table 8-1 and Table 8-2 but not in Table 8-3 1189 * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by 1190 * any TPMRs but will propagate no further than the nearest S-VLAN component, 1191 * C-VLAN component, or MAC Bridge. 1192 * 1193 * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address 1194 * that no conformant C-VLAN component, MAC Bridge can forward; however, it is 1195 * relayed by TPMR components and S-VLAN components. PDUs using this 1196 * destination address, or any of the other addresses that appear in Table 8-1 1197 * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]), 1198 * will be relayed by TPMR components and S-VLAN components but will propagate 1199 * no further than the nearest C-VLAN component or MAC Bridge. 1200 * 1201 * Because the LLC Entity associated with each Bridge Port is provided via CPU 1202 * port, we must not filter these frames but forward them to CPU port. 1203 * 1204 * In a Bridge, the transmission Port is majorly decided by ingress and egress 1205 * rules, FDB, and spanning tree Port State functions of the Forwarding Process. 1206 * For link-local frames, only CPU port should be designated as destination port 1207 * in the FDB, and the other functions of the Forwarding Process must not 1208 * interfere with the decision of the transmission Port. We call this process 1209 * trapping frames to CPU port. 1210 * 1211 * Therefore, on the switch with CPU port architecture, link-local frames must 1212 * be trapped to CPU port, and certain link-local frames received by a Port of a 1213 * Bridge comprising a TPMR component or an S-VLAN component must be excluded 1214 * from it. 1215 * 1216 * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port 1217 * MAC Relay (TPMR) component as a TPMR component supports only a subset of the 1218 * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port 1219 * doesn't count) of this architecture will either function as a standard MAC 1220 * Bridge or a standard VLAN Bridge. 1221 * 1222 * Therefore, a Bridge of this architecture can only comprise S-VLAN components, 1223 * C-VLAN components, or MAC Bridge components. Since there's no TPMR component, 1224 * we don't need to relay PDUs using the destination addresses specified on the 1225 * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge 1226 * section where they must be relayed by TPMR components. 1227 * 1228 * One option to trap link-local frames to CPU port is to add static FDB entries 1229 * with CPU port designated as destination port. However, because that 1230 * Independent VLAN Learning (IVL) is being used on every VID, each entry only 1231 * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC 1232 * Bridge component or a C-VLAN component, there would have to be 16 times 4096 1233 * entries. This switch intellectual property can only hold a maximum of 2048 1234 * entries. Using this option, there also isn't a mechanism to prevent 1235 * link-local frames from being discarded when the spanning tree Port State of 1236 * the reception Port is discarding. 1237 * 1238 * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4 1239 * registers. Whilst this applies to every VID, it doesn't contain all of the 1240 * reserved MAC addresses without affecting the remaining Standard Group MAC 1241 * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the 1242 * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination 1243 * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF 1244 * destination addresses which may be relayed by MAC Bridges or VLAN Bridges. 1245 * The latter option provides better but not complete conformance. 1246 * 1247 * This switch intellectual property also does not provide a mechanism to trap 1248 * link-local frames with specific destination addresses to CPU port by Bridge, 1249 * to conform to the filtering rules for the distinct Bridge components. 1250 * 1251 * Therefore, regardless of the type of the Bridge component, link-local frames 1252 * with these destination addresses will be trapped to CPU port: 1253 * 1254 * 01-80-C2-00-00-[00,01,02,03,0E] 1255 * 1256 * In a Bridge comprising a MAC Bridge component or a C-VLAN component: 1257 * 1258 * Link-local frames with these destination addresses won't be trapped to CPU 1259 * port which won't conform to IEEE Std 802.1Q-2022: 1260 * 1261 * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] 1262 * 1263 * In a Bridge comprising an S-VLAN component: 1264 * 1265 * Link-local frames with these destination addresses will be trapped to CPU 1266 * port which won't conform to IEEE Std 802.1Q-2022: 1267 * 1268 * 01-80-C2-00-00-00 1269 * 1270 * Link-local frames with these destination addresses won't be trapped to CPU 1271 * port which won't conform to IEEE Std 802.1Q-2022: 1272 * 1273 * 01-80-C2-00-00-[04,05,06,07,08,09,0A] 1274 * 1275 * To trap link-local frames to CPU port as conformant as this switch 1276 * intellectual property can allow, link-local frames are made to be regarded as 1277 * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual 1278 * property only lets the frames regarded as BPDUs bypass the spanning tree Port 1279 * State function of the Forwarding Process. 1280 * 1281 * The only remaining interference is the ingress rules. When the reception Port 1282 * has no PVID assigned on software, VLAN-untagged frames won't be allowed in. 1283 * There doesn't seem to be a mechanism on the switch intellectual property to 1284 * have link-local frames bypass this function of the Forwarding Process. 1285 */ 1286 static void 1287 mt753x_trap_frames(struct mt7530_priv *priv) 1288 { 1289 /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress 1290 * them with the EG_TAG attribute set to disabled (system default) 1291 * so that any VLAN tags in the frame are not modified by the 1292 * switch egress VLAN tag processing. This preserves VLAN tags 1293 * for reception on VLAN sub-interfaces. 1294 */ 1295 mt7530_rmw(priv, MT753X_BPC, 1296 PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK | 1297 BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK, 1298 PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1299 PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) | 1300 BPDU_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1301 TO_CPU_FW_CPU_ONLY); 1302 1303 /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and 1304 * egress them with EG_TAG disabled. 1305 */ 1306 mt7530_rmw(priv, MT753X_RGAC1, 1307 R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK | 1308 R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK, 1309 R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1310 R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR | 1311 R01_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1312 TO_CPU_FW_CPU_ONLY); 1313 1314 /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and 1315 * egress them with EG_TAG disabled. 1316 */ 1317 mt7530_rmw(priv, MT753X_RGAC2, 1318 R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK | 1319 R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK, 1320 R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1321 R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR | 1322 R03_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1323 TO_CPU_FW_CPU_ONLY); 1324 } 1325 1326 static void 1327 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1328 { 1329 struct mt7530_priv *priv = ds->priv; 1330 1331 /* Enable Mediatek header mode on the cpu port */ 1332 mt7530_write(priv, MT7530_PVC_P(port), 1333 PORT_SPEC_TAG); 1334 1335 /* Enable flooding on the CPU port */ 1336 mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | 1337 UNU_FFP(BIT(port))); 1338 1339 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on 1340 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that 1341 * is affine to the inbound user port. 1342 */ 1343 if (priv->id == ID_MT7531 || priv->id == ID_MT7988 || 1344 priv->id == ID_EN7581 || priv->id == ID_AN7583) 1345 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); 1346 1347 /* CPU port gets connected to all user ports of 1348 * the switch. 1349 */ 1350 mt7530_write(priv, MT7530_PCR_P(port), 1351 PCR_MATRIX(dsa_user_ports(priv->ds))); 1352 1353 /* Set to fallback mode for independent VLAN learning */ 1354 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1355 MT7530_PORT_FALLBACK_MODE); 1356 } 1357 1358 static int 1359 mt7530_port_enable(struct dsa_switch *ds, int port, 1360 struct phy_device *phy) 1361 { 1362 struct dsa_port *dp = dsa_to_port(ds, port); 1363 struct mt7530_priv *priv = ds->priv; 1364 1365 mutex_lock(&priv->reg_mutex); 1366 1367 /* Allow the user port gets connected to the cpu port and also 1368 * restore the port matrix if the port is the member of a certain 1369 * bridge. 1370 */ 1371 if (dsa_port_is_user(dp)) { 1372 struct dsa_port *cpu_dp = dp->cpu_dp; 1373 1374 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1375 } 1376 priv->ports[port].enable = true; 1377 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1378 priv->ports[port].pm); 1379 1380 mutex_unlock(&priv->reg_mutex); 1381 1382 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 1383 return 0; 1384 1385 if (port == 5) 1386 mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); 1387 else if (port == 6) 1388 mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS); 1389 1390 return 0; 1391 } 1392 1393 static void 1394 mt7530_port_disable(struct dsa_switch *ds, int port) 1395 { 1396 struct mt7530_priv *priv = ds->priv; 1397 1398 mutex_lock(&priv->reg_mutex); 1399 1400 /* Clear up all port matrix which could be restored in the next 1401 * enablement for the port. 1402 */ 1403 priv->ports[port].enable = false; 1404 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1405 PCR_MATRIX_CLR); 1406 1407 mutex_unlock(&priv->reg_mutex); 1408 1409 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 1410 return; 1411 1412 /* Do not set MT7530_P5_DIS when port 5 is being used for PHY muxing. */ 1413 if (port == 5 && priv->p5_mode == GMAC5) 1414 mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS); 1415 else if (port == 6) 1416 mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS); 1417 } 1418 1419 static int 1420 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1421 { 1422 struct mt7530_priv *priv = ds->priv; 1423 int length; 1424 u32 val; 1425 1426 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1427 * largest MTU of the user ports. Because the switch only has a global 1428 * RX length register, only allowing CPU port here is enough. 1429 */ 1430 if (!dsa_is_cpu_port(ds, port)) 1431 return 0; 1432 1433 mt7530_mutex_lock(priv); 1434 1435 val = mt7530_mii_read(priv, MT7530_GMACCR); 1436 val &= ~MAX_RX_PKT_LEN_MASK; 1437 1438 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1439 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1440 if (length <= 1522) { 1441 val |= MAX_RX_PKT_LEN_1522; 1442 } else if (length <= 1536) { 1443 val |= MAX_RX_PKT_LEN_1536; 1444 } else if (length <= 1552) { 1445 val |= MAX_RX_PKT_LEN_1552; 1446 } else { 1447 val &= ~MAX_RX_JUMBO_MASK; 1448 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1449 val |= MAX_RX_PKT_LEN_JUMBO; 1450 } 1451 1452 mt7530_mii_write(priv, MT7530_GMACCR, val); 1453 1454 mt7530_mutex_unlock(priv); 1455 1456 return 0; 1457 } 1458 1459 static int 1460 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1461 { 1462 return MT7530_MAX_MTU; 1463 } 1464 1465 static void 1466 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1467 { 1468 struct mt7530_priv *priv = ds->priv; 1469 u32 stp_state; 1470 1471 switch (state) { 1472 case BR_STATE_DISABLED: 1473 stp_state = MT7530_STP_DISABLED; 1474 break; 1475 case BR_STATE_BLOCKING: 1476 stp_state = MT7530_STP_BLOCKING; 1477 break; 1478 case BR_STATE_LISTENING: 1479 stp_state = MT7530_STP_LISTENING; 1480 break; 1481 case BR_STATE_LEARNING: 1482 stp_state = MT7530_STP_LEARNING; 1483 break; 1484 case BR_STATE_FORWARDING: 1485 default: 1486 stp_state = MT7530_STP_FORWARDING; 1487 break; 1488 } 1489 1490 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1491 FID_PST(FID_BRIDGED, stp_state)); 1492 } 1493 1494 static void mt7530_update_port_member(struct mt7530_priv *priv, int port, 1495 const struct net_device *bridge_dev, 1496 bool join) __must_hold(&priv->reg_mutex) 1497 { 1498 struct dsa_port *dp = dsa_to_port(priv->ds, port), *other_dp; 1499 struct mt7530_port *p = &priv->ports[port], *other_p; 1500 struct dsa_port *cpu_dp = dp->cpu_dp; 1501 u32 port_bitmap = BIT(cpu_dp->index); 1502 int other_port; 1503 bool isolated; 1504 1505 dsa_switch_for_each_user_port(other_dp, priv->ds) { 1506 other_port = other_dp->index; 1507 other_p = &priv->ports[other_port]; 1508 1509 if (dp == other_dp) 1510 continue; 1511 1512 /* Add/remove this port to/from the port matrix of the other 1513 * ports in the same bridge. If the port is disabled, port 1514 * matrix is kept and not being setup until the port becomes 1515 * enabled. 1516 */ 1517 if (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev)) 1518 continue; 1519 1520 isolated = p->isolated && other_p->isolated; 1521 1522 if (join && !isolated) { 1523 other_p->pm |= PCR_MATRIX(BIT(port)); 1524 port_bitmap |= BIT(other_port); 1525 } else { 1526 other_p->pm &= ~PCR_MATRIX(BIT(port)); 1527 } 1528 1529 if (other_p->enable) 1530 mt7530_rmw(priv, MT7530_PCR_P(other_port), 1531 PCR_MATRIX_MASK, other_p->pm); 1532 } 1533 1534 /* Add/remove the all other ports to this port matrix. For !join 1535 * (leaving the bridge), only the CPU port will remain in the port matrix 1536 * of this port. 1537 */ 1538 p->pm = PCR_MATRIX(port_bitmap); 1539 if (priv->ports[port].enable) 1540 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, p->pm); 1541 } 1542 1543 static int 1544 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1545 struct switchdev_brport_flags flags, 1546 struct netlink_ext_ack *extack) 1547 { 1548 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1549 BR_BCAST_FLOOD | BR_ISOLATED)) 1550 return -EINVAL; 1551 1552 return 0; 1553 } 1554 1555 static int 1556 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1557 struct switchdev_brport_flags flags, 1558 struct netlink_ext_ack *extack) 1559 { 1560 struct mt7530_priv *priv = ds->priv; 1561 1562 if (flags.mask & BR_LEARNING) 1563 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1564 flags.val & BR_LEARNING ? 0 : SA_DIS); 1565 1566 if (flags.mask & BR_FLOOD) 1567 mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)), 1568 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1569 1570 if (flags.mask & BR_MCAST_FLOOD) 1571 mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)), 1572 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1573 1574 if (flags.mask & BR_BCAST_FLOOD) 1575 mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)), 1576 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1577 1578 if (flags.mask & BR_ISOLATED) { 1579 struct dsa_port *dp = dsa_to_port(ds, port); 1580 struct net_device *bridge_dev = dsa_port_bridge_dev_get(dp); 1581 1582 priv->ports[port].isolated = !!(flags.val & BR_ISOLATED); 1583 1584 mutex_lock(&priv->reg_mutex); 1585 mt7530_update_port_member(priv, port, bridge_dev, true); 1586 mutex_unlock(&priv->reg_mutex); 1587 } 1588 1589 return 0; 1590 } 1591 1592 static int 1593 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1594 struct dsa_bridge bridge, bool *tx_fwd_offload, 1595 struct netlink_ext_ack *extack) 1596 { 1597 struct mt7530_priv *priv = ds->priv; 1598 1599 mutex_lock(&priv->reg_mutex); 1600 1601 mt7530_update_port_member(priv, port, bridge.dev, true); 1602 1603 /* Set to fallback mode for independent VLAN learning */ 1604 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1605 MT7530_PORT_FALLBACK_MODE); 1606 1607 mutex_unlock(&priv->reg_mutex); 1608 1609 return 0; 1610 } 1611 1612 static int 1613 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1614 { 1615 u32 val; 1616 int ret; 1617 1618 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1619 mt7530_write(priv, MT7530_VTCR, val); 1620 1621 mt7530_mutex_lock(priv); 1622 1623 ret = regmap_read_poll_timeout(priv->regmap, MT7530_VTCR, val, 1624 !(val & VTCR_BUSY), 20, 20000); 1625 if (!ret) 1626 ret = regmap_read(priv->regmap, MT7530_VTCR, &val); 1627 1628 mt7530_mutex_unlock(priv); 1629 1630 if (ret < 0) { 1631 dev_err(priv->dev, "poll timeout\n"); 1632 return ret; 1633 } 1634 1635 if (val & VTCR_INVALID) { 1636 dev_err(priv->dev, "read VTCR invalid\n"); 1637 return -EINVAL; 1638 } 1639 1640 return 0; 1641 } 1642 1643 static int 1644 mt7530_setup_vlan0(struct mt7530_priv *priv) 1645 { 1646 u32 val; 1647 1648 /* Validate the entry with independent learning, keep the original 1649 * ingress tag attribute. 1650 */ 1651 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1652 VLAN_VALID; 1653 mt7530_write(priv, MT7530_VAWD1, val); 1654 mt7530_write(priv, MT7530_VAWD2, 0); 1655 1656 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1657 } 1658 1659 static void 1660 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1661 { 1662 struct mt7530_priv *priv = ds->priv; 1663 bool all_user_ports_removed = true; 1664 int i; 1665 1666 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1667 * bridge. Don't set standalone ports to fallback mode. 1668 */ 1669 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1670 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1671 MT7530_PORT_FALLBACK_MODE); 1672 1673 mt7530_rmw(priv, MT7530_PVC_P(port), 1674 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1675 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1676 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1677 MT7530_VLAN_ACC_ALL); 1678 1679 /* Set PVID to 0 */ 1680 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1681 G0_PORT_VID_DEF); 1682 1683 for (i = 0; i < priv->ds->num_ports; i++) { 1684 if (i == port) 1685 continue; 1686 if (dsa_is_user_port(ds, i) && 1687 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1688 all_user_ports_removed = false; 1689 break; 1690 } 1691 } 1692 1693 /* CPU port also does the same thing until all user ports belonging to 1694 * the CPU port get out of VLAN filtering mode. 1695 */ 1696 if (all_user_ports_removed) { 1697 mutex_lock(&priv->reg_mutex); 1698 mt7530_setup_vlan0(priv); 1699 mutex_unlock(&priv->reg_mutex); 1700 } 1701 } 1702 1703 static void 1704 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1705 { 1706 struct mt7530_priv *priv = ds->priv; 1707 1708 /* Trapped into security mode allows packet forwarding through VLAN 1709 * table lookup. 1710 */ 1711 if (dsa_is_user_port(ds, port)) { 1712 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1713 MT7530_PORT_SECURITY_MODE); 1714 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1715 G0_PORT_VID(priv->ports[port].pvid)); 1716 1717 /* Only accept tagged frames if PVID is not set */ 1718 if (!priv->ports[port].pvid) 1719 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1720 MT7530_VLAN_ACC_TAGGED); 1721 1722 /* Set the port as a user port which is to be able to recognize 1723 * VID from incoming packets before fetching entry within the 1724 * VLAN table. 1725 */ 1726 mt7530_rmw(priv, MT7530_PVC_P(port), 1727 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1728 VLAN_ATTR(MT7530_VLAN_USER) | 1729 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1730 } else { 1731 /* Also set CPU ports to the "user" VLAN port attribute, to 1732 * allow VLAN classification, but keep the EG_TAG attribute as 1733 * "consistent" (i.o.w. don't change its value) for packets 1734 * received by the switch from the CPU, so that tagged packets 1735 * are forwarded to user ports as tagged, and untagged as 1736 * untagged. 1737 */ 1738 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1739 VLAN_ATTR(MT7530_VLAN_USER)); 1740 } 1741 } 1742 1743 static void 1744 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1745 struct dsa_bridge bridge) 1746 { 1747 struct mt7530_priv *priv = ds->priv; 1748 1749 mutex_lock(&priv->reg_mutex); 1750 1751 mt7530_update_port_member(priv, port, bridge.dev, false); 1752 1753 /* When a port is removed from the bridge, the port would be set up 1754 * back to the default as is at initial boot which is a VLAN-unaware 1755 * port. 1756 */ 1757 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1758 MT7530_PORT_MATRIX_MODE); 1759 1760 mutex_unlock(&priv->reg_mutex); 1761 } 1762 1763 static int 1764 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1765 const unsigned char *addr, u16 vid, 1766 struct dsa_db db) 1767 { 1768 struct mt7530_priv *priv = ds->priv; 1769 int ret; 1770 u8 port_mask = BIT(port); 1771 1772 mutex_lock(&priv->reg_mutex); 1773 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1774 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1775 mutex_unlock(&priv->reg_mutex); 1776 1777 return ret; 1778 } 1779 1780 static int 1781 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1782 const unsigned char *addr, u16 vid, 1783 struct dsa_db db) 1784 { 1785 struct mt7530_priv *priv = ds->priv; 1786 int ret; 1787 u8 port_mask = BIT(port); 1788 1789 mutex_lock(&priv->reg_mutex); 1790 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1791 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1792 mutex_unlock(&priv->reg_mutex); 1793 1794 return ret; 1795 } 1796 1797 static int 1798 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1799 dsa_fdb_dump_cb_t *cb, void *data) 1800 { 1801 struct mt7530_priv *priv = ds->priv; 1802 struct mt7530_fdb _fdb = { 0 }; 1803 int cnt = MT7530_NUM_FDB_RECORDS; 1804 int ret = 0; 1805 u32 rsp = 0; 1806 1807 mutex_lock(&priv->reg_mutex); 1808 1809 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1810 if (ret < 0) 1811 goto err; 1812 1813 do { 1814 if (rsp & ATC_SRCH_HIT) { 1815 mt7530_fdb_read(priv, &_fdb); 1816 if (_fdb.port_mask & BIT(port)) { 1817 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1818 data); 1819 if (ret < 0) 1820 break; 1821 } 1822 } 1823 } while (--cnt && 1824 !(rsp & ATC_SRCH_END) && 1825 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1826 err: 1827 mutex_unlock(&priv->reg_mutex); 1828 1829 return 0; 1830 } 1831 1832 static int 1833 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1834 const struct switchdev_obj_port_mdb *mdb, 1835 struct dsa_db db) 1836 { 1837 struct mt7530_priv *priv = ds->priv; 1838 const u8 *addr = mdb->addr; 1839 u16 vid = mdb->vid; 1840 u8 port_mask = 0; 1841 int ret; 1842 1843 mutex_lock(&priv->reg_mutex); 1844 1845 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1846 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1847 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1848 & PORT_MAP_MASK; 1849 1850 port_mask |= BIT(port); 1851 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1852 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1853 1854 mutex_unlock(&priv->reg_mutex); 1855 1856 return ret; 1857 } 1858 1859 static int 1860 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1861 const struct switchdev_obj_port_mdb *mdb, 1862 struct dsa_db db) 1863 { 1864 struct mt7530_priv *priv = ds->priv; 1865 const u8 *addr = mdb->addr; 1866 u16 vid = mdb->vid; 1867 u8 port_mask = 0; 1868 int ret; 1869 1870 mutex_lock(&priv->reg_mutex); 1871 1872 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1873 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1874 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1875 & PORT_MAP_MASK; 1876 1877 port_mask &= ~BIT(port); 1878 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1879 port_mask ? STATIC_ENT : STATIC_EMP); 1880 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1881 1882 mutex_unlock(&priv->reg_mutex); 1883 1884 return ret; 1885 } 1886 1887 static int 1888 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1889 struct netlink_ext_ack *extack) 1890 { 1891 struct dsa_port *dp = dsa_to_port(ds, port); 1892 struct dsa_port *cpu_dp = dp->cpu_dp; 1893 1894 if (vlan_filtering) { 1895 /* The port is being kept as VLAN-unaware port when bridge is 1896 * set up with vlan_filtering not being set, Otherwise, the 1897 * port and the corresponding CPU port is required the setup 1898 * for becoming a VLAN-aware port. 1899 */ 1900 mt7530_port_set_vlan_aware(ds, port); 1901 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1902 } else { 1903 mt7530_port_set_vlan_unaware(ds, port); 1904 } 1905 1906 return 0; 1907 } 1908 1909 static void 1910 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1911 struct mt7530_hw_vlan_entry *entry) 1912 { 1913 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1914 u8 new_members; 1915 u32 val; 1916 1917 new_members = entry->old_members | BIT(entry->port); 1918 1919 /* Validate the entry with independent learning, create egress tag per 1920 * VLAN and joining the port as one of the port members. 1921 */ 1922 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1923 VLAN_VALID; 1924 mt7530_write(priv, MT7530_VAWD1, val); 1925 1926 /* Decide whether adding tag or not for those outgoing packets from the 1927 * port inside the VLAN. 1928 * CPU port is always taken as a tagged port for serving more than one 1929 * VLANs across and also being applied with egress type stack mode for 1930 * that VLAN tags would be appended after hardware special tag used as 1931 * DSA tag. 1932 */ 1933 if (dsa_port_is_cpu(dp)) 1934 val = MT7530_VLAN_EGRESS_STACK; 1935 else if (entry->untagged) 1936 val = MT7530_VLAN_EGRESS_UNTAG; 1937 else 1938 val = MT7530_VLAN_EGRESS_TAG; 1939 mt7530_rmw(priv, MT7530_VAWD2, 1940 ETAG_CTRL_P_MASK(entry->port), 1941 ETAG_CTRL_P(entry->port, val)); 1942 } 1943 1944 static void 1945 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1946 struct mt7530_hw_vlan_entry *entry) 1947 { 1948 u8 new_members; 1949 u32 val; 1950 1951 new_members = entry->old_members & ~BIT(entry->port); 1952 1953 val = mt7530_read(priv, MT7530_VAWD1); 1954 if (!(val & VLAN_VALID)) { 1955 dev_err(priv->dev, 1956 "Cannot be deleted due to invalid entry\n"); 1957 return; 1958 } 1959 1960 if (new_members) { 1961 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1962 VLAN_VALID; 1963 mt7530_write(priv, MT7530_VAWD1, val); 1964 } else { 1965 mt7530_write(priv, MT7530_VAWD1, 0); 1966 mt7530_write(priv, MT7530_VAWD2, 0); 1967 } 1968 } 1969 1970 static void 1971 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1972 struct mt7530_hw_vlan_entry *entry, 1973 mt7530_vlan_op vlan_op) 1974 { 1975 u32 val; 1976 1977 /* Fetch entry */ 1978 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1979 1980 val = mt7530_read(priv, MT7530_VAWD1); 1981 1982 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1983 1984 /* Manipulate entry */ 1985 vlan_op(priv, entry); 1986 1987 /* Flush result to hardware */ 1988 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1989 } 1990 1991 static int 1992 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1993 const struct switchdev_obj_port_vlan *vlan, 1994 struct netlink_ext_ack *extack) 1995 { 1996 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1997 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1998 struct mt7530_hw_vlan_entry new_entry; 1999 struct mt7530_priv *priv = ds->priv; 2000 2001 mutex_lock(&priv->reg_mutex); 2002 2003 /* VID 0 is managed exclusively by mt7530_setup_vlan0() for 2004 * VLAN-unaware bridge operation. Don't let the bridge overwrite 2005 * its EG_CON flag with VTAG_EN and corrupt PORT_MEM. 2006 */ 2007 if (vlan->vid == 0) 2008 goto skip_vlan_table; 2009 2010 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 2011 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 2012 2013 skip_vlan_table: 2014 2015 if (pvid) { 2016 priv->ports[port].pvid = vlan->vid; 2017 2018 /* Accept all frames if PVID is set */ 2019 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 2020 MT7530_VLAN_ACC_ALL); 2021 2022 /* Only configure PVID if VLAN filtering is enabled */ 2023 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 2024 mt7530_rmw(priv, MT7530_PPBV1_P(port), 2025 G0_PORT_VID_MASK, 2026 G0_PORT_VID(vlan->vid)); 2027 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 2028 /* This VLAN is overwritten without PVID, so unset it */ 2029 priv->ports[port].pvid = G0_PORT_VID_DEF; 2030 2031 /* Only accept tagged frames if the port is VLAN-aware */ 2032 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 2033 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 2034 MT7530_VLAN_ACC_TAGGED); 2035 2036 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 2037 G0_PORT_VID_DEF); 2038 } 2039 2040 mutex_unlock(&priv->reg_mutex); 2041 2042 return 0; 2043 } 2044 2045 static int 2046 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 2047 const struct switchdev_obj_port_vlan *vlan) 2048 { 2049 struct mt7530_hw_vlan_entry target_entry; 2050 struct mt7530_priv *priv = ds->priv; 2051 2052 mutex_lock(&priv->reg_mutex); 2053 2054 /* VID 0 is managed exclusively by mt7530_setup_vlan0(). */ 2055 if (vlan->vid == 0) 2056 goto skip_vlan_table; 2057 2058 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 2059 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 2060 mt7530_hw_vlan_del); 2061 2062 skip_vlan_table: 2063 /* PVID is being restored to the default whenever the PVID port 2064 * is being removed from the VLAN. 2065 */ 2066 if (priv->ports[port].pvid == vlan->vid) { 2067 priv->ports[port].pvid = G0_PORT_VID_DEF; 2068 2069 /* Only accept tagged frames if the port is VLAN-aware */ 2070 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 2071 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 2072 MT7530_VLAN_ACC_TAGGED); 2073 2074 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 2075 G0_PORT_VID_DEF); 2076 } 2077 2078 2079 mutex_unlock(&priv->reg_mutex); 2080 2081 return 0; 2082 } 2083 2084 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 2085 struct dsa_mall_mirror_tc_entry *mirror, 2086 bool ingress, struct netlink_ext_ack *extack) 2087 { 2088 struct mt7530_priv *priv = ds->priv; 2089 int monitor_port; 2090 u32 val; 2091 2092 /* Check for existent entry */ 2093 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 2094 return -EEXIST; 2095 2096 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 2097 2098 /* MT7530 only supports one monitor port */ 2099 monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val); 2100 if (val & MT753X_MIRROR_EN(priv->id) && 2101 monitor_port != mirror->to_local_port) 2102 return -EEXIST; 2103 2104 val |= MT753X_MIRROR_EN(priv->id); 2105 val &= ~MT753X_MIRROR_PORT_MASK(priv->id); 2106 val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port); 2107 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 2108 2109 val = mt7530_read(priv, MT7530_PCR_P(port)); 2110 if (ingress) { 2111 val |= PORT_RX_MIR; 2112 priv->mirror_rx |= BIT(port); 2113 } else { 2114 val |= PORT_TX_MIR; 2115 priv->mirror_tx |= BIT(port); 2116 } 2117 mt7530_write(priv, MT7530_PCR_P(port), val); 2118 2119 return 0; 2120 } 2121 2122 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 2123 struct dsa_mall_mirror_tc_entry *mirror) 2124 { 2125 struct mt7530_priv *priv = ds->priv; 2126 u32 val; 2127 2128 val = mt7530_read(priv, MT7530_PCR_P(port)); 2129 if (mirror->ingress) { 2130 val &= ~PORT_RX_MIR; 2131 priv->mirror_rx &= ~BIT(port); 2132 } else { 2133 val &= ~PORT_TX_MIR; 2134 priv->mirror_tx &= ~BIT(port); 2135 } 2136 mt7530_write(priv, MT7530_PCR_P(port), val); 2137 2138 if (!priv->mirror_rx && !priv->mirror_tx) { 2139 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 2140 val &= ~MT753X_MIRROR_EN(priv->id); 2141 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 2142 } 2143 } 2144 2145 static enum dsa_tag_protocol 2146 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 2147 enum dsa_tag_protocol mp) 2148 { 2149 return DSA_TAG_PROTO_MTK; 2150 } 2151 2152 #ifdef CONFIG_GPIOLIB 2153 static inline u32 2154 mt7530_gpio_to_bit(unsigned int offset) 2155 { 2156 /* Map GPIO offset to register bit 2157 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 2158 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 2159 * [10: 8] port 2 LED 0..2 as GPIO 6..8 2160 * [14:12] port 3 LED 0..2 as GPIO 9..11 2161 * [18:16] port 4 LED 0..2 as GPIO 12..14 2162 */ 2163 return BIT(offset + offset / 3); 2164 } 2165 2166 static int 2167 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 2168 { 2169 struct mt7530_priv *priv = gpiochip_get_data(gc); 2170 u32 bit = mt7530_gpio_to_bit(offset); 2171 2172 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 2173 } 2174 2175 static int 2176 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 2177 { 2178 struct mt7530_priv *priv = gpiochip_get_data(gc); 2179 u32 bit = mt7530_gpio_to_bit(offset); 2180 2181 if (value) 2182 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 2183 else 2184 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 2185 2186 return 0; 2187 } 2188 2189 static int 2190 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 2191 { 2192 struct mt7530_priv *priv = gpiochip_get_data(gc); 2193 u32 bit = mt7530_gpio_to_bit(offset); 2194 2195 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 2196 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 2197 } 2198 2199 static int 2200 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 2201 { 2202 struct mt7530_priv *priv = gpiochip_get_data(gc); 2203 u32 bit = mt7530_gpio_to_bit(offset); 2204 2205 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 2206 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 2207 2208 return 0; 2209 } 2210 2211 static int 2212 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 2213 { 2214 struct mt7530_priv *priv = gpiochip_get_data(gc); 2215 u32 bit = mt7530_gpio_to_bit(offset); 2216 2217 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 2218 2219 if (value) 2220 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 2221 else 2222 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 2223 2224 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 2225 2226 return 0; 2227 } 2228 2229 static int 2230 mt7530_setup_gpio(struct mt7530_priv *priv) 2231 { 2232 struct device *dev = priv->dev; 2233 struct gpio_chip *gc; 2234 2235 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 2236 if (!gc) 2237 return -ENOMEM; 2238 2239 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 2240 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 2241 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 2242 2243 gc->label = "mt7530"; 2244 gc->parent = dev; 2245 gc->owner = THIS_MODULE; 2246 gc->get_direction = mt7530_gpio_get_direction; 2247 gc->direction_input = mt7530_gpio_direction_input; 2248 gc->direction_output = mt7530_gpio_direction_output; 2249 gc->get = mt7530_gpio_get; 2250 gc->set = mt7530_gpio_set; 2251 gc->base = -1; 2252 gc->ngpio = 15; 2253 gc->can_sleep = true; 2254 2255 return devm_gpiochip_add_data(dev, gc, priv); 2256 } 2257 #endif /* CONFIG_GPIOLIB */ 2258 2259 static void 2260 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 2261 { 2262 struct dsa_switch *ds = priv->ds; 2263 int p; 2264 2265 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2266 if (BIT(p) & ds->phys_mii_mask) { 2267 unsigned int irq; 2268 2269 irq = irq_create_mapping(priv->irq_domain, p); 2270 ds->user_mii_bus->irq[p] = irq; 2271 } 2272 } 2273 } 2274 2275 static const struct regmap_irq mt7530_irqs[] = { 2276 REGMAP_IRQ_REG_LINE(0, 32), /* PHY0_LC */ 2277 REGMAP_IRQ_REG_LINE(1, 32), /* PHY1_LC */ 2278 REGMAP_IRQ_REG_LINE(2, 32), /* PHY2_LC */ 2279 REGMAP_IRQ_REG_LINE(3, 32), /* PHY3_LC */ 2280 REGMAP_IRQ_REG_LINE(4, 32), /* PHY4_LC */ 2281 REGMAP_IRQ_REG_LINE(5, 32), /* PHY5_LC */ 2282 REGMAP_IRQ_REG_LINE(6, 32), /* PHY6_LC */ 2283 REGMAP_IRQ_REG_LINE(16, 32), /* MAC_PC */ 2284 REGMAP_IRQ_REG_LINE(17, 32), /* BMU */ 2285 REGMAP_IRQ_REG_LINE(18, 32), /* MIB */ 2286 REGMAP_IRQ_REG_LINE(22, 32), /* ARL_COL_FULL_COL */ 2287 REGMAP_IRQ_REG_LINE(23, 32), /* ARL_COL_FULL */ 2288 REGMAP_IRQ_REG_LINE(24, 32), /* ARL_TBL_ERR */ 2289 REGMAP_IRQ_REG_LINE(25, 32), /* ARL_PKT_QERR */ 2290 REGMAP_IRQ_REG_LINE(26, 32), /* ARL_EQ_ERR */ 2291 REGMAP_IRQ_REG_LINE(27, 32), /* ARL_PKT_BC */ 2292 REGMAP_IRQ_REG_LINE(28, 32), /* ARL_SEC_IG1X */ 2293 REGMAP_IRQ_REG_LINE(29, 32), /* ARL_SEC_VLAN */ 2294 REGMAP_IRQ_REG_LINE(30, 32), /* ARL_SEC_TAG */ 2295 REGMAP_IRQ_REG_LINE(31, 32), /* ACL */ 2296 }; 2297 2298 static const struct regmap_irq_chip mt7530_regmap_irq_chip = { 2299 .name = KBUILD_MODNAME, 2300 .status_base = MT7530_SYS_INT_STS, 2301 .unmask_base = MT7530_SYS_INT_EN, 2302 .ack_base = MT7530_SYS_INT_STS, 2303 .init_ack_masked = true, 2304 .irqs = mt7530_irqs, 2305 .num_irqs = ARRAY_SIZE(mt7530_irqs), 2306 .num_regs = 1, 2307 }; 2308 2309 static int 2310 mt7530_setup_irq(struct mt7530_priv *priv) 2311 { 2312 struct regmap_irq_chip_data *irq_data; 2313 struct device *dev = priv->dev; 2314 struct device_node *np = dev->of_node; 2315 int irq, ret; 2316 2317 if (!of_property_read_bool(np, "interrupt-controller")) { 2318 dev_info(dev, "no interrupt support\n"); 2319 return 0; 2320 } 2321 2322 irq = of_irq_get(np, 0); 2323 if (irq <= 0) { 2324 dev_err(dev, "failed to get parent IRQ: %d\n", irq); 2325 return irq ? : -EINVAL; 2326 } 2327 2328 /* This register must be set for MT7530 to properly fire interrupts */ 2329 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) 2330 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2331 2332 ret = devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(dev), 2333 priv->regmap, irq, 2334 IRQF_ONESHOT, 2335 0, &mt7530_regmap_irq_chip, 2336 &irq_data); 2337 if (ret) 2338 return ret; 2339 2340 priv->irq_domain = regmap_irq_get_domain(irq_data); 2341 2342 return 0; 2343 } 2344 2345 static void 2346 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2347 { 2348 int p; 2349 2350 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2351 if (BIT(p) & priv->ds->phys_mii_mask) { 2352 unsigned int irq; 2353 2354 irq = irq_find_mapping(priv->irq_domain, p); 2355 irq_dispose_mapping(irq); 2356 } 2357 } 2358 } 2359 2360 static int 2361 mt7530_setup_mdio(struct mt7530_priv *priv) 2362 { 2363 struct device_node *mnp, *np = priv->dev->of_node; 2364 struct dsa_switch *ds = priv->ds; 2365 struct device *dev = priv->dev; 2366 struct mii_bus *bus; 2367 static int idx; 2368 int ret = 0; 2369 2370 mnp = of_get_child_by_name(np, "mdio"); 2371 2372 if (mnp && !of_device_is_available(mnp)) 2373 goto out; 2374 2375 bus = devm_mdiobus_alloc(dev); 2376 if (!bus) { 2377 ret = -ENOMEM; 2378 goto out; 2379 } 2380 2381 if (!mnp) 2382 ds->user_mii_bus = bus; 2383 2384 bus->priv = priv; 2385 bus->name = KBUILD_MODNAME "-mii"; 2386 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2387 bus->read = mt753x_phy_read_c22; 2388 bus->write = mt753x_phy_write_c22; 2389 bus->read_c45 = mt753x_phy_read_c45; 2390 bus->write_c45 = mt753x_phy_write_c45; 2391 bus->parent = dev; 2392 bus->phy_mask = ~ds->phys_mii_mask; 2393 2394 if (priv->irq_domain && !mnp) 2395 mt7530_setup_mdio_irq(priv); 2396 2397 ret = devm_of_mdiobus_register(dev, bus, mnp); 2398 if (ret) { 2399 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2400 if (priv->irq_domain && !mnp) 2401 mt7530_free_mdio_irq(priv); 2402 } 2403 2404 out: 2405 of_node_put(mnp); 2406 return ret; 2407 } 2408 2409 static int 2410 mt7530_setup(struct dsa_switch *ds) 2411 { 2412 struct mt7530_priv *priv = ds->priv; 2413 struct device_node *dn = NULL; 2414 struct device_node *phy_node; 2415 struct device_node *mac_np; 2416 struct mt7530_dummy_poll p; 2417 phy_interface_t interface; 2418 struct dsa_port *cpu_dp; 2419 u32 id, val; 2420 int ret, i; 2421 2422 /* The parent node of conduit netdev which holds the common system 2423 * controller also is the container for two GMACs nodes representing 2424 * as two netdev instances. 2425 */ 2426 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2427 dn = cpu_dp->conduit->dev.of_node->parent; 2428 /* It doesn't matter which CPU port is found first, 2429 * their conduits should share the same parent OF node 2430 */ 2431 break; 2432 } 2433 2434 if (!dn) { 2435 dev_err(ds->dev, "parent OF node of DSA conduit not found"); 2436 return -EINVAL; 2437 } 2438 2439 ds->assisted_learning_on_cpu_port = true; 2440 ds->untag_vlan_aware_bridge_pvid = true; 2441 ds->mtu_enforcement_ingress = true; 2442 ds->ageing_time_min = 2 * 1000; 2443 ds->ageing_time_max = (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1) * 1000; 2444 2445 if (priv->id == ID_MT7530) { 2446 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2447 ret = regulator_enable(priv->core_pwr); 2448 if (ret < 0) { 2449 dev_err(priv->dev, 2450 "Failed to enable core power: %d\n", ret); 2451 return ret; 2452 } 2453 2454 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2455 ret = regulator_enable(priv->io_pwr); 2456 if (ret < 0) { 2457 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2458 ret); 2459 return ret; 2460 } 2461 } 2462 2463 /* Reset whole chip through gpio pin or memory-mapped registers for 2464 * different type of hardware 2465 */ 2466 if (priv->mcm) { 2467 reset_control_assert(priv->rstc); 2468 usleep_range(5000, 5100); 2469 reset_control_deassert(priv->rstc); 2470 } else { 2471 gpiod_set_value_cansleep(priv->reset, 0); 2472 usleep_range(5000, 5100); 2473 gpiod_set_value_cansleep(priv->reset, 1); 2474 } 2475 2476 /* Waiting for MT7530 got to stable */ 2477 INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); 2478 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2479 20, 1000000); 2480 if (ret < 0) { 2481 dev_err(priv->dev, "reset timeout\n"); 2482 return ret; 2483 } 2484 2485 id = mt7530_read(priv, MT7530_CREV); 2486 id >>= CHIP_NAME_SHIFT; 2487 if (id != MT7530_ID) { 2488 dev_err(priv->dev, "chip %x can't be supported\n", id); 2489 return -ENODEV; 2490 } 2491 2492 if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) { 2493 dev_err(priv->dev, 2494 "MT7530 with a 20MHz XTAL is not supported!\n"); 2495 return -EINVAL; 2496 } 2497 2498 /* Reset the switch through internal reset */ 2499 mt7530_write(priv, MT7530_SYS_CTRL, 2500 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2501 SYS_CTRL_REG_RST); 2502 2503 /* Lower Tx driving for TRGMII path */ 2504 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2505 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 2506 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2507 2508 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2509 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 2510 RD_TAP_MASK, RD_TAP(16)); 2511 2512 /* Allow modifying the trap and directly access PHY registers via the 2513 * MDIO bus the switch is on. 2514 */ 2515 mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP | 2516 MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP); 2517 2518 if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ) 2519 mt7530_pll_setup(priv); 2520 2521 mt753x_trap_frames(priv); 2522 2523 /* Enable and reset MIB counters */ 2524 mt7530_mib_reset(ds); 2525 2526 for (i = 0; i < priv->ds->num_ports; i++) { 2527 /* Clear link settings and enable force mode to force link down 2528 * on all ports until they're enabled later. 2529 */ 2530 mt7530_rmw(priv, MT753X_PMCR_P(i), 2531 PMCR_LINK_SETTINGS_MASK | 2532 MT753X_FORCE_MODE(priv->id), 2533 MT753X_FORCE_MODE(priv->id)); 2534 2535 /* Disable forwarding by default on all ports */ 2536 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2537 PCR_MATRIX_CLR); 2538 2539 /* Disable learning by default on all ports */ 2540 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2541 2542 if (dsa_is_cpu_port(ds, i)) { 2543 mt753x_cpu_port_enable(ds, i); 2544 } else { 2545 mt7530_port_disable(ds, i); 2546 2547 /* Set default PVID to 0 on all user ports */ 2548 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2549 G0_PORT_VID_DEF); 2550 } 2551 /* Enable consistent egress tag */ 2552 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2553 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2554 } 2555 2556 /* Allow mirroring frames received on the local port (monitor port). */ 2557 mt7530_set(priv, MT753X_AGC, LOCAL_EN); 2558 2559 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2560 ret = mt7530_setup_vlan0(priv); 2561 if (ret) 2562 return ret; 2563 2564 /* Check for PHY muxing on port 5 */ 2565 if (dsa_is_unused_port(ds, 5)) { 2566 /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. 2567 * Set priv->p5_mode to the appropriate value if PHY muxing is 2568 * detected. 2569 */ 2570 for_each_child_of_node(dn, mac_np) { 2571 if (!of_device_is_compatible(mac_np, 2572 "mediatek,eth-mac")) 2573 continue; 2574 2575 ret = of_property_read_u32(mac_np, "reg", &id); 2576 if (ret < 0 || id != 1) 2577 continue; 2578 2579 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2580 if (!phy_node) 2581 continue; 2582 2583 if (phy_node->parent == priv->dev->of_node->parent || 2584 phy_node->parent->parent == priv->dev->of_node) { 2585 ret = of_get_phy_mode(mac_np, &interface); 2586 if (ret && ret != -ENODEV) { 2587 of_node_put(mac_np); 2588 of_node_put(phy_node); 2589 return ret; 2590 } 2591 id = of_mdio_parse_addr(ds->dev, phy_node); 2592 if (id == 0) 2593 priv->p5_mode = MUX_PHY_P0; 2594 if (id == 4) 2595 priv->p5_mode = MUX_PHY_P4; 2596 } 2597 of_node_put(mac_np); 2598 of_node_put(phy_node); 2599 break; 2600 } 2601 2602 if (priv->p5_mode == MUX_PHY_P0 || 2603 priv->p5_mode == MUX_PHY_P4) { 2604 mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); 2605 mt7530_setup_port5(ds, interface); 2606 } 2607 } 2608 2609 #ifdef CONFIG_GPIOLIB 2610 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2611 ret = mt7530_setup_gpio(priv); 2612 if (ret) 2613 return ret; 2614 } 2615 #endif /* CONFIG_GPIOLIB */ 2616 2617 /* Flush the FDB table */ 2618 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2619 if (ret < 0) 2620 return ret; 2621 2622 return 0; 2623 } 2624 2625 static int 2626 mt7531_setup_common(struct dsa_switch *ds) 2627 { 2628 struct mt7530_priv *priv = ds->priv; 2629 int ret, i; 2630 2631 ds->assisted_learning_on_cpu_port = true; 2632 ds->untag_vlan_aware_bridge_pvid = true; 2633 ds->mtu_enforcement_ingress = true; 2634 ds->ageing_time_min = 2 * 1000; 2635 ds->ageing_time_max = (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1) * 1000; 2636 2637 mt753x_trap_frames(priv); 2638 2639 /* Enable and reset MIB counters */ 2640 mt7530_mib_reset(ds); 2641 2642 /* Disable flooding on all ports */ 2643 mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK | 2644 UNU_FFP_MASK); 2645 2646 for (i = 0; i < priv->ds->num_ports; i++) { 2647 /* Clear link settings and enable force mode to force link down 2648 * on all ports until they're enabled later. 2649 */ 2650 mt7530_rmw(priv, MT753X_PMCR_P(i), 2651 PMCR_LINK_SETTINGS_MASK | 2652 MT753X_FORCE_MODE(priv->id), 2653 MT753X_FORCE_MODE(priv->id)); 2654 2655 /* Disable forwarding by default on all ports */ 2656 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2657 PCR_MATRIX_CLR); 2658 2659 /* Disable learning by default on all ports */ 2660 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2661 2662 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2663 2664 if (dsa_is_cpu_port(ds, i)) { 2665 mt753x_cpu_port_enable(ds, i); 2666 } else { 2667 mt7530_port_disable(ds, i); 2668 2669 /* Set default PVID to 0 on all user ports */ 2670 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2671 G0_PORT_VID_DEF); 2672 } 2673 2674 /* Enable consistent egress tag */ 2675 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2676 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2677 } 2678 2679 /* Allow mirroring frames received on the local port (monitor port). */ 2680 mt7530_set(priv, MT753X_AGC, LOCAL_EN); 2681 2682 /* Enable Special Tag for rx frames */ 2683 if (priv->id == ID_EN7581 || priv->id == ID_AN7583) 2684 mt7530_write(priv, MT753X_CPORT_SPTAG_CFG, 2685 CPORT_SW2FE_STAG_EN | CPORT_FE2SW_STAG_EN); 2686 2687 /* Flush the FDB table */ 2688 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2689 if (ret < 0) 2690 return ret; 2691 2692 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2693 return mt7530_setup_vlan0(priv); 2694 } 2695 2696 static int 2697 mt7531_setup(struct dsa_switch *ds) 2698 { 2699 struct mt7530_priv *priv = ds->priv; 2700 struct mt7530_dummy_poll p; 2701 u32 val, id; 2702 int ret, i; 2703 2704 /* Reset whole chip through gpio pin or memory-mapped registers for 2705 * different type of hardware 2706 */ 2707 if (priv->mcm) { 2708 reset_control_assert(priv->rstc); 2709 usleep_range(5000, 5100); 2710 reset_control_deassert(priv->rstc); 2711 } else { 2712 gpiod_set_value_cansleep(priv->reset, 0); 2713 usleep_range(5000, 5100); 2714 gpiod_set_value_cansleep(priv->reset, 1); 2715 } 2716 2717 /* Waiting for MT7530 got to stable */ 2718 INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); 2719 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2720 20, 1000000); 2721 if (ret < 0) { 2722 dev_err(priv->dev, "reset timeout\n"); 2723 return ret; 2724 } 2725 2726 id = mt7530_read(priv, MT7531_CREV); 2727 id >>= CHIP_NAME_SHIFT; 2728 2729 if (id != MT7531_ID) { 2730 dev_err(priv->dev, "chip %x can't be supported\n", id); 2731 return -ENODEV; 2732 } 2733 2734 /* MT7531AE has got two SGMII units. One for port 5, one for port 6. 2735 * MT7531BE has got only one SGMII unit which is for port 6. 2736 */ 2737 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 2738 priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); 2739 2740 /* Force link down on all ports before internal reset */ 2741 for (i = 0; i < priv->ds->num_ports; i++) 2742 mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK); 2743 2744 /* Reset the switch through internal reset */ 2745 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); 2746 2747 if (!priv->p5_sgmii) { 2748 mt7531_pll_setup(priv); 2749 } else { 2750 /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on 2751 * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO 2752 * to expose the MDIO bus of the switch. 2753 */ 2754 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2755 MT7531_EXT_P_MDC_11); 2756 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2757 MT7531_EXT_P_MDIO_12); 2758 } 2759 2760 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2761 MT7531_GPIO0_INTERRUPT); 2762 2763 /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since 2764 * phy_device has not yet been created provided for 2765 * phy_[read,write]_mmd_indirect is called, we provide our own 2766 * mt7531_ind_mmd_phy_[read,write] to complete this function. 2767 */ 2768 val = mt7531_ind_c45_phy_read(priv, 2769 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 2770 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2771 val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE; 2772 val &= ~MT7531_PHY_PLL_OFF; 2773 mt7531_ind_c45_phy_write(priv, 2774 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 2775 MDIO_MMD_VEND2, CORE_PLL_GROUP4, val); 2776 2777 /* Disable EEE advertisement on the switch PHYs. */ 2778 for (i = MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr); 2779 i < MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr) + MT7530_NUM_PHYS; 2780 i++) { 2781 mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 2782 0); 2783 } 2784 2785 ret = mt7531_setup_common(ds); 2786 if (ret) 2787 return ret; 2788 2789 return 0; 2790 } 2791 2792 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2793 struct phylink_config *config) 2794 { 2795 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2796 2797 switch (port) { 2798 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2799 case 0 ... 4: 2800 __set_bit(PHY_INTERFACE_MODE_GMII, 2801 config->supported_interfaces); 2802 break; 2803 2804 /* Port 5 supports rgmii with delays, mii, and gmii. */ 2805 case 5: 2806 phy_interface_set_rgmii(config->supported_interfaces); 2807 __set_bit(PHY_INTERFACE_MODE_MII, 2808 config->supported_interfaces); 2809 __set_bit(PHY_INTERFACE_MODE_GMII, 2810 config->supported_interfaces); 2811 break; 2812 2813 /* Port 6 supports rgmii and trgmii. */ 2814 case 6: 2815 __set_bit(PHY_INTERFACE_MODE_RGMII, 2816 config->supported_interfaces); 2817 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2818 config->supported_interfaces); 2819 break; 2820 } 2821 } 2822 2823 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2824 struct phylink_config *config) 2825 { 2826 struct mt7530_priv *priv = ds->priv; 2827 2828 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2829 2830 switch (port) { 2831 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2832 case 0 ... 4: 2833 __set_bit(PHY_INTERFACE_MODE_GMII, 2834 config->supported_interfaces); 2835 break; 2836 2837 /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on 2838 * MT7531AE. 2839 */ 2840 case 5: 2841 if (!priv->p5_sgmii) { 2842 phy_interface_set_rgmii(config->supported_interfaces); 2843 break; 2844 } 2845 fallthrough; 2846 2847 /* Port 6 supports sgmii/802.3z. */ 2848 case 6: 2849 __set_bit(PHY_INTERFACE_MODE_SGMII, 2850 config->supported_interfaces); 2851 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2852 config->supported_interfaces); 2853 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2854 config->supported_interfaces); 2855 2856 config->mac_capabilities |= MAC_2500FD; 2857 break; 2858 } 2859 } 2860 2861 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, 2862 struct phylink_config *config) 2863 { 2864 switch (port) { 2865 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2866 case 0 ... 3: 2867 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2868 config->supported_interfaces); 2869 2870 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2871 break; 2872 2873 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2874 case 6: 2875 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2876 config->supported_interfaces); 2877 2878 config->mac_capabilities |= MAC_10000FD; 2879 break; 2880 } 2881 } 2882 2883 static void en7581_mac_port_get_caps(struct dsa_switch *ds, int port, 2884 struct phylink_config *config) 2885 { 2886 switch (port) { 2887 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2888 case 0 ... 4: 2889 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2890 config->supported_interfaces); 2891 2892 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2893 break; 2894 2895 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2896 case 6: 2897 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2898 config->supported_interfaces); 2899 2900 config->mac_capabilities |= MAC_10000FD; 2901 break; 2902 } 2903 } 2904 2905 static void 2906 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2907 phy_interface_t interface) 2908 { 2909 struct mt7530_priv *priv = ds->priv; 2910 2911 if (port == 5) 2912 mt7530_setup_port5(priv->ds, interface); 2913 else if (port == 6) 2914 mt7530_setup_port6(priv->ds, interface); 2915 } 2916 2917 static void mt7531_rgmii_setup(struct mt7530_priv *priv, 2918 phy_interface_t interface, 2919 struct phy_device *phydev) 2920 { 2921 u32 val; 2922 2923 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2924 val |= GP_CLK_EN; 2925 val &= ~GP_MODE_MASK; 2926 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2927 val &= ~CLK_SKEW_IN_MASK; 2928 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2929 val &= ~CLK_SKEW_OUT_MASK; 2930 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2931 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2932 2933 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2934 if (!phydev || phy_driver_is_genphy(phydev)) { 2935 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2936 switch (interface) { 2937 case PHY_INTERFACE_MODE_RGMII: 2938 val |= TXCLK_NO_REVERSE; 2939 val |= RXCLK_NO_DELAY; 2940 break; 2941 case PHY_INTERFACE_MODE_RGMII_RXID: 2942 val |= TXCLK_NO_REVERSE; 2943 break; 2944 case PHY_INTERFACE_MODE_RGMII_TXID: 2945 val |= RXCLK_NO_DELAY; 2946 break; 2947 case PHY_INTERFACE_MODE_RGMII_ID: 2948 break; 2949 default: 2950 break; 2951 } 2952 } 2953 2954 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2955 } 2956 2957 static void 2958 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2959 phy_interface_t interface) 2960 { 2961 struct mt7530_priv *priv = ds->priv; 2962 struct phy_device *phydev; 2963 struct dsa_port *dp; 2964 2965 if (phy_interface_mode_is_rgmii(interface)) { 2966 dp = dsa_to_port(ds, port); 2967 phydev = dp->user->phydev; 2968 mt7531_rgmii_setup(priv, interface, phydev); 2969 } 2970 } 2971 2972 static struct phylink_pcs * 2973 mt753x_phylink_mac_select_pcs(struct phylink_config *config, 2974 phy_interface_t interface) 2975 { 2976 struct dsa_port *dp = dsa_phylink_to_port(config); 2977 struct mt7530_priv *priv = dp->ds->priv; 2978 2979 switch (interface) { 2980 case PHY_INTERFACE_MODE_TRGMII: 2981 return &priv->pcs[dp->index].pcs; 2982 case PHY_INTERFACE_MODE_SGMII: 2983 case PHY_INTERFACE_MODE_1000BASEX: 2984 case PHY_INTERFACE_MODE_2500BASEX: 2985 return priv->ports[dp->index].sgmii_pcs; 2986 default: 2987 return NULL; 2988 } 2989 } 2990 2991 static void 2992 mt753x_phylink_mac_config(struct phylink_config *config, unsigned int mode, 2993 const struct phylink_link_state *state) 2994 { 2995 struct dsa_port *dp = dsa_phylink_to_port(config); 2996 struct dsa_switch *ds = dp->ds; 2997 struct mt7530_priv *priv; 2998 int port = dp->index; 2999 3000 priv = ds->priv; 3001 3002 if ((port == 5 || port == 6) && priv->info->mac_port_config) 3003 priv->info->mac_port_config(ds, port, mode, state->interface); 3004 3005 /* Are we connected to external phy */ 3006 if (port == 5 && dsa_is_user_port(ds, 5)) 3007 mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY); 3008 } 3009 3010 static void mt753x_phylink_mac_link_down(struct phylink_config *config, 3011 unsigned int mode, 3012 phy_interface_t interface) 3013 { 3014 struct dsa_port *dp = dsa_phylink_to_port(config); 3015 struct mt7530_priv *priv = dp->ds->priv; 3016 3017 mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); 3018 } 3019 3020 static void mt753x_phylink_mac_link_up(struct phylink_config *config, 3021 struct phy_device *phydev, 3022 unsigned int mode, 3023 phy_interface_t interface, 3024 int speed, int duplex, 3025 bool tx_pause, bool rx_pause) 3026 { 3027 struct dsa_port *dp = dsa_phylink_to_port(config); 3028 struct mt7530_priv *priv = dp->ds->priv; 3029 u32 mcr; 3030 3031 mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK; 3032 3033 switch (speed) { 3034 case SPEED_1000: 3035 case SPEED_2500: 3036 case SPEED_10000: 3037 mcr |= PMCR_FORCE_SPEED_1000; 3038 break; 3039 case SPEED_100: 3040 mcr |= PMCR_FORCE_SPEED_100; 3041 break; 3042 } 3043 if (duplex == DUPLEX_FULL) { 3044 mcr |= PMCR_FORCE_FDX; 3045 if (tx_pause) 3046 mcr |= PMCR_FORCE_TX_FC_EN; 3047 if (rx_pause) 3048 mcr |= PMCR_FORCE_RX_FC_EN; 3049 } 3050 3051 mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr); 3052 } 3053 3054 static void mt753x_phylink_mac_disable_tx_lpi(struct phylink_config *config) 3055 { 3056 struct dsa_port *dp = dsa_phylink_to_port(config); 3057 struct mt7530_priv *priv = dp->ds->priv; 3058 3059 mt7530_clear(priv, MT753X_PMCR_P(dp->index), 3060 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100); 3061 } 3062 3063 static int mt753x_phylink_mac_enable_tx_lpi(struct phylink_config *config, 3064 u32 timer, bool tx_clock_stop) 3065 { 3066 struct dsa_port *dp = dsa_phylink_to_port(config); 3067 struct mt7530_priv *priv = dp->ds->priv; 3068 u32 val; 3069 3070 /* If the timer is zero, then set LPI_MODE_EN, which allows the 3071 * system to enter LPI mode immediately rather than waiting for 3072 * the LPI threshold. 3073 */ 3074 if (!timer) 3075 val = LPI_MODE_EN; 3076 else if (FIELD_FIT(LPI_THRESH_MASK, timer)) 3077 val = FIELD_PREP(LPI_THRESH_MASK, timer); 3078 else 3079 val = LPI_THRESH_MASK; 3080 3081 mt7530_rmw(priv, MT753X_PMEEECR_P(dp->index), 3082 LPI_THRESH_MASK | LPI_MODE_EN, val); 3083 3084 mt7530_set(priv, MT753X_PMCR_P(dp->index), 3085 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100); 3086 3087 return 0; 3088 } 3089 3090 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 3091 struct phylink_config *config) 3092 { 3093 struct mt7530_priv *priv = ds->priv; 3094 u32 eeecr; 3095 3096 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE; 3097 3098 config->lpi_capabilities = MAC_100FD | MAC_1000FD | MAC_2500FD; 3099 3100 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port)); 3101 /* tx_lpi_timer should be in microseconds. The time units for 3102 * LPI threshold are unspecified. 3103 */ 3104 config->lpi_timer_default = FIELD_GET(LPI_THRESH_MASK, eeecr); 3105 3106 priv->info->mac_port_get_caps(ds, port, config); 3107 } 3108 3109 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 3110 unsigned long *supported, 3111 const struct phylink_link_state *state) 3112 { 3113 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 3114 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 3115 phy_interface_mode_is_8023z(state->interface)) 3116 phylink_clear(supported, Autoneg); 3117 3118 return 0; 3119 } 3120 3121 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, 3122 struct phylink_link_state *state) 3123 { 3124 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 3125 int port = pcs_to_mt753x_pcs(pcs)->port; 3126 u32 pmsr; 3127 3128 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 3129 3130 state->link = (pmsr & PMSR_LINK); 3131 state->an_complete = state->link; 3132 state->duplex = !!(pmsr & PMSR_DPX); 3133 3134 switch (pmsr & PMSR_SPEED_MASK) { 3135 case PMSR_SPEED_10: 3136 state->speed = SPEED_10; 3137 break; 3138 case PMSR_SPEED_100: 3139 state->speed = SPEED_100; 3140 break; 3141 case PMSR_SPEED_1000: 3142 state->speed = SPEED_1000; 3143 break; 3144 default: 3145 state->speed = SPEED_UNKNOWN; 3146 break; 3147 } 3148 3149 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 3150 if (pmsr & PMSR_RX_FC) 3151 state->pause |= MLO_PAUSE_RX; 3152 if (pmsr & PMSR_TX_FC) 3153 state->pause |= MLO_PAUSE_TX; 3154 } 3155 3156 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 3157 phy_interface_t interface, 3158 const unsigned long *advertising, 3159 bool permit_pause_to_mac) 3160 { 3161 return 0; 3162 } 3163 3164 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 3165 { 3166 } 3167 3168 static const struct phylink_pcs_ops mt7530_pcs_ops = { 3169 .pcs_validate = mt753x_pcs_validate, 3170 .pcs_get_state = mt7530_pcs_get_state, 3171 .pcs_config = mt753x_pcs_config, 3172 .pcs_an_restart = mt7530_pcs_an_restart, 3173 }; 3174 3175 static int 3176 mt753x_setup(struct dsa_switch *ds) 3177 { 3178 struct mt7530_priv *priv = ds->priv; 3179 int ret = priv->info->sw_setup(ds); 3180 int i; 3181 3182 if (ret) 3183 return ret; 3184 3185 ret = mt7530_setup_irq(priv); 3186 if (ret) 3187 return ret; 3188 3189 ret = mt7530_setup_mdio(priv); 3190 if (ret) 3191 return ret; 3192 3193 /* Initialise the PCS devices */ 3194 for (i = 0; i < priv->ds->num_ports; i++) { 3195 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3196 priv->pcs[i].priv = priv; 3197 priv->pcs[i].port = i; 3198 } 3199 3200 if (priv->create_sgmii) 3201 ret = priv->create_sgmii(priv); 3202 3203 if (ret && priv->irq_domain) 3204 mt7530_free_mdio_irq(priv); 3205 3206 if (!ret && priv->bus) { 3207 mt7530_stats_refresh(priv); 3208 schedule_delayed_work(&priv->stats_work, 3209 MT7530_STATS_POLL_INTERVAL); 3210 } 3211 3212 return ret; 3213 } 3214 3215 static void 3216 mt753x_teardown(struct dsa_switch *ds) 3217 { 3218 struct mt7530_priv *priv = ds->priv; 3219 3220 if (priv->bus) 3221 cancel_delayed_work_sync(&priv->stats_work); 3222 } 3223 3224 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3225 struct ethtool_keee *e) 3226 { 3227 if (e->tx_lpi_timer > 0xFFF) 3228 return -EINVAL; 3229 3230 return 0; 3231 } 3232 3233 static void 3234 mt753x_conduit_state_change(struct dsa_switch *ds, 3235 const struct net_device *conduit, 3236 bool operational) 3237 { 3238 struct dsa_port *cpu_dp = conduit->dsa_ptr; 3239 struct mt7530_priv *priv = ds->priv; 3240 int val = 0; 3241 u8 mask; 3242 3243 /* Set the CPU port to trap frames to for MT7530. Trapped frames will be 3244 * forwarded to the numerically smallest CPU port whose conduit 3245 * interface is up. 3246 */ 3247 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 3248 return; 3249 3250 mask = BIT(cpu_dp->index); 3251 3252 if (operational) 3253 priv->active_cpu_ports |= mask; 3254 else 3255 priv->active_cpu_ports &= ~mask; 3256 3257 if (priv->active_cpu_ports) { 3258 val = MT7530_CPU_EN | 3259 MT7530_CPU_PORT(__ffs(priv->active_cpu_ports)); 3260 } 3261 3262 mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val); 3263 } 3264 3265 static int mt753x_tc_setup_qdisc_tbf(struct dsa_switch *ds, int port, 3266 struct tc_tbf_qopt_offload *qopt) 3267 { 3268 struct tc_tbf_qopt_offload_replace_params *p = &qopt->replace_params; 3269 struct mt7530_priv *priv = ds->priv; 3270 u32 rate = 0; 3271 3272 switch (qopt->command) { 3273 case TC_TBF_REPLACE: 3274 rate = div_u64(p->rate.rate_bytes_ps, 1000) << 3; /* kbps */ 3275 fallthrough; 3276 case TC_TBF_DESTROY: { 3277 u32 val, tick; 3278 3279 mt7530_rmw(priv, MT753X_GERLCR, EGR_BC_MASK, 3280 EGR_BC_CRC_IPG_PREAMBLE); 3281 3282 /* if rate is greater than 10Mbps tick is 1/32 ms, 3283 * 1ms otherwise 3284 */ 3285 tick = rate > 10000 ? 2 : 7; 3286 val = FIELD_PREP(ERLCR_CIR_MASK, (rate >> 5)) | 3287 FIELD_PREP(ERLCR_EN_MASK, !!rate) | 3288 FIELD_PREP(ERLCR_EXP_MASK, tick) | 3289 ERLCR_TBF_MODE_MASK | 3290 FIELD_PREP(ERLCR_MANT_MASK, 0xf); 3291 mt7530_write(priv, MT753X_ERLCR_P(port), val); 3292 break; 3293 } 3294 default: 3295 return -EOPNOTSUPP; 3296 } 3297 3298 return 0; 3299 } 3300 3301 static int mt753x_setup_tc(struct dsa_switch *ds, int port, 3302 enum tc_setup_type type, void *type_data) 3303 { 3304 switch (type) { 3305 case TC_SETUP_QDISC_TBF: 3306 return mt753x_tc_setup_qdisc_tbf(ds, port, type_data); 3307 default: 3308 return -EOPNOTSUPP; 3309 } 3310 } 3311 3312 static int mt7988_setup(struct dsa_switch *ds) 3313 { 3314 struct mt7530_priv *priv = ds->priv; 3315 3316 /* Reset the switch */ 3317 reset_control_assert(priv->rstc); 3318 usleep_range(20, 50); 3319 reset_control_deassert(priv->rstc); 3320 usleep_range(20, 50); 3321 3322 /* AN7583 require additional tweak to CONN_CFG */ 3323 if (priv->id == ID_AN7583) 3324 mt7530_rmw(priv, AN7583_GEPHY_CONN_CFG, 3325 AN7583_CSR_DPHY_CKIN_SEL | 3326 AN7583_CSR_PHY_CORE_REG_CLK_SEL | 3327 AN7583_CSR_ETHER_AFE_PWD, 3328 AN7583_CSR_DPHY_CKIN_SEL | 3329 AN7583_CSR_PHY_CORE_REG_CLK_SEL | 3330 FIELD_PREP(AN7583_CSR_ETHER_AFE_PWD, 0)); 3331 3332 /* Reset the switch PHYs */ 3333 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST); 3334 3335 return mt7531_setup_common(ds); 3336 } 3337 3338 static const struct dsa_switch_ops mt7530_switch_ops = { 3339 .get_tag_protocol = mtk_get_tag_protocol, 3340 .setup = mt753x_setup, 3341 .teardown = mt753x_teardown, 3342 .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, 3343 .get_strings = mt7530_get_strings, 3344 .get_ethtool_stats = mt7530_get_ethtool_stats, 3345 .get_sset_count = mt7530_get_sset_count, 3346 .get_eth_mac_stats = mt7530_get_eth_mac_stats, 3347 .get_rmon_stats = mt7530_get_rmon_stats, 3348 .get_eth_ctrl_stats = mt7530_get_eth_ctrl_stats, 3349 .get_stats64 = mt7530_get_stats64, 3350 .set_ageing_time = mt7530_set_ageing_time, 3351 .port_enable = mt7530_port_enable, 3352 .port_disable = mt7530_port_disable, 3353 .port_change_mtu = mt7530_port_change_mtu, 3354 .port_max_mtu = mt7530_port_max_mtu, 3355 .port_stp_state_set = mt7530_stp_state_set, 3356 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3357 .port_bridge_flags = mt7530_port_bridge_flags, 3358 .port_bridge_join = mt7530_port_bridge_join, 3359 .port_bridge_leave = mt7530_port_bridge_leave, 3360 .port_fdb_add = mt7530_port_fdb_add, 3361 .port_fdb_del = mt7530_port_fdb_del, 3362 .port_fdb_dump = mt7530_port_fdb_dump, 3363 .port_mdb_add = mt7530_port_mdb_add, 3364 .port_mdb_del = mt7530_port_mdb_del, 3365 .port_vlan_filtering = mt7530_port_vlan_filtering, 3366 .port_vlan_add = mt7530_port_vlan_add, 3367 .port_vlan_del = mt7530_port_vlan_del, 3368 .port_mirror_add = mt753x_port_mirror_add, 3369 .port_mirror_del = mt753x_port_mirror_del, 3370 .phylink_get_caps = mt753x_phylink_get_caps, 3371 .support_eee = dsa_supports_eee, 3372 .set_mac_eee = mt753x_set_mac_eee, 3373 .conduit_state_change = mt753x_conduit_state_change, 3374 .port_setup_tc = mt753x_setup_tc, 3375 .port_hsr_join = dsa_port_simple_hsr_join, 3376 .port_hsr_leave = dsa_port_simple_hsr_leave, 3377 }; 3378 3379 static const struct phylink_mac_ops mt753x_phylink_mac_ops = { 3380 .mac_select_pcs = mt753x_phylink_mac_select_pcs, 3381 .mac_config = mt753x_phylink_mac_config, 3382 .mac_link_down = mt753x_phylink_mac_link_down, 3383 .mac_link_up = mt753x_phylink_mac_link_up, 3384 .mac_disable_tx_lpi = mt753x_phylink_mac_disable_tx_lpi, 3385 .mac_enable_tx_lpi = mt753x_phylink_mac_enable_tx_lpi, 3386 }; 3387 3388 const struct mt753x_info mt753x_table[] = { 3389 [ID_MT7621] = { 3390 .id = ID_MT7621, 3391 .pcs_ops = &mt7530_pcs_ops, 3392 .sw_setup = mt7530_setup, 3393 .phy_read_c22 = mt7530_phy_read_c22, 3394 .phy_write_c22 = mt7530_phy_write_c22, 3395 .phy_read_c45 = mt7530_phy_read_c45, 3396 .phy_write_c45 = mt7530_phy_write_c45, 3397 .mac_port_get_caps = mt7530_mac_port_get_caps, 3398 .mac_port_config = mt7530_mac_config, 3399 }, 3400 [ID_MT7530] = { 3401 .id = ID_MT7530, 3402 .pcs_ops = &mt7530_pcs_ops, 3403 .sw_setup = mt7530_setup, 3404 .phy_read_c22 = mt7530_phy_read_c22, 3405 .phy_write_c22 = mt7530_phy_write_c22, 3406 .phy_read_c45 = mt7530_phy_read_c45, 3407 .phy_write_c45 = mt7530_phy_write_c45, 3408 .mac_port_get_caps = mt7530_mac_port_get_caps, 3409 .mac_port_config = mt7530_mac_config, 3410 }, 3411 [ID_MT7531] = { 3412 .id = ID_MT7531, 3413 .pcs_ops = &mt7530_pcs_ops, 3414 .sw_setup = mt7531_setup, 3415 .phy_read_c22 = mt7531_ind_c22_phy_read, 3416 .phy_write_c22 = mt7531_ind_c22_phy_write, 3417 .phy_read_c45 = mt7531_ind_c45_phy_read, 3418 .phy_write_c45 = mt7531_ind_c45_phy_write, 3419 .mac_port_get_caps = mt7531_mac_port_get_caps, 3420 .mac_port_config = mt7531_mac_config, 3421 }, 3422 [ID_MT7988] = { 3423 .id = ID_MT7988, 3424 .pcs_ops = &mt7530_pcs_ops, 3425 .sw_setup = mt7988_setup, 3426 .phy_read_c22 = mt7531_ind_c22_phy_read, 3427 .phy_write_c22 = mt7531_ind_c22_phy_write, 3428 .phy_read_c45 = mt7531_ind_c45_phy_read, 3429 .phy_write_c45 = mt7531_ind_c45_phy_write, 3430 .mac_port_get_caps = mt7988_mac_port_get_caps, 3431 }, 3432 [ID_EN7581] = { 3433 .id = ID_EN7581, 3434 .pcs_ops = &mt7530_pcs_ops, 3435 .sw_setup = mt7988_setup, 3436 .phy_read_c22 = mt7531_ind_c22_phy_read, 3437 .phy_write_c22 = mt7531_ind_c22_phy_write, 3438 .phy_read_c45 = mt7531_ind_c45_phy_read, 3439 .phy_write_c45 = mt7531_ind_c45_phy_write, 3440 .mac_port_get_caps = en7581_mac_port_get_caps, 3441 }, 3442 [ID_AN7583] = { 3443 .id = ID_AN7583, 3444 .pcs_ops = &mt7530_pcs_ops, 3445 .sw_setup = mt7988_setup, 3446 .phy_read_c22 = mt7531_ind_c22_phy_read, 3447 .phy_write_c22 = mt7531_ind_c22_phy_write, 3448 .phy_read_c45 = mt7531_ind_c45_phy_read, 3449 .phy_write_c45 = mt7531_ind_c45_phy_write, 3450 .mac_port_get_caps = en7581_mac_port_get_caps, 3451 }, 3452 }; 3453 EXPORT_SYMBOL_GPL(mt753x_table); 3454 3455 int 3456 mt7530_probe_common(struct mt7530_priv *priv) 3457 { 3458 struct device *dev = priv->dev; 3459 3460 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 3461 if (!priv->ds) 3462 return -ENOMEM; 3463 3464 priv->ds->dev = dev; 3465 priv->ds->num_ports = MT7530_NUM_PORTS; 3466 3467 /* Get the hardware identifier from the devicetree node. 3468 * We will need it for some of the clock and regulator setup. 3469 */ 3470 priv->info = of_device_get_match_data(dev); 3471 if (!priv->info) 3472 return -EINVAL; 3473 3474 priv->id = priv->info->id; 3475 priv->dev = dev; 3476 priv->ds->priv = priv; 3477 priv->ds->ops = &mt7530_switch_ops; 3478 priv->ds->phylink_mac_ops = &mt753x_phylink_mac_ops; 3479 mutex_init(&priv->reg_mutex); 3480 spin_lock_init(&priv->stats_lock); 3481 INIT_DELAYED_WORK(&priv->stats_work, mt7530_stats_poll); 3482 3483 dev_set_drvdata(dev, priv); 3484 3485 return 0; 3486 } 3487 EXPORT_SYMBOL_GPL(mt7530_probe_common); 3488 3489 void 3490 mt7530_remove_common(struct mt7530_priv *priv) 3491 { 3492 if (priv->irq_domain) 3493 mt7530_free_mdio_irq(priv); 3494 3495 dsa_unregister_switch(priv->ds); 3496 3497 mutex_destroy(&priv->reg_mutex); 3498 } 3499 EXPORT_SYMBOL_GPL(mt7530_remove_common); 3500 3501 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3502 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3503 MODULE_LICENSE("GPL"); 3504