1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 28 { 29 return container_of(pcs, struct mt753x_pcs, pcs); 30 } 31 32 /* String, offset, and register size in bytes if different from 4 bytes */ 33 static const struct mt7530_mib_desc mt7530_mib[] = { 34 MIB_DESC(1, 0x00, "TxDrop"), 35 MIB_DESC(1, 0x04, "TxCrcErr"), 36 MIB_DESC(1, 0x08, "TxUnicast"), 37 MIB_DESC(1, 0x0c, "TxMulticast"), 38 MIB_DESC(1, 0x10, "TxBroadcast"), 39 MIB_DESC(1, 0x14, "TxCollision"), 40 MIB_DESC(1, 0x18, "TxSingleCollision"), 41 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 42 MIB_DESC(1, 0x20, "TxDeferred"), 43 MIB_DESC(1, 0x24, "TxLateCollision"), 44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 45 MIB_DESC(1, 0x2c, "TxPause"), 46 MIB_DESC(1, 0x30, "TxPktSz64"), 47 MIB_DESC(1, 0x34, "TxPktSz65To127"), 48 MIB_DESC(1, 0x38, "TxPktSz128To255"), 49 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 50 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 51 MIB_DESC(1, 0x44, "Tx1024ToMax"), 52 MIB_DESC(2, 0x48, "TxBytes"), 53 MIB_DESC(1, 0x60, "RxDrop"), 54 MIB_DESC(1, 0x64, "RxFiltering"), 55 MIB_DESC(1, 0x68, "RxUnicast"), 56 MIB_DESC(1, 0x6c, "RxMulticast"), 57 MIB_DESC(1, 0x70, "RxBroadcast"), 58 MIB_DESC(1, 0x74, "RxAlignErr"), 59 MIB_DESC(1, 0x78, "RxCrcErr"), 60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 61 MIB_DESC(1, 0x80, "RxFragErr"), 62 MIB_DESC(1, 0x84, "RxOverSzErr"), 63 MIB_DESC(1, 0x88, "RxJabberErr"), 64 MIB_DESC(1, 0x8c, "RxPause"), 65 MIB_DESC(1, 0x90, "RxPktSz64"), 66 MIB_DESC(1, 0x94, "RxPktSz65To127"), 67 MIB_DESC(1, 0x98, "RxPktSz128To255"), 68 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 71 MIB_DESC(2, 0xa8, "RxBytes"), 72 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 73 MIB_DESC(1, 0xb4, "RxIngressDrop"), 74 MIB_DESC(1, 0xb8, "RxArlDrop"), 75 }; 76 77 /* Since phy_device has not yet been created and 78 * phy_{read,write}_mmd_indirect is not available, we provide our own 79 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 80 * to complete this function. 81 */ 82 static int 83 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 84 { 85 struct mii_bus *bus = priv->bus; 86 int value, ret; 87 88 /* Write the desired MMD Devad */ 89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 90 if (ret < 0) 91 goto err; 92 93 /* Write the desired MMD register address */ 94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 95 if (ret < 0) 96 goto err; 97 98 /* Select the Function : DATA with no post increment */ 99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 100 if (ret < 0) 101 goto err; 102 103 /* Read the content of the MMD's selected register */ 104 value = bus->read(bus, 0, MII_MMD_DATA); 105 106 return value; 107 err: 108 dev_err(&bus->dev, "failed to read mmd register\n"); 109 110 return ret; 111 } 112 113 static int 114 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 115 int devad, u32 data) 116 { 117 struct mii_bus *bus = priv->bus; 118 int ret; 119 120 /* Write the desired MMD Devad */ 121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 122 if (ret < 0) 123 goto err; 124 125 /* Write the desired MMD register address */ 126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 127 if (ret < 0) 128 goto err; 129 130 /* Select the Function : DATA with no post increment */ 131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 132 if (ret < 0) 133 goto err; 134 135 /* Write the data into MMD's selected register */ 136 ret = bus->write(bus, 0, MII_MMD_DATA, data); 137 err: 138 if (ret < 0) 139 dev_err(&bus->dev, 140 "failed to write mmd register\n"); 141 return ret; 142 } 143 144 static void 145 mt7530_mutex_lock(struct mt7530_priv *priv) 146 { 147 if (priv->bus) 148 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 149 } 150 151 static void 152 mt7530_mutex_unlock(struct mt7530_priv *priv) 153 { 154 if (priv->bus) 155 mutex_unlock(&priv->bus->mdio_lock); 156 } 157 158 static void 159 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 160 { 161 mt7530_mutex_lock(priv); 162 163 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 164 165 mt7530_mutex_unlock(priv); 166 } 167 168 static void 169 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 170 { 171 u32 val; 172 173 mt7530_mutex_lock(priv); 174 175 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 176 val &= ~mask; 177 val |= set; 178 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 179 180 mt7530_mutex_unlock(priv); 181 } 182 183 static void 184 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 185 { 186 core_rmw(priv, reg, 0, val); 187 } 188 189 static void 190 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 191 { 192 core_rmw(priv, reg, val, 0); 193 } 194 195 static int 196 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 197 { 198 int ret; 199 200 ret = regmap_write(priv->regmap, reg, val); 201 202 if (ret < 0) 203 dev_err(priv->dev, 204 "failed to write mt7530 register\n"); 205 206 return ret; 207 } 208 209 static u32 210 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 211 { 212 int ret; 213 u32 val; 214 215 ret = regmap_read(priv->regmap, reg, &val); 216 if (ret) { 217 WARN_ON_ONCE(1); 218 dev_err(priv->dev, 219 "failed to read mt7530 register\n"); 220 return 0; 221 } 222 223 return val; 224 } 225 226 static void 227 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 228 { 229 mt7530_mutex_lock(priv); 230 231 mt7530_mii_write(priv, reg, val); 232 233 mt7530_mutex_unlock(priv); 234 } 235 236 static u32 237 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 238 { 239 return mt7530_mii_read(p->priv, p->reg); 240 } 241 242 static u32 243 _mt7530_read(struct mt7530_dummy_poll *p) 244 { 245 u32 val; 246 247 mt7530_mutex_lock(p->priv); 248 249 val = mt7530_mii_read(p->priv, p->reg); 250 251 mt7530_mutex_unlock(p->priv); 252 253 return val; 254 } 255 256 static u32 257 mt7530_read(struct mt7530_priv *priv, u32 reg) 258 { 259 struct mt7530_dummy_poll p; 260 261 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 262 return _mt7530_read(&p); 263 } 264 265 static void 266 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 267 u32 mask, u32 set) 268 { 269 mt7530_mutex_lock(priv); 270 271 regmap_update_bits(priv->regmap, reg, mask, set); 272 273 mt7530_mutex_unlock(priv); 274 } 275 276 static void 277 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 278 { 279 mt7530_rmw(priv, reg, val, val); 280 } 281 282 static void 283 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 284 { 285 mt7530_rmw(priv, reg, val, 0); 286 } 287 288 static int 289 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 290 { 291 u32 val; 292 int ret; 293 struct mt7530_dummy_poll p; 294 295 /* Set the command operating upon the MAC address entries */ 296 val = ATC_BUSY | ATC_MAT(0) | cmd; 297 mt7530_write(priv, MT7530_ATC, val); 298 299 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 300 ret = readx_poll_timeout(_mt7530_read, &p, val, 301 !(val & ATC_BUSY), 20, 20000); 302 if (ret < 0) { 303 dev_err(priv->dev, "reset timeout\n"); 304 return ret; 305 } 306 307 /* Additional sanity for read command if the specified 308 * entry is invalid 309 */ 310 val = mt7530_read(priv, MT7530_ATC); 311 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 312 return -EINVAL; 313 314 if (rsp) 315 *rsp = val; 316 317 return 0; 318 } 319 320 static void 321 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 322 { 323 u32 reg[3]; 324 int i; 325 326 /* Read from ARL table into an array */ 327 for (i = 0; i < 3; i++) { 328 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 329 330 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 331 __func__, __LINE__, i, reg[i]); 332 } 333 334 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 335 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 336 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 337 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 338 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 339 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 340 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 341 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 342 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 343 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 344 } 345 346 static void 347 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 348 u8 port_mask, const u8 *mac, 349 u8 aging, u8 type) 350 { 351 u32 reg[3] = { 0 }; 352 int i; 353 354 reg[1] |= vid & CVID_MASK; 355 reg[1] |= ATA2_IVL; 356 reg[1] |= ATA2_FID(FID_BRIDGED); 357 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 358 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 359 /* STATIC_ENT indicate that entry is static wouldn't 360 * be aged out and STATIC_EMP specified as erasing an 361 * entry 362 */ 363 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 364 reg[1] |= mac[5] << MAC_BYTE_5; 365 reg[1] |= mac[4] << MAC_BYTE_4; 366 reg[0] |= mac[3] << MAC_BYTE_3; 367 reg[0] |= mac[2] << MAC_BYTE_2; 368 reg[0] |= mac[1] << MAC_BYTE_1; 369 reg[0] |= mac[0] << MAC_BYTE_0; 370 371 /* Write array into the ARL table */ 372 for (i = 0; i < 3; i++) 373 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 374 } 375 376 /* Set up switch core clock for MT7530 */ 377 static void mt7530_pll_setup(struct mt7530_priv *priv) 378 { 379 /* Disable core clock */ 380 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 381 382 /* Disable PLL */ 383 core_write(priv, CORE_GSWPLL_GRP1, 0); 384 385 /* Set core clock into 500Mhz */ 386 core_write(priv, CORE_GSWPLL_GRP2, 387 RG_GSWPLL_POSDIV_500M(1) | 388 RG_GSWPLL_FBKDIV_500M(25)); 389 390 /* Enable PLL */ 391 core_write(priv, CORE_GSWPLL_GRP1, 392 RG_GSWPLL_EN_PRE | 393 RG_GSWPLL_POSDIV_200M(2) | 394 RG_GSWPLL_FBKDIV_200M(32)); 395 396 udelay(20); 397 398 /* Enable core clock */ 399 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 400 } 401 402 /* If port 6 is available as a CPU port, always prefer that as the default, 403 * otherwise don't care. 404 */ 405 static struct dsa_port * 406 mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) 407 { 408 struct dsa_port *cpu_dp = dsa_to_port(ds, 6); 409 410 if (dsa_port_is_cpu(cpu_dp)) 411 return cpu_dp; 412 413 return NULL; 414 } 415 416 /* Setup port 6 interface mode and TRGMII TX circuit */ 417 static int 418 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 419 { 420 struct mt7530_priv *priv = ds->priv; 421 u32 ncpo1, ssc_delta, trgint, xtal; 422 423 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 424 425 if (xtal == HWTRAP_XTAL_20MHZ) { 426 dev_err(priv->dev, 427 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 428 __func__); 429 return -EINVAL; 430 } 431 432 switch (interface) { 433 case PHY_INTERFACE_MODE_RGMII: 434 trgint = 0; 435 break; 436 case PHY_INTERFACE_MODE_TRGMII: 437 trgint = 1; 438 if (xtal == HWTRAP_XTAL_25MHZ) 439 ssc_delta = 0x57; 440 else 441 ssc_delta = 0x87; 442 if (priv->id == ID_MT7621) { 443 /* PLL frequency: 125MHz: 1.0GBit */ 444 if (xtal == HWTRAP_XTAL_40MHZ) 445 ncpo1 = 0x0640; 446 if (xtal == HWTRAP_XTAL_25MHZ) 447 ncpo1 = 0x0a00; 448 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 449 if (xtal == HWTRAP_XTAL_40MHZ) 450 ncpo1 = 0x0c80; 451 if (xtal == HWTRAP_XTAL_25MHZ) 452 ncpo1 = 0x1400; 453 } 454 break; 455 default: 456 dev_err(priv->dev, "xMII interface %d not supported\n", 457 interface); 458 return -EINVAL; 459 } 460 461 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 462 P6_INTF_MODE(trgint)); 463 464 if (trgint) { 465 /* Disable the MT7530 TRGMII clocks */ 466 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 467 468 /* Setup the MT7530 TRGMII Tx Clock */ 469 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 470 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 471 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 472 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 473 core_write(priv, CORE_PLL_GROUP4, 474 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 475 RG_SYSPLL_BIAS_LPF_EN); 476 core_write(priv, CORE_PLL_GROUP2, 477 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 478 RG_SYSPLL_POSDIV(1)); 479 core_write(priv, CORE_PLL_GROUP7, 480 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 481 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 482 483 /* Enable the MT7530 TRGMII clocks */ 484 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 485 } 486 487 return 0; 488 } 489 490 static int 491 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 492 { 493 return 0; 494 } 495 496 static void 497 mt7531_pll_setup(struct mt7530_priv *priv) 498 { 499 u32 top_sig; 500 u32 hwstrap; 501 u32 xtal; 502 u32 val; 503 504 val = mt7530_read(priv, MT7531_CREV); 505 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 506 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 507 if ((val & CHIP_REV_M) > 0) 508 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 509 HWTRAP_XTAL_FSEL_25MHZ; 510 else 511 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 512 513 /* Step 1 : Disable MT7531 COREPLL */ 514 val = mt7530_read(priv, MT7531_PLLGP_EN); 515 val &= ~EN_COREPLL; 516 mt7530_write(priv, MT7531_PLLGP_EN, val); 517 518 /* Step 2: switch to XTAL output */ 519 val = mt7530_read(priv, MT7531_PLLGP_EN); 520 val |= SW_CLKSW; 521 mt7530_write(priv, MT7531_PLLGP_EN, val); 522 523 val = mt7530_read(priv, MT7531_PLLGP_CR0); 524 val &= ~RG_COREPLL_EN; 525 mt7530_write(priv, MT7531_PLLGP_CR0, val); 526 527 /* Step 3: disable PLLGP and enable program PLLGP */ 528 val = mt7530_read(priv, MT7531_PLLGP_EN); 529 val |= SW_PLLGP; 530 mt7530_write(priv, MT7531_PLLGP_EN, val); 531 532 /* Step 4: program COREPLL output frequency to 500MHz */ 533 val = mt7530_read(priv, MT7531_PLLGP_CR0); 534 val &= ~RG_COREPLL_POSDIV_M; 535 val |= 2 << RG_COREPLL_POSDIV_S; 536 mt7530_write(priv, MT7531_PLLGP_CR0, val); 537 usleep_range(25, 35); 538 539 switch (xtal) { 540 case HWTRAP_XTAL_FSEL_25MHZ: 541 val = mt7530_read(priv, MT7531_PLLGP_CR0); 542 val &= ~RG_COREPLL_SDM_PCW_M; 543 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 544 mt7530_write(priv, MT7531_PLLGP_CR0, val); 545 break; 546 case HWTRAP_XTAL_FSEL_40MHZ: 547 val = mt7530_read(priv, MT7531_PLLGP_CR0); 548 val &= ~RG_COREPLL_SDM_PCW_M; 549 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 550 mt7530_write(priv, MT7531_PLLGP_CR0, val); 551 break; 552 } 553 554 /* Set feedback divide ratio update signal to high */ 555 val = mt7530_read(priv, MT7531_PLLGP_CR0); 556 val |= RG_COREPLL_SDM_PCW_CHG; 557 mt7530_write(priv, MT7531_PLLGP_CR0, val); 558 /* Wait for at least 16 XTAL clocks */ 559 usleep_range(10, 20); 560 561 /* Step 5: set feedback divide ratio update signal to low */ 562 val = mt7530_read(priv, MT7531_PLLGP_CR0); 563 val &= ~RG_COREPLL_SDM_PCW_CHG; 564 mt7530_write(priv, MT7531_PLLGP_CR0, val); 565 566 /* Enable 325M clock for SGMII */ 567 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 568 569 /* Enable 250SSC clock for RGMII */ 570 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 571 572 /* Step 6: Enable MT7531 PLL */ 573 val = mt7530_read(priv, MT7531_PLLGP_CR0); 574 val |= RG_COREPLL_EN; 575 mt7530_write(priv, MT7531_PLLGP_CR0, val); 576 577 val = mt7530_read(priv, MT7531_PLLGP_EN); 578 val |= EN_COREPLL; 579 mt7530_write(priv, MT7531_PLLGP_EN, val); 580 usleep_range(25, 35); 581 } 582 583 static void 584 mt7530_mib_reset(struct dsa_switch *ds) 585 { 586 struct mt7530_priv *priv = ds->priv; 587 588 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 589 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 590 } 591 592 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 593 { 594 return mdiobus_read_nested(priv->bus, port, regnum); 595 } 596 597 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 598 u16 val) 599 { 600 return mdiobus_write_nested(priv->bus, port, regnum, val); 601 } 602 603 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 604 int devad, int regnum) 605 { 606 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 607 } 608 609 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 610 int regnum, u16 val) 611 { 612 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 613 } 614 615 static int 616 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 617 int regnum) 618 { 619 struct mt7530_dummy_poll p; 620 u32 reg, val; 621 int ret; 622 623 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 624 625 mt7530_mutex_lock(priv); 626 627 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 628 !(val & MT7531_PHY_ACS_ST), 20, 100000); 629 if (ret < 0) { 630 dev_err(priv->dev, "poll timeout\n"); 631 goto out; 632 } 633 634 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 635 MT7531_MDIO_DEV_ADDR(devad) | regnum; 636 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 637 638 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 639 !(val & MT7531_PHY_ACS_ST), 20, 100000); 640 if (ret < 0) { 641 dev_err(priv->dev, "poll timeout\n"); 642 goto out; 643 } 644 645 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 646 MT7531_MDIO_DEV_ADDR(devad); 647 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 648 649 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 650 !(val & MT7531_PHY_ACS_ST), 20, 100000); 651 if (ret < 0) { 652 dev_err(priv->dev, "poll timeout\n"); 653 goto out; 654 } 655 656 ret = val & MT7531_MDIO_RW_DATA_MASK; 657 out: 658 mt7530_mutex_unlock(priv); 659 660 return ret; 661 } 662 663 static int 664 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 665 int regnum, u16 data) 666 { 667 struct mt7530_dummy_poll p; 668 u32 val, reg; 669 int ret; 670 671 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 672 673 mt7530_mutex_lock(priv); 674 675 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 676 !(val & MT7531_PHY_ACS_ST), 20, 100000); 677 if (ret < 0) { 678 dev_err(priv->dev, "poll timeout\n"); 679 goto out; 680 } 681 682 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 683 MT7531_MDIO_DEV_ADDR(devad) | regnum; 684 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 685 686 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 687 !(val & MT7531_PHY_ACS_ST), 20, 100000); 688 if (ret < 0) { 689 dev_err(priv->dev, "poll timeout\n"); 690 goto out; 691 } 692 693 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 694 MT7531_MDIO_DEV_ADDR(devad) | data; 695 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 696 697 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 698 !(val & MT7531_PHY_ACS_ST), 20, 100000); 699 if (ret < 0) { 700 dev_err(priv->dev, "poll timeout\n"); 701 goto out; 702 } 703 704 out: 705 mt7530_mutex_unlock(priv); 706 707 return ret; 708 } 709 710 static int 711 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 712 { 713 struct mt7530_dummy_poll p; 714 int ret; 715 u32 val; 716 717 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 718 719 mt7530_mutex_lock(priv); 720 721 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 722 !(val & MT7531_PHY_ACS_ST), 20, 100000); 723 if (ret < 0) { 724 dev_err(priv->dev, "poll timeout\n"); 725 goto out; 726 } 727 728 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 729 MT7531_MDIO_REG_ADDR(regnum); 730 731 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 732 733 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 734 !(val & MT7531_PHY_ACS_ST), 20, 100000); 735 if (ret < 0) { 736 dev_err(priv->dev, "poll timeout\n"); 737 goto out; 738 } 739 740 ret = val & MT7531_MDIO_RW_DATA_MASK; 741 out: 742 mt7530_mutex_unlock(priv); 743 744 return ret; 745 } 746 747 static int 748 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 749 u16 data) 750 { 751 struct mt7530_dummy_poll p; 752 int ret; 753 u32 reg; 754 755 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 756 757 mt7530_mutex_lock(priv); 758 759 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 760 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 761 if (ret < 0) { 762 dev_err(priv->dev, "poll timeout\n"); 763 goto out; 764 } 765 766 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 767 MT7531_MDIO_REG_ADDR(regnum) | data; 768 769 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 770 771 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 772 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 773 if (ret < 0) { 774 dev_err(priv->dev, "poll timeout\n"); 775 goto out; 776 } 777 778 out: 779 mt7530_mutex_unlock(priv); 780 781 return ret; 782 } 783 784 static int 785 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 786 { 787 struct mt7530_priv *priv = bus->priv; 788 789 return priv->info->phy_read_c22(priv, port, regnum); 790 } 791 792 static int 793 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 794 { 795 struct mt7530_priv *priv = bus->priv; 796 797 return priv->info->phy_read_c45(priv, port, devad, regnum); 798 } 799 800 static int 801 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 802 { 803 struct mt7530_priv *priv = bus->priv; 804 805 return priv->info->phy_write_c22(priv, port, regnum, val); 806 } 807 808 static int 809 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 810 u16 val) 811 { 812 struct mt7530_priv *priv = bus->priv; 813 814 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 815 } 816 817 static void 818 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 819 uint8_t *data) 820 { 821 int i; 822 823 if (stringset != ETH_SS_STATS) 824 return; 825 826 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 827 ethtool_puts(&data, mt7530_mib[i].name); 828 } 829 830 static void 831 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 832 uint64_t *data) 833 { 834 struct mt7530_priv *priv = ds->priv; 835 const struct mt7530_mib_desc *mib; 836 u32 reg, i; 837 u64 hi; 838 839 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 840 mib = &mt7530_mib[i]; 841 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 842 843 data[i] = mt7530_read(priv, reg); 844 if (mib->size == 2) { 845 hi = mt7530_read(priv, reg + 4); 846 data[i] |= hi << 32; 847 } 848 } 849 } 850 851 static int 852 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 853 { 854 if (sset != ETH_SS_STATS) 855 return 0; 856 857 return ARRAY_SIZE(mt7530_mib); 858 } 859 860 static int 861 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 862 { 863 struct mt7530_priv *priv = ds->priv; 864 unsigned int secs = msecs / 1000; 865 unsigned int tmp_age_count; 866 unsigned int error = -1; 867 unsigned int age_count; 868 unsigned int age_unit; 869 870 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 871 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 872 return -ERANGE; 873 874 /* iterate through all possible age_count to find the closest pair */ 875 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 876 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 877 878 if (tmp_age_unit <= AGE_UNIT_MAX) { 879 unsigned int tmp_error = secs - 880 (tmp_age_count + 1) * (tmp_age_unit + 1); 881 882 /* found a closer pair */ 883 if (error > tmp_error) { 884 error = tmp_error; 885 age_count = tmp_age_count; 886 age_unit = tmp_age_unit; 887 } 888 889 /* found the exact match, so break the loop */ 890 if (!error) 891 break; 892 } 893 } 894 895 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 896 897 return 0; 898 } 899 900 static const char *p5_intf_modes(unsigned int p5_interface) 901 { 902 switch (p5_interface) { 903 case P5_DISABLED: 904 return "DISABLED"; 905 case P5_INTF_SEL_PHY_P0: 906 return "PHY P0"; 907 case P5_INTF_SEL_PHY_P4: 908 return "PHY P4"; 909 case P5_INTF_SEL_GMAC5: 910 return "GMAC5"; 911 default: 912 return "unknown"; 913 } 914 } 915 916 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 917 { 918 struct mt7530_priv *priv = ds->priv; 919 u8 tx_delay = 0; 920 int val; 921 922 mutex_lock(&priv->reg_mutex); 923 924 val = mt7530_read(priv, MT7530_MHWTRAP); 925 926 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 927 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 928 929 switch (priv->p5_intf_sel) { 930 case P5_INTF_SEL_PHY_P0: 931 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 932 val |= MHWTRAP_PHY0_SEL; 933 fallthrough; 934 case P5_INTF_SEL_PHY_P4: 935 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 936 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 937 938 /* Setup the MAC by default for the cpu port */ 939 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 940 break; 941 case P5_INTF_SEL_GMAC5: 942 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 943 val &= ~MHWTRAP_P5_DIS; 944 break; 945 default: 946 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 947 priv->p5_intf_sel); 948 goto unlock_exit; 949 } 950 951 /* Setup RGMII settings */ 952 if (phy_interface_mode_is_rgmii(interface)) { 953 val |= MHWTRAP_P5_RGMII_MODE; 954 955 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 956 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 957 958 /* Don't set delay in DSA mode */ 959 if (!dsa_is_dsa_port(priv->ds, 5) && 960 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 961 interface == PHY_INTERFACE_MODE_RGMII_ID)) 962 tx_delay = 4; /* n * 0.5 ns */ 963 964 /* P5 RGMII TX Clock Control: delay x */ 965 mt7530_write(priv, MT7530_P5RGMIITXCR, 966 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 967 968 /* reduce P5 RGMII Tx driving, 8mA */ 969 mt7530_write(priv, MT7530_IO_DRV_CR, 970 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 971 } 972 973 mt7530_write(priv, MT7530_MHWTRAP, val); 974 975 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 976 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 977 978 unlock_exit: 979 mutex_unlock(&priv->reg_mutex); 980 } 981 982 static void 983 mt753x_trap_frames(struct mt7530_priv *priv) 984 { 985 /* Trap BPDUs to the CPU port(s) */ 986 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 987 MT753X_BPDU_CPU_ONLY); 988 989 /* Trap 802.1X PAE frames to the CPU port(s) */ 990 mt7530_rmw(priv, MT753X_BPC, MT753X_PAE_PORT_FW_MASK, 991 MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY)); 992 993 /* Trap LLDP frames with :0E MAC DA to the CPU port(s) */ 994 mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_PORT_FW_MASK, 995 MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY)); 996 } 997 998 static int 999 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1000 { 1001 struct mt7530_priv *priv = ds->priv; 1002 int ret; 1003 1004 /* Setup max capability of CPU port at first */ 1005 if (priv->info->cpu_port_config) { 1006 ret = priv->info->cpu_port_config(ds, port); 1007 if (ret) 1008 return ret; 1009 } 1010 1011 /* Enable Mediatek header mode on the cpu port */ 1012 mt7530_write(priv, MT7530_PVC_P(port), 1013 PORT_SPEC_TAG); 1014 1015 /* Enable flooding on the CPU port */ 1016 mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | 1017 UNU_FFP(BIT(port))); 1018 1019 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on 1020 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that 1021 * is affine to the inbound user port. 1022 */ 1023 if (priv->id == ID_MT7531 || priv->id == ID_MT7988) 1024 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); 1025 1026 /* CPU port gets connected to all user ports of 1027 * the switch. 1028 */ 1029 mt7530_write(priv, MT7530_PCR_P(port), 1030 PCR_MATRIX(dsa_user_ports(priv->ds))); 1031 1032 /* Set to fallback mode for independent VLAN learning */ 1033 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1034 MT7530_PORT_FALLBACK_MODE); 1035 1036 return 0; 1037 } 1038 1039 static int 1040 mt7530_port_enable(struct dsa_switch *ds, int port, 1041 struct phy_device *phy) 1042 { 1043 struct dsa_port *dp = dsa_to_port(ds, port); 1044 struct mt7530_priv *priv = ds->priv; 1045 1046 mutex_lock(&priv->reg_mutex); 1047 1048 /* Allow the user port gets connected to the cpu port and also 1049 * restore the port matrix if the port is the member of a certain 1050 * bridge. 1051 */ 1052 if (dsa_port_is_user(dp)) { 1053 struct dsa_port *cpu_dp = dp->cpu_dp; 1054 1055 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1056 } 1057 priv->ports[port].enable = true; 1058 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1059 priv->ports[port].pm); 1060 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1061 1062 mutex_unlock(&priv->reg_mutex); 1063 1064 return 0; 1065 } 1066 1067 static void 1068 mt7530_port_disable(struct dsa_switch *ds, int port) 1069 { 1070 struct mt7530_priv *priv = ds->priv; 1071 1072 mutex_lock(&priv->reg_mutex); 1073 1074 /* Clear up all port matrix which could be restored in the next 1075 * enablement for the port. 1076 */ 1077 priv->ports[port].enable = false; 1078 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1079 PCR_MATRIX_CLR); 1080 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1081 1082 mutex_unlock(&priv->reg_mutex); 1083 } 1084 1085 static int 1086 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1087 { 1088 struct mt7530_priv *priv = ds->priv; 1089 int length; 1090 u32 val; 1091 1092 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1093 * largest MTU of the user ports. Because the switch only has a global 1094 * RX length register, only allowing CPU port here is enough. 1095 */ 1096 if (!dsa_is_cpu_port(ds, port)) 1097 return 0; 1098 1099 mt7530_mutex_lock(priv); 1100 1101 val = mt7530_mii_read(priv, MT7530_GMACCR); 1102 val &= ~MAX_RX_PKT_LEN_MASK; 1103 1104 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1105 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1106 if (length <= 1522) { 1107 val |= MAX_RX_PKT_LEN_1522; 1108 } else if (length <= 1536) { 1109 val |= MAX_RX_PKT_LEN_1536; 1110 } else if (length <= 1552) { 1111 val |= MAX_RX_PKT_LEN_1552; 1112 } else { 1113 val &= ~MAX_RX_JUMBO_MASK; 1114 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1115 val |= MAX_RX_PKT_LEN_JUMBO; 1116 } 1117 1118 mt7530_mii_write(priv, MT7530_GMACCR, val); 1119 1120 mt7530_mutex_unlock(priv); 1121 1122 return 0; 1123 } 1124 1125 static int 1126 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1127 { 1128 return MT7530_MAX_MTU; 1129 } 1130 1131 static void 1132 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1133 { 1134 struct mt7530_priv *priv = ds->priv; 1135 u32 stp_state; 1136 1137 switch (state) { 1138 case BR_STATE_DISABLED: 1139 stp_state = MT7530_STP_DISABLED; 1140 break; 1141 case BR_STATE_BLOCKING: 1142 stp_state = MT7530_STP_BLOCKING; 1143 break; 1144 case BR_STATE_LISTENING: 1145 stp_state = MT7530_STP_LISTENING; 1146 break; 1147 case BR_STATE_LEARNING: 1148 stp_state = MT7530_STP_LEARNING; 1149 break; 1150 case BR_STATE_FORWARDING: 1151 default: 1152 stp_state = MT7530_STP_FORWARDING; 1153 break; 1154 } 1155 1156 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1157 FID_PST(FID_BRIDGED, stp_state)); 1158 } 1159 1160 static int 1161 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1162 struct switchdev_brport_flags flags, 1163 struct netlink_ext_ack *extack) 1164 { 1165 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1166 BR_BCAST_FLOOD)) 1167 return -EINVAL; 1168 1169 return 0; 1170 } 1171 1172 static int 1173 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1174 struct switchdev_brport_flags flags, 1175 struct netlink_ext_ack *extack) 1176 { 1177 struct mt7530_priv *priv = ds->priv; 1178 1179 if (flags.mask & BR_LEARNING) 1180 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1181 flags.val & BR_LEARNING ? 0 : SA_DIS); 1182 1183 if (flags.mask & BR_FLOOD) 1184 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1185 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1186 1187 if (flags.mask & BR_MCAST_FLOOD) 1188 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1189 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1190 1191 if (flags.mask & BR_BCAST_FLOOD) 1192 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1193 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1194 1195 return 0; 1196 } 1197 1198 static int 1199 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1200 struct dsa_bridge bridge, bool *tx_fwd_offload, 1201 struct netlink_ext_ack *extack) 1202 { 1203 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1204 struct dsa_port *cpu_dp = dp->cpu_dp; 1205 u32 port_bitmap = BIT(cpu_dp->index); 1206 struct mt7530_priv *priv = ds->priv; 1207 1208 mutex_lock(&priv->reg_mutex); 1209 1210 dsa_switch_for_each_user_port(other_dp, ds) { 1211 int other_port = other_dp->index; 1212 1213 if (dp == other_dp) 1214 continue; 1215 1216 /* Add this port to the port matrix of the other ports in the 1217 * same bridge. If the port is disabled, port matrix is kept 1218 * and not being setup until the port becomes enabled. 1219 */ 1220 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1221 continue; 1222 1223 if (priv->ports[other_port].enable) 1224 mt7530_set(priv, MT7530_PCR_P(other_port), 1225 PCR_MATRIX(BIT(port))); 1226 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); 1227 1228 port_bitmap |= BIT(other_port); 1229 } 1230 1231 /* Add the all other ports to this port matrix. */ 1232 if (priv->ports[port].enable) 1233 mt7530_rmw(priv, MT7530_PCR_P(port), 1234 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1235 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1236 1237 /* Set to fallback mode for independent VLAN learning */ 1238 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1239 MT7530_PORT_FALLBACK_MODE); 1240 1241 mutex_unlock(&priv->reg_mutex); 1242 1243 return 0; 1244 } 1245 1246 static void 1247 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1248 { 1249 struct mt7530_priv *priv = ds->priv; 1250 bool all_user_ports_removed = true; 1251 int i; 1252 1253 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1254 * bridge. Don't set standalone ports to fallback mode. 1255 */ 1256 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1257 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1258 MT7530_PORT_FALLBACK_MODE); 1259 1260 mt7530_rmw(priv, MT7530_PVC_P(port), 1261 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1262 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1263 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1264 MT7530_VLAN_ACC_ALL); 1265 1266 /* Set PVID to 0 */ 1267 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1268 G0_PORT_VID_DEF); 1269 1270 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1271 if (dsa_is_user_port(ds, i) && 1272 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1273 all_user_ports_removed = false; 1274 break; 1275 } 1276 } 1277 1278 /* CPU port also does the same thing until all user ports belonging to 1279 * the CPU port get out of VLAN filtering mode. 1280 */ 1281 if (all_user_ports_removed) { 1282 struct dsa_port *dp = dsa_to_port(ds, port); 1283 struct dsa_port *cpu_dp = dp->cpu_dp; 1284 1285 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1286 PCR_MATRIX(dsa_user_ports(priv->ds))); 1287 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1288 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1289 } 1290 } 1291 1292 static void 1293 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1294 { 1295 struct mt7530_priv *priv = ds->priv; 1296 1297 /* Trapped into security mode allows packet forwarding through VLAN 1298 * table lookup. 1299 */ 1300 if (dsa_is_user_port(ds, port)) { 1301 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1302 MT7530_PORT_SECURITY_MODE); 1303 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1304 G0_PORT_VID(priv->ports[port].pvid)); 1305 1306 /* Only accept tagged frames if PVID is not set */ 1307 if (!priv->ports[port].pvid) 1308 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1309 MT7530_VLAN_ACC_TAGGED); 1310 1311 /* Set the port as a user port which is to be able to recognize 1312 * VID from incoming packets before fetching entry within the 1313 * VLAN table. 1314 */ 1315 mt7530_rmw(priv, MT7530_PVC_P(port), 1316 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1317 VLAN_ATTR(MT7530_VLAN_USER) | 1318 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1319 } else { 1320 /* Also set CPU ports to the "user" VLAN port attribute, to 1321 * allow VLAN classification, but keep the EG_TAG attribute as 1322 * "consistent" (i.o.w. don't change its value) for packets 1323 * received by the switch from the CPU, so that tagged packets 1324 * are forwarded to user ports as tagged, and untagged as 1325 * untagged. 1326 */ 1327 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1328 VLAN_ATTR(MT7530_VLAN_USER)); 1329 } 1330 } 1331 1332 static void 1333 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1334 struct dsa_bridge bridge) 1335 { 1336 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1337 struct dsa_port *cpu_dp = dp->cpu_dp; 1338 struct mt7530_priv *priv = ds->priv; 1339 1340 mutex_lock(&priv->reg_mutex); 1341 1342 dsa_switch_for_each_user_port(other_dp, ds) { 1343 int other_port = other_dp->index; 1344 1345 if (dp == other_dp) 1346 continue; 1347 1348 /* Remove this port from the port matrix of the other ports 1349 * in the same bridge. If the port is disabled, port matrix 1350 * is kept and not being setup until the port becomes enabled. 1351 */ 1352 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1353 continue; 1354 1355 if (priv->ports[other_port].enable) 1356 mt7530_clear(priv, MT7530_PCR_P(other_port), 1357 PCR_MATRIX(BIT(port))); 1358 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); 1359 } 1360 1361 /* Set the cpu port to be the only one in the port matrix of 1362 * this port. 1363 */ 1364 if (priv->ports[port].enable) 1365 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1366 PCR_MATRIX(BIT(cpu_dp->index))); 1367 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); 1368 1369 /* When a port is removed from the bridge, the port would be set up 1370 * back to the default as is at initial boot which is a VLAN-unaware 1371 * port. 1372 */ 1373 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1374 MT7530_PORT_MATRIX_MODE); 1375 1376 mutex_unlock(&priv->reg_mutex); 1377 } 1378 1379 static int 1380 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1381 const unsigned char *addr, u16 vid, 1382 struct dsa_db db) 1383 { 1384 struct mt7530_priv *priv = ds->priv; 1385 int ret; 1386 u8 port_mask = BIT(port); 1387 1388 mutex_lock(&priv->reg_mutex); 1389 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1390 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1391 mutex_unlock(&priv->reg_mutex); 1392 1393 return ret; 1394 } 1395 1396 static int 1397 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1398 const unsigned char *addr, u16 vid, 1399 struct dsa_db db) 1400 { 1401 struct mt7530_priv *priv = ds->priv; 1402 int ret; 1403 u8 port_mask = BIT(port); 1404 1405 mutex_lock(&priv->reg_mutex); 1406 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1407 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1408 mutex_unlock(&priv->reg_mutex); 1409 1410 return ret; 1411 } 1412 1413 static int 1414 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1415 dsa_fdb_dump_cb_t *cb, void *data) 1416 { 1417 struct mt7530_priv *priv = ds->priv; 1418 struct mt7530_fdb _fdb = { 0 }; 1419 int cnt = MT7530_NUM_FDB_RECORDS; 1420 int ret = 0; 1421 u32 rsp = 0; 1422 1423 mutex_lock(&priv->reg_mutex); 1424 1425 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1426 if (ret < 0) 1427 goto err; 1428 1429 do { 1430 if (rsp & ATC_SRCH_HIT) { 1431 mt7530_fdb_read(priv, &_fdb); 1432 if (_fdb.port_mask & BIT(port)) { 1433 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1434 data); 1435 if (ret < 0) 1436 break; 1437 } 1438 } 1439 } while (--cnt && 1440 !(rsp & ATC_SRCH_END) && 1441 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1442 err: 1443 mutex_unlock(&priv->reg_mutex); 1444 1445 return 0; 1446 } 1447 1448 static int 1449 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1450 const struct switchdev_obj_port_mdb *mdb, 1451 struct dsa_db db) 1452 { 1453 struct mt7530_priv *priv = ds->priv; 1454 const u8 *addr = mdb->addr; 1455 u16 vid = mdb->vid; 1456 u8 port_mask = 0; 1457 int ret; 1458 1459 mutex_lock(&priv->reg_mutex); 1460 1461 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1462 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1463 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1464 & PORT_MAP_MASK; 1465 1466 port_mask |= BIT(port); 1467 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1468 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1469 1470 mutex_unlock(&priv->reg_mutex); 1471 1472 return ret; 1473 } 1474 1475 static int 1476 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1477 const struct switchdev_obj_port_mdb *mdb, 1478 struct dsa_db db) 1479 { 1480 struct mt7530_priv *priv = ds->priv; 1481 const u8 *addr = mdb->addr; 1482 u16 vid = mdb->vid; 1483 u8 port_mask = 0; 1484 int ret; 1485 1486 mutex_lock(&priv->reg_mutex); 1487 1488 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1489 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1490 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1491 & PORT_MAP_MASK; 1492 1493 port_mask &= ~BIT(port); 1494 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1495 port_mask ? STATIC_ENT : STATIC_EMP); 1496 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1497 1498 mutex_unlock(&priv->reg_mutex); 1499 1500 return ret; 1501 } 1502 1503 static int 1504 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1505 { 1506 struct mt7530_dummy_poll p; 1507 u32 val; 1508 int ret; 1509 1510 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1511 mt7530_write(priv, MT7530_VTCR, val); 1512 1513 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1514 ret = readx_poll_timeout(_mt7530_read, &p, val, 1515 !(val & VTCR_BUSY), 20, 20000); 1516 if (ret < 0) { 1517 dev_err(priv->dev, "poll timeout\n"); 1518 return ret; 1519 } 1520 1521 val = mt7530_read(priv, MT7530_VTCR); 1522 if (val & VTCR_INVALID) { 1523 dev_err(priv->dev, "read VTCR invalid\n"); 1524 return -EINVAL; 1525 } 1526 1527 return 0; 1528 } 1529 1530 static int 1531 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1532 struct netlink_ext_ack *extack) 1533 { 1534 struct dsa_port *dp = dsa_to_port(ds, port); 1535 struct dsa_port *cpu_dp = dp->cpu_dp; 1536 1537 if (vlan_filtering) { 1538 /* The port is being kept as VLAN-unaware port when bridge is 1539 * set up with vlan_filtering not being set, Otherwise, the 1540 * port and the corresponding CPU port is required the setup 1541 * for becoming a VLAN-aware port. 1542 */ 1543 mt7530_port_set_vlan_aware(ds, port); 1544 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1545 } else { 1546 mt7530_port_set_vlan_unaware(ds, port); 1547 } 1548 1549 return 0; 1550 } 1551 1552 static void 1553 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1554 struct mt7530_hw_vlan_entry *entry) 1555 { 1556 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1557 u8 new_members; 1558 u32 val; 1559 1560 new_members = entry->old_members | BIT(entry->port); 1561 1562 /* Validate the entry with independent learning, create egress tag per 1563 * VLAN and joining the port as one of the port members. 1564 */ 1565 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1566 VLAN_VALID; 1567 mt7530_write(priv, MT7530_VAWD1, val); 1568 1569 /* Decide whether adding tag or not for those outgoing packets from the 1570 * port inside the VLAN. 1571 * CPU port is always taken as a tagged port for serving more than one 1572 * VLANs across and also being applied with egress type stack mode for 1573 * that VLAN tags would be appended after hardware special tag used as 1574 * DSA tag. 1575 */ 1576 if (dsa_port_is_cpu(dp)) 1577 val = MT7530_VLAN_EGRESS_STACK; 1578 else if (entry->untagged) 1579 val = MT7530_VLAN_EGRESS_UNTAG; 1580 else 1581 val = MT7530_VLAN_EGRESS_TAG; 1582 mt7530_rmw(priv, MT7530_VAWD2, 1583 ETAG_CTRL_P_MASK(entry->port), 1584 ETAG_CTRL_P(entry->port, val)); 1585 } 1586 1587 static void 1588 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1589 struct mt7530_hw_vlan_entry *entry) 1590 { 1591 u8 new_members; 1592 u32 val; 1593 1594 new_members = entry->old_members & ~BIT(entry->port); 1595 1596 val = mt7530_read(priv, MT7530_VAWD1); 1597 if (!(val & VLAN_VALID)) { 1598 dev_err(priv->dev, 1599 "Cannot be deleted due to invalid entry\n"); 1600 return; 1601 } 1602 1603 if (new_members) { 1604 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1605 VLAN_VALID; 1606 mt7530_write(priv, MT7530_VAWD1, val); 1607 } else { 1608 mt7530_write(priv, MT7530_VAWD1, 0); 1609 mt7530_write(priv, MT7530_VAWD2, 0); 1610 } 1611 } 1612 1613 static void 1614 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1615 struct mt7530_hw_vlan_entry *entry, 1616 mt7530_vlan_op vlan_op) 1617 { 1618 u32 val; 1619 1620 /* Fetch entry */ 1621 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1622 1623 val = mt7530_read(priv, MT7530_VAWD1); 1624 1625 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1626 1627 /* Manipulate entry */ 1628 vlan_op(priv, entry); 1629 1630 /* Flush result to hardware */ 1631 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1632 } 1633 1634 static int 1635 mt7530_setup_vlan0(struct mt7530_priv *priv) 1636 { 1637 u32 val; 1638 1639 /* Validate the entry with independent learning, keep the original 1640 * ingress tag attribute. 1641 */ 1642 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1643 VLAN_VALID; 1644 mt7530_write(priv, MT7530_VAWD1, val); 1645 1646 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1647 } 1648 1649 static int 1650 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1651 const struct switchdev_obj_port_vlan *vlan, 1652 struct netlink_ext_ack *extack) 1653 { 1654 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1655 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1656 struct mt7530_hw_vlan_entry new_entry; 1657 struct mt7530_priv *priv = ds->priv; 1658 1659 mutex_lock(&priv->reg_mutex); 1660 1661 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1662 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1663 1664 if (pvid) { 1665 priv->ports[port].pvid = vlan->vid; 1666 1667 /* Accept all frames if PVID is set */ 1668 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1669 MT7530_VLAN_ACC_ALL); 1670 1671 /* Only configure PVID if VLAN filtering is enabled */ 1672 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1673 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1674 G0_PORT_VID_MASK, 1675 G0_PORT_VID(vlan->vid)); 1676 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1677 /* This VLAN is overwritten without PVID, so unset it */ 1678 priv->ports[port].pvid = G0_PORT_VID_DEF; 1679 1680 /* Only accept tagged frames if the port is VLAN-aware */ 1681 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1682 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1683 MT7530_VLAN_ACC_TAGGED); 1684 1685 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1686 G0_PORT_VID_DEF); 1687 } 1688 1689 mutex_unlock(&priv->reg_mutex); 1690 1691 return 0; 1692 } 1693 1694 static int 1695 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1696 const struct switchdev_obj_port_vlan *vlan) 1697 { 1698 struct mt7530_hw_vlan_entry target_entry; 1699 struct mt7530_priv *priv = ds->priv; 1700 1701 mutex_lock(&priv->reg_mutex); 1702 1703 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1704 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1705 mt7530_hw_vlan_del); 1706 1707 /* PVID is being restored to the default whenever the PVID port 1708 * is being removed from the VLAN. 1709 */ 1710 if (priv->ports[port].pvid == vlan->vid) { 1711 priv->ports[port].pvid = G0_PORT_VID_DEF; 1712 1713 /* Only accept tagged frames if the port is VLAN-aware */ 1714 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1715 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1716 MT7530_VLAN_ACC_TAGGED); 1717 1718 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1719 G0_PORT_VID_DEF); 1720 } 1721 1722 1723 mutex_unlock(&priv->reg_mutex); 1724 1725 return 0; 1726 } 1727 1728 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1729 { 1730 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1731 MIRROR_PORT(val); 1732 } 1733 1734 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1735 { 1736 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1737 MIRROR_PORT(val); 1738 } 1739 1740 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1741 struct dsa_mall_mirror_tc_entry *mirror, 1742 bool ingress, struct netlink_ext_ack *extack) 1743 { 1744 struct mt7530_priv *priv = ds->priv; 1745 int monitor_port; 1746 u32 val; 1747 1748 /* Check for existent entry */ 1749 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1750 return -EEXIST; 1751 1752 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1753 1754 /* MT7530 only supports one monitor port */ 1755 monitor_port = mt753x_mirror_port_get(priv->id, val); 1756 if (val & MT753X_MIRROR_EN(priv->id) && 1757 monitor_port != mirror->to_local_port) 1758 return -EEXIST; 1759 1760 val |= MT753X_MIRROR_EN(priv->id); 1761 val &= ~MT753X_MIRROR_MASK(priv->id); 1762 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1763 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1764 1765 val = mt7530_read(priv, MT7530_PCR_P(port)); 1766 if (ingress) { 1767 val |= PORT_RX_MIR; 1768 priv->mirror_rx |= BIT(port); 1769 } else { 1770 val |= PORT_TX_MIR; 1771 priv->mirror_tx |= BIT(port); 1772 } 1773 mt7530_write(priv, MT7530_PCR_P(port), val); 1774 1775 return 0; 1776 } 1777 1778 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1779 struct dsa_mall_mirror_tc_entry *mirror) 1780 { 1781 struct mt7530_priv *priv = ds->priv; 1782 u32 val; 1783 1784 val = mt7530_read(priv, MT7530_PCR_P(port)); 1785 if (mirror->ingress) { 1786 val &= ~PORT_RX_MIR; 1787 priv->mirror_rx &= ~BIT(port); 1788 } else { 1789 val &= ~PORT_TX_MIR; 1790 priv->mirror_tx &= ~BIT(port); 1791 } 1792 mt7530_write(priv, MT7530_PCR_P(port), val); 1793 1794 if (!priv->mirror_rx && !priv->mirror_tx) { 1795 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1796 val &= ~MT753X_MIRROR_EN(priv->id); 1797 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1798 } 1799 } 1800 1801 static enum dsa_tag_protocol 1802 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1803 enum dsa_tag_protocol mp) 1804 { 1805 return DSA_TAG_PROTO_MTK; 1806 } 1807 1808 #ifdef CONFIG_GPIOLIB 1809 static inline u32 1810 mt7530_gpio_to_bit(unsigned int offset) 1811 { 1812 /* Map GPIO offset to register bit 1813 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1814 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1815 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1816 * [14:12] port 3 LED 0..2 as GPIO 9..11 1817 * [18:16] port 4 LED 0..2 as GPIO 12..14 1818 */ 1819 return BIT(offset + offset / 3); 1820 } 1821 1822 static int 1823 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1824 { 1825 struct mt7530_priv *priv = gpiochip_get_data(gc); 1826 u32 bit = mt7530_gpio_to_bit(offset); 1827 1828 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1829 } 1830 1831 static void 1832 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1833 { 1834 struct mt7530_priv *priv = gpiochip_get_data(gc); 1835 u32 bit = mt7530_gpio_to_bit(offset); 1836 1837 if (value) 1838 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1839 else 1840 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1841 } 1842 1843 static int 1844 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1845 { 1846 struct mt7530_priv *priv = gpiochip_get_data(gc); 1847 u32 bit = mt7530_gpio_to_bit(offset); 1848 1849 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1850 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1851 } 1852 1853 static int 1854 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1855 { 1856 struct mt7530_priv *priv = gpiochip_get_data(gc); 1857 u32 bit = mt7530_gpio_to_bit(offset); 1858 1859 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1860 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1861 1862 return 0; 1863 } 1864 1865 static int 1866 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1867 { 1868 struct mt7530_priv *priv = gpiochip_get_data(gc); 1869 u32 bit = mt7530_gpio_to_bit(offset); 1870 1871 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1872 1873 if (value) 1874 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1875 else 1876 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1877 1878 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1879 1880 return 0; 1881 } 1882 1883 static int 1884 mt7530_setup_gpio(struct mt7530_priv *priv) 1885 { 1886 struct device *dev = priv->dev; 1887 struct gpio_chip *gc; 1888 1889 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1890 if (!gc) 1891 return -ENOMEM; 1892 1893 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1894 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1895 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1896 1897 gc->label = "mt7530"; 1898 gc->parent = dev; 1899 gc->owner = THIS_MODULE; 1900 gc->get_direction = mt7530_gpio_get_direction; 1901 gc->direction_input = mt7530_gpio_direction_input; 1902 gc->direction_output = mt7530_gpio_direction_output; 1903 gc->get = mt7530_gpio_get; 1904 gc->set = mt7530_gpio_set; 1905 gc->base = -1; 1906 gc->ngpio = 15; 1907 gc->can_sleep = true; 1908 1909 return devm_gpiochip_add_data(dev, gc, priv); 1910 } 1911 #endif /* CONFIG_GPIOLIB */ 1912 1913 static irqreturn_t 1914 mt7530_irq_thread_fn(int irq, void *dev_id) 1915 { 1916 struct mt7530_priv *priv = dev_id; 1917 bool handled = false; 1918 u32 val; 1919 int p; 1920 1921 mt7530_mutex_lock(priv); 1922 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1923 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1924 mt7530_mutex_unlock(priv); 1925 1926 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1927 if (BIT(p) & val) { 1928 unsigned int irq; 1929 1930 irq = irq_find_mapping(priv->irq_domain, p); 1931 handle_nested_irq(irq); 1932 handled = true; 1933 } 1934 } 1935 1936 return IRQ_RETVAL(handled); 1937 } 1938 1939 static void 1940 mt7530_irq_mask(struct irq_data *d) 1941 { 1942 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1943 1944 priv->irq_enable &= ~BIT(d->hwirq); 1945 } 1946 1947 static void 1948 mt7530_irq_unmask(struct irq_data *d) 1949 { 1950 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1951 1952 priv->irq_enable |= BIT(d->hwirq); 1953 } 1954 1955 static void 1956 mt7530_irq_bus_lock(struct irq_data *d) 1957 { 1958 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1959 1960 mt7530_mutex_lock(priv); 1961 } 1962 1963 static void 1964 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1965 { 1966 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1967 1968 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1969 mt7530_mutex_unlock(priv); 1970 } 1971 1972 static struct irq_chip mt7530_irq_chip = { 1973 .name = KBUILD_MODNAME, 1974 .irq_mask = mt7530_irq_mask, 1975 .irq_unmask = mt7530_irq_unmask, 1976 .irq_bus_lock = mt7530_irq_bus_lock, 1977 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 1978 }; 1979 1980 static int 1981 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 1982 irq_hw_number_t hwirq) 1983 { 1984 irq_set_chip_data(irq, domain->host_data); 1985 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 1986 irq_set_nested_thread(irq, true); 1987 irq_set_noprobe(irq); 1988 1989 return 0; 1990 } 1991 1992 static const struct irq_domain_ops mt7530_irq_domain_ops = { 1993 .map = mt7530_irq_map, 1994 .xlate = irq_domain_xlate_onecell, 1995 }; 1996 1997 static void 1998 mt7988_irq_mask(struct irq_data *d) 1999 { 2000 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2001 2002 priv->irq_enable &= ~BIT(d->hwirq); 2003 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2004 } 2005 2006 static void 2007 mt7988_irq_unmask(struct irq_data *d) 2008 { 2009 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2010 2011 priv->irq_enable |= BIT(d->hwirq); 2012 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2013 } 2014 2015 static struct irq_chip mt7988_irq_chip = { 2016 .name = KBUILD_MODNAME, 2017 .irq_mask = mt7988_irq_mask, 2018 .irq_unmask = mt7988_irq_unmask, 2019 }; 2020 2021 static int 2022 mt7988_irq_map(struct irq_domain *domain, unsigned int irq, 2023 irq_hw_number_t hwirq) 2024 { 2025 irq_set_chip_data(irq, domain->host_data); 2026 irq_set_chip_and_handler(irq, &mt7988_irq_chip, handle_simple_irq); 2027 irq_set_nested_thread(irq, true); 2028 irq_set_noprobe(irq); 2029 2030 return 0; 2031 } 2032 2033 static const struct irq_domain_ops mt7988_irq_domain_ops = { 2034 .map = mt7988_irq_map, 2035 .xlate = irq_domain_xlate_onecell, 2036 }; 2037 2038 static void 2039 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 2040 { 2041 struct dsa_switch *ds = priv->ds; 2042 int p; 2043 2044 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2045 if (BIT(p) & ds->phys_mii_mask) { 2046 unsigned int irq; 2047 2048 irq = irq_create_mapping(priv->irq_domain, p); 2049 ds->user_mii_bus->irq[p] = irq; 2050 } 2051 } 2052 } 2053 2054 static int 2055 mt7530_setup_irq(struct mt7530_priv *priv) 2056 { 2057 struct device *dev = priv->dev; 2058 struct device_node *np = dev->of_node; 2059 int ret; 2060 2061 if (!of_property_read_bool(np, "interrupt-controller")) { 2062 dev_info(dev, "no interrupt support\n"); 2063 return 0; 2064 } 2065 2066 priv->irq = of_irq_get(np, 0); 2067 if (priv->irq <= 0) { 2068 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 2069 return priv->irq ? : -EINVAL; 2070 } 2071 2072 if (priv->id == ID_MT7988) 2073 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2074 &mt7988_irq_domain_ops, 2075 priv); 2076 else 2077 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2078 &mt7530_irq_domain_ops, 2079 priv); 2080 2081 if (!priv->irq_domain) { 2082 dev_err(dev, "failed to create IRQ domain\n"); 2083 return -ENOMEM; 2084 } 2085 2086 /* This register must be set for MT7530 to properly fire interrupts */ 2087 if (priv->id != ID_MT7531) 2088 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2089 2090 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2091 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2092 if (ret) { 2093 irq_domain_remove(priv->irq_domain); 2094 dev_err(dev, "failed to request IRQ: %d\n", ret); 2095 return ret; 2096 } 2097 2098 return 0; 2099 } 2100 2101 static void 2102 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2103 { 2104 int p; 2105 2106 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2107 if (BIT(p) & priv->ds->phys_mii_mask) { 2108 unsigned int irq; 2109 2110 irq = irq_find_mapping(priv->irq_domain, p); 2111 irq_dispose_mapping(irq); 2112 } 2113 } 2114 } 2115 2116 static void 2117 mt7530_free_irq_common(struct mt7530_priv *priv) 2118 { 2119 free_irq(priv->irq, priv); 2120 irq_domain_remove(priv->irq_domain); 2121 } 2122 2123 static void 2124 mt7530_free_irq(struct mt7530_priv *priv) 2125 { 2126 struct device_node *mnp, *np = priv->dev->of_node; 2127 2128 mnp = of_get_child_by_name(np, "mdio"); 2129 if (!mnp) 2130 mt7530_free_mdio_irq(priv); 2131 of_node_put(mnp); 2132 2133 mt7530_free_irq_common(priv); 2134 } 2135 2136 static int 2137 mt7530_setup_mdio(struct mt7530_priv *priv) 2138 { 2139 struct device_node *mnp, *np = priv->dev->of_node; 2140 struct dsa_switch *ds = priv->ds; 2141 struct device *dev = priv->dev; 2142 struct mii_bus *bus; 2143 static int idx; 2144 int ret = 0; 2145 2146 mnp = of_get_child_by_name(np, "mdio"); 2147 2148 if (mnp && !of_device_is_available(mnp)) 2149 goto out; 2150 2151 bus = devm_mdiobus_alloc(dev); 2152 if (!bus) { 2153 ret = -ENOMEM; 2154 goto out; 2155 } 2156 2157 if (!mnp) 2158 ds->user_mii_bus = bus; 2159 2160 bus->priv = priv; 2161 bus->name = KBUILD_MODNAME "-mii"; 2162 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2163 bus->read = mt753x_phy_read_c22; 2164 bus->write = mt753x_phy_write_c22; 2165 bus->read_c45 = mt753x_phy_read_c45; 2166 bus->write_c45 = mt753x_phy_write_c45; 2167 bus->parent = dev; 2168 bus->phy_mask = ~ds->phys_mii_mask; 2169 2170 if (priv->irq && !mnp) 2171 mt7530_setup_mdio_irq(priv); 2172 2173 ret = devm_of_mdiobus_register(dev, bus, mnp); 2174 if (ret) { 2175 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2176 if (priv->irq && !mnp) 2177 mt7530_free_mdio_irq(priv); 2178 } 2179 2180 out: 2181 of_node_put(mnp); 2182 return ret; 2183 } 2184 2185 static int 2186 mt7530_setup(struct dsa_switch *ds) 2187 { 2188 struct mt7530_priv *priv = ds->priv; 2189 struct device_node *dn = NULL; 2190 struct device_node *phy_node; 2191 struct device_node *mac_np; 2192 struct mt7530_dummy_poll p; 2193 phy_interface_t interface; 2194 struct dsa_port *cpu_dp; 2195 u32 id, val; 2196 int ret, i; 2197 2198 /* The parent node of conduit netdev which holds the common system 2199 * controller also is the container for two GMACs nodes representing 2200 * as two netdev instances. 2201 */ 2202 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2203 dn = cpu_dp->conduit->dev.of_node->parent; 2204 /* It doesn't matter which CPU port is found first, 2205 * their conduits should share the same parent OF node 2206 */ 2207 break; 2208 } 2209 2210 if (!dn) { 2211 dev_err(ds->dev, "parent OF node of DSA conduit not found"); 2212 return -EINVAL; 2213 } 2214 2215 ds->assisted_learning_on_cpu_port = true; 2216 ds->mtu_enforcement_ingress = true; 2217 2218 if (priv->id == ID_MT7530) { 2219 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2220 ret = regulator_enable(priv->core_pwr); 2221 if (ret < 0) { 2222 dev_err(priv->dev, 2223 "Failed to enable core power: %d\n", ret); 2224 return ret; 2225 } 2226 2227 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2228 ret = regulator_enable(priv->io_pwr); 2229 if (ret < 0) { 2230 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2231 ret); 2232 return ret; 2233 } 2234 } 2235 2236 /* Reset whole chip through gpio pin or memory-mapped registers for 2237 * different type of hardware 2238 */ 2239 if (priv->mcm) { 2240 reset_control_assert(priv->rstc); 2241 usleep_range(1000, 1100); 2242 reset_control_deassert(priv->rstc); 2243 } else { 2244 gpiod_set_value_cansleep(priv->reset, 0); 2245 usleep_range(1000, 1100); 2246 gpiod_set_value_cansleep(priv->reset, 1); 2247 } 2248 2249 /* Waiting for MT7530 got to stable */ 2250 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2251 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2252 20, 1000000); 2253 if (ret < 0) { 2254 dev_err(priv->dev, "reset timeout\n"); 2255 return ret; 2256 } 2257 2258 id = mt7530_read(priv, MT7530_CREV); 2259 id >>= CHIP_NAME_SHIFT; 2260 if (id != MT7530_ID) { 2261 dev_err(priv->dev, "chip %x can't be supported\n", id); 2262 return -ENODEV; 2263 } 2264 2265 /* Reset the switch through internal reset */ 2266 mt7530_write(priv, MT7530_SYS_CTRL, 2267 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2268 SYS_CTRL_REG_RST); 2269 2270 mt7530_pll_setup(priv); 2271 2272 /* Lower Tx driving for TRGMII path */ 2273 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2274 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 2275 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2276 2277 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2278 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 2279 RD_TAP_MASK, RD_TAP(16)); 2280 2281 /* Enable port 6 */ 2282 val = mt7530_read(priv, MT7530_MHWTRAP); 2283 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2284 val |= MHWTRAP_MANUAL; 2285 mt7530_write(priv, MT7530_MHWTRAP, val); 2286 2287 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2288 2289 mt753x_trap_frames(priv); 2290 2291 /* Enable and reset MIB counters */ 2292 mt7530_mib_reset(ds); 2293 2294 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2295 /* Disable forwarding by default on all ports */ 2296 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2297 PCR_MATRIX_CLR); 2298 2299 /* Disable learning by default on all ports */ 2300 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2301 2302 if (dsa_is_cpu_port(ds, i)) { 2303 ret = mt753x_cpu_port_enable(ds, i); 2304 if (ret) 2305 return ret; 2306 } else { 2307 mt7530_port_disable(ds, i); 2308 2309 /* Set default PVID to 0 on all user ports */ 2310 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2311 G0_PORT_VID_DEF); 2312 } 2313 /* Enable consistent egress tag */ 2314 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2315 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2316 } 2317 2318 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2319 ret = mt7530_setup_vlan0(priv); 2320 if (ret) 2321 return ret; 2322 2323 /* Setup port 5 */ 2324 if (!dsa_is_unused_port(ds, 5)) { 2325 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2326 } else { 2327 /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. 2328 * Set priv->p5_intf_sel to the appropriate value if PHY muxing 2329 * is detected. 2330 */ 2331 for_each_child_of_node(dn, mac_np) { 2332 if (!of_device_is_compatible(mac_np, 2333 "mediatek,eth-mac")) 2334 continue; 2335 2336 ret = of_property_read_u32(mac_np, "reg", &id); 2337 if (ret < 0 || id != 1) 2338 continue; 2339 2340 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2341 if (!phy_node) 2342 continue; 2343 2344 if (phy_node->parent == priv->dev->of_node->parent) { 2345 ret = of_get_phy_mode(mac_np, &interface); 2346 if (ret && ret != -ENODEV) { 2347 of_node_put(mac_np); 2348 of_node_put(phy_node); 2349 return ret; 2350 } 2351 id = of_mdio_parse_addr(ds->dev, phy_node); 2352 if (id == 0) 2353 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2354 if (id == 4) 2355 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2356 } 2357 of_node_put(mac_np); 2358 of_node_put(phy_node); 2359 break; 2360 } 2361 2362 if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 || 2363 priv->p5_intf_sel == P5_INTF_SEL_PHY_P4) 2364 mt7530_setup_port5(ds, interface); 2365 } 2366 2367 #ifdef CONFIG_GPIOLIB 2368 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2369 ret = mt7530_setup_gpio(priv); 2370 if (ret) 2371 return ret; 2372 } 2373 #endif /* CONFIG_GPIOLIB */ 2374 2375 /* Flush the FDB table */ 2376 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2377 if (ret < 0) 2378 return ret; 2379 2380 return 0; 2381 } 2382 2383 static int 2384 mt7531_setup_common(struct dsa_switch *ds) 2385 { 2386 struct mt7530_priv *priv = ds->priv; 2387 int ret, i; 2388 2389 mt753x_trap_frames(priv); 2390 2391 /* Enable and reset MIB counters */ 2392 mt7530_mib_reset(ds); 2393 2394 /* Disable flooding on all ports */ 2395 mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | 2396 UNU_FFP_MASK); 2397 2398 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2399 /* Disable forwarding by default on all ports */ 2400 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2401 PCR_MATRIX_CLR); 2402 2403 /* Disable learning by default on all ports */ 2404 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2405 2406 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2407 2408 if (dsa_is_cpu_port(ds, i)) { 2409 ret = mt753x_cpu_port_enable(ds, i); 2410 if (ret) 2411 return ret; 2412 } else { 2413 mt7530_port_disable(ds, i); 2414 2415 /* Set default PVID to 0 on all user ports */ 2416 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2417 G0_PORT_VID_DEF); 2418 } 2419 2420 /* Enable consistent egress tag */ 2421 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2422 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2423 } 2424 2425 /* Flush the FDB table */ 2426 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2427 if (ret < 0) 2428 return ret; 2429 2430 return 0; 2431 } 2432 2433 static int 2434 mt7531_setup(struct dsa_switch *ds) 2435 { 2436 struct mt7530_priv *priv = ds->priv; 2437 struct mt7530_dummy_poll p; 2438 u32 val, id; 2439 int ret, i; 2440 2441 /* Reset whole chip through gpio pin or memory-mapped registers for 2442 * different type of hardware 2443 */ 2444 if (priv->mcm) { 2445 reset_control_assert(priv->rstc); 2446 usleep_range(1000, 1100); 2447 reset_control_deassert(priv->rstc); 2448 } else { 2449 gpiod_set_value_cansleep(priv->reset, 0); 2450 usleep_range(1000, 1100); 2451 gpiod_set_value_cansleep(priv->reset, 1); 2452 } 2453 2454 /* Waiting for MT7530 got to stable */ 2455 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2456 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2457 20, 1000000); 2458 if (ret < 0) { 2459 dev_err(priv->dev, "reset timeout\n"); 2460 return ret; 2461 } 2462 2463 id = mt7530_read(priv, MT7531_CREV); 2464 id >>= CHIP_NAME_SHIFT; 2465 2466 if (id != MT7531_ID) { 2467 dev_err(priv->dev, "chip %x can't be supported\n", id); 2468 return -ENODEV; 2469 } 2470 2471 /* MT7531AE has got two SGMII units. One for port 5, one for port 6. 2472 * MT7531BE has got only one SGMII unit which is for port 6. 2473 */ 2474 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 2475 priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); 2476 2477 /* all MACs must be forced link-down before sw reset */ 2478 for (i = 0; i < MT7530_NUM_PORTS; i++) 2479 mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); 2480 2481 /* Reset the switch through internal reset */ 2482 mt7530_write(priv, MT7530_SYS_CTRL, 2483 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2484 SYS_CTRL_REG_RST); 2485 2486 if (!priv->p5_sgmii) { 2487 mt7531_pll_setup(priv); 2488 } else { 2489 /* Let ds->user_mii_bus be able to access external phy. */ 2490 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2491 MT7531_EXT_P_MDC_11); 2492 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2493 MT7531_EXT_P_MDIO_12); 2494 } 2495 2496 if (!dsa_is_unused_port(ds, 5)) 2497 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2498 2499 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2500 MT7531_GPIO0_INTERRUPT); 2501 2502 /* Let phylink decide the interface later. */ 2503 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2504 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2505 2506 /* Enable PHY core PLL, since phy_device has not yet been created 2507 * provided for phy_[read,write]_mmd_indirect is called, we provide 2508 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2509 * function. 2510 */ 2511 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2512 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2513 val |= MT7531_PHY_PLL_BYPASS_MODE; 2514 val &= ~MT7531_PHY_PLL_OFF; 2515 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2516 CORE_PLL_GROUP4, val); 2517 2518 mt7531_setup_common(ds); 2519 2520 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2521 ret = mt7530_setup_vlan0(priv); 2522 if (ret) 2523 return ret; 2524 2525 ds->assisted_learning_on_cpu_port = true; 2526 ds->mtu_enforcement_ingress = true; 2527 2528 return 0; 2529 } 2530 2531 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2532 struct phylink_config *config) 2533 { 2534 switch (port) { 2535 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2536 case 0 ... 4: 2537 __set_bit(PHY_INTERFACE_MODE_GMII, 2538 config->supported_interfaces); 2539 break; 2540 2541 /* Port 5 supports rgmii with delays, mii, and gmii. */ 2542 case 5: 2543 phy_interface_set_rgmii(config->supported_interfaces); 2544 __set_bit(PHY_INTERFACE_MODE_MII, 2545 config->supported_interfaces); 2546 __set_bit(PHY_INTERFACE_MODE_GMII, 2547 config->supported_interfaces); 2548 break; 2549 2550 /* Port 6 supports rgmii and trgmii. */ 2551 case 6: 2552 __set_bit(PHY_INTERFACE_MODE_RGMII, 2553 config->supported_interfaces); 2554 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2555 config->supported_interfaces); 2556 break; 2557 } 2558 } 2559 2560 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2561 struct phylink_config *config) 2562 { 2563 struct mt7530_priv *priv = ds->priv; 2564 2565 switch (port) { 2566 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2567 case 0 ... 4: 2568 __set_bit(PHY_INTERFACE_MODE_GMII, 2569 config->supported_interfaces); 2570 break; 2571 2572 /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on 2573 * MT7531AE. 2574 */ 2575 case 5: 2576 if (!priv->p5_sgmii) { 2577 phy_interface_set_rgmii(config->supported_interfaces); 2578 break; 2579 } 2580 fallthrough; 2581 2582 /* Port 6 supports sgmii/802.3z. */ 2583 case 6: 2584 __set_bit(PHY_INTERFACE_MODE_SGMII, 2585 config->supported_interfaces); 2586 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2587 config->supported_interfaces); 2588 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2589 config->supported_interfaces); 2590 2591 config->mac_capabilities |= MAC_2500FD; 2592 break; 2593 } 2594 } 2595 2596 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, 2597 struct phylink_config *config) 2598 { 2599 phy_interface_zero(config->supported_interfaces); 2600 2601 switch (port) { 2602 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2603 case 0 ... 4: 2604 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2605 config->supported_interfaces); 2606 break; 2607 2608 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2609 case 6: 2610 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2611 config->supported_interfaces); 2612 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2613 MAC_10000FD; 2614 } 2615 } 2616 2617 static int 2618 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2619 { 2620 struct mt7530_priv *priv = ds->priv; 2621 2622 return priv->info->pad_setup(ds, state->interface); 2623 } 2624 2625 static int 2626 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2627 phy_interface_t interface) 2628 { 2629 struct mt7530_priv *priv = ds->priv; 2630 2631 /* Only need to setup port5. */ 2632 if (port != 5) 2633 return 0; 2634 2635 mt7530_setup_port5(priv->ds, interface); 2636 2637 return 0; 2638 } 2639 2640 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2641 phy_interface_t interface, 2642 struct phy_device *phydev) 2643 { 2644 u32 val; 2645 2646 if (priv->p5_sgmii) { 2647 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2648 port); 2649 return -EINVAL; 2650 } 2651 2652 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2653 val |= GP_CLK_EN; 2654 val &= ~GP_MODE_MASK; 2655 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2656 val &= ~CLK_SKEW_IN_MASK; 2657 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2658 val &= ~CLK_SKEW_OUT_MASK; 2659 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2660 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2661 2662 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2663 if (!phydev || phy_driver_is_genphy(phydev)) { 2664 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2665 switch (interface) { 2666 case PHY_INTERFACE_MODE_RGMII: 2667 val |= TXCLK_NO_REVERSE; 2668 val |= RXCLK_NO_DELAY; 2669 break; 2670 case PHY_INTERFACE_MODE_RGMII_RXID: 2671 val |= TXCLK_NO_REVERSE; 2672 break; 2673 case PHY_INTERFACE_MODE_RGMII_TXID: 2674 val |= RXCLK_NO_DELAY; 2675 break; 2676 case PHY_INTERFACE_MODE_RGMII_ID: 2677 break; 2678 default: 2679 return -EINVAL; 2680 } 2681 } 2682 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2683 2684 return 0; 2685 } 2686 2687 static bool mt753x_is_mac_port(u32 port) 2688 { 2689 return (port == 5 || port == 6); 2690 } 2691 2692 static int 2693 mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2694 phy_interface_t interface) 2695 { 2696 if (dsa_is_cpu_port(ds, port) && 2697 interface == PHY_INTERFACE_MODE_INTERNAL) 2698 return 0; 2699 2700 return -EINVAL; 2701 } 2702 2703 static int 2704 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2705 phy_interface_t interface) 2706 { 2707 struct mt7530_priv *priv = ds->priv; 2708 struct phy_device *phydev; 2709 struct dsa_port *dp; 2710 2711 if (!mt753x_is_mac_port(port)) { 2712 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2713 return -EINVAL; 2714 } 2715 2716 switch (interface) { 2717 case PHY_INTERFACE_MODE_RGMII: 2718 case PHY_INTERFACE_MODE_RGMII_ID: 2719 case PHY_INTERFACE_MODE_RGMII_RXID: 2720 case PHY_INTERFACE_MODE_RGMII_TXID: 2721 dp = dsa_to_port(ds, port); 2722 phydev = dp->user->phydev; 2723 return mt7531_rgmii_setup(priv, port, interface, phydev); 2724 case PHY_INTERFACE_MODE_SGMII: 2725 case PHY_INTERFACE_MODE_NA: 2726 case PHY_INTERFACE_MODE_1000BASEX: 2727 case PHY_INTERFACE_MODE_2500BASEX: 2728 /* handled in SGMII PCS driver */ 2729 return 0; 2730 default: 2731 return -EINVAL; 2732 } 2733 2734 return -EINVAL; 2735 } 2736 2737 static int 2738 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2739 const struct phylink_link_state *state) 2740 { 2741 struct mt7530_priv *priv = ds->priv; 2742 2743 return priv->info->mac_port_config(ds, port, mode, state->interface); 2744 } 2745 2746 static struct phylink_pcs * 2747 mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port, 2748 phy_interface_t interface) 2749 { 2750 struct mt7530_priv *priv = ds->priv; 2751 2752 switch (interface) { 2753 case PHY_INTERFACE_MODE_TRGMII: 2754 return &priv->pcs[port].pcs; 2755 case PHY_INTERFACE_MODE_SGMII: 2756 case PHY_INTERFACE_MODE_1000BASEX: 2757 case PHY_INTERFACE_MODE_2500BASEX: 2758 return priv->ports[port].sgmii_pcs; 2759 default: 2760 return NULL; 2761 } 2762 } 2763 2764 static void 2765 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2766 const struct phylink_link_state *state) 2767 { 2768 struct mt7530_priv *priv = ds->priv; 2769 u32 mcr_cur, mcr_new; 2770 2771 switch (port) { 2772 case 0 ... 4: 2773 if (state->interface != PHY_INTERFACE_MODE_GMII && 2774 state->interface != PHY_INTERFACE_MODE_INTERNAL) 2775 goto unsupported; 2776 break; 2777 case 5: 2778 if (priv->p5_interface == state->interface) 2779 break; 2780 2781 if (mt753x_mac_config(ds, port, mode, state) < 0) 2782 goto unsupported; 2783 2784 if (priv->p5_intf_sel != P5_DISABLED) 2785 priv->p5_interface = state->interface; 2786 break; 2787 case 6: 2788 if (priv->p6_interface == state->interface) 2789 break; 2790 2791 mt753x_pad_setup(ds, state); 2792 2793 if (mt753x_mac_config(ds, port, mode, state) < 0) 2794 goto unsupported; 2795 2796 priv->p6_interface = state->interface; 2797 break; 2798 default: 2799 unsupported: 2800 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2801 __func__, phy_modes(state->interface), port); 2802 return; 2803 } 2804 2805 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2806 mcr_new = mcr_cur; 2807 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2808 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2809 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2810 2811 /* Are we connected to external phy */ 2812 if (port == 5 && dsa_is_user_port(ds, 5)) 2813 mcr_new |= PMCR_EXT_PHY; 2814 2815 if (mcr_new != mcr_cur) 2816 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2817 } 2818 2819 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2820 unsigned int mode, 2821 phy_interface_t interface) 2822 { 2823 struct mt7530_priv *priv = ds->priv; 2824 2825 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2826 } 2827 2828 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2829 unsigned int mode, 2830 phy_interface_t interface, 2831 struct phy_device *phydev, 2832 int speed, int duplex, 2833 bool tx_pause, bool rx_pause) 2834 { 2835 struct mt7530_priv *priv = ds->priv; 2836 u32 mcr; 2837 2838 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2839 2840 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2841 * variants. 2842 */ 2843 if (interface == PHY_INTERFACE_MODE_TRGMII || 2844 (phy_interface_mode_is_8023z(interface))) { 2845 speed = SPEED_1000; 2846 duplex = DUPLEX_FULL; 2847 } 2848 2849 switch (speed) { 2850 case SPEED_1000: 2851 mcr |= PMCR_FORCE_SPEED_1000; 2852 break; 2853 case SPEED_100: 2854 mcr |= PMCR_FORCE_SPEED_100; 2855 break; 2856 } 2857 if (duplex == DUPLEX_FULL) { 2858 mcr |= PMCR_FORCE_FDX; 2859 if (tx_pause) 2860 mcr |= PMCR_TX_FC_EN; 2861 if (rx_pause) 2862 mcr |= PMCR_RX_FC_EN; 2863 } 2864 2865 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { 2866 switch (speed) { 2867 case SPEED_1000: 2868 mcr |= PMCR_FORCE_EEE1G; 2869 break; 2870 case SPEED_100: 2871 mcr |= PMCR_FORCE_EEE100; 2872 break; 2873 } 2874 } 2875 2876 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2877 } 2878 2879 static int 2880 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2881 { 2882 struct mt7530_priv *priv = ds->priv; 2883 phy_interface_t interface; 2884 int speed; 2885 int ret; 2886 2887 switch (port) { 2888 case 5: 2889 if (!priv->p5_sgmii) 2890 interface = PHY_INTERFACE_MODE_RGMII; 2891 else 2892 interface = PHY_INTERFACE_MODE_2500BASEX; 2893 2894 priv->p5_interface = interface; 2895 break; 2896 case 6: 2897 interface = PHY_INTERFACE_MODE_2500BASEX; 2898 2899 priv->p6_interface = interface; 2900 break; 2901 default: 2902 return -EINVAL; 2903 } 2904 2905 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2906 speed = SPEED_2500; 2907 else 2908 speed = SPEED_1000; 2909 2910 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2911 if (ret) 2912 return ret; 2913 mt7530_write(priv, MT7530_PMCR_P(port), 2914 PMCR_CPU_PORT_SETTING(priv->id)); 2915 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2916 speed, DUPLEX_FULL, true, true); 2917 2918 return 0; 2919 } 2920 2921 static int 2922 mt7988_cpu_port_config(struct dsa_switch *ds, int port) 2923 { 2924 struct mt7530_priv *priv = ds->priv; 2925 2926 mt7530_write(priv, MT7530_PMCR_P(port), 2927 PMCR_CPU_PORT_SETTING(priv->id)); 2928 2929 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, 2930 PHY_INTERFACE_MODE_INTERNAL, NULL, 2931 SPEED_10000, DUPLEX_FULL, true, true); 2932 2933 return 0; 2934 } 2935 2936 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 2937 struct phylink_config *config) 2938 { 2939 struct mt7530_priv *priv = ds->priv; 2940 2941 /* This switch only supports full-duplex at 1Gbps */ 2942 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2943 MAC_10 | MAC_100 | MAC_1000FD; 2944 2945 priv->info->mac_port_get_caps(ds, port, config); 2946 } 2947 2948 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 2949 unsigned long *supported, 2950 const struct phylink_link_state *state) 2951 { 2952 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 2953 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 2954 phy_interface_mode_is_8023z(state->interface)) 2955 phylink_clear(supported, Autoneg); 2956 2957 return 0; 2958 } 2959 2960 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, 2961 struct phylink_link_state *state) 2962 { 2963 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2964 int port = pcs_to_mt753x_pcs(pcs)->port; 2965 u32 pmsr; 2966 2967 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2968 2969 state->link = (pmsr & PMSR_LINK); 2970 state->an_complete = state->link; 2971 state->duplex = !!(pmsr & PMSR_DPX); 2972 2973 switch (pmsr & PMSR_SPEED_MASK) { 2974 case PMSR_SPEED_10: 2975 state->speed = SPEED_10; 2976 break; 2977 case PMSR_SPEED_100: 2978 state->speed = SPEED_100; 2979 break; 2980 case PMSR_SPEED_1000: 2981 state->speed = SPEED_1000; 2982 break; 2983 default: 2984 state->speed = SPEED_UNKNOWN; 2985 break; 2986 } 2987 2988 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2989 if (pmsr & PMSR_RX_FC) 2990 state->pause |= MLO_PAUSE_RX; 2991 if (pmsr & PMSR_TX_FC) 2992 state->pause |= MLO_PAUSE_TX; 2993 } 2994 2995 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 2996 phy_interface_t interface, 2997 const unsigned long *advertising, 2998 bool permit_pause_to_mac) 2999 { 3000 return 0; 3001 } 3002 3003 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 3004 { 3005 } 3006 3007 static const struct phylink_pcs_ops mt7530_pcs_ops = { 3008 .pcs_validate = mt753x_pcs_validate, 3009 .pcs_get_state = mt7530_pcs_get_state, 3010 .pcs_config = mt753x_pcs_config, 3011 .pcs_an_restart = mt7530_pcs_an_restart, 3012 }; 3013 3014 static int 3015 mt753x_setup(struct dsa_switch *ds) 3016 { 3017 struct mt7530_priv *priv = ds->priv; 3018 int i, ret; 3019 3020 /* Initialise the PCS devices */ 3021 for (i = 0; i < priv->ds->num_ports; i++) { 3022 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3023 priv->pcs[i].pcs.neg_mode = true; 3024 priv->pcs[i].priv = priv; 3025 priv->pcs[i].port = i; 3026 } 3027 3028 ret = priv->info->sw_setup(ds); 3029 if (ret) 3030 return ret; 3031 3032 ret = mt7530_setup_irq(priv); 3033 if (ret) 3034 return ret; 3035 3036 ret = mt7530_setup_mdio(priv); 3037 if (ret && priv->irq) 3038 mt7530_free_irq_common(priv); 3039 3040 if (priv->create_sgmii) { 3041 ret = priv->create_sgmii(priv); 3042 if (ret && priv->irq) 3043 mt7530_free_irq(priv); 3044 } 3045 3046 return ret; 3047 } 3048 3049 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3050 struct ethtool_keee *e) 3051 { 3052 struct mt7530_priv *priv = ds->priv; 3053 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 3054 3055 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3056 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 3057 3058 return 0; 3059 } 3060 3061 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3062 struct ethtool_keee *e) 3063 { 3064 struct mt7530_priv *priv = ds->priv; 3065 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3066 3067 if (e->tx_lpi_timer > 0xFFF) 3068 return -EINVAL; 3069 3070 set = SET_LPI_THRESH(e->tx_lpi_timer); 3071 if (!e->tx_lpi_enabled) 3072 /* Force LPI Mode without a delay */ 3073 set |= LPI_MODE_EN; 3074 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3075 3076 return 0; 3077 } 3078 3079 static void 3080 mt753x_conduit_state_change(struct dsa_switch *ds, 3081 const struct net_device *conduit, 3082 bool operational) 3083 { 3084 struct dsa_port *cpu_dp = conduit->dsa_ptr; 3085 struct mt7530_priv *priv = ds->priv; 3086 int val = 0; 3087 u8 mask; 3088 3089 /* Set the CPU port to trap frames to for MT7530. Trapped frames will be 3090 * forwarded to the numerically smallest CPU port whose conduit 3091 * interface is up. 3092 */ 3093 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 3094 return; 3095 3096 mask = BIT(cpu_dp->index); 3097 3098 if (operational) 3099 priv->active_cpu_ports |= mask; 3100 else 3101 priv->active_cpu_ports &= ~mask; 3102 3103 if (priv->active_cpu_ports) 3104 val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports)); 3105 3106 mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val); 3107 } 3108 3109 static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 3110 { 3111 return 0; 3112 } 3113 3114 static int mt7988_setup(struct dsa_switch *ds) 3115 { 3116 struct mt7530_priv *priv = ds->priv; 3117 3118 /* Reset the switch */ 3119 reset_control_assert(priv->rstc); 3120 usleep_range(20, 50); 3121 reset_control_deassert(priv->rstc); 3122 usleep_range(20, 50); 3123 3124 /* Reset the switch PHYs */ 3125 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST); 3126 3127 return mt7531_setup_common(ds); 3128 } 3129 3130 const struct dsa_switch_ops mt7530_switch_ops = { 3131 .get_tag_protocol = mtk_get_tag_protocol, 3132 .setup = mt753x_setup, 3133 .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, 3134 .get_strings = mt7530_get_strings, 3135 .get_ethtool_stats = mt7530_get_ethtool_stats, 3136 .get_sset_count = mt7530_get_sset_count, 3137 .set_ageing_time = mt7530_set_ageing_time, 3138 .port_enable = mt7530_port_enable, 3139 .port_disable = mt7530_port_disable, 3140 .port_change_mtu = mt7530_port_change_mtu, 3141 .port_max_mtu = mt7530_port_max_mtu, 3142 .port_stp_state_set = mt7530_stp_state_set, 3143 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3144 .port_bridge_flags = mt7530_port_bridge_flags, 3145 .port_bridge_join = mt7530_port_bridge_join, 3146 .port_bridge_leave = mt7530_port_bridge_leave, 3147 .port_fdb_add = mt7530_port_fdb_add, 3148 .port_fdb_del = mt7530_port_fdb_del, 3149 .port_fdb_dump = mt7530_port_fdb_dump, 3150 .port_mdb_add = mt7530_port_mdb_add, 3151 .port_mdb_del = mt7530_port_mdb_del, 3152 .port_vlan_filtering = mt7530_port_vlan_filtering, 3153 .port_vlan_add = mt7530_port_vlan_add, 3154 .port_vlan_del = mt7530_port_vlan_del, 3155 .port_mirror_add = mt753x_port_mirror_add, 3156 .port_mirror_del = mt753x_port_mirror_del, 3157 .phylink_get_caps = mt753x_phylink_get_caps, 3158 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs, 3159 .phylink_mac_config = mt753x_phylink_mac_config, 3160 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3161 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3162 .get_mac_eee = mt753x_get_mac_eee, 3163 .set_mac_eee = mt753x_set_mac_eee, 3164 .conduit_state_change = mt753x_conduit_state_change, 3165 }; 3166 EXPORT_SYMBOL_GPL(mt7530_switch_ops); 3167 3168 const struct mt753x_info mt753x_table[] = { 3169 [ID_MT7621] = { 3170 .id = ID_MT7621, 3171 .pcs_ops = &mt7530_pcs_ops, 3172 .sw_setup = mt7530_setup, 3173 .phy_read_c22 = mt7530_phy_read_c22, 3174 .phy_write_c22 = mt7530_phy_write_c22, 3175 .phy_read_c45 = mt7530_phy_read_c45, 3176 .phy_write_c45 = mt7530_phy_write_c45, 3177 .pad_setup = mt7530_pad_clk_setup, 3178 .mac_port_get_caps = mt7530_mac_port_get_caps, 3179 .mac_port_config = mt7530_mac_config, 3180 }, 3181 [ID_MT7530] = { 3182 .id = ID_MT7530, 3183 .pcs_ops = &mt7530_pcs_ops, 3184 .sw_setup = mt7530_setup, 3185 .phy_read_c22 = mt7530_phy_read_c22, 3186 .phy_write_c22 = mt7530_phy_write_c22, 3187 .phy_read_c45 = mt7530_phy_read_c45, 3188 .phy_write_c45 = mt7530_phy_write_c45, 3189 .pad_setup = mt7530_pad_clk_setup, 3190 .mac_port_get_caps = mt7530_mac_port_get_caps, 3191 .mac_port_config = mt7530_mac_config, 3192 }, 3193 [ID_MT7531] = { 3194 .id = ID_MT7531, 3195 .pcs_ops = &mt7530_pcs_ops, 3196 .sw_setup = mt7531_setup, 3197 .phy_read_c22 = mt7531_ind_c22_phy_read, 3198 .phy_write_c22 = mt7531_ind_c22_phy_write, 3199 .phy_read_c45 = mt7531_ind_c45_phy_read, 3200 .phy_write_c45 = mt7531_ind_c45_phy_write, 3201 .pad_setup = mt7531_pad_setup, 3202 .cpu_port_config = mt7531_cpu_port_config, 3203 .mac_port_get_caps = mt7531_mac_port_get_caps, 3204 .mac_port_config = mt7531_mac_config, 3205 }, 3206 [ID_MT7988] = { 3207 .id = ID_MT7988, 3208 .pcs_ops = &mt7530_pcs_ops, 3209 .sw_setup = mt7988_setup, 3210 .phy_read_c22 = mt7531_ind_c22_phy_read, 3211 .phy_write_c22 = mt7531_ind_c22_phy_write, 3212 .phy_read_c45 = mt7531_ind_c45_phy_read, 3213 .phy_write_c45 = mt7531_ind_c45_phy_write, 3214 .pad_setup = mt7988_pad_setup, 3215 .cpu_port_config = mt7988_cpu_port_config, 3216 .mac_port_get_caps = mt7988_mac_port_get_caps, 3217 .mac_port_config = mt7988_mac_config, 3218 }, 3219 }; 3220 EXPORT_SYMBOL_GPL(mt753x_table); 3221 3222 int 3223 mt7530_probe_common(struct mt7530_priv *priv) 3224 { 3225 struct device *dev = priv->dev; 3226 3227 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 3228 if (!priv->ds) 3229 return -ENOMEM; 3230 3231 priv->ds->dev = dev; 3232 priv->ds->num_ports = MT7530_NUM_PORTS; 3233 3234 /* Get the hardware identifier from the devicetree node. 3235 * We will need it for some of the clock and regulator setup. 3236 */ 3237 priv->info = of_device_get_match_data(dev); 3238 if (!priv->info) 3239 return -EINVAL; 3240 3241 /* Sanity check if these required device operations are filled 3242 * properly. 3243 */ 3244 if (!priv->info->sw_setup || !priv->info->pad_setup || 3245 !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || 3246 !priv->info->mac_port_get_caps || 3247 !priv->info->mac_port_config) 3248 return -EINVAL; 3249 3250 priv->id = priv->info->id; 3251 priv->dev = dev; 3252 priv->ds->priv = priv; 3253 priv->ds->ops = &mt7530_switch_ops; 3254 mutex_init(&priv->reg_mutex); 3255 dev_set_drvdata(dev, priv); 3256 3257 return 0; 3258 } 3259 EXPORT_SYMBOL_GPL(mt7530_probe_common); 3260 3261 void 3262 mt7530_remove_common(struct mt7530_priv *priv) 3263 { 3264 if (priv->irq) 3265 mt7530_free_irq(priv); 3266 3267 dsa_unregister_switch(priv->ds); 3268 3269 mutex_destroy(&priv->reg_mutex); 3270 } 3271 EXPORT_SYMBOL_GPL(mt7530_remove_common); 3272 3273 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3274 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3275 MODULE_LICENSE("GPL"); 3276