1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 28 { 29 return container_of(pcs, struct mt753x_pcs, pcs); 30 } 31 32 /* String, offset, and register size in bytes if different from 4 bytes */ 33 static const struct mt7530_mib_desc mt7530_mib[] = { 34 MIB_DESC(1, 0x00, "TxDrop"), 35 MIB_DESC(1, 0x04, "TxCrcErr"), 36 MIB_DESC(1, 0x08, "TxUnicast"), 37 MIB_DESC(1, 0x0c, "TxMulticast"), 38 MIB_DESC(1, 0x10, "TxBroadcast"), 39 MIB_DESC(1, 0x14, "TxCollision"), 40 MIB_DESC(1, 0x18, "TxSingleCollision"), 41 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 42 MIB_DESC(1, 0x20, "TxDeferred"), 43 MIB_DESC(1, 0x24, "TxLateCollision"), 44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 45 MIB_DESC(1, 0x2c, "TxPause"), 46 MIB_DESC(1, 0x30, "TxPktSz64"), 47 MIB_DESC(1, 0x34, "TxPktSz65To127"), 48 MIB_DESC(1, 0x38, "TxPktSz128To255"), 49 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 50 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 51 MIB_DESC(1, 0x44, "Tx1024ToMax"), 52 MIB_DESC(2, 0x48, "TxBytes"), 53 MIB_DESC(1, 0x60, "RxDrop"), 54 MIB_DESC(1, 0x64, "RxFiltering"), 55 MIB_DESC(1, 0x68, "RxUnicast"), 56 MIB_DESC(1, 0x6c, "RxMulticast"), 57 MIB_DESC(1, 0x70, "RxBroadcast"), 58 MIB_DESC(1, 0x74, "RxAlignErr"), 59 MIB_DESC(1, 0x78, "RxCrcErr"), 60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 61 MIB_DESC(1, 0x80, "RxFragErr"), 62 MIB_DESC(1, 0x84, "RxOverSzErr"), 63 MIB_DESC(1, 0x88, "RxJabberErr"), 64 MIB_DESC(1, 0x8c, "RxPause"), 65 MIB_DESC(1, 0x90, "RxPktSz64"), 66 MIB_DESC(1, 0x94, "RxPktSz65To127"), 67 MIB_DESC(1, 0x98, "RxPktSz128To255"), 68 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 71 MIB_DESC(2, 0xa8, "RxBytes"), 72 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 73 MIB_DESC(1, 0xb4, "RxIngressDrop"), 74 MIB_DESC(1, 0xb8, "RxArlDrop"), 75 }; 76 77 /* Since phy_device has not yet been created and 78 * phy_{read,write}_mmd_indirect is not available, we provide our own 79 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 80 * to complete this function. 81 */ 82 static int 83 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 84 { 85 struct mii_bus *bus = priv->bus; 86 int value, ret; 87 88 /* Write the desired MMD Devad */ 89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 90 if (ret < 0) 91 goto err; 92 93 /* Write the desired MMD register address */ 94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 95 if (ret < 0) 96 goto err; 97 98 /* Select the Function : DATA with no post increment */ 99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 100 if (ret < 0) 101 goto err; 102 103 /* Read the content of the MMD's selected register */ 104 value = bus->read(bus, 0, MII_MMD_DATA); 105 106 return value; 107 err: 108 dev_err(&bus->dev, "failed to read mmd register\n"); 109 110 return ret; 111 } 112 113 static int 114 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 115 int devad, u32 data) 116 { 117 struct mii_bus *bus = priv->bus; 118 int ret; 119 120 /* Write the desired MMD Devad */ 121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 122 if (ret < 0) 123 goto err; 124 125 /* Write the desired MMD register address */ 126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 127 if (ret < 0) 128 goto err; 129 130 /* Select the Function : DATA with no post increment */ 131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 132 if (ret < 0) 133 goto err; 134 135 /* Write the data into MMD's selected register */ 136 ret = bus->write(bus, 0, MII_MMD_DATA, data); 137 err: 138 if (ret < 0) 139 dev_err(&bus->dev, 140 "failed to write mmd register\n"); 141 return ret; 142 } 143 144 static void 145 mt7530_mutex_lock(struct mt7530_priv *priv) 146 { 147 if (priv->bus) 148 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 149 } 150 151 static void 152 mt7530_mutex_unlock(struct mt7530_priv *priv) 153 { 154 if (priv->bus) 155 mutex_unlock(&priv->bus->mdio_lock); 156 } 157 158 static void 159 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 160 { 161 mt7530_mutex_lock(priv); 162 163 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 164 165 mt7530_mutex_unlock(priv); 166 } 167 168 static void 169 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 170 { 171 u32 val; 172 173 mt7530_mutex_lock(priv); 174 175 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 176 val &= ~mask; 177 val |= set; 178 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 179 180 mt7530_mutex_unlock(priv); 181 } 182 183 static void 184 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 185 { 186 core_rmw(priv, reg, 0, val); 187 } 188 189 static void 190 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 191 { 192 core_rmw(priv, reg, val, 0); 193 } 194 195 static int 196 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 197 { 198 int ret; 199 200 ret = regmap_write(priv->regmap, reg, val); 201 202 if (ret < 0) 203 dev_err(priv->dev, 204 "failed to write mt7530 register\n"); 205 206 return ret; 207 } 208 209 static u32 210 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 211 { 212 int ret; 213 u32 val; 214 215 ret = regmap_read(priv->regmap, reg, &val); 216 if (ret) { 217 WARN_ON_ONCE(1); 218 dev_err(priv->dev, 219 "failed to read mt7530 register\n"); 220 return 0; 221 } 222 223 return val; 224 } 225 226 static void 227 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 228 { 229 mt7530_mutex_lock(priv); 230 231 mt7530_mii_write(priv, reg, val); 232 233 mt7530_mutex_unlock(priv); 234 } 235 236 static u32 237 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 238 { 239 return mt7530_mii_read(p->priv, p->reg); 240 } 241 242 static u32 243 _mt7530_read(struct mt7530_dummy_poll *p) 244 { 245 u32 val; 246 247 mt7530_mutex_lock(p->priv); 248 249 val = mt7530_mii_read(p->priv, p->reg); 250 251 mt7530_mutex_unlock(p->priv); 252 253 return val; 254 } 255 256 static u32 257 mt7530_read(struct mt7530_priv *priv, u32 reg) 258 { 259 struct mt7530_dummy_poll p; 260 261 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 262 return _mt7530_read(&p); 263 } 264 265 static void 266 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 267 u32 mask, u32 set) 268 { 269 mt7530_mutex_lock(priv); 270 271 regmap_update_bits(priv->regmap, reg, mask, set); 272 273 mt7530_mutex_unlock(priv); 274 } 275 276 static void 277 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 278 { 279 mt7530_rmw(priv, reg, val, val); 280 } 281 282 static void 283 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 284 { 285 mt7530_rmw(priv, reg, val, 0); 286 } 287 288 static int 289 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 290 { 291 u32 val; 292 int ret; 293 struct mt7530_dummy_poll p; 294 295 /* Set the command operating upon the MAC address entries */ 296 val = ATC_BUSY | ATC_MAT(0) | cmd; 297 mt7530_write(priv, MT7530_ATC, val); 298 299 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 300 ret = readx_poll_timeout(_mt7530_read, &p, val, 301 !(val & ATC_BUSY), 20, 20000); 302 if (ret < 0) { 303 dev_err(priv->dev, "reset timeout\n"); 304 return ret; 305 } 306 307 /* Additional sanity for read command if the specified 308 * entry is invalid 309 */ 310 val = mt7530_read(priv, MT7530_ATC); 311 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 312 return -EINVAL; 313 314 if (rsp) 315 *rsp = val; 316 317 return 0; 318 } 319 320 static void 321 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 322 { 323 u32 reg[3]; 324 int i; 325 326 /* Read from ARL table into an array */ 327 for (i = 0; i < 3; i++) { 328 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 329 330 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 331 __func__, __LINE__, i, reg[i]); 332 } 333 334 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 335 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 336 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 337 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 338 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 339 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 340 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 341 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 342 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 343 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 344 } 345 346 static void 347 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 348 u8 port_mask, const u8 *mac, 349 u8 aging, u8 type) 350 { 351 u32 reg[3] = { 0 }; 352 int i; 353 354 reg[1] |= vid & CVID_MASK; 355 reg[1] |= ATA2_IVL; 356 reg[1] |= ATA2_FID(FID_BRIDGED); 357 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 358 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 359 /* STATIC_ENT indicate that entry is static wouldn't 360 * be aged out and STATIC_EMP specified as erasing an 361 * entry 362 */ 363 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 364 reg[1] |= mac[5] << MAC_BYTE_5; 365 reg[1] |= mac[4] << MAC_BYTE_4; 366 reg[0] |= mac[3] << MAC_BYTE_3; 367 reg[0] |= mac[2] << MAC_BYTE_2; 368 reg[0] |= mac[1] << MAC_BYTE_1; 369 reg[0] |= mac[0] << MAC_BYTE_0; 370 371 /* Write array into the ARL table */ 372 for (i = 0; i < 3; i++) 373 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 374 } 375 376 /* Set up switch core clock for MT7530 */ 377 static void mt7530_pll_setup(struct mt7530_priv *priv) 378 { 379 /* Disable core clock */ 380 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 381 382 /* Disable PLL */ 383 core_write(priv, CORE_GSWPLL_GRP1, 0); 384 385 /* Set core clock into 500Mhz */ 386 core_write(priv, CORE_GSWPLL_GRP2, 387 RG_GSWPLL_POSDIV_500M(1) | 388 RG_GSWPLL_FBKDIV_500M(25)); 389 390 /* Enable PLL */ 391 core_write(priv, CORE_GSWPLL_GRP1, 392 RG_GSWPLL_EN_PRE | 393 RG_GSWPLL_POSDIV_200M(2) | 394 RG_GSWPLL_FBKDIV_200M(32)); 395 396 udelay(20); 397 398 /* Enable core clock */ 399 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 400 } 401 402 /* If port 6 is available as a CPU port, always prefer that as the default, 403 * otherwise don't care. 404 */ 405 static struct dsa_port * 406 mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) 407 { 408 struct dsa_port *cpu_dp = dsa_to_port(ds, 6); 409 410 if (dsa_port_is_cpu(cpu_dp)) 411 return cpu_dp; 412 413 return NULL; 414 } 415 416 /* Setup port 6 interface mode and TRGMII TX circuit */ 417 static int 418 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 419 { 420 struct mt7530_priv *priv = ds->priv; 421 u32 ncpo1, ssc_delta, trgint, xtal; 422 423 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 424 425 if (xtal == HWTRAP_XTAL_20MHZ) { 426 dev_err(priv->dev, 427 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 428 __func__); 429 return -EINVAL; 430 } 431 432 switch (interface) { 433 case PHY_INTERFACE_MODE_RGMII: 434 trgint = 0; 435 break; 436 case PHY_INTERFACE_MODE_TRGMII: 437 trgint = 1; 438 if (xtal == HWTRAP_XTAL_25MHZ) 439 ssc_delta = 0x57; 440 else 441 ssc_delta = 0x87; 442 if (priv->id == ID_MT7621) { 443 /* PLL frequency: 125MHz: 1.0GBit */ 444 if (xtal == HWTRAP_XTAL_40MHZ) 445 ncpo1 = 0x0640; 446 if (xtal == HWTRAP_XTAL_25MHZ) 447 ncpo1 = 0x0a00; 448 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 449 if (xtal == HWTRAP_XTAL_40MHZ) 450 ncpo1 = 0x0c80; 451 if (xtal == HWTRAP_XTAL_25MHZ) 452 ncpo1 = 0x1400; 453 } 454 break; 455 default: 456 dev_err(priv->dev, "xMII interface %d not supported\n", 457 interface); 458 return -EINVAL; 459 } 460 461 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 462 P6_INTF_MODE(trgint)); 463 464 if (trgint) { 465 /* Disable the MT7530 TRGMII clocks */ 466 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 467 468 /* Setup the MT7530 TRGMII Tx Clock */ 469 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 470 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 471 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 472 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 473 core_write(priv, CORE_PLL_GROUP4, 474 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 475 RG_SYSPLL_BIAS_LPF_EN); 476 core_write(priv, CORE_PLL_GROUP2, 477 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 478 RG_SYSPLL_POSDIV(1)); 479 core_write(priv, CORE_PLL_GROUP7, 480 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 481 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 482 483 /* Enable the MT7530 TRGMII clocks */ 484 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 485 } 486 487 return 0; 488 } 489 490 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 491 { 492 u32 val; 493 494 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 495 496 return (val & PAD_DUAL_SGMII_EN) != 0; 497 } 498 499 static int 500 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 501 { 502 return 0; 503 } 504 505 static void 506 mt7531_pll_setup(struct mt7530_priv *priv) 507 { 508 u32 top_sig; 509 u32 hwstrap; 510 u32 xtal; 511 u32 val; 512 513 if (mt7531_dual_sgmii_supported(priv)) 514 return; 515 516 val = mt7530_read(priv, MT7531_CREV); 517 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 518 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 519 if ((val & CHIP_REV_M) > 0) 520 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 521 HWTRAP_XTAL_FSEL_25MHZ; 522 else 523 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 524 525 /* Step 1 : Disable MT7531 COREPLL */ 526 val = mt7530_read(priv, MT7531_PLLGP_EN); 527 val &= ~EN_COREPLL; 528 mt7530_write(priv, MT7531_PLLGP_EN, val); 529 530 /* Step 2: switch to XTAL output */ 531 val = mt7530_read(priv, MT7531_PLLGP_EN); 532 val |= SW_CLKSW; 533 mt7530_write(priv, MT7531_PLLGP_EN, val); 534 535 val = mt7530_read(priv, MT7531_PLLGP_CR0); 536 val &= ~RG_COREPLL_EN; 537 mt7530_write(priv, MT7531_PLLGP_CR0, val); 538 539 /* Step 3: disable PLLGP and enable program PLLGP */ 540 val = mt7530_read(priv, MT7531_PLLGP_EN); 541 val |= SW_PLLGP; 542 mt7530_write(priv, MT7531_PLLGP_EN, val); 543 544 /* Step 4: program COREPLL output frequency to 500MHz */ 545 val = mt7530_read(priv, MT7531_PLLGP_CR0); 546 val &= ~RG_COREPLL_POSDIV_M; 547 val |= 2 << RG_COREPLL_POSDIV_S; 548 mt7530_write(priv, MT7531_PLLGP_CR0, val); 549 usleep_range(25, 35); 550 551 switch (xtal) { 552 case HWTRAP_XTAL_FSEL_25MHZ: 553 val = mt7530_read(priv, MT7531_PLLGP_CR0); 554 val &= ~RG_COREPLL_SDM_PCW_M; 555 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 556 mt7530_write(priv, MT7531_PLLGP_CR0, val); 557 break; 558 case HWTRAP_XTAL_FSEL_40MHZ: 559 val = mt7530_read(priv, MT7531_PLLGP_CR0); 560 val &= ~RG_COREPLL_SDM_PCW_M; 561 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 562 mt7530_write(priv, MT7531_PLLGP_CR0, val); 563 break; 564 } 565 566 /* Set feedback divide ratio update signal to high */ 567 val = mt7530_read(priv, MT7531_PLLGP_CR0); 568 val |= RG_COREPLL_SDM_PCW_CHG; 569 mt7530_write(priv, MT7531_PLLGP_CR0, val); 570 /* Wait for at least 16 XTAL clocks */ 571 usleep_range(10, 20); 572 573 /* Step 5: set feedback divide ratio update signal to low */ 574 val = mt7530_read(priv, MT7531_PLLGP_CR0); 575 val &= ~RG_COREPLL_SDM_PCW_CHG; 576 mt7530_write(priv, MT7531_PLLGP_CR0, val); 577 578 /* Enable 325M clock for SGMII */ 579 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 580 581 /* Enable 250SSC clock for RGMII */ 582 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 583 584 /* Step 6: Enable MT7531 PLL */ 585 val = mt7530_read(priv, MT7531_PLLGP_CR0); 586 val |= RG_COREPLL_EN; 587 mt7530_write(priv, MT7531_PLLGP_CR0, val); 588 589 val = mt7530_read(priv, MT7531_PLLGP_EN); 590 val |= EN_COREPLL; 591 mt7530_write(priv, MT7531_PLLGP_EN, val); 592 usleep_range(25, 35); 593 } 594 595 static void 596 mt7530_mib_reset(struct dsa_switch *ds) 597 { 598 struct mt7530_priv *priv = ds->priv; 599 600 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 601 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 602 } 603 604 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 605 { 606 return mdiobus_read_nested(priv->bus, port, regnum); 607 } 608 609 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 610 u16 val) 611 { 612 return mdiobus_write_nested(priv->bus, port, regnum, val); 613 } 614 615 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 616 int devad, int regnum) 617 { 618 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 619 } 620 621 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 622 int regnum, u16 val) 623 { 624 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 625 } 626 627 static int 628 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 629 int regnum) 630 { 631 struct mt7530_dummy_poll p; 632 u32 reg, val; 633 int ret; 634 635 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 636 637 mt7530_mutex_lock(priv); 638 639 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 640 !(val & MT7531_PHY_ACS_ST), 20, 100000); 641 if (ret < 0) { 642 dev_err(priv->dev, "poll timeout\n"); 643 goto out; 644 } 645 646 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 647 MT7531_MDIO_DEV_ADDR(devad) | regnum; 648 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 649 650 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 651 !(val & MT7531_PHY_ACS_ST), 20, 100000); 652 if (ret < 0) { 653 dev_err(priv->dev, "poll timeout\n"); 654 goto out; 655 } 656 657 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 658 MT7531_MDIO_DEV_ADDR(devad); 659 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 660 661 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 662 !(val & MT7531_PHY_ACS_ST), 20, 100000); 663 if (ret < 0) { 664 dev_err(priv->dev, "poll timeout\n"); 665 goto out; 666 } 667 668 ret = val & MT7531_MDIO_RW_DATA_MASK; 669 out: 670 mt7530_mutex_unlock(priv); 671 672 return ret; 673 } 674 675 static int 676 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 677 int regnum, u16 data) 678 { 679 struct mt7530_dummy_poll p; 680 u32 val, reg; 681 int ret; 682 683 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 684 685 mt7530_mutex_lock(priv); 686 687 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 688 !(val & MT7531_PHY_ACS_ST), 20, 100000); 689 if (ret < 0) { 690 dev_err(priv->dev, "poll timeout\n"); 691 goto out; 692 } 693 694 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 695 MT7531_MDIO_DEV_ADDR(devad) | regnum; 696 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 697 698 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 699 !(val & MT7531_PHY_ACS_ST), 20, 100000); 700 if (ret < 0) { 701 dev_err(priv->dev, "poll timeout\n"); 702 goto out; 703 } 704 705 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 706 MT7531_MDIO_DEV_ADDR(devad) | data; 707 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 708 709 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 710 !(val & MT7531_PHY_ACS_ST), 20, 100000); 711 if (ret < 0) { 712 dev_err(priv->dev, "poll timeout\n"); 713 goto out; 714 } 715 716 out: 717 mt7530_mutex_unlock(priv); 718 719 return ret; 720 } 721 722 static int 723 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 724 { 725 struct mt7530_dummy_poll p; 726 int ret; 727 u32 val; 728 729 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 730 731 mt7530_mutex_lock(priv); 732 733 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 734 !(val & MT7531_PHY_ACS_ST), 20, 100000); 735 if (ret < 0) { 736 dev_err(priv->dev, "poll timeout\n"); 737 goto out; 738 } 739 740 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 741 MT7531_MDIO_REG_ADDR(regnum); 742 743 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 744 745 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 746 !(val & MT7531_PHY_ACS_ST), 20, 100000); 747 if (ret < 0) { 748 dev_err(priv->dev, "poll timeout\n"); 749 goto out; 750 } 751 752 ret = val & MT7531_MDIO_RW_DATA_MASK; 753 out: 754 mt7530_mutex_unlock(priv); 755 756 return ret; 757 } 758 759 static int 760 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 761 u16 data) 762 { 763 struct mt7530_dummy_poll p; 764 int ret; 765 u32 reg; 766 767 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 768 769 mt7530_mutex_lock(priv); 770 771 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 772 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 773 if (ret < 0) { 774 dev_err(priv->dev, "poll timeout\n"); 775 goto out; 776 } 777 778 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 779 MT7531_MDIO_REG_ADDR(regnum) | data; 780 781 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 782 783 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 784 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 785 if (ret < 0) { 786 dev_err(priv->dev, "poll timeout\n"); 787 goto out; 788 } 789 790 out: 791 mt7530_mutex_unlock(priv); 792 793 return ret; 794 } 795 796 static int 797 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 798 { 799 struct mt7530_priv *priv = bus->priv; 800 801 return priv->info->phy_read_c22(priv, port, regnum); 802 } 803 804 static int 805 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 806 { 807 struct mt7530_priv *priv = bus->priv; 808 809 return priv->info->phy_read_c45(priv, port, devad, regnum); 810 } 811 812 static int 813 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 814 { 815 struct mt7530_priv *priv = bus->priv; 816 817 return priv->info->phy_write_c22(priv, port, regnum, val); 818 } 819 820 static int 821 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 822 u16 val) 823 { 824 struct mt7530_priv *priv = bus->priv; 825 826 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 827 } 828 829 static void 830 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 831 uint8_t *data) 832 { 833 int i; 834 835 if (stringset != ETH_SS_STATS) 836 return; 837 838 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 839 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 840 ETH_GSTRING_LEN); 841 } 842 843 static void 844 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 845 uint64_t *data) 846 { 847 struct mt7530_priv *priv = ds->priv; 848 const struct mt7530_mib_desc *mib; 849 u32 reg, i; 850 u64 hi; 851 852 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 853 mib = &mt7530_mib[i]; 854 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 855 856 data[i] = mt7530_read(priv, reg); 857 if (mib->size == 2) { 858 hi = mt7530_read(priv, reg + 4); 859 data[i] |= hi << 32; 860 } 861 } 862 } 863 864 static int 865 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 866 { 867 if (sset != ETH_SS_STATS) 868 return 0; 869 870 return ARRAY_SIZE(mt7530_mib); 871 } 872 873 static int 874 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 875 { 876 struct mt7530_priv *priv = ds->priv; 877 unsigned int secs = msecs / 1000; 878 unsigned int tmp_age_count; 879 unsigned int error = -1; 880 unsigned int age_count; 881 unsigned int age_unit; 882 883 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 884 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 885 return -ERANGE; 886 887 /* iterate through all possible age_count to find the closest pair */ 888 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 889 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 890 891 if (tmp_age_unit <= AGE_UNIT_MAX) { 892 unsigned int tmp_error = secs - 893 (tmp_age_count + 1) * (tmp_age_unit + 1); 894 895 /* found a closer pair */ 896 if (error > tmp_error) { 897 error = tmp_error; 898 age_count = tmp_age_count; 899 age_unit = tmp_age_unit; 900 } 901 902 /* found the exact match, so break the loop */ 903 if (!error) 904 break; 905 } 906 } 907 908 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 909 910 return 0; 911 } 912 913 static const char *p5_intf_modes(unsigned int p5_interface) 914 { 915 switch (p5_interface) { 916 case P5_DISABLED: 917 return "DISABLED"; 918 case P5_INTF_SEL_PHY_P0: 919 return "PHY P0"; 920 case P5_INTF_SEL_PHY_P4: 921 return "PHY P4"; 922 case P5_INTF_SEL_GMAC5: 923 return "GMAC5"; 924 case P5_INTF_SEL_GMAC5_SGMII: 925 return "GMAC5_SGMII"; 926 default: 927 return "unknown"; 928 } 929 } 930 931 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 932 { 933 struct mt7530_priv *priv = ds->priv; 934 u8 tx_delay = 0; 935 int val; 936 937 mutex_lock(&priv->reg_mutex); 938 939 val = mt7530_read(priv, MT7530_MHWTRAP); 940 941 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 942 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 943 944 switch (priv->p5_intf_sel) { 945 case P5_INTF_SEL_PHY_P0: 946 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 947 val |= MHWTRAP_PHY0_SEL; 948 fallthrough; 949 case P5_INTF_SEL_PHY_P4: 950 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 951 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 952 953 /* Setup the MAC by default for the cpu port */ 954 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 955 break; 956 case P5_INTF_SEL_GMAC5: 957 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 958 val &= ~MHWTRAP_P5_DIS; 959 break; 960 case P5_DISABLED: 961 interface = PHY_INTERFACE_MODE_NA; 962 break; 963 default: 964 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 965 priv->p5_intf_sel); 966 goto unlock_exit; 967 } 968 969 /* Setup RGMII settings */ 970 if (phy_interface_mode_is_rgmii(interface)) { 971 val |= MHWTRAP_P5_RGMII_MODE; 972 973 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 974 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 975 976 /* Don't set delay in DSA mode */ 977 if (!dsa_is_dsa_port(priv->ds, 5) && 978 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 979 interface == PHY_INTERFACE_MODE_RGMII_ID)) 980 tx_delay = 4; /* n * 0.5 ns */ 981 982 /* P5 RGMII TX Clock Control: delay x */ 983 mt7530_write(priv, MT7530_P5RGMIITXCR, 984 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 985 986 /* reduce P5 RGMII Tx driving, 8mA */ 987 mt7530_write(priv, MT7530_IO_DRV_CR, 988 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 989 } 990 991 mt7530_write(priv, MT7530_MHWTRAP, val); 992 993 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 994 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 995 996 priv->p5_interface = interface; 997 998 unlock_exit: 999 mutex_unlock(&priv->reg_mutex); 1000 } 1001 1002 static void 1003 mt753x_trap_frames(struct mt7530_priv *priv) 1004 { 1005 /* Trap BPDUs to the CPU port(s) */ 1006 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 1007 MT753X_BPDU_CPU_ONLY); 1008 1009 /* Trap 802.1X PAE frames to the CPU port(s) */ 1010 mt7530_rmw(priv, MT753X_BPC, MT753X_PAE_PORT_FW_MASK, 1011 MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY)); 1012 1013 /* Trap LLDP frames with :0E MAC DA to the CPU port(s) */ 1014 mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_PORT_FW_MASK, 1015 MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY)); 1016 } 1017 1018 static int 1019 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1020 { 1021 struct mt7530_priv *priv = ds->priv; 1022 int ret; 1023 1024 /* Setup max capability of CPU port at first */ 1025 if (priv->info->cpu_port_config) { 1026 ret = priv->info->cpu_port_config(ds, port); 1027 if (ret) 1028 return ret; 1029 } 1030 1031 /* Enable Mediatek header mode on the cpu port */ 1032 mt7530_write(priv, MT7530_PVC_P(port), 1033 PORT_SPEC_TAG); 1034 1035 /* Enable flooding on the CPU port */ 1036 mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | 1037 UNU_FFP(BIT(port))); 1038 1039 /* Set CPU port number */ 1040 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) 1041 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1042 1043 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on 1044 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that 1045 * is affine to the inbound user port. 1046 */ 1047 if (priv->id == ID_MT7531 || priv->id == ID_MT7988) 1048 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); 1049 1050 /* CPU port gets connected to all user ports of 1051 * the switch. 1052 */ 1053 mt7530_write(priv, MT7530_PCR_P(port), 1054 PCR_MATRIX(dsa_user_ports(priv->ds))); 1055 1056 /* Set to fallback mode for independent VLAN learning */ 1057 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1058 MT7530_PORT_FALLBACK_MODE); 1059 1060 return 0; 1061 } 1062 1063 static int 1064 mt7530_port_enable(struct dsa_switch *ds, int port, 1065 struct phy_device *phy) 1066 { 1067 struct dsa_port *dp = dsa_to_port(ds, port); 1068 struct mt7530_priv *priv = ds->priv; 1069 1070 mutex_lock(&priv->reg_mutex); 1071 1072 /* Allow the user port gets connected to the cpu port and also 1073 * restore the port matrix if the port is the member of a certain 1074 * bridge. 1075 */ 1076 if (dsa_port_is_user(dp)) { 1077 struct dsa_port *cpu_dp = dp->cpu_dp; 1078 1079 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1080 } 1081 priv->ports[port].enable = true; 1082 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1083 priv->ports[port].pm); 1084 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1085 1086 mutex_unlock(&priv->reg_mutex); 1087 1088 return 0; 1089 } 1090 1091 static void 1092 mt7530_port_disable(struct dsa_switch *ds, int port) 1093 { 1094 struct mt7530_priv *priv = ds->priv; 1095 1096 mutex_lock(&priv->reg_mutex); 1097 1098 /* Clear up all port matrix which could be restored in the next 1099 * enablement for the port. 1100 */ 1101 priv->ports[port].enable = false; 1102 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1103 PCR_MATRIX_CLR); 1104 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1105 1106 mutex_unlock(&priv->reg_mutex); 1107 } 1108 1109 static int 1110 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1111 { 1112 struct mt7530_priv *priv = ds->priv; 1113 int length; 1114 u32 val; 1115 1116 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1117 * largest MTU of the slave ports. Because the switch only has a global 1118 * RX length register, only allowing CPU port here is enough. 1119 */ 1120 if (!dsa_is_cpu_port(ds, port)) 1121 return 0; 1122 1123 mt7530_mutex_lock(priv); 1124 1125 val = mt7530_mii_read(priv, MT7530_GMACCR); 1126 val &= ~MAX_RX_PKT_LEN_MASK; 1127 1128 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1129 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1130 if (length <= 1522) { 1131 val |= MAX_RX_PKT_LEN_1522; 1132 } else if (length <= 1536) { 1133 val |= MAX_RX_PKT_LEN_1536; 1134 } else if (length <= 1552) { 1135 val |= MAX_RX_PKT_LEN_1552; 1136 } else { 1137 val &= ~MAX_RX_JUMBO_MASK; 1138 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1139 val |= MAX_RX_PKT_LEN_JUMBO; 1140 } 1141 1142 mt7530_mii_write(priv, MT7530_GMACCR, val); 1143 1144 mt7530_mutex_unlock(priv); 1145 1146 return 0; 1147 } 1148 1149 static int 1150 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1151 { 1152 return MT7530_MAX_MTU; 1153 } 1154 1155 static void 1156 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1157 { 1158 struct mt7530_priv *priv = ds->priv; 1159 u32 stp_state; 1160 1161 switch (state) { 1162 case BR_STATE_DISABLED: 1163 stp_state = MT7530_STP_DISABLED; 1164 break; 1165 case BR_STATE_BLOCKING: 1166 stp_state = MT7530_STP_BLOCKING; 1167 break; 1168 case BR_STATE_LISTENING: 1169 stp_state = MT7530_STP_LISTENING; 1170 break; 1171 case BR_STATE_LEARNING: 1172 stp_state = MT7530_STP_LEARNING; 1173 break; 1174 case BR_STATE_FORWARDING: 1175 default: 1176 stp_state = MT7530_STP_FORWARDING; 1177 break; 1178 } 1179 1180 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1181 FID_PST(FID_BRIDGED, stp_state)); 1182 } 1183 1184 static int 1185 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1186 struct switchdev_brport_flags flags, 1187 struct netlink_ext_ack *extack) 1188 { 1189 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1190 BR_BCAST_FLOOD)) 1191 return -EINVAL; 1192 1193 return 0; 1194 } 1195 1196 static int 1197 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1198 struct switchdev_brport_flags flags, 1199 struct netlink_ext_ack *extack) 1200 { 1201 struct mt7530_priv *priv = ds->priv; 1202 1203 if (flags.mask & BR_LEARNING) 1204 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1205 flags.val & BR_LEARNING ? 0 : SA_DIS); 1206 1207 if (flags.mask & BR_FLOOD) 1208 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1209 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1210 1211 if (flags.mask & BR_MCAST_FLOOD) 1212 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1213 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1214 1215 if (flags.mask & BR_BCAST_FLOOD) 1216 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1217 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1218 1219 return 0; 1220 } 1221 1222 static int 1223 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1224 struct dsa_bridge bridge, bool *tx_fwd_offload, 1225 struct netlink_ext_ack *extack) 1226 { 1227 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1228 struct dsa_port *cpu_dp = dp->cpu_dp; 1229 u32 port_bitmap = BIT(cpu_dp->index); 1230 struct mt7530_priv *priv = ds->priv; 1231 1232 mutex_lock(&priv->reg_mutex); 1233 1234 dsa_switch_for_each_user_port(other_dp, ds) { 1235 int other_port = other_dp->index; 1236 1237 if (dp == other_dp) 1238 continue; 1239 1240 /* Add this port to the port matrix of the other ports in the 1241 * same bridge. If the port is disabled, port matrix is kept 1242 * and not being setup until the port becomes enabled. 1243 */ 1244 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1245 continue; 1246 1247 if (priv->ports[other_port].enable) 1248 mt7530_set(priv, MT7530_PCR_P(other_port), 1249 PCR_MATRIX(BIT(port))); 1250 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); 1251 1252 port_bitmap |= BIT(other_port); 1253 } 1254 1255 /* Add the all other ports to this port matrix. */ 1256 if (priv->ports[port].enable) 1257 mt7530_rmw(priv, MT7530_PCR_P(port), 1258 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1259 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1260 1261 /* Set to fallback mode for independent VLAN learning */ 1262 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1263 MT7530_PORT_FALLBACK_MODE); 1264 1265 mutex_unlock(&priv->reg_mutex); 1266 1267 return 0; 1268 } 1269 1270 static void 1271 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1272 { 1273 struct mt7530_priv *priv = ds->priv; 1274 bool all_user_ports_removed = true; 1275 int i; 1276 1277 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1278 * bridge. Don't set standalone ports to fallback mode. 1279 */ 1280 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1281 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1282 MT7530_PORT_FALLBACK_MODE); 1283 1284 mt7530_rmw(priv, MT7530_PVC_P(port), 1285 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1286 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1287 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1288 MT7530_VLAN_ACC_ALL); 1289 1290 /* Set PVID to 0 */ 1291 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1292 G0_PORT_VID_DEF); 1293 1294 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1295 if (dsa_is_user_port(ds, i) && 1296 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1297 all_user_ports_removed = false; 1298 break; 1299 } 1300 } 1301 1302 /* CPU port also does the same thing until all user ports belonging to 1303 * the CPU port get out of VLAN filtering mode. 1304 */ 1305 if (all_user_ports_removed) { 1306 struct dsa_port *dp = dsa_to_port(ds, port); 1307 struct dsa_port *cpu_dp = dp->cpu_dp; 1308 1309 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1310 PCR_MATRIX(dsa_user_ports(priv->ds))); 1311 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1312 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1313 } 1314 } 1315 1316 static void 1317 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1318 { 1319 struct mt7530_priv *priv = ds->priv; 1320 1321 /* Trapped into security mode allows packet forwarding through VLAN 1322 * table lookup. 1323 */ 1324 if (dsa_is_user_port(ds, port)) { 1325 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1326 MT7530_PORT_SECURITY_MODE); 1327 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1328 G0_PORT_VID(priv->ports[port].pvid)); 1329 1330 /* Only accept tagged frames if PVID is not set */ 1331 if (!priv->ports[port].pvid) 1332 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1333 MT7530_VLAN_ACC_TAGGED); 1334 1335 /* Set the port as a user port which is to be able to recognize 1336 * VID from incoming packets before fetching entry within the 1337 * VLAN table. 1338 */ 1339 mt7530_rmw(priv, MT7530_PVC_P(port), 1340 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1341 VLAN_ATTR(MT7530_VLAN_USER) | 1342 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1343 } else { 1344 /* Also set CPU ports to the "user" VLAN port attribute, to 1345 * allow VLAN classification, but keep the EG_TAG attribute as 1346 * "consistent" (i.o.w. don't change its value) for packets 1347 * received by the switch from the CPU, so that tagged packets 1348 * are forwarded to user ports as tagged, and untagged as 1349 * untagged. 1350 */ 1351 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1352 VLAN_ATTR(MT7530_VLAN_USER)); 1353 } 1354 } 1355 1356 static void 1357 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1358 struct dsa_bridge bridge) 1359 { 1360 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1361 struct dsa_port *cpu_dp = dp->cpu_dp; 1362 struct mt7530_priv *priv = ds->priv; 1363 1364 mutex_lock(&priv->reg_mutex); 1365 1366 dsa_switch_for_each_user_port(other_dp, ds) { 1367 int other_port = other_dp->index; 1368 1369 if (dp == other_dp) 1370 continue; 1371 1372 /* Remove this port from the port matrix of the other ports 1373 * in the same bridge. If the port is disabled, port matrix 1374 * is kept and not being setup until the port becomes enabled. 1375 */ 1376 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1377 continue; 1378 1379 if (priv->ports[other_port].enable) 1380 mt7530_clear(priv, MT7530_PCR_P(other_port), 1381 PCR_MATRIX(BIT(port))); 1382 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); 1383 } 1384 1385 /* Set the cpu port to be the only one in the port matrix of 1386 * this port. 1387 */ 1388 if (priv->ports[port].enable) 1389 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1390 PCR_MATRIX(BIT(cpu_dp->index))); 1391 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); 1392 1393 /* When a port is removed from the bridge, the port would be set up 1394 * back to the default as is at initial boot which is a VLAN-unaware 1395 * port. 1396 */ 1397 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1398 MT7530_PORT_MATRIX_MODE); 1399 1400 mutex_unlock(&priv->reg_mutex); 1401 } 1402 1403 static int 1404 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1405 const unsigned char *addr, u16 vid, 1406 struct dsa_db db) 1407 { 1408 struct mt7530_priv *priv = ds->priv; 1409 int ret; 1410 u8 port_mask = BIT(port); 1411 1412 mutex_lock(&priv->reg_mutex); 1413 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1414 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1415 mutex_unlock(&priv->reg_mutex); 1416 1417 return ret; 1418 } 1419 1420 static int 1421 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1422 const unsigned char *addr, u16 vid, 1423 struct dsa_db db) 1424 { 1425 struct mt7530_priv *priv = ds->priv; 1426 int ret; 1427 u8 port_mask = BIT(port); 1428 1429 mutex_lock(&priv->reg_mutex); 1430 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1431 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1432 mutex_unlock(&priv->reg_mutex); 1433 1434 return ret; 1435 } 1436 1437 static int 1438 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1439 dsa_fdb_dump_cb_t *cb, void *data) 1440 { 1441 struct mt7530_priv *priv = ds->priv; 1442 struct mt7530_fdb _fdb = { 0 }; 1443 int cnt = MT7530_NUM_FDB_RECORDS; 1444 int ret = 0; 1445 u32 rsp = 0; 1446 1447 mutex_lock(&priv->reg_mutex); 1448 1449 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1450 if (ret < 0) 1451 goto err; 1452 1453 do { 1454 if (rsp & ATC_SRCH_HIT) { 1455 mt7530_fdb_read(priv, &_fdb); 1456 if (_fdb.port_mask & BIT(port)) { 1457 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1458 data); 1459 if (ret < 0) 1460 break; 1461 } 1462 } 1463 } while (--cnt && 1464 !(rsp & ATC_SRCH_END) && 1465 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1466 err: 1467 mutex_unlock(&priv->reg_mutex); 1468 1469 return 0; 1470 } 1471 1472 static int 1473 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1474 const struct switchdev_obj_port_mdb *mdb, 1475 struct dsa_db db) 1476 { 1477 struct mt7530_priv *priv = ds->priv; 1478 const u8 *addr = mdb->addr; 1479 u16 vid = mdb->vid; 1480 u8 port_mask = 0; 1481 int ret; 1482 1483 mutex_lock(&priv->reg_mutex); 1484 1485 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1486 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1487 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1488 & PORT_MAP_MASK; 1489 1490 port_mask |= BIT(port); 1491 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1492 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1493 1494 mutex_unlock(&priv->reg_mutex); 1495 1496 return ret; 1497 } 1498 1499 static int 1500 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1501 const struct switchdev_obj_port_mdb *mdb, 1502 struct dsa_db db) 1503 { 1504 struct mt7530_priv *priv = ds->priv; 1505 const u8 *addr = mdb->addr; 1506 u16 vid = mdb->vid; 1507 u8 port_mask = 0; 1508 int ret; 1509 1510 mutex_lock(&priv->reg_mutex); 1511 1512 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1513 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1514 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1515 & PORT_MAP_MASK; 1516 1517 port_mask &= ~BIT(port); 1518 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1519 port_mask ? STATIC_ENT : STATIC_EMP); 1520 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1521 1522 mutex_unlock(&priv->reg_mutex); 1523 1524 return ret; 1525 } 1526 1527 static int 1528 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1529 { 1530 struct mt7530_dummy_poll p; 1531 u32 val; 1532 int ret; 1533 1534 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1535 mt7530_write(priv, MT7530_VTCR, val); 1536 1537 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1538 ret = readx_poll_timeout(_mt7530_read, &p, val, 1539 !(val & VTCR_BUSY), 20, 20000); 1540 if (ret < 0) { 1541 dev_err(priv->dev, "poll timeout\n"); 1542 return ret; 1543 } 1544 1545 val = mt7530_read(priv, MT7530_VTCR); 1546 if (val & VTCR_INVALID) { 1547 dev_err(priv->dev, "read VTCR invalid\n"); 1548 return -EINVAL; 1549 } 1550 1551 return 0; 1552 } 1553 1554 static int 1555 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1556 struct netlink_ext_ack *extack) 1557 { 1558 struct dsa_port *dp = dsa_to_port(ds, port); 1559 struct dsa_port *cpu_dp = dp->cpu_dp; 1560 1561 if (vlan_filtering) { 1562 /* The port is being kept as VLAN-unaware port when bridge is 1563 * set up with vlan_filtering not being set, Otherwise, the 1564 * port and the corresponding CPU port is required the setup 1565 * for becoming a VLAN-aware port. 1566 */ 1567 mt7530_port_set_vlan_aware(ds, port); 1568 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1569 } else { 1570 mt7530_port_set_vlan_unaware(ds, port); 1571 } 1572 1573 return 0; 1574 } 1575 1576 static void 1577 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1578 struct mt7530_hw_vlan_entry *entry) 1579 { 1580 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1581 u8 new_members; 1582 u32 val; 1583 1584 new_members = entry->old_members | BIT(entry->port); 1585 1586 /* Validate the entry with independent learning, create egress tag per 1587 * VLAN and joining the port as one of the port members. 1588 */ 1589 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1590 VLAN_VALID; 1591 mt7530_write(priv, MT7530_VAWD1, val); 1592 1593 /* Decide whether adding tag or not for those outgoing packets from the 1594 * port inside the VLAN. 1595 * CPU port is always taken as a tagged port for serving more than one 1596 * VLANs across and also being applied with egress type stack mode for 1597 * that VLAN tags would be appended after hardware special tag used as 1598 * DSA tag. 1599 */ 1600 if (dsa_port_is_cpu(dp)) 1601 val = MT7530_VLAN_EGRESS_STACK; 1602 else if (entry->untagged) 1603 val = MT7530_VLAN_EGRESS_UNTAG; 1604 else 1605 val = MT7530_VLAN_EGRESS_TAG; 1606 mt7530_rmw(priv, MT7530_VAWD2, 1607 ETAG_CTRL_P_MASK(entry->port), 1608 ETAG_CTRL_P(entry->port, val)); 1609 } 1610 1611 static void 1612 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1613 struct mt7530_hw_vlan_entry *entry) 1614 { 1615 u8 new_members; 1616 u32 val; 1617 1618 new_members = entry->old_members & ~BIT(entry->port); 1619 1620 val = mt7530_read(priv, MT7530_VAWD1); 1621 if (!(val & VLAN_VALID)) { 1622 dev_err(priv->dev, 1623 "Cannot be deleted due to invalid entry\n"); 1624 return; 1625 } 1626 1627 if (new_members) { 1628 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1629 VLAN_VALID; 1630 mt7530_write(priv, MT7530_VAWD1, val); 1631 } else { 1632 mt7530_write(priv, MT7530_VAWD1, 0); 1633 mt7530_write(priv, MT7530_VAWD2, 0); 1634 } 1635 } 1636 1637 static void 1638 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1639 struct mt7530_hw_vlan_entry *entry, 1640 mt7530_vlan_op vlan_op) 1641 { 1642 u32 val; 1643 1644 /* Fetch entry */ 1645 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1646 1647 val = mt7530_read(priv, MT7530_VAWD1); 1648 1649 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1650 1651 /* Manipulate entry */ 1652 vlan_op(priv, entry); 1653 1654 /* Flush result to hardware */ 1655 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1656 } 1657 1658 static int 1659 mt7530_setup_vlan0(struct mt7530_priv *priv) 1660 { 1661 u32 val; 1662 1663 /* Validate the entry with independent learning, keep the original 1664 * ingress tag attribute. 1665 */ 1666 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1667 VLAN_VALID; 1668 mt7530_write(priv, MT7530_VAWD1, val); 1669 1670 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1671 } 1672 1673 static int 1674 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1675 const struct switchdev_obj_port_vlan *vlan, 1676 struct netlink_ext_ack *extack) 1677 { 1678 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1679 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1680 struct mt7530_hw_vlan_entry new_entry; 1681 struct mt7530_priv *priv = ds->priv; 1682 1683 mutex_lock(&priv->reg_mutex); 1684 1685 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1686 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1687 1688 if (pvid) { 1689 priv->ports[port].pvid = vlan->vid; 1690 1691 /* Accept all frames if PVID is set */ 1692 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1693 MT7530_VLAN_ACC_ALL); 1694 1695 /* Only configure PVID if VLAN filtering is enabled */ 1696 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1697 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1698 G0_PORT_VID_MASK, 1699 G0_PORT_VID(vlan->vid)); 1700 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1701 /* This VLAN is overwritten without PVID, so unset it */ 1702 priv->ports[port].pvid = G0_PORT_VID_DEF; 1703 1704 /* Only accept tagged frames if the port is VLAN-aware */ 1705 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1706 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1707 MT7530_VLAN_ACC_TAGGED); 1708 1709 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1710 G0_PORT_VID_DEF); 1711 } 1712 1713 mutex_unlock(&priv->reg_mutex); 1714 1715 return 0; 1716 } 1717 1718 static int 1719 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1720 const struct switchdev_obj_port_vlan *vlan) 1721 { 1722 struct mt7530_hw_vlan_entry target_entry; 1723 struct mt7530_priv *priv = ds->priv; 1724 1725 mutex_lock(&priv->reg_mutex); 1726 1727 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1728 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1729 mt7530_hw_vlan_del); 1730 1731 /* PVID is being restored to the default whenever the PVID port 1732 * is being removed from the VLAN. 1733 */ 1734 if (priv->ports[port].pvid == vlan->vid) { 1735 priv->ports[port].pvid = G0_PORT_VID_DEF; 1736 1737 /* Only accept tagged frames if the port is VLAN-aware */ 1738 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1739 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1740 MT7530_VLAN_ACC_TAGGED); 1741 1742 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1743 G0_PORT_VID_DEF); 1744 } 1745 1746 1747 mutex_unlock(&priv->reg_mutex); 1748 1749 return 0; 1750 } 1751 1752 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1753 { 1754 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1755 MIRROR_PORT(val); 1756 } 1757 1758 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1759 { 1760 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1761 MIRROR_PORT(val); 1762 } 1763 1764 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1765 struct dsa_mall_mirror_tc_entry *mirror, 1766 bool ingress, struct netlink_ext_ack *extack) 1767 { 1768 struct mt7530_priv *priv = ds->priv; 1769 int monitor_port; 1770 u32 val; 1771 1772 /* Check for existent entry */ 1773 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1774 return -EEXIST; 1775 1776 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1777 1778 /* MT7530 only supports one monitor port */ 1779 monitor_port = mt753x_mirror_port_get(priv->id, val); 1780 if (val & MT753X_MIRROR_EN(priv->id) && 1781 monitor_port != mirror->to_local_port) 1782 return -EEXIST; 1783 1784 val |= MT753X_MIRROR_EN(priv->id); 1785 val &= ~MT753X_MIRROR_MASK(priv->id); 1786 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1787 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1788 1789 val = mt7530_read(priv, MT7530_PCR_P(port)); 1790 if (ingress) { 1791 val |= PORT_RX_MIR; 1792 priv->mirror_rx |= BIT(port); 1793 } else { 1794 val |= PORT_TX_MIR; 1795 priv->mirror_tx |= BIT(port); 1796 } 1797 mt7530_write(priv, MT7530_PCR_P(port), val); 1798 1799 return 0; 1800 } 1801 1802 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1803 struct dsa_mall_mirror_tc_entry *mirror) 1804 { 1805 struct mt7530_priv *priv = ds->priv; 1806 u32 val; 1807 1808 val = mt7530_read(priv, MT7530_PCR_P(port)); 1809 if (mirror->ingress) { 1810 val &= ~PORT_RX_MIR; 1811 priv->mirror_rx &= ~BIT(port); 1812 } else { 1813 val &= ~PORT_TX_MIR; 1814 priv->mirror_tx &= ~BIT(port); 1815 } 1816 mt7530_write(priv, MT7530_PCR_P(port), val); 1817 1818 if (!priv->mirror_rx && !priv->mirror_tx) { 1819 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1820 val &= ~MT753X_MIRROR_EN(priv->id); 1821 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1822 } 1823 } 1824 1825 static enum dsa_tag_protocol 1826 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1827 enum dsa_tag_protocol mp) 1828 { 1829 return DSA_TAG_PROTO_MTK; 1830 } 1831 1832 #ifdef CONFIG_GPIOLIB 1833 static inline u32 1834 mt7530_gpio_to_bit(unsigned int offset) 1835 { 1836 /* Map GPIO offset to register bit 1837 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1838 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1839 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1840 * [14:12] port 3 LED 0..2 as GPIO 9..11 1841 * [18:16] port 4 LED 0..2 as GPIO 12..14 1842 */ 1843 return BIT(offset + offset / 3); 1844 } 1845 1846 static int 1847 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1848 { 1849 struct mt7530_priv *priv = gpiochip_get_data(gc); 1850 u32 bit = mt7530_gpio_to_bit(offset); 1851 1852 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1853 } 1854 1855 static void 1856 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1857 { 1858 struct mt7530_priv *priv = gpiochip_get_data(gc); 1859 u32 bit = mt7530_gpio_to_bit(offset); 1860 1861 if (value) 1862 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1863 else 1864 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1865 } 1866 1867 static int 1868 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1869 { 1870 struct mt7530_priv *priv = gpiochip_get_data(gc); 1871 u32 bit = mt7530_gpio_to_bit(offset); 1872 1873 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1874 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1875 } 1876 1877 static int 1878 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1879 { 1880 struct mt7530_priv *priv = gpiochip_get_data(gc); 1881 u32 bit = mt7530_gpio_to_bit(offset); 1882 1883 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1884 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1885 1886 return 0; 1887 } 1888 1889 static int 1890 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1891 { 1892 struct mt7530_priv *priv = gpiochip_get_data(gc); 1893 u32 bit = mt7530_gpio_to_bit(offset); 1894 1895 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1896 1897 if (value) 1898 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1899 else 1900 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1901 1902 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1903 1904 return 0; 1905 } 1906 1907 static int 1908 mt7530_setup_gpio(struct mt7530_priv *priv) 1909 { 1910 struct device *dev = priv->dev; 1911 struct gpio_chip *gc; 1912 1913 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1914 if (!gc) 1915 return -ENOMEM; 1916 1917 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1918 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1919 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1920 1921 gc->label = "mt7530"; 1922 gc->parent = dev; 1923 gc->owner = THIS_MODULE; 1924 gc->get_direction = mt7530_gpio_get_direction; 1925 gc->direction_input = mt7530_gpio_direction_input; 1926 gc->direction_output = mt7530_gpio_direction_output; 1927 gc->get = mt7530_gpio_get; 1928 gc->set = mt7530_gpio_set; 1929 gc->base = -1; 1930 gc->ngpio = 15; 1931 gc->can_sleep = true; 1932 1933 return devm_gpiochip_add_data(dev, gc, priv); 1934 } 1935 #endif /* CONFIG_GPIOLIB */ 1936 1937 static irqreturn_t 1938 mt7530_irq_thread_fn(int irq, void *dev_id) 1939 { 1940 struct mt7530_priv *priv = dev_id; 1941 bool handled = false; 1942 u32 val; 1943 int p; 1944 1945 mt7530_mutex_lock(priv); 1946 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1947 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1948 mt7530_mutex_unlock(priv); 1949 1950 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1951 if (BIT(p) & val) { 1952 unsigned int irq; 1953 1954 irq = irq_find_mapping(priv->irq_domain, p); 1955 handle_nested_irq(irq); 1956 handled = true; 1957 } 1958 } 1959 1960 return IRQ_RETVAL(handled); 1961 } 1962 1963 static void 1964 mt7530_irq_mask(struct irq_data *d) 1965 { 1966 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1967 1968 priv->irq_enable &= ~BIT(d->hwirq); 1969 } 1970 1971 static void 1972 mt7530_irq_unmask(struct irq_data *d) 1973 { 1974 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1975 1976 priv->irq_enable |= BIT(d->hwirq); 1977 } 1978 1979 static void 1980 mt7530_irq_bus_lock(struct irq_data *d) 1981 { 1982 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1983 1984 mt7530_mutex_lock(priv); 1985 } 1986 1987 static void 1988 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1989 { 1990 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1991 1992 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1993 mt7530_mutex_unlock(priv); 1994 } 1995 1996 static struct irq_chip mt7530_irq_chip = { 1997 .name = KBUILD_MODNAME, 1998 .irq_mask = mt7530_irq_mask, 1999 .irq_unmask = mt7530_irq_unmask, 2000 .irq_bus_lock = mt7530_irq_bus_lock, 2001 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 2002 }; 2003 2004 static int 2005 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 2006 irq_hw_number_t hwirq) 2007 { 2008 irq_set_chip_data(irq, domain->host_data); 2009 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 2010 irq_set_nested_thread(irq, true); 2011 irq_set_noprobe(irq); 2012 2013 return 0; 2014 } 2015 2016 static const struct irq_domain_ops mt7530_irq_domain_ops = { 2017 .map = mt7530_irq_map, 2018 .xlate = irq_domain_xlate_onecell, 2019 }; 2020 2021 static void 2022 mt7988_irq_mask(struct irq_data *d) 2023 { 2024 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2025 2026 priv->irq_enable &= ~BIT(d->hwirq); 2027 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2028 } 2029 2030 static void 2031 mt7988_irq_unmask(struct irq_data *d) 2032 { 2033 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2034 2035 priv->irq_enable |= BIT(d->hwirq); 2036 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2037 } 2038 2039 static struct irq_chip mt7988_irq_chip = { 2040 .name = KBUILD_MODNAME, 2041 .irq_mask = mt7988_irq_mask, 2042 .irq_unmask = mt7988_irq_unmask, 2043 }; 2044 2045 static int 2046 mt7988_irq_map(struct irq_domain *domain, unsigned int irq, 2047 irq_hw_number_t hwirq) 2048 { 2049 irq_set_chip_data(irq, domain->host_data); 2050 irq_set_chip_and_handler(irq, &mt7988_irq_chip, handle_simple_irq); 2051 irq_set_nested_thread(irq, true); 2052 irq_set_noprobe(irq); 2053 2054 return 0; 2055 } 2056 2057 static const struct irq_domain_ops mt7988_irq_domain_ops = { 2058 .map = mt7988_irq_map, 2059 .xlate = irq_domain_xlate_onecell, 2060 }; 2061 2062 static void 2063 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 2064 { 2065 struct dsa_switch *ds = priv->ds; 2066 int p; 2067 2068 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2069 if (BIT(p) & ds->phys_mii_mask) { 2070 unsigned int irq; 2071 2072 irq = irq_create_mapping(priv->irq_domain, p); 2073 ds->slave_mii_bus->irq[p] = irq; 2074 } 2075 } 2076 } 2077 2078 static int 2079 mt7530_setup_irq(struct mt7530_priv *priv) 2080 { 2081 struct device *dev = priv->dev; 2082 struct device_node *np = dev->of_node; 2083 int ret; 2084 2085 if (!of_property_read_bool(np, "interrupt-controller")) { 2086 dev_info(dev, "no interrupt support\n"); 2087 return 0; 2088 } 2089 2090 priv->irq = of_irq_get(np, 0); 2091 if (priv->irq <= 0) { 2092 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 2093 return priv->irq ? : -EINVAL; 2094 } 2095 2096 if (priv->id == ID_MT7988) 2097 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2098 &mt7988_irq_domain_ops, 2099 priv); 2100 else 2101 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2102 &mt7530_irq_domain_ops, 2103 priv); 2104 2105 if (!priv->irq_domain) { 2106 dev_err(dev, "failed to create IRQ domain\n"); 2107 return -ENOMEM; 2108 } 2109 2110 /* This register must be set for MT7530 to properly fire interrupts */ 2111 if (priv->id != ID_MT7531) 2112 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2113 2114 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2115 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2116 if (ret) { 2117 irq_domain_remove(priv->irq_domain); 2118 dev_err(dev, "failed to request IRQ: %d\n", ret); 2119 return ret; 2120 } 2121 2122 return 0; 2123 } 2124 2125 static void 2126 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2127 { 2128 int p; 2129 2130 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2131 if (BIT(p) & priv->ds->phys_mii_mask) { 2132 unsigned int irq; 2133 2134 irq = irq_find_mapping(priv->irq_domain, p); 2135 irq_dispose_mapping(irq); 2136 } 2137 } 2138 } 2139 2140 static void 2141 mt7530_free_irq_common(struct mt7530_priv *priv) 2142 { 2143 free_irq(priv->irq, priv); 2144 irq_domain_remove(priv->irq_domain); 2145 } 2146 2147 static void 2148 mt7530_free_irq(struct mt7530_priv *priv) 2149 { 2150 mt7530_free_mdio_irq(priv); 2151 mt7530_free_irq_common(priv); 2152 } 2153 2154 static int 2155 mt7530_setup_mdio(struct mt7530_priv *priv) 2156 { 2157 struct dsa_switch *ds = priv->ds; 2158 struct device *dev = priv->dev; 2159 struct mii_bus *bus; 2160 static int idx; 2161 int ret; 2162 2163 bus = devm_mdiobus_alloc(dev); 2164 if (!bus) 2165 return -ENOMEM; 2166 2167 ds->slave_mii_bus = bus; 2168 bus->priv = priv; 2169 bus->name = KBUILD_MODNAME "-mii"; 2170 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2171 bus->read = mt753x_phy_read_c22; 2172 bus->write = mt753x_phy_write_c22; 2173 bus->read_c45 = mt753x_phy_read_c45; 2174 bus->write_c45 = mt753x_phy_write_c45; 2175 bus->parent = dev; 2176 bus->phy_mask = ~ds->phys_mii_mask; 2177 2178 if (priv->irq) 2179 mt7530_setup_mdio_irq(priv); 2180 2181 ret = devm_mdiobus_register(dev, bus); 2182 if (ret) { 2183 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2184 if (priv->irq) 2185 mt7530_free_mdio_irq(priv); 2186 } 2187 2188 return ret; 2189 } 2190 2191 static int 2192 mt7530_setup(struct dsa_switch *ds) 2193 { 2194 struct mt7530_priv *priv = ds->priv; 2195 struct device_node *dn = NULL; 2196 struct device_node *phy_node; 2197 struct device_node *mac_np; 2198 struct mt7530_dummy_poll p; 2199 phy_interface_t interface; 2200 struct dsa_port *cpu_dp; 2201 u32 id, val; 2202 int ret, i; 2203 2204 /* The parent node of master netdev which holds the common system 2205 * controller also is the container for two GMACs nodes representing 2206 * as two netdev instances. 2207 */ 2208 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2209 dn = cpu_dp->master->dev.of_node->parent; 2210 /* It doesn't matter which CPU port is found first, 2211 * their masters should share the same parent OF node 2212 */ 2213 break; 2214 } 2215 2216 if (!dn) { 2217 dev_err(ds->dev, "parent OF node of DSA master not found"); 2218 return -EINVAL; 2219 } 2220 2221 ds->assisted_learning_on_cpu_port = true; 2222 ds->mtu_enforcement_ingress = true; 2223 2224 if (priv->id == ID_MT7530) { 2225 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2226 ret = regulator_enable(priv->core_pwr); 2227 if (ret < 0) { 2228 dev_err(priv->dev, 2229 "Failed to enable core power: %d\n", ret); 2230 return ret; 2231 } 2232 2233 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2234 ret = regulator_enable(priv->io_pwr); 2235 if (ret < 0) { 2236 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2237 ret); 2238 return ret; 2239 } 2240 } 2241 2242 /* Reset whole chip through gpio pin or memory-mapped registers for 2243 * different type of hardware 2244 */ 2245 if (priv->mcm) { 2246 reset_control_assert(priv->rstc); 2247 usleep_range(1000, 1100); 2248 reset_control_deassert(priv->rstc); 2249 } else { 2250 gpiod_set_value_cansleep(priv->reset, 0); 2251 usleep_range(1000, 1100); 2252 gpiod_set_value_cansleep(priv->reset, 1); 2253 } 2254 2255 /* Waiting for MT7530 got to stable */ 2256 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2257 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2258 20, 1000000); 2259 if (ret < 0) { 2260 dev_err(priv->dev, "reset timeout\n"); 2261 return ret; 2262 } 2263 2264 id = mt7530_read(priv, MT7530_CREV); 2265 id >>= CHIP_NAME_SHIFT; 2266 if (id != MT7530_ID) { 2267 dev_err(priv->dev, "chip %x can't be supported\n", id); 2268 return -ENODEV; 2269 } 2270 2271 /* Reset the switch through internal reset */ 2272 mt7530_write(priv, MT7530_SYS_CTRL, 2273 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2274 SYS_CTRL_REG_RST); 2275 2276 mt7530_pll_setup(priv); 2277 2278 /* Lower Tx driving for TRGMII path */ 2279 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2280 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 2281 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2282 2283 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2284 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 2285 RD_TAP_MASK, RD_TAP(16)); 2286 2287 /* Enable port 6 */ 2288 val = mt7530_read(priv, MT7530_MHWTRAP); 2289 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2290 val |= MHWTRAP_MANUAL; 2291 mt7530_write(priv, MT7530_MHWTRAP, val); 2292 2293 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2294 2295 mt753x_trap_frames(priv); 2296 2297 /* Enable and reset MIB counters */ 2298 mt7530_mib_reset(ds); 2299 2300 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2301 /* Disable forwarding by default on all ports */ 2302 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2303 PCR_MATRIX_CLR); 2304 2305 /* Disable learning by default on all ports */ 2306 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2307 2308 if (dsa_is_cpu_port(ds, i)) { 2309 ret = mt753x_cpu_port_enable(ds, i); 2310 if (ret) 2311 return ret; 2312 } else { 2313 mt7530_port_disable(ds, i); 2314 2315 /* Set default PVID to 0 on all user ports */ 2316 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2317 G0_PORT_VID_DEF); 2318 } 2319 /* Enable consistent egress tag */ 2320 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2321 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2322 } 2323 2324 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2325 ret = mt7530_setup_vlan0(priv); 2326 if (ret) 2327 return ret; 2328 2329 /* Setup port 5 */ 2330 priv->p5_intf_sel = P5_DISABLED; 2331 interface = PHY_INTERFACE_MODE_NA; 2332 2333 if (!dsa_is_unused_port(ds, 5)) { 2334 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2335 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 2336 if (ret && ret != -ENODEV) 2337 return ret; 2338 } else { 2339 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 2340 for_each_child_of_node(dn, mac_np) { 2341 if (!of_device_is_compatible(mac_np, 2342 "mediatek,eth-mac")) 2343 continue; 2344 2345 ret = of_property_read_u32(mac_np, "reg", &id); 2346 if (ret < 0 || id != 1) 2347 continue; 2348 2349 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2350 if (!phy_node) 2351 continue; 2352 2353 if (phy_node->parent == priv->dev->of_node->parent) { 2354 ret = of_get_phy_mode(mac_np, &interface); 2355 if (ret && ret != -ENODEV) { 2356 of_node_put(mac_np); 2357 of_node_put(phy_node); 2358 return ret; 2359 } 2360 id = of_mdio_parse_addr(ds->dev, phy_node); 2361 if (id == 0) 2362 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2363 if (id == 4) 2364 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2365 } 2366 of_node_put(mac_np); 2367 of_node_put(phy_node); 2368 break; 2369 } 2370 } 2371 2372 #ifdef CONFIG_GPIOLIB 2373 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2374 ret = mt7530_setup_gpio(priv); 2375 if (ret) 2376 return ret; 2377 } 2378 #endif /* CONFIG_GPIOLIB */ 2379 2380 mt7530_setup_port5(ds, interface); 2381 2382 /* Flush the FDB table */ 2383 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2384 if (ret < 0) 2385 return ret; 2386 2387 return 0; 2388 } 2389 2390 static int 2391 mt7531_setup_common(struct dsa_switch *ds) 2392 { 2393 struct mt7530_priv *priv = ds->priv; 2394 int ret, i; 2395 2396 mt753x_trap_frames(priv); 2397 2398 /* Enable and reset MIB counters */ 2399 mt7530_mib_reset(ds); 2400 2401 /* Disable flooding on all ports */ 2402 mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | 2403 UNU_FFP_MASK); 2404 2405 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2406 /* Disable forwarding by default on all ports */ 2407 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2408 PCR_MATRIX_CLR); 2409 2410 /* Disable learning by default on all ports */ 2411 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2412 2413 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2414 2415 if (dsa_is_cpu_port(ds, i)) { 2416 ret = mt753x_cpu_port_enable(ds, i); 2417 if (ret) 2418 return ret; 2419 } else { 2420 mt7530_port_disable(ds, i); 2421 2422 /* Set default PVID to 0 on all user ports */ 2423 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2424 G0_PORT_VID_DEF); 2425 } 2426 2427 /* Enable consistent egress tag */ 2428 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2429 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2430 } 2431 2432 /* Flush the FDB table */ 2433 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2434 if (ret < 0) 2435 return ret; 2436 2437 return 0; 2438 } 2439 2440 static int 2441 mt7531_setup(struct dsa_switch *ds) 2442 { 2443 struct mt7530_priv *priv = ds->priv; 2444 struct mt7530_dummy_poll p; 2445 u32 val, id; 2446 int ret, i; 2447 2448 /* Reset whole chip through gpio pin or memory-mapped registers for 2449 * different type of hardware 2450 */ 2451 if (priv->mcm) { 2452 reset_control_assert(priv->rstc); 2453 usleep_range(1000, 1100); 2454 reset_control_deassert(priv->rstc); 2455 } else { 2456 gpiod_set_value_cansleep(priv->reset, 0); 2457 usleep_range(1000, 1100); 2458 gpiod_set_value_cansleep(priv->reset, 1); 2459 } 2460 2461 /* Waiting for MT7530 got to stable */ 2462 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2463 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2464 20, 1000000); 2465 if (ret < 0) { 2466 dev_err(priv->dev, "reset timeout\n"); 2467 return ret; 2468 } 2469 2470 id = mt7530_read(priv, MT7531_CREV); 2471 id >>= CHIP_NAME_SHIFT; 2472 2473 if (id != MT7531_ID) { 2474 dev_err(priv->dev, "chip %x can't be supported\n", id); 2475 return -ENODEV; 2476 } 2477 2478 /* all MACs must be forced link-down before sw reset */ 2479 for (i = 0; i < MT7530_NUM_PORTS; i++) 2480 mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); 2481 2482 /* Reset the switch through internal reset */ 2483 mt7530_write(priv, MT7530_SYS_CTRL, 2484 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2485 SYS_CTRL_REG_RST); 2486 2487 mt7531_pll_setup(priv); 2488 2489 if (mt7531_dual_sgmii_supported(priv)) { 2490 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2491 2492 /* Let ds->slave_mii_bus be able to access external phy. */ 2493 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2494 MT7531_EXT_P_MDC_11); 2495 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2496 MT7531_EXT_P_MDIO_12); 2497 } else { 2498 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2499 } 2500 dev_dbg(ds->dev, "P5 support %s interface\n", 2501 p5_intf_modes(priv->p5_intf_sel)); 2502 2503 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2504 MT7531_GPIO0_INTERRUPT); 2505 2506 /* Let phylink decide the interface later. */ 2507 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2508 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2509 2510 /* Enable PHY core PLL, since phy_device has not yet been created 2511 * provided for phy_[read,write]_mmd_indirect is called, we provide 2512 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2513 * function. 2514 */ 2515 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2516 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2517 val |= MT7531_PHY_PLL_BYPASS_MODE; 2518 val &= ~MT7531_PHY_PLL_OFF; 2519 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2520 CORE_PLL_GROUP4, val); 2521 2522 mt7531_setup_common(ds); 2523 2524 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2525 ret = mt7530_setup_vlan0(priv); 2526 if (ret) 2527 return ret; 2528 2529 ds->assisted_learning_on_cpu_port = true; 2530 ds->mtu_enforcement_ingress = true; 2531 2532 return 0; 2533 } 2534 2535 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2536 struct phylink_config *config) 2537 { 2538 switch (port) { 2539 case 0 ... 4: /* Internal phy */ 2540 __set_bit(PHY_INTERFACE_MODE_GMII, 2541 config->supported_interfaces); 2542 break; 2543 2544 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2545 phy_interface_set_rgmii(config->supported_interfaces); 2546 __set_bit(PHY_INTERFACE_MODE_MII, 2547 config->supported_interfaces); 2548 __set_bit(PHY_INTERFACE_MODE_GMII, 2549 config->supported_interfaces); 2550 break; 2551 2552 case 6: /* 1st cpu port */ 2553 __set_bit(PHY_INTERFACE_MODE_RGMII, 2554 config->supported_interfaces); 2555 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2556 config->supported_interfaces); 2557 break; 2558 } 2559 } 2560 2561 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2562 { 2563 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2564 } 2565 2566 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2567 struct phylink_config *config) 2568 { 2569 struct mt7530_priv *priv = ds->priv; 2570 2571 switch (port) { 2572 case 0 ... 4: /* Internal phy */ 2573 __set_bit(PHY_INTERFACE_MODE_GMII, 2574 config->supported_interfaces); 2575 break; 2576 2577 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2578 if (mt7531_is_rgmii_port(priv, port)) { 2579 phy_interface_set_rgmii(config->supported_interfaces); 2580 break; 2581 } 2582 fallthrough; 2583 2584 case 6: /* 1st cpu port supports sgmii/8023z only */ 2585 __set_bit(PHY_INTERFACE_MODE_SGMII, 2586 config->supported_interfaces); 2587 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2588 config->supported_interfaces); 2589 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2590 config->supported_interfaces); 2591 2592 config->mac_capabilities |= MAC_2500FD; 2593 break; 2594 } 2595 } 2596 2597 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, 2598 struct phylink_config *config) 2599 { 2600 phy_interface_zero(config->supported_interfaces); 2601 2602 switch (port) { 2603 case 0 ... 4: /* Internal phy */ 2604 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2605 config->supported_interfaces); 2606 break; 2607 2608 case 6: 2609 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2610 config->supported_interfaces); 2611 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2612 MAC_10000FD; 2613 } 2614 } 2615 2616 static int 2617 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2618 { 2619 struct mt7530_priv *priv = ds->priv; 2620 2621 return priv->info->pad_setup(ds, state->interface); 2622 } 2623 2624 static int 2625 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2626 phy_interface_t interface) 2627 { 2628 struct mt7530_priv *priv = ds->priv; 2629 2630 /* Only need to setup port5. */ 2631 if (port != 5) 2632 return 0; 2633 2634 mt7530_setup_port5(priv->ds, interface); 2635 2636 return 0; 2637 } 2638 2639 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2640 phy_interface_t interface, 2641 struct phy_device *phydev) 2642 { 2643 u32 val; 2644 2645 if (!mt7531_is_rgmii_port(priv, port)) { 2646 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2647 port); 2648 return -EINVAL; 2649 } 2650 2651 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2652 val |= GP_CLK_EN; 2653 val &= ~GP_MODE_MASK; 2654 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2655 val &= ~CLK_SKEW_IN_MASK; 2656 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2657 val &= ~CLK_SKEW_OUT_MASK; 2658 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2659 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2660 2661 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2662 if (!phydev || phy_driver_is_genphy(phydev)) { 2663 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2664 switch (interface) { 2665 case PHY_INTERFACE_MODE_RGMII: 2666 val |= TXCLK_NO_REVERSE; 2667 val |= RXCLK_NO_DELAY; 2668 break; 2669 case PHY_INTERFACE_MODE_RGMII_RXID: 2670 val |= TXCLK_NO_REVERSE; 2671 break; 2672 case PHY_INTERFACE_MODE_RGMII_TXID: 2673 val |= RXCLK_NO_DELAY; 2674 break; 2675 case PHY_INTERFACE_MODE_RGMII_ID: 2676 break; 2677 default: 2678 return -EINVAL; 2679 } 2680 } 2681 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2682 2683 return 0; 2684 } 2685 2686 static bool mt753x_is_mac_port(u32 port) 2687 { 2688 return (port == 5 || port == 6); 2689 } 2690 2691 static int 2692 mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2693 phy_interface_t interface) 2694 { 2695 if (dsa_is_cpu_port(ds, port) && 2696 interface == PHY_INTERFACE_MODE_INTERNAL) 2697 return 0; 2698 2699 return -EINVAL; 2700 } 2701 2702 static int 2703 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2704 phy_interface_t interface) 2705 { 2706 struct mt7530_priv *priv = ds->priv; 2707 struct phy_device *phydev; 2708 struct dsa_port *dp; 2709 2710 if (!mt753x_is_mac_port(port)) { 2711 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2712 return -EINVAL; 2713 } 2714 2715 switch (interface) { 2716 case PHY_INTERFACE_MODE_RGMII: 2717 case PHY_INTERFACE_MODE_RGMII_ID: 2718 case PHY_INTERFACE_MODE_RGMII_RXID: 2719 case PHY_INTERFACE_MODE_RGMII_TXID: 2720 dp = dsa_to_port(ds, port); 2721 phydev = dp->slave->phydev; 2722 return mt7531_rgmii_setup(priv, port, interface, phydev); 2723 case PHY_INTERFACE_MODE_SGMII: 2724 case PHY_INTERFACE_MODE_NA: 2725 case PHY_INTERFACE_MODE_1000BASEX: 2726 case PHY_INTERFACE_MODE_2500BASEX: 2727 /* handled in SGMII PCS driver */ 2728 return 0; 2729 default: 2730 return -EINVAL; 2731 } 2732 2733 return -EINVAL; 2734 } 2735 2736 static int 2737 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2738 const struct phylink_link_state *state) 2739 { 2740 struct mt7530_priv *priv = ds->priv; 2741 2742 return priv->info->mac_port_config(ds, port, mode, state->interface); 2743 } 2744 2745 static struct phylink_pcs * 2746 mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port, 2747 phy_interface_t interface) 2748 { 2749 struct mt7530_priv *priv = ds->priv; 2750 2751 switch (interface) { 2752 case PHY_INTERFACE_MODE_TRGMII: 2753 return &priv->pcs[port].pcs; 2754 case PHY_INTERFACE_MODE_SGMII: 2755 case PHY_INTERFACE_MODE_1000BASEX: 2756 case PHY_INTERFACE_MODE_2500BASEX: 2757 return priv->ports[port].sgmii_pcs; 2758 default: 2759 return NULL; 2760 } 2761 } 2762 2763 static void 2764 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2765 const struct phylink_link_state *state) 2766 { 2767 struct mt7530_priv *priv = ds->priv; 2768 u32 mcr_cur, mcr_new; 2769 2770 switch (port) { 2771 case 0 ... 4: /* Internal phy */ 2772 if (state->interface != PHY_INTERFACE_MODE_GMII && 2773 state->interface != PHY_INTERFACE_MODE_INTERNAL) 2774 goto unsupported; 2775 break; 2776 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2777 if (priv->p5_interface == state->interface) 2778 break; 2779 2780 if (mt753x_mac_config(ds, port, mode, state) < 0) 2781 goto unsupported; 2782 2783 if (priv->p5_intf_sel != P5_DISABLED) 2784 priv->p5_interface = state->interface; 2785 break; 2786 case 6: /* 1st cpu port */ 2787 if (priv->p6_interface == state->interface) 2788 break; 2789 2790 mt753x_pad_setup(ds, state); 2791 2792 if (mt753x_mac_config(ds, port, mode, state) < 0) 2793 goto unsupported; 2794 2795 priv->p6_interface = state->interface; 2796 break; 2797 default: 2798 unsupported: 2799 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2800 __func__, phy_modes(state->interface), port); 2801 return; 2802 } 2803 2804 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2805 mcr_new = mcr_cur; 2806 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2807 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2808 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2809 2810 /* Are we connected to external phy */ 2811 if (port == 5 && dsa_is_user_port(ds, 5)) 2812 mcr_new |= PMCR_EXT_PHY; 2813 2814 if (mcr_new != mcr_cur) 2815 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2816 } 2817 2818 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2819 unsigned int mode, 2820 phy_interface_t interface) 2821 { 2822 struct mt7530_priv *priv = ds->priv; 2823 2824 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2825 } 2826 2827 static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs, 2828 unsigned int mode, 2829 phy_interface_t interface, 2830 int speed, int duplex) 2831 { 2832 if (pcs->ops->pcs_link_up) 2833 pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex); 2834 } 2835 2836 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2837 unsigned int mode, 2838 phy_interface_t interface, 2839 struct phy_device *phydev, 2840 int speed, int duplex, 2841 bool tx_pause, bool rx_pause) 2842 { 2843 struct mt7530_priv *priv = ds->priv; 2844 u32 mcr; 2845 2846 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2847 2848 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2849 * variants. 2850 */ 2851 if (interface == PHY_INTERFACE_MODE_INTERNAL || 2852 interface == PHY_INTERFACE_MODE_TRGMII || 2853 (phy_interface_mode_is_8023z(interface))) { 2854 speed = SPEED_1000; 2855 duplex = DUPLEX_FULL; 2856 } 2857 2858 switch (speed) { 2859 case SPEED_1000: 2860 mcr |= PMCR_FORCE_SPEED_1000; 2861 break; 2862 case SPEED_100: 2863 mcr |= PMCR_FORCE_SPEED_100; 2864 break; 2865 } 2866 if (duplex == DUPLEX_FULL) { 2867 mcr |= PMCR_FORCE_FDX; 2868 if (tx_pause) 2869 mcr |= PMCR_TX_FC_EN; 2870 if (rx_pause) 2871 mcr |= PMCR_RX_FC_EN; 2872 } 2873 2874 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { 2875 switch (speed) { 2876 case SPEED_1000: 2877 mcr |= PMCR_FORCE_EEE1G; 2878 break; 2879 case SPEED_100: 2880 mcr |= PMCR_FORCE_EEE100; 2881 break; 2882 } 2883 } 2884 2885 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2886 } 2887 2888 static int 2889 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2890 { 2891 struct mt7530_priv *priv = ds->priv; 2892 phy_interface_t interface; 2893 int speed; 2894 int ret; 2895 2896 switch (port) { 2897 case 5: 2898 if (mt7531_is_rgmii_port(priv, port)) 2899 interface = PHY_INTERFACE_MODE_RGMII; 2900 else 2901 interface = PHY_INTERFACE_MODE_2500BASEX; 2902 2903 priv->p5_interface = interface; 2904 break; 2905 case 6: 2906 interface = PHY_INTERFACE_MODE_2500BASEX; 2907 2908 priv->p6_interface = interface; 2909 break; 2910 default: 2911 return -EINVAL; 2912 } 2913 2914 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2915 speed = SPEED_2500; 2916 else 2917 speed = SPEED_1000; 2918 2919 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2920 if (ret) 2921 return ret; 2922 mt7530_write(priv, MT7530_PMCR_P(port), 2923 PMCR_CPU_PORT_SETTING(priv->id)); 2924 mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED, 2925 interface, speed, DUPLEX_FULL); 2926 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2927 speed, DUPLEX_FULL, true, true); 2928 2929 return 0; 2930 } 2931 2932 static int 2933 mt7988_cpu_port_config(struct dsa_switch *ds, int port) 2934 { 2935 struct mt7530_priv *priv = ds->priv; 2936 2937 mt7530_write(priv, MT7530_PMCR_P(port), 2938 PMCR_CPU_PORT_SETTING(priv->id)); 2939 2940 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, 2941 PHY_INTERFACE_MODE_INTERNAL, NULL, 2942 SPEED_10000, DUPLEX_FULL, true, true); 2943 2944 return 0; 2945 } 2946 2947 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 2948 struct phylink_config *config) 2949 { 2950 struct mt7530_priv *priv = ds->priv; 2951 2952 /* This switch only supports full-duplex at 1Gbps */ 2953 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2954 MAC_10 | MAC_100 | MAC_1000FD; 2955 2956 priv->info->mac_port_get_caps(ds, port, config); 2957 } 2958 2959 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 2960 unsigned long *supported, 2961 const struct phylink_link_state *state) 2962 { 2963 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 2964 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 2965 phy_interface_mode_is_8023z(state->interface)) 2966 phylink_clear(supported, Autoneg); 2967 2968 return 0; 2969 } 2970 2971 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, 2972 struct phylink_link_state *state) 2973 { 2974 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2975 int port = pcs_to_mt753x_pcs(pcs)->port; 2976 u32 pmsr; 2977 2978 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2979 2980 state->link = (pmsr & PMSR_LINK); 2981 state->an_complete = state->link; 2982 state->duplex = !!(pmsr & PMSR_DPX); 2983 2984 switch (pmsr & PMSR_SPEED_MASK) { 2985 case PMSR_SPEED_10: 2986 state->speed = SPEED_10; 2987 break; 2988 case PMSR_SPEED_100: 2989 state->speed = SPEED_100; 2990 break; 2991 case PMSR_SPEED_1000: 2992 state->speed = SPEED_1000; 2993 break; 2994 default: 2995 state->speed = SPEED_UNKNOWN; 2996 break; 2997 } 2998 2999 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 3000 if (pmsr & PMSR_RX_FC) 3001 state->pause |= MLO_PAUSE_RX; 3002 if (pmsr & PMSR_TX_FC) 3003 state->pause |= MLO_PAUSE_TX; 3004 } 3005 3006 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 3007 phy_interface_t interface, 3008 const unsigned long *advertising, 3009 bool permit_pause_to_mac) 3010 { 3011 return 0; 3012 } 3013 3014 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 3015 { 3016 } 3017 3018 static const struct phylink_pcs_ops mt7530_pcs_ops = { 3019 .pcs_validate = mt753x_pcs_validate, 3020 .pcs_get_state = mt7530_pcs_get_state, 3021 .pcs_config = mt753x_pcs_config, 3022 .pcs_an_restart = mt7530_pcs_an_restart, 3023 }; 3024 3025 static int 3026 mt753x_setup(struct dsa_switch *ds) 3027 { 3028 struct mt7530_priv *priv = ds->priv; 3029 int i, ret; 3030 3031 /* Initialise the PCS devices */ 3032 for (i = 0; i < priv->ds->num_ports; i++) { 3033 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3034 priv->pcs[i].pcs.neg_mode = true; 3035 priv->pcs[i].priv = priv; 3036 priv->pcs[i].port = i; 3037 } 3038 3039 ret = priv->info->sw_setup(ds); 3040 if (ret) 3041 return ret; 3042 3043 ret = mt7530_setup_irq(priv); 3044 if (ret) 3045 return ret; 3046 3047 ret = mt7530_setup_mdio(priv); 3048 if (ret && priv->irq) 3049 mt7530_free_irq_common(priv); 3050 3051 if (priv->create_sgmii) { 3052 ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv)); 3053 if (ret && priv->irq) 3054 mt7530_free_irq(priv); 3055 } 3056 3057 return ret; 3058 } 3059 3060 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3061 struct ethtool_eee *e) 3062 { 3063 struct mt7530_priv *priv = ds->priv; 3064 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 3065 3066 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3067 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 3068 3069 return 0; 3070 } 3071 3072 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3073 struct ethtool_eee *e) 3074 { 3075 struct mt7530_priv *priv = ds->priv; 3076 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3077 3078 if (e->tx_lpi_timer > 0xFFF) 3079 return -EINVAL; 3080 3081 set = SET_LPI_THRESH(e->tx_lpi_timer); 3082 if (!e->tx_lpi_enabled) 3083 /* Force LPI Mode without a delay */ 3084 set |= LPI_MODE_EN; 3085 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3086 3087 return 0; 3088 } 3089 3090 static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 3091 { 3092 return 0; 3093 } 3094 3095 static int mt7988_setup(struct dsa_switch *ds) 3096 { 3097 struct mt7530_priv *priv = ds->priv; 3098 3099 /* Reset the switch */ 3100 reset_control_assert(priv->rstc); 3101 usleep_range(20, 50); 3102 reset_control_deassert(priv->rstc); 3103 usleep_range(20, 50); 3104 3105 /* Reset the switch PHYs */ 3106 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST); 3107 3108 return mt7531_setup_common(ds); 3109 } 3110 3111 const struct dsa_switch_ops mt7530_switch_ops = { 3112 .get_tag_protocol = mtk_get_tag_protocol, 3113 .setup = mt753x_setup, 3114 .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, 3115 .get_strings = mt7530_get_strings, 3116 .get_ethtool_stats = mt7530_get_ethtool_stats, 3117 .get_sset_count = mt7530_get_sset_count, 3118 .set_ageing_time = mt7530_set_ageing_time, 3119 .port_enable = mt7530_port_enable, 3120 .port_disable = mt7530_port_disable, 3121 .port_change_mtu = mt7530_port_change_mtu, 3122 .port_max_mtu = mt7530_port_max_mtu, 3123 .port_stp_state_set = mt7530_stp_state_set, 3124 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3125 .port_bridge_flags = mt7530_port_bridge_flags, 3126 .port_bridge_join = mt7530_port_bridge_join, 3127 .port_bridge_leave = mt7530_port_bridge_leave, 3128 .port_fdb_add = mt7530_port_fdb_add, 3129 .port_fdb_del = mt7530_port_fdb_del, 3130 .port_fdb_dump = mt7530_port_fdb_dump, 3131 .port_mdb_add = mt7530_port_mdb_add, 3132 .port_mdb_del = mt7530_port_mdb_del, 3133 .port_vlan_filtering = mt7530_port_vlan_filtering, 3134 .port_vlan_add = mt7530_port_vlan_add, 3135 .port_vlan_del = mt7530_port_vlan_del, 3136 .port_mirror_add = mt753x_port_mirror_add, 3137 .port_mirror_del = mt753x_port_mirror_del, 3138 .phylink_get_caps = mt753x_phylink_get_caps, 3139 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs, 3140 .phylink_mac_config = mt753x_phylink_mac_config, 3141 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3142 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3143 .get_mac_eee = mt753x_get_mac_eee, 3144 .set_mac_eee = mt753x_set_mac_eee, 3145 }; 3146 EXPORT_SYMBOL_GPL(mt7530_switch_ops); 3147 3148 const struct mt753x_info mt753x_table[] = { 3149 [ID_MT7621] = { 3150 .id = ID_MT7621, 3151 .pcs_ops = &mt7530_pcs_ops, 3152 .sw_setup = mt7530_setup, 3153 .phy_read_c22 = mt7530_phy_read_c22, 3154 .phy_write_c22 = mt7530_phy_write_c22, 3155 .phy_read_c45 = mt7530_phy_read_c45, 3156 .phy_write_c45 = mt7530_phy_write_c45, 3157 .pad_setup = mt7530_pad_clk_setup, 3158 .mac_port_get_caps = mt7530_mac_port_get_caps, 3159 .mac_port_config = mt7530_mac_config, 3160 }, 3161 [ID_MT7530] = { 3162 .id = ID_MT7530, 3163 .pcs_ops = &mt7530_pcs_ops, 3164 .sw_setup = mt7530_setup, 3165 .phy_read_c22 = mt7530_phy_read_c22, 3166 .phy_write_c22 = mt7530_phy_write_c22, 3167 .phy_read_c45 = mt7530_phy_read_c45, 3168 .phy_write_c45 = mt7530_phy_write_c45, 3169 .pad_setup = mt7530_pad_clk_setup, 3170 .mac_port_get_caps = mt7530_mac_port_get_caps, 3171 .mac_port_config = mt7530_mac_config, 3172 }, 3173 [ID_MT7531] = { 3174 .id = ID_MT7531, 3175 .pcs_ops = &mt7530_pcs_ops, 3176 .sw_setup = mt7531_setup, 3177 .phy_read_c22 = mt7531_ind_c22_phy_read, 3178 .phy_write_c22 = mt7531_ind_c22_phy_write, 3179 .phy_read_c45 = mt7531_ind_c45_phy_read, 3180 .phy_write_c45 = mt7531_ind_c45_phy_write, 3181 .pad_setup = mt7531_pad_setup, 3182 .cpu_port_config = mt7531_cpu_port_config, 3183 .mac_port_get_caps = mt7531_mac_port_get_caps, 3184 .mac_port_config = mt7531_mac_config, 3185 }, 3186 [ID_MT7988] = { 3187 .id = ID_MT7988, 3188 .pcs_ops = &mt7530_pcs_ops, 3189 .sw_setup = mt7988_setup, 3190 .phy_read_c22 = mt7531_ind_c22_phy_read, 3191 .phy_write_c22 = mt7531_ind_c22_phy_write, 3192 .phy_read_c45 = mt7531_ind_c45_phy_read, 3193 .phy_write_c45 = mt7531_ind_c45_phy_write, 3194 .pad_setup = mt7988_pad_setup, 3195 .cpu_port_config = mt7988_cpu_port_config, 3196 .mac_port_get_caps = mt7988_mac_port_get_caps, 3197 .mac_port_config = mt7988_mac_config, 3198 }, 3199 }; 3200 EXPORT_SYMBOL_GPL(mt753x_table); 3201 3202 int 3203 mt7530_probe_common(struct mt7530_priv *priv) 3204 { 3205 struct device *dev = priv->dev; 3206 3207 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 3208 if (!priv->ds) 3209 return -ENOMEM; 3210 3211 priv->ds->dev = dev; 3212 priv->ds->num_ports = MT7530_NUM_PORTS; 3213 3214 /* Get the hardware identifier from the devicetree node. 3215 * We will need it for some of the clock and regulator setup. 3216 */ 3217 priv->info = of_device_get_match_data(dev); 3218 if (!priv->info) 3219 return -EINVAL; 3220 3221 /* Sanity check if these required device operations are filled 3222 * properly. 3223 */ 3224 if (!priv->info->sw_setup || !priv->info->pad_setup || 3225 !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || 3226 !priv->info->mac_port_get_caps || 3227 !priv->info->mac_port_config) 3228 return -EINVAL; 3229 3230 priv->id = priv->info->id; 3231 priv->dev = dev; 3232 priv->ds->priv = priv; 3233 priv->ds->ops = &mt7530_switch_ops; 3234 mutex_init(&priv->reg_mutex); 3235 dev_set_drvdata(dev, priv); 3236 3237 return 0; 3238 } 3239 EXPORT_SYMBOL_GPL(mt7530_probe_common); 3240 3241 void 3242 mt7530_remove_common(struct mt7530_priv *priv) 3243 { 3244 if (priv->irq) 3245 mt7530_free_irq(priv); 3246 3247 dsa_unregister_switch(priv->ds); 3248 3249 mutex_destroy(&priv->reg_mutex); 3250 } 3251 EXPORT_SYMBOL_GPL(mt7530_remove_common); 3252 3253 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3254 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3255 MODULE_LICENSE("GPL"); 3256