1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 28 { 29 return container_of(pcs, struct mt753x_pcs, pcs); 30 } 31 32 /* String, offset, and register size in bytes if different from 4 bytes */ 33 static const struct mt7530_mib_desc mt7530_mib[] = { 34 MIB_DESC(1, 0x00, "TxDrop"), 35 MIB_DESC(1, 0x04, "TxCrcErr"), 36 MIB_DESC(1, 0x08, "TxUnicast"), 37 MIB_DESC(1, 0x0c, "TxMulticast"), 38 MIB_DESC(1, 0x10, "TxBroadcast"), 39 MIB_DESC(1, 0x14, "TxCollision"), 40 MIB_DESC(1, 0x18, "TxSingleCollision"), 41 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 42 MIB_DESC(1, 0x20, "TxDeferred"), 43 MIB_DESC(1, 0x24, "TxLateCollision"), 44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 45 MIB_DESC(1, 0x2c, "TxPause"), 46 MIB_DESC(1, 0x30, "TxPktSz64"), 47 MIB_DESC(1, 0x34, "TxPktSz65To127"), 48 MIB_DESC(1, 0x38, "TxPktSz128To255"), 49 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 50 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 51 MIB_DESC(1, 0x44, "Tx1024ToMax"), 52 MIB_DESC(2, 0x48, "TxBytes"), 53 MIB_DESC(1, 0x60, "RxDrop"), 54 MIB_DESC(1, 0x64, "RxFiltering"), 55 MIB_DESC(1, 0x68, "RxUnicast"), 56 MIB_DESC(1, 0x6c, "RxMulticast"), 57 MIB_DESC(1, 0x70, "RxBroadcast"), 58 MIB_DESC(1, 0x74, "RxAlignErr"), 59 MIB_DESC(1, 0x78, "RxCrcErr"), 60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 61 MIB_DESC(1, 0x80, "RxFragErr"), 62 MIB_DESC(1, 0x84, "RxOverSzErr"), 63 MIB_DESC(1, 0x88, "RxJabberErr"), 64 MIB_DESC(1, 0x8c, "RxPause"), 65 MIB_DESC(1, 0x90, "RxPktSz64"), 66 MIB_DESC(1, 0x94, "RxPktSz65To127"), 67 MIB_DESC(1, 0x98, "RxPktSz128To255"), 68 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 71 MIB_DESC(2, 0xa8, "RxBytes"), 72 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 73 MIB_DESC(1, 0xb4, "RxIngressDrop"), 74 MIB_DESC(1, 0xb8, "RxArlDrop"), 75 }; 76 77 static void 78 mt7530_mutex_lock(struct mt7530_priv *priv) 79 { 80 if (priv->bus) 81 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 82 } 83 84 static void 85 mt7530_mutex_unlock(struct mt7530_priv *priv) 86 { 87 if (priv->bus) 88 mutex_unlock(&priv->bus->mdio_lock); 89 } 90 91 static void 92 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 93 { 94 struct mii_bus *bus = priv->bus; 95 int ret; 96 97 mt7530_mutex_lock(priv); 98 99 /* Write the desired MMD Devad */ 100 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 101 MII_MMD_CTRL, MDIO_MMD_VEND2); 102 if (ret < 0) 103 goto err; 104 105 /* Write the desired MMD register address */ 106 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 107 MII_MMD_DATA, reg); 108 if (ret < 0) 109 goto err; 110 111 /* Select the Function : DATA with no post increment */ 112 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 113 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); 114 if (ret < 0) 115 goto err; 116 117 /* Write the data into MMD's selected register */ 118 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 119 MII_MMD_DATA, val); 120 err: 121 if (ret < 0) 122 dev_err(&bus->dev, "failed to write mmd register\n"); 123 124 mt7530_mutex_unlock(priv); 125 } 126 127 static void 128 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 129 { 130 struct mii_bus *bus = priv->bus; 131 u32 val; 132 int ret; 133 134 mt7530_mutex_lock(priv); 135 136 /* Write the desired MMD Devad */ 137 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 138 MII_MMD_CTRL, MDIO_MMD_VEND2); 139 if (ret < 0) 140 goto err; 141 142 /* Write the desired MMD register address */ 143 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 144 MII_MMD_DATA, reg); 145 if (ret < 0) 146 goto err; 147 148 /* Select the Function : DATA with no post increment */ 149 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 150 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); 151 if (ret < 0) 152 goto err; 153 154 /* Read the content of the MMD's selected register */ 155 val = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 156 MII_MMD_DATA); 157 val &= ~mask; 158 val |= set; 159 /* Write the data into MMD's selected register */ 160 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 161 MII_MMD_DATA, val); 162 err: 163 if (ret < 0) 164 dev_err(&bus->dev, "failed to write mmd register\n"); 165 166 mt7530_mutex_unlock(priv); 167 } 168 169 static void 170 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 171 { 172 core_rmw(priv, reg, 0, val); 173 } 174 175 static void 176 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 177 { 178 core_rmw(priv, reg, val, 0); 179 } 180 181 static int 182 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 183 { 184 int ret; 185 186 ret = regmap_write(priv->regmap, reg, val); 187 188 if (ret < 0) 189 dev_err(priv->dev, 190 "failed to write mt7530 register\n"); 191 192 return ret; 193 } 194 195 static u32 196 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 197 { 198 int ret; 199 u32 val; 200 201 ret = regmap_read(priv->regmap, reg, &val); 202 if (ret) { 203 WARN_ON_ONCE(1); 204 dev_err(priv->dev, 205 "failed to read mt7530 register\n"); 206 return 0; 207 } 208 209 return val; 210 } 211 212 static void 213 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 214 { 215 mt7530_mutex_lock(priv); 216 217 mt7530_mii_write(priv, reg, val); 218 219 mt7530_mutex_unlock(priv); 220 } 221 222 static u32 223 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 224 { 225 return mt7530_mii_read(p->priv, p->reg); 226 } 227 228 static u32 229 _mt7530_read(struct mt7530_dummy_poll *p) 230 { 231 u32 val; 232 233 mt7530_mutex_lock(p->priv); 234 235 val = mt7530_mii_read(p->priv, p->reg); 236 237 mt7530_mutex_unlock(p->priv); 238 239 return val; 240 } 241 242 static u32 243 mt7530_read(struct mt7530_priv *priv, u32 reg) 244 { 245 struct mt7530_dummy_poll p; 246 247 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 248 return _mt7530_read(&p); 249 } 250 251 static void 252 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 253 u32 mask, u32 set) 254 { 255 mt7530_mutex_lock(priv); 256 257 regmap_update_bits(priv->regmap, reg, mask, set); 258 259 mt7530_mutex_unlock(priv); 260 } 261 262 static void 263 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 264 { 265 mt7530_rmw(priv, reg, val, val); 266 } 267 268 static void 269 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 270 { 271 mt7530_rmw(priv, reg, val, 0); 272 } 273 274 static int 275 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 276 { 277 u32 val; 278 int ret; 279 struct mt7530_dummy_poll p; 280 281 /* Set the command operating upon the MAC address entries */ 282 val = ATC_BUSY | ATC_MAT(0) | cmd; 283 mt7530_write(priv, MT7530_ATC, val); 284 285 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 286 ret = readx_poll_timeout(_mt7530_read, &p, val, 287 !(val & ATC_BUSY), 20, 20000); 288 if (ret < 0) { 289 dev_err(priv->dev, "reset timeout\n"); 290 return ret; 291 } 292 293 /* Additional sanity for read command if the specified 294 * entry is invalid 295 */ 296 val = mt7530_read(priv, MT7530_ATC); 297 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 298 return -EINVAL; 299 300 if (rsp) 301 *rsp = val; 302 303 return 0; 304 } 305 306 static void 307 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 308 { 309 u32 reg[3]; 310 int i; 311 312 /* Read from ARL table into an array */ 313 for (i = 0; i < 3; i++) { 314 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 315 316 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 317 __func__, __LINE__, i, reg[i]); 318 } 319 320 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 321 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 322 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 323 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 324 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 325 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 326 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 327 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 328 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 329 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 330 } 331 332 static void 333 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 334 u8 port_mask, const u8 *mac, 335 u8 aging, u8 type) 336 { 337 u32 reg[3] = { 0 }; 338 int i; 339 340 reg[1] |= vid & CVID_MASK; 341 reg[1] |= ATA2_IVL; 342 reg[1] |= ATA2_FID(FID_BRIDGED); 343 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 344 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 345 /* STATIC_ENT indicate that entry is static wouldn't 346 * be aged out and STATIC_EMP specified as erasing an 347 * entry 348 */ 349 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 350 reg[1] |= mac[5] << MAC_BYTE_5; 351 reg[1] |= mac[4] << MAC_BYTE_4; 352 reg[0] |= mac[3] << MAC_BYTE_3; 353 reg[0] |= mac[2] << MAC_BYTE_2; 354 reg[0] |= mac[1] << MAC_BYTE_1; 355 reg[0] |= mac[0] << MAC_BYTE_0; 356 357 /* Write array into the ARL table */ 358 for (i = 0; i < 3; i++) 359 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 360 } 361 362 /* Set up switch core clock for MT7530 */ 363 static void mt7530_pll_setup(struct mt7530_priv *priv) 364 { 365 /* Disable core clock */ 366 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 367 368 /* Disable PLL */ 369 core_write(priv, CORE_GSWPLL_GRP1, 0); 370 371 /* Set core clock into 500Mhz */ 372 core_write(priv, CORE_GSWPLL_GRP2, 373 RG_GSWPLL_POSDIV_500M(1) | 374 RG_GSWPLL_FBKDIV_500M(25)); 375 376 /* Enable PLL */ 377 core_write(priv, CORE_GSWPLL_GRP1, 378 RG_GSWPLL_EN_PRE | 379 RG_GSWPLL_POSDIV_200M(2) | 380 RG_GSWPLL_FBKDIV_200M(32)); 381 382 udelay(20); 383 384 /* Enable core clock */ 385 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 386 } 387 388 /* If port 6 is available as a CPU port, always prefer that as the default, 389 * otherwise don't care. 390 */ 391 static struct dsa_port * 392 mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) 393 { 394 struct dsa_port *cpu_dp = dsa_to_port(ds, 6); 395 396 if (dsa_port_is_cpu(cpu_dp)) 397 return cpu_dp; 398 399 return NULL; 400 } 401 402 /* Setup port 6 interface mode and TRGMII TX circuit */ 403 static void 404 mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) 405 { 406 struct mt7530_priv *priv = ds->priv; 407 u32 ncpo1, ssc_delta, xtal; 408 409 /* Disable the MT7530 TRGMII clocks */ 410 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 411 412 if (interface == PHY_INTERFACE_MODE_RGMII) { 413 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 414 P6_INTF_MODE(0)); 415 return; 416 } 417 418 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1)); 419 420 xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK; 421 422 if (xtal == MT7530_XTAL_25MHZ) 423 ssc_delta = 0x57; 424 else 425 ssc_delta = 0x87; 426 427 if (priv->id == ID_MT7621) { 428 /* PLL frequency: 125MHz: 1.0GBit */ 429 if (xtal == MT7530_XTAL_40MHZ) 430 ncpo1 = 0x0640; 431 if (xtal == MT7530_XTAL_25MHZ) 432 ncpo1 = 0x0a00; 433 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 434 if (xtal == MT7530_XTAL_40MHZ) 435 ncpo1 = 0x0c80; 436 if (xtal == MT7530_XTAL_25MHZ) 437 ncpo1 = 0x1400; 438 } 439 440 /* Setup the MT7530 TRGMII Tx Clock */ 441 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 442 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 443 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 444 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 445 core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | 446 RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); 447 core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL | 448 RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1)); 449 core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG | 450 RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 451 452 /* Enable the MT7530 TRGMII clocks */ 453 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 454 } 455 456 static void 457 mt7531_pll_setup(struct mt7530_priv *priv) 458 { 459 enum mt7531_xtal_fsel xtal; 460 u32 top_sig; 461 u32 hwstrap; 462 u32 val; 463 464 val = mt7530_read(priv, MT7531_CREV); 465 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 466 hwstrap = mt7530_read(priv, MT753X_TRAP); 467 if ((val & CHIP_REV_M) > 0) 468 xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ : 469 MT7531_XTAL_FSEL_25MHZ; 470 else 471 xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ : 472 MT7531_XTAL_FSEL_40MHZ; 473 474 /* Step 1 : Disable MT7531 COREPLL */ 475 val = mt7530_read(priv, MT7531_PLLGP_EN); 476 val &= ~EN_COREPLL; 477 mt7530_write(priv, MT7531_PLLGP_EN, val); 478 479 /* Step 2: switch to XTAL output */ 480 val = mt7530_read(priv, MT7531_PLLGP_EN); 481 val |= SW_CLKSW; 482 mt7530_write(priv, MT7531_PLLGP_EN, val); 483 484 val = mt7530_read(priv, MT7531_PLLGP_CR0); 485 val &= ~RG_COREPLL_EN; 486 mt7530_write(priv, MT7531_PLLGP_CR0, val); 487 488 /* Step 3: disable PLLGP and enable program PLLGP */ 489 val = mt7530_read(priv, MT7531_PLLGP_EN); 490 val |= SW_PLLGP; 491 mt7530_write(priv, MT7531_PLLGP_EN, val); 492 493 /* Step 4: program COREPLL output frequency to 500MHz */ 494 val = mt7530_read(priv, MT7531_PLLGP_CR0); 495 val &= ~RG_COREPLL_POSDIV_M; 496 val |= 2 << RG_COREPLL_POSDIV_S; 497 mt7530_write(priv, MT7531_PLLGP_CR0, val); 498 usleep_range(25, 35); 499 500 switch (xtal) { 501 case MT7531_XTAL_FSEL_25MHZ: 502 val = mt7530_read(priv, MT7531_PLLGP_CR0); 503 val &= ~RG_COREPLL_SDM_PCW_M; 504 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 505 mt7530_write(priv, MT7531_PLLGP_CR0, val); 506 break; 507 case MT7531_XTAL_FSEL_40MHZ: 508 val = mt7530_read(priv, MT7531_PLLGP_CR0); 509 val &= ~RG_COREPLL_SDM_PCW_M; 510 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 511 mt7530_write(priv, MT7531_PLLGP_CR0, val); 512 break; 513 } 514 515 /* Set feedback divide ratio update signal to high */ 516 val = mt7530_read(priv, MT7531_PLLGP_CR0); 517 val |= RG_COREPLL_SDM_PCW_CHG; 518 mt7530_write(priv, MT7531_PLLGP_CR0, val); 519 /* Wait for at least 16 XTAL clocks */ 520 usleep_range(10, 20); 521 522 /* Step 5: set feedback divide ratio update signal to low */ 523 val = mt7530_read(priv, MT7531_PLLGP_CR0); 524 val &= ~RG_COREPLL_SDM_PCW_CHG; 525 mt7530_write(priv, MT7531_PLLGP_CR0, val); 526 527 /* Enable 325M clock for SGMII */ 528 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 529 530 /* Enable 250SSC clock for RGMII */ 531 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 532 533 /* Step 6: Enable MT7531 PLL */ 534 val = mt7530_read(priv, MT7531_PLLGP_CR0); 535 val |= RG_COREPLL_EN; 536 mt7530_write(priv, MT7531_PLLGP_CR0, val); 537 538 val = mt7530_read(priv, MT7531_PLLGP_EN); 539 val |= EN_COREPLL; 540 mt7530_write(priv, MT7531_PLLGP_EN, val); 541 usleep_range(25, 35); 542 } 543 544 static void 545 mt7530_mib_reset(struct dsa_switch *ds) 546 { 547 struct mt7530_priv *priv = ds->priv; 548 549 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 550 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 551 } 552 553 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 554 { 555 return mdiobus_read_nested(priv->bus, port, regnum); 556 } 557 558 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 559 u16 val) 560 { 561 return mdiobus_write_nested(priv->bus, port, regnum, val); 562 } 563 564 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 565 int devad, int regnum) 566 { 567 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 568 } 569 570 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 571 int regnum, u16 val) 572 { 573 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 574 } 575 576 static int 577 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 578 int regnum) 579 { 580 struct mt7530_dummy_poll p; 581 u32 reg, val; 582 int ret; 583 584 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 585 586 mt7530_mutex_lock(priv); 587 588 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 589 !(val & MT7531_PHY_ACS_ST), 20, 100000); 590 if (ret < 0) { 591 dev_err(priv->dev, "poll timeout\n"); 592 goto out; 593 } 594 595 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 596 MT7531_MDIO_DEV_ADDR(devad) | regnum; 597 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 598 599 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 600 !(val & MT7531_PHY_ACS_ST), 20, 100000); 601 if (ret < 0) { 602 dev_err(priv->dev, "poll timeout\n"); 603 goto out; 604 } 605 606 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 607 MT7531_MDIO_DEV_ADDR(devad); 608 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 609 610 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 611 !(val & MT7531_PHY_ACS_ST), 20, 100000); 612 if (ret < 0) { 613 dev_err(priv->dev, "poll timeout\n"); 614 goto out; 615 } 616 617 ret = val & MT7531_MDIO_RW_DATA_MASK; 618 out: 619 mt7530_mutex_unlock(priv); 620 621 return ret; 622 } 623 624 static int 625 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 626 int regnum, u16 data) 627 { 628 struct mt7530_dummy_poll p; 629 u32 val, reg; 630 int ret; 631 632 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 633 634 mt7530_mutex_lock(priv); 635 636 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 637 !(val & MT7531_PHY_ACS_ST), 20, 100000); 638 if (ret < 0) { 639 dev_err(priv->dev, "poll timeout\n"); 640 goto out; 641 } 642 643 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 644 MT7531_MDIO_DEV_ADDR(devad) | regnum; 645 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 646 647 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 648 !(val & MT7531_PHY_ACS_ST), 20, 100000); 649 if (ret < 0) { 650 dev_err(priv->dev, "poll timeout\n"); 651 goto out; 652 } 653 654 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 655 MT7531_MDIO_DEV_ADDR(devad) | data; 656 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 657 658 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 659 !(val & MT7531_PHY_ACS_ST), 20, 100000); 660 if (ret < 0) { 661 dev_err(priv->dev, "poll timeout\n"); 662 goto out; 663 } 664 665 out: 666 mt7530_mutex_unlock(priv); 667 668 return ret; 669 } 670 671 static int 672 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 673 { 674 struct mt7530_dummy_poll p; 675 int ret; 676 u32 val; 677 678 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 679 680 mt7530_mutex_lock(priv); 681 682 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 683 !(val & MT7531_PHY_ACS_ST), 20, 100000); 684 if (ret < 0) { 685 dev_err(priv->dev, "poll timeout\n"); 686 goto out; 687 } 688 689 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 690 MT7531_MDIO_REG_ADDR(regnum); 691 692 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 693 694 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 695 !(val & MT7531_PHY_ACS_ST), 20, 100000); 696 if (ret < 0) { 697 dev_err(priv->dev, "poll timeout\n"); 698 goto out; 699 } 700 701 ret = val & MT7531_MDIO_RW_DATA_MASK; 702 out: 703 mt7530_mutex_unlock(priv); 704 705 return ret; 706 } 707 708 static int 709 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 710 u16 data) 711 { 712 struct mt7530_dummy_poll p; 713 int ret; 714 u32 reg; 715 716 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 717 718 mt7530_mutex_lock(priv); 719 720 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 721 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 722 if (ret < 0) { 723 dev_err(priv->dev, "poll timeout\n"); 724 goto out; 725 } 726 727 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 728 MT7531_MDIO_REG_ADDR(regnum) | data; 729 730 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 731 732 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 733 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 734 if (ret < 0) { 735 dev_err(priv->dev, "poll timeout\n"); 736 goto out; 737 } 738 739 out: 740 mt7530_mutex_unlock(priv); 741 742 return ret; 743 } 744 745 static int 746 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 747 { 748 struct mt7530_priv *priv = bus->priv; 749 750 return priv->info->phy_read_c22(priv, port, regnum); 751 } 752 753 static int 754 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 755 { 756 struct mt7530_priv *priv = bus->priv; 757 758 return priv->info->phy_read_c45(priv, port, devad, regnum); 759 } 760 761 static int 762 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 763 { 764 struct mt7530_priv *priv = bus->priv; 765 766 return priv->info->phy_write_c22(priv, port, regnum, val); 767 } 768 769 static int 770 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 771 u16 val) 772 { 773 struct mt7530_priv *priv = bus->priv; 774 775 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 776 } 777 778 static void 779 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 780 uint8_t *data) 781 { 782 int i; 783 784 if (stringset != ETH_SS_STATS) 785 return; 786 787 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 788 ethtool_puts(&data, mt7530_mib[i].name); 789 } 790 791 static void 792 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 793 uint64_t *data) 794 { 795 struct mt7530_priv *priv = ds->priv; 796 const struct mt7530_mib_desc *mib; 797 u32 reg, i; 798 u64 hi; 799 800 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 801 mib = &mt7530_mib[i]; 802 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 803 804 data[i] = mt7530_read(priv, reg); 805 if (mib->size == 2) { 806 hi = mt7530_read(priv, reg + 4); 807 data[i] |= hi << 32; 808 } 809 } 810 } 811 812 static int 813 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 814 { 815 if (sset != ETH_SS_STATS) 816 return 0; 817 818 return ARRAY_SIZE(mt7530_mib); 819 } 820 821 static int 822 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 823 { 824 struct mt7530_priv *priv = ds->priv; 825 unsigned int secs = msecs / 1000; 826 unsigned int tmp_age_count; 827 unsigned int error = -1; 828 unsigned int age_count; 829 unsigned int age_unit; 830 831 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 832 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 833 return -ERANGE; 834 835 /* iterate through all possible age_count to find the closest pair */ 836 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 837 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 838 839 if (tmp_age_unit <= AGE_UNIT_MAX) { 840 unsigned int tmp_error = secs - 841 (tmp_age_count + 1) * (tmp_age_unit + 1); 842 843 /* found a closer pair */ 844 if (error > tmp_error) { 845 error = tmp_error; 846 age_count = tmp_age_count; 847 age_unit = tmp_age_unit; 848 } 849 850 /* found the exact match, so break the loop */ 851 if (!error) 852 break; 853 } 854 } 855 856 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 857 858 return 0; 859 } 860 861 static const char *mt7530_p5_mode_str(unsigned int mode) 862 { 863 switch (mode) { 864 case MUX_PHY_P0: 865 return "MUX PHY P0"; 866 case MUX_PHY_P4: 867 return "MUX PHY P4"; 868 default: 869 return "GMAC5"; 870 } 871 } 872 873 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 874 { 875 struct mt7530_priv *priv = ds->priv; 876 u8 tx_delay = 0; 877 int val; 878 879 mutex_lock(&priv->reg_mutex); 880 881 val = mt7530_read(priv, MT753X_MTRAP); 882 883 val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE; 884 885 switch (priv->p5_mode) { 886 /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ 887 case MUX_PHY_P0: 888 val |= MT7530_P5_PHY0_SEL; 889 fallthrough; 890 891 /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ 892 case MUX_PHY_P4: 893 /* Setup the MAC by default for the cpu port */ 894 mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); 895 break; 896 897 /* GMAC5: P5 -> SoC MAC or external PHY */ 898 default: 899 val |= MT7530_P5_MAC_SEL; 900 break; 901 } 902 903 /* Setup RGMII settings */ 904 if (phy_interface_mode_is_rgmii(interface)) { 905 val |= MT7530_P5_RGMII_MODE; 906 907 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 908 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 909 910 /* Don't set delay in DSA mode */ 911 if (!dsa_is_dsa_port(priv->ds, 5) && 912 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 913 interface == PHY_INTERFACE_MODE_RGMII_ID)) 914 tx_delay = 4; /* n * 0.5 ns */ 915 916 /* P5 RGMII TX Clock Control: delay x */ 917 mt7530_write(priv, MT7530_P5RGMIITXCR, 918 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 919 920 /* reduce P5 RGMII Tx driving, 8mA */ 921 mt7530_write(priv, MT7530_IO_DRV_CR, 922 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 923 } 924 925 mt7530_write(priv, MT753X_MTRAP, val); 926 927 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, 928 mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); 929 930 mutex_unlock(&priv->reg_mutex); 931 } 932 933 /* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL) 934 * of the Open Systems Interconnection basic reference model (OSI/RM) are 935 * described; the medium access control (MAC) and logical link control (LLC) 936 * sublayers. The MAC sublayer is the one facing the physical layer. 937 * 938 * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A 939 * Bridge component comprises a MAC Relay Entity for interconnecting the Ports 940 * of the Bridge, at least two Ports, and higher layer entities with at least a 941 * Spanning Tree Protocol Entity included. 942 * 943 * Each Bridge Port also functions as an end station and shall provide the MAC 944 * Service to an LLC Entity. Each instance of the MAC Service is provided to a 945 * distinct LLC Entity that supports protocol identification, multiplexing, and 946 * demultiplexing, for protocol data unit (PDU) transmission and reception by 947 * one or more higher layer entities. 948 * 949 * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC 950 * Entity associated with each Bridge Port is modeled as being directly 951 * connected to the attached Local Area Network (LAN). 952 * 953 * On the switch with CPU port architecture, CPU port functions as Management 954 * Port, and the Management Port functionality is provided by software which 955 * functions as an end station. Software is connected to an IEEE 802 LAN that is 956 * wholly contained within the system that incorporates the Bridge. Software 957 * provides access to the LLC Entity associated with each Bridge Port by the 958 * value of the source port field on the special tag on the frame received by 959 * software. 960 * 961 * We call frames that carry control information to determine the active 962 * topology and current extent of each Virtual Local Area Network (VLAN), i.e., 963 * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration 964 * Protocol Data Units (MVRPDUs), and frames from other link constrained 965 * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and 966 * Link Layer Discovery Protocol (LLDP), link-local frames. They are not 967 * forwarded by a Bridge. Permanently configured entries in the filtering 968 * database (FDB) ensure that such frames are discarded by the Forwarding 969 * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail: 970 * 971 * Each of the reserved MAC addresses specified in Table 8-1 972 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be 973 * permanently configured in the FDB in C-VLAN components and ERs. 974 * 975 * Each of the reserved MAC addresses specified in Table 8-2 976 * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently 977 * configured in the FDB in S-VLAN components. 978 * 979 * Each of the reserved MAC addresses specified in Table 8-3 980 * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in 981 * TPMR components. 982 * 983 * The FDB entries for reserved MAC addresses shall specify filtering for all 984 * Bridge Ports and all VIDs. Management shall not provide the capability to 985 * modify or remove entries for reserved MAC addresses. 986 * 987 * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of 988 * propagation of PDUs within a Bridged Network, as follows: 989 * 990 * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no 991 * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN) 992 * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward. 993 * PDUs transmitted using this destination address, or any other addresses 994 * that appear in Table 8-1, Table 8-2, and Table 8-3 995 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can 996 * therefore travel no further than those stations that can be reached via a 997 * single individual LAN from the originating station. 998 * 999 * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an 1000 * address that no conformant S-VLAN component, C-VLAN component, or MAC 1001 * Bridge can forward; however, this address is relayed by a TPMR component. 1002 * PDUs using this destination address, or any of the other addresses that 1003 * appear in both Table 8-1 and Table 8-2 but not in Table 8-3 1004 * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by 1005 * any TPMRs but will propagate no further than the nearest S-VLAN component, 1006 * C-VLAN component, or MAC Bridge. 1007 * 1008 * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address 1009 * that no conformant C-VLAN component, MAC Bridge can forward; however, it is 1010 * relayed by TPMR components and S-VLAN components. PDUs using this 1011 * destination address, or any of the other addresses that appear in Table 8-1 1012 * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]), 1013 * will be relayed by TPMR components and S-VLAN components but will propagate 1014 * no further than the nearest C-VLAN component or MAC Bridge. 1015 * 1016 * Because the LLC Entity associated with each Bridge Port is provided via CPU 1017 * port, we must not filter these frames but forward them to CPU port. 1018 * 1019 * In a Bridge, the transmission Port is majorly decided by ingress and egress 1020 * rules, FDB, and spanning tree Port State functions of the Forwarding Process. 1021 * For link-local frames, only CPU port should be designated as destination port 1022 * in the FDB, and the other functions of the Forwarding Process must not 1023 * interfere with the decision of the transmission Port. We call this process 1024 * trapping frames to CPU port. 1025 * 1026 * Therefore, on the switch with CPU port architecture, link-local frames must 1027 * be trapped to CPU port, and certain link-local frames received by a Port of a 1028 * Bridge comprising a TPMR component or an S-VLAN component must be excluded 1029 * from it. 1030 * 1031 * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port 1032 * MAC Relay (TPMR) component as a TPMR component supports only a subset of the 1033 * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port 1034 * doesn't count) of this architecture will either function as a standard MAC 1035 * Bridge or a standard VLAN Bridge. 1036 * 1037 * Therefore, a Bridge of this architecture can only comprise S-VLAN components, 1038 * C-VLAN components, or MAC Bridge components. Since there's no TPMR component, 1039 * we don't need to relay PDUs using the destination addresses specified on the 1040 * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge 1041 * section where they must be relayed by TPMR components. 1042 * 1043 * One option to trap link-local frames to CPU port is to add static FDB entries 1044 * with CPU port designated as destination port. However, because that 1045 * Independent VLAN Learning (IVL) is being used on every VID, each entry only 1046 * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC 1047 * Bridge component or a C-VLAN component, there would have to be 16 times 4096 1048 * entries. This switch intellectual property can only hold a maximum of 2048 1049 * entries. Using this option, there also isn't a mechanism to prevent 1050 * link-local frames from being discarded when the spanning tree Port State of 1051 * the reception Port is discarding. 1052 * 1053 * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4 1054 * registers. Whilst this applies to every VID, it doesn't contain all of the 1055 * reserved MAC addresses without affecting the remaining Standard Group MAC 1056 * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the 1057 * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination 1058 * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF 1059 * destination addresses which may be relayed by MAC Bridges or VLAN Bridges. 1060 * The latter option provides better but not complete conformance. 1061 * 1062 * This switch intellectual property also does not provide a mechanism to trap 1063 * link-local frames with specific destination addresses to CPU port by Bridge, 1064 * to conform to the filtering rules for the distinct Bridge components. 1065 * 1066 * Therefore, regardless of the type of the Bridge component, link-local frames 1067 * with these destination addresses will be trapped to CPU port: 1068 * 1069 * 01-80-C2-00-00-[00,01,02,03,0E] 1070 * 1071 * In a Bridge comprising a MAC Bridge component or a C-VLAN component: 1072 * 1073 * Link-local frames with these destination addresses won't be trapped to CPU 1074 * port which won't conform to IEEE Std 802.1Q-2022: 1075 * 1076 * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] 1077 * 1078 * In a Bridge comprising an S-VLAN component: 1079 * 1080 * Link-local frames with these destination addresses will be trapped to CPU 1081 * port which won't conform to IEEE Std 802.1Q-2022: 1082 * 1083 * 01-80-C2-00-00-00 1084 * 1085 * Link-local frames with these destination addresses won't be trapped to CPU 1086 * port which won't conform to IEEE Std 802.1Q-2022: 1087 * 1088 * 01-80-C2-00-00-[04,05,06,07,08,09,0A] 1089 * 1090 * To trap link-local frames to CPU port as conformant as this switch 1091 * intellectual property can allow, link-local frames are made to be regarded as 1092 * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual 1093 * property only lets the frames regarded as BPDUs bypass the spanning tree Port 1094 * State function of the Forwarding Process. 1095 * 1096 * The only remaining interference is the ingress rules. When the reception Port 1097 * has no PVID assigned on software, VLAN-untagged frames won't be allowed in. 1098 * There doesn't seem to be a mechanism on the switch intellectual property to 1099 * have link-local frames bypass this function of the Forwarding Process. 1100 */ 1101 static void 1102 mt753x_trap_frames(struct mt7530_priv *priv) 1103 { 1104 /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them 1105 * VLAN-untagged. 1106 */ 1107 mt7530_rmw(priv, MT753X_BPC, 1108 PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK | 1109 BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK, 1110 PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1111 PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) | 1112 BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1113 TO_CPU_FW_CPU_ONLY); 1114 1115 /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress 1116 * them VLAN-untagged. 1117 */ 1118 mt7530_rmw(priv, MT753X_RGAC1, 1119 R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK | 1120 R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK, 1121 R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1122 R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR | 1123 R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1124 TO_CPU_FW_CPU_ONLY); 1125 1126 /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress 1127 * them VLAN-untagged. 1128 */ 1129 mt7530_rmw(priv, MT753X_RGAC2, 1130 R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK | 1131 R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK, 1132 R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1133 R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR | 1134 R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1135 TO_CPU_FW_CPU_ONLY); 1136 } 1137 1138 static void 1139 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1140 { 1141 struct mt7530_priv *priv = ds->priv; 1142 1143 /* Enable Mediatek header mode on the cpu port */ 1144 mt7530_write(priv, MT7530_PVC_P(port), 1145 PORT_SPEC_TAG); 1146 1147 /* Enable flooding on the CPU port */ 1148 mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | 1149 UNU_FFP(BIT(port))); 1150 1151 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on 1152 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that 1153 * is affine to the inbound user port. 1154 */ 1155 if (priv->id == ID_MT7531 || priv->id == ID_MT7988) 1156 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); 1157 1158 /* CPU port gets connected to all user ports of 1159 * the switch. 1160 */ 1161 mt7530_write(priv, MT7530_PCR_P(port), 1162 PCR_MATRIX(dsa_user_ports(priv->ds))); 1163 1164 /* Set to fallback mode for independent VLAN learning */ 1165 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1166 MT7530_PORT_FALLBACK_MODE); 1167 } 1168 1169 static int 1170 mt7530_port_enable(struct dsa_switch *ds, int port, 1171 struct phy_device *phy) 1172 { 1173 struct dsa_port *dp = dsa_to_port(ds, port); 1174 struct mt7530_priv *priv = ds->priv; 1175 1176 mutex_lock(&priv->reg_mutex); 1177 1178 /* Allow the user port gets connected to the cpu port and also 1179 * restore the port matrix if the port is the member of a certain 1180 * bridge. 1181 */ 1182 if (dsa_port_is_user(dp)) { 1183 struct dsa_port *cpu_dp = dp->cpu_dp; 1184 1185 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1186 } 1187 priv->ports[port].enable = true; 1188 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1189 priv->ports[port].pm); 1190 1191 mutex_unlock(&priv->reg_mutex); 1192 1193 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 1194 return 0; 1195 1196 if (port == 5) 1197 mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); 1198 else if (port == 6) 1199 mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS); 1200 1201 return 0; 1202 } 1203 1204 static void 1205 mt7530_port_disable(struct dsa_switch *ds, int port) 1206 { 1207 struct mt7530_priv *priv = ds->priv; 1208 1209 mutex_lock(&priv->reg_mutex); 1210 1211 /* Clear up all port matrix which could be restored in the next 1212 * enablement for the port. 1213 */ 1214 priv->ports[port].enable = false; 1215 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1216 PCR_MATRIX_CLR); 1217 1218 mutex_unlock(&priv->reg_mutex); 1219 1220 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 1221 return; 1222 1223 if (port == 5) 1224 mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS); 1225 else if (port == 6) 1226 mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS); 1227 } 1228 1229 static int 1230 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1231 { 1232 struct mt7530_priv *priv = ds->priv; 1233 int length; 1234 u32 val; 1235 1236 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1237 * largest MTU of the user ports. Because the switch only has a global 1238 * RX length register, only allowing CPU port here is enough. 1239 */ 1240 if (!dsa_is_cpu_port(ds, port)) 1241 return 0; 1242 1243 mt7530_mutex_lock(priv); 1244 1245 val = mt7530_mii_read(priv, MT7530_GMACCR); 1246 val &= ~MAX_RX_PKT_LEN_MASK; 1247 1248 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1249 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1250 if (length <= 1522) { 1251 val |= MAX_RX_PKT_LEN_1522; 1252 } else if (length <= 1536) { 1253 val |= MAX_RX_PKT_LEN_1536; 1254 } else if (length <= 1552) { 1255 val |= MAX_RX_PKT_LEN_1552; 1256 } else { 1257 val &= ~MAX_RX_JUMBO_MASK; 1258 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1259 val |= MAX_RX_PKT_LEN_JUMBO; 1260 } 1261 1262 mt7530_mii_write(priv, MT7530_GMACCR, val); 1263 1264 mt7530_mutex_unlock(priv); 1265 1266 return 0; 1267 } 1268 1269 static int 1270 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1271 { 1272 return MT7530_MAX_MTU; 1273 } 1274 1275 static void 1276 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1277 { 1278 struct mt7530_priv *priv = ds->priv; 1279 u32 stp_state; 1280 1281 switch (state) { 1282 case BR_STATE_DISABLED: 1283 stp_state = MT7530_STP_DISABLED; 1284 break; 1285 case BR_STATE_BLOCKING: 1286 stp_state = MT7530_STP_BLOCKING; 1287 break; 1288 case BR_STATE_LISTENING: 1289 stp_state = MT7530_STP_LISTENING; 1290 break; 1291 case BR_STATE_LEARNING: 1292 stp_state = MT7530_STP_LEARNING; 1293 break; 1294 case BR_STATE_FORWARDING: 1295 default: 1296 stp_state = MT7530_STP_FORWARDING; 1297 break; 1298 } 1299 1300 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1301 FID_PST(FID_BRIDGED, stp_state)); 1302 } 1303 1304 static int 1305 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1306 struct switchdev_brport_flags flags, 1307 struct netlink_ext_ack *extack) 1308 { 1309 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1310 BR_BCAST_FLOOD)) 1311 return -EINVAL; 1312 1313 return 0; 1314 } 1315 1316 static int 1317 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1318 struct switchdev_brport_flags flags, 1319 struct netlink_ext_ack *extack) 1320 { 1321 struct mt7530_priv *priv = ds->priv; 1322 1323 if (flags.mask & BR_LEARNING) 1324 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1325 flags.val & BR_LEARNING ? 0 : SA_DIS); 1326 1327 if (flags.mask & BR_FLOOD) 1328 mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)), 1329 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1330 1331 if (flags.mask & BR_MCAST_FLOOD) 1332 mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)), 1333 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1334 1335 if (flags.mask & BR_BCAST_FLOOD) 1336 mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)), 1337 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1338 1339 return 0; 1340 } 1341 1342 static int 1343 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1344 struct dsa_bridge bridge, bool *tx_fwd_offload, 1345 struct netlink_ext_ack *extack) 1346 { 1347 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1348 struct dsa_port *cpu_dp = dp->cpu_dp; 1349 u32 port_bitmap = BIT(cpu_dp->index); 1350 struct mt7530_priv *priv = ds->priv; 1351 1352 mutex_lock(&priv->reg_mutex); 1353 1354 dsa_switch_for_each_user_port(other_dp, ds) { 1355 int other_port = other_dp->index; 1356 1357 if (dp == other_dp) 1358 continue; 1359 1360 /* Add this port to the port matrix of the other ports in the 1361 * same bridge. If the port is disabled, port matrix is kept 1362 * and not being setup until the port becomes enabled. 1363 */ 1364 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1365 continue; 1366 1367 if (priv->ports[other_port].enable) 1368 mt7530_set(priv, MT7530_PCR_P(other_port), 1369 PCR_MATRIX(BIT(port))); 1370 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); 1371 1372 port_bitmap |= BIT(other_port); 1373 } 1374 1375 /* Add the all other ports to this port matrix. */ 1376 if (priv->ports[port].enable) 1377 mt7530_rmw(priv, MT7530_PCR_P(port), 1378 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1379 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1380 1381 /* Set to fallback mode for independent VLAN learning */ 1382 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1383 MT7530_PORT_FALLBACK_MODE); 1384 1385 mutex_unlock(&priv->reg_mutex); 1386 1387 return 0; 1388 } 1389 1390 static void 1391 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1392 { 1393 struct mt7530_priv *priv = ds->priv; 1394 bool all_user_ports_removed = true; 1395 int i; 1396 1397 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1398 * bridge. Don't set standalone ports to fallback mode. 1399 */ 1400 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1401 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1402 MT7530_PORT_FALLBACK_MODE); 1403 1404 mt7530_rmw(priv, MT7530_PVC_P(port), 1405 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1406 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1407 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1408 MT7530_VLAN_ACC_ALL); 1409 1410 /* Set PVID to 0 */ 1411 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1412 G0_PORT_VID_DEF); 1413 1414 for (i = 0; i < priv->ds->num_ports; i++) { 1415 if (dsa_is_user_port(ds, i) && 1416 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1417 all_user_ports_removed = false; 1418 break; 1419 } 1420 } 1421 1422 /* CPU port also does the same thing until all user ports belonging to 1423 * the CPU port get out of VLAN filtering mode. 1424 */ 1425 if (all_user_ports_removed) { 1426 struct dsa_port *dp = dsa_to_port(ds, port); 1427 struct dsa_port *cpu_dp = dp->cpu_dp; 1428 1429 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1430 PCR_MATRIX(dsa_user_ports(priv->ds))); 1431 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1432 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1433 } 1434 } 1435 1436 static void 1437 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1438 { 1439 struct mt7530_priv *priv = ds->priv; 1440 1441 /* Trapped into security mode allows packet forwarding through VLAN 1442 * table lookup. 1443 */ 1444 if (dsa_is_user_port(ds, port)) { 1445 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1446 MT7530_PORT_SECURITY_MODE); 1447 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1448 G0_PORT_VID(priv->ports[port].pvid)); 1449 1450 /* Only accept tagged frames if PVID is not set */ 1451 if (!priv->ports[port].pvid) 1452 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1453 MT7530_VLAN_ACC_TAGGED); 1454 1455 /* Set the port as a user port which is to be able to recognize 1456 * VID from incoming packets before fetching entry within the 1457 * VLAN table. 1458 */ 1459 mt7530_rmw(priv, MT7530_PVC_P(port), 1460 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1461 VLAN_ATTR(MT7530_VLAN_USER) | 1462 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1463 } else { 1464 /* Also set CPU ports to the "user" VLAN port attribute, to 1465 * allow VLAN classification, but keep the EG_TAG attribute as 1466 * "consistent" (i.o.w. don't change its value) for packets 1467 * received by the switch from the CPU, so that tagged packets 1468 * are forwarded to user ports as tagged, and untagged as 1469 * untagged. 1470 */ 1471 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1472 VLAN_ATTR(MT7530_VLAN_USER)); 1473 } 1474 } 1475 1476 static void 1477 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1478 struct dsa_bridge bridge) 1479 { 1480 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1481 struct dsa_port *cpu_dp = dp->cpu_dp; 1482 struct mt7530_priv *priv = ds->priv; 1483 1484 mutex_lock(&priv->reg_mutex); 1485 1486 dsa_switch_for_each_user_port(other_dp, ds) { 1487 int other_port = other_dp->index; 1488 1489 if (dp == other_dp) 1490 continue; 1491 1492 /* Remove this port from the port matrix of the other ports 1493 * in the same bridge. If the port is disabled, port matrix 1494 * is kept and not being setup until the port becomes enabled. 1495 */ 1496 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1497 continue; 1498 1499 if (priv->ports[other_port].enable) 1500 mt7530_clear(priv, MT7530_PCR_P(other_port), 1501 PCR_MATRIX(BIT(port))); 1502 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); 1503 } 1504 1505 /* Set the cpu port to be the only one in the port matrix of 1506 * this port. 1507 */ 1508 if (priv->ports[port].enable) 1509 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1510 PCR_MATRIX(BIT(cpu_dp->index))); 1511 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); 1512 1513 /* When a port is removed from the bridge, the port would be set up 1514 * back to the default as is at initial boot which is a VLAN-unaware 1515 * port. 1516 */ 1517 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1518 MT7530_PORT_MATRIX_MODE); 1519 1520 mutex_unlock(&priv->reg_mutex); 1521 } 1522 1523 static int 1524 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1525 const unsigned char *addr, u16 vid, 1526 struct dsa_db db) 1527 { 1528 struct mt7530_priv *priv = ds->priv; 1529 int ret; 1530 u8 port_mask = BIT(port); 1531 1532 mutex_lock(&priv->reg_mutex); 1533 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1534 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1535 mutex_unlock(&priv->reg_mutex); 1536 1537 return ret; 1538 } 1539 1540 static int 1541 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1542 const unsigned char *addr, u16 vid, 1543 struct dsa_db db) 1544 { 1545 struct mt7530_priv *priv = ds->priv; 1546 int ret; 1547 u8 port_mask = BIT(port); 1548 1549 mutex_lock(&priv->reg_mutex); 1550 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1551 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1552 mutex_unlock(&priv->reg_mutex); 1553 1554 return ret; 1555 } 1556 1557 static int 1558 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1559 dsa_fdb_dump_cb_t *cb, void *data) 1560 { 1561 struct mt7530_priv *priv = ds->priv; 1562 struct mt7530_fdb _fdb = { 0 }; 1563 int cnt = MT7530_NUM_FDB_RECORDS; 1564 int ret = 0; 1565 u32 rsp = 0; 1566 1567 mutex_lock(&priv->reg_mutex); 1568 1569 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1570 if (ret < 0) 1571 goto err; 1572 1573 do { 1574 if (rsp & ATC_SRCH_HIT) { 1575 mt7530_fdb_read(priv, &_fdb); 1576 if (_fdb.port_mask & BIT(port)) { 1577 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1578 data); 1579 if (ret < 0) 1580 break; 1581 } 1582 } 1583 } while (--cnt && 1584 !(rsp & ATC_SRCH_END) && 1585 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1586 err: 1587 mutex_unlock(&priv->reg_mutex); 1588 1589 return 0; 1590 } 1591 1592 static int 1593 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1594 const struct switchdev_obj_port_mdb *mdb, 1595 struct dsa_db db) 1596 { 1597 struct mt7530_priv *priv = ds->priv; 1598 const u8 *addr = mdb->addr; 1599 u16 vid = mdb->vid; 1600 u8 port_mask = 0; 1601 int ret; 1602 1603 mutex_lock(&priv->reg_mutex); 1604 1605 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1606 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1607 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1608 & PORT_MAP_MASK; 1609 1610 port_mask |= BIT(port); 1611 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1612 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1613 1614 mutex_unlock(&priv->reg_mutex); 1615 1616 return ret; 1617 } 1618 1619 static int 1620 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1621 const struct switchdev_obj_port_mdb *mdb, 1622 struct dsa_db db) 1623 { 1624 struct mt7530_priv *priv = ds->priv; 1625 const u8 *addr = mdb->addr; 1626 u16 vid = mdb->vid; 1627 u8 port_mask = 0; 1628 int ret; 1629 1630 mutex_lock(&priv->reg_mutex); 1631 1632 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1633 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1634 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1635 & PORT_MAP_MASK; 1636 1637 port_mask &= ~BIT(port); 1638 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1639 port_mask ? STATIC_ENT : STATIC_EMP); 1640 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1641 1642 mutex_unlock(&priv->reg_mutex); 1643 1644 return ret; 1645 } 1646 1647 static int 1648 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1649 { 1650 struct mt7530_dummy_poll p; 1651 u32 val; 1652 int ret; 1653 1654 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1655 mt7530_write(priv, MT7530_VTCR, val); 1656 1657 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1658 ret = readx_poll_timeout(_mt7530_read, &p, val, 1659 !(val & VTCR_BUSY), 20, 20000); 1660 if (ret < 0) { 1661 dev_err(priv->dev, "poll timeout\n"); 1662 return ret; 1663 } 1664 1665 val = mt7530_read(priv, MT7530_VTCR); 1666 if (val & VTCR_INVALID) { 1667 dev_err(priv->dev, "read VTCR invalid\n"); 1668 return -EINVAL; 1669 } 1670 1671 return 0; 1672 } 1673 1674 static int 1675 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1676 struct netlink_ext_ack *extack) 1677 { 1678 struct dsa_port *dp = dsa_to_port(ds, port); 1679 struct dsa_port *cpu_dp = dp->cpu_dp; 1680 1681 if (vlan_filtering) { 1682 /* The port is being kept as VLAN-unaware port when bridge is 1683 * set up with vlan_filtering not being set, Otherwise, the 1684 * port and the corresponding CPU port is required the setup 1685 * for becoming a VLAN-aware port. 1686 */ 1687 mt7530_port_set_vlan_aware(ds, port); 1688 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1689 } else { 1690 mt7530_port_set_vlan_unaware(ds, port); 1691 } 1692 1693 return 0; 1694 } 1695 1696 static void 1697 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1698 struct mt7530_hw_vlan_entry *entry) 1699 { 1700 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1701 u8 new_members; 1702 u32 val; 1703 1704 new_members = entry->old_members | BIT(entry->port); 1705 1706 /* Validate the entry with independent learning, create egress tag per 1707 * VLAN and joining the port as one of the port members. 1708 */ 1709 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1710 VLAN_VALID; 1711 mt7530_write(priv, MT7530_VAWD1, val); 1712 1713 /* Decide whether adding tag or not for those outgoing packets from the 1714 * port inside the VLAN. 1715 * CPU port is always taken as a tagged port for serving more than one 1716 * VLANs across and also being applied with egress type stack mode for 1717 * that VLAN tags would be appended after hardware special tag used as 1718 * DSA tag. 1719 */ 1720 if (dsa_port_is_cpu(dp)) 1721 val = MT7530_VLAN_EGRESS_STACK; 1722 else if (entry->untagged) 1723 val = MT7530_VLAN_EGRESS_UNTAG; 1724 else 1725 val = MT7530_VLAN_EGRESS_TAG; 1726 mt7530_rmw(priv, MT7530_VAWD2, 1727 ETAG_CTRL_P_MASK(entry->port), 1728 ETAG_CTRL_P(entry->port, val)); 1729 } 1730 1731 static void 1732 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1733 struct mt7530_hw_vlan_entry *entry) 1734 { 1735 u8 new_members; 1736 u32 val; 1737 1738 new_members = entry->old_members & ~BIT(entry->port); 1739 1740 val = mt7530_read(priv, MT7530_VAWD1); 1741 if (!(val & VLAN_VALID)) { 1742 dev_err(priv->dev, 1743 "Cannot be deleted due to invalid entry\n"); 1744 return; 1745 } 1746 1747 if (new_members) { 1748 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1749 VLAN_VALID; 1750 mt7530_write(priv, MT7530_VAWD1, val); 1751 } else { 1752 mt7530_write(priv, MT7530_VAWD1, 0); 1753 mt7530_write(priv, MT7530_VAWD2, 0); 1754 } 1755 } 1756 1757 static void 1758 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1759 struct mt7530_hw_vlan_entry *entry, 1760 mt7530_vlan_op vlan_op) 1761 { 1762 u32 val; 1763 1764 /* Fetch entry */ 1765 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1766 1767 val = mt7530_read(priv, MT7530_VAWD1); 1768 1769 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1770 1771 /* Manipulate entry */ 1772 vlan_op(priv, entry); 1773 1774 /* Flush result to hardware */ 1775 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1776 } 1777 1778 static int 1779 mt7530_setup_vlan0(struct mt7530_priv *priv) 1780 { 1781 u32 val; 1782 1783 /* Validate the entry with independent learning, keep the original 1784 * ingress tag attribute. 1785 */ 1786 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1787 VLAN_VALID; 1788 mt7530_write(priv, MT7530_VAWD1, val); 1789 1790 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1791 } 1792 1793 static int 1794 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1795 const struct switchdev_obj_port_vlan *vlan, 1796 struct netlink_ext_ack *extack) 1797 { 1798 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1799 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1800 struct mt7530_hw_vlan_entry new_entry; 1801 struct mt7530_priv *priv = ds->priv; 1802 1803 mutex_lock(&priv->reg_mutex); 1804 1805 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1806 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1807 1808 if (pvid) { 1809 priv->ports[port].pvid = vlan->vid; 1810 1811 /* Accept all frames if PVID is set */ 1812 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1813 MT7530_VLAN_ACC_ALL); 1814 1815 /* Only configure PVID if VLAN filtering is enabled */ 1816 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1817 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1818 G0_PORT_VID_MASK, 1819 G0_PORT_VID(vlan->vid)); 1820 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1821 /* This VLAN is overwritten without PVID, so unset it */ 1822 priv->ports[port].pvid = G0_PORT_VID_DEF; 1823 1824 /* Only accept tagged frames if the port is VLAN-aware */ 1825 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1826 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1827 MT7530_VLAN_ACC_TAGGED); 1828 1829 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1830 G0_PORT_VID_DEF); 1831 } 1832 1833 mutex_unlock(&priv->reg_mutex); 1834 1835 return 0; 1836 } 1837 1838 static int 1839 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1840 const struct switchdev_obj_port_vlan *vlan) 1841 { 1842 struct mt7530_hw_vlan_entry target_entry; 1843 struct mt7530_priv *priv = ds->priv; 1844 1845 mutex_lock(&priv->reg_mutex); 1846 1847 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1848 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1849 mt7530_hw_vlan_del); 1850 1851 /* PVID is being restored to the default whenever the PVID port 1852 * is being removed from the VLAN. 1853 */ 1854 if (priv->ports[port].pvid == vlan->vid) { 1855 priv->ports[port].pvid = G0_PORT_VID_DEF; 1856 1857 /* Only accept tagged frames if the port is VLAN-aware */ 1858 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1859 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1860 MT7530_VLAN_ACC_TAGGED); 1861 1862 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1863 G0_PORT_VID_DEF); 1864 } 1865 1866 1867 mutex_unlock(&priv->reg_mutex); 1868 1869 return 0; 1870 } 1871 1872 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1873 struct dsa_mall_mirror_tc_entry *mirror, 1874 bool ingress, struct netlink_ext_ack *extack) 1875 { 1876 struct mt7530_priv *priv = ds->priv; 1877 int monitor_port; 1878 u32 val; 1879 1880 /* Check for existent entry */ 1881 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1882 return -EEXIST; 1883 1884 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1885 1886 /* MT7530 only supports one monitor port */ 1887 monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val); 1888 if (val & MT753X_MIRROR_EN(priv->id) && 1889 monitor_port != mirror->to_local_port) 1890 return -EEXIST; 1891 1892 val |= MT753X_MIRROR_EN(priv->id); 1893 val &= ~MT753X_MIRROR_PORT_MASK(priv->id); 1894 val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port); 1895 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1896 1897 val = mt7530_read(priv, MT7530_PCR_P(port)); 1898 if (ingress) { 1899 val |= PORT_RX_MIR; 1900 priv->mirror_rx |= BIT(port); 1901 } else { 1902 val |= PORT_TX_MIR; 1903 priv->mirror_tx |= BIT(port); 1904 } 1905 mt7530_write(priv, MT7530_PCR_P(port), val); 1906 1907 return 0; 1908 } 1909 1910 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1911 struct dsa_mall_mirror_tc_entry *mirror) 1912 { 1913 struct mt7530_priv *priv = ds->priv; 1914 u32 val; 1915 1916 val = mt7530_read(priv, MT7530_PCR_P(port)); 1917 if (mirror->ingress) { 1918 val &= ~PORT_RX_MIR; 1919 priv->mirror_rx &= ~BIT(port); 1920 } else { 1921 val &= ~PORT_TX_MIR; 1922 priv->mirror_tx &= ~BIT(port); 1923 } 1924 mt7530_write(priv, MT7530_PCR_P(port), val); 1925 1926 if (!priv->mirror_rx && !priv->mirror_tx) { 1927 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1928 val &= ~MT753X_MIRROR_EN(priv->id); 1929 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1930 } 1931 } 1932 1933 static enum dsa_tag_protocol 1934 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1935 enum dsa_tag_protocol mp) 1936 { 1937 return DSA_TAG_PROTO_MTK; 1938 } 1939 1940 #ifdef CONFIG_GPIOLIB 1941 static inline u32 1942 mt7530_gpio_to_bit(unsigned int offset) 1943 { 1944 /* Map GPIO offset to register bit 1945 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1946 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1947 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1948 * [14:12] port 3 LED 0..2 as GPIO 9..11 1949 * [18:16] port 4 LED 0..2 as GPIO 12..14 1950 */ 1951 return BIT(offset + offset / 3); 1952 } 1953 1954 static int 1955 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1956 { 1957 struct mt7530_priv *priv = gpiochip_get_data(gc); 1958 u32 bit = mt7530_gpio_to_bit(offset); 1959 1960 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1961 } 1962 1963 static void 1964 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1965 { 1966 struct mt7530_priv *priv = gpiochip_get_data(gc); 1967 u32 bit = mt7530_gpio_to_bit(offset); 1968 1969 if (value) 1970 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1971 else 1972 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1973 } 1974 1975 static int 1976 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1977 { 1978 struct mt7530_priv *priv = gpiochip_get_data(gc); 1979 u32 bit = mt7530_gpio_to_bit(offset); 1980 1981 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1982 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1983 } 1984 1985 static int 1986 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1987 { 1988 struct mt7530_priv *priv = gpiochip_get_data(gc); 1989 u32 bit = mt7530_gpio_to_bit(offset); 1990 1991 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1992 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1993 1994 return 0; 1995 } 1996 1997 static int 1998 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1999 { 2000 struct mt7530_priv *priv = gpiochip_get_data(gc); 2001 u32 bit = mt7530_gpio_to_bit(offset); 2002 2003 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 2004 2005 if (value) 2006 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 2007 else 2008 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 2009 2010 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 2011 2012 return 0; 2013 } 2014 2015 static int 2016 mt7530_setup_gpio(struct mt7530_priv *priv) 2017 { 2018 struct device *dev = priv->dev; 2019 struct gpio_chip *gc; 2020 2021 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 2022 if (!gc) 2023 return -ENOMEM; 2024 2025 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 2026 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 2027 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 2028 2029 gc->label = "mt7530"; 2030 gc->parent = dev; 2031 gc->owner = THIS_MODULE; 2032 gc->get_direction = mt7530_gpio_get_direction; 2033 gc->direction_input = mt7530_gpio_direction_input; 2034 gc->direction_output = mt7530_gpio_direction_output; 2035 gc->get = mt7530_gpio_get; 2036 gc->set = mt7530_gpio_set; 2037 gc->base = -1; 2038 gc->ngpio = 15; 2039 gc->can_sleep = true; 2040 2041 return devm_gpiochip_add_data(dev, gc, priv); 2042 } 2043 #endif /* CONFIG_GPIOLIB */ 2044 2045 static irqreturn_t 2046 mt7530_irq_thread_fn(int irq, void *dev_id) 2047 { 2048 struct mt7530_priv *priv = dev_id; 2049 bool handled = false; 2050 u32 val; 2051 int p; 2052 2053 mt7530_mutex_lock(priv); 2054 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 2055 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 2056 mt7530_mutex_unlock(priv); 2057 2058 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2059 if (BIT(p) & val) { 2060 unsigned int irq; 2061 2062 irq = irq_find_mapping(priv->irq_domain, p); 2063 handle_nested_irq(irq); 2064 handled = true; 2065 } 2066 } 2067 2068 return IRQ_RETVAL(handled); 2069 } 2070 2071 static void 2072 mt7530_irq_mask(struct irq_data *d) 2073 { 2074 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2075 2076 priv->irq_enable &= ~BIT(d->hwirq); 2077 } 2078 2079 static void 2080 mt7530_irq_unmask(struct irq_data *d) 2081 { 2082 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2083 2084 priv->irq_enable |= BIT(d->hwirq); 2085 } 2086 2087 static void 2088 mt7530_irq_bus_lock(struct irq_data *d) 2089 { 2090 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2091 2092 mt7530_mutex_lock(priv); 2093 } 2094 2095 static void 2096 mt7530_irq_bus_sync_unlock(struct irq_data *d) 2097 { 2098 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2099 2100 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2101 mt7530_mutex_unlock(priv); 2102 } 2103 2104 static struct irq_chip mt7530_irq_chip = { 2105 .name = KBUILD_MODNAME, 2106 .irq_mask = mt7530_irq_mask, 2107 .irq_unmask = mt7530_irq_unmask, 2108 .irq_bus_lock = mt7530_irq_bus_lock, 2109 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 2110 }; 2111 2112 static int 2113 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 2114 irq_hw_number_t hwirq) 2115 { 2116 irq_set_chip_data(irq, domain->host_data); 2117 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 2118 irq_set_nested_thread(irq, true); 2119 irq_set_noprobe(irq); 2120 2121 return 0; 2122 } 2123 2124 static const struct irq_domain_ops mt7530_irq_domain_ops = { 2125 .map = mt7530_irq_map, 2126 .xlate = irq_domain_xlate_onecell, 2127 }; 2128 2129 static void 2130 mt7988_irq_mask(struct irq_data *d) 2131 { 2132 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2133 2134 priv->irq_enable &= ~BIT(d->hwirq); 2135 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2136 } 2137 2138 static void 2139 mt7988_irq_unmask(struct irq_data *d) 2140 { 2141 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2142 2143 priv->irq_enable |= BIT(d->hwirq); 2144 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2145 } 2146 2147 static struct irq_chip mt7988_irq_chip = { 2148 .name = KBUILD_MODNAME, 2149 .irq_mask = mt7988_irq_mask, 2150 .irq_unmask = mt7988_irq_unmask, 2151 }; 2152 2153 static int 2154 mt7988_irq_map(struct irq_domain *domain, unsigned int irq, 2155 irq_hw_number_t hwirq) 2156 { 2157 irq_set_chip_data(irq, domain->host_data); 2158 irq_set_chip_and_handler(irq, &mt7988_irq_chip, handle_simple_irq); 2159 irq_set_nested_thread(irq, true); 2160 irq_set_noprobe(irq); 2161 2162 return 0; 2163 } 2164 2165 static const struct irq_domain_ops mt7988_irq_domain_ops = { 2166 .map = mt7988_irq_map, 2167 .xlate = irq_domain_xlate_onecell, 2168 }; 2169 2170 static void 2171 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 2172 { 2173 struct dsa_switch *ds = priv->ds; 2174 int p; 2175 2176 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2177 if (BIT(p) & ds->phys_mii_mask) { 2178 unsigned int irq; 2179 2180 irq = irq_create_mapping(priv->irq_domain, p); 2181 ds->user_mii_bus->irq[p] = irq; 2182 } 2183 } 2184 } 2185 2186 static int 2187 mt7530_setup_irq(struct mt7530_priv *priv) 2188 { 2189 struct device *dev = priv->dev; 2190 struct device_node *np = dev->of_node; 2191 int ret; 2192 2193 if (!of_property_read_bool(np, "interrupt-controller")) { 2194 dev_info(dev, "no interrupt support\n"); 2195 return 0; 2196 } 2197 2198 priv->irq = of_irq_get(np, 0); 2199 if (priv->irq <= 0) { 2200 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 2201 return priv->irq ? : -EINVAL; 2202 } 2203 2204 if (priv->id == ID_MT7988) 2205 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2206 &mt7988_irq_domain_ops, 2207 priv); 2208 else 2209 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2210 &mt7530_irq_domain_ops, 2211 priv); 2212 2213 if (!priv->irq_domain) { 2214 dev_err(dev, "failed to create IRQ domain\n"); 2215 return -ENOMEM; 2216 } 2217 2218 /* This register must be set for MT7530 to properly fire interrupts */ 2219 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) 2220 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2221 2222 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2223 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2224 if (ret) { 2225 irq_domain_remove(priv->irq_domain); 2226 dev_err(dev, "failed to request IRQ: %d\n", ret); 2227 return ret; 2228 } 2229 2230 return 0; 2231 } 2232 2233 static void 2234 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2235 { 2236 int p; 2237 2238 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2239 if (BIT(p) & priv->ds->phys_mii_mask) { 2240 unsigned int irq; 2241 2242 irq = irq_find_mapping(priv->irq_domain, p); 2243 irq_dispose_mapping(irq); 2244 } 2245 } 2246 } 2247 2248 static void 2249 mt7530_free_irq_common(struct mt7530_priv *priv) 2250 { 2251 free_irq(priv->irq, priv); 2252 irq_domain_remove(priv->irq_domain); 2253 } 2254 2255 static void 2256 mt7530_free_irq(struct mt7530_priv *priv) 2257 { 2258 struct device_node *mnp, *np = priv->dev->of_node; 2259 2260 mnp = of_get_child_by_name(np, "mdio"); 2261 if (!mnp) 2262 mt7530_free_mdio_irq(priv); 2263 of_node_put(mnp); 2264 2265 mt7530_free_irq_common(priv); 2266 } 2267 2268 static int 2269 mt7530_setup_mdio(struct mt7530_priv *priv) 2270 { 2271 struct device_node *mnp, *np = priv->dev->of_node; 2272 struct dsa_switch *ds = priv->ds; 2273 struct device *dev = priv->dev; 2274 struct mii_bus *bus; 2275 static int idx; 2276 int ret = 0; 2277 2278 mnp = of_get_child_by_name(np, "mdio"); 2279 2280 if (mnp && !of_device_is_available(mnp)) 2281 goto out; 2282 2283 bus = devm_mdiobus_alloc(dev); 2284 if (!bus) { 2285 ret = -ENOMEM; 2286 goto out; 2287 } 2288 2289 if (!mnp) 2290 ds->user_mii_bus = bus; 2291 2292 bus->priv = priv; 2293 bus->name = KBUILD_MODNAME "-mii"; 2294 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2295 bus->read = mt753x_phy_read_c22; 2296 bus->write = mt753x_phy_write_c22; 2297 bus->read_c45 = mt753x_phy_read_c45; 2298 bus->write_c45 = mt753x_phy_write_c45; 2299 bus->parent = dev; 2300 bus->phy_mask = ~ds->phys_mii_mask; 2301 2302 if (priv->irq && !mnp) 2303 mt7530_setup_mdio_irq(priv); 2304 2305 ret = devm_of_mdiobus_register(dev, bus, mnp); 2306 if (ret) { 2307 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2308 if (priv->irq && !mnp) 2309 mt7530_free_mdio_irq(priv); 2310 } 2311 2312 out: 2313 of_node_put(mnp); 2314 return ret; 2315 } 2316 2317 static int 2318 mt7530_setup(struct dsa_switch *ds) 2319 { 2320 struct mt7530_priv *priv = ds->priv; 2321 struct device_node *dn = NULL; 2322 struct device_node *phy_node; 2323 struct device_node *mac_np; 2324 struct mt7530_dummy_poll p; 2325 phy_interface_t interface; 2326 struct dsa_port *cpu_dp; 2327 u32 id, val; 2328 int ret, i; 2329 2330 /* The parent node of conduit netdev which holds the common system 2331 * controller also is the container for two GMACs nodes representing 2332 * as two netdev instances. 2333 */ 2334 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2335 dn = cpu_dp->conduit->dev.of_node->parent; 2336 /* It doesn't matter which CPU port is found first, 2337 * their conduits should share the same parent OF node 2338 */ 2339 break; 2340 } 2341 2342 if (!dn) { 2343 dev_err(ds->dev, "parent OF node of DSA conduit not found"); 2344 return -EINVAL; 2345 } 2346 2347 ds->assisted_learning_on_cpu_port = true; 2348 ds->mtu_enforcement_ingress = true; 2349 2350 if (priv->id == ID_MT7530) { 2351 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2352 ret = regulator_enable(priv->core_pwr); 2353 if (ret < 0) { 2354 dev_err(priv->dev, 2355 "Failed to enable core power: %d\n", ret); 2356 return ret; 2357 } 2358 2359 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2360 ret = regulator_enable(priv->io_pwr); 2361 if (ret < 0) { 2362 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2363 ret); 2364 return ret; 2365 } 2366 } 2367 2368 /* Reset whole chip through gpio pin or memory-mapped registers for 2369 * different type of hardware 2370 */ 2371 if (priv->mcm) { 2372 reset_control_assert(priv->rstc); 2373 usleep_range(5000, 5100); 2374 reset_control_deassert(priv->rstc); 2375 } else { 2376 gpiod_set_value_cansleep(priv->reset, 0); 2377 usleep_range(5000, 5100); 2378 gpiod_set_value_cansleep(priv->reset, 1); 2379 } 2380 2381 /* Waiting for MT7530 got to stable */ 2382 INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); 2383 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2384 20, 1000000); 2385 if (ret < 0) { 2386 dev_err(priv->dev, "reset timeout\n"); 2387 return ret; 2388 } 2389 2390 id = mt7530_read(priv, MT7530_CREV); 2391 id >>= CHIP_NAME_SHIFT; 2392 if (id != MT7530_ID) { 2393 dev_err(priv->dev, "chip %x can't be supported\n", id); 2394 return -ENODEV; 2395 } 2396 2397 if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) { 2398 dev_err(priv->dev, 2399 "MT7530 with a 20MHz XTAL is not supported!\n"); 2400 return -EINVAL; 2401 } 2402 2403 /* Reset the switch through internal reset */ 2404 mt7530_write(priv, MT7530_SYS_CTRL, 2405 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2406 SYS_CTRL_REG_RST); 2407 2408 /* Lower Tx driving for TRGMII path */ 2409 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2410 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 2411 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2412 2413 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2414 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 2415 RD_TAP_MASK, RD_TAP(16)); 2416 2417 /* Allow modifying the trap and directly access PHY registers via the 2418 * MDIO bus the switch is on. 2419 */ 2420 mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP | 2421 MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP); 2422 2423 if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ) 2424 mt7530_pll_setup(priv); 2425 2426 mt753x_trap_frames(priv); 2427 2428 /* Enable and reset MIB counters */ 2429 mt7530_mib_reset(ds); 2430 2431 for (i = 0; i < priv->ds->num_ports; i++) { 2432 /* Clear link settings and enable force mode to force link down 2433 * on all ports until they're enabled later. 2434 */ 2435 mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | 2436 MT7530_FORCE_MODE, MT7530_FORCE_MODE); 2437 2438 /* Disable forwarding by default on all ports */ 2439 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2440 PCR_MATRIX_CLR); 2441 2442 /* Disable learning by default on all ports */ 2443 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2444 2445 if (dsa_is_cpu_port(ds, i)) { 2446 mt753x_cpu_port_enable(ds, i); 2447 } else { 2448 mt7530_port_disable(ds, i); 2449 2450 /* Set default PVID to 0 on all user ports */ 2451 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2452 G0_PORT_VID_DEF); 2453 } 2454 /* Enable consistent egress tag */ 2455 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2456 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2457 } 2458 2459 /* Allow mirroring frames received on the local port (monitor port). */ 2460 mt7530_set(priv, MT753X_AGC, LOCAL_EN); 2461 2462 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2463 ret = mt7530_setup_vlan0(priv); 2464 if (ret) 2465 return ret; 2466 2467 /* Check for PHY muxing on port 5 */ 2468 if (dsa_is_unused_port(ds, 5)) { 2469 /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. 2470 * Set priv->p5_mode to the appropriate value if PHY muxing is 2471 * detected. 2472 */ 2473 for_each_child_of_node(dn, mac_np) { 2474 if (!of_device_is_compatible(mac_np, 2475 "mediatek,eth-mac")) 2476 continue; 2477 2478 ret = of_property_read_u32(mac_np, "reg", &id); 2479 if (ret < 0 || id != 1) 2480 continue; 2481 2482 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2483 if (!phy_node) 2484 continue; 2485 2486 if (phy_node->parent == priv->dev->of_node->parent) { 2487 ret = of_get_phy_mode(mac_np, &interface); 2488 if (ret && ret != -ENODEV) { 2489 of_node_put(mac_np); 2490 of_node_put(phy_node); 2491 return ret; 2492 } 2493 id = of_mdio_parse_addr(ds->dev, phy_node); 2494 if (id == 0) 2495 priv->p5_mode = MUX_PHY_P0; 2496 if (id == 4) 2497 priv->p5_mode = MUX_PHY_P4; 2498 } 2499 of_node_put(mac_np); 2500 of_node_put(phy_node); 2501 break; 2502 } 2503 2504 if (priv->p5_mode == MUX_PHY_P0 || 2505 priv->p5_mode == MUX_PHY_P4) { 2506 mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); 2507 mt7530_setup_port5(ds, interface); 2508 } 2509 } 2510 2511 #ifdef CONFIG_GPIOLIB 2512 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2513 ret = mt7530_setup_gpio(priv); 2514 if (ret) 2515 return ret; 2516 } 2517 #endif /* CONFIG_GPIOLIB */ 2518 2519 /* Flush the FDB table */ 2520 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2521 if (ret < 0) 2522 return ret; 2523 2524 return 0; 2525 } 2526 2527 static int 2528 mt7531_setup_common(struct dsa_switch *ds) 2529 { 2530 struct mt7530_priv *priv = ds->priv; 2531 int ret, i; 2532 2533 mt753x_trap_frames(priv); 2534 2535 /* Enable and reset MIB counters */ 2536 mt7530_mib_reset(ds); 2537 2538 /* Disable flooding on all ports */ 2539 mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK | 2540 UNU_FFP_MASK); 2541 2542 for (i = 0; i < priv->ds->num_ports; i++) { 2543 /* Clear link settings and enable force mode to force link down 2544 * on all ports until they're enabled later. 2545 */ 2546 mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | 2547 MT7531_FORCE_MODE_MASK, MT7531_FORCE_MODE_MASK); 2548 2549 /* Disable forwarding by default on all ports */ 2550 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2551 PCR_MATRIX_CLR); 2552 2553 /* Disable learning by default on all ports */ 2554 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2555 2556 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2557 2558 if (dsa_is_cpu_port(ds, i)) { 2559 mt753x_cpu_port_enable(ds, i); 2560 } else { 2561 mt7530_port_disable(ds, i); 2562 2563 /* Set default PVID to 0 on all user ports */ 2564 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2565 G0_PORT_VID_DEF); 2566 } 2567 2568 /* Enable consistent egress tag */ 2569 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2570 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2571 } 2572 2573 /* Allow mirroring frames received on the local port (monitor port). */ 2574 mt7530_set(priv, MT753X_AGC, LOCAL_EN); 2575 2576 /* Flush the FDB table */ 2577 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2578 if (ret < 0) 2579 return ret; 2580 2581 return 0; 2582 } 2583 2584 static int 2585 mt7531_setup(struct dsa_switch *ds) 2586 { 2587 struct mt7530_priv *priv = ds->priv; 2588 struct mt7530_dummy_poll p; 2589 u32 val, id; 2590 int ret, i; 2591 2592 /* Reset whole chip through gpio pin or memory-mapped registers for 2593 * different type of hardware 2594 */ 2595 if (priv->mcm) { 2596 reset_control_assert(priv->rstc); 2597 usleep_range(5000, 5100); 2598 reset_control_deassert(priv->rstc); 2599 } else { 2600 gpiod_set_value_cansleep(priv->reset, 0); 2601 usleep_range(5000, 5100); 2602 gpiod_set_value_cansleep(priv->reset, 1); 2603 } 2604 2605 /* Waiting for MT7530 got to stable */ 2606 INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); 2607 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2608 20, 1000000); 2609 if (ret < 0) { 2610 dev_err(priv->dev, "reset timeout\n"); 2611 return ret; 2612 } 2613 2614 id = mt7530_read(priv, MT7531_CREV); 2615 id >>= CHIP_NAME_SHIFT; 2616 2617 if (id != MT7531_ID) { 2618 dev_err(priv->dev, "chip %x can't be supported\n", id); 2619 return -ENODEV; 2620 } 2621 2622 /* MT7531AE has got two SGMII units. One for port 5, one for port 6. 2623 * MT7531BE has got only one SGMII unit which is for port 6. 2624 */ 2625 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 2626 priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); 2627 2628 /* Force link down on all ports before internal reset */ 2629 for (i = 0; i < priv->ds->num_ports; i++) 2630 mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK); 2631 2632 /* Reset the switch through internal reset */ 2633 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); 2634 2635 if (!priv->p5_sgmii) { 2636 mt7531_pll_setup(priv); 2637 } else { 2638 /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on 2639 * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO 2640 * to expose the MDIO bus of the switch. 2641 */ 2642 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2643 MT7531_EXT_P_MDC_11); 2644 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2645 MT7531_EXT_P_MDIO_12); 2646 } 2647 2648 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2649 MT7531_GPIO0_INTERRUPT); 2650 2651 /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since 2652 * phy_device has not yet been created provided for 2653 * phy_[read,write]_mmd_indirect is called, we provide our own 2654 * mt7531_ind_mmd_phy_[read,write] to complete this function. 2655 */ 2656 val = mt7531_ind_c45_phy_read(priv, 2657 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 2658 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2659 val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE; 2660 val &= ~MT7531_PHY_PLL_OFF; 2661 mt7531_ind_c45_phy_write(priv, 2662 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 2663 MDIO_MMD_VEND2, CORE_PLL_GROUP4, val); 2664 2665 /* Disable EEE advertisement on the switch PHYs. */ 2666 for (i = MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr); 2667 i < MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr) + MT7530_NUM_PHYS; 2668 i++) { 2669 mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 2670 0); 2671 } 2672 2673 ret = mt7531_setup_common(ds); 2674 if (ret) 2675 return ret; 2676 2677 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2678 ret = mt7530_setup_vlan0(priv); 2679 if (ret) 2680 return ret; 2681 2682 ds->assisted_learning_on_cpu_port = true; 2683 ds->mtu_enforcement_ingress = true; 2684 2685 return 0; 2686 } 2687 2688 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2689 struct phylink_config *config) 2690 { 2691 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2692 2693 switch (port) { 2694 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2695 case 0 ... 4: 2696 __set_bit(PHY_INTERFACE_MODE_GMII, 2697 config->supported_interfaces); 2698 break; 2699 2700 /* Port 5 supports rgmii with delays, mii, and gmii. */ 2701 case 5: 2702 phy_interface_set_rgmii(config->supported_interfaces); 2703 __set_bit(PHY_INTERFACE_MODE_MII, 2704 config->supported_interfaces); 2705 __set_bit(PHY_INTERFACE_MODE_GMII, 2706 config->supported_interfaces); 2707 break; 2708 2709 /* Port 6 supports rgmii and trgmii. */ 2710 case 6: 2711 __set_bit(PHY_INTERFACE_MODE_RGMII, 2712 config->supported_interfaces); 2713 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2714 config->supported_interfaces); 2715 break; 2716 } 2717 } 2718 2719 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2720 struct phylink_config *config) 2721 { 2722 struct mt7530_priv *priv = ds->priv; 2723 2724 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2725 2726 switch (port) { 2727 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2728 case 0 ... 4: 2729 __set_bit(PHY_INTERFACE_MODE_GMII, 2730 config->supported_interfaces); 2731 break; 2732 2733 /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on 2734 * MT7531AE. 2735 */ 2736 case 5: 2737 if (!priv->p5_sgmii) { 2738 phy_interface_set_rgmii(config->supported_interfaces); 2739 break; 2740 } 2741 fallthrough; 2742 2743 /* Port 6 supports sgmii/802.3z. */ 2744 case 6: 2745 __set_bit(PHY_INTERFACE_MODE_SGMII, 2746 config->supported_interfaces); 2747 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2748 config->supported_interfaces); 2749 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2750 config->supported_interfaces); 2751 2752 config->mac_capabilities |= MAC_2500FD; 2753 break; 2754 } 2755 } 2756 2757 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, 2758 struct phylink_config *config) 2759 { 2760 switch (port) { 2761 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2762 case 0 ... 3: 2763 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2764 config->supported_interfaces); 2765 2766 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2767 break; 2768 2769 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2770 case 6: 2771 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2772 config->supported_interfaces); 2773 2774 config->mac_capabilities |= MAC_10000FD; 2775 break; 2776 } 2777 } 2778 2779 static void 2780 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2781 phy_interface_t interface) 2782 { 2783 struct mt7530_priv *priv = ds->priv; 2784 2785 if (port == 5) 2786 mt7530_setup_port5(priv->ds, interface); 2787 else if (port == 6) 2788 mt7530_setup_port6(priv->ds, interface); 2789 } 2790 2791 static void mt7531_rgmii_setup(struct mt7530_priv *priv, 2792 phy_interface_t interface, 2793 struct phy_device *phydev) 2794 { 2795 u32 val; 2796 2797 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2798 val |= GP_CLK_EN; 2799 val &= ~GP_MODE_MASK; 2800 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2801 val &= ~CLK_SKEW_IN_MASK; 2802 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2803 val &= ~CLK_SKEW_OUT_MASK; 2804 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2805 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2806 2807 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2808 if (!phydev || phy_driver_is_genphy(phydev)) { 2809 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2810 switch (interface) { 2811 case PHY_INTERFACE_MODE_RGMII: 2812 val |= TXCLK_NO_REVERSE; 2813 val |= RXCLK_NO_DELAY; 2814 break; 2815 case PHY_INTERFACE_MODE_RGMII_RXID: 2816 val |= TXCLK_NO_REVERSE; 2817 break; 2818 case PHY_INTERFACE_MODE_RGMII_TXID: 2819 val |= RXCLK_NO_DELAY; 2820 break; 2821 case PHY_INTERFACE_MODE_RGMII_ID: 2822 break; 2823 default: 2824 break; 2825 } 2826 } 2827 2828 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2829 } 2830 2831 static void 2832 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2833 phy_interface_t interface) 2834 { 2835 struct mt7530_priv *priv = ds->priv; 2836 struct phy_device *phydev; 2837 struct dsa_port *dp; 2838 2839 if (phy_interface_mode_is_rgmii(interface)) { 2840 dp = dsa_to_port(ds, port); 2841 phydev = dp->user->phydev; 2842 mt7531_rgmii_setup(priv, interface, phydev); 2843 } 2844 } 2845 2846 static struct phylink_pcs * 2847 mt753x_phylink_mac_select_pcs(struct phylink_config *config, 2848 phy_interface_t interface) 2849 { 2850 struct dsa_port *dp = dsa_phylink_to_port(config); 2851 struct mt7530_priv *priv = dp->ds->priv; 2852 2853 switch (interface) { 2854 case PHY_INTERFACE_MODE_TRGMII: 2855 return &priv->pcs[dp->index].pcs; 2856 case PHY_INTERFACE_MODE_SGMII: 2857 case PHY_INTERFACE_MODE_1000BASEX: 2858 case PHY_INTERFACE_MODE_2500BASEX: 2859 return priv->ports[dp->index].sgmii_pcs; 2860 default: 2861 return NULL; 2862 } 2863 } 2864 2865 static void 2866 mt753x_phylink_mac_config(struct phylink_config *config, unsigned int mode, 2867 const struct phylink_link_state *state) 2868 { 2869 struct dsa_port *dp = dsa_phylink_to_port(config); 2870 struct dsa_switch *ds = dp->ds; 2871 struct mt7530_priv *priv; 2872 int port = dp->index; 2873 2874 priv = ds->priv; 2875 2876 if ((port == 5 || port == 6) && priv->info->mac_port_config) 2877 priv->info->mac_port_config(ds, port, mode, state->interface); 2878 2879 /* Are we connected to external phy */ 2880 if (port == 5 && dsa_is_user_port(ds, 5)) 2881 mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY); 2882 } 2883 2884 static void mt753x_phylink_mac_link_down(struct phylink_config *config, 2885 unsigned int mode, 2886 phy_interface_t interface) 2887 { 2888 struct dsa_port *dp = dsa_phylink_to_port(config); 2889 struct mt7530_priv *priv = dp->ds->priv; 2890 2891 mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); 2892 } 2893 2894 static void mt753x_phylink_mac_link_up(struct phylink_config *config, 2895 struct phy_device *phydev, 2896 unsigned int mode, 2897 phy_interface_t interface, 2898 int speed, int duplex, 2899 bool tx_pause, bool rx_pause) 2900 { 2901 struct dsa_port *dp = dsa_phylink_to_port(config); 2902 struct mt7530_priv *priv = dp->ds->priv; 2903 u32 mcr; 2904 2905 mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK; 2906 2907 switch (speed) { 2908 case SPEED_1000: 2909 case SPEED_2500: 2910 case SPEED_10000: 2911 mcr |= PMCR_FORCE_SPEED_1000; 2912 break; 2913 case SPEED_100: 2914 mcr |= PMCR_FORCE_SPEED_100; 2915 break; 2916 } 2917 if (duplex == DUPLEX_FULL) { 2918 mcr |= PMCR_FORCE_FDX; 2919 if (tx_pause) 2920 mcr |= PMCR_FORCE_TX_FC_EN; 2921 if (rx_pause) 2922 mcr |= PMCR_FORCE_RX_FC_EN; 2923 } 2924 2925 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { 2926 switch (speed) { 2927 case SPEED_1000: 2928 case SPEED_2500: 2929 mcr |= PMCR_FORCE_EEE1G; 2930 break; 2931 case SPEED_100: 2932 mcr |= PMCR_FORCE_EEE100; 2933 break; 2934 } 2935 } 2936 2937 mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr); 2938 } 2939 2940 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 2941 struct phylink_config *config) 2942 { 2943 struct mt7530_priv *priv = ds->priv; 2944 2945 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE; 2946 2947 priv->info->mac_port_get_caps(ds, port, config); 2948 } 2949 2950 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 2951 unsigned long *supported, 2952 const struct phylink_link_state *state) 2953 { 2954 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 2955 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 2956 phy_interface_mode_is_8023z(state->interface)) 2957 phylink_clear(supported, Autoneg); 2958 2959 return 0; 2960 } 2961 2962 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, 2963 struct phylink_link_state *state) 2964 { 2965 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2966 int port = pcs_to_mt753x_pcs(pcs)->port; 2967 u32 pmsr; 2968 2969 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2970 2971 state->link = (pmsr & PMSR_LINK); 2972 state->an_complete = state->link; 2973 state->duplex = !!(pmsr & PMSR_DPX); 2974 2975 switch (pmsr & PMSR_SPEED_MASK) { 2976 case PMSR_SPEED_10: 2977 state->speed = SPEED_10; 2978 break; 2979 case PMSR_SPEED_100: 2980 state->speed = SPEED_100; 2981 break; 2982 case PMSR_SPEED_1000: 2983 state->speed = SPEED_1000; 2984 break; 2985 default: 2986 state->speed = SPEED_UNKNOWN; 2987 break; 2988 } 2989 2990 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2991 if (pmsr & PMSR_RX_FC) 2992 state->pause |= MLO_PAUSE_RX; 2993 if (pmsr & PMSR_TX_FC) 2994 state->pause |= MLO_PAUSE_TX; 2995 } 2996 2997 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 2998 phy_interface_t interface, 2999 const unsigned long *advertising, 3000 bool permit_pause_to_mac) 3001 { 3002 return 0; 3003 } 3004 3005 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 3006 { 3007 } 3008 3009 static const struct phylink_pcs_ops mt7530_pcs_ops = { 3010 .pcs_validate = mt753x_pcs_validate, 3011 .pcs_get_state = mt7530_pcs_get_state, 3012 .pcs_config = mt753x_pcs_config, 3013 .pcs_an_restart = mt7530_pcs_an_restart, 3014 }; 3015 3016 static int 3017 mt753x_setup(struct dsa_switch *ds) 3018 { 3019 struct mt7530_priv *priv = ds->priv; 3020 int ret = priv->info->sw_setup(ds); 3021 int i; 3022 3023 if (ret) 3024 return ret; 3025 3026 ret = mt7530_setup_irq(priv); 3027 if (ret) 3028 return ret; 3029 3030 ret = mt7530_setup_mdio(priv); 3031 if (ret && priv->irq) 3032 mt7530_free_irq_common(priv); 3033 if (ret) 3034 return ret; 3035 3036 /* Initialise the PCS devices */ 3037 for (i = 0; i < priv->ds->num_ports; i++) { 3038 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3039 priv->pcs[i].pcs.neg_mode = true; 3040 priv->pcs[i].priv = priv; 3041 priv->pcs[i].port = i; 3042 } 3043 3044 if (priv->create_sgmii) { 3045 ret = priv->create_sgmii(priv); 3046 if (ret && priv->irq) 3047 mt7530_free_irq(priv); 3048 } 3049 3050 return ret; 3051 } 3052 3053 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3054 struct ethtool_keee *e) 3055 { 3056 struct mt7530_priv *priv = ds->priv; 3057 u32 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port)); 3058 3059 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3060 e->tx_lpi_timer = LPI_THRESH_GET(eeecr); 3061 3062 return 0; 3063 } 3064 3065 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3066 struct ethtool_keee *e) 3067 { 3068 struct mt7530_priv *priv = ds->priv; 3069 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3070 3071 if (e->tx_lpi_timer > 0xFFF) 3072 return -EINVAL; 3073 3074 set = LPI_THRESH_SET(e->tx_lpi_timer); 3075 if (!e->tx_lpi_enabled) 3076 /* Force LPI Mode without a delay */ 3077 set |= LPI_MODE_EN; 3078 mt7530_rmw(priv, MT753X_PMEEECR_P(port), mask, set); 3079 3080 return 0; 3081 } 3082 3083 static void 3084 mt753x_conduit_state_change(struct dsa_switch *ds, 3085 const struct net_device *conduit, 3086 bool operational) 3087 { 3088 struct dsa_port *cpu_dp = conduit->dsa_ptr; 3089 struct mt7530_priv *priv = ds->priv; 3090 int val = 0; 3091 u8 mask; 3092 3093 /* Set the CPU port to trap frames to for MT7530. Trapped frames will be 3094 * forwarded to the numerically smallest CPU port whose conduit 3095 * interface is up. 3096 */ 3097 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 3098 return; 3099 3100 mask = BIT(cpu_dp->index); 3101 3102 if (operational) 3103 priv->active_cpu_ports |= mask; 3104 else 3105 priv->active_cpu_ports &= ~mask; 3106 3107 if (priv->active_cpu_ports) { 3108 val = MT7530_CPU_EN | 3109 MT7530_CPU_PORT(__ffs(priv->active_cpu_ports)); 3110 } 3111 3112 mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val); 3113 } 3114 3115 static int mt7988_setup(struct dsa_switch *ds) 3116 { 3117 struct mt7530_priv *priv = ds->priv; 3118 3119 /* Reset the switch */ 3120 reset_control_assert(priv->rstc); 3121 usleep_range(20, 50); 3122 reset_control_deassert(priv->rstc); 3123 usleep_range(20, 50); 3124 3125 /* Reset the switch PHYs */ 3126 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST); 3127 3128 return mt7531_setup_common(ds); 3129 } 3130 3131 const struct dsa_switch_ops mt7530_switch_ops = { 3132 .get_tag_protocol = mtk_get_tag_protocol, 3133 .setup = mt753x_setup, 3134 .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, 3135 .get_strings = mt7530_get_strings, 3136 .get_ethtool_stats = mt7530_get_ethtool_stats, 3137 .get_sset_count = mt7530_get_sset_count, 3138 .set_ageing_time = mt7530_set_ageing_time, 3139 .port_enable = mt7530_port_enable, 3140 .port_disable = mt7530_port_disable, 3141 .port_change_mtu = mt7530_port_change_mtu, 3142 .port_max_mtu = mt7530_port_max_mtu, 3143 .port_stp_state_set = mt7530_stp_state_set, 3144 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3145 .port_bridge_flags = mt7530_port_bridge_flags, 3146 .port_bridge_join = mt7530_port_bridge_join, 3147 .port_bridge_leave = mt7530_port_bridge_leave, 3148 .port_fdb_add = mt7530_port_fdb_add, 3149 .port_fdb_del = mt7530_port_fdb_del, 3150 .port_fdb_dump = mt7530_port_fdb_dump, 3151 .port_mdb_add = mt7530_port_mdb_add, 3152 .port_mdb_del = mt7530_port_mdb_del, 3153 .port_vlan_filtering = mt7530_port_vlan_filtering, 3154 .port_vlan_add = mt7530_port_vlan_add, 3155 .port_vlan_del = mt7530_port_vlan_del, 3156 .port_mirror_add = mt753x_port_mirror_add, 3157 .port_mirror_del = mt753x_port_mirror_del, 3158 .phylink_get_caps = mt753x_phylink_get_caps, 3159 .get_mac_eee = mt753x_get_mac_eee, 3160 .set_mac_eee = mt753x_set_mac_eee, 3161 .conduit_state_change = mt753x_conduit_state_change, 3162 }; 3163 EXPORT_SYMBOL_GPL(mt7530_switch_ops); 3164 3165 static const struct phylink_mac_ops mt753x_phylink_mac_ops = { 3166 .mac_select_pcs = mt753x_phylink_mac_select_pcs, 3167 .mac_config = mt753x_phylink_mac_config, 3168 .mac_link_down = mt753x_phylink_mac_link_down, 3169 .mac_link_up = mt753x_phylink_mac_link_up, 3170 }; 3171 3172 const struct mt753x_info mt753x_table[] = { 3173 [ID_MT7621] = { 3174 .id = ID_MT7621, 3175 .pcs_ops = &mt7530_pcs_ops, 3176 .sw_setup = mt7530_setup, 3177 .phy_read_c22 = mt7530_phy_read_c22, 3178 .phy_write_c22 = mt7530_phy_write_c22, 3179 .phy_read_c45 = mt7530_phy_read_c45, 3180 .phy_write_c45 = mt7530_phy_write_c45, 3181 .mac_port_get_caps = mt7530_mac_port_get_caps, 3182 .mac_port_config = mt7530_mac_config, 3183 }, 3184 [ID_MT7530] = { 3185 .id = ID_MT7530, 3186 .pcs_ops = &mt7530_pcs_ops, 3187 .sw_setup = mt7530_setup, 3188 .phy_read_c22 = mt7530_phy_read_c22, 3189 .phy_write_c22 = mt7530_phy_write_c22, 3190 .phy_read_c45 = mt7530_phy_read_c45, 3191 .phy_write_c45 = mt7530_phy_write_c45, 3192 .mac_port_get_caps = mt7530_mac_port_get_caps, 3193 .mac_port_config = mt7530_mac_config, 3194 }, 3195 [ID_MT7531] = { 3196 .id = ID_MT7531, 3197 .pcs_ops = &mt7530_pcs_ops, 3198 .sw_setup = mt7531_setup, 3199 .phy_read_c22 = mt7531_ind_c22_phy_read, 3200 .phy_write_c22 = mt7531_ind_c22_phy_write, 3201 .phy_read_c45 = mt7531_ind_c45_phy_read, 3202 .phy_write_c45 = mt7531_ind_c45_phy_write, 3203 .mac_port_get_caps = mt7531_mac_port_get_caps, 3204 .mac_port_config = mt7531_mac_config, 3205 }, 3206 [ID_MT7988] = { 3207 .id = ID_MT7988, 3208 .pcs_ops = &mt7530_pcs_ops, 3209 .sw_setup = mt7988_setup, 3210 .phy_read_c22 = mt7531_ind_c22_phy_read, 3211 .phy_write_c22 = mt7531_ind_c22_phy_write, 3212 .phy_read_c45 = mt7531_ind_c45_phy_read, 3213 .phy_write_c45 = mt7531_ind_c45_phy_write, 3214 .mac_port_get_caps = mt7988_mac_port_get_caps, 3215 }, 3216 }; 3217 EXPORT_SYMBOL_GPL(mt753x_table); 3218 3219 int 3220 mt7530_probe_common(struct mt7530_priv *priv) 3221 { 3222 struct device *dev = priv->dev; 3223 3224 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 3225 if (!priv->ds) 3226 return -ENOMEM; 3227 3228 priv->ds->dev = dev; 3229 priv->ds->num_ports = MT7530_NUM_PORTS; 3230 3231 /* Get the hardware identifier from the devicetree node. 3232 * We will need it for some of the clock and regulator setup. 3233 */ 3234 priv->info = of_device_get_match_data(dev); 3235 if (!priv->info) 3236 return -EINVAL; 3237 3238 priv->id = priv->info->id; 3239 priv->dev = dev; 3240 priv->ds->priv = priv; 3241 priv->ds->ops = &mt7530_switch_ops; 3242 priv->ds->phylink_mac_ops = &mt753x_phylink_mac_ops; 3243 mutex_init(&priv->reg_mutex); 3244 dev_set_drvdata(dev, priv); 3245 3246 return 0; 3247 } 3248 EXPORT_SYMBOL_GPL(mt7530_probe_common); 3249 3250 void 3251 mt7530_remove_common(struct mt7530_priv *priv) 3252 { 3253 if (priv->irq) 3254 mt7530_free_irq(priv); 3255 3256 dsa_unregister_switch(priv->ds); 3257 3258 mutex_destroy(&priv->reg_mutex); 3259 } 3260 EXPORT_SYMBOL_GPL(mt7530_remove_common); 3261 3262 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3263 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3264 MODULE_LICENSE("GPL"); 3265