1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 #include <net/pkt_cls.h> 25 26 #include "mt7530.h" 27 28 #define MT7530_STATS_POLL_INTERVAL (1 * HZ) 29 #define MT7530_STATS_RATE_LIMIT (HZ / 10) 30 31 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 32 { 33 return container_of(pcs, struct mt753x_pcs, pcs); 34 } 35 36 /* String, offset, and register size in bytes if different from 4 bytes */ 37 static const struct mt7530_mib_desc mt7530_mib[] = { 38 MIB_DESC(1, MT7530_PORT_MIB_TX_DROP, "TxDrop"), 39 MIB_DESC(1, MT7530_PORT_MIB_TX_CRC_ERR, "TxCrcErr"), 40 MIB_DESC(1, MT7530_PORT_MIB_TX_COLLISION, "TxCollision"), 41 MIB_DESC(1, MT7530_PORT_MIB_RX_DROP, "RxDrop"), 42 MIB_DESC(1, MT7530_PORT_MIB_RX_FILTERING, "RxFiltering"), 43 MIB_DESC(1, MT7530_PORT_MIB_RX_CRC_ERR, "RxCrcErr"), 44 MIB_DESC(1, MT7530_PORT_MIB_RX_CTRL_DROP, "RxCtrlDrop"), 45 MIB_DESC(1, MT7530_PORT_MIB_RX_INGRESS_DROP, "RxIngressDrop"), 46 MIB_DESC(1, MT7530_PORT_MIB_RX_ARL_DROP, "RxArlDrop"), 47 }; 48 49 static void 50 mt7530_mutex_lock(struct mt7530_priv *priv) 51 { 52 if (priv->bus) 53 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 54 } 55 56 static void 57 mt7530_mutex_unlock(struct mt7530_priv *priv) 58 { 59 if (priv->bus) 60 mutex_unlock(&priv->bus->mdio_lock); 61 } 62 63 static void 64 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 65 { 66 struct mii_bus *bus = priv->bus; 67 int ret; 68 69 mt7530_mutex_lock(priv); 70 71 /* Write the desired MMD Devad */ 72 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 73 MII_MMD_CTRL, MDIO_MMD_VEND2); 74 if (ret < 0) 75 goto err; 76 77 /* Write the desired MMD register address */ 78 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 79 MII_MMD_DATA, reg); 80 if (ret < 0) 81 goto err; 82 83 /* Select the Function : DATA with no post increment */ 84 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 85 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); 86 if (ret < 0) 87 goto err; 88 89 /* Write the data into MMD's selected register */ 90 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 91 MII_MMD_DATA, val); 92 err: 93 if (ret < 0) 94 dev_err(&bus->dev, "failed to write mmd register\n"); 95 96 mt7530_mutex_unlock(priv); 97 } 98 99 static void 100 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 101 { 102 struct mii_bus *bus = priv->bus; 103 u32 val; 104 int ret; 105 106 mt7530_mutex_lock(priv); 107 108 /* Write the desired MMD Devad */ 109 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 110 MII_MMD_CTRL, MDIO_MMD_VEND2); 111 if (ret < 0) 112 goto err; 113 114 /* Write the desired MMD register address */ 115 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 116 MII_MMD_DATA, reg); 117 if (ret < 0) 118 goto err; 119 120 /* Select the Function : DATA with no post increment */ 121 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 122 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); 123 if (ret < 0) 124 goto err; 125 126 /* Read the content of the MMD's selected register */ 127 ret = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 128 MII_MMD_DATA); 129 if (ret < 0) 130 goto err; 131 val = ret; 132 133 val &= ~mask; 134 val |= set; 135 /* Write the data into MMD's selected register */ 136 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 137 MII_MMD_DATA, val); 138 err: 139 if (ret < 0) 140 dev_err(&bus->dev, "failed to write mmd register\n"); 141 142 mt7530_mutex_unlock(priv); 143 } 144 145 static void 146 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 147 { 148 core_rmw(priv, reg, 0, val); 149 } 150 151 static void 152 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 153 { 154 core_rmw(priv, reg, val, 0); 155 } 156 157 static int 158 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 159 { 160 int ret; 161 162 ret = regmap_write(priv->regmap, reg, val); 163 164 if (ret < 0) 165 dev_err(priv->dev, 166 "failed to write mt7530 register\n"); 167 168 return ret; 169 } 170 171 static u32 172 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 173 { 174 int ret; 175 u32 val; 176 177 ret = regmap_read(priv->regmap, reg, &val); 178 if (ret) { 179 WARN_ON_ONCE(1); 180 dev_err(priv->dev, 181 "failed to read mt7530 register\n"); 182 return 0; 183 } 184 185 return val; 186 } 187 188 static int 189 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 190 { 191 int ret; 192 193 mt7530_mutex_lock(priv); 194 195 ret = mt7530_mii_write(priv, reg, val); 196 197 mt7530_mutex_unlock(priv); 198 199 return ret; 200 } 201 202 static u32 203 _mt7530_read(struct mt7530_dummy_poll *p) 204 { 205 u32 val; 206 207 mt7530_mutex_lock(p->priv); 208 209 val = mt7530_mii_read(p->priv, p->reg); 210 211 mt7530_mutex_unlock(p->priv); 212 213 return val; 214 } 215 216 static u32 217 mt7530_read(struct mt7530_priv *priv, u32 reg) 218 { 219 struct mt7530_dummy_poll p; 220 221 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 222 return _mt7530_read(&p); 223 } 224 225 static void 226 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 227 u32 mask, u32 set) 228 { 229 mt7530_mutex_lock(priv); 230 231 regmap_update_bits(priv->regmap, reg, mask, set); 232 233 mt7530_mutex_unlock(priv); 234 } 235 236 static void 237 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 238 { 239 mt7530_rmw(priv, reg, val, val); 240 } 241 242 static void 243 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 244 { 245 mt7530_rmw(priv, reg, val, 0); 246 } 247 248 static int 249 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 250 { 251 u32 val; 252 int ret; 253 254 /* Set the command operating upon the MAC address entries */ 255 val = ATC_BUSY | ATC_MAT(0) | cmd; 256 ret = mt7530_write(priv, MT7530_ATC, val); 257 if (ret) 258 return ret; 259 260 mt7530_mutex_lock(priv); 261 262 ret = regmap_read_poll_timeout(priv->regmap, MT7530_ATC, val, 263 !(val & ATC_BUSY), 20, 20000); 264 if (!ret) 265 ret = regmap_read(priv->regmap, MT7530_ATC, &val); 266 267 mt7530_mutex_unlock(priv); 268 269 if (ret < 0) { 270 dev_err(priv->dev, "reset timeout\n"); 271 return ret; 272 } 273 274 /* Additional sanity for read command if the specified 275 * entry is invalid 276 */ 277 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 278 return -EINVAL; 279 280 if (rsp) 281 *rsp = val; 282 283 return 0; 284 } 285 286 static void 287 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 288 { 289 u32 reg[3]; 290 int i; 291 292 /* Read from ARL table into an array */ 293 for (i = 0; i < 3; i++) { 294 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 295 296 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 297 __func__, __LINE__, i, reg[i]); 298 } 299 300 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 301 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 302 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 303 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 304 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 305 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 306 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 307 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 308 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 309 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 310 } 311 312 static void 313 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 314 u8 port_mask, const u8 *mac, 315 u8 aging, u8 type) 316 { 317 u32 reg[3] = { 0 }; 318 int i; 319 320 reg[1] |= vid & CVID_MASK; 321 reg[1] |= ATA2_IVL; 322 reg[1] |= ATA2_FID(FID_BRIDGED); 323 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 324 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 325 /* STATIC_ENT indicate that entry is static wouldn't 326 * be aged out and STATIC_EMP specified as erasing an 327 * entry 328 */ 329 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 330 reg[1] |= mac[5] << MAC_BYTE_5; 331 reg[1] |= mac[4] << MAC_BYTE_4; 332 reg[0] |= mac[3] << MAC_BYTE_3; 333 reg[0] |= mac[2] << MAC_BYTE_2; 334 reg[0] |= mac[1] << MAC_BYTE_1; 335 reg[0] |= mac[0] << MAC_BYTE_0; 336 337 /* Write array into the ARL table */ 338 for (i = 0; i < 3; i++) 339 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 340 } 341 342 /* Set up switch core clock for MT7530 */ 343 static void mt7530_pll_setup(struct mt7530_priv *priv) 344 { 345 /* Disable core clock */ 346 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 347 348 /* Disable PLL */ 349 core_write(priv, CORE_GSWPLL_GRP1, 0); 350 351 /* Set core clock into 500Mhz */ 352 core_write(priv, CORE_GSWPLL_GRP2, 353 RG_GSWPLL_POSDIV_500M(1) | 354 RG_GSWPLL_FBKDIV_500M(25)); 355 356 /* Enable PLL */ 357 core_write(priv, CORE_GSWPLL_GRP1, 358 RG_GSWPLL_EN_PRE | 359 RG_GSWPLL_POSDIV_200M(2) | 360 RG_GSWPLL_FBKDIV_200M(32)); 361 362 udelay(20); 363 364 /* Enable core clock */ 365 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 366 } 367 368 /* If port 6 is available as a CPU port, always prefer that as the default, 369 * otherwise don't care. 370 */ 371 static struct dsa_port * 372 mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) 373 { 374 struct dsa_port *cpu_dp = dsa_to_port(ds, 6); 375 376 if (dsa_port_is_cpu(cpu_dp)) 377 return cpu_dp; 378 379 return NULL; 380 } 381 382 /* Setup port 6 interface mode and TRGMII TX circuit */ 383 static void 384 mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) 385 { 386 struct mt7530_priv *priv = ds->priv; 387 u32 ncpo1, ssc_delta, xtal; 388 389 /* Disable the MT7530 TRGMII clocks */ 390 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 391 392 if (interface == PHY_INTERFACE_MODE_RGMII) { 393 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 394 P6_INTF_MODE(0)); 395 return; 396 } 397 398 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1)); 399 400 xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK; 401 402 if (xtal == MT7530_XTAL_25MHZ) 403 ssc_delta = 0x57; 404 else 405 ssc_delta = 0x87; 406 407 if (priv->id == ID_MT7621) { 408 /* PLL frequency: 125MHz: 1.0GBit */ 409 if (xtal == MT7530_XTAL_40MHZ) 410 ncpo1 = 0x0640; 411 if (xtal == MT7530_XTAL_25MHZ) 412 ncpo1 = 0x0a00; 413 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 414 if (xtal == MT7530_XTAL_40MHZ) 415 ncpo1 = 0x0c80; 416 if (xtal == MT7530_XTAL_25MHZ) 417 ncpo1 = 0x1400; 418 } 419 420 /* Setup the MT7530 TRGMII Tx Clock */ 421 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 422 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 423 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 424 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 425 core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | 426 RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); 427 core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL | 428 RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1)); 429 core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG | 430 RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 431 432 /* Enable the MT7530 TRGMII clocks */ 433 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 434 } 435 436 static void 437 mt7531_pll_setup(struct mt7530_priv *priv) 438 { 439 enum mt7531_xtal_fsel xtal; 440 u32 top_sig; 441 u32 hwstrap; 442 u32 val; 443 444 val = mt7530_read(priv, MT7531_CREV); 445 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 446 hwstrap = mt7530_read(priv, MT753X_TRAP); 447 if ((val & CHIP_REV_M) > 0) 448 xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ : 449 MT7531_XTAL_FSEL_25MHZ; 450 else 451 xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ : 452 MT7531_XTAL_FSEL_40MHZ; 453 454 /* Step 1 : Disable MT7531 COREPLL */ 455 val = mt7530_read(priv, MT7531_PLLGP_EN); 456 val &= ~EN_COREPLL; 457 mt7530_write(priv, MT7531_PLLGP_EN, val); 458 459 /* Step 2: switch to XTAL output */ 460 val = mt7530_read(priv, MT7531_PLLGP_EN); 461 val |= SW_CLKSW; 462 mt7530_write(priv, MT7531_PLLGP_EN, val); 463 464 val = mt7530_read(priv, MT7531_PLLGP_CR0); 465 val &= ~RG_COREPLL_EN; 466 mt7530_write(priv, MT7531_PLLGP_CR0, val); 467 468 /* Step 3: disable PLLGP and enable program PLLGP */ 469 val = mt7530_read(priv, MT7531_PLLGP_EN); 470 val |= SW_PLLGP; 471 mt7530_write(priv, MT7531_PLLGP_EN, val); 472 473 /* Step 4: program COREPLL output frequency to 500MHz */ 474 val = mt7530_read(priv, MT7531_PLLGP_CR0); 475 val &= ~RG_COREPLL_POSDIV_M; 476 val |= 2 << RG_COREPLL_POSDIV_S; 477 mt7530_write(priv, MT7531_PLLGP_CR0, val); 478 usleep_range(25, 35); 479 480 switch (xtal) { 481 case MT7531_XTAL_FSEL_25MHZ: 482 val = mt7530_read(priv, MT7531_PLLGP_CR0); 483 val &= ~RG_COREPLL_SDM_PCW_M; 484 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 485 mt7530_write(priv, MT7531_PLLGP_CR0, val); 486 break; 487 case MT7531_XTAL_FSEL_40MHZ: 488 val = mt7530_read(priv, MT7531_PLLGP_CR0); 489 val &= ~RG_COREPLL_SDM_PCW_M; 490 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 491 mt7530_write(priv, MT7531_PLLGP_CR0, val); 492 break; 493 } 494 495 /* Set feedback divide ratio update signal to high */ 496 val = mt7530_read(priv, MT7531_PLLGP_CR0); 497 val |= RG_COREPLL_SDM_PCW_CHG; 498 mt7530_write(priv, MT7531_PLLGP_CR0, val); 499 /* Wait for at least 16 XTAL clocks */ 500 usleep_range(10, 20); 501 502 /* Step 5: set feedback divide ratio update signal to low */ 503 val = mt7530_read(priv, MT7531_PLLGP_CR0); 504 val &= ~RG_COREPLL_SDM_PCW_CHG; 505 mt7530_write(priv, MT7531_PLLGP_CR0, val); 506 507 /* Enable 325M clock for SGMII */ 508 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 509 510 /* Enable 250SSC clock for RGMII */ 511 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 512 513 /* Step 6: Enable MT7531 PLL */ 514 val = mt7530_read(priv, MT7531_PLLGP_CR0); 515 val |= RG_COREPLL_EN; 516 mt7530_write(priv, MT7531_PLLGP_CR0, val); 517 518 val = mt7530_read(priv, MT7531_PLLGP_EN); 519 val |= EN_COREPLL; 520 mt7530_write(priv, MT7531_PLLGP_EN, val); 521 usleep_range(25, 35); 522 } 523 524 static void 525 mt7530_mib_reset(struct dsa_switch *ds) 526 { 527 struct mt7530_priv *priv = ds->priv; 528 529 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 530 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 531 } 532 533 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 534 { 535 return mdiobus_read_nested(priv->bus, port, regnum); 536 } 537 538 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 539 u16 val) 540 { 541 return mdiobus_write_nested(priv->bus, port, regnum, val); 542 } 543 544 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 545 int devad, int regnum) 546 { 547 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 548 } 549 550 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 551 int regnum, u16 val) 552 { 553 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 554 } 555 556 static int 557 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 558 int regnum) 559 { 560 u32 reg, val; 561 int ret; 562 563 mt7530_mutex_lock(priv); 564 565 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 566 !(val & MT7531_PHY_ACS_ST), 20, 100000); 567 if (ret < 0) { 568 dev_err(priv->dev, "poll timeout\n"); 569 goto out; 570 } 571 572 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 573 MT7531_MDIO_DEV_ADDR(devad) | regnum; 574 ret = mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 575 if (ret < 0) 576 goto out; 577 578 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 579 !(val & MT7531_PHY_ACS_ST), 20, 100000); 580 if (ret < 0) { 581 dev_err(priv->dev, "poll timeout\n"); 582 goto out; 583 } 584 585 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 586 MT7531_MDIO_DEV_ADDR(devad); 587 ret = mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 588 if (ret < 0) 589 goto out; 590 591 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 592 !(val & MT7531_PHY_ACS_ST), 20, 100000); 593 if (ret < 0) { 594 dev_err(priv->dev, "poll timeout\n"); 595 goto out; 596 } 597 598 ret = val & MT7531_MDIO_RW_DATA_MASK; 599 out: 600 mt7530_mutex_unlock(priv); 601 602 return ret; 603 } 604 605 static int 606 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 607 int regnum, u16 data) 608 { 609 u32 val, reg; 610 int ret; 611 612 mt7530_mutex_lock(priv); 613 614 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 615 !(val & MT7531_PHY_ACS_ST), 20, 100000); 616 if (ret < 0) { 617 dev_err(priv->dev, "poll timeout\n"); 618 goto out; 619 } 620 621 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 622 MT7531_MDIO_DEV_ADDR(devad) | regnum; 623 ret = mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 624 if (ret < 0) 625 goto out; 626 627 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 628 !(val & MT7531_PHY_ACS_ST), 20, 100000); 629 if (ret < 0) { 630 dev_err(priv->dev, "poll timeout\n"); 631 goto out; 632 } 633 634 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 635 MT7531_MDIO_DEV_ADDR(devad) | data; 636 ret = mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 637 if (ret < 0) 638 goto out; 639 640 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 641 !(val & MT7531_PHY_ACS_ST), 20, 100000); 642 if (ret < 0) { 643 dev_err(priv->dev, "poll timeout\n"); 644 goto out; 645 } 646 647 out: 648 mt7530_mutex_unlock(priv); 649 650 return ret; 651 } 652 653 static int 654 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 655 { 656 int ret; 657 u32 val; 658 659 mt7530_mutex_lock(priv); 660 661 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 662 !(val & MT7531_PHY_ACS_ST), 20, 100000); 663 if (ret < 0) { 664 dev_err(priv->dev, "poll timeout\n"); 665 goto out; 666 } 667 668 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 669 MT7531_MDIO_REG_ADDR(regnum); 670 671 ret = mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 672 if (ret < 0) 673 goto out; 674 675 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, val, 676 !(val & MT7531_PHY_ACS_ST), 20, 100000); 677 if (ret < 0) { 678 dev_err(priv->dev, "poll timeout\n"); 679 goto out; 680 } 681 682 ret = val & MT7531_MDIO_RW_DATA_MASK; 683 out: 684 mt7530_mutex_unlock(priv); 685 686 return ret; 687 } 688 689 static int 690 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 691 u16 data) 692 { 693 int ret; 694 u32 reg; 695 696 mt7530_mutex_lock(priv); 697 698 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, reg, 699 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 700 if (ret < 0) { 701 dev_err(priv->dev, "poll timeout\n"); 702 goto out; 703 } 704 705 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 706 MT7531_MDIO_REG_ADDR(regnum) | data; 707 708 ret = mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 709 if (ret < 0) 710 goto out; 711 712 ret = regmap_read_poll_timeout(priv->regmap, MT7531_PHY_IAC, reg, 713 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 714 if (ret < 0) { 715 dev_err(priv->dev, "poll timeout\n"); 716 goto out; 717 } 718 719 out: 720 mt7530_mutex_unlock(priv); 721 722 return ret; 723 } 724 725 static int 726 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 727 { 728 struct mt7530_priv *priv = bus->priv; 729 730 return priv->info->phy_read_c22(priv, port, regnum); 731 } 732 733 static int 734 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 735 { 736 struct mt7530_priv *priv = bus->priv; 737 738 return priv->info->phy_read_c45(priv, port, devad, regnum); 739 } 740 741 static int 742 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 743 { 744 struct mt7530_priv *priv = bus->priv; 745 746 return priv->info->phy_write_c22(priv, port, regnum, val); 747 } 748 749 static int 750 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 751 u16 val) 752 { 753 struct mt7530_priv *priv = bus->priv; 754 755 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 756 } 757 758 static void 759 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 760 uint8_t *data) 761 { 762 int i; 763 764 if (stringset != ETH_SS_STATS) 765 return; 766 767 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 768 ethtool_puts(&data, mt7530_mib[i].name); 769 } 770 771 static void 772 mt7530_read_port_stats(struct mt7530_priv *priv, int port, 773 u32 offset, u8 size, uint64_t *data) 774 { 775 u32 val, reg = MT7530_PORT_MIB_COUNTER(port) + offset; 776 777 val = mt7530_read(priv, reg); 778 *data = val; 779 780 if (size == 2) { 781 val = mt7530_read(priv, reg + 4); 782 *data |= (u64)val << 32; 783 } 784 } 785 786 static void 787 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 788 uint64_t *data) 789 { 790 struct mt7530_priv *priv = ds->priv; 791 const struct mt7530_mib_desc *mib; 792 int i; 793 794 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 795 mib = &mt7530_mib[i]; 796 797 mt7530_read_port_stats(priv, port, mib->offset, mib->size, 798 data + i); 799 } 800 } 801 802 static int 803 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 804 { 805 if (sset != ETH_SS_STATS) 806 return 0; 807 808 return ARRAY_SIZE(mt7530_mib); 809 } 810 811 static void mt7530_get_eth_mac_stats(struct dsa_switch *ds, int port, 812 struct ethtool_eth_mac_stats *mac_stats) 813 { 814 struct mt7530_priv *priv = ds->priv; 815 816 /* MIB counter doesn't provide a FramesTransmittedOK but instead 817 * provide stats for Unicast, Broadcast and Multicast frames separately. 818 * To simulate a global frame counter, read Unicast and addition Multicast 819 * and Broadcast later 820 */ 821 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1, 822 &mac_stats->FramesTransmittedOK); 823 824 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_SINGLE_COLLISION, 1, 825 &mac_stats->SingleCollisionFrames); 826 827 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTIPLE_COLLISION, 1, 828 &mac_stats->MultipleCollisionFrames); 829 830 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1, 831 &mac_stats->FramesReceivedOK); 832 833 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2, 834 &mac_stats->OctetsTransmittedOK); 835 836 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_ALIGN_ERR, 1, 837 &mac_stats->AlignmentErrors); 838 839 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DEFERRED, 1, 840 &mac_stats->FramesWithDeferredXmissions); 841 842 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_LATE_COLLISION, 1, 843 &mac_stats->LateCollisions); 844 845 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION, 1, 846 &mac_stats->FramesAbortedDueToXSColls); 847 848 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2, 849 &mac_stats->OctetsReceivedOK); 850 851 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1, 852 &mac_stats->MulticastFramesXmittedOK); 853 mac_stats->FramesTransmittedOK += mac_stats->MulticastFramesXmittedOK; 854 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1, 855 &mac_stats->BroadcastFramesXmittedOK); 856 mac_stats->FramesTransmittedOK += mac_stats->BroadcastFramesXmittedOK; 857 858 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1, 859 &mac_stats->MulticastFramesReceivedOK); 860 mac_stats->FramesReceivedOK += mac_stats->MulticastFramesReceivedOK; 861 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1, 862 &mac_stats->BroadcastFramesReceivedOK); 863 mac_stats->FramesReceivedOK += mac_stats->BroadcastFramesReceivedOK; 864 } 865 866 static const struct ethtool_rmon_hist_range mt7530_rmon_ranges[] = { 867 { 0, 64 }, 868 { 65, 127 }, 869 { 128, 255 }, 870 { 256, 511 }, 871 { 512, 1023 }, 872 { 1024, MT7530_MAX_MTU }, 873 {} 874 }; 875 876 static void mt7530_get_rmon_stats(struct dsa_switch *ds, int port, 877 struct ethtool_rmon_stats *rmon_stats, 878 const struct ethtool_rmon_hist_range **ranges) 879 { 880 struct mt7530_priv *priv = ds->priv; 881 882 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNDER_SIZE_ERR, 1, 883 &rmon_stats->undersize_pkts); 884 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_OVER_SZ_ERR, 1, 885 &rmon_stats->oversize_pkts); 886 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_FRAG_ERR, 1, 887 &rmon_stats->fragments); 888 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_JABBER_ERR, 1, 889 &rmon_stats->jabbers); 890 891 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_64, 1, 892 &rmon_stats->hist[0]); 893 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127, 1, 894 &rmon_stats->hist[1]); 895 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255, 1, 896 &rmon_stats->hist[2]); 897 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511, 1, 898 &rmon_stats->hist[3]); 899 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023, 1, 900 &rmon_stats->hist[4]); 901 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX, 1, 902 &rmon_stats->hist[5]); 903 904 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_64, 1, 905 &rmon_stats->hist_tx[0]); 906 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127, 1, 907 &rmon_stats->hist_tx[1]); 908 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255, 1, 909 &rmon_stats->hist_tx[2]); 910 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511, 1, 911 &rmon_stats->hist_tx[3]); 912 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023, 1, 913 &rmon_stats->hist_tx[4]); 914 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX, 1, 915 &rmon_stats->hist_tx[5]); 916 917 *ranges = mt7530_rmon_ranges; 918 } 919 920 static void mt7530_read_port_stats64(struct mt7530_priv *priv, int port, 921 struct rtnl_link_stats64 *storage) 922 { 923 uint64_t data; 924 925 /* MIB counter doesn't provide a FramesTransmittedOK but instead 926 * provide stats for Unicast, Broadcast and Multicast frames separately. 927 * To simulate a global frame counter, read Unicast and addition Multicast 928 * and Broadcast later 929 */ 930 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1, 931 &storage->rx_packets); 932 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1, 933 &storage->multicast); 934 storage->rx_packets += storage->multicast; 935 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1, 936 &data); 937 storage->rx_packets += data; 938 939 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1, 940 &storage->tx_packets); 941 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1, 942 &data); 943 storage->tx_packets += data; 944 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1, 945 &data); 946 storage->tx_packets += data; 947 948 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2, 949 &storage->rx_bytes); 950 951 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2, 952 &storage->tx_bytes); 953 954 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_DROP, 1, 955 &storage->rx_dropped); 956 957 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DROP, 1, 958 &storage->tx_dropped); 959 960 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_CRC_ERR, 1, 961 &storage->rx_crc_errors); 962 } 963 964 static void mt7530_stats_refresh(struct mt7530_priv *priv) 965 { 966 struct rtnl_link_stats64 stats = {}; 967 struct dsa_port *dp; 968 int port; 969 970 dsa_switch_for_each_user_port(dp, priv->ds) { 971 port = dp->index; 972 973 mt7530_read_port_stats64(priv, port, &stats); 974 975 spin_lock_bh(&priv->stats_lock); 976 priv->ports[port].stats = stats; 977 priv->stats_last = jiffies; 978 spin_unlock_bh(&priv->stats_lock); 979 } 980 } 981 982 static void mt7530_stats_poll(struct work_struct *work) 983 { 984 struct mt7530_priv *priv = container_of(work, struct mt7530_priv, 985 stats_work.work); 986 987 mt7530_stats_refresh(priv); 988 schedule_delayed_work(&priv->stats_work, 989 MT7530_STATS_POLL_INTERVAL); 990 } 991 992 static void mt7530_get_stats64(struct dsa_switch *ds, int port, 993 struct rtnl_link_stats64 *storage) 994 { 995 struct mt7530_priv *priv = ds->priv; 996 bool refresh; 997 998 if (priv->bus) { 999 spin_lock_bh(&priv->stats_lock); 1000 *storage = priv->ports[port].stats; 1001 refresh = time_after(jiffies, priv->stats_last + 1002 MT7530_STATS_RATE_LIMIT); 1003 spin_unlock_bh(&priv->stats_lock); 1004 if (refresh) 1005 mod_delayed_work(system_percpu_wq, 1006 &priv->stats_work, 0); 1007 } else { 1008 mt7530_read_port_stats64(priv, port, storage); 1009 } 1010 } 1011 1012 static void mt7530_get_eth_ctrl_stats(struct dsa_switch *ds, int port, 1013 struct ethtool_eth_ctrl_stats *ctrl_stats) 1014 { 1015 struct mt7530_priv *priv = ds->priv; 1016 1017 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PAUSE, 1, 1018 &ctrl_stats->MACControlFramesTransmitted); 1019 1020 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PAUSE, 1, 1021 &ctrl_stats->MACControlFramesReceived); 1022 } 1023 1024 static int 1025 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 1026 { 1027 struct mt7530_priv *priv = ds->priv; 1028 unsigned int secs = msecs / 1000; 1029 unsigned int tmp_age_count; 1030 unsigned int error = -1; 1031 unsigned int age_count; 1032 unsigned int age_unit; 1033 1034 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds. 1035 * The DSA core has already validated the range using 1036 * ds->ageing_time_min and ds->ageing_time_max. 1037 * 1038 * Iterate through all possible age_count values to find the closest 1039 * pair. Start from 1 because the per-entry aging counter is 1040 * initialized to AGE_CNT and a value of 0 means the entry will 1041 * never be aged out. 1042 */ 1043 for (tmp_age_count = 1; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 1044 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 1045 1046 if (tmp_age_unit <= AGE_UNIT_MAX) { 1047 unsigned int tmp_error = secs - 1048 (tmp_age_count + 1) * (tmp_age_unit + 1); 1049 1050 /* found a closer pair */ 1051 if (error > tmp_error) { 1052 error = tmp_error; 1053 age_count = tmp_age_count; 1054 age_unit = tmp_age_unit; 1055 } 1056 1057 /* found the exact match, so break the loop */ 1058 if (!error) 1059 break; 1060 } 1061 } 1062 1063 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 1064 1065 return 0; 1066 } 1067 1068 static const char *mt7530_p5_mode_str(unsigned int mode) 1069 { 1070 switch (mode) { 1071 case MUX_PHY_P0: 1072 return "MUX PHY P0"; 1073 case MUX_PHY_P4: 1074 return "MUX PHY P4"; 1075 default: 1076 return "GMAC5"; 1077 } 1078 } 1079 1080 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 1081 { 1082 struct mt7530_priv *priv = ds->priv; 1083 u8 tx_delay = 0; 1084 int val; 1085 1086 mutex_lock(&priv->reg_mutex); 1087 1088 val = mt7530_read(priv, MT753X_MTRAP); 1089 1090 val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE; 1091 1092 switch (priv->p5_mode) { 1093 /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ 1094 case MUX_PHY_P0: 1095 val |= MT7530_P5_PHY0_SEL; 1096 fallthrough; 1097 1098 /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ 1099 case MUX_PHY_P4: 1100 /* Setup the MAC by default for the cpu port */ 1101 mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); 1102 break; 1103 1104 /* GMAC5: P5 -> SoC MAC or external PHY */ 1105 default: 1106 val |= MT7530_P5_MAC_SEL; 1107 break; 1108 } 1109 1110 /* Setup RGMII settings */ 1111 if (phy_interface_mode_is_rgmii(interface)) { 1112 val |= MT7530_P5_RGMII_MODE; 1113 1114 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 1115 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 1116 1117 /* Don't set delay in DSA mode */ 1118 if (!dsa_is_dsa_port(priv->ds, 5) && 1119 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 1120 interface == PHY_INTERFACE_MODE_RGMII_ID)) 1121 tx_delay = 4; /* n * 0.5 ns */ 1122 1123 /* P5 RGMII TX Clock Control: delay x */ 1124 mt7530_write(priv, MT7530_P5RGMIITXCR, 1125 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 1126 1127 /* reduce P5 RGMII Tx driving, 8mA */ 1128 mt7530_write(priv, MT7530_IO_DRV_CR, 1129 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 1130 } 1131 1132 mt7530_write(priv, MT753X_MTRAP, val); 1133 1134 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, 1135 mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); 1136 1137 mutex_unlock(&priv->reg_mutex); 1138 } 1139 1140 /* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL) 1141 * of the Open Systems Interconnection basic reference model (OSI/RM) are 1142 * described; the medium access control (MAC) and logical link control (LLC) 1143 * sublayers. The MAC sublayer is the one facing the physical layer. 1144 * 1145 * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A 1146 * Bridge component comprises a MAC Relay Entity for interconnecting the Ports 1147 * of the Bridge, at least two Ports, and higher layer entities with at least a 1148 * Spanning Tree Protocol Entity included. 1149 * 1150 * Each Bridge Port also functions as an end station and shall provide the MAC 1151 * Service to an LLC Entity. Each instance of the MAC Service is provided to a 1152 * distinct LLC Entity that supports protocol identification, multiplexing, and 1153 * demultiplexing, for protocol data unit (PDU) transmission and reception by 1154 * one or more higher layer entities. 1155 * 1156 * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC 1157 * Entity associated with each Bridge Port is modeled as being directly 1158 * connected to the attached Local Area Network (LAN). 1159 * 1160 * On the switch with CPU port architecture, CPU port functions as Management 1161 * Port, and the Management Port functionality is provided by software which 1162 * functions as an end station. Software is connected to an IEEE 802 LAN that is 1163 * wholly contained within the system that incorporates the Bridge. Software 1164 * provides access to the LLC Entity associated with each Bridge Port by the 1165 * value of the source port field on the special tag on the frame received by 1166 * software. 1167 * 1168 * We call frames that carry control information to determine the active 1169 * topology and current extent of each Virtual Local Area Network (VLAN), i.e., 1170 * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration 1171 * Protocol Data Units (MVRPDUs), and frames from other link constrained 1172 * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and 1173 * Link Layer Discovery Protocol (LLDP), link-local frames. They are not 1174 * forwarded by a Bridge. Permanently configured entries in the filtering 1175 * database (FDB) ensure that such frames are discarded by the Forwarding 1176 * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail: 1177 * 1178 * Each of the reserved MAC addresses specified in Table 8-1 1179 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be 1180 * permanently configured in the FDB in C-VLAN components and ERs. 1181 * 1182 * Each of the reserved MAC addresses specified in Table 8-2 1183 * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently 1184 * configured in the FDB in S-VLAN components. 1185 * 1186 * Each of the reserved MAC addresses specified in Table 8-3 1187 * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in 1188 * TPMR components. 1189 * 1190 * The FDB entries for reserved MAC addresses shall specify filtering for all 1191 * Bridge Ports and all VIDs. Management shall not provide the capability to 1192 * modify or remove entries for reserved MAC addresses. 1193 * 1194 * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of 1195 * propagation of PDUs within a Bridged Network, as follows: 1196 * 1197 * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no 1198 * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN) 1199 * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward. 1200 * PDUs transmitted using this destination address, or any other addresses 1201 * that appear in Table 8-1, Table 8-2, and Table 8-3 1202 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can 1203 * therefore travel no further than those stations that can be reached via a 1204 * single individual LAN from the originating station. 1205 * 1206 * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an 1207 * address that no conformant S-VLAN component, C-VLAN component, or MAC 1208 * Bridge can forward; however, this address is relayed by a TPMR component. 1209 * PDUs using this destination address, or any of the other addresses that 1210 * appear in both Table 8-1 and Table 8-2 but not in Table 8-3 1211 * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by 1212 * any TPMRs but will propagate no further than the nearest S-VLAN component, 1213 * C-VLAN component, or MAC Bridge. 1214 * 1215 * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address 1216 * that no conformant C-VLAN component, MAC Bridge can forward; however, it is 1217 * relayed by TPMR components and S-VLAN components. PDUs using this 1218 * destination address, or any of the other addresses that appear in Table 8-1 1219 * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]), 1220 * will be relayed by TPMR components and S-VLAN components but will propagate 1221 * no further than the nearest C-VLAN component or MAC Bridge. 1222 * 1223 * Because the LLC Entity associated with each Bridge Port is provided via CPU 1224 * port, we must not filter these frames but forward them to CPU port. 1225 * 1226 * In a Bridge, the transmission Port is majorly decided by ingress and egress 1227 * rules, FDB, and spanning tree Port State functions of the Forwarding Process. 1228 * For link-local frames, only CPU port should be designated as destination port 1229 * in the FDB, and the other functions of the Forwarding Process must not 1230 * interfere with the decision of the transmission Port. We call this process 1231 * trapping frames to CPU port. 1232 * 1233 * Therefore, on the switch with CPU port architecture, link-local frames must 1234 * be trapped to CPU port, and certain link-local frames received by a Port of a 1235 * Bridge comprising a TPMR component or an S-VLAN component must be excluded 1236 * from it. 1237 * 1238 * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port 1239 * MAC Relay (TPMR) component as a TPMR component supports only a subset of the 1240 * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port 1241 * doesn't count) of this architecture will either function as a standard MAC 1242 * Bridge or a standard VLAN Bridge. 1243 * 1244 * Therefore, a Bridge of this architecture can only comprise S-VLAN components, 1245 * C-VLAN components, or MAC Bridge components. Since there's no TPMR component, 1246 * we don't need to relay PDUs using the destination addresses specified on the 1247 * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge 1248 * section where they must be relayed by TPMR components. 1249 * 1250 * One option to trap link-local frames to CPU port is to add static FDB entries 1251 * with CPU port designated as destination port. However, because that 1252 * Independent VLAN Learning (IVL) is being used on every VID, each entry only 1253 * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC 1254 * Bridge component or a C-VLAN component, there would have to be 16 times 4096 1255 * entries. This switch intellectual property can only hold a maximum of 2048 1256 * entries. Using this option, there also isn't a mechanism to prevent 1257 * link-local frames from being discarded when the spanning tree Port State of 1258 * the reception Port is discarding. 1259 * 1260 * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4 1261 * registers. Whilst this applies to every VID, it doesn't contain all of the 1262 * reserved MAC addresses without affecting the remaining Standard Group MAC 1263 * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the 1264 * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination 1265 * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF 1266 * destination addresses which may be relayed by MAC Bridges or VLAN Bridges. 1267 * The latter option provides better but not complete conformance. 1268 * 1269 * This switch intellectual property also does not provide a mechanism to trap 1270 * link-local frames with specific destination addresses to CPU port by Bridge, 1271 * to conform to the filtering rules for the distinct Bridge components. 1272 * 1273 * Therefore, regardless of the type of the Bridge component, link-local frames 1274 * with these destination addresses will be trapped to CPU port: 1275 * 1276 * 01-80-C2-00-00-[00,01,02,03,0E] 1277 * 1278 * In a Bridge comprising a MAC Bridge component or a C-VLAN component: 1279 * 1280 * Link-local frames with these destination addresses won't be trapped to CPU 1281 * port which won't conform to IEEE Std 802.1Q-2022: 1282 * 1283 * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] 1284 * 1285 * In a Bridge comprising an S-VLAN component: 1286 * 1287 * Link-local frames with these destination addresses will be trapped to CPU 1288 * port which won't conform to IEEE Std 802.1Q-2022: 1289 * 1290 * 01-80-C2-00-00-00 1291 * 1292 * Link-local frames with these destination addresses won't be trapped to CPU 1293 * port which won't conform to IEEE Std 802.1Q-2022: 1294 * 1295 * 01-80-C2-00-00-[04,05,06,07,08,09,0A] 1296 * 1297 * To trap link-local frames to CPU port as conformant as this switch 1298 * intellectual property can allow, link-local frames are made to be regarded as 1299 * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual 1300 * property only lets the frames regarded as BPDUs bypass the spanning tree Port 1301 * State function of the Forwarding Process. 1302 * 1303 * The only remaining interference is the ingress rules. When the reception Port 1304 * has no PVID assigned on software, VLAN-untagged frames won't be allowed in. 1305 * There doesn't seem to be a mechanism on the switch intellectual property to 1306 * have link-local frames bypass this function of the Forwarding Process. 1307 */ 1308 static void 1309 mt753x_trap_frames(struct mt7530_priv *priv) 1310 { 1311 /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress 1312 * them with the EG_TAG attribute set to disabled (system default) 1313 * so that any VLAN tags in the frame are not modified by the 1314 * switch egress VLAN tag processing. This preserves VLAN tags 1315 * for reception on VLAN sub-interfaces. 1316 */ 1317 mt7530_rmw(priv, MT753X_BPC, 1318 PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK | 1319 BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK, 1320 PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1321 PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) | 1322 BPDU_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1323 TO_CPU_FW_CPU_ONLY); 1324 1325 /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and 1326 * egress them with EG_TAG disabled. 1327 */ 1328 mt7530_rmw(priv, MT753X_RGAC1, 1329 R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK | 1330 R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK, 1331 R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1332 R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR | 1333 R01_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1334 TO_CPU_FW_CPU_ONLY); 1335 1336 /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and 1337 * egress them with EG_TAG disabled. 1338 */ 1339 mt7530_rmw(priv, MT753X_RGAC2, 1340 R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK | 1341 R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK, 1342 R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1343 R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR | 1344 R03_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1345 TO_CPU_FW_CPU_ONLY); 1346 } 1347 1348 static void 1349 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1350 { 1351 struct mt7530_priv *priv = ds->priv; 1352 1353 /* Enable Mediatek header mode on the cpu port */ 1354 mt7530_write(priv, MT7530_PVC_P(port), 1355 PORT_SPEC_TAG); 1356 1357 /* Enable flooding on the CPU port */ 1358 mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | 1359 UNU_FFP(BIT(port))); 1360 1361 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on 1362 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that 1363 * is affine to the inbound user port. 1364 */ 1365 if (priv->id == ID_MT7531 || priv->id == ID_MT7988 || 1366 priv->id == ID_EN7581 || priv->id == ID_AN7583) 1367 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); 1368 1369 /* CPU port gets connected to all user ports of 1370 * the switch. 1371 */ 1372 mt7530_write(priv, MT7530_PCR_P(port), 1373 PCR_MATRIX(dsa_user_ports(priv->ds))); 1374 1375 /* Set to fallback mode for independent VLAN learning */ 1376 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1377 MT7530_PORT_FALLBACK_MODE); 1378 } 1379 1380 static int 1381 mt7530_port_enable(struct dsa_switch *ds, int port, 1382 struct phy_device *phy) 1383 { 1384 struct dsa_port *dp = dsa_to_port(ds, port); 1385 struct mt7530_priv *priv = ds->priv; 1386 1387 mutex_lock(&priv->reg_mutex); 1388 1389 /* Allow the user port gets connected to the cpu port and also 1390 * restore the port matrix if the port is the member of a certain 1391 * bridge. 1392 */ 1393 if (dsa_port_is_user(dp)) { 1394 struct dsa_port *cpu_dp = dp->cpu_dp; 1395 1396 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1397 } 1398 priv->ports[port].enable = true; 1399 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1400 priv->ports[port].pm); 1401 1402 mutex_unlock(&priv->reg_mutex); 1403 1404 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 1405 return 0; 1406 1407 if (port == 5) 1408 mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); 1409 else if (port == 6) 1410 mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS); 1411 1412 return 0; 1413 } 1414 1415 static void 1416 mt7530_port_disable(struct dsa_switch *ds, int port) 1417 { 1418 struct mt7530_priv *priv = ds->priv; 1419 1420 mutex_lock(&priv->reg_mutex); 1421 1422 /* Clear up all port matrix which could be restored in the next 1423 * enablement for the port. 1424 */ 1425 priv->ports[port].enable = false; 1426 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1427 PCR_MATRIX_CLR); 1428 1429 mutex_unlock(&priv->reg_mutex); 1430 1431 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 1432 return; 1433 1434 /* Do not set MT7530_P5_DIS when port 5 is being used for PHY muxing. */ 1435 if (port == 5 && priv->p5_mode == GMAC5) 1436 mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS); 1437 else if (port == 6) 1438 mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS); 1439 } 1440 1441 static int 1442 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1443 { 1444 struct mt7530_priv *priv = ds->priv; 1445 int length; 1446 u32 val; 1447 1448 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1449 * largest MTU of the user ports. Because the switch only has a global 1450 * RX length register, only allowing CPU port here is enough. 1451 */ 1452 if (!dsa_is_cpu_port(ds, port)) 1453 return 0; 1454 1455 mt7530_mutex_lock(priv); 1456 1457 val = mt7530_mii_read(priv, MT7530_GMACCR); 1458 val &= ~MAX_RX_PKT_LEN_MASK; 1459 1460 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1461 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1462 if (length <= 1522) { 1463 val |= MAX_RX_PKT_LEN_1522; 1464 } else if (length <= 1536) { 1465 val |= MAX_RX_PKT_LEN_1536; 1466 } else if (length <= 1552) { 1467 val |= MAX_RX_PKT_LEN_1552; 1468 } else { 1469 val &= ~MAX_RX_JUMBO_MASK; 1470 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1471 val |= MAX_RX_PKT_LEN_JUMBO; 1472 } 1473 1474 mt7530_mii_write(priv, MT7530_GMACCR, val); 1475 1476 mt7530_mutex_unlock(priv); 1477 1478 return 0; 1479 } 1480 1481 static int 1482 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1483 { 1484 return MT7530_MAX_MTU; 1485 } 1486 1487 static void 1488 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1489 { 1490 struct mt7530_priv *priv = ds->priv; 1491 u32 stp_state; 1492 1493 switch (state) { 1494 case BR_STATE_DISABLED: 1495 stp_state = MT7530_STP_DISABLED; 1496 break; 1497 case BR_STATE_BLOCKING: 1498 stp_state = MT7530_STP_BLOCKING; 1499 break; 1500 case BR_STATE_LISTENING: 1501 stp_state = MT7530_STP_LISTENING; 1502 break; 1503 case BR_STATE_LEARNING: 1504 stp_state = MT7530_STP_LEARNING; 1505 break; 1506 case BR_STATE_FORWARDING: 1507 default: 1508 stp_state = MT7530_STP_FORWARDING; 1509 break; 1510 } 1511 1512 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1513 FID_PST(FID_BRIDGED, stp_state)); 1514 } 1515 1516 static void mt7530_update_port_member(struct mt7530_priv *priv, int port, 1517 const struct net_device *bridge_dev, 1518 bool join) __must_hold(&priv->reg_mutex) 1519 { 1520 struct dsa_port *dp = dsa_to_port(priv->ds, port), *other_dp; 1521 struct mt7530_port *p = &priv->ports[port], *other_p; 1522 struct dsa_port *cpu_dp = dp->cpu_dp; 1523 u32 port_bitmap = BIT(cpu_dp->index); 1524 int other_port; 1525 bool isolated; 1526 1527 dsa_switch_for_each_user_port(other_dp, priv->ds) { 1528 other_port = other_dp->index; 1529 other_p = &priv->ports[other_port]; 1530 1531 if (dp == other_dp) 1532 continue; 1533 1534 /* Add/remove this port to/from the port matrix of the other 1535 * ports in the same bridge. If the port is disabled, port 1536 * matrix is kept and not being setup until the port becomes 1537 * enabled. 1538 */ 1539 if (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev)) 1540 continue; 1541 1542 isolated = p->isolated && other_p->isolated; 1543 1544 if (join && !isolated) { 1545 other_p->pm |= PCR_MATRIX(BIT(port)); 1546 port_bitmap |= BIT(other_port); 1547 } else { 1548 other_p->pm &= ~PCR_MATRIX(BIT(port)); 1549 } 1550 1551 if (other_p->enable) 1552 mt7530_rmw(priv, MT7530_PCR_P(other_port), 1553 PCR_MATRIX_MASK, other_p->pm); 1554 } 1555 1556 /* Add/remove the all other ports to this port matrix. For !join 1557 * (leaving the bridge), only the CPU port will remain in the port matrix 1558 * of this port. 1559 */ 1560 p->pm = PCR_MATRIX(port_bitmap); 1561 if (priv->ports[port].enable) 1562 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, p->pm); 1563 } 1564 1565 static int 1566 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1567 struct switchdev_brport_flags flags, 1568 struct netlink_ext_ack *extack) 1569 { 1570 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1571 BR_BCAST_FLOOD | BR_ISOLATED)) 1572 return -EINVAL; 1573 1574 return 0; 1575 } 1576 1577 static int 1578 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1579 struct switchdev_brport_flags flags, 1580 struct netlink_ext_ack *extack) 1581 { 1582 struct mt7530_priv *priv = ds->priv; 1583 1584 if (flags.mask & BR_LEARNING) 1585 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1586 flags.val & BR_LEARNING ? 0 : SA_DIS); 1587 1588 if (flags.mask & BR_FLOOD) 1589 mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)), 1590 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1591 1592 if (flags.mask & BR_MCAST_FLOOD) 1593 mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)), 1594 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1595 1596 if (flags.mask & BR_BCAST_FLOOD) 1597 mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)), 1598 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1599 1600 if (flags.mask & BR_ISOLATED) { 1601 struct dsa_port *dp = dsa_to_port(ds, port); 1602 struct net_device *bridge_dev = dsa_port_bridge_dev_get(dp); 1603 1604 priv->ports[port].isolated = !!(flags.val & BR_ISOLATED); 1605 1606 mutex_lock(&priv->reg_mutex); 1607 mt7530_update_port_member(priv, port, bridge_dev, true); 1608 mutex_unlock(&priv->reg_mutex); 1609 } 1610 1611 return 0; 1612 } 1613 1614 static int 1615 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1616 struct dsa_bridge bridge, bool *tx_fwd_offload, 1617 struct netlink_ext_ack *extack) 1618 { 1619 struct mt7530_priv *priv = ds->priv; 1620 1621 mutex_lock(&priv->reg_mutex); 1622 1623 mt7530_update_port_member(priv, port, bridge.dev, true); 1624 1625 /* Set to fallback mode for independent VLAN learning */ 1626 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1627 MT7530_PORT_FALLBACK_MODE); 1628 1629 mutex_unlock(&priv->reg_mutex); 1630 1631 return 0; 1632 } 1633 1634 static int 1635 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1636 { 1637 u32 val; 1638 int ret; 1639 1640 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1641 ret = mt7530_write(priv, MT7530_VTCR, val); 1642 if (ret) 1643 return ret; 1644 1645 mt7530_mutex_lock(priv); 1646 1647 ret = regmap_read_poll_timeout(priv->regmap, MT7530_VTCR, val, 1648 !(val & VTCR_BUSY), 20, 20000); 1649 if (!ret) 1650 ret = regmap_read(priv->regmap, MT7530_VTCR, &val); 1651 1652 mt7530_mutex_unlock(priv); 1653 1654 if (ret < 0) { 1655 dev_err(priv->dev, "poll timeout\n"); 1656 return ret; 1657 } 1658 1659 if (val & VTCR_INVALID) { 1660 dev_err(priv->dev, "read VTCR invalid\n"); 1661 return -EINVAL; 1662 } 1663 1664 return 0; 1665 } 1666 1667 static int 1668 mt7530_setup_vlan0(struct mt7530_priv *priv) 1669 { 1670 u32 val; 1671 1672 /* Validate the entry with independent learning, keep the original 1673 * ingress tag attribute. 1674 */ 1675 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1676 VLAN_VALID; 1677 mt7530_write(priv, MT7530_VAWD1, val); 1678 mt7530_write(priv, MT7530_VAWD2, 0); 1679 1680 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1681 } 1682 1683 static void 1684 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1685 { 1686 struct mt7530_priv *priv = ds->priv; 1687 bool all_user_ports_removed = true; 1688 int i; 1689 1690 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1691 * bridge. Don't set standalone ports to fallback mode. 1692 */ 1693 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1694 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1695 MT7530_PORT_FALLBACK_MODE); 1696 1697 mt7530_rmw(priv, MT7530_PVC_P(port), 1698 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1699 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1700 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1701 MT7530_VLAN_ACC_ALL); 1702 1703 /* Set PVID to 0 */ 1704 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1705 G0_PORT_VID_DEF); 1706 1707 for (i = 0; i < priv->ds->num_ports; i++) { 1708 if (i == port) 1709 continue; 1710 if (dsa_is_user_port(ds, i) && 1711 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1712 all_user_ports_removed = false; 1713 break; 1714 } 1715 } 1716 1717 /* CPU port also does the same thing until all user ports belonging to 1718 * the CPU port get out of VLAN filtering mode. 1719 */ 1720 if (all_user_ports_removed) { 1721 mutex_lock(&priv->reg_mutex); 1722 mt7530_setup_vlan0(priv); 1723 mutex_unlock(&priv->reg_mutex); 1724 } 1725 } 1726 1727 static void 1728 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1729 { 1730 struct mt7530_priv *priv = ds->priv; 1731 1732 /* Trapped into security mode allows packet forwarding through VLAN 1733 * table lookup. 1734 */ 1735 if (dsa_is_user_port(ds, port)) { 1736 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1737 MT7530_PORT_SECURITY_MODE); 1738 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1739 G0_PORT_VID(priv->ports[port].pvid)); 1740 1741 /* Only accept tagged frames if PVID is not set */ 1742 if (!priv->ports[port].pvid) 1743 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1744 MT7530_VLAN_ACC_TAGGED); 1745 1746 /* Set the port as a user port which is to be able to recognize 1747 * VID from incoming packets before fetching entry within the 1748 * VLAN table. 1749 */ 1750 mt7530_rmw(priv, MT7530_PVC_P(port), 1751 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1752 VLAN_ATTR(MT7530_VLAN_USER) | 1753 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1754 } else { 1755 /* Also set CPU ports to the "user" VLAN port attribute, to 1756 * allow VLAN classification, but keep the EG_TAG attribute as 1757 * "consistent" (i.o.w. don't change its value) for packets 1758 * received by the switch from the CPU, so that tagged packets 1759 * are forwarded to user ports as tagged, and untagged as 1760 * untagged. 1761 */ 1762 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1763 VLAN_ATTR(MT7530_VLAN_USER)); 1764 } 1765 } 1766 1767 static void 1768 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1769 struct dsa_bridge bridge) 1770 { 1771 struct mt7530_priv *priv = ds->priv; 1772 1773 mutex_lock(&priv->reg_mutex); 1774 1775 mt7530_update_port_member(priv, port, bridge.dev, false); 1776 1777 /* When a port is removed from the bridge, the port would be set up 1778 * back to the default as is at initial boot which is a VLAN-unaware 1779 * port. 1780 */ 1781 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1782 MT7530_PORT_MATRIX_MODE); 1783 1784 mutex_unlock(&priv->reg_mutex); 1785 } 1786 1787 static int 1788 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1789 const unsigned char *addr, u16 vid, 1790 struct dsa_db db) 1791 { 1792 struct mt7530_priv *priv = ds->priv; 1793 int ret; 1794 u8 port_mask = BIT(port); 1795 1796 mutex_lock(&priv->reg_mutex); 1797 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1798 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1799 mutex_unlock(&priv->reg_mutex); 1800 1801 return ret; 1802 } 1803 1804 static int 1805 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1806 const unsigned char *addr, u16 vid, 1807 struct dsa_db db) 1808 { 1809 struct mt7530_priv *priv = ds->priv; 1810 int ret; 1811 u8 port_mask = BIT(port); 1812 1813 mutex_lock(&priv->reg_mutex); 1814 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1815 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1816 mutex_unlock(&priv->reg_mutex); 1817 1818 return ret; 1819 } 1820 1821 static int 1822 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1823 dsa_fdb_dump_cb_t *cb, void *data) 1824 { 1825 struct mt7530_priv *priv = ds->priv; 1826 struct mt7530_fdb _fdb = { 0 }; 1827 int cnt = MT7530_NUM_FDB_RECORDS; 1828 int ret = 0; 1829 u32 rsp = 0; 1830 1831 mutex_lock(&priv->reg_mutex); 1832 1833 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1834 if (ret < 0) 1835 goto err; 1836 1837 do { 1838 if (rsp & ATC_SRCH_HIT) { 1839 mt7530_fdb_read(priv, &_fdb); 1840 if (_fdb.port_mask & BIT(port)) { 1841 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1842 data); 1843 if (ret < 0) 1844 break; 1845 } 1846 } 1847 } while (--cnt && 1848 !(rsp & ATC_SRCH_END) && 1849 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1850 err: 1851 mutex_unlock(&priv->reg_mutex); 1852 1853 return 0; 1854 } 1855 1856 static int 1857 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1858 const struct switchdev_obj_port_mdb *mdb, 1859 struct dsa_db db) 1860 { 1861 struct mt7530_priv *priv = ds->priv; 1862 const u8 *addr = mdb->addr; 1863 u16 vid = mdb->vid; 1864 u8 port_mask = 0; 1865 int ret; 1866 1867 mutex_lock(&priv->reg_mutex); 1868 1869 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1870 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1871 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1872 & PORT_MAP_MASK; 1873 1874 port_mask |= BIT(port); 1875 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1876 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1877 1878 mutex_unlock(&priv->reg_mutex); 1879 1880 return ret; 1881 } 1882 1883 static int 1884 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1885 const struct switchdev_obj_port_mdb *mdb, 1886 struct dsa_db db) 1887 { 1888 struct mt7530_priv *priv = ds->priv; 1889 const u8 *addr = mdb->addr; 1890 u16 vid = mdb->vid; 1891 u8 port_mask = 0; 1892 int ret; 1893 1894 mutex_lock(&priv->reg_mutex); 1895 1896 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1897 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1898 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1899 & PORT_MAP_MASK; 1900 1901 port_mask &= ~BIT(port); 1902 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1903 port_mask ? STATIC_ENT : STATIC_EMP); 1904 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1905 1906 mutex_unlock(&priv->reg_mutex); 1907 1908 return ret; 1909 } 1910 1911 static int 1912 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1913 struct netlink_ext_ack *extack) 1914 { 1915 struct dsa_port *dp = dsa_to_port(ds, port); 1916 struct dsa_port *cpu_dp = dp->cpu_dp; 1917 1918 if (vlan_filtering) { 1919 /* The port is being kept as VLAN-unaware port when bridge is 1920 * set up with vlan_filtering not being set, Otherwise, the 1921 * port and the corresponding CPU port is required the setup 1922 * for becoming a VLAN-aware port. 1923 */ 1924 mt7530_port_set_vlan_aware(ds, port); 1925 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1926 } else { 1927 mt7530_port_set_vlan_unaware(ds, port); 1928 } 1929 1930 return 0; 1931 } 1932 1933 static void 1934 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1935 struct mt7530_hw_vlan_entry *entry) 1936 { 1937 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1938 u8 new_members; 1939 u32 val; 1940 1941 new_members = entry->old_members | BIT(entry->port); 1942 1943 /* Validate the entry with independent learning, create egress tag per 1944 * VLAN and joining the port as one of the port members. 1945 */ 1946 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1947 VLAN_VALID; 1948 mt7530_write(priv, MT7530_VAWD1, val); 1949 1950 /* Decide whether adding tag or not for those outgoing packets from the 1951 * port inside the VLAN. 1952 * CPU port is always taken as a tagged port for serving more than one 1953 * VLANs across and also being applied with egress type stack mode for 1954 * that VLAN tags would be appended after hardware special tag used as 1955 * DSA tag. 1956 */ 1957 if (dsa_port_is_cpu(dp)) 1958 val = MT7530_VLAN_EGRESS_STACK; 1959 else if (entry->untagged) 1960 val = MT7530_VLAN_EGRESS_UNTAG; 1961 else 1962 val = MT7530_VLAN_EGRESS_TAG; 1963 mt7530_rmw(priv, MT7530_VAWD2, 1964 ETAG_CTRL_P_MASK(entry->port), 1965 ETAG_CTRL_P(entry->port, val)); 1966 } 1967 1968 static void 1969 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1970 struct mt7530_hw_vlan_entry *entry) 1971 { 1972 u8 new_members; 1973 u32 val; 1974 1975 new_members = entry->old_members & ~BIT(entry->port); 1976 1977 val = mt7530_read(priv, MT7530_VAWD1); 1978 if (!(val & VLAN_VALID)) { 1979 dev_err(priv->dev, 1980 "Cannot be deleted due to invalid entry\n"); 1981 return; 1982 } 1983 1984 if (new_members) { 1985 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1986 VLAN_VALID; 1987 mt7530_write(priv, MT7530_VAWD1, val); 1988 } else { 1989 mt7530_write(priv, MT7530_VAWD1, 0); 1990 mt7530_write(priv, MT7530_VAWD2, 0); 1991 } 1992 } 1993 1994 static void 1995 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1996 struct mt7530_hw_vlan_entry *entry, 1997 mt7530_vlan_op vlan_op) 1998 { 1999 u32 val; 2000 2001 /* Fetch entry */ 2002 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 2003 2004 val = mt7530_read(priv, MT7530_VAWD1); 2005 2006 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 2007 2008 /* Manipulate entry */ 2009 vlan_op(priv, entry); 2010 2011 /* Flush result to hardware */ 2012 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 2013 } 2014 2015 static int 2016 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 2017 const struct switchdev_obj_port_vlan *vlan, 2018 struct netlink_ext_ack *extack) 2019 { 2020 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2021 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2022 struct mt7530_hw_vlan_entry new_entry; 2023 struct mt7530_priv *priv = ds->priv; 2024 2025 mutex_lock(&priv->reg_mutex); 2026 2027 /* VID 0 is managed exclusively by mt7530_setup_vlan0() for 2028 * VLAN-unaware bridge operation. Don't let the bridge overwrite 2029 * its EG_CON flag with VTAG_EN and corrupt PORT_MEM. 2030 */ 2031 if (vlan->vid == 0) 2032 goto skip_vlan_table; 2033 2034 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 2035 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 2036 2037 skip_vlan_table: 2038 2039 if (pvid) { 2040 priv->ports[port].pvid = vlan->vid; 2041 2042 /* Accept all frames if PVID is set */ 2043 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 2044 MT7530_VLAN_ACC_ALL); 2045 2046 /* Only configure PVID if VLAN filtering is enabled */ 2047 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 2048 mt7530_rmw(priv, MT7530_PPBV1_P(port), 2049 G0_PORT_VID_MASK, 2050 G0_PORT_VID(vlan->vid)); 2051 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 2052 /* This VLAN is overwritten without PVID, so unset it */ 2053 priv->ports[port].pvid = G0_PORT_VID_DEF; 2054 2055 /* Only accept tagged frames if the port is VLAN-aware */ 2056 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 2057 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 2058 MT7530_VLAN_ACC_TAGGED); 2059 2060 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 2061 G0_PORT_VID_DEF); 2062 } 2063 2064 mutex_unlock(&priv->reg_mutex); 2065 2066 return 0; 2067 } 2068 2069 static int 2070 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 2071 const struct switchdev_obj_port_vlan *vlan) 2072 { 2073 struct mt7530_hw_vlan_entry target_entry; 2074 struct mt7530_priv *priv = ds->priv; 2075 2076 mutex_lock(&priv->reg_mutex); 2077 2078 /* VID 0 is managed exclusively by mt7530_setup_vlan0(). */ 2079 if (vlan->vid == 0) 2080 goto skip_vlan_table; 2081 2082 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 2083 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 2084 mt7530_hw_vlan_del); 2085 2086 skip_vlan_table: 2087 /* PVID is being restored to the default whenever the PVID port 2088 * is being removed from the VLAN. 2089 */ 2090 if (priv->ports[port].pvid == vlan->vid) { 2091 priv->ports[port].pvid = G0_PORT_VID_DEF; 2092 2093 /* Only accept tagged frames if the port is VLAN-aware */ 2094 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 2095 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 2096 MT7530_VLAN_ACC_TAGGED); 2097 2098 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 2099 G0_PORT_VID_DEF); 2100 } 2101 2102 2103 mutex_unlock(&priv->reg_mutex); 2104 2105 return 0; 2106 } 2107 2108 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 2109 struct dsa_mall_mirror_tc_entry *mirror, 2110 bool ingress, struct netlink_ext_ack *extack) 2111 { 2112 struct mt7530_priv *priv = ds->priv; 2113 int monitor_port; 2114 u32 val; 2115 2116 /* Check for existent entry */ 2117 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 2118 return -EEXIST; 2119 2120 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 2121 2122 /* MT7530 only supports one monitor port */ 2123 monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val); 2124 if (val & MT753X_MIRROR_EN(priv->id) && 2125 monitor_port != mirror->to_local_port) 2126 return -EEXIST; 2127 2128 val |= MT753X_MIRROR_EN(priv->id); 2129 val &= ~MT753X_MIRROR_PORT_MASK(priv->id); 2130 val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port); 2131 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 2132 2133 val = mt7530_read(priv, MT7530_PCR_P(port)); 2134 if (ingress) { 2135 val |= PORT_RX_MIR; 2136 priv->mirror_rx |= BIT(port); 2137 } else { 2138 val |= PORT_TX_MIR; 2139 priv->mirror_tx |= BIT(port); 2140 } 2141 mt7530_write(priv, MT7530_PCR_P(port), val); 2142 2143 return 0; 2144 } 2145 2146 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 2147 struct dsa_mall_mirror_tc_entry *mirror) 2148 { 2149 struct mt7530_priv *priv = ds->priv; 2150 u32 val; 2151 2152 val = mt7530_read(priv, MT7530_PCR_P(port)); 2153 if (mirror->ingress) { 2154 val &= ~PORT_RX_MIR; 2155 priv->mirror_rx &= ~BIT(port); 2156 } else { 2157 val &= ~PORT_TX_MIR; 2158 priv->mirror_tx &= ~BIT(port); 2159 } 2160 mt7530_write(priv, MT7530_PCR_P(port), val); 2161 2162 if (!priv->mirror_rx && !priv->mirror_tx) { 2163 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 2164 val &= ~MT753X_MIRROR_EN(priv->id); 2165 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 2166 } 2167 } 2168 2169 static enum dsa_tag_protocol 2170 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 2171 enum dsa_tag_protocol mp) 2172 { 2173 return DSA_TAG_PROTO_MTK; 2174 } 2175 2176 #ifdef CONFIG_GPIOLIB 2177 static inline u32 2178 mt7530_gpio_to_bit(unsigned int offset) 2179 { 2180 /* Map GPIO offset to register bit 2181 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 2182 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 2183 * [10: 8] port 2 LED 0..2 as GPIO 6..8 2184 * [14:12] port 3 LED 0..2 as GPIO 9..11 2185 * [18:16] port 4 LED 0..2 as GPIO 12..14 2186 */ 2187 return BIT(offset + offset / 3); 2188 } 2189 2190 static int 2191 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 2192 { 2193 struct mt7530_priv *priv = gpiochip_get_data(gc); 2194 u32 bit = mt7530_gpio_to_bit(offset); 2195 2196 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 2197 } 2198 2199 static int 2200 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 2201 { 2202 struct mt7530_priv *priv = gpiochip_get_data(gc); 2203 u32 bit = mt7530_gpio_to_bit(offset); 2204 2205 if (value) 2206 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 2207 else 2208 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 2209 2210 return 0; 2211 } 2212 2213 static int 2214 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 2215 { 2216 struct mt7530_priv *priv = gpiochip_get_data(gc); 2217 u32 bit = mt7530_gpio_to_bit(offset); 2218 2219 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 2220 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 2221 } 2222 2223 static int 2224 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 2225 { 2226 struct mt7530_priv *priv = gpiochip_get_data(gc); 2227 u32 bit = mt7530_gpio_to_bit(offset); 2228 2229 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 2230 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 2231 2232 return 0; 2233 } 2234 2235 static int 2236 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 2237 { 2238 struct mt7530_priv *priv = gpiochip_get_data(gc); 2239 u32 bit = mt7530_gpio_to_bit(offset); 2240 2241 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 2242 2243 if (value) 2244 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 2245 else 2246 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 2247 2248 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 2249 2250 return 0; 2251 } 2252 2253 static int 2254 mt7530_setup_gpio(struct mt7530_priv *priv) 2255 { 2256 struct device *dev = priv->dev; 2257 struct gpio_chip *gc; 2258 2259 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 2260 if (!gc) 2261 return -ENOMEM; 2262 2263 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 2264 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 2265 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 2266 2267 gc->label = "mt7530"; 2268 gc->parent = dev; 2269 gc->owner = THIS_MODULE; 2270 gc->get_direction = mt7530_gpio_get_direction; 2271 gc->direction_input = mt7530_gpio_direction_input; 2272 gc->direction_output = mt7530_gpio_direction_output; 2273 gc->get = mt7530_gpio_get; 2274 gc->set = mt7530_gpio_set; 2275 gc->base = -1; 2276 gc->ngpio = 15; 2277 gc->can_sleep = true; 2278 2279 return devm_gpiochip_add_data(dev, gc, priv); 2280 } 2281 #endif /* CONFIG_GPIOLIB */ 2282 2283 static void 2284 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 2285 { 2286 struct dsa_switch *ds = priv->ds; 2287 int p; 2288 2289 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2290 if (BIT(p) & ds->phys_mii_mask) { 2291 unsigned int irq; 2292 2293 irq = irq_create_mapping(priv->irq_domain, p); 2294 ds->user_mii_bus->irq[p] = irq; 2295 } 2296 } 2297 } 2298 2299 static const struct regmap_irq mt7530_irqs[] = { 2300 REGMAP_IRQ_REG_LINE(0, 32), /* PHY0_LC */ 2301 REGMAP_IRQ_REG_LINE(1, 32), /* PHY1_LC */ 2302 REGMAP_IRQ_REG_LINE(2, 32), /* PHY2_LC */ 2303 REGMAP_IRQ_REG_LINE(3, 32), /* PHY3_LC */ 2304 REGMAP_IRQ_REG_LINE(4, 32), /* PHY4_LC */ 2305 REGMAP_IRQ_REG_LINE(5, 32), /* PHY5_LC */ 2306 REGMAP_IRQ_REG_LINE(6, 32), /* PHY6_LC */ 2307 REGMAP_IRQ_REG_LINE(16, 32), /* MAC_PC */ 2308 REGMAP_IRQ_REG_LINE(17, 32), /* BMU */ 2309 REGMAP_IRQ_REG_LINE(18, 32), /* MIB */ 2310 REGMAP_IRQ_REG_LINE(22, 32), /* ARL_COL_FULL_COL */ 2311 REGMAP_IRQ_REG_LINE(23, 32), /* ARL_COL_FULL */ 2312 REGMAP_IRQ_REG_LINE(24, 32), /* ARL_TBL_ERR */ 2313 REGMAP_IRQ_REG_LINE(25, 32), /* ARL_PKT_QERR */ 2314 REGMAP_IRQ_REG_LINE(26, 32), /* ARL_EQ_ERR */ 2315 REGMAP_IRQ_REG_LINE(27, 32), /* ARL_PKT_BC */ 2316 REGMAP_IRQ_REG_LINE(28, 32), /* ARL_SEC_IG1X */ 2317 REGMAP_IRQ_REG_LINE(29, 32), /* ARL_SEC_VLAN */ 2318 REGMAP_IRQ_REG_LINE(30, 32), /* ARL_SEC_TAG */ 2319 REGMAP_IRQ_REG_LINE(31, 32), /* ACL */ 2320 }; 2321 2322 /* Serialize regmap-irq's mask sync like every other regmap user */ 2323 static int mt7530_irq_mask_sync(int index, unsigned int mask_buf_def, 2324 unsigned int mask_buf, void *irq_drv_data) 2325 { 2326 struct mt7530_priv *priv = irq_drv_data; 2327 int ret; 2328 2329 mt7530_mutex_lock(priv); 2330 ret = regmap_update_bits(priv->regmap, MT7530_SYS_INT_EN, 2331 mask_buf_def, ~mask_buf); 2332 mt7530_mutex_unlock(priv); 2333 2334 return ret; 2335 } 2336 2337 static const struct regmap_irq_chip mt7530_regmap_irq_chip = { 2338 .name = KBUILD_MODNAME, 2339 .status_base = MT7530_SYS_INT_STS, 2340 .unmask_base = MT7530_SYS_INT_EN, 2341 .ack_base = MT7530_SYS_INT_STS, 2342 .init_ack_masked = true, 2343 .irqs = mt7530_irqs, 2344 .num_irqs = ARRAY_SIZE(mt7530_irqs), 2345 .num_regs = 1, 2346 .handle_mask_sync = mt7530_irq_mask_sync, 2347 }; 2348 2349 static int 2350 mt7530_setup_irq(struct mt7530_priv *priv) 2351 { 2352 struct regmap_irq_chip_data *irq_data; 2353 struct regmap_irq_chip *chip; 2354 struct device *dev = priv->dev; 2355 struct device_node *np = dev->of_node; 2356 int irq, ret; 2357 2358 if (!of_property_read_bool(np, "interrupt-controller")) { 2359 dev_info(dev, "no interrupt support\n"); 2360 return 0; 2361 } 2362 2363 irq = of_irq_get(np, 0); 2364 if (irq <= 0) { 2365 dev_err(dev, "failed to get parent IRQ: %d\n", irq); 2366 return irq ? : -EINVAL; 2367 } 2368 2369 /* This register must be set for MT7530 to properly fire interrupts */ 2370 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) 2371 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2372 2373 chip = devm_kmemdup(dev, &mt7530_regmap_irq_chip, sizeof(*chip), 2374 GFP_KERNEL); 2375 if (!chip) 2376 return -ENOMEM; 2377 2378 chip->irq_drv_data = priv; 2379 2380 ret = devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(dev), 2381 priv->regmap, irq, 2382 IRQF_ONESHOT, 2383 0, chip, 2384 &irq_data); 2385 if (ret) 2386 return ret; 2387 2388 priv->irq_domain = regmap_irq_get_domain(irq_data); 2389 2390 return 0; 2391 } 2392 2393 static void 2394 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2395 { 2396 int p; 2397 2398 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2399 if (BIT(p) & priv->ds->phys_mii_mask) { 2400 unsigned int irq; 2401 2402 irq = irq_find_mapping(priv->irq_domain, p); 2403 irq_dispose_mapping(irq); 2404 } 2405 } 2406 } 2407 2408 static int 2409 mt7530_setup_mdio(struct mt7530_priv *priv) 2410 { 2411 struct device_node *mnp, *np = priv->dev->of_node; 2412 struct dsa_switch *ds = priv->ds; 2413 struct device *dev = priv->dev; 2414 struct mii_bus *bus; 2415 static int idx; 2416 int ret = 0; 2417 2418 mnp = of_get_child_by_name(np, "mdio"); 2419 2420 if (mnp && !of_device_is_available(mnp)) 2421 goto out; 2422 2423 bus = devm_mdiobus_alloc(dev); 2424 if (!bus) { 2425 ret = -ENOMEM; 2426 goto out; 2427 } 2428 2429 if (!mnp) 2430 ds->user_mii_bus = bus; 2431 2432 bus->priv = priv; 2433 bus->name = KBUILD_MODNAME "-mii"; 2434 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2435 bus->read = mt753x_phy_read_c22; 2436 bus->write = mt753x_phy_write_c22; 2437 bus->read_c45 = mt753x_phy_read_c45; 2438 bus->write_c45 = mt753x_phy_write_c45; 2439 bus->parent = dev; 2440 bus->phy_mask = ~ds->phys_mii_mask; 2441 2442 if (priv->irq_domain && !mnp) 2443 mt7530_setup_mdio_irq(priv); 2444 2445 ret = devm_of_mdiobus_register(dev, bus, mnp); 2446 if (ret) { 2447 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2448 if (priv->irq_domain && !mnp) 2449 mt7530_free_mdio_irq(priv); 2450 } 2451 2452 out: 2453 of_node_put(mnp); 2454 return ret; 2455 } 2456 2457 static int 2458 mt7530_setup(struct dsa_switch *ds) 2459 { 2460 struct mt7530_priv *priv = ds->priv; 2461 struct device_node *dn = NULL; 2462 struct device_node *phy_node; 2463 struct device_node *mac_np; 2464 struct mt7530_dummy_poll p; 2465 phy_interface_t interface; 2466 struct dsa_port *cpu_dp; 2467 u32 id, val; 2468 int ret, i; 2469 2470 /* The parent node of conduit netdev which holds the common system 2471 * controller also is the container for two GMACs nodes representing 2472 * as two netdev instances. 2473 */ 2474 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2475 dn = cpu_dp->conduit->dev.of_node->parent; 2476 /* It doesn't matter which CPU port is found first, 2477 * their conduits should share the same parent OF node 2478 */ 2479 break; 2480 } 2481 2482 if (!dn) { 2483 dev_err(ds->dev, "parent OF node of DSA conduit not found"); 2484 return -EINVAL; 2485 } 2486 2487 ds->assisted_learning_on_cpu_port = true; 2488 ds->untag_vlan_aware_bridge_pvid = true; 2489 ds->mtu_enforcement_ingress = true; 2490 ds->ageing_time_min = 2 * 1000; 2491 ds->ageing_time_max = (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1) * 1000; 2492 2493 if (priv->id == ID_MT7530) { 2494 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2495 ret = regulator_enable(priv->core_pwr); 2496 if (ret < 0) { 2497 dev_err(priv->dev, 2498 "Failed to enable core power: %d\n", ret); 2499 return ret; 2500 } 2501 2502 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2503 ret = regulator_enable(priv->io_pwr); 2504 if (ret < 0) { 2505 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2506 ret); 2507 return ret; 2508 } 2509 } 2510 2511 /* Reset whole chip through gpio pin or memory-mapped registers for 2512 * different type of hardware 2513 */ 2514 if (priv->mcm) { 2515 reset_control_assert(priv->rstc); 2516 usleep_range(5000, 5100); 2517 reset_control_deassert(priv->rstc); 2518 } else { 2519 gpiod_set_value_cansleep(priv->reset, 0); 2520 usleep_range(5000, 5100); 2521 gpiod_set_value_cansleep(priv->reset, 1); 2522 } 2523 2524 /* Waiting for MT7530 got to stable */ 2525 INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); 2526 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2527 20, 1000000); 2528 if (ret < 0) { 2529 dev_err(priv->dev, "reset timeout\n"); 2530 return ret; 2531 } 2532 2533 id = mt7530_read(priv, MT7530_CREV); 2534 id >>= CHIP_NAME_SHIFT; 2535 if (id != MT7530_ID) { 2536 dev_err(priv->dev, "chip %x can't be supported\n", id); 2537 return -ENODEV; 2538 } 2539 2540 if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) { 2541 dev_err(priv->dev, 2542 "MT7530 with a 20MHz XTAL is not supported!\n"); 2543 return -EINVAL; 2544 } 2545 2546 /* Reset the switch through internal reset */ 2547 mt7530_write(priv, MT7530_SYS_CTRL, 2548 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2549 SYS_CTRL_REG_RST); 2550 2551 /* Lower Tx driving for TRGMII path */ 2552 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2553 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 2554 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2555 2556 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2557 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 2558 RD_TAP_MASK, RD_TAP(16)); 2559 2560 /* Allow modifying the trap and directly access PHY registers via the 2561 * MDIO bus the switch is on. 2562 */ 2563 mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP | 2564 MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP); 2565 2566 if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ) 2567 mt7530_pll_setup(priv); 2568 2569 mt753x_trap_frames(priv); 2570 2571 /* Enable and reset MIB counters */ 2572 mt7530_mib_reset(ds); 2573 2574 for (i = 0; i < priv->ds->num_ports; i++) { 2575 /* Clear link settings and enable force mode to force link down 2576 * on all ports until they're enabled later. 2577 */ 2578 mt7530_rmw(priv, MT753X_PMCR_P(i), 2579 PMCR_LINK_SETTINGS_MASK | 2580 MT753X_FORCE_MODE(priv->id), 2581 MT753X_FORCE_MODE(priv->id)); 2582 2583 /* Disable forwarding by default on all ports */ 2584 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2585 PCR_MATRIX_CLR); 2586 2587 /* Disable learning by default on all ports */ 2588 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2589 2590 if (dsa_is_cpu_port(ds, i)) { 2591 mt753x_cpu_port_enable(ds, i); 2592 } else { 2593 mt7530_port_disable(ds, i); 2594 2595 /* Set default PVID to 0 on all user ports */ 2596 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2597 G0_PORT_VID_DEF); 2598 } 2599 /* Enable consistent egress tag */ 2600 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2601 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2602 } 2603 2604 /* Allow mirroring frames received on the local port (monitor port). */ 2605 mt7530_set(priv, MT753X_AGC, LOCAL_EN); 2606 2607 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2608 ret = mt7530_setup_vlan0(priv); 2609 if (ret) 2610 return ret; 2611 2612 /* Check for PHY muxing on port 5 */ 2613 if (dsa_is_unused_port(ds, 5)) { 2614 /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. 2615 * Set priv->p5_mode to the appropriate value if PHY muxing is 2616 * detected. 2617 */ 2618 for_each_child_of_node(dn, mac_np) { 2619 if (!of_device_is_compatible(mac_np, 2620 "mediatek,eth-mac")) 2621 continue; 2622 2623 ret = of_property_read_u32(mac_np, "reg", &id); 2624 if (ret < 0 || id != 1) 2625 continue; 2626 2627 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2628 if (!phy_node) 2629 continue; 2630 2631 if (phy_node->parent == priv->dev->of_node->parent || 2632 phy_node->parent->parent == priv->dev->of_node) { 2633 ret = of_get_phy_mode(mac_np, &interface); 2634 if (ret && ret != -ENODEV) { 2635 of_node_put(mac_np); 2636 of_node_put(phy_node); 2637 return ret; 2638 } 2639 id = of_mdio_parse_addr(ds->dev, phy_node); 2640 if (id == 0) 2641 priv->p5_mode = MUX_PHY_P0; 2642 if (id == 4) 2643 priv->p5_mode = MUX_PHY_P4; 2644 } 2645 of_node_put(mac_np); 2646 of_node_put(phy_node); 2647 break; 2648 } 2649 2650 if (priv->p5_mode == MUX_PHY_P0 || 2651 priv->p5_mode == MUX_PHY_P4) { 2652 mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); 2653 mt7530_setup_port5(ds, interface); 2654 } 2655 } 2656 2657 #ifdef CONFIG_GPIOLIB 2658 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2659 ret = mt7530_setup_gpio(priv); 2660 if (ret) 2661 return ret; 2662 } 2663 #endif /* CONFIG_GPIOLIB */ 2664 2665 /* Flush the FDB table */ 2666 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2667 if (ret < 0) 2668 return ret; 2669 2670 return 0; 2671 } 2672 2673 static int 2674 mt7531_setup_common(struct dsa_switch *ds) 2675 { 2676 struct mt7530_priv *priv = ds->priv; 2677 int ret, i; 2678 2679 ds->assisted_learning_on_cpu_port = true; 2680 ds->untag_vlan_aware_bridge_pvid = true; 2681 ds->mtu_enforcement_ingress = true; 2682 ds->ageing_time_min = 2 * 1000; 2683 ds->ageing_time_max = (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1) * 1000; 2684 2685 mt753x_trap_frames(priv); 2686 2687 /* Enable and reset MIB counters */ 2688 mt7530_mib_reset(ds); 2689 2690 /* Disable flooding on all ports */ 2691 mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK | 2692 UNU_FFP_MASK); 2693 2694 for (i = 0; i < priv->ds->num_ports; i++) { 2695 /* Clear link settings and enable force mode to force link down 2696 * on all ports until they're enabled later. 2697 */ 2698 mt7530_rmw(priv, MT753X_PMCR_P(i), 2699 PMCR_LINK_SETTINGS_MASK | 2700 MT753X_FORCE_MODE(priv->id), 2701 MT753X_FORCE_MODE(priv->id)); 2702 2703 /* Disable forwarding by default on all ports */ 2704 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2705 PCR_MATRIX_CLR); 2706 2707 /* Disable learning by default on all ports */ 2708 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2709 2710 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2711 2712 if (dsa_is_cpu_port(ds, i)) { 2713 mt753x_cpu_port_enable(ds, i); 2714 } else { 2715 mt7530_port_disable(ds, i); 2716 2717 /* Set default PVID to 0 on all user ports */ 2718 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2719 G0_PORT_VID_DEF); 2720 } 2721 2722 /* Enable consistent egress tag */ 2723 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2724 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2725 } 2726 2727 /* Allow mirroring frames received on the local port (monitor port). */ 2728 mt7530_set(priv, MT753X_AGC, LOCAL_EN); 2729 2730 /* Enable Special Tag for rx frames */ 2731 if (priv->id == ID_EN7581 || priv->id == ID_AN7583) 2732 mt7530_write(priv, MT753X_CPORT_SPTAG_CFG, 2733 CPORT_SW2FE_STAG_EN | CPORT_FE2SW_STAG_EN); 2734 2735 /* Flush the FDB table */ 2736 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2737 if (ret < 0) 2738 return ret; 2739 2740 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2741 return mt7530_setup_vlan0(priv); 2742 } 2743 2744 static int 2745 mt7531_setup(struct dsa_switch *ds) 2746 { 2747 struct mt7530_priv *priv = ds->priv; 2748 struct mt7530_dummy_poll p; 2749 u32 val, id; 2750 int ret, i; 2751 2752 /* Reset whole chip through gpio pin or memory-mapped registers for 2753 * different type of hardware 2754 */ 2755 if (priv->mcm) { 2756 reset_control_assert(priv->rstc); 2757 usleep_range(5000, 5100); 2758 reset_control_deassert(priv->rstc); 2759 } else { 2760 gpiod_set_value_cansleep(priv->reset, 0); 2761 usleep_range(5000, 5100); 2762 gpiod_set_value_cansleep(priv->reset, 1); 2763 } 2764 2765 /* Waiting for MT7530 got to stable */ 2766 INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); 2767 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2768 20, 1000000); 2769 if (ret < 0) { 2770 dev_err(priv->dev, "reset timeout\n"); 2771 return ret; 2772 } 2773 2774 id = mt7530_read(priv, MT7531_CREV); 2775 id >>= CHIP_NAME_SHIFT; 2776 2777 if (id != MT7531_ID) { 2778 dev_err(priv->dev, "chip %x can't be supported\n", id); 2779 return -ENODEV; 2780 } 2781 2782 /* MT7531AE has got two SGMII units. One for port 5, one for port 6. 2783 * MT7531BE has got only one SGMII unit which is for port 6. 2784 */ 2785 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 2786 priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); 2787 2788 /* Force link down on all ports before internal reset */ 2789 for (i = 0; i < priv->ds->num_ports; i++) 2790 mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK); 2791 2792 /* Reset the switch through internal reset */ 2793 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); 2794 2795 if (!priv->p5_sgmii) { 2796 mt7531_pll_setup(priv); 2797 } else { 2798 /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on 2799 * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO 2800 * to expose the MDIO bus of the switch. 2801 */ 2802 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2803 MT7531_EXT_P_MDC_11); 2804 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2805 MT7531_EXT_P_MDIO_12); 2806 } 2807 2808 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2809 MT7531_GPIO0_INTERRUPT); 2810 2811 /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since 2812 * phy_device has not yet been created provided for 2813 * phy_[read,write]_mmd_indirect is called, we provide our own 2814 * mt7531_ind_mmd_phy_[read,write] to complete this function. 2815 */ 2816 ret = mt7531_ind_c45_phy_read(priv, 2817 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 2818 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2819 if (ret < 0) 2820 return ret; 2821 2822 val = ret; 2823 val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE; 2824 val &= ~MT7531_PHY_PLL_OFF; 2825 ret = mt7531_ind_c45_phy_write(priv, 2826 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 2827 MDIO_MMD_VEND2, CORE_PLL_GROUP4, val); 2828 if (ret < 0) 2829 return ret; 2830 2831 /* Disable EEE advertisement on the switch PHYs. */ 2832 for (i = MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr); 2833 i < MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr) + MT7530_NUM_PHYS; 2834 i++) { 2835 mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 2836 0); 2837 } 2838 2839 ret = mt7531_setup_common(ds); 2840 if (ret) 2841 return ret; 2842 2843 return 0; 2844 } 2845 2846 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2847 struct phylink_config *config) 2848 { 2849 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2850 2851 switch (port) { 2852 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2853 case 0 ... 4: 2854 __set_bit(PHY_INTERFACE_MODE_GMII, 2855 config->supported_interfaces); 2856 break; 2857 2858 /* Port 5 supports rgmii with delays, mii, and gmii. */ 2859 case 5: 2860 phy_interface_set_rgmii(config->supported_interfaces); 2861 __set_bit(PHY_INTERFACE_MODE_MII, 2862 config->supported_interfaces); 2863 __set_bit(PHY_INTERFACE_MODE_GMII, 2864 config->supported_interfaces); 2865 break; 2866 2867 /* Port 6 supports rgmii and trgmii. */ 2868 case 6: 2869 __set_bit(PHY_INTERFACE_MODE_RGMII, 2870 config->supported_interfaces); 2871 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2872 config->supported_interfaces); 2873 break; 2874 } 2875 } 2876 2877 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2878 struct phylink_config *config) 2879 { 2880 struct mt7530_priv *priv = ds->priv; 2881 2882 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2883 2884 switch (port) { 2885 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2886 case 0 ... 4: 2887 __set_bit(PHY_INTERFACE_MODE_GMII, 2888 config->supported_interfaces); 2889 break; 2890 2891 /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on 2892 * MT7531AE. 2893 */ 2894 case 5: 2895 if (!priv->p5_sgmii) { 2896 phy_interface_set_rgmii(config->supported_interfaces); 2897 break; 2898 } 2899 fallthrough; 2900 2901 /* Port 6 supports sgmii/802.3z. */ 2902 case 6: 2903 __set_bit(PHY_INTERFACE_MODE_SGMII, 2904 config->supported_interfaces); 2905 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2906 config->supported_interfaces); 2907 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2908 config->supported_interfaces); 2909 2910 config->mac_capabilities |= MAC_2500FD; 2911 break; 2912 } 2913 } 2914 2915 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, 2916 struct phylink_config *config) 2917 { 2918 switch (port) { 2919 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2920 case 0 ... 3: 2921 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2922 config->supported_interfaces); 2923 2924 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2925 break; 2926 2927 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2928 case 6: 2929 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2930 config->supported_interfaces); 2931 2932 config->mac_capabilities |= MAC_10000FD; 2933 break; 2934 } 2935 } 2936 2937 static void en7581_mac_port_get_caps(struct dsa_switch *ds, int port, 2938 struct phylink_config *config) 2939 { 2940 switch (port) { 2941 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2942 case 0 ... 4: 2943 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2944 config->supported_interfaces); 2945 2946 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2947 break; 2948 2949 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2950 case 6: 2951 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2952 config->supported_interfaces); 2953 2954 config->mac_capabilities |= MAC_10000FD; 2955 break; 2956 } 2957 } 2958 2959 static void en7528_mac_port_get_caps(struct dsa_switch *ds, int port, 2960 struct phylink_config *config) 2961 { 2962 switch (port) { 2963 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2964 case 1 ... 4: 2965 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2966 config->supported_interfaces); 2967 2968 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2969 break; 2970 2971 /* Port 6 is connected to SoC's GMAC at 1000 Mbps full duplex. There 2972 * is no MII pinout. 2973 */ 2974 case 6: 2975 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2976 config->supported_interfaces); 2977 2978 config->mac_capabilities |= MAC_1000FD; 2979 break; 2980 } 2981 } 2982 2983 static void 2984 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2985 phy_interface_t interface) 2986 { 2987 struct mt7530_priv *priv = ds->priv; 2988 2989 if (port == 5) 2990 mt7530_setup_port5(priv->ds, interface); 2991 else if (port == 6) 2992 mt7530_setup_port6(priv->ds, interface); 2993 } 2994 2995 static void mt7531_rgmii_setup(struct mt7530_priv *priv, 2996 phy_interface_t interface, 2997 struct phy_device *phydev) 2998 { 2999 u32 val; 3000 3001 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 3002 val |= GP_CLK_EN; 3003 val &= ~GP_MODE_MASK; 3004 val |= GP_MODE(MT7531_GP_MODE_RGMII); 3005 val &= ~CLK_SKEW_IN_MASK; 3006 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 3007 val &= ~CLK_SKEW_OUT_MASK; 3008 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 3009 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 3010 3011 /* Do not adjust rgmii delay when vendor phy driver presents. */ 3012 if (!phydev || phy_driver_is_genphy(phydev)) { 3013 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 3014 switch (interface) { 3015 case PHY_INTERFACE_MODE_RGMII: 3016 val |= TXCLK_NO_REVERSE; 3017 val |= RXCLK_NO_DELAY; 3018 break; 3019 case PHY_INTERFACE_MODE_RGMII_RXID: 3020 val |= TXCLK_NO_REVERSE; 3021 break; 3022 case PHY_INTERFACE_MODE_RGMII_TXID: 3023 val |= RXCLK_NO_DELAY; 3024 break; 3025 case PHY_INTERFACE_MODE_RGMII_ID: 3026 break; 3027 default: 3028 break; 3029 } 3030 } 3031 3032 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 3033 } 3034 3035 static void 3036 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 3037 phy_interface_t interface) 3038 { 3039 struct mt7530_priv *priv = ds->priv; 3040 struct phy_device *phydev; 3041 struct dsa_port *dp; 3042 3043 if (phy_interface_mode_is_rgmii(interface)) { 3044 dp = dsa_to_port(ds, port); 3045 phydev = dp->user->phydev; 3046 mt7531_rgmii_setup(priv, interface, phydev); 3047 } 3048 } 3049 3050 static struct phylink_pcs * 3051 mt753x_phylink_mac_select_pcs(struct phylink_config *config, 3052 phy_interface_t interface) 3053 { 3054 struct dsa_port *dp = dsa_phylink_to_port(config); 3055 struct mt7530_priv *priv = dp->ds->priv; 3056 3057 switch (interface) { 3058 case PHY_INTERFACE_MODE_TRGMII: 3059 return &priv->pcs[dp->index].pcs; 3060 case PHY_INTERFACE_MODE_SGMII: 3061 case PHY_INTERFACE_MODE_1000BASEX: 3062 case PHY_INTERFACE_MODE_2500BASEX: 3063 return priv->ports[dp->index].sgmii_pcs; 3064 default: 3065 return NULL; 3066 } 3067 } 3068 3069 static void 3070 mt753x_phylink_mac_config(struct phylink_config *config, unsigned int mode, 3071 const struct phylink_link_state *state) 3072 { 3073 struct dsa_port *dp = dsa_phylink_to_port(config); 3074 struct dsa_switch *ds = dp->ds; 3075 struct mt7530_priv *priv; 3076 int port = dp->index; 3077 3078 priv = ds->priv; 3079 3080 if ((port == 5 || port == 6) && priv->info->mac_port_config) 3081 priv->info->mac_port_config(ds, port, mode, state->interface); 3082 3083 /* Are we connected to external phy */ 3084 if (port == 5 && dsa_is_user_port(ds, 5)) 3085 mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY); 3086 } 3087 3088 static void mt753x_phylink_mac_link_down(struct phylink_config *config, 3089 unsigned int mode, 3090 phy_interface_t interface) 3091 { 3092 struct dsa_port *dp = dsa_phylink_to_port(config); 3093 struct mt7530_priv *priv = dp->ds->priv; 3094 3095 mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); 3096 } 3097 3098 static void mt753x_phylink_mac_link_up(struct phylink_config *config, 3099 struct phy_device *phydev, 3100 unsigned int mode, 3101 phy_interface_t interface, 3102 int speed, int duplex, 3103 bool tx_pause, bool rx_pause) 3104 { 3105 struct dsa_port *dp = dsa_phylink_to_port(config); 3106 struct mt7530_priv *priv = dp->ds->priv; 3107 u32 mcr; 3108 3109 mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK; 3110 3111 switch (speed) { 3112 case SPEED_1000: 3113 case SPEED_2500: 3114 case SPEED_10000: 3115 mcr |= PMCR_FORCE_SPEED_1000; 3116 break; 3117 case SPEED_100: 3118 mcr |= PMCR_FORCE_SPEED_100; 3119 break; 3120 } 3121 if (duplex == DUPLEX_FULL) { 3122 mcr |= PMCR_FORCE_FDX; 3123 if (tx_pause) 3124 mcr |= PMCR_FORCE_TX_FC_EN; 3125 if (rx_pause) 3126 mcr |= PMCR_FORCE_RX_FC_EN; 3127 } 3128 3129 mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr); 3130 } 3131 3132 static void mt753x_phylink_mac_disable_tx_lpi(struct phylink_config *config) 3133 { 3134 struct dsa_port *dp = dsa_phylink_to_port(config); 3135 struct mt7530_priv *priv = dp->ds->priv; 3136 3137 mt7530_clear(priv, MT753X_PMCR_P(dp->index), 3138 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100); 3139 } 3140 3141 static int mt753x_phylink_mac_enable_tx_lpi(struct phylink_config *config, 3142 u32 timer, bool tx_clock_stop) 3143 { 3144 struct dsa_port *dp = dsa_phylink_to_port(config); 3145 struct mt7530_priv *priv = dp->ds->priv; 3146 u32 val; 3147 3148 /* If the timer is zero, then set LPI_MODE_EN, which allows the 3149 * system to enter LPI mode immediately rather than waiting for 3150 * the LPI threshold. 3151 */ 3152 if (!timer) 3153 val = LPI_MODE_EN; 3154 else if (FIELD_FIT(LPI_THRESH_MASK, timer)) 3155 val = FIELD_PREP(LPI_THRESH_MASK, timer); 3156 else 3157 val = LPI_THRESH_MASK; 3158 3159 mt7530_rmw(priv, MT753X_PMEEECR_P(dp->index), 3160 LPI_THRESH_MASK | LPI_MODE_EN, val); 3161 3162 mt7530_set(priv, MT753X_PMCR_P(dp->index), 3163 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100); 3164 3165 return 0; 3166 } 3167 3168 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 3169 struct phylink_config *config) 3170 { 3171 struct mt7530_priv *priv = ds->priv; 3172 3173 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE; 3174 3175 /* The EN7528 GPHYs report EEE capability, but negotiating EEE with 3176 * common link partners (e.g. Realtek GbE NICs) results in an unstable 3177 * link with dropped frames. Leave the LPI capabilities empty so that 3178 * phylink disables EEE on these PHYs and refuses to enable it from 3179 * userspace. 3180 */ 3181 if (priv->id != ID_EN7528) { 3182 u32 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port)); 3183 3184 config->lpi_capabilities = MAC_100FD | MAC_1000FD | MAC_2500FD; 3185 /* tx_lpi_timer should be in microseconds. The time units for 3186 * LPI threshold are unspecified. 3187 */ 3188 config->lpi_timer_default = FIELD_GET(LPI_THRESH_MASK, eeecr); 3189 } 3190 3191 priv->info->mac_port_get_caps(ds, port, config); 3192 } 3193 3194 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 3195 unsigned long *supported, 3196 const struct phylink_link_state *state) 3197 { 3198 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 3199 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 3200 phy_interface_mode_is_8023z(state->interface)) 3201 phylink_clear(supported, Autoneg); 3202 3203 return 0; 3204 } 3205 3206 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, 3207 struct phylink_link_state *state) 3208 { 3209 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 3210 int port = pcs_to_mt753x_pcs(pcs)->port; 3211 u32 pmsr; 3212 3213 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 3214 3215 state->link = (pmsr & PMSR_LINK); 3216 state->an_complete = state->link; 3217 state->duplex = !!(pmsr & PMSR_DPX); 3218 3219 switch (pmsr & PMSR_SPEED_MASK) { 3220 case PMSR_SPEED_10: 3221 state->speed = SPEED_10; 3222 break; 3223 case PMSR_SPEED_100: 3224 state->speed = SPEED_100; 3225 break; 3226 case PMSR_SPEED_1000: 3227 state->speed = SPEED_1000; 3228 break; 3229 default: 3230 state->speed = SPEED_UNKNOWN; 3231 break; 3232 } 3233 3234 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 3235 if (pmsr & PMSR_RX_FC) 3236 state->pause |= MLO_PAUSE_RX; 3237 if (pmsr & PMSR_TX_FC) 3238 state->pause |= MLO_PAUSE_TX; 3239 } 3240 3241 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 3242 phy_interface_t interface, 3243 const unsigned long *advertising, 3244 bool permit_pause_to_mac) 3245 { 3246 return 0; 3247 } 3248 3249 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 3250 { 3251 } 3252 3253 static const struct phylink_pcs_ops mt7530_pcs_ops = { 3254 .pcs_validate = mt753x_pcs_validate, 3255 .pcs_get_state = mt7530_pcs_get_state, 3256 .pcs_config = mt753x_pcs_config, 3257 .pcs_an_restart = mt7530_pcs_an_restart, 3258 }; 3259 3260 static int 3261 mt753x_setup(struct dsa_switch *ds) 3262 { 3263 struct mt7530_priv *priv = ds->priv; 3264 int ret = priv->info->sw_setup(ds); 3265 int i; 3266 3267 if (ret) 3268 return ret; 3269 3270 ret = mt7530_setup_irq(priv); 3271 if (ret) 3272 return ret; 3273 3274 ret = mt7530_setup_mdio(priv); 3275 if (ret) 3276 return ret; 3277 3278 /* Initialise the PCS devices */ 3279 for (i = 0; i < priv->ds->num_ports; i++) { 3280 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3281 priv->pcs[i].priv = priv; 3282 priv->pcs[i].port = i; 3283 } 3284 3285 if (priv->create_sgmii) 3286 ret = priv->create_sgmii(priv); 3287 3288 if (ret && priv->irq_domain) 3289 mt7530_free_mdio_irq(priv); 3290 3291 if (!ret && priv->bus) { 3292 mt7530_stats_refresh(priv); 3293 schedule_delayed_work(&priv->stats_work, 3294 MT7530_STATS_POLL_INTERVAL); 3295 } 3296 3297 return ret; 3298 } 3299 3300 static void 3301 mt753x_teardown(struct dsa_switch *ds) 3302 { 3303 struct mt7530_priv *priv = ds->priv; 3304 3305 if (priv->bus) 3306 cancel_delayed_work_sync(&priv->stats_work); 3307 } 3308 3309 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3310 struct ethtool_keee *e) 3311 { 3312 if (e->tx_lpi_timer > 0xFFF) 3313 return -EINVAL; 3314 3315 return 0; 3316 } 3317 3318 static void 3319 mt753x_conduit_state_change(struct dsa_switch *ds, 3320 const struct net_device *conduit, 3321 bool operational) 3322 { 3323 struct dsa_port *cpu_dp = conduit->dsa_ptr; 3324 struct mt7530_priv *priv = ds->priv; 3325 int val = 0; 3326 u8 mask; 3327 3328 /* Set the CPU port to trap frames to for MT7530. Trapped frames will be 3329 * forwarded to the numerically smallest CPU port whose conduit 3330 * interface is up. 3331 */ 3332 if (priv->id != ID_MT7530 && priv->id != ID_MT7621 && 3333 priv->id != ID_EN7528) 3334 return; 3335 3336 mask = BIT(cpu_dp->index); 3337 3338 if (operational) 3339 priv->active_cpu_ports |= mask; 3340 else 3341 priv->active_cpu_ports &= ~mask; 3342 3343 if (priv->active_cpu_ports) { 3344 val = MT7530_CPU_EN | 3345 MT7530_CPU_PORT(__ffs(priv->active_cpu_ports)); 3346 } 3347 3348 mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val); 3349 } 3350 3351 static int mt753x_tc_setup_qdisc_tbf(struct dsa_switch *ds, int port, 3352 struct tc_tbf_qopt_offload *qopt) 3353 { 3354 struct tc_tbf_qopt_offload_replace_params *p = &qopt->replace_params; 3355 struct mt7530_priv *priv = ds->priv; 3356 u32 rate = 0; 3357 3358 switch (qopt->command) { 3359 case TC_TBF_REPLACE: 3360 rate = div_u64(p->rate.rate_bytes_ps, 1000) << 3; /* kbps */ 3361 fallthrough; 3362 case TC_TBF_DESTROY: { 3363 u32 val, tick; 3364 3365 mt7530_rmw(priv, MT753X_GERLCR, EGR_BC_MASK, 3366 EGR_BC_CRC_IPG_PREAMBLE); 3367 3368 /* if rate is greater than 10Mbps tick is 1/32 ms, 3369 * 1ms otherwise 3370 */ 3371 tick = rate > 10000 ? 2 : 7; 3372 val = FIELD_PREP(ERLCR_CIR_MASK, (rate >> 5)) | 3373 FIELD_PREP(ERLCR_EN_MASK, !!rate) | 3374 FIELD_PREP(ERLCR_EXP_MASK, tick) | 3375 ERLCR_TBF_MODE_MASK | 3376 FIELD_PREP(ERLCR_MANT_MASK, 0xf); 3377 mt7530_write(priv, MT753X_ERLCR_P(port), val); 3378 break; 3379 } 3380 default: 3381 return -EOPNOTSUPP; 3382 } 3383 3384 return 0; 3385 } 3386 3387 static int mt753x_setup_tc(struct dsa_switch *ds, int port, 3388 enum tc_setup_type type, void *type_data) 3389 { 3390 switch (type) { 3391 case TC_SETUP_QDISC_TBF: 3392 return mt753x_tc_setup_qdisc_tbf(ds, port, type_data); 3393 default: 3394 return -EOPNOTSUPP; 3395 } 3396 } 3397 3398 static int mt7988_setup(struct dsa_switch *ds) 3399 { 3400 struct mt7530_priv *priv = ds->priv; 3401 3402 /* Reset the switch */ 3403 reset_control_assert(priv->rstc); 3404 usleep_range(20, 50); 3405 reset_control_deassert(priv->rstc); 3406 usleep_range(20, 50); 3407 3408 /* AN7583 require additional tweak to CONN_CFG */ 3409 if (priv->id == ID_AN7583) 3410 mt7530_rmw(priv, AN7583_GEPHY_CONN_CFG, 3411 AN7583_CSR_DPHY_CKIN_SEL | 3412 AN7583_CSR_PHY_CORE_REG_CLK_SEL | 3413 AN7583_CSR_ETHER_AFE_PWD, 3414 AN7583_CSR_DPHY_CKIN_SEL | 3415 AN7583_CSR_PHY_CORE_REG_CLK_SEL | 3416 FIELD_PREP(AN7583_CSR_ETHER_AFE_PWD, 0)); 3417 3418 /* Reset the switch PHYs */ 3419 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST); 3420 3421 return mt7531_setup_common(ds); 3422 } 3423 3424 static const struct dsa_switch_ops mt7530_switch_ops = { 3425 .get_tag_protocol = mtk_get_tag_protocol, 3426 .setup = mt753x_setup, 3427 .teardown = mt753x_teardown, 3428 .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, 3429 .get_strings = mt7530_get_strings, 3430 .get_ethtool_stats = mt7530_get_ethtool_stats, 3431 .get_sset_count = mt7530_get_sset_count, 3432 .get_eth_mac_stats = mt7530_get_eth_mac_stats, 3433 .get_rmon_stats = mt7530_get_rmon_stats, 3434 .get_eth_ctrl_stats = mt7530_get_eth_ctrl_stats, 3435 .get_stats64 = mt7530_get_stats64, 3436 .set_ageing_time = mt7530_set_ageing_time, 3437 .port_enable = mt7530_port_enable, 3438 .port_disable = mt7530_port_disable, 3439 .port_change_mtu = mt7530_port_change_mtu, 3440 .port_max_mtu = mt7530_port_max_mtu, 3441 .port_stp_state_set = mt7530_stp_state_set, 3442 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3443 .port_bridge_flags = mt7530_port_bridge_flags, 3444 .port_bridge_join = mt7530_port_bridge_join, 3445 .port_bridge_leave = mt7530_port_bridge_leave, 3446 .port_fdb_add = mt7530_port_fdb_add, 3447 .port_fdb_del = mt7530_port_fdb_del, 3448 .port_fdb_dump = mt7530_port_fdb_dump, 3449 .port_mdb_add = mt7530_port_mdb_add, 3450 .port_mdb_del = mt7530_port_mdb_del, 3451 .port_vlan_filtering = mt7530_port_vlan_filtering, 3452 .port_vlan_add = mt7530_port_vlan_add, 3453 .port_vlan_del = mt7530_port_vlan_del, 3454 .port_mirror_add = mt753x_port_mirror_add, 3455 .port_mirror_del = mt753x_port_mirror_del, 3456 .phylink_get_caps = mt753x_phylink_get_caps, 3457 .support_eee = dsa_supports_eee, 3458 .set_mac_eee = mt753x_set_mac_eee, 3459 .conduit_state_change = mt753x_conduit_state_change, 3460 .port_setup_tc = mt753x_setup_tc, 3461 .port_hsr_join = dsa_port_simple_hsr_join, 3462 .port_hsr_leave = dsa_port_simple_hsr_leave, 3463 }; 3464 3465 static const struct phylink_mac_ops mt753x_phylink_mac_ops = { 3466 .mac_select_pcs = mt753x_phylink_mac_select_pcs, 3467 .mac_config = mt753x_phylink_mac_config, 3468 .mac_link_down = mt753x_phylink_mac_link_down, 3469 .mac_link_up = mt753x_phylink_mac_link_up, 3470 .mac_disable_tx_lpi = mt753x_phylink_mac_disable_tx_lpi, 3471 .mac_enable_tx_lpi = mt753x_phylink_mac_enable_tx_lpi, 3472 }; 3473 3474 const struct mt753x_info mt753x_table[] = { 3475 [ID_MT7621] = { 3476 .id = ID_MT7621, 3477 .pcs_ops = &mt7530_pcs_ops, 3478 .sw_setup = mt7530_setup, 3479 .phy_read_c22 = mt7530_phy_read_c22, 3480 .phy_write_c22 = mt7530_phy_write_c22, 3481 .phy_read_c45 = mt7530_phy_read_c45, 3482 .phy_write_c45 = mt7530_phy_write_c45, 3483 .mac_port_get_caps = mt7530_mac_port_get_caps, 3484 .mac_port_config = mt7530_mac_config, 3485 }, 3486 [ID_MT7530] = { 3487 .id = ID_MT7530, 3488 .pcs_ops = &mt7530_pcs_ops, 3489 .sw_setup = mt7530_setup, 3490 .phy_read_c22 = mt7530_phy_read_c22, 3491 .phy_write_c22 = mt7530_phy_write_c22, 3492 .phy_read_c45 = mt7530_phy_read_c45, 3493 .phy_write_c45 = mt7530_phy_write_c45, 3494 .mac_port_get_caps = mt7530_mac_port_get_caps, 3495 .mac_port_config = mt7530_mac_config, 3496 }, 3497 [ID_MT7531] = { 3498 .id = ID_MT7531, 3499 .pcs_ops = &mt7530_pcs_ops, 3500 .sw_setup = mt7531_setup, 3501 .phy_read_c22 = mt7531_ind_c22_phy_read, 3502 .phy_write_c22 = mt7531_ind_c22_phy_write, 3503 .phy_read_c45 = mt7531_ind_c45_phy_read, 3504 .phy_write_c45 = mt7531_ind_c45_phy_write, 3505 .mac_port_get_caps = mt7531_mac_port_get_caps, 3506 .mac_port_config = mt7531_mac_config, 3507 }, 3508 [ID_MT7988] = { 3509 .id = ID_MT7988, 3510 .pcs_ops = &mt7530_pcs_ops, 3511 .sw_setup = mt7988_setup, 3512 .phy_read_c22 = mt7531_ind_c22_phy_read, 3513 .phy_write_c22 = mt7531_ind_c22_phy_write, 3514 .phy_read_c45 = mt7531_ind_c45_phy_read, 3515 .phy_write_c45 = mt7531_ind_c45_phy_write, 3516 .mac_port_get_caps = mt7988_mac_port_get_caps, 3517 }, 3518 [ID_EN7581] = { 3519 .id = ID_EN7581, 3520 .pcs_ops = &mt7530_pcs_ops, 3521 .sw_setup = mt7988_setup, 3522 .phy_read_c22 = mt7531_ind_c22_phy_read, 3523 .phy_write_c22 = mt7531_ind_c22_phy_write, 3524 .phy_read_c45 = mt7531_ind_c45_phy_read, 3525 .phy_write_c45 = mt7531_ind_c45_phy_write, 3526 .mac_port_get_caps = en7581_mac_port_get_caps, 3527 }, 3528 [ID_AN7583] = { 3529 .id = ID_AN7583, 3530 .pcs_ops = &mt7530_pcs_ops, 3531 .sw_setup = mt7988_setup, 3532 .phy_read_c22 = mt7531_ind_c22_phy_read, 3533 .phy_write_c22 = mt7531_ind_c22_phy_write, 3534 .phy_read_c45 = mt7531_ind_c45_phy_read, 3535 .phy_write_c45 = mt7531_ind_c45_phy_write, 3536 .mac_port_get_caps = en7581_mac_port_get_caps, 3537 }, 3538 [ID_EN7528] = { 3539 .id = ID_EN7528, 3540 .pcs_ops = &mt7530_pcs_ops, 3541 .sw_setup = mt7988_setup, 3542 .phy_read_c22 = mt7531_ind_c22_phy_read, 3543 .phy_write_c22 = mt7531_ind_c22_phy_write, 3544 .phy_read_c45 = mt7531_ind_c45_phy_read, 3545 .phy_write_c45 = mt7531_ind_c45_phy_write, 3546 .mac_port_get_caps = en7528_mac_port_get_caps, 3547 }, 3548 }; 3549 EXPORT_SYMBOL_GPL(mt753x_table); 3550 3551 int 3552 mt7530_probe_common(struct mt7530_priv *priv) 3553 { 3554 struct device *dev = priv->dev; 3555 3556 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 3557 if (!priv->ds) 3558 return -ENOMEM; 3559 3560 priv->ds->dev = dev; 3561 priv->ds->num_ports = MT7530_NUM_PORTS; 3562 3563 /* Get the hardware identifier from the devicetree node. 3564 * We will need it for some of the clock and regulator setup. 3565 */ 3566 priv->info = of_device_get_match_data(dev); 3567 if (!priv->info) 3568 return -EINVAL; 3569 3570 priv->id = priv->info->id; 3571 priv->dev = dev; 3572 priv->ds->priv = priv; 3573 priv->ds->ops = &mt7530_switch_ops; 3574 priv->ds->phylink_mac_ops = &mt753x_phylink_mac_ops; 3575 mutex_init(&priv->reg_mutex); 3576 spin_lock_init(&priv->stats_lock); 3577 INIT_DELAYED_WORK(&priv->stats_work, mt7530_stats_poll); 3578 3579 dev_set_drvdata(dev, priv); 3580 3581 return 0; 3582 } 3583 EXPORT_SYMBOL_GPL(mt7530_probe_common); 3584 3585 void 3586 mt7530_remove_common(struct mt7530_priv *priv) 3587 { 3588 if (priv->irq_domain) 3589 mt7530_free_mdio_irq(priv); 3590 3591 dsa_unregister_switch(priv->ds); 3592 3593 mutex_destroy(&priv->reg_mutex); 3594 } 3595 EXPORT_SYMBOL_GPL(mt7530_remove_common); 3596 3597 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3598 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3599 MODULE_LICENSE("GPL"); 3600