1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 28 { 29 return container_of(pcs, struct mt753x_pcs, pcs); 30 } 31 32 /* String, offset, and register size in bytes if different from 4 bytes */ 33 static const struct mt7530_mib_desc mt7530_mib[] = { 34 MIB_DESC(1, 0x00, "TxDrop"), 35 MIB_DESC(1, 0x04, "TxCrcErr"), 36 MIB_DESC(1, 0x08, "TxUnicast"), 37 MIB_DESC(1, 0x0c, "TxMulticast"), 38 MIB_DESC(1, 0x10, "TxBroadcast"), 39 MIB_DESC(1, 0x14, "TxCollision"), 40 MIB_DESC(1, 0x18, "TxSingleCollision"), 41 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 42 MIB_DESC(1, 0x20, "TxDeferred"), 43 MIB_DESC(1, 0x24, "TxLateCollision"), 44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 45 MIB_DESC(1, 0x2c, "TxPause"), 46 MIB_DESC(1, 0x30, "TxPktSz64"), 47 MIB_DESC(1, 0x34, "TxPktSz65To127"), 48 MIB_DESC(1, 0x38, "TxPktSz128To255"), 49 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 50 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 51 MIB_DESC(1, 0x44, "Tx1024ToMax"), 52 MIB_DESC(2, 0x48, "TxBytes"), 53 MIB_DESC(1, 0x60, "RxDrop"), 54 MIB_DESC(1, 0x64, "RxFiltering"), 55 MIB_DESC(1, 0x68, "RxUnicast"), 56 MIB_DESC(1, 0x6c, "RxMulticast"), 57 MIB_DESC(1, 0x70, "RxBroadcast"), 58 MIB_DESC(1, 0x74, "RxAlignErr"), 59 MIB_DESC(1, 0x78, "RxCrcErr"), 60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 61 MIB_DESC(1, 0x80, "RxFragErr"), 62 MIB_DESC(1, 0x84, "RxOverSzErr"), 63 MIB_DESC(1, 0x88, "RxJabberErr"), 64 MIB_DESC(1, 0x8c, "RxPause"), 65 MIB_DESC(1, 0x90, "RxPktSz64"), 66 MIB_DESC(1, 0x94, "RxPktSz65To127"), 67 MIB_DESC(1, 0x98, "RxPktSz128To255"), 68 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 71 MIB_DESC(2, 0xa8, "RxBytes"), 72 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 73 MIB_DESC(1, 0xb4, "RxIngressDrop"), 74 MIB_DESC(1, 0xb8, "RxArlDrop"), 75 }; 76 77 /* Since phy_device has not yet been created and 78 * phy_{read,write}_mmd_indirect is not available, we provide our own 79 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 80 * to complete this function. 81 */ 82 static int 83 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 84 { 85 struct mii_bus *bus = priv->bus; 86 int value, ret; 87 88 /* Write the desired MMD Devad */ 89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 90 if (ret < 0) 91 goto err; 92 93 /* Write the desired MMD register address */ 94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 95 if (ret < 0) 96 goto err; 97 98 /* Select the Function : DATA with no post increment */ 99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 100 if (ret < 0) 101 goto err; 102 103 /* Read the content of the MMD's selected register */ 104 value = bus->read(bus, 0, MII_MMD_DATA); 105 106 return value; 107 err: 108 dev_err(&bus->dev, "failed to read mmd register\n"); 109 110 return ret; 111 } 112 113 static int 114 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 115 int devad, u32 data) 116 { 117 struct mii_bus *bus = priv->bus; 118 int ret; 119 120 /* Write the desired MMD Devad */ 121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 122 if (ret < 0) 123 goto err; 124 125 /* Write the desired MMD register address */ 126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 127 if (ret < 0) 128 goto err; 129 130 /* Select the Function : DATA with no post increment */ 131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 132 if (ret < 0) 133 goto err; 134 135 /* Write the data into MMD's selected register */ 136 ret = bus->write(bus, 0, MII_MMD_DATA, data); 137 err: 138 if (ret < 0) 139 dev_err(&bus->dev, 140 "failed to write mmd register\n"); 141 return ret; 142 } 143 144 static void 145 mt7530_mutex_lock(struct mt7530_priv *priv) 146 { 147 if (priv->bus) 148 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 149 } 150 151 static void 152 mt7530_mutex_unlock(struct mt7530_priv *priv) 153 { 154 if (priv->bus) 155 mutex_unlock(&priv->bus->mdio_lock); 156 } 157 158 static void 159 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 160 { 161 mt7530_mutex_lock(priv); 162 163 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 164 165 mt7530_mutex_unlock(priv); 166 } 167 168 static void 169 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 170 { 171 u32 val; 172 173 mt7530_mutex_lock(priv); 174 175 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 176 val &= ~mask; 177 val |= set; 178 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 179 180 mt7530_mutex_unlock(priv); 181 } 182 183 static void 184 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 185 { 186 core_rmw(priv, reg, 0, val); 187 } 188 189 static void 190 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 191 { 192 core_rmw(priv, reg, val, 0); 193 } 194 195 static int 196 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 197 { 198 int ret; 199 200 ret = regmap_write(priv->regmap, reg, val); 201 202 if (ret < 0) 203 dev_err(priv->dev, 204 "failed to write mt7530 register\n"); 205 206 return ret; 207 } 208 209 static u32 210 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 211 { 212 int ret; 213 u32 val; 214 215 ret = regmap_read(priv->regmap, reg, &val); 216 if (ret) { 217 WARN_ON_ONCE(1); 218 dev_err(priv->dev, 219 "failed to read mt7530 register\n"); 220 return 0; 221 } 222 223 return val; 224 } 225 226 static void 227 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 228 { 229 mt7530_mutex_lock(priv); 230 231 mt7530_mii_write(priv, reg, val); 232 233 mt7530_mutex_unlock(priv); 234 } 235 236 static u32 237 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 238 { 239 return mt7530_mii_read(p->priv, p->reg); 240 } 241 242 static u32 243 _mt7530_read(struct mt7530_dummy_poll *p) 244 { 245 u32 val; 246 247 mt7530_mutex_lock(p->priv); 248 249 val = mt7530_mii_read(p->priv, p->reg); 250 251 mt7530_mutex_unlock(p->priv); 252 253 return val; 254 } 255 256 static u32 257 mt7530_read(struct mt7530_priv *priv, u32 reg) 258 { 259 struct mt7530_dummy_poll p; 260 261 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 262 return _mt7530_read(&p); 263 } 264 265 static void 266 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 267 u32 mask, u32 set) 268 { 269 mt7530_mutex_lock(priv); 270 271 regmap_update_bits(priv->regmap, reg, mask, set); 272 273 mt7530_mutex_unlock(priv); 274 } 275 276 static void 277 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 278 { 279 mt7530_rmw(priv, reg, val, val); 280 } 281 282 static void 283 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 284 { 285 mt7530_rmw(priv, reg, val, 0); 286 } 287 288 static int 289 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 290 { 291 u32 val; 292 int ret; 293 struct mt7530_dummy_poll p; 294 295 /* Set the command operating upon the MAC address entries */ 296 val = ATC_BUSY | ATC_MAT(0) | cmd; 297 mt7530_write(priv, MT7530_ATC, val); 298 299 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 300 ret = readx_poll_timeout(_mt7530_read, &p, val, 301 !(val & ATC_BUSY), 20, 20000); 302 if (ret < 0) { 303 dev_err(priv->dev, "reset timeout\n"); 304 return ret; 305 } 306 307 /* Additional sanity for read command if the specified 308 * entry is invalid 309 */ 310 val = mt7530_read(priv, MT7530_ATC); 311 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 312 return -EINVAL; 313 314 if (rsp) 315 *rsp = val; 316 317 return 0; 318 } 319 320 static void 321 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 322 { 323 u32 reg[3]; 324 int i; 325 326 /* Read from ARL table into an array */ 327 for (i = 0; i < 3; i++) { 328 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 329 330 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 331 __func__, __LINE__, i, reg[i]); 332 } 333 334 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 335 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 336 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 337 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 338 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 339 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 340 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 341 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 342 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 343 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 344 } 345 346 static void 347 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 348 u8 port_mask, const u8 *mac, 349 u8 aging, u8 type) 350 { 351 u32 reg[3] = { 0 }; 352 int i; 353 354 reg[1] |= vid & CVID_MASK; 355 reg[1] |= ATA2_IVL; 356 reg[1] |= ATA2_FID(FID_BRIDGED); 357 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 358 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 359 /* STATIC_ENT indicate that entry is static wouldn't 360 * be aged out and STATIC_EMP specified as erasing an 361 * entry 362 */ 363 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 364 reg[1] |= mac[5] << MAC_BYTE_5; 365 reg[1] |= mac[4] << MAC_BYTE_4; 366 reg[0] |= mac[3] << MAC_BYTE_3; 367 reg[0] |= mac[2] << MAC_BYTE_2; 368 reg[0] |= mac[1] << MAC_BYTE_1; 369 reg[0] |= mac[0] << MAC_BYTE_0; 370 371 /* Write array into the ARL table */ 372 for (i = 0; i < 3; i++) 373 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 374 } 375 376 /* Set up switch core clock for MT7530 */ 377 static void mt7530_pll_setup(struct mt7530_priv *priv) 378 { 379 /* Disable core clock */ 380 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 381 382 /* Disable PLL */ 383 core_write(priv, CORE_GSWPLL_GRP1, 0); 384 385 /* Set core clock into 500Mhz */ 386 core_write(priv, CORE_GSWPLL_GRP2, 387 RG_GSWPLL_POSDIV_500M(1) | 388 RG_GSWPLL_FBKDIV_500M(25)); 389 390 /* Enable PLL */ 391 core_write(priv, CORE_GSWPLL_GRP1, 392 RG_GSWPLL_EN_PRE | 393 RG_GSWPLL_POSDIV_200M(2) | 394 RG_GSWPLL_FBKDIV_200M(32)); 395 396 udelay(20); 397 398 /* Enable core clock */ 399 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 400 } 401 402 /* If port 6 is available as a CPU port, always prefer that as the default, 403 * otherwise don't care. 404 */ 405 static struct dsa_port * 406 mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) 407 { 408 struct dsa_port *cpu_dp = dsa_to_port(ds, 6); 409 410 if (dsa_port_is_cpu(cpu_dp)) 411 return cpu_dp; 412 413 return NULL; 414 } 415 416 /* Setup port 6 interface mode and TRGMII TX circuit */ 417 static void 418 mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) 419 { 420 struct mt7530_priv *priv = ds->priv; 421 u32 ncpo1, ssc_delta, xtal; 422 423 /* Disable the MT7530 TRGMII clocks */ 424 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 425 426 if (interface == PHY_INTERFACE_MODE_RGMII) { 427 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 428 P6_INTF_MODE(0)); 429 return; 430 } 431 432 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1)); 433 434 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 435 436 if (xtal == HWTRAP_XTAL_25MHZ) 437 ssc_delta = 0x57; 438 else 439 ssc_delta = 0x87; 440 441 if (priv->id == ID_MT7621) { 442 /* PLL frequency: 125MHz: 1.0GBit */ 443 if (xtal == HWTRAP_XTAL_40MHZ) 444 ncpo1 = 0x0640; 445 if (xtal == HWTRAP_XTAL_25MHZ) 446 ncpo1 = 0x0a00; 447 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 448 if (xtal == HWTRAP_XTAL_40MHZ) 449 ncpo1 = 0x0c80; 450 if (xtal == HWTRAP_XTAL_25MHZ) 451 ncpo1 = 0x1400; 452 } 453 454 /* Setup the MT7530 TRGMII Tx Clock */ 455 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 456 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 457 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 458 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 459 core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | 460 RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); 461 core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL | 462 RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1)); 463 core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG | 464 RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 465 466 /* Enable the MT7530 TRGMII clocks */ 467 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 468 } 469 470 static void 471 mt7531_pll_setup(struct mt7530_priv *priv) 472 { 473 u32 top_sig; 474 u32 hwstrap; 475 u32 xtal; 476 u32 val; 477 478 val = mt7530_read(priv, MT7531_CREV); 479 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 480 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 481 if ((val & CHIP_REV_M) > 0) 482 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 483 HWTRAP_XTAL_FSEL_25MHZ; 484 else 485 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 486 487 /* Step 1 : Disable MT7531 COREPLL */ 488 val = mt7530_read(priv, MT7531_PLLGP_EN); 489 val &= ~EN_COREPLL; 490 mt7530_write(priv, MT7531_PLLGP_EN, val); 491 492 /* Step 2: switch to XTAL output */ 493 val = mt7530_read(priv, MT7531_PLLGP_EN); 494 val |= SW_CLKSW; 495 mt7530_write(priv, MT7531_PLLGP_EN, val); 496 497 val = mt7530_read(priv, MT7531_PLLGP_CR0); 498 val &= ~RG_COREPLL_EN; 499 mt7530_write(priv, MT7531_PLLGP_CR0, val); 500 501 /* Step 3: disable PLLGP and enable program PLLGP */ 502 val = mt7530_read(priv, MT7531_PLLGP_EN); 503 val |= SW_PLLGP; 504 mt7530_write(priv, MT7531_PLLGP_EN, val); 505 506 /* Step 4: program COREPLL output frequency to 500MHz */ 507 val = mt7530_read(priv, MT7531_PLLGP_CR0); 508 val &= ~RG_COREPLL_POSDIV_M; 509 val |= 2 << RG_COREPLL_POSDIV_S; 510 mt7530_write(priv, MT7531_PLLGP_CR0, val); 511 usleep_range(25, 35); 512 513 switch (xtal) { 514 case HWTRAP_XTAL_FSEL_25MHZ: 515 val = mt7530_read(priv, MT7531_PLLGP_CR0); 516 val &= ~RG_COREPLL_SDM_PCW_M; 517 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 518 mt7530_write(priv, MT7531_PLLGP_CR0, val); 519 break; 520 case HWTRAP_XTAL_FSEL_40MHZ: 521 val = mt7530_read(priv, MT7531_PLLGP_CR0); 522 val &= ~RG_COREPLL_SDM_PCW_M; 523 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 524 mt7530_write(priv, MT7531_PLLGP_CR0, val); 525 break; 526 } 527 528 /* Set feedback divide ratio update signal to high */ 529 val = mt7530_read(priv, MT7531_PLLGP_CR0); 530 val |= RG_COREPLL_SDM_PCW_CHG; 531 mt7530_write(priv, MT7531_PLLGP_CR0, val); 532 /* Wait for at least 16 XTAL clocks */ 533 usleep_range(10, 20); 534 535 /* Step 5: set feedback divide ratio update signal to low */ 536 val = mt7530_read(priv, MT7531_PLLGP_CR0); 537 val &= ~RG_COREPLL_SDM_PCW_CHG; 538 mt7530_write(priv, MT7531_PLLGP_CR0, val); 539 540 /* Enable 325M clock for SGMII */ 541 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 542 543 /* Enable 250SSC clock for RGMII */ 544 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 545 546 /* Step 6: Enable MT7531 PLL */ 547 val = mt7530_read(priv, MT7531_PLLGP_CR0); 548 val |= RG_COREPLL_EN; 549 mt7530_write(priv, MT7531_PLLGP_CR0, val); 550 551 val = mt7530_read(priv, MT7531_PLLGP_EN); 552 val |= EN_COREPLL; 553 mt7530_write(priv, MT7531_PLLGP_EN, val); 554 usleep_range(25, 35); 555 } 556 557 static void 558 mt7530_mib_reset(struct dsa_switch *ds) 559 { 560 struct mt7530_priv *priv = ds->priv; 561 562 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 563 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 564 } 565 566 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 567 { 568 return mdiobus_read_nested(priv->bus, port, regnum); 569 } 570 571 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 572 u16 val) 573 { 574 return mdiobus_write_nested(priv->bus, port, regnum, val); 575 } 576 577 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 578 int devad, int regnum) 579 { 580 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 581 } 582 583 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 584 int regnum, u16 val) 585 { 586 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 587 } 588 589 static int 590 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 591 int regnum) 592 { 593 struct mt7530_dummy_poll p; 594 u32 reg, val; 595 int ret; 596 597 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 598 599 mt7530_mutex_lock(priv); 600 601 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 602 !(val & MT7531_PHY_ACS_ST), 20, 100000); 603 if (ret < 0) { 604 dev_err(priv->dev, "poll timeout\n"); 605 goto out; 606 } 607 608 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 609 MT7531_MDIO_DEV_ADDR(devad) | regnum; 610 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 611 612 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 613 !(val & MT7531_PHY_ACS_ST), 20, 100000); 614 if (ret < 0) { 615 dev_err(priv->dev, "poll timeout\n"); 616 goto out; 617 } 618 619 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 620 MT7531_MDIO_DEV_ADDR(devad); 621 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 622 623 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 624 !(val & MT7531_PHY_ACS_ST), 20, 100000); 625 if (ret < 0) { 626 dev_err(priv->dev, "poll timeout\n"); 627 goto out; 628 } 629 630 ret = val & MT7531_MDIO_RW_DATA_MASK; 631 out: 632 mt7530_mutex_unlock(priv); 633 634 return ret; 635 } 636 637 static int 638 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 639 int regnum, u16 data) 640 { 641 struct mt7530_dummy_poll p; 642 u32 val, reg; 643 int ret; 644 645 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 646 647 mt7530_mutex_lock(priv); 648 649 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 650 !(val & MT7531_PHY_ACS_ST), 20, 100000); 651 if (ret < 0) { 652 dev_err(priv->dev, "poll timeout\n"); 653 goto out; 654 } 655 656 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 657 MT7531_MDIO_DEV_ADDR(devad) | regnum; 658 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 659 660 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 661 !(val & MT7531_PHY_ACS_ST), 20, 100000); 662 if (ret < 0) { 663 dev_err(priv->dev, "poll timeout\n"); 664 goto out; 665 } 666 667 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 668 MT7531_MDIO_DEV_ADDR(devad) | data; 669 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 670 671 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 672 !(val & MT7531_PHY_ACS_ST), 20, 100000); 673 if (ret < 0) { 674 dev_err(priv->dev, "poll timeout\n"); 675 goto out; 676 } 677 678 out: 679 mt7530_mutex_unlock(priv); 680 681 return ret; 682 } 683 684 static int 685 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 686 { 687 struct mt7530_dummy_poll p; 688 int ret; 689 u32 val; 690 691 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 692 693 mt7530_mutex_lock(priv); 694 695 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 696 !(val & MT7531_PHY_ACS_ST), 20, 100000); 697 if (ret < 0) { 698 dev_err(priv->dev, "poll timeout\n"); 699 goto out; 700 } 701 702 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 703 MT7531_MDIO_REG_ADDR(regnum); 704 705 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 706 707 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 708 !(val & MT7531_PHY_ACS_ST), 20, 100000); 709 if (ret < 0) { 710 dev_err(priv->dev, "poll timeout\n"); 711 goto out; 712 } 713 714 ret = val & MT7531_MDIO_RW_DATA_MASK; 715 out: 716 mt7530_mutex_unlock(priv); 717 718 return ret; 719 } 720 721 static int 722 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 723 u16 data) 724 { 725 struct mt7530_dummy_poll p; 726 int ret; 727 u32 reg; 728 729 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 730 731 mt7530_mutex_lock(priv); 732 733 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 734 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 735 if (ret < 0) { 736 dev_err(priv->dev, "poll timeout\n"); 737 goto out; 738 } 739 740 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 741 MT7531_MDIO_REG_ADDR(regnum) | data; 742 743 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 744 745 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 746 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 747 if (ret < 0) { 748 dev_err(priv->dev, "poll timeout\n"); 749 goto out; 750 } 751 752 out: 753 mt7530_mutex_unlock(priv); 754 755 return ret; 756 } 757 758 static int 759 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 760 { 761 struct mt7530_priv *priv = bus->priv; 762 763 return priv->info->phy_read_c22(priv, port, regnum); 764 } 765 766 static int 767 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 768 { 769 struct mt7530_priv *priv = bus->priv; 770 771 return priv->info->phy_read_c45(priv, port, devad, regnum); 772 } 773 774 static int 775 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 776 { 777 struct mt7530_priv *priv = bus->priv; 778 779 return priv->info->phy_write_c22(priv, port, regnum, val); 780 } 781 782 static int 783 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 784 u16 val) 785 { 786 struct mt7530_priv *priv = bus->priv; 787 788 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 789 } 790 791 static void 792 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 793 uint8_t *data) 794 { 795 int i; 796 797 if (stringset != ETH_SS_STATS) 798 return; 799 800 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 801 ethtool_puts(&data, mt7530_mib[i].name); 802 } 803 804 static void 805 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 806 uint64_t *data) 807 { 808 struct mt7530_priv *priv = ds->priv; 809 const struct mt7530_mib_desc *mib; 810 u32 reg, i; 811 u64 hi; 812 813 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 814 mib = &mt7530_mib[i]; 815 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 816 817 data[i] = mt7530_read(priv, reg); 818 if (mib->size == 2) { 819 hi = mt7530_read(priv, reg + 4); 820 data[i] |= hi << 32; 821 } 822 } 823 } 824 825 static int 826 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 827 { 828 if (sset != ETH_SS_STATS) 829 return 0; 830 831 return ARRAY_SIZE(mt7530_mib); 832 } 833 834 static int 835 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 836 { 837 struct mt7530_priv *priv = ds->priv; 838 unsigned int secs = msecs / 1000; 839 unsigned int tmp_age_count; 840 unsigned int error = -1; 841 unsigned int age_count; 842 unsigned int age_unit; 843 844 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 845 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 846 return -ERANGE; 847 848 /* iterate through all possible age_count to find the closest pair */ 849 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 850 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 851 852 if (tmp_age_unit <= AGE_UNIT_MAX) { 853 unsigned int tmp_error = secs - 854 (tmp_age_count + 1) * (tmp_age_unit + 1); 855 856 /* found a closer pair */ 857 if (error > tmp_error) { 858 error = tmp_error; 859 age_count = tmp_age_count; 860 age_unit = tmp_age_unit; 861 } 862 863 /* found the exact match, so break the loop */ 864 if (!error) 865 break; 866 } 867 } 868 869 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 870 871 return 0; 872 } 873 874 static const char *p5_intf_modes(unsigned int p5_interface) 875 { 876 switch (p5_interface) { 877 case P5_DISABLED: 878 return "DISABLED"; 879 case P5_INTF_SEL_PHY_P0: 880 return "PHY P0"; 881 case P5_INTF_SEL_PHY_P4: 882 return "PHY P4"; 883 case P5_INTF_SEL_GMAC5: 884 return "GMAC5"; 885 default: 886 return "unknown"; 887 } 888 } 889 890 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 891 { 892 struct mt7530_priv *priv = ds->priv; 893 u8 tx_delay = 0; 894 int val; 895 896 mutex_lock(&priv->reg_mutex); 897 898 val = mt7530_read(priv, MT7530_MHWTRAP); 899 900 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 901 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 902 903 switch (priv->p5_intf_sel) { 904 case P5_INTF_SEL_PHY_P0: 905 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 906 val |= MHWTRAP_PHY0_SEL; 907 fallthrough; 908 case P5_INTF_SEL_PHY_P4: 909 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 910 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 911 912 /* Setup the MAC by default for the cpu port */ 913 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 914 break; 915 case P5_INTF_SEL_GMAC5: 916 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 917 val &= ~MHWTRAP_P5_DIS; 918 break; 919 default: 920 break; 921 } 922 923 /* Setup RGMII settings */ 924 if (phy_interface_mode_is_rgmii(interface)) { 925 val |= MHWTRAP_P5_RGMII_MODE; 926 927 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 928 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 929 930 /* Don't set delay in DSA mode */ 931 if (!dsa_is_dsa_port(priv->ds, 5) && 932 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 933 interface == PHY_INTERFACE_MODE_RGMII_ID)) 934 tx_delay = 4; /* n * 0.5 ns */ 935 936 /* P5 RGMII TX Clock Control: delay x */ 937 mt7530_write(priv, MT7530_P5RGMIITXCR, 938 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 939 940 /* reduce P5 RGMII Tx driving, 8mA */ 941 mt7530_write(priv, MT7530_IO_DRV_CR, 942 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 943 } 944 945 mt7530_write(priv, MT7530_MHWTRAP, val); 946 947 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 948 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 949 950 mutex_unlock(&priv->reg_mutex); 951 } 952 953 static void 954 mt753x_trap_frames(struct mt7530_priv *priv) 955 { 956 /* Trap BPDUs to the CPU port(s) */ 957 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 958 MT753X_BPDU_CPU_ONLY); 959 960 /* Trap 802.1X PAE frames to the CPU port(s) */ 961 mt7530_rmw(priv, MT753X_BPC, MT753X_PAE_PORT_FW_MASK, 962 MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY)); 963 964 /* Trap LLDP frames with :0E MAC DA to the CPU port(s) */ 965 mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_PORT_FW_MASK, 966 MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY)); 967 } 968 969 static int 970 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 971 { 972 struct mt7530_priv *priv = ds->priv; 973 int ret; 974 975 /* Setup max capability of CPU port at first */ 976 if (priv->info->cpu_port_config) { 977 ret = priv->info->cpu_port_config(ds, port); 978 if (ret) 979 return ret; 980 } 981 982 /* Enable Mediatek header mode on the cpu port */ 983 mt7530_write(priv, MT7530_PVC_P(port), 984 PORT_SPEC_TAG); 985 986 /* Enable flooding on the CPU port */ 987 mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | 988 UNU_FFP(BIT(port))); 989 990 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on 991 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that 992 * is affine to the inbound user port. 993 */ 994 if (priv->id == ID_MT7531 || priv->id == ID_MT7988) 995 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); 996 997 /* CPU port gets connected to all user ports of 998 * the switch. 999 */ 1000 mt7530_write(priv, MT7530_PCR_P(port), 1001 PCR_MATRIX(dsa_user_ports(priv->ds))); 1002 1003 /* Set to fallback mode for independent VLAN learning */ 1004 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1005 MT7530_PORT_FALLBACK_MODE); 1006 1007 return 0; 1008 } 1009 1010 static int 1011 mt7530_port_enable(struct dsa_switch *ds, int port, 1012 struct phy_device *phy) 1013 { 1014 struct dsa_port *dp = dsa_to_port(ds, port); 1015 struct mt7530_priv *priv = ds->priv; 1016 1017 mutex_lock(&priv->reg_mutex); 1018 1019 /* Allow the user port gets connected to the cpu port and also 1020 * restore the port matrix if the port is the member of a certain 1021 * bridge. 1022 */ 1023 if (dsa_port_is_user(dp)) { 1024 struct dsa_port *cpu_dp = dp->cpu_dp; 1025 1026 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1027 } 1028 priv->ports[port].enable = true; 1029 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1030 priv->ports[port].pm); 1031 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1032 1033 mutex_unlock(&priv->reg_mutex); 1034 1035 return 0; 1036 } 1037 1038 static void 1039 mt7530_port_disable(struct dsa_switch *ds, int port) 1040 { 1041 struct mt7530_priv *priv = ds->priv; 1042 1043 mutex_lock(&priv->reg_mutex); 1044 1045 /* Clear up all port matrix which could be restored in the next 1046 * enablement for the port. 1047 */ 1048 priv->ports[port].enable = false; 1049 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1050 PCR_MATRIX_CLR); 1051 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1052 1053 mutex_unlock(&priv->reg_mutex); 1054 } 1055 1056 static int 1057 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1058 { 1059 struct mt7530_priv *priv = ds->priv; 1060 int length; 1061 u32 val; 1062 1063 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1064 * largest MTU of the user ports. Because the switch only has a global 1065 * RX length register, only allowing CPU port here is enough. 1066 */ 1067 if (!dsa_is_cpu_port(ds, port)) 1068 return 0; 1069 1070 mt7530_mutex_lock(priv); 1071 1072 val = mt7530_mii_read(priv, MT7530_GMACCR); 1073 val &= ~MAX_RX_PKT_LEN_MASK; 1074 1075 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1076 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1077 if (length <= 1522) { 1078 val |= MAX_RX_PKT_LEN_1522; 1079 } else if (length <= 1536) { 1080 val |= MAX_RX_PKT_LEN_1536; 1081 } else if (length <= 1552) { 1082 val |= MAX_RX_PKT_LEN_1552; 1083 } else { 1084 val &= ~MAX_RX_JUMBO_MASK; 1085 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1086 val |= MAX_RX_PKT_LEN_JUMBO; 1087 } 1088 1089 mt7530_mii_write(priv, MT7530_GMACCR, val); 1090 1091 mt7530_mutex_unlock(priv); 1092 1093 return 0; 1094 } 1095 1096 static int 1097 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1098 { 1099 return MT7530_MAX_MTU; 1100 } 1101 1102 static void 1103 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1104 { 1105 struct mt7530_priv *priv = ds->priv; 1106 u32 stp_state; 1107 1108 switch (state) { 1109 case BR_STATE_DISABLED: 1110 stp_state = MT7530_STP_DISABLED; 1111 break; 1112 case BR_STATE_BLOCKING: 1113 stp_state = MT7530_STP_BLOCKING; 1114 break; 1115 case BR_STATE_LISTENING: 1116 stp_state = MT7530_STP_LISTENING; 1117 break; 1118 case BR_STATE_LEARNING: 1119 stp_state = MT7530_STP_LEARNING; 1120 break; 1121 case BR_STATE_FORWARDING: 1122 default: 1123 stp_state = MT7530_STP_FORWARDING; 1124 break; 1125 } 1126 1127 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1128 FID_PST(FID_BRIDGED, stp_state)); 1129 } 1130 1131 static int 1132 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1133 struct switchdev_brport_flags flags, 1134 struct netlink_ext_ack *extack) 1135 { 1136 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1137 BR_BCAST_FLOOD)) 1138 return -EINVAL; 1139 1140 return 0; 1141 } 1142 1143 static int 1144 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1145 struct switchdev_brport_flags flags, 1146 struct netlink_ext_ack *extack) 1147 { 1148 struct mt7530_priv *priv = ds->priv; 1149 1150 if (flags.mask & BR_LEARNING) 1151 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1152 flags.val & BR_LEARNING ? 0 : SA_DIS); 1153 1154 if (flags.mask & BR_FLOOD) 1155 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1156 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1157 1158 if (flags.mask & BR_MCAST_FLOOD) 1159 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1160 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1161 1162 if (flags.mask & BR_BCAST_FLOOD) 1163 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1164 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1165 1166 return 0; 1167 } 1168 1169 static int 1170 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1171 struct dsa_bridge bridge, bool *tx_fwd_offload, 1172 struct netlink_ext_ack *extack) 1173 { 1174 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1175 struct dsa_port *cpu_dp = dp->cpu_dp; 1176 u32 port_bitmap = BIT(cpu_dp->index); 1177 struct mt7530_priv *priv = ds->priv; 1178 1179 mutex_lock(&priv->reg_mutex); 1180 1181 dsa_switch_for_each_user_port(other_dp, ds) { 1182 int other_port = other_dp->index; 1183 1184 if (dp == other_dp) 1185 continue; 1186 1187 /* Add this port to the port matrix of the other ports in the 1188 * same bridge. If the port is disabled, port matrix is kept 1189 * and not being setup until the port becomes enabled. 1190 */ 1191 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1192 continue; 1193 1194 if (priv->ports[other_port].enable) 1195 mt7530_set(priv, MT7530_PCR_P(other_port), 1196 PCR_MATRIX(BIT(port))); 1197 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); 1198 1199 port_bitmap |= BIT(other_port); 1200 } 1201 1202 /* Add the all other ports to this port matrix. */ 1203 if (priv->ports[port].enable) 1204 mt7530_rmw(priv, MT7530_PCR_P(port), 1205 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1206 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1207 1208 /* Set to fallback mode for independent VLAN learning */ 1209 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1210 MT7530_PORT_FALLBACK_MODE); 1211 1212 mutex_unlock(&priv->reg_mutex); 1213 1214 return 0; 1215 } 1216 1217 static void 1218 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1219 { 1220 struct mt7530_priv *priv = ds->priv; 1221 bool all_user_ports_removed = true; 1222 int i; 1223 1224 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1225 * bridge. Don't set standalone ports to fallback mode. 1226 */ 1227 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1228 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1229 MT7530_PORT_FALLBACK_MODE); 1230 1231 mt7530_rmw(priv, MT7530_PVC_P(port), 1232 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1233 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1234 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1235 MT7530_VLAN_ACC_ALL); 1236 1237 /* Set PVID to 0 */ 1238 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1239 G0_PORT_VID_DEF); 1240 1241 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1242 if (dsa_is_user_port(ds, i) && 1243 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1244 all_user_ports_removed = false; 1245 break; 1246 } 1247 } 1248 1249 /* CPU port also does the same thing until all user ports belonging to 1250 * the CPU port get out of VLAN filtering mode. 1251 */ 1252 if (all_user_ports_removed) { 1253 struct dsa_port *dp = dsa_to_port(ds, port); 1254 struct dsa_port *cpu_dp = dp->cpu_dp; 1255 1256 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1257 PCR_MATRIX(dsa_user_ports(priv->ds))); 1258 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1259 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1260 } 1261 } 1262 1263 static void 1264 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1265 { 1266 struct mt7530_priv *priv = ds->priv; 1267 1268 /* Trapped into security mode allows packet forwarding through VLAN 1269 * table lookup. 1270 */ 1271 if (dsa_is_user_port(ds, port)) { 1272 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1273 MT7530_PORT_SECURITY_MODE); 1274 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1275 G0_PORT_VID(priv->ports[port].pvid)); 1276 1277 /* Only accept tagged frames if PVID is not set */ 1278 if (!priv->ports[port].pvid) 1279 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1280 MT7530_VLAN_ACC_TAGGED); 1281 1282 /* Set the port as a user port which is to be able to recognize 1283 * VID from incoming packets before fetching entry within the 1284 * VLAN table. 1285 */ 1286 mt7530_rmw(priv, MT7530_PVC_P(port), 1287 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1288 VLAN_ATTR(MT7530_VLAN_USER) | 1289 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1290 } else { 1291 /* Also set CPU ports to the "user" VLAN port attribute, to 1292 * allow VLAN classification, but keep the EG_TAG attribute as 1293 * "consistent" (i.o.w. don't change its value) for packets 1294 * received by the switch from the CPU, so that tagged packets 1295 * are forwarded to user ports as tagged, and untagged as 1296 * untagged. 1297 */ 1298 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1299 VLAN_ATTR(MT7530_VLAN_USER)); 1300 } 1301 } 1302 1303 static void 1304 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1305 struct dsa_bridge bridge) 1306 { 1307 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1308 struct dsa_port *cpu_dp = dp->cpu_dp; 1309 struct mt7530_priv *priv = ds->priv; 1310 1311 mutex_lock(&priv->reg_mutex); 1312 1313 dsa_switch_for_each_user_port(other_dp, ds) { 1314 int other_port = other_dp->index; 1315 1316 if (dp == other_dp) 1317 continue; 1318 1319 /* Remove this port from the port matrix of the other ports 1320 * in the same bridge. If the port is disabled, port matrix 1321 * is kept and not being setup until the port becomes enabled. 1322 */ 1323 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1324 continue; 1325 1326 if (priv->ports[other_port].enable) 1327 mt7530_clear(priv, MT7530_PCR_P(other_port), 1328 PCR_MATRIX(BIT(port))); 1329 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); 1330 } 1331 1332 /* Set the cpu port to be the only one in the port matrix of 1333 * this port. 1334 */ 1335 if (priv->ports[port].enable) 1336 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1337 PCR_MATRIX(BIT(cpu_dp->index))); 1338 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); 1339 1340 /* When a port is removed from the bridge, the port would be set up 1341 * back to the default as is at initial boot which is a VLAN-unaware 1342 * port. 1343 */ 1344 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1345 MT7530_PORT_MATRIX_MODE); 1346 1347 mutex_unlock(&priv->reg_mutex); 1348 } 1349 1350 static int 1351 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1352 const unsigned char *addr, u16 vid, 1353 struct dsa_db db) 1354 { 1355 struct mt7530_priv *priv = ds->priv; 1356 int ret; 1357 u8 port_mask = BIT(port); 1358 1359 mutex_lock(&priv->reg_mutex); 1360 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1361 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1362 mutex_unlock(&priv->reg_mutex); 1363 1364 return ret; 1365 } 1366 1367 static int 1368 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1369 const unsigned char *addr, u16 vid, 1370 struct dsa_db db) 1371 { 1372 struct mt7530_priv *priv = ds->priv; 1373 int ret; 1374 u8 port_mask = BIT(port); 1375 1376 mutex_lock(&priv->reg_mutex); 1377 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1378 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1379 mutex_unlock(&priv->reg_mutex); 1380 1381 return ret; 1382 } 1383 1384 static int 1385 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1386 dsa_fdb_dump_cb_t *cb, void *data) 1387 { 1388 struct mt7530_priv *priv = ds->priv; 1389 struct mt7530_fdb _fdb = { 0 }; 1390 int cnt = MT7530_NUM_FDB_RECORDS; 1391 int ret = 0; 1392 u32 rsp = 0; 1393 1394 mutex_lock(&priv->reg_mutex); 1395 1396 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1397 if (ret < 0) 1398 goto err; 1399 1400 do { 1401 if (rsp & ATC_SRCH_HIT) { 1402 mt7530_fdb_read(priv, &_fdb); 1403 if (_fdb.port_mask & BIT(port)) { 1404 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1405 data); 1406 if (ret < 0) 1407 break; 1408 } 1409 } 1410 } while (--cnt && 1411 !(rsp & ATC_SRCH_END) && 1412 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1413 err: 1414 mutex_unlock(&priv->reg_mutex); 1415 1416 return 0; 1417 } 1418 1419 static int 1420 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1421 const struct switchdev_obj_port_mdb *mdb, 1422 struct dsa_db db) 1423 { 1424 struct mt7530_priv *priv = ds->priv; 1425 const u8 *addr = mdb->addr; 1426 u16 vid = mdb->vid; 1427 u8 port_mask = 0; 1428 int ret; 1429 1430 mutex_lock(&priv->reg_mutex); 1431 1432 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1433 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1434 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1435 & PORT_MAP_MASK; 1436 1437 port_mask |= BIT(port); 1438 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1439 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1440 1441 mutex_unlock(&priv->reg_mutex); 1442 1443 return ret; 1444 } 1445 1446 static int 1447 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1448 const struct switchdev_obj_port_mdb *mdb, 1449 struct dsa_db db) 1450 { 1451 struct mt7530_priv *priv = ds->priv; 1452 const u8 *addr = mdb->addr; 1453 u16 vid = mdb->vid; 1454 u8 port_mask = 0; 1455 int ret; 1456 1457 mutex_lock(&priv->reg_mutex); 1458 1459 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1460 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1461 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1462 & PORT_MAP_MASK; 1463 1464 port_mask &= ~BIT(port); 1465 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1466 port_mask ? STATIC_ENT : STATIC_EMP); 1467 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1468 1469 mutex_unlock(&priv->reg_mutex); 1470 1471 return ret; 1472 } 1473 1474 static int 1475 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1476 { 1477 struct mt7530_dummy_poll p; 1478 u32 val; 1479 int ret; 1480 1481 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1482 mt7530_write(priv, MT7530_VTCR, val); 1483 1484 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1485 ret = readx_poll_timeout(_mt7530_read, &p, val, 1486 !(val & VTCR_BUSY), 20, 20000); 1487 if (ret < 0) { 1488 dev_err(priv->dev, "poll timeout\n"); 1489 return ret; 1490 } 1491 1492 val = mt7530_read(priv, MT7530_VTCR); 1493 if (val & VTCR_INVALID) { 1494 dev_err(priv->dev, "read VTCR invalid\n"); 1495 return -EINVAL; 1496 } 1497 1498 return 0; 1499 } 1500 1501 static int 1502 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1503 struct netlink_ext_ack *extack) 1504 { 1505 struct dsa_port *dp = dsa_to_port(ds, port); 1506 struct dsa_port *cpu_dp = dp->cpu_dp; 1507 1508 if (vlan_filtering) { 1509 /* The port is being kept as VLAN-unaware port when bridge is 1510 * set up with vlan_filtering not being set, Otherwise, the 1511 * port and the corresponding CPU port is required the setup 1512 * for becoming a VLAN-aware port. 1513 */ 1514 mt7530_port_set_vlan_aware(ds, port); 1515 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1516 } else { 1517 mt7530_port_set_vlan_unaware(ds, port); 1518 } 1519 1520 return 0; 1521 } 1522 1523 static void 1524 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1525 struct mt7530_hw_vlan_entry *entry) 1526 { 1527 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1528 u8 new_members; 1529 u32 val; 1530 1531 new_members = entry->old_members | BIT(entry->port); 1532 1533 /* Validate the entry with independent learning, create egress tag per 1534 * VLAN and joining the port as one of the port members. 1535 */ 1536 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1537 VLAN_VALID; 1538 mt7530_write(priv, MT7530_VAWD1, val); 1539 1540 /* Decide whether adding tag or not for those outgoing packets from the 1541 * port inside the VLAN. 1542 * CPU port is always taken as a tagged port for serving more than one 1543 * VLANs across and also being applied with egress type stack mode for 1544 * that VLAN tags would be appended after hardware special tag used as 1545 * DSA tag. 1546 */ 1547 if (dsa_port_is_cpu(dp)) 1548 val = MT7530_VLAN_EGRESS_STACK; 1549 else if (entry->untagged) 1550 val = MT7530_VLAN_EGRESS_UNTAG; 1551 else 1552 val = MT7530_VLAN_EGRESS_TAG; 1553 mt7530_rmw(priv, MT7530_VAWD2, 1554 ETAG_CTRL_P_MASK(entry->port), 1555 ETAG_CTRL_P(entry->port, val)); 1556 } 1557 1558 static void 1559 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1560 struct mt7530_hw_vlan_entry *entry) 1561 { 1562 u8 new_members; 1563 u32 val; 1564 1565 new_members = entry->old_members & ~BIT(entry->port); 1566 1567 val = mt7530_read(priv, MT7530_VAWD1); 1568 if (!(val & VLAN_VALID)) { 1569 dev_err(priv->dev, 1570 "Cannot be deleted due to invalid entry\n"); 1571 return; 1572 } 1573 1574 if (new_members) { 1575 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1576 VLAN_VALID; 1577 mt7530_write(priv, MT7530_VAWD1, val); 1578 } else { 1579 mt7530_write(priv, MT7530_VAWD1, 0); 1580 mt7530_write(priv, MT7530_VAWD2, 0); 1581 } 1582 } 1583 1584 static void 1585 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1586 struct mt7530_hw_vlan_entry *entry, 1587 mt7530_vlan_op vlan_op) 1588 { 1589 u32 val; 1590 1591 /* Fetch entry */ 1592 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1593 1594 val = mt7530_read(priv, MT7530_VAWD1); 1595 1596 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1597 1598 /* Manipulate entry */ 1599 vlan_op(priv, entry); 1600 1601 /* Flush result to hardware */ 1602 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1603 } 1604 1605 static int 1606 mt7530_setup_vlan0(struct mt7530_priv *priv) 1607 { 1608 u32 val; 1609 1610 /* Validate the entry with independent learning, keep the original 1611 * ingress tag attribute. 1612 */ 1613 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1614 VLAN_VALID; 1615 mt7530_write(priv, MT7530_VAWD1, val); 1616 1617 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1618 } 1619 1620 static int 1621 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1622 const struct switchdev_obj_port_vlan *vlan, 1623 struct netlink_ext_ack *extack) 1624 { 1625 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1626 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1627 struct mt7530_hw_vlan_entry new_entry; 1628 struct mt7530_priv *priv = ds->priv; 1629 1630 mutex_lock(&priv->reg_mutex); 1631 1632 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1633 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1634 1635 if (pvid) { 1636 priv->ports[port].pvid = vlan->vid; 1637 1638 /* Accept all frames if PVID is set */ 1639 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1640 MT7530_VLAN_ACC_ALL); 1641 1642 /* Only configure PVID if VLAN filtering is enabled */ 1643 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1644 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1645 G0_PORT_VID_MASK, 1646 G0_PORT_VID(vlan->vid)); 1647 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1648 /* This VLAN is overwritten without PVID, so unset it */ 1649 priv->ports[port].pvid = G0_PORT_VID_DEF; 1650 1651 /* Only accept tagged frames if the port is VLAN-aware */ 1652 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1653 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1654 MT7530_VLAN_ACC_TAGGED); 1655 1656 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1657 G0_PORT_VID_DEF); 1658 } 1659 1660 mutex_unlock(&priv->reg_mutex); 1661 1662 return 0; 1663 } 1664 1665 static int 1666 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1667 const struct switchdev_obj_port_vlan *vlan) 1668 { 1669 struct mt7530_hw_vlan_entry target_entry; 1670 struct mt7530_priv *priv = ds->priv; 1671 1672 mutex_lock(&priv->reg_mutex); 1673 1674 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1675 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1676 mt7530_hw_vlan_del); 1677 1678 /* PVID is being restored to the default whenever the PVID port 1679 * is being removed from the VLAN. 1680 */ 1681 if (priv->ports[port].pvid == vlan->vid) { 1682 priv->ports[port].pvid = G0_PORT_VID_DEF; 1683 1684 /* Only accept tagged frames if the port is VLAN-aware */ 1685 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1686 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1687 MT7530_VLAN_ACC_TAGGED); 1688 1689 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1690 G0_PORT_VID_DEF); 1691 } 1692 1693 1694 mutex_unlock(&priv->reg_mutex); 1695 1696 return 0; 1697 } 1698 1699 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1700 { 1701 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1702 MIRROR_PORT(val); 1703 } 1704 1705 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1706 { 1707 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1708 MIRROR_PORT(val); 1709 } 1710 1711 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1712 struct dsa_mall_mirror_tc_entry *mirror, 1713 bool ingress, struct netlink_ext_ack *extack) 1714 { 1715 struct mt7530_priv *priv = ds->priv; 1716 int monitor_port; 1717 u32 val; 1718 1719 /* Check for existent entry */ 1720 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1721 return -EEXIST; 1722 1723 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1724 1725 /* MT7530 only supports one monitor port */ 1726 monitor_port = mt753x_mirror_port_get(priv->id, val); 1727 if (val & MT753X_MIRROR_EN(priv->id) && 1728 monitor_port != mirror->to_local_port) 1729 return -EEXIST; 1730 1731 val |= MT753X_MIRROR_EN(priv->id); 1732 val &= ~MT753X_MIRROR_MASK(priv->id); 1733 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1734 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1735 1736 val = mt7530_read(priv, MT7530_PCR_P(port)); 1737 if (ingress) { 1738 val |= PORT_RX_MIR; 1739 priv->mirror_rx |= BIT(port); 1740 } else { 1741 val |= PORT_TX_MIR; 1742 priv->mirror_tx |= BIT(port); 1743 } 1744 mt7530_write(priv, MT7530_PCR_P(port), val); 1745 1746 return 0; 1747 } 1748 1749 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1750 struct dsa_mall_mirror_tc_entry *mirror) 1751 { 1752 struct mt7530_priv *priv = ds->priv; 1753 u32 val; 1754 1755 val = mt7530_read(priv, MT7530_PCR_P(port)); 1756 if (mirror->ingress) { 1757 val &= ~PORT_RX_MIR; 1758 priv->mirror_rx &= ~BIT(port); 1759 } else { 1760 val &= ~PORT_TX_MIR; 1761 priv->mirror_tx &= ~BIT(port); 1762 } 1763 mt7530_write(priv, MT7530_PCR_P(port), val); 1764 1765 if (!priv->mirror_rx && !priv->mirror_tx) { 1766 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1767 val &= ~MT753X_MIRROR_EN(priv->id); 1768 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1769 } 1770 } 1771 1772 static enum dsa_tag_protocol 1773 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1774 enum dsa_tag_protocol mp) 1775 { 1776 return DSA_TAG_PROTO_MTK; 1777 } 1778 1779 #ifdef CONFIG_GPIOLIB 1780 static inline u32 1781 mt7530_gpio_to_bit(unsigned int offset) 1782 { 1783 /* Map GPIO offset to register bit 1784 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1785 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1786 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1787 * [14:12] port 3 LED 0..2 as GPIO 9..11 1788 * [18:16] port 4 LED 0..2 as GPIO 12..14 1789 */ 1790 return BIT(offset + offset / 3); 1791 } 1792 1793 static int 1794 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1795 { 1796 struct mt7530_priv *priv = gpiochip_get_data(gc); 1797 u32 bit = mt7530_gpio_to_bit(offset); 1798 1799 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1800 } 1801 1802 static void 1803 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1804 { 1805 struct mt7530_priv *priv = gpiochip_get_data(gc); 1806 u32 bit = mt7530_gpio_to_bit(offset); 1807 1808 if (value) 1809 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1810 else 1811 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1812 } 1813 1814 static int 1815 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1816 { 1817 struct mt7530_priv *priv = gpiochip_get_data(gc); 1818 u32 bit = mt7530_gpio_to_bit(offset); 1819 1820 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1821 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1822 } 1823 1824 static int 1825 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1826 { 1827 struct mt7530_priv *priv = gpiochip_get_data(gc); 1828 u32 bit = mt7530_gpio_to_bit(offset); 1829 1830 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1831 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1832 1833 return 0; 1834 } 1835 1836 static int 1837 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1838 { 1839 struct mt7530_priv *priv = gpiochip_get_data(gc); 1840 u32 bit = mt7530_gpio_to_bit(offset); 1841 1842 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1843 1844 if (value) 1845 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1846 else 1847 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1848 1849 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1850 1851 return 0; 1852 } 1853 1854 static int 1855 mt7530_setup_gpio(struct mt7530_priv *priv) 1856 { 1857 struct device *dev = priv->dev; 1858 struct gpio_chip *gc; 1859 1860 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1861 if (!gc) 1862 return -ENOMEM; 1863 1864 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1865 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1866 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1867 1868 gc->label = "mt7530"; 1869 gc->parent = dev; 1870 gc->owner = THIS_MODULE; 1871 gc->get_direction = mt7530_gpio_get_direction; 1872 gc->direction_input = mt7530_gpio_direction_input; 1873 gc->direction_output = mt7530_gpio_direction_output; 1874 gc->get = mt7530_gpio_get; 1875 gc->set = mt7530_gpio_set; 1876 gc->base = -1; 1877 gc->ngpio = 15; 1878 gc->can_sleep = true; 1879 1880 return devm_gpiochip_add_data(dev, gc, priv); 1881 } 1882 #endif /* CONFIG_GPIOLIB */ 1883 1884 static irqreturn_t 1885 mt7530_irq_thread_fn(int irq, void *dev_id) 1886 { 1887 struct mt7530_priv *priv = dev_id; 1888 bool handled = false; 1889 u32 val; 1890 int p; 1891 1892 mt7530_mutex_lock(priv); 1893 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1894 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1895 mt7530_mutex_unlock(priv); 1896 1897 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1898 if (BIT(p) & val) { 1899 unsigned int irq; 1900 1901 irq = irq_find_mapping(priv->irq_domain, p); 1902 handle_nested_irq(irq); 1903 handled = true; 1904 } 1905 } 1906 1907 return IRQ_RETVAL(handled); 1908 } 1909 1910 static void 1911 mt7530_irq_mask(struct irq_data *d) 1912 { 1913 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1914 1915 priv->irq_enable &= ~BIT(d->hwirq); 1916 } 1917 1918 static void 1919 mt7530_irq_unmask(struct irq_data *d) 1920 { 1921 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1922 1923 priv->irq_enable |= BIT(d->hwirq); 1924 } 1925 1926 static void 1927 mt7530_irq_bus_lock(struct irq_data *d) 1928 { 1929 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1930 1931 mt7530_mutex_lock(priv); 1932 } 1933 1934 static void 1935 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1936 { 1937 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1938 1939 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1940 mt7530_mutex_unlock(priv); 1941 } 1942 1943 static struct irq_chip mt7530_irq_chip = { 1944 .name = KBUILD_MODNAME, 1945 .irq_mask = mt7530_irq_mask, 1946 .irq_unmask = mt7530_irq_unmask, 1947 .irq_bus_lock = mt7530_irq_bus_lock, 1948 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 1949 }; 1950 1951 static int 1952 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 1953 irq_hw_number_t hwirq) 1954 { 1955 irq_set_chip_data(irq, domain->host_data); 1956 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 1957 irq_set_nested_thread(irq, true); 1958 irq_set_noprobe(irq); 1959 1960 return 0; 1961 } 1962 1963 static const struct irq_domain_ops mt7530_irq_domain_ops = { 1964 .map = mt7530_irq_map, 1965 .xlate = irq_domain_xlate_onecell, 1966 }; 1967 1968 static void 1969 mt7988_irq_mask(struct irq_data *d) 1970 { 1971 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1972 1973 priv->irq_enable &= ~BIT(d->hwirq); 1974 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1975 } 1976 1977 static void 1978 mt7988_irq_unmask(struct irq_data *d) 1979 { 1980 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1981 1982 priv->irq_enable |= BIT(d->hwirq); 1983 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1984 } 1985 1986 static struct irq_chip mt7988_irq_chip = { 1987 .name = KBUILD_MODNAME, 1988 .irq_mask = mt7988_irq_mask, 1989 .irq_unmask = mt7988_irq_unmask, 1990 }; 1991 1992 static int 1993 mt7988_irq_map(struct irq_domain *domain, unsigned int irq, 1994 irq_hw_number_t hwirq) 1995 { 1996 irq_set_chip_data(irq, domain->host_data); 1997 irq_set_chip_and_handler(irq, &mt7988_irq_chip, handle_simple_irq); 1998 irq_set_nested_thread(irq, true); 1999 irq_set_noprobe(irq); 2000 2001 return 0; 2002 } 2003 2004 static const struct irq_domain_ops mt7988_irq_domain_ops = { 2005 .map = mt7988_irq_map, 2006 .xlate = irq_domain_xlate_onecell, 2007 }; 2008 2009 static void 2010 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 2011 { 2012 struct dsa_switch *ds = priv->ds; 2013 int p; 2014 2015 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2016 if (BIT(p) & ds->phys_mii_mask) { 2017 unsigned int irq; 2018 2019 irq = irq_create_mapping(priv->irq_domain, p); 2020 ds->user_mii_bus->irq[p] = irq; 2021 } 2022 } 2023 } 2024 2025 static int 2026 mt7530_setup_irq(struct mt7530_priv *priv) 2027 { 2028 struct device *dev = priv->dev; 2029 struct device_node *np = dev->of_node; 2030 int ret; 2031 2032 if (!of_property_read_bool(np, "interrupt-controller")) { 2033 dev_info(dev, "no interrupt support\n"); 2034 return 0; 2035 } 2036 2037 priv->irq = of_irq_get(np, 0); 2038 if (priv->irq <= 0) { 2039 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 2040 return priv->irq ? : -EINVAL; 2041 } 2042 2043 if (priv->id == ID_MT7988) 2044 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2045 &mt7988_irq_domain_ops, 2046 priv); 2047 else 2048 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2049 &mt7530_irq_domain_ops, 2050 priv); 2051 2052 if (!priv->irq_domain) { 2053 dev_err(dev, "failed to create IRQ domain\n"); 2054 return -ENOMEM; 2055 } 2056 2057 /* This register must be set for MT7530 to properly fire interrupts */ 2058 if (priv->id != ID_MT7531) 2059 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2060 2061 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2062 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2063 if (ret) { 2064 irq_domain_remove(priv->irq_domain); 2065 dev_err(dev, "failed to request IRQ: %d\n", ret); 2066 return ret; 2067 } 2068 2069 return 0; 2070 } 2071 2072 static void 2073 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2074 { 2075 int p; 2076 2077 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2078 if (BIT(p) & priv->ds->phys_mii_mask) { 2079 unsigned int irq; 2080 2081 irq = irq_find_mapping(priv->irq_domain, p); 2082 irq_dispose_mapping(irq); 2083 } 2084 } 2085 } 2086 2087 static void 2088 mt7530_free_irq_common(struct mt7530_priv *priv) 2089 { 2090 free_irq(priv->irq, priv); 2091 irq_domain_remove(priv->irq_domain); 2092 } 2093 2094 static void 2095 mt7530_free_irq(struct mt7530_priv *priv) 2096 { 2097 struct device_node *mnp, *np = priv->dev->of_node; 2098 2099 mnp = of_get_child_by_name(np, "mdio"); 2100 if (!mnp) 2101 mt7530_free_mdio_irq(priv); 2102 of_node_put(mnp); 2103 2104 mt7530_free_irq_common(priv); 2105 } 2106 2107 static int 2108 mt7530_setup_mdio(struct mt7530_priv *priv) 2109 { 2110 struct device_node *mnp, *np = priv->dev->of_node; 2111 struct dsa_switch *ds = priv->ds; 2112 struct device *dev = priv->dev; 2113 struct mii_bus *bus; 2114 static int idx; 2115 int ret = 0; 2116 2117 mnp = of_get_child_by_name(np, "mdio"); 2118 2119 if (mnp && !of_device_is_available(mnp)) 2120 goto out; 2121 2122 bus = devm_mdiobus_alloc(dev); 2123 if (!bus) { 2124 ret = -ENOMEM; 2125 goto out; 2126 } 2127 2128 if (!mnp) 2129 ds->user_mii_bus = bus; 2130 2131 bus->priv = priv; 2132 bus->name = KBUILD_MODNAME "-mii"; 2133 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2134 bus->read = mt753x_phy_read_c22; 2135 bus->write = mt753x_phy_write_c22; 2136 bus->read_c45 = mt753x_phy_read_c45; 2137 bus->write_c45 = mt753x_phy_write_c45; 2138 bus->parent = dev; 2139 bus->phy_mask = ~ds->phys_mii_mask; 2140 2141 if (priv->irq && !mnp) 2142 mt7530_setup_mdio_irq(priv); 2143 2144 ret = devm_of_mdiobus_register(dev, bus, mnp); 2145 if (ret) { 2146 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2147 if (priv->irq && !mnp) 2148 mt7530_free_mdio_irq(priv); 2149 } 2150 2151 out: 2152 of_node_put(mnp); 2153 return ret; 2154 } 2155 2156 static int 2157 mt7530_setup(struct dsa_switch *ds) 2158 { 2159 struct mt7530_priv *priv = ds->priv; 2160 struct device_node *dn = NULL; 2161 struct device_node *phy_node; 2162 struct device_node *mac_np; 2163 struct mt7530_dummy_poll p; 2164 phy_interface_t interface; 2165 struct dsa_port *cpu_dp; 2166 u32 id, val; 2167 int ret, i; 2168 2169 /* The parent node of conduit netdev which holds the common system 2170 * controller also is the container for two GMACs nodes representing 2171 * as two netdev instances. 2172 */ 2173 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2174 dn = cpu_dp->conduit->dev.of_node->parent; 2175 /* It doesn't matter which CPU port is found first, 2176 * their conduits should share the same parent OF node 2177 */ 2178 break; 2179 } 2180 2181 if (!dn) { 2182 dev_err(ds->dev, "parent OF node of DSA conduit not found"); 2183 return -EINVAL; 2184 } 2185 2186 ds->assisted_learning_on_cpu_port = true; 2187 ds->mtu_enforcement_ingress = true; 2188 2189 if (priv->id == ID_MT7530) { 2190 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2191 ret = regulator_enable(priv->core_pwr); 2192 if (ret < 0) { 2193 dev_err(priv->dev, 2194 "Failed to enable core power: %d\n", ret); 2195 return ret; 2196 } 2197 2198 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2199 ret = regulator_enable(priv->io_pwr); 2200 if (ret < 0) { 2201 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2202 ret); 2203 return ret; 2204 } 2205 } 2206 2207 /* Reset whole chip through gpio pin or memory-mapped registers for 2208 * different type of hardware 2209 */ 2210 if (priv->mcm) { 2211 reset_control_assert(priv->rstc); 2212 usleep_range(1000, 1100); 2213 reset_control_deassert(priv->rstc); 2214 } else { 2215 gpiod_set_value_cansleep(priv->reset, 0); 2216 usleep_range(1000, 1100); 2217 gpiod_set_value_cansleep(priv->reset, 1); 2218 } 2219 2220 /* Waiting for MT7530 got to stable */ 2221 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2222 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2223 20, 1000000); 2224 if (ret < 0) { 2225 dev_err(priv->dev, "reset timeout\n"); 2226 return ret; 2227 } 2228 2229 id = mt7530_read(priv, MT7530_CREV); 2230 id >>= CHIP_NAME_SHIFT; 2231 if (id != MT7530_ID) { 2232 dev_err(priv->dev, "chip %x can't be supported\n", id); 2233 return -ENODEV; 2234 } 2235 2236 if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) { 2237 dev_err(priv->dev, 2238 "MT7530 with a 20MHz XTAL is not supported!\n"); 2239 return -EINVAL; 2240 } 2241 2242 /* Reset the switch through internal reset */ 2243 mt7530_write(priv, MT7530_SYS_CTRL, 2244 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2245 SYS_CTRL_REG_RST); 2246 2247 mt7530_pll_setup(priv); 2248 2249 /* Lower Tx driving for TRGMII path */ 2250 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2251 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 2252 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2253 2254 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2255 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 2256 RD_TAP_MASK, RD_TAP(16)); 2257 2258 /* Enable port 6 */ 2259 val = mt7530_read(priv, MT7530_MHWTRAP); 2260 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2261 val |= MHWTRAP_MANUAL; 2262 mt7530_write(priv, MT7530_MHWTRAP, val); 2263 2264 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2265 2266 mt753x_trap_frames(priv); 2267 2268 /* Enable and reset MIB counters */ 2269 mt7530_mib_reset(ds); 2270 2271 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2272 /* Disable forwarding by default on all ports */ 2273 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2274 PCR_MATRIX_CLR); 2275 2276 /* Disable learning by default on all ports */ 2277 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2278 2279 if (dsa_is_cpu_port(ds, i)) { 2280 ret = mt753x_cpu_port_enable(ds, i); 2281 if (ret) 2282 return ret; 2283 } else { 2284 mt7530_port_disable(ds, i); 2285 2286 /* Set default PVID to 0 on all user ports */ 2287 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2288 G0_PORT_VID_DEF); 2289 } 2290 /* Enable consistent egress tag */ 2291 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2292 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2293 } 2294 2295 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2296 ret = mt7530_setup_vlan0(priv); 2297 if (ret) 2298 return ret; 2299 2300 /* Setup port 5 */ 2301 if (!dsa_is_unused_port(ds, 5)) { 2302 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2303 } else { 2304 /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. 2305 * Set priv->p5_intf_sel to the appropriate value if PHY muxing 2306 * is detected. 2307 */ 2308 for_each_child_of_node(dn, mac_np) { 2309 if (!of_device_is_compatible(mac_np, 2310 "mediatek,eth-mac")) 2311 continue; 2312 2313 ret = of_property_read_u32(mac_np, "reg", &id); 2314 if (ret < 0 || id != 1) 2315 continue; 2316 2317 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2318 if (!phy_node) 2319 continue; 2320 2321 if (phy_node->parent == priv->dev->of_node->parent) { 2322 ret = of_get_phy_mode(mac_np, &interface); 2323 if (ret && ret != -ENODEV) { 2324 of_node_put(mac_np); 2325 of_node_put(phy_node); 2326 return ret; 2327 } 2328 id = of_mdio_parse_addr(ds->dev, phy_node); 2329 if (id == 0) 2330 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2331 if (id == 4) 2332 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2333 } 2334 of_node_put(mac_np); 2335 of_node_put(phy_node); 2336 break; 2337 } 2338 2339 if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 || 2340 priv->p5_intf_sel == P5_INTF_SEL_PHY_P4) 2341 mt7530_setup_port5(ds, interface); 2342 } 2343 2344 #ifdef CONFIG_GPIOLIB 2345 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2346 ret = mt7530_setup_gpio(priv); 2347 if (ret) 2348 return ret; 2349 } 2350 #endif /* CONFIG_GPIOLIB */ 2351 2352 /* Flush the FDB table */ 2353 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2354 if (ret < 0) 2355 return ret; 2356 2357 return 0; 2358 } 2359 2360 static int 2361 mt7531_setup_common(struct dsa_switch *ds) 2362 { 2363 struct mt7530_priv *priv = ds->priv; 2364 int ret, i; 2365 2366 mt753x_trap_frames(priv); 2367 2368 /* Enable and reset MIB counters */ 2369 mt7530_mib_reset(ds); 2370 2371 /* Disable flooding on all ports */ 2372 mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | 2373 UNU_FFP_MASK); 2374 2375 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2376 /* Disable forwarding by default on all ports */ 2377 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2378 PCR_MATRIX_CLR); 2379 2380 /* Disable learning by default on all ports */ 2381 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2382 2383 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2384 2385 if (dsa_is_cpu_port(ds, i)) { 2386 ret = mt753x_cpu_port_enable(ds, i); 2387 if (ret) 2388 return ret; 2389 } else { 2390 mt7530_port_disable(ds, i); 2391 2392 /* Set default PVID to 0 on all user ports */ 2393 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2394 G0_PORT_VID_DEF); 2395 } 2396 2397 /* Enable consistent egress tag */ 2398 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2399 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2400 } 2401 2402 /* Flush the FDB table */ 2403 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2404 if (ret < 0) 2405 return ret; 2406 2407 return 0; 2408 } 2409 2410 static int 2411 mt7531_setup(struct dsa_switch *ds) 2412 { 2413 struct mt7530_priv *priv = ds->priv; 2414 struct mt7530_dummy_poll p; 2415 u32 val, id; 2416 int ret, i; 2417 2418 /* Reset whole chip through gpio pin or memory-mapped registers for 2419 * different type of hardware 2420 */ 2421 if (priv->mcm) { 2422 reset_control_assert(priv->rstc); 2423 usleep_range(1000, 1100); 2424 reset_control_deassert(priv->rstc); 2425 } else { 2426 gpiod_set_value_cansleep(priv->reset, 0); 2427 usleep_range(1000, 1100); 2428 gpiod_set_value_cansleep(priv->reset, 1); 2429 } 2430 2431 /* Waiting for MT7530 got to stable */ 2432 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2433 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2434 20, 1000000); 2435 if (ret < 0) { 2436 dev_err(priv->dev, "reset timeout\n"); 2437 return ret; 2438 } 2439 2440 id = mt7530_read(priv, MT7531_CREV); 2441 id >>= CHIP_NAME_SHIFT; 2442 2443 if (id != MT7531_ID) { 2444 dev_err(priv->dev, "chip %x can't be supported\n", id); 2445 return -ENODEV; 2446 } 2447 2448 /* MT7531AE has got two SGMII units. One for port 5, one for port 6. 2449 * MT7531BE has got only one SGMII unit which is for port 6. 2450 */ 2451 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 2452 priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); 2453 2454 /* all MACs must be forced link-down before sw reset */ 2455 for (i = 0; i < MT7530_NUM_PORTS; i++) 2456 mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); 2457 2458 /* Reset the switch through internal reset */ 2459 mt7530_write(priv, MT7530_SYS_CTRL, 2460 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2461 SYS_CTRL_REG_RST); 2462 2463 if (!priv->p5_sgmii) { 2464 mt7531_pll_setup(priv); 2465 } else { 2466 /* Let ds->user_mii_bus be able to access external phy. */ 2467 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2468 MT7531_EXT_P_MDC_11); 2469 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2470 MT7531_EXT_P_MDIO_12); 2471 } 2472 2473 if (!dsa_is_unused_port(ds, 5)) 2474 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2475 2476 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2477 MT7531_GPIO0_INTERRUPT); 2478 2479 /* Let phylink decide the interface later. */ 2480 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2481 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2482 2483 /* Enable PHY core PLL, since phy_device has not yet been created 2484 * provided for phy_[read,write]_mmd_indirect is called, we provide 2485 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2486 * function. 2487 */ 2488 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2489 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2490 val |= MT7531_PHY_PLL_BYPASS_MODE; 2491 val &= ~MT7531_PHY_PLL_OFF; 2492 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2493 CORE_PLL_GROUP4, val); 2494 2495 mt7531_setup_common(ds); 2496 2497 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2498 ret = mt7530_setup_vlan0(priv); 2499 if (ret) 2500 return ret; 2501 2502 ds->assisted_learning_on_cpu_port = true; 2503 ds->mtu_enforcement_ingress = true; 2504 2505 return 0; 2506 } 2507 2508 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2509 struct phylink_config *config) 2510 { 2511 switch (port) { 2512 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2513 case 0 ... 4: 2514 __set_bit(PHY_INTERFACE_MODE_GMII, 2515 config->supported_interfaces); 2516 break; 2517 2518 /* Port 5 supports rgmii with delays, mii, and gmii. */ 2519 case 5: 2520 phy_interface_set_rgmii(config->supported_interfaces); 2521 __set_bit(PHY_INTERFACE_MODE_MII, 2522 config->supported_interfaces); 2523 __set_bit(PHY_INTERFACE_MODE_GMII, 2524 config->supported_interfaces); 2525 break; 2526 2527 /* Port 6 supports rgmii and trgmii. */ 2528 case 6: 2529 __set_bit(PHY_INTERFACE_MODE_RGMII, 2530 config->supported_interfaces); 2531 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2532 config->supported_interfaces); 2533 break; 2534 } 2535 } 2536 2537 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2538 struct phylink_config *config) 2539 { 2540 struct mt7530_priv *priv = ds->priv; 2541 2542 switch (port) { 2543 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2544 case 0 ... 4: 2545 __set_bit(PHY_INTERFACE_MODE_GMII, 2546 config->supported_interfaces); 2547 break; 2548 2549 /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on 2550 * MT7531AE. 2551 */ 2552 case 5: 2553 if (!priv->p5_sgmii) { 2554 phy_interface_set_rgmii(config->supported_interfaces); 2555 break; 2556 } 2557 fallthrough; 2558 2559 /* Port 6 supports sgmii/802.3z. */ 2560 case 6: 2561 __set_bit(PHY_INTERFACE_MODE_SGMII, 2562 config->supported_interfaces); 2563 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2564 config->supported_interfaces); 2565 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2566 config->supported_interfaces); 2567 2568 config->mac_capabilities |= MAC_2500FD; 2569 break; 2570 } 2571 } 2572 2573 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, 2574 struct phylink_config *config) 2575 { 2576 switch (port) { 2577 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2578 case 0 ... 3: 2579 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2580 config->supported_interfaces); 2581 break; 2582 2583 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2584 case 6: 2585 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2586 config->supported_interfaces); 2587 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2588 MAC_10000FD; 2589 } 2590 } 2591 2592 static int 2593 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2594 phy_interface_t interface) 2595 { 2596 struct mt7530_priv *priv = ds->priv; 2597 2598 if (port == 5) 2599 mt7530_setup_port5(priv->ds, interface); 2600 else if (port == 6) 2601 mt7530_setup_port6(priv->ds, interface); 2602 2603 return 0; 2604 } 2605 2606 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2607 phy_interface_t interface, 2608 struct phy_device *phydev) 2609 { 2610 u32 val; 2611 2612 if (priv->p5_sgmii) { 2613 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2614 port); 2615 return -EINVAL; 2616 } 2617 2618 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2619 val |= GP_CLK_EN; 2620 val &= ~GP_MODE_MASK; 2621 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2622 val &= ~CLK_SKEW_IN_MASK; 2623 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2624 val &= ~CLK_SKEW_OUT_MASK; 2625 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2626 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2627 2628 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2629 if (!phydev || phy_driver_is_genphy(phydev)) { 2630 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2631 switch (interface) { 2632 case PHY_INTERFACE_MODE_RGMII: 2633 val |= TXCLK_NO_REVERSE; 2634 val |= RXCLK_NO_DELAY; 2635 break; 2636 case PHY_INTERFACE_MODE_RGMII_RXID: 2637 val |= TXCLK_NO_REVERSE; 2638 break; 2639 case PHY_INTERFACE_MODE_RGMII_TXID: 2640 val |= RXCLK_NO_DELAY; 2641 break; 2642 case PHY_INTERFACE_MODE_RGMII_ID: 2643 break; 2644 default: 2645 return -EINVAL; 2646 } 2647 } 2648 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2649 2650 return 0; 2651 } 2652 2653 static bool mt753x_is_mac_port(u32 port) 2654 { 2655 return (port == 5 || port == 6); 2656 } 2657 2658 static int 2659 mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2660 phy_interface_t interface) 2661 { 2662 if (dsa_is_cpu_port(ds, port) && 2663 interface == PHY_INTERFACE_MODE_INTERNAL) 2664 return 0; 2665 2666 return -EINVAL; 2667 } 2668 2669 static int 2670 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2671 phy_interface_t interface) 2672 { 2673 struct mt7530_priv *priv = ds->priv; 2674 struct phy_device *phydev; 2675 struct dsa_port *dp; 2676 2677 if (!mt753x_is_mac_port(port)) { 2678 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2679 return -EINVAL; 2680 } 2681 2682 switch (interface) { 2683 case PHY_INTERFACE_MODE_RGMII: 2684 case PHY_INTERFACE_MODE_RGMII_ID: 2685 case PHY_INTERFACE_MODE_RGMII_RXID: 2686 case PHY_INTERFACE_MODE_RGMII_TXID: 2687 dp = dsa_to_port(ds, port); 2688 phydev = dp->user->phydev; 2689 return mt7531_rgmii_setup(priv, port, interface, phydev); 2690 case PHY_INTERFACE_MODE_SGMII: 2691 case PHY_INTERFACE_MODE_NA: 2692 case PHY_INTERFACE_MODE_1000BASEX: 2693 case PHY_INTERFACE_MODE_2500BASEX: 2694 /* handled in SGMII PCS driver */ 2695 return 0; 2696 default: 2697 return -EINVAL; 2698 } 2699 2700 return -EINVAL; 2701 } 2702 2703 static int 2704 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2705 const struct phylink_link_state *state) 2706 { 2707 struct mt7530_priv *priv = ds->priv; 2708 2709 return priv->info->mac_port_config(ds, port, mode, state->interface); 2710 } 2711 2712 static struct phylink_pcs * 2713 mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port, 2714 phy_interface_t interface) 2715 { 2716 struct mt7530_priv *priv = ds->priv; 2717 2718 switch (interface) { 2719 case PHY_INTERFACE_MODE_TRGMII: 2720 return &priv->pcs[port].pcs; 2721 case PHY_INTERFACE_MODE_SGMII: 2722 case PHY_INTERFACE_MODE_1000BASEX: 2723 case PHY_INTERFACE_MODE_2500BASEX: 2724 return priv->ports[port].sgmii_pcs; 2725 default: 2726 return NULL; 2727 } 2728 } 2729 2730 static void 2731 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2732 const struct phylink_link_state *state) 2733 { 2734 struct mt7530_priv *priv = ds->priv; 2735 u32 mcr_cur, mcr_new; 2736 2737 switch (port) { 2738 case 0 ... 4: 2739 if (state->interface != PHY_INTERFACE_MODE_GMII && 2740 state->interface != PHY_INTERFACE_MODE_INTERNAL) 2741 goto unsupported; 2742 break; 2743 case 5: 2744 if (priv->p5_interface == state->interface) 2745 break; 2746 2747 if (mt753x_mac_config(ds, port, mode, state) < 0) 2748 goto unsupported; 2749 2750 if (priv->p5_intf_sel != P5_DISABLED) 2751 priv->p5_interface = state->interface; 2752 break; 2753 case 6: 2754 if (priv->p6_interface == state->interface) 2755 break; 2756 2757 if (mt753x_mac_config(ds, port, mode, state) < 0) 2758 goto unsupported; 2759 2760 priv->p6_interface = state->interface; 2761 break; 2762 default: 2763 unsupported: 2764 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2765 __func__, phy_modes(state->interface), port); 2766 return; 2767 } 2768 2769 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2770 mcr_new = mcr_cur; 2771 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2772 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2773 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2774 2775 /* Are we connected to external phy */ 2776 if (port == 5 && dsa_is_user_port(ds, 5)) 2777 mcr_new |= PMCR_EXT_PHY; 2778 2779 if (mcr_new != mcr_cur) 2780 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2781 } 2782 2783 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2784 unsigned int mode, 2785 phy_interface_t interface) 2786 { 2787 struct mt7530_priv *priv = ds->priv; 2788 2789 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2790 } 2791 2792 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2793 unsigned int mode, 2794 phy_interface_t interface, 2795 struct phy_device *phydev, 2796 int speed, int duplex, 2797 bool tx_pause, bool rx_pause) 2798 { 2799 struct mt7530_priv *priv = ds->priv; 2800 u32 mcr; 2801 2802 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2803 2804 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2805 * variants. 2806 */ 2807 if (interface == PHY_INTERFACE_MODE_TRGMII || 2808 (phy_interface_mode_is_8023z(interface))) { 2809 speed = SPEED_1000; 2810 duplex = DUPLEX_FULL; 2811 } 2812 2813 switch (speed) { 2814 case SPEED_1000: 2815 mcr |= PMCR_FORCE_SPEED_1000; 2816 break; 2817 case SPEED_100: 2818 mcr |= PMCR_FORCE_SPEED_100; 2819 break; 2820 } 2821 if (duplex == DUPLEX_FULL) { 2822 mcr |= PMCR_FORCE_FDX; 2823 if (tx_pause) 2824 mcr |= PMCR_TX_FC_EN; 2825 if (rx_pause) 2826 mcr |= PMCR_RX_FC_EN; 2827 } 2828 2829 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { 2830 switch (speed) { 2831 case SPEED_1000: 2832 mcr |= PMCR_FORCE_EEE1G; 2833 break; 2834 case SPEED_100: 2835 mcr |= PMCR_FORCE_EEE100; 2836 break; 2837 } 2838 } 2839 2840 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2841 } 2842 2843 static int 2844 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2845 { 2846 struct mt7530_priv *priv = ds->priv; 2847 phy_interface_t interface; 2848 int speed; 2849 int ret; 2850 2851 switch (port) { 2852 case 5: 2853 if (!priv->p5_sgmii) 2854 interface = PHY_INTERFACE_MODE_RGMII; 2855 else 2856 interface = PHY_INTERFACE_MODE_2500BASEX; 2857 2858 priv->p5_interface = interface; 2859 break; 2860 case 6: 2861 interface = PHY_INTERFACE_MODE_2500BASEX; 2862 2863 priv->p6_interface = interface; 2864 break; 2865 default: 2866 return -EINVAL; 2867 } 2868 2869 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2870 speed = SPEED_2500; 2871 else 2872 speed = SPEED_1000; 2873 2874 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2875 if (ret) 2876 return ret; 2877 mt7530_write(priv, MT7530_PMCR_P(port), 2878 PMCR_CPU_PORT_SETTING(priv->id)); 2879 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2880 speed, DUPLEX_FULL, true, true); 2881 2882 return 0; 2883 } 2884 2885 static int 2886 mt7988_cpu_port_config(struct dsa_switch *ds, int port) 2887 { 2888 struct mt7530_priv *priv = ds->priv; 2889 2890 mt7530_write(priv, MT7530_PMCR_P(port), 2891 PMCR_CPU_PORT_SETTING(priv->id)); 2892 2893 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, 2894 PHY_INTERFACE_MODE_INTERNAL, NULL, 2895 SPEED_10000, DUPLEX_FULL, true, true); 2896 2897 return 0; 2898 } 2899 2900 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 2901 struct phylink_config *config) 2902 { 2903 struct mt7530_priv *priv = ds->priv; 2904 2905 /* This switch only supports full-duplex at 1Gbps */ 2906 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2907 MAC_10 | MAC_100 | MAC_1000FD; 2908 2909 priv->info->mac_port_get_caps(ds, port, config); 2910 } 2911 2912 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 2913 unsigned long *supported, 2914 const struct phylink_link_state *state) 2915 { 2916 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 2917 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 2918 phy_interface_mode_is_8023z(state->interface)) 2919 phylink_clear(supported, Autoneg); 2920 2921 return 0; 2922 } 2923 2924 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, 2925 struct phylink_link_state *state) 2926 { 2927 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2928 int port = pcs_to_mt753x_pcs(pcs)->port; 2929 u32 pmsr; 2930 2931 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2932 2933 state->link = (pmsr & PMSR_LINK); 2934 state->an_complete = state->link; 2935 state->duplex = !!(pmsr & PMSR_DPX); 2936 2937 switch (pmsr & PMSR_SPEED_MASK) { 2938 case PMSR_SPEED_10: 2939 state->speed = SPEED_10; 2940 break; 2941 case PMSR_SPEED_100: 2942 state->speed = SPEED_100; 2943 break; 2944 case PMSR_SPEED_1000: 2945 state->speed = SPEED_1000; 2946 break; 2947 default: 2948 state->speed = SPEED_UNKNOWN; 2949 break; 2950 } 2951 2952 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2953 if (pmsr & PMSR_RX_FC) 2954 state->pause |= MLO_PAUSE_RX; 2955 if (pmsr & PMSR_TX_FC) 2956 state->pause |= MLO_PAUSE_TX; 2957 } 2958 2959 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 2960 phy_interface_t interface, 2961 const unsigned long *advertising, 2962 bool permit_pause_to_mac) 2963 { 2964 return 0; 2965 } 2966 2967 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 2968 { 2969 } 2970 2971 static const struct phylink_pcs_ops mt7530_pcs_ops = { 2972 .pcs_validate = mt753x_pcs_validate, 2973 .pcs_get_state = mt7530_pcs_get_state, 2974 .pcs_config = mt753x_pcs_config, 2975 .pcs_an_restart = mt7530_pcs_an_restart, 2976 }; 2977 2978 static int 2979 mt753x_setup(struct dsa_switch *ds) 2980 { 2981 struct mt7530_priv *priv = ds->priv; 2982 int i, ret; 2983 2984 /* Initialise the PCS devices */ 2985 for (i = 0; i < priv->ds->num_ports; i++) { 2986 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 2987 priv->pcs[i].pcs.neg_mode = true; 2988 priv->pcs[i].priv = priv; 2989 priv->pcs[i].port = i; 2990 } 2991 2992 ret = priv->info->sw_setup(ds); 2993 if (ret) 2994 return ret; 2995 2996 ret = mt7530_setup_irq(priv); 2997 if (ret) 2998 return ret; 2999 3000 ret = mt7530_setup_mdio(priv); 3001 if (ret && priv->irq) 3002 mt7530_free_irq_common(priv); 3003 3004 if (priv->create_sgmii) { 3005 ret = priv->create_sgmii(priv); 3006 if (ret && priv->irq) 3007 mt7530_free_irq(priv); 3008 } 3009 3010 return ret; 3011 } 3012 3013 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3014 struct ethtool_keee *e) 3015 { 3016 struct mt7530_priv *priv = ds->priv; 3017 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 3018 3019 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3020 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 3021 3022 return 0; 3023 } 3024 3025 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3026 struct ethtool_keee *e) 3027 { 3028 struct mt7530_priv *priv = ds->priv; 3029 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3030 3031 if (e->tx_lpi_timer > 0xFFF) 3032 return -EINVAL; 3033 3034 set = SET_LPI_THRESH(e->tx_lpi_timer); 3035 if (!e->tx_lpi_enabled) 3036 /* Force LPI Mode without a delay */ 3037 set |= LPI_MODE_EN; 3038 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3039 3040 return 0; 3041 } 3042 3043 static void 3044 mt753x_conduit_state_change(struct dsa_switch *ds, 3045 const struct net_device *conduit, 3046 bool operational) 3047 { 3048 struct dsa_port *cpu_dp = conduit->dsa_ptr; 3049 struct mt7530_priv *priv = ds->priv; 3050 int val = 0; 3051 u8 mask; 3052 3053 /* Set the CPU port to trap frames to for MT7530. Trapped frames will be 3054 * forwarded to the numerically smallest CPU port whose conduit 3055 * interface is up. 3056 */ 3057 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 3058 return; 3059 3060 mask = BIT(cpu_dp->index); 3061 3062 if (operational) 3063 priv->active_cpu_ports |= mask; 3064 else 3065 priv->active_cpu_ports &= ~mask; 3066 3067 if (priv->active_cpu_ports) 3068 val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports)); 3069 3070 mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val); 3071 } 3072 3073 static int mt7988_setup(struct dsa_switch *ds) 3074 { 3075 struct mt7530_priv *priv = ds->priv; 3076 3077 /* Reset the switch */ 3078 reset_control_assert(priv->rstc); 3079 usleep_range(20, 50); 3080 reset_control_deassert(priv->rstc); 3081 usleep_range(20, 50); 3082 3083 /* Reset the switch PHYs */ 3084 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST); 3085 3086 return mt7531_setup_common(ds); 3087 } 3088 3089 const struct dsa_switch_ops mt7530_switch_ops = { 3090 .get_tag_protocol = mtk_get_tag_protocol, 3091 .setup = mt753x_setup, 3092 .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, 3093 .get_strings = mt7530_get_strings, 3094 .get_ethtool_stats = mt7530_get_ethtool_stats, 3095 .get_sset_count = mt7530_get_sset_count, 3096 .set_ageing_time = mt7530_set_ageing_time, 3097 .port_enable = mt7530_port_enable, 3098 .port_disable = mt7530_port_disable, 3099 .port_change_mtu = mt7530_port_change_mtu, 3100 .port_max_mtu = mt7530_port_max_mtu, 3101 .port_stp_state_set = mt7530_stp_state_set, 3102 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3103 .port_bridge_flags = mt7530_port_bridge_flags, 3104 .port_bridge_join = mt7530_port_bridge_join, 3105 .port_bridge_leave = mt7530_port_bridge_leave, 3106 .port_fdb_add = mt7530_port_fdb_add, 3107 .port_fdb_del = mt7530_port_fdb_del, 3108 .port_fdb_dump = mt7530_port_fdb_dump, 3109 .port_mdb_add = mt7530_port_mdb_add, 3110 .port_mdb_del = mt7530_port_mdb_del, 3111 .port_vlan_filtering = mt7530_port_vlan_filtering, 3112 .port_vlan_add = mt7530_port_vlan_add, 3113 .port_vlan_del = mt7530_port_vlan_del, 3114 .port_mirror_add = mt753x_port_mirror_add, 3115 .port_mirror_del = mt753x_port_mirror_del, 3116 .phylink_get_caps = mt753x_phylink_get_caps, 3117 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs, 3118 .phylink_mac_config = mt753x_phylink_mac_config, 3119 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3120 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3121 .get_mac_eee = mt753x_get_mac_eee, 3122 .set_mac_eee = mt753x_set_mac_eee, 3123 .conduit_state_change = mt753x_conduit_state_change, 3124 }; 3125 EXPORT_SYMBOL_GPL(mt7530_switch_ops); 3126 3127 const struct mt753x_info mt753x_table[] = { 3128 [ID_MT7621] = { 3129 .id = ID_MT7621, 3130 .pcs_ops = &mt7530_pcs_ops, 3131 .sw_setup = mt7530_setup, 3132 .phy_read_c22 = mt7530_phy_read_c22, 3133 .phy_write_c22 = mt7530_phy_write_c22, 3134 .phy_read_c45 = mt7530_phy_read_c45, 3135 .phy_write_c45 = mt7530_phy_write_c45, 3136 .mac_port_get_caps = mt7530_mac_port_get_caps, 3137 .mac_port_config = mt7530_mac_config, 3138 }, 3139 [ID_MT7530] = { 3140 .id = ID_MT7530, 3141 .pcs_ops = &mt7530_pcs_ops, 3142 .sw_setup = mt7530_setup, 3143 .phy_read_c22 = mt7530_phy_read_c22, 3144 .phy_write_c22 = mt7530_phy_write_c22, 3145 .phy_read_c45 = mt7530_phy_read_c45, 3146 .phy_write_c45 = mt7530_phy_write_c45, 3147 .mac_port_get_caps = mt7530_mac_port_get_caps, 3148 .mac_port_config = mt7530_mac_config, 3149 }, 3150 [ID_MT7531] = { 3151 .id = ID_MT7531, 3152 .pcs_ops = &mt7530_pcs_ops, 3153 .sw_setup = mt7531_setup, 3154 .phy_read_c22 = mt7531_ind_c22_phy_read, 3155 .phy_write_c22 = mt7531_ind_c22_phy_write, 3156 .phy_read_c45 = mt7531_ind_c45_phy_read, 3157 .phy_write_c45 = mt7531_ind_c45_phy_write, 3158 .cpu_port_config = mt7531_cpu_port_config, 3159 .mac_port_get_caps = mt7531_mac_port_get_caps, 3160 .mac_port_config = mt7531_mac_config, 3161 }, 3162 [ID_MT7988] = { 3163 .id = ID_MT7988, 3164 .pcs_ops = &mt7530_pcs_ops, 3165 .sw_setup = mt7988_setup, 3166 .phy_read_c22 = mt7531_ind_c22_phy_read, 3167 .phy_write_c22 = mt7531_ind_c22_phy_write, 3168 .phy_read_c45 = mt7531_ind_c45_phy_read, 3169 .phy_write_c45 = mt7531_ind_c45_phy_write, 3170 .cpu_port_config = mt7988_cpu_port_config, 3171 .mac_port_get_caps = mt7988_mac_port_get_caps, 3172 .mac_port_config = mt7988_mac_config, 3173 }, 3174 }; 3175 EXPORT_SYMBOL_GPL(mt753x_table); 3176 3177 int 3178 mt7530_probe_common(struct mt7530_priv *priv) 3179 { 3180 struct device *dev = priv->dev; 3181 3182 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 3183 if (!priv->ds) 3184 return -ENOMEM; 3185 3186 priv->ds->dev = dev; 3187 priv->ds->num_ports = MT7530_NUM_PORTS; 3188 3189 /* Get the hardware identifier from the devicetree node. 3190 * We will need it for some of the clock and regulator setup. 3191 */ 3192 priv->info = of_device_get_match_data(dev); 3193 if (!priv->info) 3194 return -EINVAL; 3195 3196 /* Sanity check if these required device operations are filled 3197 * properly. 3198 */ 3199 if (!priv->info->sw_setup || !priv->info->phy_read_c22 || 3200 !priv->info->phy_write_c22 || !priv->info->mac_port_get_caps || 3201 !priv->info->mac_port_config) 3202 return -EINVAL; 3203 3204 priv->id = priv->info->id; 3205 priv->dev = dev; 3206 priv->ds->priv = priv; 3207 priv->ds->ops = &mt7530_switch_ops; 3208 mutex_init(&priv->reg_mutex); 3209 dev_set_drvdata(dev, priv); 3210 3211 return 0; 3212 } 3213 EXPORT_SYMBOL_GPL(mt7530_probe_common); 3214 3215 void 3216 mt7530_remove_common(struct mt7530_priv *priv) 3217 { 3218 if (priv->irq) 3219 mt7530_free_irq(priv); 3220 3221 dsa_unregister_switch(priv->ds); 3222 3223 mutex_destroy(&priv->reg_mutex); 3224 } 3225 EXPORT_SYMBOL_GPL(mt7530_remove_common); 3226 3227 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3228 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3229 MODULE_LICENSE("GPL"); 3230