1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Motorcomm YT921x Switch 4 * 5 * Should work on YT9213/YT9214/YT9215/YT9218, but only tested on YT9215+SGMII, 6 * be sure to do your own checks before porting to another chip. 7 * 8 * Copyright (c) 2025 David Yang 9 */ 10 11 #include <linux/dcbnl.h> 12 #include <linux/etherdevice.h> 13 #include <linux/if_bridge.h> 14 #include <linux/if_hsr.h> 15 #include <linux/if_vlan.h> 16 #include <linux/mdio.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_mdio.h> 20 #include <linux/of_net.h> 21 #include <linux/sort.h> 22 #include <linux/u64_stats_sync.h> 23 24 #include <net/dsa.h> 25 #include <net/dscp.h> 26 #include <net/ieee8021q.h> 27 28 #include "chip.h" 29 #include "leds.h" 30 #include "mdio_bus.h" 31 #include "mib.h" 32 #include "pcs.h" 33 #include "smi.h" 34 #include "tc.h" 35 36 static const struct yt921x_info yt921x_infos[] = { 37 { 38 "YT9215SC", YT9215_MAJOR, 1, 0, 39 GENMASK(4, 0), 40 BIT(9), 41 BIT(8) | BIT(9), 42 }, 43 { 44 "YT9215S", YT9215_MAJOR, 2, 0, 45 GENMASK(4, 0), 46 BIT(9), 47 BIT(8), 48 }, 49 { 50 "YT9215RB", YT9215_MAJOR, 3, 0, 51 GENMASK(4, 0), 52 BIT(8) | BIT(9), 53 0, 54 }, 55 { 56 "YT9214NB", YT9215_MAJOR, 3, 2, 57 BIT(1) | BIT(3), 58 BIT(9), 59 BIT(8), 60 }, 61 { 62 "YT9213NB", YT9215_MAJOR, 3, 3, 63 BIT(1) | BIT(3), 64 BIT(9), 65 BIT(9), 66 }, 67 { 68 "YT9218N", YT9218_MAJOR, 0, 0, 69 GENMASK(7, 0), 70 0, 71 0, 72 }, 73 { 74 "YT9218MB", YT9218_MAJOR, 1, 0, 75 GENMASK(7, 0), 76 BIT(8) | BIT(9), 77 BIT(8) | BIT(9), 78 }, 79 {} 80 }; 81 82 #define YT921X_VID_UNWARE 4095 83 84 struct yt921x_reg_mdio { 85 struct mii_bus *bus; 86 int addr; 87 /* SWITCH_ID_1 / SWITCH_ID_0 of the device 88 * 89 * This is a way to multiplex multiple devices on the same MII phyaddr 90 * and should be configurable in DT. However, MDIO core simply doesn't 91 * allow multiple devices over one reg addr, so this is a fixed value 92 * for now until a solution is found. 93 * 94 * Keep this because we need switchid to form MII regaddrs anyway. 95 */ 96 unsigned char switchid; 97 }; 98 99 /* TODO: SPI/I2C */ 100 101 static int yt921x_reg_mdio_read(void *context, u32 reg, u32 *valp) 102 { 103 struct yt921x_reg_mdio *mdio = context; 104 struct mii_bus *bus = mdio->bus; 105 int addr = mdio->addr; 106 u32 reg_addr; 107 u32 reg_data; 108 u32 val; 109 int res; 110 111 /* Hold the mdio bus lock to avoid (un)locking for 4 times */ 112 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 113 114 reg_addr = YT921X_SMI_SWITCHID(mdio->switchid) | YT921X_SMI_ADDR | 115 YT921X_SMI_READ; 116 res = __mdiobus_write(bus, addr, reg_addr, (u16)(reg >> 16)); 117 if (res) 118 goto end; 119 res = __mdiobus_write(bus, addr, reg_addr, (u16)reg); 120 if (res) 121 goto end; 122 123 reg_data = YT921X_SMI_SWITCHID(mdio->switchid) | YT921X_SMI_DATA | 124 YT921X_SMI_READ; 125 res = __mdiobus_read(bus, addr, reg_data); 126 if (res < 0) 127 goto end; 128 val = (u16)res; 129 res = __mdiobus_read(bus, addr, reg_data); 130 if (res < 0) 131 goto end; 132 val = (val << 16) | (u16)res; 133 134 *valp = val; 135 res = 0; 136 137 end: 138 mutex_unlock(&bus->mdio_lock); 139 return res; 140 } 141 142 static int yt921x_reg_mdio_write(void *context, u32 reg, u32 val) 143 { 144 struct yt921x_reg_mdio *mdio = context; 145 struct mii_bus *bus = mdio->bus; 146 int addr = mdio->addr; 147 u32 reg_addr; 148 u32 reg_data; 149 int res; 150 151 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 152 153 reg_addr = YT921X_SMI_SWITCHID(mdio->switchid) | YT921X_SMI_ADDR | 154 YT921X_SMI_WRITE; 155 res = __mdiobus_write(bus, addr, reg_addr, (u16)(reg >> 16)); 156 if (res) 157 goto end; 158 res = __mdiobus_write(bus, addr, reg_addr, (u16)reg); 159 if (res) 160 goto end; 161 162 reg_data = YT921X_SMI_SWITCHID(mdio->switchid) | YT921X_SMI_DATA | 163 YT921X_SMI_WRITE; 164 res = __mdiobus_write(bus, addr, reg_data, (u16)(val >> 16)); 165 if (res) 166 goto end; 167 res = __mdiobus_write(bus, addr, reg_data, (u16)val); 168 if (res) 169 goto end; 170 171 res = 0; 172 173 end: 174 mutex_unlock(&bus->mdio_lock); 175 return res; 176 } 177 178 static const struct yt921x_reg_ops yt921x_reg_ops_mdio = { 179 .read = yt921x_reg_mdio_read, 180 .write = yt921x_reg_mdio_write, 181 }; 182 183 /* TODO: SPI/I2C */ 184 185 static int 186 yt921x_set_eee(struct yt921x_priv *priv, int port, struct ethtool_keee *e) 187 { 188 /* Poor datasheet for EEE operations; don't ask if you are confused */ 189 190 bool enable = e->eee_enabled; 191 u16 new_mask; 192 int res; 193 194 /* Enable / disable global EEE */ 195 new_mask = priv->eee_ports_mask; 196 new_mask &= ~BIT(port); 197 new_mask |= !enable ? 0 : BIT(port); 198 199 if (!!new_mask != !!priv->eee_ports_mask) { 200 res = yt921x_reg_toggle_bits(priv, YT921X_PON_STRAP_FUNC, 201 YT921X_PON_STRAP_EEE, !!new_mask); 202 if (res) 203 return res; 204 res = yt921x_reg_toggle_bits(priv, YT921X_PON_STRAP_VAL, 205 YT921X_PON_STRAP_EEE, !!new_mask); 206 if (res) 207 return res; 208 } 209 210 priv->eee_ports_mask = new_mask; 211 212 /* Enable / disable port EEE */ 213 res = yt921x_reg_toggle_bits(priv, YT921X_EEE_CTRL, 214 YT921X_EEE_CTRL_ENn(port), enable); 215 if (res) 216 return res; 217 res = yt921x_reg_toggle_bits(priv, YT921X_EEEn_VAL(port), 218 YT921X_EEE_VAL_DATA, enable); 219 if (res) 220 return res; 221 222 return 0; 223 } 224 225 static int 226 yt921x_dsa_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e) 227 { 228 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 229 int res; 230 231 mutex_lock(&priv->reg_lock); 232 res = yt921x_set_eee(priv, port, e); 233 mutex_unlock(&priv->reg_lock); 234 235 return res; 236 } 237 238 static int 239 yt921x_dsa_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 240 { 241 /* Only serves as packet filter, since the frame size is always set to 242 * maximum after reset 243 */ 244 245 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 246 struct dsa_port *dp = dsa_to_port(ds, port); 247 int frame_size; 248 int res; 249 250 frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN; 251 if (dsa_port_is_cpu(dp)) 252 frame_size += YT921X_TAG_LEN; 253 254 mutex_lock(&priv->reg_lock); 255 res = yt921x_reg_update_bits(priv, YT921X_MACn_FRAME(port), 256 YT921X_MAC_FRAME_SIZE_M, 257 YT921X_MAC_FRAME_SIZE(frame_size)); 258 mutex_unlock(&priv->reg_lock); 259 260 return res; 261 } 262 263 static int yt921x_dsa_port_max_mtu(struct dsa_switch *ds, int port) 264 { 265 /* Only called for user ports, exclude tag len here */ 266 return YT921X_FRAME_SIZE_MAX - ETH_HLEN - ETH_FCS_LEN - YT921X_TAG_LEN; 267 } 268 269 static int yt921x_lag_hash(struct yt921x_priv *priv, u32 ctrl, bool unique_lag, 270 struct netlink_ext_ack *extack) 271 { 272 u32 val; 273 int res; 274 275 /* Hash Mode is global. Make sure the same Hash Mode is set to all the 276 * 2 possible lags. 277 * If we are the unique LAG we can set whatever hash mode we want. 278 * To change hash mode it's needed to remove all LAG and change the mode 279 * with the latest. 280 */ 281 if (unique_lag) { 282 res = yt921x_reg_write(priv, YT921X_LAG_HASH, ctrl); 283 if (res) 284 return res; 285 } else { 286 res = yt921x_reg_read(priv, YT921X_LAG_HASH, &val); 287 if (res) 288 return res; 289 290 if (val != ctrl) { 291 NL_SET_ERR_MSG_MOD(extack, 292 "Mismatched Hash Mode across different lags is not supported"); 293 return -EOPNOTSUPP; 294 } 295 } 296 297 return 0; 298 } 299 300 static int yt921x_lag_set(struct yt921x_priv *priv, u8 index, u16 ports_mask) 301 { 302 unsigned long targets_mask = ports_mask; 303 unsigned int cnt; 304 u32 ctrl; 305 int port; 306 int res; 307 308 cnt = 0; 309 for_each_set_bit(port, &targets_mask, YT921X_PORT_NUM) { 310 ctrl = YT921X_LAG_MEMBER_PORT(port); 311 res = yt921x_reg_write(priv, YT921X_LAG_MEMBERnm(index, cnt), 312 ctrl); 313 if (res) 314 return res; 315 316 cnt++; 317 } 318 319 ctrl = YT921X_LAG_GROUP_PORTS(ports_mask) | 320 YT921X_LAG_GROUP_MEMBER_NUM(cnt); 321 return yt921x_reg_write(priv, YT921X_LAG_GROUPn(index), ctrl); 322 } 323 324 static int 325 yt921x_dsa_port_lag_leave(struct dsa_switch *ds, int port, struct dsa_lag lag) 326 { 327 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 328 struct dsa_port *dp; 329 u32 ctrl; 330 int res; 331 332 if (!lag.id) 333 return -EINVAL; 334 335 ctrl = 0; 336 dsa_lag_foreach_port(dp, ds->dst, &lag) 337 ctrl |= BIT(dp->index); 338 339 mutex_lock(&priv->reg_lock); 340 res = yt921x_lag_set(priv, lag.id - 1, ctrl); 341 mutex_unlock(&priv->reg_lock); 342 343 return res; 344 } 345 346 static int 347 yt921x_dsa_port_lag_check(struct dsa_switch *ds, struct dsa_lag lag, 348 struct netdev_lag_upper_info *info, 349 struct netlink_ext_ack *extack) 350 { 351 unsigned int members; 352 struct dsa_port *dp; 353 354 if (!lag.id) 355 return -EINVAL; 356 357 members = 0; 358 dsa_lag_foreach_port(dp, ds->dst, &lag) 359 /* Includes the port joining the LAG */ 360 members++; 361 362 if (members > YT921X_LAG_PORT_NUM) { 363 NL_SET_ERR_MSG_MOD(extack, 364 "Cannot offload more than 4 LAG ports"); 365 return -EOPNOTSUPP; 366 } 367 368 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 369 NL_SET_ERR_MSG_MOD(extack, 370 "Can only offload LAG using hash TX type"); 371 return -EOPNOTSUPP; 372 } 373 374 if (info->hash_type != NETDEV_LAG_HASH_L2 && 375 info->hash_type != NETDEV_LAG_HASH_L23 && 376 info->hash_type != NETDEV_LAG_HASH_L34) { 377 NL_SET_ERR_MSG_MOD(extack, 378 "Can only offload L2 or L2+L3 or L3+L4 TX hash"); 379 return -EOPNOTSUPP; 380 } 381 382 return 0; 383 } 384 385 static int 386 yt921x_dsa_port_lag_join(struct dsa_switch *ds, int port, struct dsa_lag lag, 387 struct netdev_lag_upper_info *info, 388 struct netlink_ext_ack *extack) 389 { 390 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 391 struct dsa_port *dp; 392 bool unique_lag; 393 unsigned int i; 394 u32 ctrl; 395 int res; 396 397 res = yt921x_dsa_port_lag_check(ds, lag, info, extack); 398 if (res) 399 return res; 400 401 ctrl = 0; 402 switch (info->hash_type) { 403 case NETDEV_LAG_HASH_L34: 404 ctrl |= YT921X_LAG_HASH_IP_DST; 405 ctrl |= YT921X_LAG_HASH_IP_SRC; 406 ctrl |= YT921X_LAG_HASH_IP_PROTO; 407 408 ctrl |= YT921X_LAG_HASH_L4_DPORT; 409 ctrl |= YT921X_LAG_HASH_L4_SPORT; 410 break; 411 case NETDEV_LAG_HASH_L23: 412 ctrl |= YT921X_LAG_HASH_MAC_DA; 413 ctrl |= YT921X_LAG_HASH_MAC_SA; 414 415 ctrl |= YT921X_LAG_HASH_IP_DST; 416 ctrl |= YT921X_LAG_HASH_IP_SRC; 417 ctrl |= YT921X_LAG_HASH_IP_PROTO; 418 break; 419 case NETDEV_LAG_HASH_L2: 420 ctrl |= YT921X_LAG_HASH_MAC_DA; 421 ctrl |= YT921X_LAG_HASH_MAC_SA; 422 break; 423 default: 424 return -EOPNOTSUPP; 425 } 426 427 /* Check if we are the unique configured LAG */ 428 unique_lag = true; 429 dsa_lags_foreach_id(i, ds->dst) 430 if (i != lag.id && dsa_lag_by_id(ds->dst, i)) { 431 unique_lag = false; 432 break; 433 } 434 435 mutex_lock(&priv->reg_lock); 436 do { 437 res = yt921x_lag_hash(priv, ctrl, unique_lag, extack); 438 if (res) 439 break; 440 441 ctrl = 0; 442 dsa_lag_foreach_port(dp, ds->dst, &lag) 443 ctrl |= BIT(dp->index); 444 res = yt921x_lag_set(priv, lag.id - 1, ctrl); 445 } while (0); 446 mutex_unlock(&priv->reg_lock); 447 448 return res; 449 } 450 451 static int yt921x_fdb_wait(struct yt921x_priv *priv, u32 *valp) 452 { 453 struct device *dev = yt921x_priv_to_device(priv); 454 u32 val = YT921X_FDB_RESULT_DONE; 455 int res; 456 457 res = yt921x_reg_wait(priv, YT921X_FDB_RESULT, YT921X_FDB_RESULT_DONE, 458 &val); 459 if (res) { 460 dev_err(dev, "FDB probably stuck\n"); 461 return res; 462 } 463 464 *valp = val; 465 return 0; 466 } 467 468 static int 469 yt921x_fdb_in01(struct yt921x_priv *priv, const unsigned char *addr, 470 u16 vid, u32 ctrl1) 471 { 472 u32 ctrl; 473 int res; 474 475 ctrl = ethaddr_hi4_to_u32(addr); 476 res = yt921x_reg_write(priv, YT921X_FDB_IN0, ctrl); 477 if (res) 478 return res; 479 480 ctrl = ctrl1 | YT921X_FDB_IO1_FID(vid) | ethaddr_lo2_to_u32(addr); 481 return yt921x_reg_write(priv, YT921X_FDB_IN1, ctrl); 482 } 483 484 static int 485 yt921x_fdb_has(struct yt921x_priv *priv, const unsigned char *addr, u16 vid, 486 u16 *indexp) 487 { 488 u32 ctrl; 489 u32 val; 490 int res; 491 492 res = yt921x_fdb_in01(priv, addr, vid, 0); 493 if (res) 494 return res; 495 496 ctrl = 0; 497 res = yt921x_reg_write(priv, YT921X_FDB_IN2, ctrl); 498 if (res) 499 return res; 500 501 ctrl = YT921X_FDB_OP_OP_GET_ONE | YT921X_FDB_OP_START; 502 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 503 if (res) 504 return res; 505 506 res = yt921x_fdb_wait(priv, &val); 507 if (res) 508 return res; 509 if (val & YT921X_FDB_RESULT_NOTFOUND) { 510 *indexp = YT921X_FDB_NUM; 511 return 0; 512 } 513 514 *indexp = FIELD_GET(YT921X_FDB_RESULT_INDEX_M, val); 515 return 0; 516 } 517 518 static int 519 yt921x_fdb_read(struct yt921x_priv *priv, unsigned char *addr, u16 *vidp, 520 u16 *ports_maskp, u16 *indexp, u8 *statusp) 521 { 522 struct device *dev = yt921x_priv_to_device(priv); 523 u16 index; 524 u32 data0; 525 u32 data1; 526 u32 data2; 527 u32 val; 528 int res; 529 530 res = yt921x_fdb_wait(priv, &val); 531 if (res) 532 return res; 533 if (val & YT921X_FDB_RESULT_NOTFOUND) { 534 *ports_maskp = 0; 535 return 0; 536 } 537 index = FIELD_GET(YT921X_FDB_RESULT_INDEX_M, val); 538 539 res = yt921x_reg_read(priv, YT921X_FDB_OUT1, &data1); 540 if (res) 541 return res; 542 if ((data1 & YT921X_FDB_IO1_STATUS_M) == 543 YT921X_FDB_IO1_STATUS_INVALID) { 544 *ports_maskp = 0; 545 return 0; 546 } 547 548 res = yt921x_reg_read(priv, YT921X_FDB_OUT0, &data0); 549 if (res) 550 return res; 551 res = yt921x_reg_read(priv, YT921X_FDB_OUT2, &data2); 552 if (res) 553 return res; 554 555 addr[0] = data0 >> 24; 556 addr[1] = data0 >> 16; 557 addr[2] = data0 >> 8; 558 addr[3] = data0; 559 addr[4] = data1 >> 8; 560 addr[5] = data1; 561 *vidp = FIELD_GET(YT921X_FDB_IO1_FID_M, data1); 562 *indexp = index; 563 *ports_maskp = FIELD_GET(YT921X_FDB_IO2_EGR_PORTS_M, data2); 564 *statusp = FIELD_GET(YT921X_FDB_IO1_STATUS_M, data1); 565 566 dev_dbg(dev, 567 "%s: index 0x%x, mac %02x:%02x:%02x:%02x:%02x:%02x, vid %d, ports 0x%x, status %d\n", 568 __func__, *indexp, addr[0], addr[1], addr[2], addr[3], 569 addr[4], addr[5], *vidp, *ports_maskp, *statusp); 570 return 0; 571 } 572 573 static int 574 yt921x_fdb_dump(struct yt921x_priv *priv, u16 ports_mask, 575 dsa_fdb_dump_cb_t *cb, void *data) 576 { 577 unsigned char addr[ETH_ALEN]; 578 u8 status; 579 u16 pmask; 580 u16 index; 581 u32 ctrl; 582 u16 vid; 583 int res; 584 585 ctrl = YT921X_FDB_OP_INDEX(0) | YT921X_FDB_OP_MODE_INDEX | 586 YT921X_FDB_OP_OP_GET_ONE | YT921X_FDB_OP_START; 587 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 588 if (res) 589 return res; 590 res = yt921x_fdb_read(priv, addr, &vid, &pmask, &index, &status); 591 if (res) 592 return res; 593 if ((pmask & ports_mask) && !is_multicast_ether_addr(addr)) { 594 res = cb(addr, vid, 595 status == YT921X_FDB_ENTRY_STATUS_STATIC, data); 596 if (res) 597 return res; 598 } 599 600 ctrl = YT921X_FDB_IO2_EGR_PORTS(ports_mask); 601 res = yt921x_reg_write(priv, YT921X_FDB_IN2, ctrl); 602 if (res) 603 return res; 604 605 index = 0; 606 do { 607 ctrl = YT921X_FDB_OP_INDEX(index) | YT921X_FDB_OP_MODE_INDEX | 608 YT921X_FDB_OP_NEXT_TYPE_UCAST_PORT | 609 YT921X_FDB_OP_OP_GET_NEXT | YT921X_FDB_OP_START; 610 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 611 if (res) 612 return res; 613 614 res = yt921x_fdb_read(priv, addr, &vid, &pmask, &index, 615 &status); 616 if (res) 617 return res; 618 if (!pmask) 619 break; 620 621 if ((pmask & ports_mask) && !is_multicast_ether_addr(addr)) { 622 res = cb(addr, vid, 623 status == YT921X_FDB_ENTRY_STATUS_STATIC, 624 data); 625 if (res) 626 return res; 627 } 628 629 /* Never call GET_NEXT with 4095, otherwise it will hang 630 * forever until a reset! 631 */ 632 } while (index < YT921X_FDB_NUM - 1); 633 634 return 0; 635 } 636 637 static int 638 yt921x_fdb_flush_raw(struct yt921x_priv *priv, u16 ports_mask, u16 vid, 639 bool flush_static) 640 { 641 u32 ctrl; 642 u32 val; 643 int res; 644 645 if (vid < 4096) { 646 ctrl = YT921X_FDB_IO1_FID(vid); 647 res = yt921x_reg_write(priv, YT921X_FDB_IN1, ctrl); 648 if (res) 649 return res; 650 } 651 652 ctrl = YT921X_FDB_IO2_EGR_PORTS(ports_mask); 653 res = yt921x_reg_write(priv, YT921X_FDB_IN2, ctrl); 654 if (res) 655 return res; 656 657 ctrl = YT921X_FDB_OP_OP_FLUSH | YT921X_FDB_OP_START; 658 if (vid >= 4096) 659 ctrl |= YT921X_FDB_OP_FLUSH_PORT; 660 else 661 ctrl |= YT921X_FDB_OP_FLUSH_PORT_VID; 662 if (flush_static) 663 ctrl |= YT921X_FDB_OP_FLUSH_STATIC; 664 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 665 if (res) 666 return res; 667 668 res = yt921x_fdb_wait(priv, &val); 669 if (res) 670 return res; 671 672 return 0; 673 } 674 675 static int 676 yt921x_fdb_flush_port(struct yt921x_priv *priv, int port, bool flush_static) 677 { 678 return yt921x_fdb_flush_raw(priv, BIT(port), 4096, flush_static); 679 } 680 681 static int 682 yt921x_fdb_add_index_in12(struct yt921x_priv *priv, u16 index, u16 ctrl1, 683 u16 ctrl2) 684 { 685 u32 ctrl; 686 u32 val; 687 int res; 688 689 res = yt921x_reg_write(priv, YT921X_FDB_IN1, ctrl1); 690 if (res) 691 return res; 692 res = yt921x_reg_write(priv, YT921X_FDB_IN2, ctrl2); 693 if (res) 694 return res; 695 696 ctrl = YT921X_FDB_OP_INDEX(index) | YT921X_FDB_OP_MODE_INDEX | 697 YT921X_FDB_OP_OP_ADD | YT921X_FDB_OP_START; 698 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 699 if (res) 700 return res; 701 702 return yt921x_fdb_wait(priv, &val); 703 } 704 705 static int 706 yt921x_fdb_add(struct yt921x_priv *priv, const unsigned char *addr, u16 vid, 707 u16 ports_mask) 708 { 709 u32 ctrl; 710 u32 val; 711 int res; 712 713 ctrl = YT921X_FDB_IO1_STATUS_STATIC; 714 res = yt921x_fdb_in01(priv, addr, vid, ctrl); 715 if (res) 716 return res; 717 718 ctrl = YT921X_FDB_IO2_EGR_PORTS(ports_mask); 719 res = yt921x_reg_write(priv, YT921X_FDB_IN2, ctrl); 720 if (res) 721 return res; 722 723 ctrl = YT921X_FDB_OP_OP_ADD | YT921X_FDB_OP_START; 724 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 725 if (res) 726 return res; 727 728 return yt921x_fdb_wait(priv, &val); 729 } 730 731 static int 732 yt921x_fdb_leave(struct yt921x_priv *priv, const unsigned char *addr, 733 u16 vid, u16 ports_mask) 734 { 735 u16 index; 736 u32 ctrl1; 737 u32 ctrl2; 738 u32 ctrl; 739 u32 val2; 740 u32 val; 741 int res; 742 743 /* Check for presence */ 744 res = yt921x_fdb_has(priv, addr, vid, &index); 745 if (res) 746 return res; 747 if (index >= YT921X_FDB_NUM) 748 return 0; 749 750 /* Check if action required */ 751 res = yt921x_reg_read(priv, YT921X_FDB_OUT2, &val2); 752 if (res) 753 return res; 754 755 ctrl2 = val2 & ~YT921X_FDB_IO2_EGR_PORTS(ports_mask); 756 if (ctrl2 == val2) 757 return 0; 758 if (!(ctrl2 & YT921X_FDB_IO2_EGR_PORTS_M)) { 759 ctrl = YT921X_FDB_OP_OP_DEL | YT921X_FDB_OP_START; 760 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 761 if (res) 762 return res; 763 764 return yt921x_fdb_wait(priv, &val); 765 } 766 767 res = yt921x_reg_read(priv, YT921X_FDB_OUT1, &ctrl1); 768 if (res) 769 return res; 770 771 return yt921x_fdb_add_index_in12(priv, index, ctrl1, ctrl2); 772 } 773 774 static int 775 yt921x_fdb_join(struct yt921x_priv *priv, const unsigned char *addr, u16 vid, 776 u16 ports_mask) 777 { 778 u16 index; 779 u32 ctrl1; 780 u32 ctrl2; 781 u32 val1; 782 u32 val2; 783 int res; 784 785 /* Check for presence */ 786 res = yt921x_fdb_has(priv, addr, vid, &index); 787 if (res) 788 return res; 789 if (index >= YT921X_FDB_NUM) 790 return yt921x_fdb_add(priv, addr, vid, ports_mask); 791 792 /* Check if action required */ 793 res = yt921x_reg_read(priv, YT921X_FDB_OUT1, &val1); 794 if (res) 795 return res; 796 res = yt921x_reg_read(priv, YT921X_FDB_OUT2, &val2); 797 if (res) 798 return res; 799 800 ctrl1 = val1 & ~YT921X_FDB_IO1_STATUS_M; 801 ctrl1 |= YT921X_FDB_IO1_STATUS_STATIC; 802 ctrl2 = val2 | YT921X_FDB_IO2_EGR_PORTS(ports_mask); 803 if (ctrl1 == val1 && ctrl2 == val2) 804 return 0; 805 806 return yt921x_fdb_add_index_in12(priv, index, ctrl1, ctrl2); 807 } 808 809 static int 810 yt921x_dsa_port_fdb_dump(struct dsa_switch *ds, int port, 811 dsa_fdb_dump_cb_t *cb, void *data) 812 { 813 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 814 int res; 815 816 mutex_lock(&priv->reg_lock); 817 /* Hardware FDB is shared for fdb and mdb, "bridge fdb show" 818 * only wants to see unicast 819 */ 820 res = yt921x_fdb_dump(priv, BIT(port), cb, data); 821 mutex_unlock(&priv->reg_lock); 822 823 return res; 824 } 825 826 static void yt921x_dsa_port_fast_age(struct dsa_switch *ds, int port) 827 { 828 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 829 struct device *dev = yt921x_priv_to_device(priv); 830 int res; 831 832 mutex_lock(&priv->reg_lock); 833 res = yt921x_fdb_flush_port(priv, port, false); 834 mutex_unlock(&priv->reg_lock); 835 836 if (res) 837 dev_err(dev, "Failed to %s port %d: %i\n", "clear FDB for", 838 port, res); 839 } 840 841 static int 842 yt921x_dsa_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 843 { 844 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 845 u32 ctrl; 846 int res; 847 848 /* AGEING reg is set in 5s step */ 849 ctrl = clamp(msecs / 5000, 1, U16_MAX); 850 851 mutex_lock(&priv->reg_lock); 852 res = yt921x_reg_write(priv, YT921X_AGEING, ctrl); 853 mutex_unlock(&priv->reg_lock); 854 855 return res; 856 } 857 858 static int 859 yt921x_dsa_port_fdb_del(struct dsa_switch *ds, int port, 860 const unsigned char *addr, u16 vid, struct dsa_db db) 861 { 862 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 863 int res; 864 865 mutex_lock(&priv->reg_lock); 866 res = yt921x_fdb_leave(priv, addr, vid, BIT(port)); 867 mutex_unlock(&priv->reg_lock); 868 869 return res; 870 } 871 872 static int 873 yt921x_dsa_port_fdb_add(struct dsa_switch *ds, int port, 874 const unsigned char *addr, u16 vid, struct dsa_db db) 875 { 876 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 877 int res; 878 879 mutex_lock(&priv->reg_lock); 880 res = yt921x_fdb_join(priv, addr, vid, BIT(port)); 881 mutex_unlock(&priv->reg_lock); 882 883 return res; 884 } 885 886 static int 887 yt921x_dsa_port_mdb_del(struct dsa_switch *ds, int port, 888 const struct switchdev_obj_port_mdb *mdb, 889 struct dsa_db db) 890 { 891 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 892 const unsigned char *addr = mdb->addr; 893 u16 vid = mdb->vid; 894 int res; 895 896 mutex_lock(&priv->reg_lock); 897 res = yt921x_fdb_leave(priv, addr, vid, BIT(port)); 898 mutex_unlock(&priv->reg_lock); 899 900 return res; 901 } 902 903 static int 904 yt921x_dsa_port_mdb_add(struct dsa_switch *ds, int port, 905 const struct switchdev_obj_port_mdb *mdb, 906 struct dsa_db db) 907 { 908 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 909 const unsigned char *addr = mdb->addr; 910 u16 vid = mdb->vid; 911 int res; 912 913 mutex_lock(&priv->reg_lock); 914 res = yt921x_fdb_join(priv, addr, vid, BIT(port)); 915 mutex_unlock(&priv->reg_lock); 916 917 return res; 918 } 919 920 static int 921 yt921x_vlan_aware_set(struct yt921x_priv *priv, int port, bool vlan_aware) 922 { 923 u32 ctrl; 924 925 /* Abuse SVLAN for PCP parsing without polluting the FDB - it just works 926 * despite YT921X_VLAN_CTRL_SVLAN_EN never being set 927 */ 928 if (!vlan_aware) 929 ctrl = YT921X_PORT_IGR_TPIDn_STAG(0); 930 else 931 ctrl = YT921X_PORT_IGR_TPIDn_CTAG(0); 932 return yt921x_reg_write(priv, YT921X_PORTn_IGR_TPID(port), ctrl); 933 } 934 935 static int 936 yt921x_port_set_pvid(struct yt921x_priv *priv, int port, u16 vid) 937 { 938 u32 mask; 939 u32 ctrl; 940 941 mask = YT921X_PORT_VLAN_CTRL_CVID_M; 942 ctrl = YT921X_PORT_VLAN_CTRL_CVID(vid); 943 return yt921x_reg_update_bits(priv, YT921X_PORTn_VLAN_CTRL(port), 944 mask, ctrl); 945 } 946 947 static int 948 yt921x_vlan_filtering(struct yt921x_priv *priv, int port, bool vlan_filtering) 949 { 950 struct dsa_port *dp = dsa_to_port(&priv->ds, port); 951 struct net_device *bdev; 952 u16 pvid; 953 u32 mask; 954 u32 ctrl; 955 int res; 956 957 bdev = dsa_port_bridge_dev_get(dp); 958 959 if (!bdev || !vlan_filtering) 960 pvid = YT921X_VID_UNWARE; 961 else 962 br_vlan_get_pvid(bdev, &pvid); 963 res = yt921x_port_set_pvid(priv, port, pvid); 964 if (res) 965 return res; 966 967 mask = YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_TAGGED | 968 YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_UNTAGGED; 969 ctrl = 0; 970 /* Do not drop tagged frames here; let VLAN_IGR_FILTER do it */ 971 if (vlan_filtering && !pvid) 972 ctrl |= YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_UNTAGGED; 973 res = yt921x_reg_update_bits(priv, YT921X_PORTn_VLAN_CTRL1(port), 974 mask, ctrl); 975 if (res) 976 return res; 977 978 res = yt921x_reg_toggle_bits(priv, YT921X_VLAN_IGR_FILTER, 979 YT921X_VLAN_IGR_FILTER_PORTn(port), 980 vlan_filtering); 981 if (res) 982 return res; 983 984 res = yt921x_vlan_aware_set(priv, port, vlan_filtering); 985 if (res) 986 return res; 987 988 return 0; 989 } 990 991 static int yt921x_vlan_del(struct yt921x_priv *priv, int port, u16 vid) 992 { 993 u32 masks[2]; 994 995 masks[0] = YT921X_VLAN_CTRLa_PORTn(port); 996 masks[1] = YT921X_VLAN_CTRLb_UNTAG_PORTn(port); 997 998 return yt921x_reg64_clear_bits(priv, YT921X_VLANn_CTRL(vid), masks); 999 } 1000 1001 static int 1002 yt921x_vlan_add(struct yt921x_priv *priv, int port, u16 vid, bool untagged) 1003 { 1004 u32 masks[2]; 1005 u32 ctrls[2]; 1006 1007 masks[0] = YT921X_VLAN_CTRLa_PORTn(port) | 1008 YT921X_VLAN_CTRLa_PORTS(priv->cpu_ports_mask); 1009 ctrls[0] = masks[0]; 1010 1011 masks[1] = YT921X_VLAN_CTRLb_UNTAG_PORTn(port); 1012 ctrls[1] = untagged ? masks[1] : 0; 1013 1014 return yt921x_reg64_update_bits(priv, YT921X_VLANn_CTRL(vid), 1015 masks, ctrls); 1016 } 1017 1018 static int 1019 yt921x_pvid_clear(struct yt921x_priv *priv, int port) 1020 { 1021 struct dsa_port *dp = dsa_to_port(&priv->ds, port); 1022 bool vlan_filtering; 1023 u32 mask; 1024 int res; 1025 1026 vlan_filtering = dsa_port_is_vlan_filtering(dp); 1027 1028 res = yt921x_port_set_pvid(priv, port, 1029 vlan_filtering ? 0 : YT921X_VID_UNWARE); 1030 if (res) 1031 return res; 1032 1033 if (vlan_filtering) { 1034 mask = YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_UNTAGGED; 1035 res = yt921x_reg_set_bits(priv, YT921X_PORTn_VLAN_CTRL1(port), 1036 mask); 1037 if (res) 1038 return res; 1039 } 1040 1041 return 0; 1042 } 1043 1044 static int 1045 yt921x_pvid_set(struct yt921x_priv *priv, int port, u16 vid) 1046 { 1047 struct dsa_port *dp = dsa_to_port(&priv->ds, port); 1048 bool vlan_filtering; 1049 u32 mask; 1050 int res; 1051 1052 vlan_filtering = dsa_port_is_vlan_filtering(dp); 1053 1054 if (vlan_filtering) { 1055 res = yt921x_port_set_pvid(priv, port, vid); 1056 if (res) 1057 return res; 1058 } 1059 1060 mask = YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_UNTAGGED; 1061 res = yt921x_reg_clear_bits(priv, YT921X_PORTn_VLAN_CTRL1(port), mask); 1062 if (res) 1063 return res; 1064 1065 return 0; 1066 } 1067 1068 static int 1069 yt921x_dsa_port_vlan_filtering(struct dsa_switch *ds, int port, 1070 bool vlan_filtering, 1071 struct netlink_ext_ack *extack) 1072 { 1073 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 1074 int res; 1075 1076 if (dsa_is_cpu_port(ds, port)) 1077 return 0; 1078 1079 mutex_lock(&priv->reg_lock); 1080 res = yt921x_vlan_filtering(priv, port, vlan_filtering); 1081 mutex_unlock(&priv->reg_lock); 1082 1083 return res; 1084 } 1085 1086 static int 1087 yt921x_dsa_port_vlan_del(struct dsa_switch *ds, int port, 1088 const struct switchdev_obj_port_vlan *vlan) 1089 { 1090 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 1091 u16 vid = vlan->vid; 1092 u16 pvid; 1093 int res; 1094 1095 if (dsa_is_cpu_port(ds, port)) 1096 return 0; 1097 1098 mutex_lock(&priv->reg_lock); 1099 do { 1100 struct dsa_port *dp = dsa_to_port(ds, port); 1101 struct net_device *bdev; 1102 1103 res = yt921x_vlan_del(priv, port, vid); 1104 if (res) 1105 break; 1106 1107 bdev = dsa_port_bridge_dev_get(dp); 1108 if (bdev) { 1109 br_vlan_get_pvid(bdev, &pvid); 1110 if (pvid == vid) 1111 res = yt921x_pvid_clear(priv, port); 1112 } 1113 } while (0); 1114 mutex_unlock(&priv->reg_lock); 1115 1116 return res; 1117 } 1118 1119 static int 1120 yt921x_dsa_port_vlan_add(struct dsa_switch *ds, int port, 1121 const struct switchdev_obj_port_vlan *vlan, 1122 struct netlink_ext_ack *extack) 1123 { 1124 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 1125 u16 vid = vlan->vid; 1126 u16 pvid; 1127 int res; 1128 1129 /* CPU port is supposed to be a member of every VLAN; see 1130 * yt921x_vlan_add() and yt921x_port_setup() 1131 */ 1132 if (dsa_is_cpu_port(ds, port)) 1133 return 0; 1134 1135 mutex_lock(&priv->reg_lock); 1136 do { 1137 struct dsa_port *dp = dsa_to_port(ds, port); 1138 struct net_device *bdev; 1139 1140 res = yt921x_vlan_add(priv, port, vid, 1141 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); 1142 if (res) 1143 break; 1144 1145 bdev = dsa_port_bridge_dev_get(dp); 1146 if (bdev) { 1147 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) { 1148 res = yt921x_pvid_set(priv, port, vid); 1149 } else { 1150 br_vlan_get_pvid(bdev, &pvid); 1151 if (pvid == vid) 1152 res = yt921x_pvid_clear(priv, port); 1153 } 1154 } 1155 } while (0); 1156 mutex_unlock(&priv->reg_lock); 1157 1158 return res; 1159 } 1160 1161 static int yt921x_userport_standalone(struct yt921x_priv *priv, int port) 1162 { 1163 u32 mask; 1164 u32 ctrl; 1165 int res; 1166 1167 ctrl = ~priv->cpu_ports_mask; 1168 res = yt921x_reg_write(priv, YT921X_PORTn_ISOLATION(port), ctrl); 1169 if (res) 1170 return res; 1171 1172 /* Turn off FDB learning to prevent FDB pollution */ 1173 mask = YT921X_PORT_LEARN_DIS; 1174 res = yt921x_reg_set_bits(priv, YT921X_PORTn_LEARN(port), mask); 1175 if (res) 1176 return res; 1177 1178 /* Turn off VLAN awareness */ 1179 res = yt921x_vlan_aware_set(priv, port, false); 1180 if (res) 1181 return res; 1182 1183 /* Unrelated since learning is off and all packets are trapped; 1184 * set it anyway 1185 */ 1186 res = yt921x_port_set_pvid(priv, port, YT921X_VID_UNWARE); 1187 if (res) 1188 return res; 1189 1190 return 0; 1191 } 1192 1193 static int yt921x_userport_bridge(struct yt921x_priv *priv, int port) 1194 { 1195 u32 mask; 1196 int res; 1197 1198 mask = YT921X_PORT_LEARN_DIS; 1199 res = yt921x_reg_clear_bits(priv, YT921X_PORTn_LEARN(port), mask); 1200 if (res) 1201 return res; 1202 1203 return 0; 1204 } 1205 1206 static int yt921x_isolate(struct yt921x_priv *priv, int port) 1207 { 1208 u32 mask; 1209 int res; 1210 1211 mask = BIT(port); 1212 for (int i = 0; i < YT921X_PORT_NUM; i++) { 1213 if ((BIT(i) & priv->cpu_ports_mask) || i == port) 1214 continue; 1215 1216 res = yt921x_reg_set_bits(priv, YT921X_PORTn_ISOLATION(i), 1217 mask); 1218 if (res) 1219 return res; 1220 } 1221 1222 return 0; 1223 } 1224 1225 /* Make sure to include the CPU port in ports_mask, or your bridge will 1226 * not have it. 1227 */ 1228 static int yt921x_bridge(struct yt921x_priv *priv, u16 ports_mask) 1229 { 1230 unsigned long targets_mask = ports_mask & ~priv->cpu_ports_mask; 1231 u32 isolated_mask; 1232 u32 ctrl; 1233 int port; 1234 int res; 1235 1236 isolated_mask = 0; 1237 for_each_set_bit(port, &targets_mask, YT921X_PORT_NUM) { 1238 struct yt921x_port *pp = &priv->ports[port]; 1239 1240 if (pp->isolated) 1241 isolated_mask |= BIT(port); 1242 } 1243 1244 /* Block from non-cpu bridge ports ... */ 1245 for_each_set_bit(port, &targets_mask, YT921X_PORT_NUM) { 1246 struct yt921x_port *pp = &priv->ports[port]; 1247 1248 /* to non-bridge ports */ 1249 ctrl = ~ports_mask; 1250 /* to isolated ports when isolated */ 1251 if (pp->isolated) 1252 ctrl |= isolated_mask; 1253 /* to itself when non-hairpin */ 1254 if (!pp->hairpin) 1255 ctrl |= BIT(port); 1256 else 1257 ctrl &= ~BIT(port); 1258 1259 res = yt921x_reg_write(priv, YT921X_PORTn_ISOLATION(port), 1260 ctrl); 1261 if (res) 1262 return res; 1263 } 1264 1265 return 0; 1266 } 1267 1268 static int yt921x_bridge_leave(struct yt921x_priv *priv, int port) 1269 { 1270 int res; 1271 1272 res = yt921x_userport_standalone(priv, port); 1273 if (res) 1274 return res; 1275 1276 res = yt921x_isolate(priv, port); 1277 if (res) 1278 return res; 1279 1280 return 0; 1281 } 1282 1283 static int 1284 yt921x_bridge_join(struct yt921x_priv *priv, int port, u16 ports_mask) 1285 { 1286 int res; 1287 1288 res = yt921x_userport_bridge(priv, port); 1289 if (res) 1290 return res; 1291 1292 res = yt921x_bridge(priv, ports_mask); 1293 if (res) 1294 return res; 1295 1296 return 0; 1297 } 1298 1299 static int 1300 yt921x_bridge_flags(struct yt921x_priv *priv, int port, 1301 struct switchdev_brport_flags flags) 1302 { 1303 struct yt921x_port *pp = &priv->ports[port]; 1304 bool do_flush; 1305 u32 mask; 1306 int res; 1307 1308 if (flags.mask & BR_LEARNING) { 1309 bool learning = flags.val & BR_LEARNING; 1310 1311 mask = YT921X_PORT_LEARN_DIS; 1312 res = yt921x_reg_toggle_bits(priv, YT921X_PORTn_LEARN(port), 1313 mask, !learning); 1314 if (res) 1315 return res; 1316 } 1317 1318 /* BR_FLOOD, BR_MCAST_FLOOD: see the comment where ACT_UNK_ACTn_TRAP 1319 * is set 1320 */ 1321 1322 /* BR_BCAST_FLOOD: we can filter bcast, but cannot trap them */ 1323 1324 do_flush = false; 1325 if (flags.mask & BR_HAIRPIN_MODE) { 1326 pp->hairpin = flags.val & BR_HAIRPIN_MODE; 1327 do_flush = true; 1328 } 1329 if (flags.mask & BR_ISOLATED) { 1330 pp->isolated = flags.val & BR_ISOLATED; 1331 do_flush = true; 1332 } 1333 if (do_flush) { 1334 struct dsa_switch *ds = &priv->ds; 1335 struct dsa_port *dp = dsa_to_port(ds, port); 1336 struct net_device *bdev; 1337 1338 bdev = dsa_port_bridge_dev_get(dp); 1339 if (bdev) { 1340 u32 ports_mask; 1341 1342 ports_mask = dsa_bridge_ports(ds, bdev); 1343 ports_mask |= priv->cpu_ports_mask; 1344 res = yt921x_bridge(priv, ports_mask); 1345 if (res) 1346 return res; 1347 } 1348 } 1349 1350 return 0; 1351 } 1352 1353 static int 1354 yt921x_dsa_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1355 struct switchdev_brport_flags flags, 1356 struct netlink_ext_ack *extack) 1357 { 1358 if (flags.mask & ~(BR_HAIRPIN_MODE | BR_LEARNING | BR_FLOOD | 1359 BR_MCAST_FLOOD | BR_ISOLATED)) 1360 return -EINVAL; 1361 return 0; 1362 } 1363 1364 static int 1365 yt921x_dsa_port_bridge_flags(struct dsa_switch *ds, int port, 1366 struct switchdev_brport_flags flags, 1367 struct netlink_ext_ack *extack) 1368 { 1369 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 1370 int res; 1371 1372 if (dsa_is_cpu_port(ds, port)) 1373 return 0; 1374 1375 mutex_lock(&priv->reg_lock); 1376 res = yt921x_bridge_flags(priv, port, flags); 1377 mutex_unlock(&priv->reg_lock); 1378 1379 return res; 1380 } 1381 1382 static void 1383 yt921x_dsa_port_bridge_leave(struct dsa_switch *ds, int port, 1384 struct dsa_bridge bridge) 1385 { 1386 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 1387 struct device *dev = yt921x_priv_to_device(priv); 1388 int res; 1389 1390 if (dsa_is_cpu_port(ds, port)) 1391 return; 1392 1393 mutex_lock(&priv->reg_lock); 1394 res = yt921x_bridge_leave(priv, port); 1395 mutex_unlock(&priv->reg_lock); 1396 1397 if (res) 1398 dev_err(dev, "Failed to %s port %d: %i\n", "unbridge", 1399 port, res); 1400 } 1401 1402 static int 1403 yt921x_dsa_port_bridge_join(struct dsa_switch *ds, int port, 1404 struct dsa_bridge bridge, bool *tx_fwd_offload, 1405 struct netlink_ext_ack *extack) 1406 { 1407 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 1408 u16 ports_mask; 1409 int res; 1410 1411 if (dsa_is_cpu_port(ds, port)) 1412 return 0; 1413 1414 ports_mask = dsa_bridge_ports(ds, bridge.dev); 1415 ports_mask |= priv->cpu_ports_mask; 1416 1417 mutex_lock(&priv->reg_lock); 1418 res = yt921x_bridge_join(priv, port, ports_mask); 1419 mutex_unlock(&priv->reg_lock); 1420 1421 return res; 1422 } 1423 1424 static int 1425 yt921x_dsa_port_mst_state_set(struct dsa_switch *ds, int port, 1426 const struct switchdev_mst_state *st) 1427 { 1428 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 1429 u32 mask; 1430 u32 ctrl; 1431 int res; 1432 1433 mask = YT921X_STP_PORTn_M(port); 1434 switch (st->state) { 1435 case BR_STATE_DISABLED: 1436 ctrl = YT921X_STP_PORTn_DISABLED(port); 1437 break; 1438 case BR_STATE_LISTENING: 1439 case BR_STATE_LEARNING: 1440 ctrl = YT921X_STP_PORTn_LEARNING(port); 1441 break; 1442 case BR_STATE_FORWARDING: 1443 default: 1444 ctrl = YT921X_STP_PORTn_FORWARD(port); 1445 break; 1446 case BR_STATE_BLOCKING: 1447 ctrl = YT921X_STP_PORTn_BLOCKING(port); 1448 break; 1449 } 1450 1451 mutex_lock(&priv->reg_lock); 1452 res = yt921x_reg_update_bits(priv, YT921X_STPn(st->msti), mask, ctrl); 1453 mutex_unlock(&priv->reg_lock); 1454 1455 return res; 1456 } 1457 1458 static int 1459 yt921x_dsa_vlan_msti_set(struct dsa_switch *ds, struct dsa_bridge bridge, 1460 const struct switchdev_vlan_msti *msti) 1461 { 1462 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 1463 u32 masks[2]; 1464 u32 ctrls[2]; 1465 int res; 1466 1467 if (!msti->vid) 1468 return -EINVAL; 1469 if (!msti->msti || msti->msti >= YT921X_MSTI_NUM) 1470 return -EINVAL; 1471 1472 masks[0] = 0; 1473 ctrls[0] = 0; 1474 masks[1] = YT921X_VLAN_CTRLb_STP_ID_M; 1475 ctrls[1] = YT921X_VLAN_CTRLb_STP_ID(msti->msti); 1476 1477 mutex_lock(&priv->reg_lock); 1478 res = yt921x_reg64_update_bits(priv, YT921X_VLANn_CTRL(msti->vid), 1479 masks, ctrls); 1480 mutex_unlock(&priv->reg_lock); 1481 1482 return res; 1483 } 1484 1485 static void 1486 yt921x_dsa_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1487 { 1488 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 1489 struct device *dev = yt921x_priv_to_device(priv); 1490 struct dsa_port *dp = dsa_to_port(ds, port); 1491 bool learning; 1492 u32 mask; 1493 u32 ctrl; 1494 int res; 1495 1496 mask = YT921X_STP_PORTn_M(port); 1497 learning = false; 1498 switch (state) { 1499 case BR_STATE_DISABLED: 1500 ctrl = YT921X_STP_PORTn_DISABLED(port); 1501 break; 1502 case BR_STATE_LISTENING: 1503 ctrl = YT921X_STP_PORTn_LEARNING(port); 1504 break; 1505 case BR_STATE_LEARNING: 1506 ctrl = YT921X_STP_PORTn_LEARNING(port); 1507 learning = dp->learning; 1508 break; 1509 case BR_STATE_FORWARDING: 1510 default: 1511 ctrl = YT921X_STP_PORTn_FORWARD(port); 1512 learning = dp->learning; 1513 break; 1514 case BR_STATE_BLOCKING: 1515 ctrl = YT921X_STP_PORTn_BLOCKING(port); 1516 break; 1517 } 1518 1519 mutex_lock(&priv->reg_lock); 1520 do { 1521 res = yt921x_reg_update_bits(priv, YT921X_STPn(0), mask, ctrl); 1522 if (res) 1523 break; 1524 1525 mask = YT921X_PORT_LEARN_DIS; 1526 ctrl = !learning ? YT921X_PORT_LEARN_DIS : 0; 1527 res = yt921x_reg_update_bits(priv, YT921X_PORTn_LEARN(port), 1528 mask, ctrl); 1529 } while (0); 1530 mutex_unlock(&priv->reg_lock); 1531 1532 if (res) 1533 dev_err(dev, "Failed to %s port %d: %i\n", "set STP state for", 1534 port, res); 1535 } 1536 1537 static int __maybe_unused 1538 yt921x_dsa_port_get_default_prio(struct dsa_switch *ds, int port) 1539 { 1540 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 1541 u32 val; 1542 int res; 1543 1544 mutex_lock(&priv->reg_lock); 1545 res = yt921x_reg_read(priv, YT921X_PORTn_QOS(port), &val); 1546 mutex_unlock(&priv->reg_lock); 1547 1548 if (res) 1549 return res; 1550 1551 return FIELD_GET(YT921X_PORT_QOS_PRIO_M, val); 1552 } 1553 1554 static int __maybe_unused 1555 yt921x_dsa_port_set_default_prio(struct dsa_switch *ds, int port, u8 prio) 1556 { 1557 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 1558 u32 mask; 1559 u32 ctrl; 1560 int res; 1561 1562 if (prio >= YT921X_PRIO_NUM) 1563 return -EINVAL; 1564 1565 mutex_lock(&priv->reg_lock); 1566 mask = YT921X_PORT_QOS_PRIO_M | YT921X_PORT_QOS_PRIO_EN; 1567 ctrl = YT921X_PORT_QOS_PRIO(prio) | YT921X_PORT_QOS_PRIO_EN; 1568 res = yt921x_reg_update_bits(priv, YT921X_PORTn_QOS(port), mask, ctrl); 1569 mutex_unlock(&priv->reg_lock); 1570 1571 return res; 1572 } 1573 1574 static int __maybe_unused appprios_cmp(const void *a, const void *b) 1575 { 1576 return ((const u8 *)b)[1] - ((const u8 *)a)[1]; 1577 } 1578 1579 static int __maybe_unused 1580 yt921x_dsa_port_get_apptrust(struct dsa_switch *ds, int port, u8 *sel, 1581 int *nselp) 1582 { 1583 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 1584 u8 appprios[2][2] = {}; 1585 int nsel; 1586 u32 val; 1587 int res; 1588 1589 mutex_lock(&priv->reg_lock); 1590 res = yt921x_reg_read(priv, YT921X_PORTn_PRIO_ORD(port), &val); 1591 mutex_unlock(&priv->reg_lock); 1592 1593 if (res) 1594 return res; 1595 1596 appprios[0][0] = IEEE_8021QAZ_APP_SEL_DSCP; 1597 appprios[0][1] = (val >> (3 * YT921X_APP_SEL_DSCP)) & 7; 1598 appprios[1][0] = DCB_APP_SEL_PCP; 1599 appprios[1][1] = (val >> (3 * YT921X_APP_SEL_CVLAN_PCP)) & 7; 1600 sort(appprios, ARRAY_SIZE(appprios), sizeof(appprios[0]), appprios_cmp, 1601 NULL); 1602 1603 nsel = 0; 1604 for (int i = 0; i < ARRAY_SIZE(appprios) && appprios[i][1]; i++) { 1605 sel[nsel] = appprios[i][0]; 1606 nsel++; 1607 } 1608 *nselp = nsel; 1609 1610 return 0; 1611 } 1612 1613 static int __maybe_unused 1614 yt921x_dsa_port_set_apptrust(struct dsa_switch *ds, int port, const u8 *sel, 1615 int nsel) 1616 { 1617 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 1618 struct device *dev = yt921x_priv_to_device(priv); 1619 u32 ctrl; 1620 int res; 1621 1622 if (nsel > YT921X_APP_SEL_NUM) 1623 return -EINVAL; 1624 1625 ctrl = 0; 1626 for (int i = 0; i < nsel; i++) { 1627 switch (sel[i]) { 1628 case IEEE_8021QAZ_APP_SEL_DSCP: 1629 ctrl |= YT921X_PORT_PRIO_ORD_APPm(YT921X_APP_SEL_DSCP, 1630 7 - i); 1631 break; 1632 case DCB_APP_SEL_PCP: 1633 ctrl |= YT921X_PORT_PRIO_ORD_APPm(YT921X_APP_SEL_CVLAN_PCP, 1634 7 - i); 1635 ctrl |= YT921X_PORT_PRIO_ORD_APPm(YT921X_APP_SEL_SVLAN_PCP, 1636 7 - i); 1637 break; 1638 default: 1639 dev_err(dev, 1640 "Invalid apptrust selector (at %d-th). Supported: dscp, pcp\n", 1641 i + 1); 1642 return -EOPNOTSUPP; 1643 } 1644 } 1645 1646 mutex_lock(&priv->reg_lock); 1647 res = yt921x_reg_write(priv, YT921X_PORTn_PRIO_ORD(port), ctrl); 1648 mutex_unlock(&priv->reg_lock); 1649 1650 return res; 1651 } 1652 1653 static int yt921x_port_down(struct yt921x_priv *priv, int port) 1654 { 1655 const struct yt921x_info *info = priv->info; 1656 u32 mask; 1657 int res; 1658 1659 mask = YT921X_PORT_CTRL_LINK_AN | YT921X_PORT_RX_MAC_EN | 1660 YT921X_PORT_TX_MAC_EN; 1661 res = yt921x_reg_clear_bits(priv, YT921X_PORTn_CTRL(port), mask); 1662 if (res) 1663 return res; 1664 1665 if (BIT(port) & info->serdes_mask) { 1666 mask = YT921X_SERDES_LINK; 1667 res = yt921x_reg_clear_bits(priv, YT921X_SERDESn(port), mask); 1668 if (res) 1669 return res; 1670 } 1671 if (BIT(port) & info->xmii_mask) { 1672 mask = YT921X_XMII_LINK; 1673 res = yt921x_reg_clear_bits(priv, YT921X_XMIIn(port), mask); 1674 if (res) 1675 return res; 1676 } 1677 1678 return 0; 1679 } 1680 1681 static int 1682 yt921x_port_up(struct yt921x_priv *priv, int port, unsigned int mode, 1683 phy_interface_t interface, int speed, int duplex, 1684 bool tx_pause, bool rx_pause) 1685 { 1686 const struct yt921x_info *info = priv->info; 1687 struct yt921x_port *pp = &priv->ports[port]; 1688 int ps = ethtool_speed_to_yt921x(speed); 1689 u32 mask; 1690 u32 ctrl; 1691 int res; 1692 1693 if (ps == YT921X_SPEED_INVALID) 1694 return -EINVAL; 1695 1696 mask = YT921X_PORT_SPEED_M | YT921X_PORT_TX_MAC_EN | 1697 YT921X_PORT_RX_MAC_EN | YT921X_PORT_TX_PAUSE | 1698 YT921X_PORT_RX_PAUSE | YT921X_PORT_DUPLEX_FULL | 1699 YT921X_PORT_CTRL_LINK_AN; 1700 ctrl = YT921X_PORT_SPEED(ps); 1701 if (duplex == DUPLEX_FULL) 1702 ctrl |= YT921X_PORT_DUPLEX_FULL; 1703 if (tx_pause) 1704 ctrl |= YT921X_PORT_TX_PAUSE; 1705 if (rx_pause) 1706 ctrl |= YT921X_PORT_RX_PAUSE; 1707 ctrl |= YT921X_PORT_RX_MAC_EN | YT921X_PORT_TX_MAC_EN; 1708 if (pp->serdes && pp->inband) 1709 ctrl |= YT921X_PORT_CTRL_LINK_AN; 1710 res = yt921x_reg_update_bits(priv, YT921X_PORTn_CTRL(port), mask, ctrl); 1711 if (res) 1712 return res; 1713 1714 if (!(BIT(port) & (info->serdes_mask | info->xmii_mask))) 1715 return 0; 1716 1717 if (pp->serdes) { 1718 mask = YT921X_SERDES_SPEED_M; 1719 ctrl = YT921X_SERDES_SPEED(ps); 1720 mask |= YT921X_SERDES_DUPLEX_FULL; 1721 if (duplex == DUPLEX_FULL) 1722 ctrl |= YT921X_SERDES_DUPLEX_FULL; 1723 mask |= YT921X_SERDES_TX_PAUSE; 1724 if (tx_pause) 1725 ctrl |= YT921X_SERDES_TX_PAUSE; 1726 mask |= YT921X_SERDES_RX_PAUSE; 1727 if (rx_pause) 1728 ctrl |= YT921X_SERDES_RX_PAUSE; 1729 mask |= YT921X_SERDES_LINK; 1730 if (!pp->inband) 1731 ctrl |= YT921X_SERDES_LINK; 1732 res = yt921x_reg_update_bits(priv, YT921X_SERDESn(port), 1733 mask, ctrl); 1734 if (res) 1735 return res; 1736 } else { 1737 mask = YT921X_XMII_LINK; 1738 res = yt921x_reg_set_bits(priv, YT921X_XMIIn(port), mask); 1739 if (res) 1740 return res; 1741 1742 ctrl = YT921X_MDIO_POLLING_SPEED(ps); 1743 if (duplex == DUPLEX_FULL) 1744 ctrl |= YT921X_MDIO_POLLING_DUPLEX_FULL; 1745 ctrl |= YT921X_MDIO_POLLING_LINK; 1746 res = yt921x_reg_write(priv, YT921X_MDIO_POLLINGn(port), ctrl); 1747 if (res) 1748 return res; 1749 } 1750 1751 return 0; 1752 } 1753 1754 static int 1755 yt921x_port_config(struct yt921x_priv *priv, int port, unsigned int mode, 1756 phy_interface_t interface) 1757 { 1758 struct device *dev = yt921x_priv_to_device(priv); 1759 const struct yt921x_info *info = priv->info; 1760 struct yt921x_port *pp = &priv->ports[port]; 1761 u32 mask; 1762 int res; 1763 1764 if (BIT(port) & info->internal_mask) { 1765 if (interface != PHY_INTERFACE_MODE_INTERNAL) 1766 goto err; 1767 return 0; 1768 } 1769 1770 switch (interface) { 1771 /* SERDES */ 1772 case PHY_INTERFACE_MODE_SGMII: 1773 case PHY_INTERFACE_MODE_100BASEX: 1774 case PHY_INTERFACE_MODE_1000BASEX: 1775 case PHY_INTERFACE_MODE_2500BASEX: 1776 if (!(BIT(port) & info->serdes_mask)) 1777 goto err; 1778 1779 mask = YT921X_SERDES_CTRL_PORTn(port); 1780 res = yt921x_reg_set_bits(priv, YT921X_SERDES_CTRL, mask); 1781 if (res) 1782 return res; 1783 1784 mask = YT921X_XMII_CTRL_PORTn(port); 1785 res = yt921x_reg_clear_bits(priv, YT921X_XMII_CTRL, mask); 1786 if (res) 1787 return res; 1788 1789 /* The order is quite arbitrary - we can't return to a safe 1790 * state on IO errors. 1791 */ 1792 pp->serdes = true; 1793 1794 break; 1795 /* add XMII support here */ 1796 default: 1797 goto err; 1798 } 1799 1800 return 0; 1801 1802 err: 1803 dev_err(dev, "Wrong mode %d on port %d\n", interface, port); 1804 return -EINVAL; 1805 } 1806 1807 static struct phylink_pcs * 1808 yt921x_phylink_mac_select_pcs(struct phylink_config *config, 1809 phy_interface_t interface) 1810 { 1811 struct dsa_port *dp = dsa_phylink_to_port(config); 1812 struct yt921x_priv *priv = dsa_to_yt921x_priv(dp->ds); 1813 const struct yt921x_info *info = priv->info; 1814 int port = dp->index; 1815 1816 if (!(BIT(port) & info->serdes_mask)) 1817 return NULL; 1818 1819 switch (interface) { 1820 case PHY_INTERFACE_MODE_SGMII: 1821 case PHY_INTERFACE_MODE_100BASEX: 1822 case PHY_INTERFACE_MODE_1000BASEX: 1823 case PHY_INTERFACE_MODE_2500BASEX: 1824 return &priv->ports[port].pcs; 1825 default: 1826 return NULL; 1827 } 1828 } 1829 1830 static void 1831 yt921x_phylink_mac_link_down(struct phylink_config *config, unsigned int mode, 1832 phy_interface_t interface) 1833 { 1834 struct dsa_port *dp = dsa_phylink_to_port(config); 1835 struct yt921x_priv *priv = dsa_to_yt921x_priv(dp->ds); 1836 struct yt921x_mib *pm; 1837 int port = dp->index; 1838 int res; 1839 1840 /* No need to sync; port control block is hold until device remove */ 1841 pm = priv->ports[port].mib; 1842 if (pm) 1843 cancel_delayed_work(&pm->work); 1844 1845 mutex_lock(&priv->reg_lock); 1846 res = yt921x_port_down(priv, port); 1847 mutex_unlock(&priv->reg_lock); 1848 1849 if (res) 1850 dev_err(dp->ds->dev, "Failed to %s port %d: %i\n", "bring down", 1851 port, res); 1852 } 1853 1854 static void 1855 yt921x_phylink_mac_link_up(struct phylink_config *config, 1856 struct phy_device *phydev, unsigned int mode, 1857 phy_interface_t interface, int speed, int duplex, 1858 bool tx_pause, bool rx_pause) 1859 { 1860 struct dsa_port *dp = dsa_phylink_to_port(config); 1861 struct yt921x_priv *priv = dsa_to_yt921x_priv(dp->ds); 1862 struct yt921x_mib *pm; 1863 int port = dp->index; 1864 int res; 1865 1866 mutex_lock(&priv->reg_lock); 1867 res = yt921x_port_up(priv, port, mode, interface, speed, duplex, 1868 tx_pause, rx_pause); 1869 mutex_unlock(&priv->reg_lock); 1870 1871 if (res) 1872 dev_err(dp->ds->dev, "Failed to %s port %d: %i\n", "bring up", 1873 port, res); 1874 1875 pm = priv->ports[port].mib; 1876 if (pm) 1877 schedule_delayed_work(&pm->work, 0); 1878 } 1879 1880 static void 1881 yt921x_phylink_mac_config(struct phylink_config *config, unsigned int mode, 1882 const struct phylink_link_state *state) 1883 { 1884 struct dsa_port *dp = dsa_phylink_to_port(config); 1885 struct yt921x_priv *priv = dsa_to_yt921x_priv(dp->ds); 1886 int port = dp->index; 1887 int res; 1888 1889 mutex_lock(&priv->reg_lock); 1890 res = yt921x_port_config(priv, port, mode, state->interface); 1891 mutex_unlock(&priv->reg_lock); 1892 1893 if (res) 1894 dev_err(dp->ds->dev, "Failed to %s port %d: %i\n", "config", 1895 port, res); 1896 } 1897 1898 static void 1899 yt921x_dsa_phylink_get_caps(struct dsa_switch *ds, int port, 1900 struct phylink_config *config) 1901 { 1902 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 1903 const struct yt921x_info *info = priv->info; 1904 1905 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1906 MAC_10 | MAC_100 | MAC_1000; 1907 1908 if (info->internal_mask & BIT(port)) { 1909 /* Port 10 for MCU should probably go here too. But since that 1910 * is untested yet, turn it down for the moment by letting it 1911 * fall to the default branch. 1912 */ 1913 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1914 config->supported_interfaces); 1915 return; 1916 } 1917 1918 if (BIT(port) & info->serdes_mask) { 1919 __set_bit(PHY_INTERFACE_MODE_SGMII, 1920 config->supported_interfaces); 1921 /* REVSGMII (SGMII in PHY role) should go here, once 1922 * PHY_INTERFACE_MODE_REVSGMII is introduced. 1923 */ 1924 __set_bit(PHY_INTERFACE_MODE_100BASEX, 1925 config->supported_interfaces); 1926 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 1927 config->supported_interfaces); 1928 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 1929 config->supported_interfaces); 1930 config->mac_capabilities |= MAC_2500FD; 1931 } 1932 if (BIT(port) & info->xmii_mask) { 1933 /* Not tested. To add support for XMII: 1934 * - Add proper interface modes below 1935 * - Handle them in yt921x_port_config() 1936 */ 1937 } 1938 /* no such port: empty supported_interfaces causes phylink to turn it 1939 * down 1940 */ 1941 } 1942 1943 static int yt921x_port_setup(struct yt921x_priv *priv, int port) 1944 { 1945 struct dsa_switch *ds = &priv->ds; 1946 u32 ctrl; 1947 int res; 1948 1949 res = yt921x_userport_standalone(priv, port); 1950 if (res) 1951 return res; 1952 1953 /* Clear prio order (even if DCB is not enabled) to avoid unsolicited 1954 * priorities 1955 */ 1956 res = yt921x_reg_write(priv, YT921X_PORTn_PRIO_ORD(port), 0); 1957 if (res) 1958 return res; 1959 1960 if (dsa_is_cpu_port(ds, port)) { 1961 /* Egress of CPU port is supposed to be completely controlled 1962 * via tagging, so set to oneway isolated (drop all packets 1963 * without tag). 1964 */ 1965 ctrl = ~(u32)0; 1966 res = yt921x_reg_write(priv, YT921X_PORTn_ISOLATION(port), 1967 ctrl); 1968 if (res) 1969 return res; 1970 1971 /* To simplify FDB "isolation" simulation, we also disable 1972 * learning on the CPU port, and let software identify packets 1973 * towarding CPU (either trapped or a static FDB entry is 1974 * matched, no matter which bridge that entry is for), which is 1975 * already done by yt921x_userport_standalone(). As a result, 1976 * VLAN-awareness becomes unrelated on the CPU port (set to 1977 * VLAN-unaware by the way). 1978 */ 1979 } 1980 1981 return 0; 1982 } 1983 1984 static enum dsa_tag_protocol 1985 yt921x_dsa_get_tag_protocol(struct dsa_switch *ds, int port, 1986 enum dsa_tag_protocol m) 1987 { 1988 return DSA_TAG_PROTO_YT921X; 1989 } 1990 1991 static void yt921x_dsa_port_teardown(struct dsa_switch *ds, int port) 1992 { 1993 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 1994 struct yt921x_port *pp = &priv->ports[port]; 1995 struct yt921x_mib *pm = pp->mib; 1996 1997 /* get_stats64() might not be synchronized with port_teardown(), hold 1998 * the MIB block till the device teardown 1999 */ 2000 if (pm) 2001 disable_delayed_work_sync(&pm->work); 2002 } 2003 2004 static int yt921x_dsa_port_setup(struct dsa_switch *ds, int port) 2005 { 2006 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 2007 struct yt921x_port *pp = &priv->ports[port]; 2008 const struct yt921x_info *info = priv->info; 2009 struct device *dev = yt921x_priv_to_device(priv); 2010 struct yt921x_mib *pm = pp->mib; 2011 int res; 2012 2013 if (!pm && (BIT(port) & yt921x_info_ports_mask(info))) { 2014 pm = devm_kzalloc(dev, sizeof(*pm), GFP_KERNEL); 2015 if (!pm) 2016 return -ENOMEM; 2017 pp->mib = pm; 2018 2019 pm->port = pp; 2020 u64_stats_init(&pm->syncp); 2021 INIT_DELAYED_WORK(&pm->work, yt921x_mib_poll); 2022 /* Start disabled, so that the enable below always pairs with 2023 * either this disable or the one from a previous teardown 2024 */ 2025 disable_delayed_work_sync(&pm->work); 2026 } 2027 2028 mutex_lock(&priv->reg_lock); 2029 res = yt921x_port_setup(priv, port); 2030 mutex_unlock(&priv->reg_lock); 2031 if (res) 2032 return res; 2033 2034 if (pm) 2035 enable_delayed_work(&pm->work); 2036 2037 return 0; 2038 } 2039 2040 /* Not "port" - DSCP mapping is global */ 2041 static int __maybe_unused 2042 yt921x_dsa_port_get_dscp_prio(struct dsa_switch *ds, int port, u8 dscp) 2043 { 2044 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 2045 u32 val; 2046 int res; 2047 2048 mutex_lock(&priv->reg_lock); 2049 res = yt921x_reg_read(priv, YT921X_IPM_DSCPn(dscp), &val); 2050 mutex_unlock(&priv->reg_lock); 2051 2052 if (res) 2053 return res; 2054 2055 return FIELD_GET(YT921X_IPM_PRIO_M, val); 2056 } 2057 2058 static int __maybe_unused 2059 yt921x_dsa_port_del_dscp_prio(struct dsa_switch *ds, int port, u8 dscp, u8 prio) 2060 { 2061 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 2062 u32 val; 2063 int res; 2064 2065 mutex_lock(&priv->reg_lock); 2066 /* During a "dcb app replace" command, the new app table entry will be 2067 * added first, then the old one will be deleted. But the hardware only 2068 * supports one QoS class per DSCP value (duh), so if we blindly delete 2069 * the app table entry for this DSCP value, we end up deleting the 2070 * entry with the new priority. Avoid that by checking whether user 2071 * space wants to delete the priority which is currently configured, or 2072 * something else which is no longer current. 2073 */ 2074 res = yt921x_reg_read(priv, YT921X_IPM_DSCPn(dscp), &val); 2075 if (!res && FIELD_GET(YT921X_IPM_PRIO_M, val) == prio) 2076 res = yt921x_reg_write(priv, YT921X_IPM_DSCPn(dscp), 2077 YT921X_IPM_PRIO(IEEE8021Q_TT_BK)); 2078 mutex_unlock(&priv->reg_lock); 2079 2080 return res; 2081 } 2082 2083 static int __maybe_unused 2084 yt921x_dsa_port_add_dscp_prio(struct dsa_switch *ds, int port, u8 dscp, u8 prio) 2085 { 2086 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 2087 int res; 2088 2089 if (prio >= YT921X_PRIO_NUM) 2090 return -EINVAL; 2091 2092 mutex_lock(&priv->reg_lock); 2093 res = yt921x_reg_write(priv, YT921X_IPM_DSCPn(dscp), 2094 YT921X_IPM_PRIO(prio)); 2095 mutex_unlock(&priv->reg_lock); 2096 2097 return res; 2098 } 2099 2100 static int yt921x_edata_wait(struct yt921x_priv *priv, u32 *valp) 2101 { 2102 u32 val = YT921X_EDATA_DATA_IDLE; 2103 int res; 2104 2105 res = yt921x_reg_wait(priv, YT921X_EDATA_DATA, 2106 YT921X_EDATA_DATA_STATUS_M, &val); 2107 if (res) 2108 return res; 2109 2110 *valp = val; 2111 return 0; 2112 } 2113 2114 static int 2115 yt921x_edata_read_cont(struct yt921x_priv *priv, u8 addr, u8 *valp) 2116 { 2117 u32 ctrl; 2118 u32 val; 2119 int res; 2120 2121 ctrl = YT921X_EDATA_CTRL_ADDR(addr) | YT921X_EDATA_CTRL_READ; 2122 res = yt921x_reg_write(priv, YT921X_EDATA_CTRL, ctrl); 2123 if (res) 2124 return res; 2125 res = yt921x_edata_wait(priv, &val); 2126 if (res) 2127 return res; 2128 2129 *valp = FIELD_GET(YT921X_EDATA_DATA_DATA_M, val); 2130 return 0; 2131 } 2132 2133 static int yt921x_edata_read(struct yt921x_priv *priv, u8 addr, u8 *valp) 2134 { 2135 u32 val; 2136 int res; 2137 2138 res = yt921x_edata_wait(priv, &val); 2139 if (res) 2140 return res; 2141 return yt921x_edata_read_cont(priv, addr, valp); 2142 } 2143 2144 static void yt921x_dsa_teardown(struct dsa_switch *ds) 2145 { 2146 #if IS_ENABLED(CONFIG_NET_DSA_YT921X_LEDS) 2147 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 2148 2149 yt921x_leds_remove(priv); 2150 #endif 2151 } 2152 2153 static int yt921x_chip_detect(struct yt921x_priv *priv) 2154 { 2155 struct device *dev = yt921x_priv_to_device(priv); 2156 const struct yt921x_info *info; 2157 u8 extmode; 2158 u32 chipid; 2159 u32 major; 2160 u32 mode; 2161 u32 val; 2162 int res; 2163 2164 res = yt921x_reg_read(priv, YT921X_CHIP_ID, &chipid); 2165 if (res) 2166 return res; 2167 2168 major = FIELD_GET(YT921X_CHIP_ID_MAJOR, chipid); 2169 2170 for (info = yt921x_infos; info->name; info++) 2171 if (info->major == major) 2172 break; 2173 if (!info->name) { 2174 dev_err(dev, "Unexpected chipid 0x%x\n", chipid); 2175 return -ENODEV; 2176 } 2177 2178 res = yt921x_reg_read(priv, YT921X_CHIP_MODE, &mode); 2179 if (res) 2180 return res; 2181 res = yt921x_edata_read(priv, YT921X_EDATA_EXTMODE, &extmode); 2182 if (res) 2183 return res; 2184 2185 for (; info->name; info++) 2186 if (info->major == major && info->mode == mode && 2187 info->extmode == extmode) 2188 break; 2189 if (!info->name) { 2190 dev_err(dev, 2191 "Unsupported chipid 0x%x with chipmode 0x%x 0x%x\n", 2192 chipid, mode, extmode); 2193 return -ENODEV; 2194 } 2195 2196 res = yt921x_reg_read(priv, YT921X_SYS_CLK, &val); 2197 if (res) 2198 return res; 2199 switch (FIELD_GET(YT921X_SYS_CLK_SEL_M, val)) { 2200 case 0: 2201 priv->cycle_ns = info->major == YT9215_MAJOR ? 8 : 6; 2202 break; 2203 case YT921X_SYS_CLK_143M: 2204 priv->cycle_ns = 7; 2205 break; 2206 default: 2207 priv->cycle_ns = 8; 2208 } 2209 2210 /* Print chipid here since we are interested in lower 16 bits */ 2211 dev_info(dev, 2212 "Motorcomm %s ethernet switch, chipid: 0x%x, chipmode: 0x%x 0x%x\n", 2213 info->name, chipid, mode, extmode); 2214 2215 priv->info = info; 2216 2217 return 0; 2218 } 2219 2220 static int yt921x_chip_reset(struct yt921x_priv *priv) 2221 { 2222 struct device *dev = yt921x_priv_to_device(priv); 2223 u16 eth_p_tag; 2224 u32 val; 2225 int res; 2226 2227 res = yt921x_chip_detect(priv); 2228 if (res) 2229 return res; 2230 2231 /* Reset */ 2232 res = yt921x_reg_write(priv, YT921X_RST, YT921X_RST_HW); 2233 if (res) 2234 return res; 2235 2236 /* RST_HW is almost same as GPIO hard reset, so we need this delay. */ 2237 fsleep(YT921X_RST_DELAY_US); 2238 2239 val = 0; 2240 res = yt921x_reg_wait(priv, YT921X_RST, ~0, &val); 2241 if (res) 2242 return res; 2243 2244 /* Check for tag EtherType; do it after reset in case you messed it up 2245 * before. 2246 */ 2247 res = yt921x_reg_read(priv, YT921X_CPU_TAG_TPID, &val); 2248 if (res) 2249 return res; 2250 eth_p_tag = FIELD_GET(YT921X_CPU_TAG_TPID_TPID_M, val); 2251 if (eth_p_tag != ETH_P_YT921X) { 2252 dev_err(dev, "Tag type 0x%x != 0x%x\n", eth_p_tag, 2253 ETH_P_YT921X); 2254 /* Despite being possible, we choose not to set CPU_TAG_TPID, 2255 * since there is no way it can be different unless you have the 2256 * wrong chip. 2257 */ 2258 return -EINVAL; 2259 } 2260 2261 return 0; 2262 } 2263 2264 static int yt921x_chip_setup_dsa(struct yt921x_priv *priv) 2265 { 2266 struct dsa_switch *ds = &priv->ds; 2267 unsigned long cpu_ports_mask; 2268 u32 ctrls[2]; 2269 u32 ctrl; 2270 int port; 2271 int res; 2272 2273 /* Enable DSA */ 2274 priv->cpu_ports_mask = dsa_cpu_ports(ds); 2275 2276 ctrl = YT921X_EXT_CPU_PORT_TAG_EN | YT921X_EXT_CPU_PORT_PORT_EN | 2277 YT921X_EXT_CPU_PORT_PORT(__ffs(priv->cpu_ports_mask)); 2278 res = yt921x_reg_write(priv, YT921X_EXT_CPU_PORT, ctrl); 2279 if (res) 2280 return res; 2281 2282 /* Setup software switch */ 2283 ctrl = YT921X_CPU_COPY_TO_EXT_CPU; 2284 res = yt921x_reg_write(priv, YT921X_CPU_COPY, ctrl); 2285 if (res) 2286 return res; 2287 2288 ctrl = GENMASK(10, 0); 2289 res = yt921x_reg_write(priv, YT921X_FILTER_UNK_UCAST, ctrl); 2290 if (res) 2291 return res; 2292 res = yt921x_reg_write(priv, YT921X_FILTER_UNK_MCAST, ctrl); 2293 if (res) 2294 return res; 2295 2296 /* YT921x does not support native DSA port bridging, so we use port 2297 * isolation to emulate it. However, be especially careful that port 2298 * isolation takes _after_ FDB lookups, i.e. if an FDB entry (from 2299 * another bridge) is matched and the destination port (in another 2300 * bridge) is blocked, the packet will be dropped instead of flooding to 2301 * the "bridged" ports, thus we need to trap and handle those packets by 2302 * software. 2303 * 2304 * If there is no more than one bridge, we might be able to drop them 2305 * directly given some conditions are met, but we trap them in all cases 2306 * for now. 2307 */ 2308 ctrl = 0; 2309 for (int i = 0; i < YT921X_PORT_NUM; i++) 2310 ctrl |= YT921X_ACT_UNK_ACTn_TRAP(i); 2311 /* Except for CPU ports, if any packets are sent via CPU ports without 2312 * tag, they should be dropped. 2313 */ 2314 cpu_ports_mask = priv->cpu_ports_mask; 2315 for_each_set_bit(port, &cpu_ports_mask, YT921X_PORT_NUM) { 2316 ctrl &= ~YT921X_ACT_UNK_ACTn_M(port); 2317 ctrl |= YT921X_ACT_UNK_ACTn_DROP(port); 2318 } 2319 res = yt921x_reg_write(priv, YT921X_ACT_UNK_UCAST, ctrl); 2320 if (res) 2321 return res; 2322 res = yt921x_reg_write(priv, YT921X_ACT_UNK_MCAST, ctrl); 2323 if (res) 2324 return res; 2325 2326 /* Tagged VID 0 should be treated as untagged, which confuses the 2327 * hardware a lot 2328 */ 2329 ctrls[0] = YT921X_VLAN_CTRLa_LEARN_DIS | YT921X_VLAN_CTRLa_PORTS_M; 2330 ctrls[1] = 0; 2331 res = yt921x_reg64_write(priv, YT921X_VLANn_CTRL(0), ctrls); 2332 if (res) 2333 return res; 2334 2335 return 0; 2336 } 2337 2338 static int __maybe_unused yt921x_chip_setup_qos(struct yt921x_priv *priv) 2339 { 2340 u32 ctrl; 2341 int res; 2342 2343 /* DSCP to internal priorities */ 2344 for (u8 dscp = 0; dscp < DSCP_MAX; dscp++) { 2345 int prio = ietf_dscp_to_ieee8021q_tt(dscp); 2346 2347 if (prio < 0) 2348 return prio; 2349 2350 res = yt921x_reg_write(priv, YT921X_IPM_DSCPn(dscp), 2351 YT921X_IPM_PRIO(prio)); 2352 if (res) 2353 return res; 2354 } 2355 2356 /* 802.1Q QoS to internal priorities */ 2357 for (u8 pcp = 0; pcp < 8; pcp++) 2358 for (u8 dei = 0; dei < 2; dei++) { 2359 ctrl = YT921X_IPM_PRIO(pcp); 2360 if (dei) 2361 /* "Red" almost means drop, so it's not that 2362 * useful. Note that tc police does not support 2363 * Three-Color very well 2364 */ 2365 ctrl |= YT921X_IPM_COLOR_YELLOW; 2366 2367 for (u8 svlan = 0; svlan < 2; svlan++) { 2368 u32 reg = YT921X_IPM_PCPn(svlan, dei, pcp); 2369 2370 res = yt921x_reg_write(priv, reg, ctrl); 2371 if (res) 2372 return res; 2373 } 2374 } 2375 2376 return 0; 2377 } 2378 2379 static int yt921x_chip_setup(struct yt921x_priv *priv) 2380 { 2381 u32 ctrl; 2382 int res; 2383 2384 ctrl = YT921X_FUNC_MIB | YT921X_FUNC_ACL | YT921X_FUNC_METER; 2385 res = yt921x_reg_set_bits(priv, YT921X_FUNC, ctrl); 2386 if (res) 2387 return res; 2388 2389 res = yt921x_chip_setup_dsa(priv); 2390 if (res) 2391 return res; 2392 2393 res = yt921x_chip_setup_tc(priv); 2394 if (res) 2395 return res; 2396 2397 res = yt921x_chip_setup_acl(priv); 2398 if (res) 2399 return res; 2400 2401 #if IS_ENABLED(CONFIG_DCB) 2402 res = yt921x_chip_setup_qos(priv); 2403 if (res) 2404 return res; 2405 #endif 2406 2407 /* Miscellaneous */ 2408 res = yt921x_reg_set_bits(priv, YT921X_SENSOR, YT921X_SENSOR_TEMP); 2409 if (res) 2410 return res; 2411 2412 res = yt921x_reg_clear_bits(priv, YT921X_SERDES_CTRL, 2413 YT921X_SERDES_CTRL_TEST); 2414 if (res) 2415 return res; 2416 2417 return 0; 2418 } 2419 2420 static int yt921x_dsa_setup(struct dsa_switch *ds) 2421 { 2422 struct yt921x_priv *priv = dsa_to_yt921x_priv(ds); 2423 struct device *dev = yt921x_priv_to_device(priv); 2424 struct device_node *np = dev->of_node; 2425 struct device_node *child; 2426 unsigned long mask; 2427 int port; 2428 int res; 2429 2430 mutex_lock(&priv->reg_lock); 2431 res = yt921x_chip_reset(priv); 2432 mutex_unlock(&priv->reg_lock); 2433 2434 if (res) 2435 return res; 2436 2437 /* Register the internal mdio bus. Nodes for internal ports should have 2438 * proper phy-handle pointing to their PHYs. Not enabling the internal 2439 * bus is possible, though pretty wired, if internal ports are not used. 2440 */ 2441 child = of_get_child_by_name(np, "mdio"); 2442 if (child) { 2443 res = yt921x_mbus_int_init(priv, child); 2444 of_node_put(child); 2445 if (res) 2446 return res; 2447 } 2448 2449 /* External mdio bus is optional */ 2450 child = of_get_child_by_name(np, "mdio-external"); 2451 if (child) { 2452 res = yt921x_mbus_ext_init(priv, child); 2453 of_node_put(child); 2454 if (res) 2455 return res; 2456 2457 dev_err(dev, "Untested external mdio bus\n"); 2458 return -ENODEV; 2459 } 2460 2461 mask = priv->info->serdes_mask; 2462 for_each_set_bit(port, &mask, YT921X_PORT_NUM) { 2463 struct yt921x_port *pp = &priv->ports[port]; 2464 2465 pp->pcs.ops = &yt921x_phylink_pcs_ops; 2466 pp->pcs.poll = true; 2467 2468 __set_bit(PHY_INTERFACE_MODE_SGMII, 2469 pp->pcs.supported_interfaces); 2470 __set_bit(PHY_INTERFACE_MODE_100BASEX, 2471 pp->pcs.supported_interfaces); 2472 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2473 pp->pcs.supported_interfaces); 2474 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2475 pp->pcs.supported_interfaces); 2476 } 2477 2478 mutex_lock(&priv->reg_lock); 2479 res = yt921x_chip_setup(priv); 2480 mutex_unlock(&priv->reg_lock); 2481 2482 if (res) 2483 return res; 2484 2485 #if IS_ENABLED(CONFIG_NET_DSA_YT921X_LEDS) 2486 res = yt921x_leds_setup(priv); 2487 if (res) 2488 dev_warn(dev, "Failed to setup LEDs: %d\n", res); 2489 #endif 2490 2491 return 0; 2492 } 2493 2494 static const struct phylink_mac_ops yt921x_phylink_mac_ops = { 2495 .mac_select_pcs = yt921x_phylink_mac_select_pcs, 2496 .mac_link_down = yt921x_phylink_mac_link_down, 2497 .mac_link_up = yt921x_phylink_mac_link_up, 2498 .mac_config = yt921x_phylink_mac_config, 2499 }; 2500 2501 static const struct dsa_switch_ops yt921x_dsa_switch_ops = { 2502 /* mib */ 2503 .get_strings = yt921x_dsa_get_strings, 2504 .get_ethtool_stats = yt921x_dsa_get_ethtool_stats, 2505 .get_sset_count = yt921x_dsa_get_sset_count, 2506 .get_eth_mac_stats = yt921x_dsa_get_eth_mac_stats, 2507 .get_eth_ctrl_stats = yt921x_dsa_get_eth_ctrl_stats, 2508 .get_rmon_stats = yt921x_dsa_get_rmon_stats, 2509 .get_stats64 = yt921x_dsa_get_stats64, 2510 .get_pause_stats = yt921x_dsa_get_pause_stats, 2511 /* eee */ 2512 .support_eee = dsa_supports_eee, 2513 .set_mac_eee = yt921x_dsa_set_mac_eee, 2514 /* mtu */ 2515 .port_change_mtu = yt921x_dsa_port_change_mtu, 2516 .port_max_mtu = yt921x_dsa_port_max_mtu, 2517 /* rate */ 2518 .port_policer_del = yt921x_dsa_port_policer_del, 2519 .port_policer_add = yt921x_dsa_port_policer_add, 2520 .port_setup_tc = yt921x_dsa_port_setup_tc, 2521 /* acl */ 2522 .cls_flower_del = yt921x_dsa_cls_flower_del, 2523 .cls_flower_add = yt921x_dsa_cls_flower_add, 2524 /* hsr */ 2525 .port_hsr_leave = dsa_port_simple_hsr_leave, 2526 .port_hsr_join = dsa_port_simple_hsr_join, 2527 /* mirror */ 2528 .port_mirror_del = yt921x_dsa_port_mirror_del, 2529 .port_mirror_add = yt921x_dsa_port_mirror_add, 2530 /* lag */ 2531 .port_lag_leave = yt921x_dsa_port_lag_leave, 2532 .port_lag_join = yt921x_dsa_port_lag_join, 2533 /* fdb */ 2534 .port_fdb_dump = yt921x_dsa_port_fdb_dump, 2535 .port_fast_age = yt921x_dsa_port_fast_age, 2536 .set_ageing_time = yt921x_dsa_set_ageing_time, 2537 .port_fdb_del = yt921x_dsa_port_fdb_del, 2538 .port_fdb_add = yt921x_dsa_port_fdb_add, 2539 .port_mdb_del = yt921x_dsa_port_mdb_del, 2540 .port_mdb_add = yt921x_dsa_port_mdb_add, 2541 /* vlan */ 2542 .port_vlan_filtering = yt921x_dsa_port_vlan_filtering, 2543 .port_vlan_del = yt921x_dsa_port_vlan_del, 2544 .port_vlan_add = yt921x_dsa_port_vlan_add, 2545 /* bridge */ 2546 .port_pre_bridge_flags = yt921x_dsa_port_pre_bridge_flags, 2547 .port_bridge_flags = yt921x_dsa_port_bridge_flags, 2548 .port_bridge_leave = yt921x_dsa_port_bridge_leave, 2549 .port_bridge_join = yt921x_dsa_port_bridge_join, 2550 /* mst */ 2551 .port_mst_state_set = yt921x_dsa_port_mst_state_set, 2552 .vlan_msti_set = yt921x_dsa_vlan_msti_set, 2553 .port_stp_state_set = yt921x_dsa_port_stp_state_set, 2554 #if IS_ENABLED(CONFIG_DCB) 2555 /* dcb */ 2556 .port_get_default_prio = yt921x_dsa_port_get_default_prio, 2557 .port_set_default_prio = yt921x_dsa_port_set_default_prio, 2558 .port_get_apptrust = yt921x_dsa_port_get_apptrust, 2559 .port_set_apptrust = yt921x_dsa_port_set_apptrust, 2560 #endif 2561 /* port */ 2562 .get_tag_protocol = yt921x_dsa_get_tag_protocol, 2563 .phylink_get_caps = yt921x_dsa_phylink_get_caps, 2564 .port_teardown = yt921x_dsa_port_teardown, 2565 .port_setup = yt921x_dsa_port_setup, 2566 #if IS_ENABLED(CONFIG_DCB) 2567 /* dscp */ 2568 .port_get_dscp_prio = yt921x_dsa_port_get_dscp_prio, 2569 .port_del_dscp_prio = yt921x_dsa_port_del_dscp_prio, 2570 .port_add_dscp_prio = yt921x_dsa_port_add_dscp_prio, 2571 #endif 2572 /* chip */ 2573 .teardown = yt921x_dsa_teardown, 2574 .setup = yt921x_dsa_setup, 2575 }; 2576 2577 static void yt921x_mdio_shutdown(struct mdio_device *mdiodev) 2578 { 2579 struct yt921x_priv *priv = mdiodev_get_drvdata(mdiodev); 2580 2581 if (!priv) 2582 return; 2583 2584 dsa_switch_shutdown(&priv->ds); 2585 } 2586 2587 static void yt921x_mdio_remove(struct mdio_device *mdiodev) 2588 { 2589 struct yt921x_priv *priv = mdiodev_get_drvdata(mdiodev); 2590 2591 if (!priv) 2592 return; 2593 2594 dsa_unregister_switch(&priv->ds); 2595 2596 for (unsigned int i = 0; i < ARRAY_SIZE(priv->acl_blks); i++) { 2597 struct yt921x_acl_blk *aclblk = priv->acl_blks[i]; 2598 2599 if (!aclblk) 2600 continue; 2601 for (unsigned int j = 0; j < ARRAY_SIZE(aclblk->rules); j++) { 2602 struct yt921x_acl_rule *aclrule = aclblk->rules[j]; 2603 2604 if (!aclrule) 2605 continue; 2606 kvfree(aclrule); 2607 } 2608 kvfree(aclblk); 2609 } 2610 mutex_destroy(&priv->reg_lock); 2611 } 2612 2613 static int yt921x_mdio_probe(struct mdio_device *mdiodev) 2614 { 2615 struct device *dev = &mdiodev->dev; 2616 struct yt921x_reg_mdio *mdio; 2617 struct yt921x_priv *priv; 2618 struct dsa_switch *ds; 2619 2620 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 2621 if (!priv) 2622 return -ENOMEM; 2623 2624 mdio = devm_kzalloc(dev, sizeof(*mdio), GFP_KERNEL); 2625 if (!mdio) 2626 return -ENOMEM; 2627 2628 mdio->bus = mdiodev->bus; 2629 mdio->addr = mdiodev->addr; 2630 mdio->switchid = 0; 2631 2632 mutex_init(&priv->reg_lock); 2633 2634 priv->reg_ops = &yt921x_reg_ops_mdio; 2635 priv->reg_ctx = mdio; 2636 2637 for (size_t i = 0; i < ARRAY_SIZE(priv->ports); i++) { 2638 struct yt921x_port *pp = &priv->ports[i]; 2639 2640 pp->index = i; 2641 } 2642 2643 ds = &priv->ds; 2644 ds->dev = dev; 2645 ds->assisted_learning_on_cpu_port = true; 2646 ds->dscp_prio_mapping_is_global = true; 2647 ds->priv = priv; 2648 ds->ops = &yt921x_dsa_switch_ops; 2649 ds->ageing_time_min = 1 * 5000; 2650 ds->ageing_time_max = U16_MAX * 5000; 2651 ds->phylink_mac_ops = &yt921x_phylink_mac_ops; 2652 ds->num_lag_ids = YT921X_LAG_NUM; 2653 ds->num_ports = YT921X_PORT_NUM; 2654 2655 mdiodev_set_drvdata(mdiodev, priv); 2656 2657 return dsa_register_switch(ds); 2658 } 2659 2660 static const struct of_device_id yt921x_of_match[] = { 2661 { .compatible = "motorcomm,yt9215" }, 2662 {} 2663 }; 2664 MODULE_DEVICE_TABLE(of, yt921x_of_match); 2665 2666 static struct mdio_driver yt921x_mdio_driver = { 2667 .probe = yt921x_mdio_probe, 2668 .remove = yt921x_mdio_remove, 2669 .shutdown = yt921x_mdio_shutdown, 2670 .mdiodrv.driver = { 2671 .name = YT921X_NAME, 2672 .of_match_table = yt921x_of_match, 2673 }, 2674 }; 2675 2676 mdio_module_driver(yt921x_mdio_driver); 2677 2678 MODULE_AUTHOR("David Yang <mmyangfl@gmail.com>"); 2679 MODULE_DESCRIPTION("Driver for Motorcomm YT921x Switch"); 2680 MODULE_LICENSE("GPL"); 2681