1 // SPDX-License-Identifier: GPL-2.0 2 /* Microchip LAN937X switch driver main logic 3 * Copyright (C) 2019-2024 Microchip Technology Inc. 4 */ 5 #include <linux/dsa/ksz_common.h> 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/iopoll.h> 9 #include <linux/phy.h> 10 #include <linux/of_net.h> 11 #include <linux/if_bridge.h> 12 #include <linux/if_vlan.h> 13 #include <linux/math.h> 14 #include <net/dsa.h> 15 #include <net/switchdev.h> 16 17 #include "lan937x_reg.h" 18 #include "ksz_common.h" 19 #include "ksz_dcb.h" 20 #include "ksz9477.h" 21 #include "lan937x.h" 22 23 /* marker for ports without built-in PHY */ 24 #define LAN937X_NO_PHY U8_MAX 25 26 /* 27 * lan9370_phy_addr - Mapping of LAN9370 switch ports to PHY addresses. 28 * 29 * Each entry corresponds to a specific port on the LAN9370 switch, 30 * where ports 1-4 are connected to integrated 100BASE-T1 PHYs, and 31 * Port 5 is connected to an RGMII interface without a PHY. The values 32 * are based on the documentation (DS00003108E, section 3.3). 33 */ 34 static const u8 lan9370_phy_addr[] = { 35 [0] = 2, /* Port 1, T1 AFE0 */ 36 [1] = 3, /* Port 2, T1 AFE1 */ 37 [2] = 5, /* Port 3, T1 AFE3 */ 38 [3] = 6, /* Port 4, T1 AFE4 */ 39 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 40 }; 41 42 /* 43 * lan9371_phy_addr - Mapping of LAN9371 switch ports to PHY addresses. 44 * 45 * The values are based on the documentation (DS00003109E, section 3.3). 46 */ 47 static const u8 lan9371_phy_addr[] = { 48 [0] = 2, /* Port 1, T1 AFE0 */ 49 [1] = 3, /* Port 2, T1 AFE1 */ 50 [2] = 5, /* Port 3, T1 AFE3 */ 51 [3] = 8, /* Port 4, TX PHY */ 52 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 53 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */ 54 }; 55 56 /* 57 * lan9372_phy_addr - Mapping of LAN9372 switch ports to PHY addresses. 58 * 59 * The values are based on the documentation (DS00003110F, section 3.3). 60 */ 61 static const u8 lan9372_phy_addr[] = { 62 [0] = 2, /* Port 1, T1 AFE0 */ 63 [1] = 3, /* Port 2, T1 AFE1 */ 64 [2] = 5, /* Port 3, T1 AFE3 */ 65 [3] = 8, /* Port 4, TX PHY */ 66 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 67 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */ 68 [6] = 6, /* Port 7, T1 AFE4 */ 69 [7] = 4, /* Port 8, T1 AFE2 */ 70 }; 71 72 /* 73 * lan9373_phy_addr - Mapping of LAN9373 switch ports to PHY addresses. 74 * 75 * The values are based on the documentation (DS00003110F, section 3.3). 76 */ 77 static const u8 lan9373_phy_addr[] = { 78 [0] = 2, /* Port 1, T1 AFE0 */ 79 [1] = 3, /* Port 2, T1 AFE1 */ 80 [2] = 5, /* Port 3, T1 AFE3 */ 81 [3] = LAN937X_NO_PHY, /* Port 4, SGMII */ 82 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 83 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */ 84 [6] = 6, /* Port 7, T1 AFE4 */ 85 [7] = 4, /* Port 8, T1 AFE2 */ 86 }; 87 88 /* 89 * lan9374_phy_addr - Mapping of LAN9374 switch ports to PHY addresses. 90 * 91 * The values are based on the documentation (DS00003110F, section 3.3). 92 */ 93 static const u8 lan9374_phy_addr[] = { 94 [0] = 2, /* Port 1, T1 AFE0 */ 95 [1] = 3, /* Port 2, T1 AFE1 */ 96 [2] = 5, /* Port 3, T1 AFE3 */ 97 [3] = 7, /* Port 4, T1 AFE5 */ 98 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 99 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */ 100 [6] = 6, /* Port 7, T1 AFE4 */ 101 [7] = 4, /* Port 8, T1 AFE2 */ 102 }; 103 104 static int lan937x_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 105 { 106 return regmap_update_bits(ksz_regmap_8(dev), addr, bits, set ? bits : 0); 107 } 108 109 static int lan937x_port_cfg(struct ksz_device *dev, int port, int offset, 110 u8 bits, bool set) 111 { 112 return regmap_update_bits(ksz_regmap_8(dev), PORT_CTRL_ADDR(port, offset), 113 bits, set ? bits : 0); 114 } 115 116 /** 117 * lan937x_create_phy_addr_map - Create port-to-PHY address map for MDIO bus. 118 * @dev: Pointer to device structure. 119 * @side_mdio: Boolean indicating if the PHYs are accessed over a side MDIO bus. 120 * 121 * This function sets up the PHY address mapping for the LAN937x switches, 122 * which support two access modes for internal PHYs: 123 * 1. **SPI Access**: A straightforward one-to-one port-to-PHY address 124 * mapping is applied. 125 * 2. **MDIO Access**: The PHY address mapping varies based on chip variant 126 * and strap configuration. An offset is calculated based on strap settings 127 * to ensure correct PHY addresses are assigned. The offset calculation logic 128 * is based on Microchip's Article Number 000015828, available at: 129 * https://microchip.my.site.com/s/article/LAN9374-Virtual-PHY-PHY-Address-Mapping 130 * 131 * The function first checks if side MDIO access is disabled, in which case a 132 * simple direct mapping (port number = PHY address) is applied. If side MDIO 133 * access is enabled, it reads the strap configuration to determine the correct 134 * offset for PHY addresses. 135 * 136 * The appropriate mapping table is selected based on the chip ID, and the 137 * `phy_addr_map` is populated with the correct addresses for each port. Any 138 * port with no PHY is assigned a `LAN937X_NO_PHY` marker. 139 * 140 * Return: 0 on success, error code on failure. 141 */ 142 static int lan937x_create_phy_addr_map(struct ksz_device *dev, bool side_mdio) 143 { 144 static const u8 *phy_addr_map; 145 u32 strap_val; 146 u8 offset = 0; 147 size_t size; 148 int ret, i; 149 150 if (!side_mdio) { 151 /* simple direct mapping */ 152 for (i = 0; i < dev->info->port_cnt; i++) 153 dev->phy_addr_map[i] = i; 154 155 return 0; 156 } 157 158 ret = ksz_read32(dev, REG_SW_CFG_STRAP_VAL, &strap_val); 159 if (ret < 0) 160 return ret; 161 162 if (!(strap_val & SW_CASCADE_ID_CFG) && !(strap_val & SW_VPHY_ADD_CFG)) 163 offset = 0; 164 else if (!(strap_val & SW_CASCADE_ID_CFG) && (strap_val & SW_VPHY_ADD_CFG)) 165 offset = 7; 166 else if ((strap_val & SW_CASCADE_ID_CFG) && !(strap_val & SW_VPHY_ADD_CFG)) 167 offset = 15; 168 else 169 offset = 22; 170 171 switch (dev->info->chip_id) { 172 case LAN9370_CHIP_ID: 173 phy_addr_map = lan9370_phy_addr; 174 size = ARRAY_SIZE(lan9370_phy_addr); 175 break; 176 case LAN9371_CHIP_ID: 177 phy_addr_map = lan9371_phy_addr; 178 size = ARRAY_SIZE(lan9371_phy_addr); 179 break; 180 case LAN9372_CHIP_ID: 181 phy_addr_map = lan9372_phy_addr; 182 size = ARRAY_SIZE(lan9372_phy_addr); 183 break; 184 case LAN9373_CHIP_ID: 185 phy_addr_map = lan9373_phy_addr; 186 size = ARRAY_SIZE(lan9373_phy_addr); 187 break; 188 case LAN9374_CHIP_ID: 189 phy_addr_map = lan9374_phy_addr; 190 size = ARRAY_SIZE(lan9374_phy_addr); 191 break; 192 default: 193 return -EINVAL; 194 } 195 196 if (size < dev->info->port_cnt) 197 return -EINVAL; 198 199 for (i = 0; i < dev->info->port_cnt; i++) { 200 if (phy_addr_map[i] == LAN937X_NO_PHY) 201 dev->phy_addr_map[i] = phy_addr_map[i]; 202 else 203 dev->phy_addr_map[i] = phy_addr_map[i] + offset; 204 } 205 206 return 0; 207 } 208 209 /** 210 * lan937x_mdio_bus_preinit - Pre-initialize MDIO bus for accessing PHYs. 211 * @dev: Pointer to device structure. 212 * @side_mdio: Boolean indicating if the PHYs are accessed over a side MDIO bus. 213 * 214 * This function configures the LAN937x switch for PHY access either through 215 * SPI or the side MDIO bus, unlocking the necessary registers for each access 216 * mode. 217 * 218 * Operation Modes: 219 * 1. **SPI Access**: Enables SPI indirect access to address clock domain 220 * crossing issues when SPI is used for PHY access. 221 * 2. **MDIO Access**: Grants access to internal PHYs over the side MDIO bus, 222 * required when using the MDIO bus for PHY management. 223 * 224 * Return: 0 on success, error code on failure. 225 */ 226 static int lan937x_mdio_bus_preinit(struct ksz_device *dev, bool side_mdio) 227 { 228 u16 data16; 229 int ret; 230 231 /* Unlock access to the PHYs, needed for SPI and side MDIO access */ 232 ret = lan937x_cfg(dev, REG_GLOBAL_CTRL_0, SW_PHY_REG_BLOCK, false); 233 if (ret < 0) 234 goto print_error; 235 236 if (side_mdio) 237 /* Allow access to internal PHYs over MDIO bus */ 238 data16 = VPHY_MDIO_INTERNAL_ENABLE; 239 else 240 /* Enable SPI indirect access to address clock domain crossing 241 * issue 242 */ 243 data16 = VPHY_SPI_INDIRECT_ENABLE; 244 245 ret = ksz_rmw16(dev, REG_VPHY_SPECIAL_CTRL__2, 246 VPHY_SPI_INDIRECT_ENABLE | VPHY_MDIO_INTERNAL_ENABLE, 247 data16); 248 249 print_error: 250 if (ret < 0) 251 dev_err(dev->dev, "failed to preinit the MDIO bus\n"); 252 253 return ret; 254 } 255 256 static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg) 257 { 258 u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE; 259 u16 temp; 260 261 if (is_lan937x_tx_phy(dev, addr)) 262 addr_base = REG_PORT_TX_PHY_CTRL_BASE; 263 264 /* get register address based on the logical port */ 265 temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2))); 266 267 return ksz_write16(dev, REG_VPHY_IND_ADDR__2, temp); 268 } 269 270 static int lan937x_internal_phy_write(struct ksz_device *dev, int addr, int reg, 271 u16 val) 272 { 273 unsigned int value; 274 int ret; 275 276 /* Check for internal phy port */ 277 if (!dev->info->internal_phy[addr]) 278 return -EOPNOTSUPP; 279 280 ret = lan937x_vphy_ind_addr_wr(dev, addr, reg); 281 if (ret < 0) 282 return ret; 283 284 /* Write the data to be written to the VPHY reg */ 285 ret = ksz_write16(dev, REG_VPHY_IND_DATA__2, val); 286 if (ret < 0) 287 return ret; 288 289 /* Write the Write En and Busy bit */ 290 ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, 291 (VPHY_IND_WRITE | VPHY_IND_BUSY)); 292 if (ret < 0) 293 return ret; 294 295 ret = regmap_read_poll_timeout(ksz_regmap_16(dev), REG_VPHY_IND_CTRL__2, 296 value, !(value & VPHY_IND_BUSY), 10, 297 1000); 298 if (ret < 0) { 299 dev_err(dev->dev, "Failed to write phy register\n"); 300 return ret; 301 } 302 303 return 0; 304 } 305 306 static int lan937x_internal_phy_read(struct ksz_device *dev, int addr, int reg, 307 u16 *val) 308 { 309 unsigned int value; 310 int ret; 311 312 /* Check for internal phy port, return 0xffff for non-existent phy */ 313 if (!dev->info->internal_phy[addr]) 314 return 0xffff; 315 316 ret = lan937x_vphy_ind_addr_wr(dev, addr, reg); 317 if (ret < 0) 318 return ret; 319 320 /* Write Read and Busy bit to start the transaction */ 321 ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, VPHY_IND_BUSY); 322 if (ret < 0) 323 return ret; 324 325 ret = regmap_read_poll_timeout(ksz_regmap_16(dev), REG_VPHY_IND_CTRL__2, 326 value, !(value & VPHY_IND_BUSY), 10, 327 1000); 328 if (ret < 0) { 329 dev_err(dev->dev, "Failed to read phy register\n"); 330 return ret; 331 } 332 333 /* Read the VPHY register which has the PHY data */ 334 return ksz_read16(dev, REG_VPHY_IND_DATA__2, val); 335 } 336 337 static int lan937x_phy_read16(struct dsa_switch *ds, int addr, int reg) 338 { 339 struct ksz_device *dev = ds->priv; 340 u16 val = 0xffff; 341 int ret; 342 343 ret = lan937x_internal_phy_read(dev, addr, reg, &val); 344 if (ret) 345 return ret; 346 347 return val; 348 } 349 350 static int lan937x_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 351 { 352 struct ksz_device *dev = ds->priv; 353 int ret; 354 355 ret = lan937x_internal_phy_write(dev, addr, reg, val); 356 if (ret) 357 return ret; 358 359 return 0; 360 } 361 362 static int lan937x_reset_switch(struct ksz_device *dev) 363 { 364 u32 data32; 365 int ret; 366 367 /* reset switch */ 368 ret = lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 369 if (ret < 0) 370 return ret; 371 372 /* Enable Auto Aging */ 373 ret = lan937x_cfg(dev, REG_SW_LUE_CTRL_1, SW_LINK_AUTO_AGING, true); 374 if (ret < 0) 375 return ret; 376 377 /* disable interrupts */ 378 ret = ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 379 if (ret < 0) 380 return ret; 381 382 ret = ksz_write32(dev, REG_SW_INT_STATUS__4, POR_READY_INT); 383 if (ret < 0) 384 return ret; 385 386 ret = ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0xFF); 387 if (ret < 0) 388 return ret; 389 390 return ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 391 } 392 393 static void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port) 394 { 395 const u32 *masks = dev->info->masks; 396 const u16 *regs = dev->info->regs; 397 struct dsa_switch *ds = dev->ds; 398 u8 member; 399 400 /* enable tag tail for host port */ 401 if (cpu_port) 402 lan937x_port_cfg(dev, port, REG_PORT_CTRL_0, 403 PORT_TAIL_TAG_ENABLE, true); 404 405 /* Enable the Port Queue split */ 406 ksz9477_port_queue_split(dev, port); 407 408 /* set back pressure for half duplex */ 409 lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, 410 true); 411 412 /* enable 802.1p priority */ 413 lan937x_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 414 415 if (!dev->info->internal_phy[port]) 416 lan937x_port_cfg(dev, port, regs[P_XMII_CTRL_0], 417 masks[P_MII_TX_FLOW_CTRL] | 418 masks[P_MII_RX_FLOW_CTRL], 419 true); 420 421 if (cpu_port) 422 member = dsa_user_ports(ds); 423 else 424 member = BIT(dsa_upstream_port(ds, port)); 425 426 dev->dev_ops->cfg_port_member(dev, port, member); 427 } 428 429 static int lan937x_dsa_port_setup(struct dsa_switch *ds, int port) 430 { 431 struct ksz_device *dev = ds->priv; 432 int ret; 433 434 if (!dsa_is_user_port(ds, port)) 435 return 0; 436 437 lan937x_port_setup(dev, port, false); 438 439 ret = ksz9477_set_default_prio_queue_mapping(dev, port); 440 if (ret) 441 return ret; 442 443 return ksz_dcb_init_port(dev, port); 444 } 445 446 static void lan937x_config_cpu_port(struct dsa_switch *ds) 447 { 448 struct ksz_device *dev = ds->priv; 449 struct dsa_port *dp; 450 451 dsa_switch_for_each_cpu_port(dp, ds) { 452 if (dev->info->cpu_ports & (1 << dp->index)) { 453 dev->cpu_port = dp->index; 454 455 /* enable cpu port */ 456 lan937x_port_setup(dev, dp->index, true); 457 } 458 } 459 460 dsa_switch_for_each_user_port(dp, ds) { 461 ksz_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED); 462 } 463 } 464 465 static int lan937x_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 466 { 467 struct ksz_device *dev = ds->priv; 468 int ret; 469 470 new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN; 471 472 if (dsa_is_cpu_port(ds, port)) 473 new_mtu += LAN937X_TAG_LEN; 474 475 if (new_mtu >= FR_MIN_SIZE) 476 ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, 477 PORT_JUMBO_PACKET, true); 478 else 479 ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, 480 PORT_JUMBO_PACKET, false); 481 if (ret < 0) { 482 dev_err(ds->dev, "failed to enable jumbo\n"); 483 return ret; 484 } 485 486 /* Write the frame size in PORT_MAX_FR_SIZE register */ 487 ret = ksz_pwrite16(dev, port, PORT_MAX_FR_SIZE, new_mtu); 488 if (ret) { 489 dev_err(ds->dev, "failed to update mtu for port %d\n", port); 490 return ret; 491 } 492 493 return 0; 494 } 495 496 static int lan937x_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 497 { 498 struct ksz_device *dev = ds->priv; 499 u8 data, mult, value8; 500 bool in_msec = false; 501 u32 max_val, value; 502 u32 secs = msecs; 503 int ret; 504 505 #define MAX_TIMER_VAL ((1 << 20) - 1) 506 507 /* The aging timer comprises a 3-bit multiplier and a 20-bit second 508 * value. Either of them cannot be zero. The maximum timer is then 509 * 7 * 1048575 = 7340025 seconds. As this value is too large for 510 * practical use it can be interpreted as microseconds, making the 511 * maximum timer 7340 seconds with finer control. This allows for 512 * maximum 122 minutes compared to 29 minutes in KSZ9477 switch. 513 */ 514 if (msecs % 1000) 515 in_msec = true; 516 else 517 secs /= 1000; 518 if (!secs) 519 secs = 1; 520 521 /* Return error if too large. */ 522 else if (secs > 7 * MAX_TIMER_VAL) 523 return -EINVAL; 524 525 /* Configure how to interpret the number value. */ 526 ret = ksz_rmw8(dev, REG_SW_LUE_CTRL_2, SW_AGE_CNT_IN_MICROSEC, 527 in_msec ? SW_AGE_CNT_IN_MICROSEC : 0); 528 if (ret < 0) 529 return ret; 530 531 ret = ksz_read8(dev, REG_SW_LUE_CTRL_0, &value8); 532 if (ret < 0) 533 return ret; 534 535 /* Check whether there is need to update the multiplier. */ 536 mult = FIELD_GET(SW_AGE_CNT_M, value8); 537 max_val = MAX_TIMER_VAL; 538 if (mult > 0) { 539 /* Try to use the same multiplier already in the register as 540 * the hardware default uses multiplier 4 and 75 seconds for 541 * 300 seconds. 542 */ 543 max_val = DIV_ROUND_UP(secs, mult); 544 if (max_val > MAX_TIMER_VAL || max_val * mult != secs) 545 max_val = MAX_TIMER_VAL; 546 } 547 548 data = DIV_ROUND_UP(secs, max_val); 549 if (mult != data) { 550 value8 &= ~SW_AGE_CNT_M; 551 value8 |= FIELD_PREP(SW_AGE_CNT_M, data); 552 ret = ksz_write8(dev, REG_SW_LUE_CTRL_0, value8); 553 if (ret < 0) 554 return ret; 555 } 556 557 secs = DIV_ROUND_UP(secs, data); 558 559 value = FIELD_GET(SW_AGE_PERIOD_7_0_M, secs); 560 561 ret = ksz_write8(dev, REG_SW_AGE_PERIOD__1, value); 562 if (ret < 0) 563 return ret; 564 565 value = FIELD_GET(SW_AGE_PERIOD_19_8_M, secs); 566 567 return ksz_write16(dev, REG_SW_AGE_PERIOD__2, value); 568 } 569 570 static void lan937x_set_tune_adj(struct ksz_device *dev, int port, 571 u16 reg, u8 val) 572 { 573 u16 data16; 574 575 ksz_pread16(dev, port, reg, &data16); 576 577 /* Update tune Adjust */ 578 data16 &= ~PORT_TUNE_ADJ; 579 data16 |= FIELD_PREP(PORT_TUNE_ADJ, val); 580 ksz_pwrite16(dev, port, reg, data16); 581 582 /* write DLL reset to take effect */ 583 data16 |= PORT_DLL_RESET; 584 ksz_pwrite16(dev, port, reg, data16); 585 } 586 587 static void lan937x_set_rgmii_tx_delay(struct ksz_device *dev, int port) 588 { 589 u8 val; 590 591 /* Apply different codes based on the ports as per characterization 592 * results 593 */ 594 val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_TX_DELAY_2NS : 595 RGMII_2_TX_DELAY_2NS; 596 597 lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_5, val); 598 } 599 600 static void lan937x_set_rgmii_rx_delay(struct ksz_device *dev, int port) 601 { 602 u8 val; 603 604 val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_RX_DELAY_2NS : 605 RGMII_2_RX_DELAY_2NS; 606 607 lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_4, val); 608 } 609 610 static void lan937x_phylink_get_caps(struct dsa_switch *ds, int port, 611 struct phylink_config *config) 612 { 613 struct ksz_device *dev = ds->priv; 614 615 config->mac_capabilities = MAC_100FD; 616 617 if (dev->info->supports_rgmii[port]) { 618 /* MII/RMII/RGMII ports */ 619 config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 620 MAC_100HD | MAC_10 | MAC_1000FD; 621 } else if (is_lan937x_tx_phy(dev, port)) { 622 config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 623 MAC_100HD | MAC_10; 624 } 625 626 ksz_phylink_get_caps(ds, port, config); 627 } 628 629 static void lan937x_setup_rgmii_delay(struct ksz_device *dev, int port) 630 { 631 struct ksz_port *p = &dev->ports[port]; 632 633 if (p->rgmii_tx_val) { 634 lan937x_set_rgmii_tx_delay(dev, port); 635 dev_info(dev->dev, "Applied rgmii tx delay for the port %d\n", 636 port); 637 } 638 639 if (p->rgmii_rx_val) { 640 lan937x_set_rgmii_rx_delay(dev, port); 641 dev_info(dev->dev, "Applied rgmii rx delay for the port %d\n", 642 port); 643 } 644 } 645 646 static int lan937x_tc_cbs_set_cinc(struct ksz_device *dev, int port, u32 val) 647 { 648 return ksz_pwrite32(dev, port, REG_PORT_MTI_CREDIT_INCREMENT, val); 649 } 650 651 static int lan937x_switch_init(struct ksz_device *dev) 652 { 653 dev->port_mask = (1 << dev->info->port_cnt) - 1; 654 655 return 0; 656 } 657 658 static int lan937x_setup(struct dsa_switch *ds) 659 { 660 struct ksz_device *dev = ds->priv; 661 u16 storm_mask, storm_rate; 662 struct dsa_port *dp; 663 struct ksz_port *p; 664 const u16 *regs; 665 int ret; 666 667 regs = dev->info->regs; 668 669 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 670 dev->info->num_vlans, GFP_KERNEL); 671 if (!dev->vlan_cache) 672 return -ENOMEM; 673 674 ret = lan937x_reset_switch(dev); 675 if (ret) { 676 dev_err(ds->dev, "failed to reset switch\n"); 677 return ret; 678 } 679 680 ret = ksz_parse_drive_strength(dev); 681 if (ret) 682 return ret; 683 684 /* set broadcast storm protection 10% rate */ 685 storm_mask = BROADCAST_STORM_RATE; 686 storm_rate = (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100; 687 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 688 storm_mask, storm_rate); 689 690 lan937x_config_cpu_port(ds); 691 692 ksz9477_enable_stp_addr(dev); 693 694 ds->num_tx_queues = dev->info->num_tx_queues; 695 696 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 697 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 698 699 ksz_init_mib_timer(dev); 700 701 ds->configure_vlan_while_not_filtering = false; 702 ds->dscp_prio_mapping_is_global = true; 703 704 /* The VLAN aware is a global setting. Mixed vlan 705 * filterings are not supported. 706 */ 707 ds->vlan_filtering_is_global = true; 708 709 /* Enable aggressive back off for half duplex & UNH mode */ 710 ret = lan937x_cfg(dev, REG_SW_MAC_CTRL_0, (SW_PAUSE_UNH_MODE | 711 SW_NEW_BACKOFF | 712 SW_AGGR_BACKOFF), true); 713 if (ret < 0) 714 return ret; 715 716 /* If NO_EXC_COLLISION_DROP bit is set, the switch will not drop 717 * packets when 16 or more collisions occur 718 */ 719 ret = lan937x_cfg(dev, REG_SW_MAC_CTRL_1, NO_EXC_COLLISION_DROP, true); 720 if (ret < 0) 721 return ret; 722 723 /* enable global MIB counter freeze function */ 724 ret = lan937x_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 725 if (ret < 0) 726 return ret; 727 728 /* disable CLK125 & CLK25, 1: disable, 0: enable */ 729 ret = lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, 730 (SW_CLK125_ENB | SW_CLK25_ENB), true); 731 if (ret < 0) 732 return ret; 733 734 /* Disable global VPHY support. Related to CPU interface only? */ 735 ret = ksz_rmw32(dev, REG_SW_CFG_STRAP_OVR, SW_VPHY_DISABLE, 736 SW_VPHY_DISABLE); 737 if (ret < 0) 738 return ret; 739 740 /* Start with learning disabled on standalone user ports, and enabled 741 * on the CPU port. In lack of other finer mechanisms, learning on the 742 * CPU port will avoid flooding bridge local addresses on the network 743 * in some cases. 744 */ 745 p = &dev->ports[dev->cpu_port]; 746 p->learning = true; 747 748 if (dev->irq > 0) { 749 ret = ksz_girq_setup(dev); 750 if (ret) 751 return ret; 752 753 dsa_switch_for_each_user_port(dp, dev->ds) { 754 ret = ksz_pirq_setup(dev, dp->index); 755 if (ret) 756 goto port_release; 757 758 ret = ksz_ptp_irq_setup(ds, dp->index); 759 if (ret) 760 goto pirq_release; 761 } 762 } 763 764 ret = ksz_ptp_clock_register(ds); 765 if (ret) { 766 dev_err(dev->dev, "Failed to register PTP clock: %d\n", 767 ret); 768 goto port_release; 769 } 770 771 ret = ksz_mdio_register(dev); 772 if (ret < 0) { 773 dev_err(dev->dev, "failed to register the mdio"); 774 goto out_ptp_clock_unregister; 775 } 776 777 ret = ksz_dcb_init(dev); 778 if (ret) 779 goto out_ptp_clock_unregister; 780 781 /* start switch */ 782 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 783 SW_START, SW_START); 784 785 return 0; 786 787 out_ptp_clock_unregister: 788 ksz_ptp_clock_unregister(ds); 789 port_release: 790 if (dev->irq > 0) { 791 dsa_switch_for_each_user_port_continue_reverse(dp, dev->ds) { 792 ksz_ptp_irq_free(ds, dp->index); 793 pirq_release: 794 ksz_irq_free(&dev->ports[dp->index].pirq); 795 } 796 ksz_irq_free(&dev->girq); 797 } 798 799 return ret; 800 } 801 802 static enum dsa_tag_protocol lan937x_get_tag_protocol(struct dsa_switch *ds, 803 int port, 804 enum dsa_tag_protocol mp) 805 { 806 return DSA_TAG_PROTO_LAN937X; 807 } 808 809 static int lan937x_connect_tag_protocol(struct dsa_switch *ds, 810 enum dsa_tag_protocol proto) 811 { 812 struct ksz_tagger_data *tagger_data; 813 814 if (proto != DSA_TAG_PROTO_LAN937X) 815 return -EPROTONOSUPPORT; 816 817 tagger_data = ksz_tagger_data(ds); 818 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 819 820 return 0; 821 } 822 823 const struct phylink_mac_ops lan937x_phylink_mac_ops = { 824 .mac_config = ksz_phylink_mac_config, 825 .mac_link_down = ksz_phylink_mac_link_down, 826 .mac_link_up = ksz9477_phylink_mac_link_up, 827 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 828 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 829 }; 830 831 const struct ksz_dev_ops lan937x_dev_ops = { 832 .get_port_addr = ksz9477_get_port_addr, 833 .cfg_port_member = ksz9477_cfg_port_member, 834 .mdio_bus_preinit = lan937x_mdio_bus_preinit, 835 .create_phy_addr_map = lan937x_create_phy_addr_map, 836 .r_mib_cnt = ksz9477_r_mib_cnt, 837 .r_mib_pkt = ksz9477_r_mib_pkt, 838 .r_mib_stat64 = ksz_r_mib_stats64, 839 .freeze_mib = ksz9477_freeze_mib, 840 .port_init_cnt = ksz9477_port_init_cnt, 841 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 842 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 843 .init = lan937x_switch_init, 844 }; 845 846 const struct dsa_switch_ops lan937x_switch_ops = { 847 .get_tag_protocol = lan937x_get_tag_protocol, 848 .connect_tag_protocol = lan937x_connect_tag_protocol, 849 .get_phy_flags = ksz_get_phy_flags, 850 .setup = lan937x_setup, 851 .teardown = ksz_teardown, 852 .phy_read = lan937x_phy_read16, 853 .phy_write = lan937x_phy_write16, 854 .phylink_get_caps = lan937x_phylink_get_caps, 855 .port_setup = lan937x_dsa_port_setup, 856 .set_ageing_time = lan937x_set_ageing_time, 857 .get_strings = ksz_get_strings, 858 .get_ethtool_stats = ksz_get_ethtool_stats, 859 .get_sset_count = ksz_sset_count, 860 .port_bridge_join = ksz_port_bridge_join, 861 .port_bridge_leave = ksz_port_bridge_leave, 862 .port_hsr_join = ksz_hsr_join, 863 .port_hsr_leave = ksz_hsr_leave, 864 .port_set_mac_address = ksz_port_set_mac_address, 865 .port_stp_state_set = ksz_port_stp_state_set, 866 .port_teardown = ksz_port_teardown, 867 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 868 .port_bridge_flags = ksz_port_bridge_flags, 869 .port_fast_age = ksz9477_flush_dyn_mac_table, 870 .port_vlan_filtering = ksz9477_port_vlan_filtering, 871 .port_vlan_add = ksz9477_port_vlan_add, 872 .port_vlan_del = ksz9477_port_vlan_del, 873 .port_fdb_dump = ksz9477_fdb_dump, 874 .port_fdb_add = ksz9477_fdb_add, 875 .port_fdb_del = ksz9477_fdb_del, 876 .port_mdb_add = ksz9477_mdb_add, 877 .port_mdb_del = ksz9477_mdb_del, 878 .port_mirror_add = ksz9477_port_mirror_add, 879 .port_mirror_del = ksz9477_port_mirror_del, 880 .get_stats64 = ksz_get_stats64, 881 .get_pause_stats = ksz_get_pause_stats, 882 .port_change_mtu = lan937x_change_mtu, 883 .port_max_mtu = ksz_max_mtu, 884 .get_wol = ksz_get_wol, 885 .set_wol = ksz_set_wol, 886 .suspend = ksz_suspend, 887 .resume = ksz_resume, 888 .get_ts_info = ksz_get_ts_info, 889 .port_hwtstamp_get = ksz_hwtstamp_get, 890 .port_hwtstamp_set = ksz_hwtstamp_set, 891 .port_txtstamp = ksz_port_txtstamp, 892 .port_rxtstamp = ksz_port_rxtstamp, 893 .cls_flower_add = ksz_cls_flower_add, 894 .cls_flower_del = ksz_cls_flower_del, 895 .port_setup_tc = ksz_setup_tc, 896 .support_eee = ksz_support_eee, 897 .set_mac_eee = ksz_set_mac_eee, 898 .port_get_default_prio = ksz_port_get_default_prio, 899 .port_set_default_prio = ksz_port_set_default_prio, 900 .port_get_dscp_prio = ksz_port_get_dscp_prio, 901 .port_add_dscp_prio = ksz_port_add_dscp_prio, 902 .port_del_dscp_prio = ksz_port_del_dscp_prio, 903 .port_get_apptrust = ksz_port_get_apptrust, 904 .port_set_apptrust = ksz_port_set_apptrust, 905 }; 906 907 MODULE_AUTHOR("Arun Ramadoss <arun.ramadoss@microchip.com>"); 908 MODULE_DESCRIPTION("Microchip LAN937x Series Switch DSA Driver"); 909 MODULE_LICENSE("GPL"); 910