1 // SPDX-License-Identifier: GPL-2.0 2 /* Microchip LAN937X switch driver main logic 3 * Copyright (C) 2019-2022 Microchip Technology Inc. 4 */ 5 #include <linux/kernel.h> 6 #include <linux/module.h> 7 #include <linux/iopoll.h> 8 #include <linux/phy.h> 9 #include <linux/of_net.h> 10 #include <linux/if_bridge.h> 11 #include <linux/if_vlan.h> 12 #include <linux/math.h> 13 #include <net/dsa.h> 14 #include <net/switchdev.h> 15 16 #include "lan937x_reg.h" 17 #include "ksz_common.h" 18 #include "ksz9477.h" 19 #include "lan937x.h" 20 21 /* marker for ports without built-in PHY */ 22 #define LAN937X_NO_PHY U8_MAX 23 24 /* 25 * lan9370_phy_addr - Mapping of LAN9370 switch ports to PHY addresses. 26 * 27 * Each entry corresponds to a specific port on the LAN9370 switch, 28 * where ports 1-4 are connected to integrated 100BASE-T1 PHYs, and 29 * Port 5 is connected to an RGMII interface without a PHY. The values 30 * are based on the documentation (DS00003108E, section 3.3). 31 */ 32 static const u8 lan9370_phy_addr[] = { 33 [0] = 2, /* Port 1, T1 AFE0 */ 34 [1] = 3, /* Port 2, T1 AFE1 */ 35 [2] = 5, /* Port 3, T1 AFE3 */ 36 [3] = 6, /* Port 4, T1 AFE4 */ 37 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 38 }; 39 40 /* 41 * lan9371_phy_addr - Mapping of LAN9371 switch ports to PHY addresses. 42 * 43 * The values are based on the documentation (DS00003109E, section 3.3). 44 */ 45 static const u8 lan9371_phy_addr[] = { 46 [0] = 2, /* Port 1, T1 AFE0 */ 47 [1] = 3, /* Port 2, T1 AFE1 */ 48 [2] = 5, /* Port 3, T1 AFE3 */ 49 [3] = 8, /* Port 4, TX PHY */ 50 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 51 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */ 52 }; 53 54 /* 55 * lan9372_phy_addr - Mapping of LAN9372 switch ports to PHY addresses. 56 * 57 * The values are based on the documentation (DS00003110F, section 3.3). 58 */ 59 static const u8 lan9372_phy_addr[] = { 60 [0] = 2, /* Port 1, T1 AFE0 */ 61 [1] = 3, /* Port 2, T1 AFE1 */ 62 [2] = 5, /* Port 3, T1 AFE3 */ 63 [3] = 8, /* Port 4, TX PHY */ 64 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 65 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */ 66 [6] = 6, /* Port 7, T1 AFE4 */ 67 [7] = 4, /* Port 8, T1 AFE2 */ 68 }; 69 70 /* 71 * lan9373_phy_addr - Mapping of LAN9373 switch ports to PHY addresses. 72 * 73 * The values are based on the documentation (DS00003110F, section 3.3). 74 */ 75 static const u8 lan9373_phy_addr[] = { 76 [0] = 2, /* Port 1, T1 AFE0 */ 77 [1] = 3, /* Port 2, T1 AFE1 */ 78 [2] = 5, /* Port 3, T1 AFE3 */ 79 [3] = LAN937X_NO_PHY, /* Port 4, SGMII */ 80 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 81 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */ 82 [6] = 6, /* Port 7, T1 AFE4 */ 83 [7] = 4, /* Port 8, T1 AFE2 */ 84 }; 85 86 /* 87 * lan9374_phy_addr - Mapping of LAN9374 switch ports to PHY addresses. 88 * 89 * The values are based on the documentation (DS00003110F, section 3.3). 90 */ 91 static const u8 lan9374_phy_addr[] = { 92 [0] = 2, /* Port 1, T1 AFE0 */ 93 [1] = 3, /* Port 2, T1 AFE1 */ 94 [2] = 5, /* Port 3, T1 AFE3 */ 95 [3] = 7, /* Port 4, T1 AFE5 */ 96 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 97 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */ 98 [6] = 6, /* Port 7, T1 AFE4 */ 99 [7] = 4, /* Port 8, T1 AFE2 */ 100 }; 101 102 static int lan937x_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 103 { 104 return regmap_update_bits(ksz_regmap_8(dev), addr, bits, set ? bits : 0); 105 } 106 107 static int lan937x_port_cfg(struct ksz_device *dev, int port, int offset, 108 u8 bits, bool set) 109 { 110 return regmap_update_bits(ksz_regmap_8(dev), PORT_CTRL_ADDR(port, offset), 111 bits, set ? bits : 0); 112 } 113 114 /** 115 * lan937x_create_phy_addr_map - Create port-to-PHY address map for MDIO bus. 116 * @dev: Pointer to device structure. 117 * @side_mdio: Boolean indicating if the PHYs are accessed over a side MDIO bus. 118 * 119 * This function sets up the PHY address mapping for the LAN937x switches, 120 * which support two access modes for internal PHYs: 121 * 1. **SPI Access**: A straightforward one-to-one port-to-PHY address 122 * mapping is applied. 123 * 2. **MDIO Access**: The PHY address mapping varies based on chip variant 124 * and strap configuration. An offset is calculated based on strap settings 125 * to ensure correct PHY addresses are assigned. The offset calculation logic 126 * is based on Microchip's Article Number 000015828, available at: 127 * https://microchip.my.site.com/s/article/LAN9374-Virtual-PHY-PHY-Address-Mapping 128 * 129 * The function first checks if side MDIO access is disabled, in which case a 130 * simple direct mapping (port number = PHY address) is applied. If side MDIO 131 * access is enabled, it reads the strap configuration to determine the correct 132 * offset for PHY addresses. 133 * 134 * The appropriate mapping table is selected based on the chip ID, and the 135 * `phy_addr_map` is populated with the correct addresses for each port. Any 136 * port with no PHY is assigned a `LAN937X_NO_PHY` marker. 137 * 138 * Return: 0 on success, error code on failure. 139 */ 140 int lan937x_create_phy_addr_map(struct ksz_device *dev, bool side_mdio) 141 { 142 static const u8 *phy_addr_map; 143 u32 strap_val; 144 u8 offset = 0; 145 size_t size; 146 int ret, i; 147 148 if (!side_mdio) { 149 /* simple direct mapping */ 150 for (i = 0; i < dev->info->port_cnt; i++) 151 dev->phy_addr_map[i] = i; 152 153 return 0; 154 } 155 156 ret = ksz_read32(dev, REG_SW_CFG_STRAP_VAL, &strap_val); 157 if (ret < 0) 158 return ret; 159 160 if (!(strap_val & SW_CASCADE_ID_CFG) && !(strap_val & SW_VPHY_ADD_CFG)) 161 offset = 0; 162 else if (!(strap_val & SW_CASCADE_ID_CFG) && (strap_val & SW_VPHY_ADD_CFG)) 163 offset = 7; 164 else if ((strap_val & SW_CASCADE_ID_CFG) && !(strap_val & SW_VPHY_ADD_CFG)) 165 offset = 15; 166 else 167 offset = 22; 168 169 switch (dev->info->chip_id) { 170 case LAN9370_CHIP_ID: 171 phy_addr_map = lan9370_phy_addr; 172 size = ARRAY_SIZE(lan9370_phy_addr); 173 break; 174 case LAN9371_CHIP_ID: 175 phy_addr_map = lan9371_phy_addr; 176 size = ARRAY_SIZE(lan9371_phy_addr); 177 break; 178 case LAN9372_CHIP_ID: 179 phy_addr_map = lan9372_phy_addr; 180 size = ARRAY_SIZE(lan9372_phy_addr); 181 break; 182 case LAN9373_CHIP_ID: 183 phy_addr_map = lan9373_phy_addr; 184 size = ARRAY_SIZE(lan9373_phy_addr); 185 break; 186 case LAN9374_CHIP_ID: 187 phy_addr_map = lan9374_phy_addr; 188 size = ARRAY_SIZE(lan9374_phy_addr); 189 break; 190 default: 191 return -EINVAL; 192 } 193 194 if (size < dev->info->port_cnt) 195 return -EINVAL; 196 197 for (i = 0; i < dev->info->port_cnt; i++) { 198 if (phy_addr_map[i] == LAN937X_NO_PHY) 199 dev->phy_addr_map[i] = phy_addr_map[i]; 200 else 201 dev->phy_addr_map[i] = phy_addr_map[i] + offset; 202 } 203 204 return 0; 205 } 206 207 /** 208 * lan937x_mdio_bus_preinit - Pre-initialize MDIO bus for accessing PHYs. 209 * @dev: Pointer to device structure. 210 * @side_mdio: Boolean indicating if the PHYs are accessed over a side MDIO bus. 211 * 212 * This function configures the LAN937x switch for PHY access either through 213 * SPI or the side MDIO bus, unlocking the necessary registers for each access 214 * mode. 215 * 216 * Operation Modes: 217 * 1. **SPI Access**: Enables SPI indirect access to address clock domain 218 * crossing issues when SPI is used for PHY access. 219 * 2. **MDIO Access**: Grants access to internal PHYs over the side MDIO bus, 220 * required when using the MDIO bus for PHY management. 221 * 222 * Return: 0 on success, error code on failure. 223 */ 224 int lan937x_mdio_bus_preinit(struct ksz_device *dev, bool side_mdio) 225 { 226 u16 data16; 227 int ret; 228 229 /* Unlock access to the PHYs, needed for SPI and side MDIO access */ 230 ret = lan937x_cfg(dev, REG_GLOBAL_CTRL_0, SW_PHY_REG_BLOCK, false); 231 if (ret < 0) 232 goto print_error; 233 234 if (side_mdio) 235 /* Allow access to internal PHYs over MDIO bus */ 236 data16 = VPHY_MDIO_INTERNAL_ENABLE; 237 else 238 /* Enable SPI indirect access to address clock domain crossing 239 * issue 240 */ 241 data16 = VPHY_SPI_INDIRECT_ENABLE; 242 243 ret = ksz_rmw16(dev, REG_VPHY_SPECIAL_CTRL__2, 244 VPHY_SPI_INDIRECT_ENABLE | VPHY_MDIO_INTERNAL_ENABLE, 245 data16); 246 247 print_error: 248 if (ret < 0) 249 dev_err(dev->dev, "failed to preinit the MDIO bus\n"); 250 251 return ret; 252 } 253 254 static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg) 255 { 256 u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE; 257 u16 temp; 258 259 if (is_lan937x_tx_phy(dev, addr)) 260 addr_base = REG_PORT_TX_PHY_CTRL_BASE; 261 262 /* get register address based on the logical port */ 263 temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2))); 264 265 return ksz_write16(dev, REG_VPHY_IND_ADDR__2, temp); 266 } 267 268 static int lan937x_internal_phy_write(struct ksz_device *dev, int addr, int reg, 269 u16 val) 270 { 271 unsigned int value; 272 int ret; 273 274 /* Check for internal phy port */ 275 if (!dev->info->internal_phy[addr]) 276 return -EOPNOTSUPP; 277 278 ret = lan937x_vphy_ind_addr_wr(dev, addr, reg); 279 if (ret < 0) 280 return ret; 281 282 /* Write the data to be written to the VPHY reg */ 283 ret = ksz_write16(dev, REG_VPHY_IND_DATA__2, val); 284 if (ret < 0) 285 return ret; 286 287 /* Write the Write En and Busy bit */ 288 ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, 289 (VPHY_IND_WRITE | VPHY_IND_BUSY)); 290 if (ret < 0) 291 return ret; 292 293 ret = regmap_read_poll_timeout(ksz_regmap_16(dev), REG_VPHY_IND_CTRL__2, 294 value, !(value & VPHY_IND_BUSY), 10, 295 1000); 296 if (ret < 0) { 297 dev_err(dev->dev, "Failed to write phy register\n"); 298 return ret; 299 } 300 301 return 0; 302 } 303 304 static int lan937x_internal_phy_read(struct ksz_device *dev, int addr, int reg, 305 u16 *val) 306 { 307 unsigned int value; 308 int ret; 309 310 /* Check for internal phy port, return 0xffff for non-existent phy */ 311 if (!dev->info->internal_phy[addr]) 312 return 0xffff; 313 314 ret = lan937x_vphy_ind_addr_wr(dev, addr, reg); 315 if (ret < 0) 316 return ret; 317 318 /* Write Read and Busy bit to start the transaction */ 319 ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, VPHY_IND_BUSY); 320 if (ret < 0) 321 return ret; 322 323 ret = regmap_read_poll_timeout(ksz_regmap_16(dev), REG_VPHY_IND_CTRL__2, 324 value, !(value & VPHY_IND_BUSY), 10, 325 1000); 326 if (ret < 0) { 327 dev_err(dev->dev, "Failed to read phy register\n"); 328 return ret; 329 } 330 331 /* Read the VPHY register which has the PHY data */ 332 return ksz_read16(dev, REG_VPHY_IND_DATA__2, val); 333 } 334 335 int lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data) 336 { 337 return lan937x_internal_phy_read(dev, addr, reg, data); 338 } 339 340 int lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val) 341 { 342 return lan937x_internal_phy_write(dev, addr, reg, val); 343 } 344 345 int lan937x_reset_switch(struct ksz_device *dev) 346 { 347 u32 data32; 348 int ret; 349 350 /* reset switch */ 351 ret = lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 352 if (ret < 0) 353 return ret; 354 355 /* Enable Auto Aging */ 356 ret = lan937x_cfg(dev, REG_SW_LUE_CTRL_1, SW_LINK_AUTO_AGING, true); 357 if (ret < 0) 358 return ret; 359 360 /* disable interrupts */ 361 ret = ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 362 if (ret < 0) 363 return ret; 364 365 ret = ksz_write32(dev, REG_SW_INT_STATUS__4, POR_READY_INT); 366 if (ret < 0) 367 return ret; 368 369 ret = ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0xFF); 370 if (ret < 0) 371 return ret; 372 373 return ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 374 } 375 376 void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port) 377 { 378 const u32 *masks = dev->info->masks; 379 const u16 *regs = dev->info->regs; 380 struct dsa_switch *ds = dev->ds; 381 u8 member; 382 383 /* enable tag tail for host port */ 384 if (cpu_port) 385 lan937x_port_cfg(dev, port, REG_PORT_CTRL_0, 386 PORT_TAIL_TAG_ENABLE, true); 387 388 /* Enable the Port Queue split */ 389 ksz9477_port_queue_split(dev, port); 390 391 /* set back pressure for half duplex */ 392 lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, 393 true); 394 395 /* enable 802.1p priority */ 396 lan937x_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 397 398 if (!dev->info->internal_phy[port]) 399 lan937x_port_cfg(dev, port, regs[P_XMII_CTRL_0], 400 masks[P_MII_TX_FLOW_CTRL] | 401 masks[P_MII_RX_FLOW_CTRL], 402 true); 403 404 if (cpu_port) 405 member = dsa_user_ports(ds); 406 else 407 member = BIT(dsa_upstream_port(ds, port)); 408 409 dev->dev_ops->cfg_port_member(dev, port, member); 410 } 411 412 void lan937x_config_cpu_port(struct dsa_switch *ds) 413 { 414 struct ksz_device *dev = ds->priv; 415 struct dsa_port *dp; 416 417 dsa_switch_for_each_cpu_port(dp, ds) { 418 if (dev->info->cpu_ports & (1 << dp->index)) { 419 dev->cpu_port = dp->index; 420 421 /* enable cpu port */ 422 lan937x_port_setup(dev, dp->index, true); 423 } 424 } 425 426 dsa_switch_for_each_user_port(dp, ds) { 427 ksz_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED); 428 } 429 } 430 431 int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu) 432 { 433 struct dsa_switch *ds = dev->ds; 434 int ret; 435 436 new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN; 437 438 if (dsa_is_cpu_port(ds, port)) 439 new_mtu += LAN937X_TAG_LEN; 440 441 if (new_mtu >= FR_MIN_SIZE) 442 ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, 443 PORT_JUMBO_PACKET, true); 444 else 445 ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, 446 PORT_JUMBO_PACKET, false); 447 if (ret < 0) { 448 dev_err(ds->dev, "failed to enable jumbo\n"); 449 return ret; 450 } 451 452 /* Write the frame size in PORT_MAX_FR_SIZE register */ 453 ret = ksz_pwrite16(dev, port, PORT_MAX_FR_SIZE, new_mtu); 454 if (ret) { 455 dev_err(ds->dev, "failed to update mtu for port %d\n", port); 456 return ret; 457 } 458 459 return 0; 460 } 461 462 int lan937x_set_ageing_time(struct ksz_device *dev, unsigned int msecs) 463 { 464 u32 secs = msecs / 1000; 465 u32 value; 466 int ret; 467 468 value = FIELD_GET(SW_AGE_PERIOD_7_0_M, secs); 469 470 ret = ksz_write8(dev, REG_SW_AGE_PERIOD__1, value); 471 if (ret < 0) 472 return ret; 473 474 value = FIELD_GET(SW_AGE_PERIOD_19_8_M, secs); 475 476 return ksz_write16(dev, REG_SW_AGE_PERIOD__2, value); 477 } 478 479 static void lan937x_set_tune_adj(struct ksz_device *dev, int port, 480 u16 reg, u8 val) 481 { 482 u16 data16; 483 484 ksz_pread16(dev, port, reg, &data16); 485 486 /* Update tune Adjust */ 487 data16 |= FIELD_PREP(PORT_TUNE_ADJ, val); 488 ksz_pwrite16(dev, port, reg, data16); 489 490 /* write DLL reset to take effect */ 491 data16 |= PORT_DLL_RESET; 492 ksz_pwrite16(dev, port, reg, data16); 493 } 494 495 static void lan937x_set_rgmii_tx_delay(struct ksz_device *dev, int port) 496 { 497 u8 val; 498 499 /* Apply different codes based on the ports as per characterization 500 * results 501 */ 502 val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_TX_DELAY_2NS : 503 RGMII_2_TX_DELAY_2NS; 504 505 lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_5, val); 506 } 507 508 static void lan937x_set_rgmii_rx_delay(struct ksz_device *dev, int port) 509 { 510 u8 val; 511 512 val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_RX_DELAY_2NS : 513 RGMII_2_RX_DELAY_2NS; 514 515 lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_4, val); 516 } 517 518 void lan937x_phylink_get_caps(struct ksz_device *dev, int port, 519 struct phylink_config *config) 520 { 521 config->mac_capabilities = MAC_100FD; 522 523 if (dev->info->supports_rgmii[port]) { 524 /* MII/RMII/RGMII ports */ 525 config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 526 MAC_100HD | MAC_10 | MAC_1000FD; 527 } else if (is_lan937x_tx_phy(dev, port)) { 528 config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 529 MAC_100HD | MAC_10; 530 } 531 } 532 533 void lan937x_setup_rgmii_delay(struct ksz_device *dev, int port) 534 { 535 struct ksz_port *p = &dev->ports[port]; 536 537 if (p->rgmii_tx_val) { 538 lan937x_set_rgmii_tx_delay(dev, port); 539 dev_info(dev->dev, "Applied rgmii tx delay for the port %d\n", 540 port); 541 } 542 543 if (p->rgmii_rx_val) { 544 lan937x_set_rgmii_rx_delay(dev, port); 545 dev_info(dev->dev, "Applied rgmii rx delay for the port %d\n", 546 port); 547 } 548 } 549 550 int lan937x_tc_cbs_set_cinc(struct ksz_device *dev, int port, u32 val) 551 { 552 return ksz_pwrite32(dev, port, REG_PORT_MTI_CREDIT_INCREMENT, val); 553 } 554 555 int lan937x_switch_init(struct ksz_device *dev) 556 { 557 dev->port_mask = (1 << dev->info->port_cnt) - 1; 558 559 return 0; 560 } 561 562 int lan937x_setup(struct dsa_switch *ds) 563 { 564 struct ksz_device *dev = ds->priv; 565 int ret; 566 567 /* The VLAN aware is a global setting. Mixed vlan 568 * filterings are not supported. 569 */ 570 ds->vlan_filtering_is_global = true; 571 572 /* Enable aggressive back off for half duplex & UNH mode */ 573 ret = lan937x_cfg(dev, REG_SW_MAC_CTRL_0, (SW_PAUSE_UNH_MODE | 574 SW_NEW_BACKOFF | 575 SW_AGGR_BACKOFF), true); 576 if (ret < 0) 577 return ret; 578 579 /* If NO_EXC_COLLISION_DROP bit is set, the switch will not drop 580 * packets when 16 or more collisions occur 581 */ 582 ret = lan937x_cfg(dev, REG_SW_MAC_CTRL_1, NO_EXC_COLLISION_DROP, true); 583 if (ret < 0) 584 return ret; 585 586 /* enable global MIB counter freeze function */ 587 ret = lan937x_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 588 if (ret < 0) 589 return ret; 590 591 /* disable CLK125 & CLK25, 1: disable, 0: enable */ 592 ret = lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, 593 (SW_CLK125_ENB | SW_CLK25_ENB), true); 594 if (ret < 0) 595 return ret; 596 597 /* Disable global VPHY support. Related to CPU interface only? */ 598 return ksz_rmw32(dev, REG_SW_CFG_STRAP_OVR, SW_VPHY_DISABLE, 599 SW_VPHY_DISABLE); 600 } 601 602 void lan937x_teardown(struct dsa_switch *ds) 603 { 604 605 } 606 607 void lan937x_switch_exit(struct ksz_device *dev) 608 { 609 lan937x_reset_switch(dev); 610 } 611 612 MODULE_AUTHOR("Arun Ramadoss <arun.ramadoss@microchip.com>"); 613 MODULE_DESCRIPTION("Microchip LAN937x Series Switch DSA Driver"); 614 MODULE_LICENSE("GPL"); 615