1 // SPDX-License-Identifier: GPL-2.0 2 /* Microchip LAN937X switch driver main logic 3 * Copyright (C) 2019-2022 Microchip Technology Inc. 4 */ 5 #include <linux/kernel.h> 6 #include <linux/module.h> 7 #include <linux/iopoll.h> 8 #include <linux/phy.h> 9 #include <linux/of_net.h> 10 #include <linux/of_mdio.h> 11 #include <linux/if_bridge.h> 12 #include <linux/if_vlan.h> 13 #include <linux/irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/math.h> 16 #include <net/dsa.h> 17 #include <net/switchdev.h> 18 19 #include "lan937x_reg.h" 20 #include "ksz_common.h" 21 #include "lan937x.h" 22 23 #define LAN937x_PNIRQS 6 24 25 static int lan937x_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 26 { 27 return regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 28 } 29 30 static int lan937x_port_cfg(struct ksz_device *dev, int port, int offset, 31 u8 bits, bool set) 32 { 33 return regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 34 bits, set ? bits : 0); 35 } 36 37 static int lan937x_enable_spi_indirect_access(struct ksz_device *dev) 38 { 39 u16 data16; 40 int ret; 41 42 /* Enable Phy access through SPI */ 43 ret = lan937x_cfg(dev, REG_GLOBAL_CTRL_0, SW_PHY_REG_BLOCK, false); 44 if (ret < 0) 45 return ret; 46 47 ret = ksz_read16(dev, REG_VPHY_SPECIAL_CTRL__2, &data16); 48 if (ret < 0) 49 return ret; 50 51 /* Allow SPI access */ 52 data16 |= VPHY_SPI_INDIRECT_ENABLE; 53 54 return ksz_write16(dev, REG_VPHY_SPECIAL_CTRL__2, data16); 55 } 56 57 static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg) 58 { 59 u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE; 60 u16 temp; 61 62 /* get register address based on the logical port */ 63 temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2))); 64 65 return ksz_write16(dev, REG_VPHY_IND_ADDR__2, temp); 66 } 67 68 static int lan937x_internal_phy_write(struct ksz_device *dev, int addr, int reg, 69 u16 val) 70 { 71 unsigned int value; 72 int ret; 73 74 /* Check for internal phy port */ 75 if (!dev->info->internal_phy[addr]) 76 return -EOPNOTSUPP; 77 78 ret = lan937x_vphy_ind_addr_wr(dev, addr, reg); 79 if (ret < 0) 80 return ret; 81 82 /* Write the data to be written to the VPHY reg */ 83 ret = ksz_write16(dev, REG_VPHY_IND_DATA__2, val); 84 if (ret < 0) 85 return ret; 86 87 /* Write the Write En and Busy bit */ 88 ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, 89 (VPHY_IND_WRITE | VPHY_IND_BUSY)); 90 if (ret < 0) 91 return ret; 92 93 ret = regmap_read_poll_timeout(dev->regmap[1], REG_VPHY_IND_CTRL__2, 94 value, !(value & VPHY_IND_BUSY), 10, 95 1000); 96 if (ret < 0) { 97 dev_err(dev->dev, "Failed to write phy register\n"); 98 return ret; 99 } 100 101 return 0; 102 } 103 104 static int lan937x_internal_phy_read(struct ksz_device *dev, int addr, int reg, 105 u16 *val) 106 { 107 unsigned int value; 108 int ret; 109 110 /* Check for internal phy port, return 0xffff for non-existent phy */ 111 if (!dev->info->internal_phy[addr]) 112 return 0xffff; 113 114 ret = lan937x_vphy_ind_addr_wr(dev, addr, reg); 115 if (ret < 0) 116 return ret; 117 118 /* Write Read and Busy bit to start the transaction */ 119 ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, VPHY_IND_BUSY); 120 if (ret < 0) 121 return ret; 122 123 ret = regmap_read_poll_timeout(dev->regmap[1], REG_VPHY_IND_CTRL__2, 124 value, !(value & VPHY_IND_BUSY), 10, 125 1000); 126 if (ret < 0) { 127 dev_err(dev->dev, "Failed to read phy register\n"); 128 return ret; 129 } 130 131 /* Read the VPHY register which has the PHY data */ 132 return ksz_read16(dev, REG_VPHY_IND_DATA__2, val); 133 } 134 135 int lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data) 136 { 137 return lan937x_internal_phy_read(dev, addr, reg, data); 138 } 139 140 int lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val) 141 { 142 return lan937x_internal_phy_write(dev, addr, reg, val); 143 } 144 145 static int lan937x_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 146 { 147 struct ksz_device *dev = bus->priv; 148 u16 val; 149 int ret; 150 151 if (regnum & MII_ADDR_C45) 152 return -EOPNOTSUPP; 153 154 ret = lan937x_internal_phy_read(dev, addr, regnum, &val); 155 if (ret < 0) 156 return ret; 157 158 return val; 159 } 160 161 static int lan937x_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 162 u16 val) 163 { 164 struct ksz_device *dev = bus->priv; 165 166 if (regnum & MII_ADDR_C45) 167 return -EOPNOTSUPP; 168 169 return lan937x_internal_phy_write(dev, addr, regnum, val); 170 } 171 172 static int lan937x_irq_phy_setup(struct ksz_device *dev) 173 { 174 struct dsa_switch *ds = dev->ds; 175 int phy, err_phy; 176 int irq; 177 int ret; 178 179 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) { 180 if (BIT(phy) & ds->phys_mii_mask) { 181 irq = irq_find_mapping(dev->ports[phy].pirq.domain, 182 PORT_SRC_PHY_INT); 183 if (irq < 0) { 184 ret = irq; 185 goto out; 186 } 187 ds->slave_mii_bus->irq[phy] = irq; 188 } 189 } 190 return 0; 191 out: 192 err_phy = phy; 193 194 for (phy = 0; phy < err_phy; phy++) 195 if (BIT(phy) & ds->phys_mii_mask) 196 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]); 197 198 return ret; 199 } 200 201 static void lan937x_irq_phy_free(struct ksz_device *dev) 202 { 203 struct dsa_switch *ds = dev->ds; 204 int phy; 205 206 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) 207 if (BIT(phy) & ds->phys_mii_mask) 208 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]); 209 } 210 211 static int lan937x_mdio_register(struct ksz_device *dev) 212 { 213 struct dsa_switch *ds = dev->ds; 214 struct device_node *mdio_np; 215 struct mii_bus *bus; 216 int ret; 217 218 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 219 if (!mdio_np) { 220 dev_err(ds->dev, "no MDIO bus node\n"); 221 return -ENODEV; 222 } 223 224 bus = devm_mdiobus_alloc(ds->dev); 225 if (!bus) { 226 of_node_put(mdio_np); 227 return -ENOMEM; 228 } 229 230 bus->priv = dev; 231 bus->read = lan937x_sw_mdio_read; 232 bus->write = lan937x_sw_mdio_write; 233 bus->name = "lan937x slave smi"; 234 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 235 bus->parent = ds->dev; 236 bus->phy_mask = ~ds->phys_mii_mask; 237 238 ds->slave_mii_bus = bus; 239 240 ret = lan937x_irq_phy_setup(dev); 241 if (ret) { 242 of_node_put(mdio_np); 243 return ret; 244 } 245 246 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 247 if (ret) { 248 dev_err(ds->dev, "unable to register MDIO bus %s\n", 249 bus->id); 250 lan937x_irq_phy_free(dev); 251 } 252 253 of_node_put(mdio_np); 254 255 return ret; 256 } 257 258 int lan937x_reset_switch(struct ksz_device *dev) 259 { 260 u32 data32; 261 int ret; 262 263 /* reset switch */ 264 ret = lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 265 if (ret < 0) 266 return ret; 267 268 /* Enable Auto Aging */ 269 ret = lan937x_cfg(dev, REG_SW_LUE_CTRL_1, SW_LINK_AUTO_AGING, true); 270 if (ret < 0) 271 return ret; 272 273 /* disable interrupts */ 274 ret = ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 275 if (ret < 0) 276 return ret; 277 278 ret = ksz_write32(dev, REG_SW_INT_STATUS__4, POR_READY_INT); 279 if (ret < 0) 280 return ret; 281 282 ret = ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0xFF); 283 if (ret < 0) 284 return ret; 285 286 return ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 287 } 288 289 void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port) 290 { 291 const u32 *masks = dev->info->masks; 292 const u16 *regs = dev->info->regs; 293 struct dsa_switch *ds = dev->ds; 294 u8 member; 295 296 /* enable tag tail for host port */ 297 if (cpu_port) 298 lan937x_port_cfg(dev, port, REG_PORT_CTRL_0, 299 PORT_TAIL_TAG_ENABLE, true); 300 301 /* set back pressure for half duplex */ 302 lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, 303 true); 304 305 /* enable 802.1p priority */ 306 lan937x_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 307 308 if (!dev->info->internal_phy[port]) 309 lan937x_port_cfg(dev, port, regs[P_XMII_CTRL_0], 310 masks[P_MII_TX_FLOW_CTRL] | 311 masks[P_MII_RX_FLOW_CTRL], 312 true); 313 314 if (cpu_port) 315 member = dsa_user_ports(ds); 316 else 317 member = BIT(dsa_upstream_port(ds, port)); 318 319 dev->dev_ops->cfg_port_member(dev, port, member); 320 } 321 322 void lan937x_config_cpu_port(struct dsa_switch *ds) 323 { 324 struct ksz_device *dev = ds->priv; 325 struct dsa_port *dp; 326 327 dsa_switch_for_each_cpu_port(dp, ds) { 328 if (dev->info->cpu_ports & (1 << dp->index)) { 329 dev->cpu_port = dp->index; 330 331 /* enable cpu port */ 332 lan937x_port_setup(dev, dp->index, true); 333 } 334 } 335 336 dsa_switch_for_each_user_port(dp, ds) { 337 ksz_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED); 338 } 339 } 340 341 int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu) 342 { 343 struct dsa_switch *ds = dev->ds; 344 int ret; 345 346 new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN; 347 348 if (dsa_is_cpu_port(ds, port)) 349 new_mtu += LAN937X_TAG_LEN; 350 351 if (new_mtu >= FR_MIN_SIZE) 352 ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, 353 PORT_JUMBO_PACKET, true); 354 else 355 ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, 356 PORT_JUMBO_PACKET, false); 357 if (ret < 0) { 358 dev_err(ds->dev, "failed to enable jumbo\n"); 359 return ret; 360 } 361 362 /* Write the frame size in PORT_MAX_FR_SIZE register */ 363 ksz_pwrite16(dev, port, PORT_MAX_FR_SIZE, new_mtu); 364 365 return 0; 366 } 367 368 int lan937x_set_ageing_time(struct ksz_device *dev, unsigned int msecs) 369 { 370 u32 secs = msecs / 1000; 371 u32 value; 372 int ret; 373 374 value = FIELD_GET(SW_AGE_PERIOD_7_0_M, secs); 375 376 ret = ksz_write8(dev, REG_SW_AGE_PERIOD__1, value); 377 if (ret < 0) 378 return ret; 379 380 value = FIELD_GET(SW_AGE_PERIOD_19_8_M, secs); 381 382 return ksz_write16(dev, REG_SW_AGE_PERIOD__2, value); 383 } 384 385 static void lan937x_set_tune_adj(struct ksz_device *dev, int port, 386 u16 reg, u8 val) 387 { 388 u16 data16; 389 390 ksz_pread16(dev, port, reg, &data16); 391 392 /* Update tune Adjust */ 393 data16 |= FIELD_PREP(PORT_TUNE_ADJ, val); 394 ksz_pwrite16(dev, port, reg, data16); 395 396 /* write DLL reset to take effect */ 397 data16 |= PORT_DLL_RESET; 398 ksz_pwrite16(dev, port, reg, data16); 399 } 400 401 static void lan937x_set_rgmii_tx_delay(struct ksz_device *dev, int port) 402 { 403 u8 val; 404 405 /* Apply different codes based on the ports as per characterization 406 * results 407 */ 408 val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_TX_DELAY_2NS : 409 RGMII_2_TX_DELAY_2NS; 410 411 lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_5, val); 412 } 413 414 static void lan937x_set_rgmii_rx_delay(struct ksz_device *dev, int port) 415 { 416 u8 val; 417 418 val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_RX_DELAY_2NS : 419 RGMII_2_RX_DELAY_2NS; 420 421 lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_4, val); 422 } 423 424 void lan937x_phylink_get_caps(struct ksz_device *dev, int port, 425 struct phylink_config *config) 426 { 427 config->mac_capabilities = MAC_100FD; 428 429 if (dev->info->supports_rgmii[port]) { 430 /* MII/RMII/RGMII ports */ 431 config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 432 MAC_100HD | MAC_10 | MAC_1000FD; 433 } 434 } 435 436 void lan937x_setup_rgmii_delay(struct ksz_device *dev, int port) 437 { 438 struct ksz_port *p = &dev->ports[port]; 439 440 if (p->rgmii_tx_val) { 441 lan937x_set_rgmii_tx_delay(dev, port); 442 dev_info(dev->dev, "Applied rgmii tx delay for the port %d\n", 443 port); 444 } 445 446 if (p->rgmii_rx_val) { 447 lan937x_set_rgmii_rx_delay(dev, port); 448 dev_info(dev->dev, "Applied rgmii rx delay for the port %d\n", 449 port); 450 } 451 } 452 453 int lan937x_switch_init(struct ksz_device *dev) 454 { 455 dev->port_mask = (1 << dev->info->port_cnt) - 1; 456 457 return 0; 458 } 459 460 static void lan937x_girq_mask(struct irq_data *d) 461 { 462 struct ksz_device *dev = irq_data_get_irq_chip_data(d); 463 unsigned int n = d->hwirq; 464 465 dev->girq.masked |= (1 << n); 466 } 467 468 static void lan937x_girq_unmask(struct irq_data *d) 469 { 470 struct ksz_device *dev = irq_data_get_irq_chip_data(d); 471 unsigned int n = d->hwirq; 472 473 dev->girq.masked &= ~(1 << n); 474 } 475 476 static void lan937x_girq_bus_lock(struct irq_data *d) 477 { 478 struct ksz_device *dev = irq_data_get_irq_chip_data(d); 479 480 mutex_lock(&dev->lock_irq); 481 } 482 483 static void lan937x_girq_bus_sync_unlock(struct irq_data *d) 484 { 485 struct ksz_device *dev = irq_data_get_irq_chip_data(d); 486 int ret; 487 488 ret = ksz_write32(dev, REG_SW_PORT_INT_MASK__4, dev->girq.masked); 489 if (ret) 490 dev_err(dev->dev, "failed to change IRQ mask\n"); 491 492 mutex_unlock(&dev->lock_irq); 493 } 494 495 static const struct irq_chip lan937x_girq_chip = { 496 .name = "lan937x-global", 497 .irq_mask = lan937x_girq_mask, 498 .irq_unmask = lan937x_girq_unmask, 499 .irq_bus_lock = lan937x_girq_bus_lock, 500 .irq_bus_sync_unlock = lan937x_girq_bus_sync_unlock, 501 }; 502 503 static int lan937x_girq_domain_map(struct irq_domain *d, 504 unsigned int irq, irq_hw_number_t hwirq) 505 { 506 struct ksz_device *dev = d->host_data; 507 508 irq_set_chip_data(irq, d->host_data); 509 irq_set_chip_and_handler(irq, &dev->girq.chip, handle_level_irq); 510 irq_set_noprobe(irq); 511 512 return 0; 513 } 514 515 static const struct irq_domain_ops lan937x_girq_domain_ops = { 516 .map = lan937x_girq_domain_map, 517 .xlate = irq_domain_xlate_twocell, 518 }; 519 520 static void lan937x_girq_free(struct ksz_device *dev) 521 { 522 int irq, virq; 523 524 free_irq(dev->irq, dev); 525 526 for (irq = 0; irq < dev->girq.nirqs; irq++) { 527 virq = irq_find_mapping(dev->girq.domain, irq); 528 irq_dispose_mapping(virq); 529 } 530 531 irq_domain_remove(dev->girq.domain); 532 } 533 534 static irqreturn_t lan937x_girq_thread_fn(int irq, void *dev_id) 535 { 536 struct ksz_device *dev = dev_id; 537 unsigned int nhandled = 0; 538 unsigned int sub_irq; 539 unsigned int n; 540 u32 data; 541 int ret; 542 543 /* Read global interrupt status register */ 544 ret = ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data); 545 if (ret) 546 goto out; 547 548 for (n = 0; n < dev->girq.nirqs; ++n) { 549 if (data & (1 << n)) { 550 sub_irq = irq_find_mapping(dev->girq.domain, n); 551 handle_nested_irq(sub_irq); 552 ++nhandled; 553 } 554 } 555 out: 556 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 557 } 558 559 static int lan937x_girq_setup(struct ksz_device *dev) 560 { 561 int ret, irq; 562 563 dev->girq.nirqs = dev->info->port_cnt; 564 dev->girq.domain = irq_domain_add_simple(NULL, dev->girq.nirqs, 0, 565 &lan937x_girq_domain_ops, dev); 566 if (!dev->girq.domain) 567 return -ENOMEM; 568 569 for (irq = 0; irq < dev->girq.nirqs; irq++) 570 irq_create_mapping(dev->girq.domain, irq); 571 572 dev->girq.chip = lan937x_girq_chip; 573 dev->girq.masked = ~0; 574 575 ret = request_threaded_irq(dev->irq, NULL, lan937x_girq_thread_fn, 576 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 577 dev_name(dev->dev), dev); 578 if (ret) 579 goto out; 580 581 return 0; 582 583 out: 584 lan937x_girq_free(dev); 585 586 return ret; 587 } 588 589 static void lan937x_pirq_mask(struct irq_data *d) 590 { 591 struct ksz_port *port = irq_data_get_irq_chip_data(d); 592 unsigned int n = d->hwirq; 593 594 port->pirq.masked |= (1 << n); 595 } 596 597 static void lan937x_pirq_unmask(struct irq_data *d) 598 { 599 struct ksz_port *port = irq_data_get_irq_chip_data(d); 600 unsigned int n = d->hwirq; 601 602 port->pirq.masked &= ~(1 << n); 603 } 604 605 static void lan937x_pirq_bus_lock(struct irq_data *d) 606 { 607 struct ksz_port *port = irq_data_get_irq_chip_data(d); 608 struct ksz_device *dev = port->ksz_dev; 609 610 mutex_lock(&dev->lock_irq); 611 } 612 613 static void lan937x_pirq_bus_sync_unlock(struct irq_data *d) 614 { 615 struct ksz_port *port = irq_data_get_irq_chip_data(d); 616 struct ksz_device *dev = port->ksz_dev; 617 618 ksz_pwrite8(dev, port->num, REG_PORT_INT_MASK, port->pirq.masked); 619 mutex_unlock(&dev->lock_irq); 620 } 621 622 static const struct irq_chip lan937x_pirq_chip = { 623 .name = "lan937x-port", 624 .irq_mask = lan937x_pirq_mask, 625 .irq_unmask = lan937x_pirq_unmask, 626 .irq_bus_lock = lan937x_pirq_bus_lock, 627 .irq_bus_sync_unlock = lan937x_pirq_bus_sync_unlock, 628 }; 629 630 static int lan937x_pirq_domain_map(struct irq_domain *d, unsigned int irq, 631 irq_hw_number_t hwirq) 632 { 633 struct ksz_port *port = d->host_data; 634 635 irq_set_chip_data(irq, d->host_data); 636 irq_set_chip_and_handler(irq, &port->pirq.chip, handle_level_irq); 637 irq_set_noprobe(irq); 638 639 return 0; 640 } 641 642 static const struct irq_domain_ops lan937x_pirq_domain_ops = { 643 .map = lan937x_pirq_domain_map, 644 .xlate = irq_domain_xlate_twocell, 645 }; 646 647 static void lan937x_pirq_free(struct ksz_device *dev, u8 p) 648 { 649 struct ksz_port *port = &dev->ports[p]; 650 int irq, virq; 651 int irq_num; 652 653 irq_num = irq_find_mapping(dev->girq.domain, p); 654 if (irq_num < 0) 655 return; 656 657 free_irq(irq_num, port); 658 659 for (irq = 0; irq < port->pirq.nirqs; irq++) { 660 virq = irq_find_mapping(port->pirq.domain, irq); 661 irq_dispose_mapping(virq); 662 } 663 664 irq_domain_remove(port->pirq.domain); 665 } 666 667 static irqreturn_t lan937x_pirq_thread_fn(int irq, void *dev_id) 668 { 669 struct ksz_port *port = dev_id; 670 unsigned int nhandled = 0; 671 struct ksz_device *dev; 672 unsigned int sub_irq; 673 unsigned int n; 674 u8 data; 675 676 dev = port->ksz_dev; 677 678 /* Read port interrupt status register */ 679 ksz_pread8(dev, port->num, REG_PORT_INT_STATUS, &data); 680 681 for (n = 0; n < port->pirq.nirqs; ++n) { 682 if (data & (1 << n)) { 683 sub_irq = irq_find_mapping(port->pirq.domain, n); 684 handle_nested_irq(sub_irq); 685 ++nhandled; 686 } 687 } 688 689 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 690 } 691 692 static int lan937x_pirq_setup(struct ksz_device *dev, u8 p) 693 { 694 struct ksz_port *port = &dev->ports[p]; 695 int ret, irq; 696 int irq_num; 697 698 port->pirq.nirqs = LAN937x_PNIRQS; 699 port->pirq.domain = irq_domain_add_simple(dev->dev->of_node, 700 port->pirq.nirqs, 0, 701 &lan937x_pirq_domain_ops, 702 port); 703 if (!port->pirq.domain) 704 return -ENOMEM; 705 706 for (irq = 0; irq < port->pirq.nirqs; irq++) 707 irq_create_mapping(port->pirq.domain, irq); 708 709 port->pirq.chip = lan937x_pirq_chip; 710 port->pirq.masked = ~0; 711 712 irq_num = irq_find_mapping(dev->girq.domain, p); 713 if (irq_num < 0) 714 return irq_num; 715 716 snprintf(port->pirq.name, sizeof(port->pirq.name), "port_irq-%d", p); 717 718 ret = request_threaded_irq(irq_num, NULL, lan937x_pirq_thread_fn, 719 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 720 port->pirq.name, port); 721 if (ret) 722 goto out; 723 724 return 0; 725 726 out: 727 lan937x_pirq_free(dev, p); 728 729 return ret; 730 } 731 732 int lan937x_setup(struct dsa_switch *ds) 733 { 734 struct ksz_device *dev = ds->priv; 735 struct dsa_port *dp; 736 int ret; 737 738 /* enable Indirect Access from SPI to the VPHY registers */ 739 ret = lan937x_enable_spi_indirect_access(dev); 740 if (ret < 0) { 741 dev_err(dev->dev, "failed to enable spi indirect access"); 742 return ret; 743 } 744 745 if (dev->irq > 0) { 746 ret = lan937x_girq_setup(dev); 747 if (ret) 748 return ret; 749 750 dsa_switch_for_each_user_port(dp, dev->ds) { 751 ret = lan937x_pirq_setup(dev, dp->index); 752 if (ret) 753 goto out_girq; 754 } 755 } 756 757 ret = lan937x_mdio_register(dev); 758 if (ret < 0) { 759 dev_err(dev->dev, "failed to register the mdio"); 760 goto out_pirq; 761 } 762 763 /* The VLAN aware is a global setting. Mixed vlan 764 * filterings are not supported. 765 */ 766 ds->vlan_filtering_is_global = true; 767 768 /* Enable aggressive back off for half duplex & UNH mode */ 769 lan937x_cfg(dev, REG_SW_MAC_CTRL_0, 770 (SW_PAUSE_UNH_MODE | SW_NEW_BACKOFF | SW_AGGR_BACKOFF), 771 true); 772 773 /* If NO_EXC_COLLISION_DROP bit is set, the switch will not drop 774 * packets when 16 or more collisions occur 775 */ 776 lan937x_cfg(dev, REG_SW_MAC_CTRL_1, NO_EXC_COLLISION_DROP, true); 777 778 /* enable global MIB counter freeze function */ 779 lan937x_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 780 781 /* disable CLK125 & CLK25, 1: disable, 0: enable */ 782 lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, 783 (SW_CLK125_ENB | SW_CLK25_ENB), true); 784 785 return 0; 786 787 out_pirq: 788 if (dev->irq > 0) 789 dsa_switch_for_each_user_port(dp, dev->ds) 790 lan937x_pirq_free(dev, dp->index); 791 out_girq: 792 if (dev->irq > 0) 793 lan937x_girq_free(dev); 794 795 return ret; 796 } 797 798 void lan937x_teardown(struct dsa_switch *ds) 799 { 800 struct ksz_device *dev = ds->priv; 801 struct dsa_port *dp; 802 803 if (dev->irq > 0) { 804 dsa_switch_for_each_user_port(dp, dev->ds) 805 lan937x_pirq_free(dev, dp->index); 806 807 lan937x_girq_free(dev); 808 } 809 } 810 811 void lan937x_switch_exit(struct ksz_device *dev) 812 { 813 lan937x_reset_switch(dev); 814 } 815 816 MODULE_AUTHOR("Arun Ramadoss <arun.ramadoss@microchip.com>"); 817 MODULE_DESCRIPTION("Microchip LAN937x Series Switch DSA Driver"); 818 MODULE_LICENSE("GPL"); 819