1 // SPDX-License-Identifier: GPL-2.0 2 /* Microchip LAN937X switch driver main logic 3 * Copyright (C) 2019-2022 Microchip Technology Inc. 4 */ 5 #include <linux/kernel.h> 6 #include <linux/module.h> 7 #include <linux/iopoll.h> 8 #include <linux/phy.h> 9 #include <linux/of_net.h> 10 #include <linux/if_bridge.h> 11 #include <linux/if_vlan.h> 12 #include <linux/math.h> 13 #include <net/dsa.h> 14 #include <net/switchdev.h> 15 16 #include "lan937x_reg.h" 17 #include "ksz_common.h" 18 #include "ksz9477.h" 19 #include "lan937x.h" 20 21 static int lan937x_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 22 { 23 return regmap_update_bits(ksz_regmap_8(dev), addr, bits, set ? bits : 0); 24 } 25 26 static int lan937x_port_cfg(struct ksz_device *dev, int port, int offset, 27 u8 bits, bool set) 28 { 29 return regmap_update_bits(ksz_regmap_8(dev), PORT_CTRL_ADDR(port, offset), 30 bits, set ? bits : 0); 31 } 32 33 static int lan937x_enable_spi_indirect_access(struct ksz_device *dev) 34 { 35 u16 data16; 36 int ret; 37 38 /* Enable Phy access through SPI */ 39 ret = lan937x_cfg(dev, REG_GLOBAL_CTRL_0, SW_PHY_REG_BLOCK, false); 40 if (ret < 0) 41 return ret; 42 43 ret = ksz_read16(dev, REG_VPHY_SPECIAL_CTRL__2, &data16); 44 if (ret < 0) 45 return ret; 46 47 /* Allow SPI access */ 48 data16 |= VPHY_SPI_INDIRECT_ENABLE; 49 50 return ksz_write16(dev, REG_VPHY_SPECIAL_CTRL__2, data16); 51 } 52 53 static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg) 54 { 55 u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE; 56 u16 temp; 57 58 if ((dev->info->chip_id == LAN9371_CHIP_ID || 59 dev->info->chip_id == LAN9372_CHIP_ID) && addr == KSZ_PORT_4) 60 addr_base = REG_PORT_TX_PHY_CTRL_BASE; 61 62 /* get register address based on the logical port */ 63 temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2))); 64 65 return ksz_write16(dev, REG_VPHY_IND_ADDR__2, temp); 66 } 67 68 static int lan937x_internal_phy_write(struct ksz_device *dev, int addr, int reg, 69 u16 val) 70 { 71 unsigned int value; 72 int ret; 73 74 /* Check for internal phy port */ 75 if (!dev->info->internal_phy[addr]) 76 return -EOPNOTSUPP; 77 78 ret = lan937x_vphy_ind_addr_wr(dev, addr, reg); 79 if (ret < 0) 80 return ret; 81 82 /* Write the data to be written to the VPHY reg */ 83 ret = ksz_write16(dev, REG_VPHY_IND_DATA__2, val); 84 if (ret < 0) 85 return ret; 86 87 /* Write the Write En and Busy bit */ 88 ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, 89 (VPHY_IND_WRITE | VPHY_IND_BUSY)); 90 if (ret < 0) 91 return ret; 92 93 ret = regmap_read_poll_timeout(ksz_regmap_16(dev), REG_VPHY_IND_CTRL__2, 94 value, !(value & VPHY_IND_BUSY), 10, 95 1000); 96 if (ret < 0) { 97 dev_err(dev->dev, "Failed to write phy register\n"); 98 return ret; 99 } 100 101 return 0; 102 } 103 104 static int lan937x_internal_phy_read(struct ksz_device *dev, int addr, int reg, 105 u16 *val) 106 { 107 unsigned int value; 108 int ret; 109 110 /* Check for internal phy port, return 0xffff for non-existent phy */ 111 if (!dev->info->internal_phy[addr]) 112 return 0xffff; 113 114 ret = lan937x_vphy_ind_addr_wr(dev, addr, reg); 115 if (ret < 0) 116 return ret; 117 118 /* Write Read and Busy bit to start the transaction */ 119 ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, VPHY_IND_BUSY); 120 if (ret < 0) 121 return ret; 122 123 ret = regmap_read_poll_timeout(ksz_regmap_16(dev), REG_VPHY_IND_CTRL__2, 124 value, !(value & VPHY_IND_BUSY), 10, 125 1000); 126 if (ret < 0) { 127 dev_err(dev->dev, "Failed to read phy register\n"); 128 return ret; 129 } 130 131 /* Read the VPHY register which has the PHY data */ 132 return ksz_read16(dev, REG_VPHY_IND_DATA__2, val); 133 } 134 135 int lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data) 136 { 137 return lan937x_internal_phy_read(dev, addr, reg, data); 138 } 139 140 int lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val) 141 { 142 return lan937x_internal_phy_write(dev, addr, reg, val); 143 } 144 145 int lan937x_reset_switch(struct ksz_device *dev) 146 { 147 u32 data32; 148 int ret; 149 150 /* reset switch */ 151 ret = lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 152 if (ret < 0) 153 return ret; 154 155 /* Enable Auto Aging */ 156 ret = lan937x_cfg(dev, REG_SW_LUE_CTRL_1, SW_LINK_AUTO_AGING, true); 157 if (ret < 0) 158 return ret; 159 160 /* disable interrupts */ 161 ret = ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 162 if (ret < 0) 163 return ret; 164 165 ret = ksz_write32(dev, REG_SW_INT_STATUS__4, POR_READY_INT); 166 if (ret < 0) 167 return ret; 168 169 ret = ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0xFF); 170 if (ret < 0) 171 return ret; 172 173 return ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 174 } 175 176 void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port) 177 { 178 const u32 *masks = dev->info->masks; 179 const u16 *regs = dev->info->regs; 180 struct dsa_switch *ds = dev->ds; 181 u8 member; 182 183 /* enable tag tail for host port */ 184 if (cpu_port) 185 lan937x_port_cfg(dev, port, REG_PORT_CTRL_0, 186 PORT_TAIL_TAG_ENABLE, true); 187 188 /* Enable the Port Queue split */ 189 ksz9477_port_queue_split(dev, port); 190 191 /* set back pressure for half duplex */ 192 lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, 193 true); 194 195 /* enable 802.1p priority */ 196 lan937x_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 197 198 if (!dev->info->internal_phy[port]) 199 lan937x_port_cfg(dev, port, regs[P_XMII_CTRL_0], 200 masks[P_MII_TX_FLOW_CTRL] | 201 masks[P_MII_RX_FLOW_CTRL], 202 true); 203 204 if (cpu_port) 205 member = dsa_user_ports(ds); 206 else 207 member = BIT(dsa_upstream_port(ds, port)); 208 209 dev->dev_ops->cfg_port_member(dev, port, member); 210 } 211 212 void lan937x_config_cpu_port(struct dsa_switch *ds) 213 { 214 struct ksz_device *dev = ds->priv; 215 struct dsa_port *dp; 216 217 dsa_switch_for_each_cpu_port(dp, ds) { 218 if (dev->info->cpu_ports & (1 << dp->index)) { 219 dev->cpu_port = dp->index; 220 221 /* enable cpu port */ 222 lan937x_port_setup(dev, dp->index, true); 223 } 224 } 225 226 dsa_switch_for_each_user_port(dp, ds) { 227 ksz_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED); 228 } 229 } 230 231 int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu) 232 { 233 struct dsa_switch *ds = dev->ds; 234 int ret; 235 236 new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN; 237 238 if (dsa_is_cpu_port(ds, port)) 239 new_mtu += LAN937X_TAG_LEN; 240 241 if (new_mtu >= FR_MIN_SIZE) 242 ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, 243 PORT_JUMBO_PACKET, true); 244 else 245 ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, 246 PORT_JUMBO_PACKET, false); 247 if (ret < 0) { 248 dev_err(ds->dev, "failed to enable jumbo\n"); 249 return ret; 250 } 251 252 /* Write the frame size in PORT_MAX_FR_SIZE register */ 253 ret = ksz_pwrite16(dev, port, PORT_MAX_FR_SIZE, new_mtu); 254 if (ret) { 255 dev_err(ds->dev, "failed to update mtu for port %d\n", port); 256 return ret; 257 } 258 259 return 0; 260 } 261 262 int lan937x_set_ageing_time(struct ksz_device *dev, unsigned int msecs) 263 { 264 u32 secs = msecs / 1000; 265 u32 value; 266 int ret; 267 268 value = FIELD_GET(SW_AGE_PERIOD_7_0_M, secs); 269 270 ret = ksz_write8(dev, REG_SW_AGE_PERIOD__1, value); 271 if (ret < 0) 272 return ret; 273 274 value = FIELD_GET(SW_AGE_PERIOD_19_8_M, secs); 275 276 return ksz_write16(dev, REG_SW_AGE_PERIOD__2, value); 277 } 278 279 static void lan937x_set_tune_adj(struct ksz_device *dev, int port, 280 u16 reg, u8 val) 281 { 282 u16 data16; 283 284 ksz_pread16(dev, port, reg, &data16); 285 286 /* Update tune Adjust */ 287 data16 |= FIELD_PREP(PORT_TUNE_ADJ, val); 288 ksz_pwrite16(dev, port, reg, data16); 289 290 /* write DLL reset to take effect */ 291 data16 |= PORT_DLL_RESET; 292 ksz_pwrite16(dev, port, reg, data16); 293 } 294 295 static void lan937x_set_rgmii_tx_delay(struct ksz_device *dev, int port) 296 { 297 u8 val; 298 299 /* Apply different codes based on the ports as per characterization 300 * results 301 */ 302 val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_TX_DELAY_2NS : 303 RGMII_2_TX_DELAY_2NS; 304 305 lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_5, val); 306 } 307 308 static void lan937x_set_rgmii_rx_delay(struct ksz_device *dev, int port) 309 { 310 u8 val; 311 312 val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_RX_DELAY_2NS : 313 RGMII_2_RX_DELAY_2NS; 314 315 lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_4, val); 316 } 317 318 void lan937x_phylink_get_caps(struct ksz_device *dev, int port, 319 struct phylink_config *config) 320 { 321 config->mac_capabilities = MAC_100FD; 322 323 if (dev->info->supports_rgmii[port]) { 324 /* MII/RMII/RGMII ports */ 325 config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 326 MAC_100HD | MAC_10 | MAC_1000FD; 327 } 328 } 329 330 void lan937x_setup_rgmii_delay(struct ksz_device *dev, int port) 331 { 332 struct ksz_port *p = &dev->ports[port]; 333 334 if (p->rgmii_tx_val) { 335 lan937x_set_rgmii_tx_delay(dev, port); 336 dev_info(dev->dev, "Applied rgmii tx delay for the port %d\n", 337 port); 338 } 339 340 if (p->rgmii_rx_val) { 341 lan937x_set_rgmii_rx_delay(dev, port); 342 dev_info(dev->dev, "Applied rgmii rx delay for the port %d\n", 343 port); 344 } 345 } 346 347 int lan937x_tc_cbs_set_cinc(struct ksz_device *dev, int port, u32 val) 348 { 349 return ksz_pwrite32(dev, port, REG_PORT_MTI_CREDIT_INCREMENT, val); 350 } 351 352 int lan937x_switch_init(struct ksz_device *dev) 353 { 354 dev->port_mask = (1 << dev->info->port_cnt) - 1; 355 356 return 0; 357 } 358 359 int lan937x_setup(struct dsa_switch *ds) 360 { 361 struct ksz_device *dev = ds->priv; 362 int ret; 363 364 /* enable Indirect Access from SPI to the VPHY registers */ 365 ret = lan937x_enable_spi_indirect_access(dev); 366 if (ret < 0) { 367 dev_err(dev->dev, "failed to enable spi indirect access"); 368 return ret; 369 } 370 371 /* The VLAN aware is a global setting. Mixed vlan 372 * filterings are not supported. 373 */ 374 ds->vlan_filtering_is_global = true; 375 376 /* Enable aggressive back off for half duplex & UNH mode */ 377 ret = lan937x_cfg(dev, REG_SW_MAC_CTRL_0, (SW_PAUSE_UNH_MODE | 378 SW_NEW_BACKOFF | 379 SW_AGGR_BACKOFF), true); 380 if (ret < 0) 381 return ret; 382 383 /* If NO_EXC_COLLISION_DROP bit is set, the switch will not drop 384 * packets when 16 or more collisions occur 385 */ 386 ret = lan937x_cfg(dev, REG_SW_MAC_CTRL_1, NO_EXC_COLLISION_DROP, true); 387 if (ret < 0) 388 return ret; 389 390 /* enable global MIB counter freeze function */ 391 ret = lan937x_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 392 if (ret < 0) 393 return ret; 394 395 /* disable CLK125 & CLK25, 1: disable, 0: enable */ 396 ret = lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, 397 (SW_CLK125_ENB | SW_CLK25_ENB), true); 398 if (ret < 0) 399 return ret; 400 401 /* Disable global VPHY support. Related to CPU interface only? */ 402 return ksz_rmw32(dev, REG_SW_CFG_STRAP_OVR, SW_VPHY_DISABLE, 403 SW_VPHY_DISABLE); 404 } 405 406 void lan937x_teardown(struct dsa_switch *ds) 407 { 408 409 } 410 411 void lan937x_switch_exit(struct ksz_device *dev) 412 { 413 lan937x_reset_switch(dev); 414 } 415 416 MODULE_AUTHOR("Arun Ramadoss <arun.ramadoss@microchip.com>"); 417 MODULE_DESCRIPTION("Microchip LAN937x Series Switch DSA Driver"); 418 MODULE_LICENSE("GPL"); 419