1 // SPDX-License-Identifier: GPL-2.0 2 /* Microchip LAN937X switch driver main logic 3 * Copyright (C) 2019-2024 Microchip Technology Inc. 4 */ 5 #include <linux/dsa/ksz_common.h> 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/iopoll.h> 9 #include <linux/phy.h> 10 #include <linux/of_net.h> 11 #include <linux/if_bridge.h> 12 #include <linux/if_vlan.h> 13 #include <linux/math.h> 14 #include <net/dsa.h> 15 #include <net/switchdev.h> 16 17 #include "lan937x_reg.h" 18 #include "ksz_common.h" 19 #include "ksz_dcb.h" 20 #include "ksz9477.h" 21 #include "lan937x.h" 22 23 /* marker for ports without built-in PHY */ 24 #define LAN937X_NO_PHY U8_MAX 25 26 /* 27 * lan9370_phy_addr - Mapping of LAN9370 switch ports to PHY addresses. 28 * 29 * Each entry corresponds to a specific port on the LAN9370 switch, 30 * where ports 1-4 are connected to integrated 100BASE-T1 PHYs, and 31 * Port 5 is connected to an RGMII interface without a PHY. The values 32 * are based on the documentation (DS00003108E, section 3.3). 33 */ 34 static const u8 lan9370_phy_addr[] = { 35 [0] = 2, /* Port 1, T1 AFE0 */ 36 [1] = 3, /* Port 2, T1 AFE1 */ 37 [2] = 5, /* Port 3, T1 AFE3 */ 38 [3] = 6, /* Port 4, T1 AFE4 */ 39 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 40 }; 41 42 /* 43 * lan9371_phy_addr - Mapping of LAN9371 switch ports to PHY addresses. 44 * 45 * The values are based on the documentation (DS00003109E, section 3.3). 46 */ 47 static const u8 lan9371_phy_addr[] = { 48 [0] = 2, /* Port 1, T1 AFE0 */ 49 [1] = 3, /* Port 2, T1 AFE1 */ 50 [2] = 5, /* Port 3, T1 AFE3 */ 51 [3] = 8, /* Port 4, TX PHY */ 52 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 53 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */ 54 }; 55 56 /* 57 * lan9372_phy_addr - Mapping of LAN9372 switch ports to PHY addresses. 58 * 59 * The values are based on the documentation (DS00003110F, section 3.3). 60 */ 61 static const u8 lan9372_phy_addr[] = { 62 [0] = 2, /* Port 1, T1 AFE0 */ 63 [1] = 3, /* Port 2, T1 AFE1 */ 64 [2] = 5, /* Port 3, T1 AFE3 */ 65 [3] = 8, /* Port 4, TX PHY */ 66 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 67 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */ 68 [6] = 6, /* Port 7, T1 AFE4 */ 69 [7] = 4, /* Port 8, T1 AFE2 */ 70 }; 71 72 /* 73 * lan9373_phy_addr - Mapping of LAN9373 switch ports to PHY addresses. 74 * 75 * The values are based on the documentation (DS00003110F, section 3.3). 76 */ 77 static const u8 lan9373_phy_addr[] = { 78 [0] = 2, /* Port 1, T1 AFE0 */ 79 [1] = 3, /* Port 2, T1 AFE1 */ 80 [2] = 5, /* Port 3, T1 AFE3 */ 81 [3] = LAN937X_NO_PHY, /* Port 4, SGMII */ 82 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 83 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */ 84 [6] = 6, /* Port 7, T1 AFE4 */ 85 [7] = 4, /* Port 8, T1 AFE2 */ 86 }; 87 88 /* 89 * lan9374_phy_addr - Mapping of LAN9374 switch ports to PHY addresses. 90 * 91 * The values are based on the documentation (DS00003110F, section 3.3). 92 */ 93 static const u8 lan9374_phy_addr[] = { 94 [0] = 2, /* Port 1, T1 AFE0 */ 95 [1] = 3, /* Port 2, T1 AFE1 */ 96 [2] = 5, /* Port 3, T1 AFE3 */ 97 [3] = 7, /* Port 4, T1 AFE5 */ 98 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 99 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */ 100 [6] = 6, /* Port 7, T1 AFE4 */ 101 [7] = 4, /* Port 8, T1 AFE2 */ 102 }; 103 104 static int lan937x_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 105 { 106 return regmap_update_bits(ksz_regmap_8(dev), addr, bits, set ? bits : 0); 107 } 108 109 static int lan937x_port_cfg(struct ksz_device *dev, int port, int offset, 110 u8 bits, bool set) 111 { 112 return regmap_update_bits(ksz_regmap_8(dev), PORT_CTRL_ADDR(port, offset), 113 bits, set ? bits : 0); 114 } 115 116 /** 117 * lan937x_create_phy_addr_map - Create port-to-PHY address map for MDIO bus. 118 * @dev: Pointer to device structure. 119 * @side_mdio: Boolean indicating if the PHYs are accessed over a side MDIO bus. 120 * 121 * This function sets up the PHY address mapping for the LAN937x switches, 122 * which support two access modes for internal PHYs: 123 * 1. **SPI Access**: A straightforward one-to-one port-to-PHY address 124 * mapping is applied. 125 * 2. **MDIO Access**: The PHY address mapping varies based on chip variant 126 * and strap configuration. An offset is calculated based on strap settings 127 * to ensure correct PHY addresses are assigned. The offset calculation logic 128 * is based on Microchip's Article Number 000015828, available at: 129 * https://microchip.my.site.com/s/article/LAN9374-Virtual-PHY-PHY-Address-Mapping 130 * 131 * The function first checks if side MDIO access is disabled, in which case a 132 * simple direct mapping (port number = PHY address) is applied. If side MDIO 133 * access is enabled, it reads the strap configuration to determine the correct 134 * offset for PHY addresses. 135 * 136 * The appropriate mapping table is selected based on the chip ID, and the 137 * `phy_addr_map` is populated with the correct addresses for each port. Any 138 * port with no PHY is assigned a `LAN937X_NO_PHY` marker. 139 * 140 * Return: 0 on success, error code on failure. 141 */ 142 static int lan937x_create_phy_addr_map(struct ksz_device *dev, bool side_mdio) 143 { 144 static const u8 *phy_addr_map; 145 u32 strap_val; 146 u8 offset = 0; 147 size_t size; 148 int ret, i; 149 150 if (!side_mdio) { 151 /* simple direct mapping */ 152 for (i = 0; i < dev->info->port_cnt; i++) 153 dev->phy_addr_map[i] = i; 154 155 return 0; 156 } 157 158 ret = ksz_read32(dev, REG_SW_CFG_STRAP_VAL, &strap_val); 159 if (ret < 0) 160 return ret; 161 162 if (!(strap_val & SW_CASCADE_ID_CFG) && !(strap_val & SW_VPHY_ADD_CFG)) 163 offset = 0; 164 else if (!(strap_val & SW_CASCADE_ID_CFG) && (strap_val & SW_VPHY_ADD_CFG)) 165 offset = 7; 166 else if ((strap_val & SW_CASCADE_ID_CFG) && !(strap_val & SW_VPHY_ADD_CFG)) 167 offset = 15; 168 else 169 offset = 22; 170 171 switch (dev->info->chip_id) { 172 case LAN9370_CHIP_ID: 173 phy_addr_map = lan9370_phy_addr; 174 size = ARRAY_SIZE(lan9370_phy_addr); 175 break; 176 case LAN9371_CHIP_ID: 177 phy_addr_map = lan9371_phy_addr; 178 size = ARRAY_SIZE(lan9371_phy_addr); 179 break; 180 case LAN9372_CHIP_ID: 181 phy_addr_map = lan9372_phy_addr; 182 size = ARRAY_SIZE(lan9372_phy_addr); 183 break; 184 case LAN9373_CHIP_ID: 185 phy_addr_map = lan9373_phy_addr; 186 size = ARRAY_SIZE(lan9373_phy_addr); 187 break; 188 case LAN9374_CHIP_ID: 189 phy_addr_map = lan9374_phy_addr; 190 size = ARRAY_SIZE(lan9374_phy_addr); 191 break; 192 default: 193 return -EINVAL; 194 } 195 196 if (size < dev->info->port_cnt) 197 return -EINVAL; 198 199 for (i = 0; i < dev->info->port_cnt; i++) { 200 if (phy_addr_map[i] == LAN937X_NO_PHY) 201 dev->phy_addr_map[i] = phy_addr_map[i]; 202 else 203 dev->phy_addr_map[i] = phy_addr_map[i] + offset; 204 } 205 206 return 0; 207 } 208 209 /** 210 * lan937x_mdio_bus_preinit - Pre-initialize MDIO bus for accessing PHYs. 211 * @dev: Pointer to device structure. 212 * @side_mdio: Boolean indicating if the PHYs are accessed over a side MDIO bus. 213 * 214 * This function configures the LAN937x switch for PHY access either through 215 * SPI or the side MDIO bus, unlocking the necessary registers for each access 216 * mode. 217 * 218 * Operation Modes: 219 * 1. **SPI Access**: Enables SPI indirect access to address clock domain 220 * crossing issues when SPI is used for PHY access. 221 * 2. **MDIO Access**: Grants access to internal PHYs over the side MDIO bus, 222 * required when using the MDIO bus for PHY management. 223 * 224 * Return: 0 on success, error code on failure. 225 */ 226 static int lan937x_mdio_bus_preinit(struct ksz_device *dev, bool side_mdio) 227 { 228 u16 data16; 229 int ret; 230 231 /* Unlock access to the PHYs, needed for SPI and side MDIO access */ 232 ret = lan937x_cfg(dev, REG_GLOBAL_CTRL_0, SW_PHY_REG_BLOCK, false); 233 if (ret < 0) 234 goto print_error; 235 236 if (side_mdio) 237 /* Allow access to internal PHYs over MDIO bus */ 238 data16 = VPHY_MDIO_INTERNAL_ENABLE; 239 else 240 /* Enable SPI indirect access to address clock domain crossing 241 * issue 242 */ 243 data16 = VPHY_SPI_INDIRECT_ENABLE; 244 245 ret = ksz_rmw16(dev, REG_VPHY_SPECIAL_CTRL__2, 246 VPHY_SPI_INDIRECT_ENABLE | VPHY_MDIO_INTERNAL_ENABLE, 247 data16); 248 249 print_error: 250 if (ret < 0) 251 dev_err(dev->dev, "failed to preinit the MDIO bus\n"); 252 253 return ret; 254 } 255 256 static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg) 257 { 258 u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE; 259 u16 temp; 260 261 if (is_lan937x_tx_phy(dev, addr)) 262 addr_base = REG_PORT_TX_PHY_CTRL_BASE; 263 264 /* get register address based on the logical port */ 265 temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2))); 266 267 return ksz_write16(dev, REG_VPHY_IND_ADDR__2, temp); 268 } 269 270 static int lan937x_internal_phy_write(struct ksz_device *dev, int addr, int reg, 271 u16 val) 272 { 273 unsigned int value; 274 int ret; 275 276 /* Check for internal phy port */ 277 if (!dev->info->internal_phy[addr]) 278 return -EOPNOTSUPP; 279 280 ret = lan937x_vphy_ind_addr_wr(dev, addr, reg); 281 if (ret < 0) 282 return ret; 283 284 /* Write the data to be written to the VPHY reg */ 285 ret = ksz_write16(dev, REG_VPHY_IND_DATA__2, val); 286 if (ret < 0) 287 return ret; 288 289 /* Write the Write En and Busy bit */ 290 ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, 291 (VPHY_IND_WRITE | VPHY_IND_BUSY)); 292 if (ret < 0) 293 return ret; 294 295 ret = regmap_read_poll_timeout(ksz_regmap_16(dev), REG_VPHY_IND_CTRL__2, 296 value, !(value & VPHY_IND_BUSY), 10, 297 1000); 298 if (ret < 0) { 299 dev_err(dev->dev, "Failed to write phy register\n"); 300 return ret; 301 } 302 303 return 0; 304 } 305 306 static int lan937x_internal_phy_read(struct ksz_device *dev, int addr, int reg, 307 u16 *val) 308 { 309 unsigned int value; 310 int ret; 311 312 /* Check for internal phy port, return 0xffff for non-existent phy */ 313 if (!dev->info->internal_phy[addr]) 314 return 0xffff; 315 316 ret = lan937x_vphy_ind_addr_wr(dev, addr, reg); 317 if (ret < 0) 318 return ret; 319 320 /* Write Read and Busy bit to start the transaction */ 321 ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, VPHY_IND_BUSY); 322 if (ret < 0) 323 return ret; 324 325 ret = regmap_read_poll_timeout(ksz_regmap_16(dev), REG_VPHY_IND_CTRL__2, 326 value, !(value & VPHY_IND_BUSY), 10, 327 1000); 328 if (ret < 0) { 329 dev_err(dev->dev, "Failed to read phy register\n"); 330 return ret; 331 } 332 333 /* Read the VPHY register which has the PHY data */ 334 return ksz_read16(dev, REG_VPHY_IND_DATA__2, val); 335 } 336 337 static int lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data) 338 { 339 return lan937x_internal_phy_read(dev, addr, reg, data); 340 } 341 342 static int lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val) 343 { 344 return lan937x_internal_phy_write(dev, addr, reg, val); 345 } 346 347 static int lan937x_reset_switch(struct ksz_device *dev) 348 { 349 u32 data32; 350 int ret; 351 352 /* reset switch */ 353 ret = lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 354 if (ret < 0) 355 return ret; 356 357 /* Enable Auto Aging */ 358 ret = lan937x_cfg(dev, REG_SW_LUE_CTRL_1, SW_LINK_AUTO_AGING, true); 359 if (ret < 0) 360 return ret; 361 362 /* disable interrupts */ 363 ret = ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 364 if (ret < 0) 365 return ret; 366 367 ret = ksz_write32(dev, REG_SW_INT_STATUS__4, POR_READY_INT); 368 if (ret < 0) 369 return ret; 370 371 ret = ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0xFF); 372 if (ret < 0) 373 return ret; 374 375 return ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 376 } 377 378 static void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port) 379 { 380 const u32 *masks = dev->info->masks; 381 const u16 *regs = dev->info->regs; 382 struct dsa_switch *ds = dev->ds; 383 u8 member; 384 385 /* enable tag tail for host port */ 386 if (cpu_port) 387 lan937x_port_cfg(dev, port, REG_PORT_CTRL_0, 388 PORT_TAIL_TAG_ENABLE, true); 389 390 /* Enable the Port Queue split */ 391 ksz9477_port_queue_split(dev, port); 392 393 /* set back pressure for half duplex */ 394 lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, 395 true); 396 397 /* enable 802.1p priority */ 398 lan937x_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 399 400 if (!dev->info->internal_phy[port]) 401 lan937x_port_cfg(dev, port, regs[P_XMII_CTRL_0], 402 masks[P_MII_TX_FLOW_CTRL] | 403 masks[P_MII_RX_FLOW_CTRL], 404 true); 405 406 if (cpu_port) 407 member = dsa_user_ports(ds); 408 else 409 member = BIT(dsa_upstream_port(ds, port)); 410 411 dev->dev_ops->cfg_port_member(dev, port, member); 412 } 413 414 static void lan937x_config_cpu_port(struct dsa_switch *ds) 415 { 416 struct ksz_device *dev = ds->priv; 417 struct dsa_port *dp; 418 419 dsa_switch_for_each_cpu_port(dp, ds) { 420 if (dev->info->cpu_ports & (1 << dp->index)) { 421 dev->cpu_port = dp->index; 422 423 /* enable cpu port */ 424 lan937x_port_setup(dev, dp->index, true); 425 } 426 } 427 428 dsa_switch_for_each_user_port(dp, ds) { 429 ksz_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED); 430 } 431 } 432 433 static int lan937x_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 434 { 435 struct ksz_device *dev = ds->priv; 436 int ret; 437 438 new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN; 439 440 if (dsa_is_cpu_port(ds, port)) 441 new_mtu += LAN937X_TAG_LEN; 442 443 if (new_mtu >= FR_MIN_SIZE) 444 ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, 445 PORT_JUMBO_PACKET, true); 446 else 447 ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, 448 PORT_JUMBO_PACKET, false); 449 if (ret < 0) { 450 dev_err(ds->dev, "failed to enable jumbo\n"); 451 return ret; 452 } 453 454 /* Write the frame size in PORT_MAX_FR_SIZE register */ 455 ret = ksz_pwrite16(dev, port, PORT_MAX_FR_SIZE, new_mtu); 456 if (ret) { 457 dev_err(ds->dev, "failed to update mtu for port %d\n", port); 458 return ret; 459 } 460 461 return 0; 462 } 463 464 static int lan937x_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 465 { 466 struct ksz_device *dev = ds->priv; 467 u8 data, mult, value8; 468 bool in_msec = false; 469 u32 max_val, value; 470 u32 secs = msecs; 471 int ret; 472 473 #define MAX_TIMER_VAL ((1 << 20) - 1) 474 475 /* The aging timer comprises a 3-bit multiplier and a 20-bit second 476 * value. Either of them cannot be zero. The maximum timer is then 477 * 7 * 1048575 = 7340025 seconds. As this value is too large for 478 * practical use it can be interpreted as microseconds, making the 479 * maximum timer 7340 seconds with finer control. This allows for 480 * maximum 122 minutes compared to 29 minutes in KSZ9477 switch. 481 */ 482 if (msecs % 1000) 483 in_msec = true; 484 else 485 secs /= 1000; 486 if (!secs) 487 secs = 1; 488 489 /* Return error if too large. */ 490 else if (secs > 7 * MAX_TIMER_VAL) 491 return -EINVAL; 492 493 /* Configure how to interpret the number value. */ 494 ret = ksz_rmw8(dev, REG_SW_LUE_CTRL_2, SW_AGE_CNT_IN_MICROSEC, 495 in_msec ? SW_AGE_CNT_IN_MICROSEC : 0); 496 if (ret < 0) 497 return ret; 498 499 ret = ksz_read8(dev, REG_SW_LUE_CTRL_0, &value8); 500 if (ret < 0) 501 return ret; 502 503 /* Check whether there is need to update the multiplier. */ 504 mult = FIELD_GET(SW_AGE_CNT_M, value8); 505 max_val = MAX_TIMER_VAL; 506 if (mult > 0) { 507 /* Try to use the same multiplier already in the register as 508 * the hardware default uses multiplier 4 and 75 seconds for 509 * 300 seconds. 510 */ 511 max_val = DIV_ROUND_UP(secs, mult); 512 if (max_val > MAX_TIMER_VAL || max_val * mult != secs) 513 max_val = MAX_TIMER_VAL; 514 } 515 516 data = DIV_ROUND_UP(secs, max_val); 517 if (mult != data) { 518 value8 &= ~SW_AGE_CNT_M; 519 value8 |= FIELD_PREP(SW_AGE_CNT_M, data); 520 ret = ksz_write8(dev, REG_SW_LUE_CTRL_0, value8); 521 if (ret < 0) 522 return ret; 523 } 524 525 secs = DIV_ROUND_UP(secs, data); 526 527 value = FIELD_GET(SW_AGE_PERIOD_7_0_M, secs); 528 529 ret = ksz_write8(dev, REG_SW_AGE_PERIOD__1, value); 530 if (ret < 0) 531 return ret; 532 533 value = FIELD_GET(SW_AGE_PERIOD_19_8_M, secs); 534 535 return ksz_write16(dev, REG_SW_AGE_PERIOD__2, value); 536 } 537 538 static void lan937x_set_tune_adj(struct ksz_device *dev, int port, 539 u16 reg, u8 val) 540 { 541 u16 data16; 542 543 ksz_pread16(dev, port, reg, &data16); 544 545 /* Update tune Adjust */ 546 data16 &= ~PORT_TUNE_ADJ; 547 data16 |= FIELD_PREP(PORT_TUNE_ADJ, val); 548 ksz_pwrite16(dev, port, reg, data16); 549 550 /* write DLL reset to take effect */ 551 data16 |= PORT_DLL_RESET; 552 ksz_pwrite16(dev, port, reg, data16); 553 } 554 555 static void lan937x_set_rgmii_tx_delay(struct ksz_device *dev, int port) 556 { 557 u8 val; 558 559 /* Apply different codes based on the ports as per characterization 560 * results 561 */ 562 val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_TX_DELAY_2NS : 563 RGMII_2_TX_DELAY_2NS; 564 565 lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_5, val); 566 } 567 568 static void lan937x_set_rgmii_rx_delay(struct ksz_device *dev, int port) 569 { 570 u8 val; 571 572 val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_RX_DELAY_2NS : 573 RGMII_2_RX_DELAY_2NS; 574 575 lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_4, val); 576 } 577 578 static void lan937x_phylink_get_caps(struct dsa_switch *ds, int port, 579 struct phylink_config *config) 580 { 581 struct ksz_device *dev = ds->priv; 582 583 config->mac_capabilities = MAC_100FD; 584 585 if (dev->info->supports_rgmii[port]) { 586 /* MII/RMII/RGMII ports */ 587 config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 588 MAC_100HD | MAC_10 | MAC_1000FD; 589 } else if (is_lan937x_tx_phy(dev, port)) { 590 config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 591 MAC_100HD | MAC_10; 592 } 593 594 ksz_phylink_get_caps(ds, port, config); 595 } 596 597 static void lan937x_setup_rgmii_delay(struct ksz_device *dev, int port) 598 { 599 struct ksz_port *p = &dev->ports[port]; 600 601 if (p->rgmii_tx_val) { 602 lan937x_set_rgmii_tx_delay(dev, port); 603 dev_info(dev->dev, "Applied rgmii tx delay for the port %d\n", 604 port); 605 } 606 607 if (p->rgmii_rx_val) { 608 lan937x_set_rgmii_rx_delay(dev, port); 609 dev_info(dev->dev, "Applied rgmii rx delay for the port %d\n", 610 port); 611 } 612 } 613 614 static int lan937x_tc_cbs_set_cinc(struct ksz_device *dev, int port, u32 val) 615 { 616 return ksz_pwrite32(dev, port, REG_PORT_MTI_CREDIT_INCREMENT, val); 617 } 618 619 static int lan937x_switch_init(struct ksz_device *dev) 620 { 621 dev->port_mask = (1 << dev->info->port_cnt) - 1; 622 623 return 0; 624 } 625 626 static int lan937x_setup(struct dsa_switch *ds) 627 { 628 struct ksz_device *dev = ds->priv; 629 int ret; 630 631 /* The VLAN aware is a global setting. Mixed vlan 632 * filterings are not supported. 633 */ 634 ds->vlan_filtering_is_global = true; 635 636 /* Enable aggressive back off for half duplex & UNH mode */ 637 ret = lan937x_cfg(dev, REG_SW_MAC_CTRL_0, (SW_PAUSE_UNH_MODE | 638 SW_NEW_BACKOFF | 639 SW_AGGR_BACKOFF), true); 640 if (ret < 0) 641 return ret; 642 643 /* If NO_EXC_COLLISION_DROP bit is set, the switch will not drop 644 * packets when 16 or more collisions occur 645 */ 646 ret = lan937x_cfg(dev, REG_SW_MAC_CTRL_1, NO_EXC_COLLISION_DROP, true); 647 if (ret < 0) 648 return ret; 649 650 /* enable global MIB counter freeze function */ 651 ret = lan937x_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 652 if (ret < 0) 653 return ret; 654 655 /* disable CLK125 & CLK25, 1: disable, 0: enable */ 656 ret = lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, 657 (SW_CLK125_ENB | SW_CLK25_ENB), true); 658 if (ret < 0) 659 return ret; 660 661 /* Disable global VPHY support. Related to CPU interface only? */ 662 return ksz_rmw32(dev, REG_SW_CFG_STRAP_OVR, SW_VPHY_DISABLE, 663 SW_VPHY_DISABLE); 664 } 665 666 static void lan937x_teardown(struct dsa_switch *ds) 667 { 668 669 } 670 671 static void lan937x_switch_exit(struct ksz_device *dev) 672 { 673 lan937x_reset_switch(dev); 674 } 675 676 static enum dsa_tag_protocol lan937x_get_tag_protocol(struct dsa_switch *ds, 677 int port, 678 enum dsa_tag_protocol mp) 679 { 680 return DSA_TAG_PROTO_LAN937X; 681 } 682 683 static int lan937x_connect_tag_protocol(struct dsa_switch *ds, 684 enum dsa_tag_protocol proto) 685 { 686 struct ksz_tagger_data *tagger_data; 687 688 if (proto != DSA_TAG_PROTO_LAN937X) 689 return -EPROTONOSUPPORT; 690 691 tagger_data = ksz_tagger_data(ds); 692 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 693 694 return 0; 695 } 696 697 const struct phylink_mac_ops lan937x_phylink_mac_ops = { 698 .mac_config = ksz_phylink_mac_config, 699 .mac_link_down = ksz_phylink_mac_link_down, 700 .mac_link_up = ksz9477_phylink_mac_link_up, 701 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 702 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 703 }; 704 705 const struct ksz_dev_ops lan937x_dev_ops = { 706 .setup = lan937x_setup, 707 .teardown = lan937x_teardown, 708 .get_port_addr = ksz9477_get_port_addr, 709 .cfg_port_member = ksz9477_cfg_port_member, 710 .port_setup = lan937x_port_setup, 711 .mdio_bus_preinit = lan937x_mdio_bus_preinit, 712 .create_phy_addr_map = lan937x_create_phy_addr_map, 713 .r_phy = lan937x_r_phy, 714 .w_phy = lan937x_w_phy, 715 .r_mib_cnt = ksz9477_r_mib_cnt, 716 .r_mib_pkt = ksz9477_r_mib_pkt, 717 .r_mib_stat64 = ksz_r_mib_stats64, 718 .freeze_mib = ksz9477_freeze_mib, 719 .port_init_cnt = ksz9477_port_init_cnt, 720 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 721 .config_cpu_port = lan937x_config_cpu_port, 722 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 723 .enable_stp_addr = ksz9477_enable_stp_addr, 724 .reset = lan937x_reset_switch, 725 .init = lan937x_switch_init, 726 .exit = lan937x_switch_exit, 727 }; 728 729 const struct dsa_switch_ops lan937x_switch_ops = { 730 .get_tag_protocol = lan937x_get_tag_protocol, 731 .connect_tag_protocol = lan937x_connect_tag_protocol, 732 .get_phy_flags = ksz_get_phy_flags, 733 .setup = ksz_setup, 734 .teardown = ksz_teardown, 735 .phy_read = ksz_phy_read16, 736 .phy_write = ksz_phy_write16, 737 .phylink_get_caps = lan937x_phylink_get_caps, 738 .port_setup = ksz_port_setup, 739 .set_ageing_time = lan937x_set_ageing_time, 740 .get_strings = ksz_get_strings, 741 .get_ethtool_stats = ksz_get_ethtool_stats, 742 .get_sset_count = ksz_sset_count, 743 .port_bridge_join = ksz_port_bridge_join, 744 .port_bridge_leave = ksz_port_bridge_leave, 745 .port_hsr_join = ksz_hsr_join, 746 .port_hsr_leave = ksz_hsr_leave, 747 .port_set_mac_address = ksz_port_set_mac_address, 748 .port_stp_state_set = ksz_port_stp_state_set, 749 .port_teardown = ksz_port_teardown, 750 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 751 .port_bridge_flags = ksz_port_bridge_flags, 752 .port_fast_age = ksz9477_flush_dyn_mac_table, 753 .port_vlan_filtering = ksz9477_port_vlan_filtering, 754 .port_vlan_add = ksz9477_port_vlan_add, 755 .port_vlan_del = ksz9477_port_vlan_del, 756 .port_fdb_dump = ksz9477_fdb_dump, 757 .port_fdb_add = ksz9477_fdb_add, 758 .port_fdb_del = ksz9477_fdb_del, 759 .port_mdb_add = ksz9477_mdb_add, 760 .port_mdb_del = ksz9477_mdb_del, 761 .port_mirror_add = ksz9477_port_mirror_add, 762 .port_mirror_del = ksz9477_port_mirror_del, 763 .get_stats64 = ksz_get_stats64, 764 .get_pause_stats = ksz_get_pause_stats, 765 .port_change_mtu = lan937x_change_mtu, 766 .port_max_mtu = ksz_max_mtu, 767 .get_wol = ksz_get_wol, 768 .set_wol = ksz_set_wol, 769 .suspend = ksz_suspend, 770 .resume = ksz_resume, 771 .get_ts_info = ksz_get_ts_info, 772 .port_hwtstamp_get = ksz_hwtstamp_get, 773 .port_hwtstamp_set = ksz_hwtstamp_set, 774 .port_txtstamp = ksz_port_txtstamp, 775 .port_rxtstamp = ksz_port_rxtstamp, 776 .cls_flower_add = ksz_cls_flower_add, 777 .cls_flower_del = ksz_cls_flower_del, 778 .port_setup_tc = ksz_setup_tc, 779 .support_eee = ksz_support_eee, 780 .set_mac_eee = ksz_set_mac_eee, 781 .port_get_default_prio = ksz_port_get_default_prio, 782 .port_set_default_prio = ksz_port_set_default_prio, 783 .port_get_dscp_prio = ksz_port_get_dscp_prio, 784 .port_add_dscp_prio = ksz_port_add_dscp_prio, 785 .port_del_dscp_prio = ksz_port_del_dscp_prio, 786 .port_get_apptrust = ksz_port_get_apptrust, 787 .port_set_apptrust = ksz_port_set_apptrust, 788 }; 789 790 MODULE_AUTHOR("Arun Ramadoss <arun.ramadoss@microchip.com>"); 791 MODULE_DESCRIPTION("Microchip LAN937x Series Switch DSA Driver"); 792 MODULE_LICENSE("GPL"); 793