1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 18 #include "ksz_ptp.h" 19 20 #define KSZ_MAX_NUM_PORTS 8 21 22 struct ksz_device; 23 struct ksz_port; 24 25 enum ksz_regmap_width { 26 KSZ_REGMAP_8, 27 KSZ_REGMAP_16, 28 KSZ_REGMAP_32, 29 __KSZ_NUM_REGMAPS, 30 }; 31 32 struct vlan_table { 33 u32 table[3]; 34 }; 35 36 struct ksz_port_mib { 37 struct mutex cnt_mutex; /* structure access */ 38 u8 cnt_ptr; 39 u64 *counters; 40 struct rtnl_link_stats64 stats64; 41 struct ethtool_pause_stats pause_stats; 42 struct spinlock stats64_lock; 43 }; 44 45 struct ksz_mib_names { 46 int index; 47 char string[ETH_GSTRING_LEN]; 48 }; 49 50 struct ksz_chip_data { 51 u32 chip_id; 52 const char *dev_name; 53 int num_vlans; 54 int num_alus; 55 int num_statics; 56 int cpu_ports; 57 int port_cnt; 58 u8 port_nirqs; 59 u8 num_tx_queues; 60 bool tc_cbs_supported; 61 bool tc_ets_supported; 62 const struct ksz_dev_ops *ops; 63 bool ksz87xx_eee_link_erratum; 64 const struct ksz_mib_names *mib_names; 65 int mib_cnt; 66 u8 reg_mib_cnt; 67 const u16 *regs; 68 const u32 *masks; 69 const u8 *shifts; 70 const u8 *xmii_ctrl0; 71 const u8 *xmii_ctrl1; 72 int stp_ctrl_reg; 73 int broadcast_ctrl_reg; 74 int multicast_ctrl_reg; 75 int start_ctrl_reg; 76 bool supports_mii[KSZ_MAX_NUM_PORTS]; 77 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 78 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 79 bool internal_phy[KSZ_MAX_NUM_PORTS]; 80 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 81 const struct regmap_access_table *wr_table; 82 const struct regmap_access_table *rd_table; 83 }; 84 85 struct ksz_irq { 86 u16 masked; 87 u16 reg_mask; 88 u16 reg_status; 89 struct irq_domain *domain; 90 int nirqs; 91 int irq_num; 92 char name[16]; 93 struct ksz_device *dev; 94 }; 95 96 struct ksz_ptp_irq { 97 struct ksz_port *port; 98 u16 ts_reg; 99 bool ts_en; 100 char name[16]; 101 int num; 102 }; 103 104 struct ksz_port { 105 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 106 bool learning; 107 int stp_state; 108 struct phy_device phydev; 109 110 u32 fiber:1; /* port is fiber */ 111 u32 force:1; 112 u32 read:1; /* read MIB counters in background */ 113 u32 freeze:1; /* MIB counter freeze is enabled */ 114 115 struct ksz_port_mib mib; 116 phy_interface_t interface; 117 u32 rgmii_tx_val; 118 u32 rgmii_rx_val; 119 struct ksz_device *ksz_dev; 120 void *acl_priv; 121 struct ksz_irq pirq; 122 u8 num; 123 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 124 struct hwtstamp_config tstamp_config; 125 bool hwts_tx_en; 126 bool hwts_rx_en; 127 struct ksz_irq ptpirq; 128 struct ksz_ptp_irq ptpmsg_irq[3]; 129 ktime_t tstamp_msg; 130 struct completion tstamp_msg_comp; 131 #endif 132 }; 133 134 struct ksz_device { 135 struct dsa_switch *ds; 136 struct ksz_platform_data *pdata; 137 const struct ksz_chip_data *info; 138 139 struct mutex dev_mutex; /* device access */ 140 struct mutex regmap_mutex; /* regmap access */ 141 struct mutex alu_mutex; /* ALU access */ 142 struct mutex vlan_mutex; /* vlan access */ 143 const struct ksz_dev_ops *dev_ops; 144 145 struct device *dev; 146 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 147 148 void *priv; 149 int irq; 150 151 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 152 153 /* chip specific data */ 154 u32 chip_id; 155 u8 chip_rev; 156 int cpu_port; /* port connected to CPU */ 157 int phy_port_cnt; 158 phy_interface_t compat_interface; 159 bool synclko_125; 160 bool synclko_disable; 161 162 struct vlan_table *vlan_cache; 163 164 struct ksz_port *ports; 165 struct delayed_work mib_read; 166 unsigned long mib_read_interval; 167 u16 mirror_rx; 168 u16 mirror_tx; 169 u16 port_mask; 170 struct mutex lock_irq; /* IRQ Access */ 171 struct ksz_irq girq; 172 struct ksz_ptp_data ptp_data; 173 }; 174 175 /* List of supported models */ 176 enum ksz_model { 177 KSZ8563, 178 KSZ8795, 179 KSZ8794, 180 KSZ8765, 181 KSZ8830, 182 KSZ9477, 183 KSZ9896, 184 KSZ9897, 185 KSZ9893, 186 KSZ9563, 187 KSZ9567, 188 LAN9370, 189 LAN9371, 190 LAN9372, 191 LAN9373, 192 LAN9374, 193 }; 194 195 enum ksz_chip_id { 196 KSZ8563_CHIP_ID = 0x8563, 197 KSZ8795_CHIP_ID = 0x8795, 198 KSZ8794_CHIP_ID = 0x8794, 199 KSZ8765_CHIP_ID = 0x8765, 200 KSZ8830_CHIP_ID = 0x8830, 201 KSZ9477_CHIP_ID = 0x00947700, 202 KSZ9896_CHIP_ID = 0x00989600, 203 KSZ9897_CHIP_ID = 0x00989700, 204 KSZ9893_CHIP_ID = 0x00989300, 205 KSZ9563_CHIP_ID = 0x00956300, 206 KSZ9567_CHIP_ID = 0x00956700, 207 LAN9370_CHIP_ID = 0x00937000, 208 LAN9371_CHIP_ID = 0x00937100, 209 LAN9372_CHIP_ID = 0x00937200, 210 LAN9373_CHIP_ID = 0x00937300, 211 LAN9374_CHIP_ID = 0x00937400, 212 }; 213 214 enum ksz_regs { 215 REG_IND_CTRL_0, 216 REG_IND_DATA_8, 217 REG_IND_DATA_CHECK, 218 REG_IND_DATA_HI, 219 REG_IND_DATA_LO, 220 REG_IND_MIB_CHECK, 221 REG_IND_BYTE, 222 P_FORCE_CTRL, 223 P_LINK_STATUS, 224 P_LOCAL_CTRL, 225 P_NEG_RESTART_CTRL, 226 P_REMOTE_STATUS, 227 P_SPEED_STATUS, 228 S_TAIL_TAG_CTRL, 229 P_STP_CTRL, 230 S_START_CTRL, 231 S_BROADCAST_CTRL, 232 S_MULTICAST_CTRL, 233 P_XMII_CTRL_0, 234 P_XMII_CTRL_1, 235 }; 236 237 enum ksz_masks { 238 PORT_802_1P_REMAPPING, 239 SW_TAIL_TAG_ENABLE, 240 MIB_COUNTER_OVERFLOW, 241 MIB_COUNTER_VALID, 242 VLAN_TABLE_FID, 243 VLAN_TABLE_MEMBERSHIP, 244 VLAN_TABLE_VALID, 245 STATIC_MAC_TABLE_VALID, 246 STATIC_MAC_TABLE_USE_FID, 247 STATIC_MAC_TABLE_FID, 248 STATIC_MAC_TABLE_OVERRIDE, 249 STATIC_MAC_TABLE_FWD_PORTS, 250 DYNAMIC_MAC_TABLE_ENTRIES_H, 251 DYNAMIC_MAC_TABLE_MAC_EMPTY, 252 DYNAMIC_MAC_TABLE_NOT_READY, 253 DYNAMIC_MAC_TABLE_ENTRIES, 254 DYNAMIC_MAC_TABLE_FID, 255 DYNAMIC_MAC_TABLE_SRC_PORT, 256 DYNAMIC_MAC_TABLE_TIMESTAMP, 257 ALU_STAT_WRITE, 258 ALU_STAT_READ, 259 P_MII_TX_FLOW_CTRL, 260 P_MII_RX_FLOW_CTRL, 261 }; 262 263 enum ksz_shifts { 264 VLAN_TABLE_MEMBERSHIP_S, 265 VLAN_TABLE, 266 STATIC_MAC_FWD_PORTS, 267 STATIC_MAC_FID, 268 DYNAMIC_MAC_ENTRIES_H, 269 DYNAMIC_MAC_ENTRIES, 270 DYNAMIC_MAC_FID, 271 DYNAMIC_MAC_TIMESTAMP, 272 DYNAMIC_MAC_SRC_PORT, 273 ALU_STAT_INDEX, 274 }; 275 276 enum ksz_xmii_ctrl0 { 277 P_MII_100MBIT, 278 P_MII_10MBIT, 279 P_MII_FULL_DUPLEX, 280 P_MII_HALF_DUPLEX, 281 }; 282 283 enum ksz_xmii_ctrl1 { 284 P_RGMII_SEL, 285 P_RMII_SEL, 286 P_GMII_SEL, 287 P_MII_SEL, 288 P_GMII_1GBIT, 289 P_GMII_NOT_1GBIT, 290 }; 291 292 struct alu_struct { 293 /* entry 1 */ 294 u8 is_static:1; 295 u8 is_src_filter:1; 296 u8 is_dst_filter:1; 297 u8 prio_age:3; 298 u32 _reserv_0_1:23; 299 u8 mstp:3; 300 /* entry 2 */ 301 u8 is_override:1; 302 u8 is_use_fid:1; 303 u32 _reserv_1_1:23; 304 u8 port_forward:7; 305 /* entry 3 & 4*/ 306 u32 _reserv_2_1:9; 307 u8 fid:7; 308 u8 mac[ETH_ALEN]; 309 }; 310 311 struct ksz_dev_ops { 312 int (*setup)(struct dsa_switch *ds); 313 void (*teardown)(struct dsa_switch *ds); 314 u32 (*get_port_addr)(int port, int offset); 315 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 316 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 317 void (*port_cleanup)(struct ksz_device *dev, int port); 318 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 319 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 320 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 321 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 322 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 323 u64 *cnt); 324 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 325 u64 *dropped, u64 *cnt); 326 void (*r_mib_stat64)(struct ksz_device *dev, int port); 327 int (*vlan_filtering)(struct ksz_device *dev, int port, 328 bool flag, struct netlink_ext_ack *extack); 329 int (*vlan_add)(struct ksz_device *dev, int port, 330 const struct switchdev_obj_port_vlan *vlan, 331 struct netlink_ext_ack *extack); 332 int (*vlan_del)(struct ksz_device *dev, int port, 333 const struct switchdev_obj_port_vlan *vlan); 334 int (*mirror_add)(struct ksz_device *dev, int port, 335 struct dsa_mall_mirror_tc_entry *mirror, 336 bool ingress, struct netlink_ext_ack *extack); 337 void (*mirror_del)(struct ksz_device *dev, int port, 338 struct dsa_mall_mirror_tc_entry *mirror); 339 int (*fdb_add)(struct ksz_device *dev, int port, 340 const unsigned char *addr, u16 vid, struct dsa_db db); 341 int (*fdb_del)(struct ksz_device *dev, int port, 342 const unsigned char *addr, u16 vid, struct dsa_db db); 343 int (*fdb_dump)(struct ksz_device *dev, int port, 344 dsa_fdb_dump_cb_t *cb, void *data); 345 int (*mdb_add)(struct ksz_device *dev, int port, 346 const struct switchdev_obj_port_mdb *mdb, 347 struct dsa_db db); 348 int (*mdb_del)(struct ksz_device *dev, int port, 349 const struct switchdev_obj_port_mdb *mdb, 350 struct dsa_db db); 351 void (*get_caps)(struct ksz_device *dev, int port, 352 struct phylink_config *config); 353 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 354 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 355 void (*port_init_cnt)(struct ksz_device *dev, int port); 356 void (*phylink_mac_config)(struct ksz_device *dev, int port, 357 unsigned int mode, 358 const struct phylink_link_state *state); 359 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 360 unsigned int mode, 361 phy_interface_t interface, 362 struct phy_device *phydev, int speed, 363 int duplex, bool tx_pause, bool rx_pause); 364 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 365 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 366 void (*config_cpu_port)(struct dsa_switch *ds); 367 int (*enable_stp_addr)(struct ksz_device *dev); 368 int (*reset)(struct ksz_device *dev); 369 int (*init)(struct ksz_device *dev); 370 void (*exit)(struct ksz_device *dev); 371 }; 372 373 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 374 int ksz_switch_register(struct ksz_device *dev); 375 void ksz_switch_remove(struct ksz_device *dev); 376 377 void ksz_init_mib_timer(struct ksz_device *dev); 378 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 379 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 380 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 381 bool ksz_get_gbit(struct ksz_device *dev, int port); 382 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 383 extern const struct ksz_chip_data ksz_switch_chips[]; 384 385 /* Common register access functions */ 386 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 387 { 388 return dev->regmap[KSZ_REGMAP_8]; 389 } 390 391 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 392 { 393 return dev->regmap[KSZ_REGMAP_16]; 394 } 395 396 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 397 { 398 return dev->regmap[KSZ_REGMAP_32]; 399 } 400 401 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 402 { 403 unsigned int value; 404 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 405 406 if (ret) 407 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 408 ERR_PTR(ret)); 409 410 *val = value; 411 return ret; 412 } 413 414 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 415 { 416 unsigned int value; 417 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 418 419 if (ret) 420 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 421 ERR_PTR(ret)); 422 423 *val = value; 424 return ret; 425 } 426 427 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 428 { 429 unsigned int value; 430 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 431 432 if (ret) 433 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 434 ERR_PTR(ret)); 435 436 *val = value; 437 return ret; 438 } 439 440 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 441 { 442 u32 value[2]; 443 int ret; 444 445 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 446 if (ret) 447 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 448 ERR_PTR(ret)); 449 else 450 *val = (u64)value[0] << 32 | value[1]; 451 452 return ret; 453 } 454 455 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 456 { 457 int ret; 458 459 ret = regmap_write(ksz_regmap_8(dev), reg, value); 460 if (ret) 461 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 462 ERR_PTR(ret)); 463 464 return ret; 465 } 466 467 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 468 { 469 int ret; 470 471 ret = regmap_write(ksz_regmap_16(dev), reg, value); 472 if (ret) 473 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 474 ERR_PTR(ret)); 475 476 return ret; 477 } 478 479 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 480 { 481 int ret; 482 483 ret = regmap_write(ksz_regmap_32(dev), reg, value); 484 if (ret) 485 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 486 ERR_PTR(ret)); 487 488 return ret; 489 } 490 491 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 492 u16 value) 493 { 494 int ret; 495 496 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 497 if (ret) 498 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 499 ERR_PTR(ret)); 500 501 return ret; 502 } 503 504 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 505 u32 value) 506 { 507 int ret; 508 509 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 510 if (ret) 511 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 512 ERR_PTR(ret)); 513 514 return ret; 515 } 516 517 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 518 { 519 u32 val[2]; 520 521 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 522 value = swab64(value); 523 val[0] = swab32(value & 0xffffffffULL); 524 val[1] = swab32(value >> 32ULL); 525 526 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 527 } 528 529 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 530 { 531 int ret; 532 533 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 534 if (ret) 535 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 536 ERR_PTR(ret)); 537 538 return ret; 539 } 540 541 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 542 u8 *data) 543 { 544 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 545 } 546 547 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 548 u16 *data) 549 { 550 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 551 } 552 553 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 554 u32 *data) 555 { 556 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 557 } 558 559 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 560 u8 data) 561 { 562 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 563 } 564 565 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 566 u16 data) 567 { 568 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 569 data); 570 } 571 572 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 573 u32 data) 574 { 575 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 576 data); 577 } 578 579 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 580 u8 mask, u8 val) 581 { 582 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 583 mask, val); 584 } 585 586 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 587 u32 mask, u32 val) 588 { 589 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 590 mask, val); 591 } 592 593 static inline void ksz_regmap_lock(void *__mtx) 594 { 595 struct mutex *mtx = __mtx; 596 mutex_lock(mtx); 597 } 598 599 static inline void ksz_regmap_unlock(void *__mtx) 600 { 601 struct mutex *mtx = __mtx; 602 mutex_unlock(mtx); 603 } 604 605 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 606 { 607 return dev->chip_id == KSZ8795_CHIP_ID || 608 dev->chip_id == KSZ8794_CHIP_ID || 609 dev->chip_id == KSZ8765_CHIP_ID; 610 } 611 612 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 613 { 614 return dev->chip_id == KSZ8830_CHIP_ID; 615 } 616 617 static inline int is_lan937x(struct ksz_device *dev) 618 { 619 return dev->chip_id == LAN9370_CHIP_ID || 620 dev->chip_id == LAN9371_CHIP_ID || 621 dev->chip_id == LAN9372_CHIP_ID || 622 dev->chip_id == LAN9373_CHIP_ID || 623 dev->chip_id == LAN9374_CHIP_ID; 624 } 625 626 /* STP State Defines */ 627 #define PORT_TX_ENABLE BIT(2) 628 #define PORT_RX_ENABLE BIT(1) 629 #define PORT_LEARN_DISABLE BIT(0) 630 631 /* Switch ID Defines */ 632 #define REG_CHIP_ID0 0x00 633 634 #define SW_FAMILY_ID_M GENMASK(15, 8) 635 #define KSZ87_FAMILY_ID 0x87 636 #define KSZ88_FAMILY_ID 0x88 637 638 #define KSZ8_PORT_STATUS_0 0x08 639 #define KSZ8_PORT_FIBER_MODE BIT(7) 640 641 #define SW_CHIP_ID_M GENMASK(7, 4) 642 #define KSZ87_CHIP_ID_94 0x6 643 #define KSZ87_CHIP_ID_95 0x9 644 #define KSZ88_CHIP_ID_63 0x3 645 646 #define SW_REV_ID_M GENMASK(7, 4) 647 648 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 649 #define REG_CHIP_ID4 0x0f 650 #define SKU_ID_KSZ8563 0x3c 651 #define SKU_ID_KSZ9563 0x1c 652 653 /* Driver set switch broadcast storm protection at 10% rate. */ 654 #define BROADCAST_STORM_PROT_RATE 10 655 656 /* 148,800 frames * 67 ms / 100 */ 657 #define BROADCAST_STORM_VALUE 9969 658 659 #define BROADCAST_STORM_RATE_HI 0x07 660 #define BROADCAST_STORM_RATE_LO 0xFF 661 #define BROADCAST_STORM_RATE 0x07FF 662 663 #define MULTICAST_STORM_DISABLE BIT(6) 664 665 #define SW_START 0x01 666 667 /* xMII configuration */ 668 #define P_MII_DUPLEX_M BIT(6) 669 #define P_MII_100MBIT_M BIT(4) 670 671 #define P_GMII_1GBIT_M BIT(6) 672 #define P_RGMII_ID_IG_ENABLE BIT(4) 673 #define P_RGMII_ID_EG_ENABLE BIT(3) 674 #define P_MII_MAC_MODE BIT(2) 675 #define P_MII_SEL_M 0x3 676 677 /* Interrupt */ 678 #define REG_SW_PORT_INT_STATUS__1 0x001B 679 #define REG_SW_PORT_INT_MASK__1 0x001F 680 681 #define REG_PORT_INT_STATUS 0x001B 682 #define REG_PORT_INT_MASK 0x001F 683 684 #define PORT_SRC_PHY_INT 1 685 #define PORT_SRC_PTP_INT 2 686 687 #define KSZ8795_HUGE_PACKET_SIZE 2000 688 #define KSZ8863_HUGE_PACKET_SIZE 1916 689 #define KSZ8863_NORMAL_PACKET_SIZE 1536 690 #define KSZ8_LEGAL_PACKET_SIZE 1518 691 #define KSZ9477_MAX_FRAME_SIZE 9000 692 693 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 694 /* Drive Strength of I/O Pad 695 * 0: 8mA, 1: 16mA 696 */ 697 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 698 699 #define KSZ8795_REG_SW_CTRL_20 0xa3 700 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 701 #define SW_DRIVE_STRENGTH_M 0x7 702 #define SW_DRIVE_STRENGTH_2MA 0 703 #define SW_DRIVE_STRENGTH_4MA 1 704 #define SW_DRIVE_STRENGTH_8MA 2 705 #define SW_DRIVE_STRENGTH_12MA 3 706 #define SW_DRIVE_STRENGTH_16MA 4 707 #define SW_DRIVE_STRENGTH_20MA 5 708 #define SW_DRIVE_STRENGTH_24MA 6 709 #define SW_DRIVE_STRENGTH_28MA 7 710 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 711 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 712 713 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 714 #define KSZ9477_OUT_RATE_NO_LIMIT 0 715 716 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 717 718 #define KSZ9477_PORT_TC_MAP_S 4 719 #define KSZ9477_MAX_TC_PRIO 7 720 721 /* CBS related registers */ 722 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 723 724 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 725 726 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 727 #define MTI_SCHEDULE_STRICT_PRIO 0 728 #define MTI_SCHEDULE_WRR 2 729 #define MTI_SHAPING_M GENMASK(5, 4) 730 #define MTI_SHAPING_OFF 0 731 #define MTI_SHAPING_SRP 1 732 #define MTI_SHAPING_TIME_AWARE 2 733 734 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 735 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 736 737 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 738 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 739 740 /* Regmap tables generation */ 741 #define KSZ_SPI_OP_RD 3 742 #define KSZ_SPI_OP_WR 2 743 744 #define swabnot_used(x) 0 745 746 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 747 swab##swp((opcode) << ((regbits) + (regpad))) 748 749 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 750 { \ 751 .name = #width, \ 752 .val_bits = (width), \ 753 .reg_stride = 1, \ 754 .reg_bits = (regbits) + (regalign), \ 755 .pad_bits = (regpad), \ 756 .max_register = BIT(regbits) - 1, \ 757 .cache_type = REGCACHE_NONE, \ 758 .read_flag_mask = \ 759 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 760 regbits, regpad), \ 761 .write_flag_mask = \ 762 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 763 regbits, regpad), \ 764 .lock = ksz_regmap_lock, \ 765 .unlock = ksz_regmap_unlock, \ 766 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 767 .val_format_endian = REGMAP_ENDIAN_BIG \ 768 } 769 770 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 771 static const struct regmap_config ksz##_regmap_config[] = { \ 772 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 773 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 774 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 775 } 776 777 #endif 778