1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 18 #include "ksz_ptp.h" 19 20 #define KSZ_MAX_NUM_PORTS 8 21 22 struct ksz_device; 23 struct ksz_port; 24 25 enum ksz_regmap_width { 26 KSZ_REGMAP_8, 27 KSZ_REGMAP_16, 28 KSZ_REGMAP_32, 29 __KSZ_NUM_REGMAPS, 30 }; 31 32 struct vlan_table { 33 u32 table[3]; 34 }; 35 36 struct ksz_port_mib { 37 struct mutex cnt_mutex; /* structure access */ 38 u8 cnt_ptr; 39 u64 *counters; 40 struct rtnl_link_stats64 stats64; 41 struct ethtool_pause_stats pause_stats; 42 struct spinlock stats64_lock; 43 }; 44 45 struct ksz_mib_names { 46 int index; 47 char string[ETH_GSTRING_LEN]; 48 }; 49 50 struct ksz_chip_data { 51 u32 chip_id; 52 const char *dev_name; 53 int num_vlans; 54 int num_alus; 55 int num_statics; 56 int cpu_ports; 57 int port_cnt; 58 u8 port_nirqs; 59 u8 num_tx_queues; 60 bool tc_cbs_supported; 61 bool tc_ets_supported; 62 const struct ksz_dev_ops *ops; 63 bool ksz87xx_eee_link_erratum; 64 const struct ksz_mib_names *mib_names; 65 int mib_cnt; 66 u8 reg_mib_cnt; 67 const u16 *regs; 68 const u32 *masks; 69 const u8 *shifts; 70 const u8 *xmii_ctrl0; 71 const u8 *xmii_ctrl1; 72 int stp_ctrl_reg; 73 int broadcast_ctrl_reg; 74 int multicast_ctrl_reg; 75 int start_ctrl_reg; 76 bool supports_mii[KSZ_MAX_NUM_PORTS]; 77 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 78 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 79 bool internal_phy[KSZ_MAX_NUM_PORTS]; 80 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 81 const struct regmap_access_table *wr_table; 82 const struct regmap_access_table *rd_table; 83 }; 84 85 struct ksz_irq { 86 u16 masked; 87 u16 reg_mask; 88 u16 reg_status; 89 struct irq_domain *domain; 90 int nirqs; 91 int irq_num; 92 char name[16]; 93 struct ksz_device *dev; 94 }; 95 96 struct ksz_ptp_irq { 97 struct ksz_port *port; 98 u16 ts_reg; 99 bool ts_en; 100 char name[16]; 101 int num; 102 }; 103 104 struct ksz_switch_macaddr { 105 unsigned char addr[ETH_ALEN]; 106 refcount_t refcount; 107 }; 108 109 struct ksz_port { 110 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 111 bool learning; 112 int stp_state; 113 struct phy_device phydev; 114 115 u32 fiber:1; /* port is fiber */ 116 u32 force:1; 117 u32 read:1; /* read MIB counters in background */ 118 u32 freeze:1; /* MIB counter freeze is enabled */ 119 120 struct ksz_port_mib mib; 121 phy_interface_t interface; 122 u32 rgmii_tx_val; 123 u32 rgmii_rx_val; 124 struct ksz_device *ksz_dev; 125 void *acl_priv; 126 struct ksz_irq pirq; 127 u8 num; 128 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 129 struct hwtstamp_config tstamp_config; 130 bool hwts_tx_en; 131 bool hwts_rx_en; 132 struct ksz_irq ptpirq; 133 struct ksz_ptp_irq ptpmsg_irq[3]; 134 ktime_t tstamp_msg; 135 struct completion tstamp_msg_comp; 136 #endif 137 }; 138 139 struct ksz_device { 140 struct dsa_switch *ds; 141 struct ksz_platform_data *pdata; 142 const struct ksz_chip_data *info; 143 144 struct mutex dev_mutex; /* device access */ 145 struct mutex regmap_mutex; /* regmap access */ 146 struct mutex alu_mutex; /* ALU access */ 147 struct mutex vlan_mutex; /* vlan access */ 148 const struct ksz_dev_ops *dev_ops; 149 150 struct device *dev; 151 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 152 153 void *priv; 154 int irq; 155 156 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 157 158 /* chip specific data */ 159 u32 chip_id; 160 u8 chip_rev; 161 int cpu_port; /* port connected to CPU */ 162 int phy_port_cnt; 163 phy_interface_t compat_interface; 164 bool synclko_125; 165 bool synclko_disable; 166 bool wakeup_source; 167 168 struct vlan_table *vlan_cache; 169 170 struct ksz_port *ports; 171 struct delayed_work mib_read; 172 unsigned long mib_read_interval; 173 u16 mirror_rx; 174 u16 mirror_tx; 175 u16 port_mask; 176 struct mutex lock_irq; /* IRQ Access */ 177 struct ksz_irq girq; 178 struct ksz_ptp_data ptp_data; 179 180 struct ksz_switch_macaddr *switch_macaddr; 181 struct net_device *hsr_dev; /* HSR */ 182 u8 hsr_ports; 183 }; 184 185 /* List of supported models */ 186 enum ksz_model { 187 KSZ8563, 188 KSZ8795, 189 KSZ8794, 190 KSZ8765, 191 KSZ8830, 192 KSZ9477, 193 KSZ9896, 194 KSZ9897, 195 KSZ9893, 196 KSZ9563, 197 KSZ9567, 198 LAN9370, 199 LAN9371, 200 LAN9372, 201 LAN9373, 202 LAN9374, 203 }; 204 205 enum ksz_chip_id { 206 KSZ8563_CHIP_ID = 0x8563, 207 KSZ8795_CHIP_ID = 0x8795, 208 KSZ8794_CHIP_ID = 0x8794, 209 KSZ8765_CHIP_ID = 0x8765, 210 KSZ8830_CHIP_ID = 0x8830, 211 KSZ9477_CHIP_ID = 0x00947700, 212 KSZ9896_CHIP_ID = 0x00989600, 213 KSZ9897_CHIP_ID = 0x00989700, 214 KSZ9893_CHIP_ID = 0x00989300, 215 KSZ9563_CHIP_ID = 0x00956300, 216 KSZ9567_CHIP_ID = 0x00956700, 217 LAN9370_CHIP_ID = 0x00937000, 218 LAN9371_CHIP_ID = 0x00937100, 219 LAN9372_CHIP_ID = 0x00937200, 220 LAN9373_CHIP_ID = 0x00937300, 221 LAN9374_CHIP_ID = 0x00937400, 222 }; 223 224 enum ksz_regs { 225 REG_SW_MAC_ADDR, 226 REG_IND_CTRL_0, 227 REG_IND_DATA_8, 228 REG_IND_DATA_CHECK, 229 REG_IND_DATA_HI, 230 REG_IND_DATA_LO, 231 REG_IND_MIB_CHECK, 232 REG_IND_BYTE, 233 P_FORCE_CTRL, 234 P_LINK_STATUS, 235 P_LOCAL_CTRL, 236 P_NEG_RESTART_CTRL, 237 P_REMOTE_STATUS, 238 P_SPEED_STATUS, 239 S_TAIL_TAG_CTRL, 240 P_STP_CTRL, 241 S_START_CTRL, 242 S_BROADCAST_CTRL, 243 S_MULTICAST_CTRL, 244 P_XMII_CTRL_0, 245 P_XMII_CTRL_1, 246 }; 247 248 enum ksz_masks { 249 PORT_802_1P_REMAPPING, 250 SW_TAIL_TAG_ENABLE, 251 MIB_COUNTER_OVERFLOW, 252 MIB_COUNTER_VALID, 253 VLAN_TABLE_FID, 254 VLAN_TABLE_MEMBERSHIP, 255 VLAN_TABLE_VALID, 256 STATIC_MAC_TABLE_VALID, 257 STATIC_MAC_TABLE_USE_FID, 258 STATIC_MAC_TABLE_FID, 259 STATIC_MAC_TABLE_OVERRIDE, 260 STATIC_MAC_TABLE_FWD_PORTS, 261 DYNAMIC_MAC_TABLE_ENTRIES_H, 262 DYNAMIC_MAC_TABLE_MAC_EMPTY, 263 DYNAMIC_MAC_TABLE_NOT_READY, 264 DYNAMIC_MAC_TABLE_ENTRIES, 265 DYNAMIC_MAC_TABLE_FID, 266 DYNAMIC_MAC_TABLE_SRC_PORT, 267 DYNAMIC_MAC_TABLE_TIMESTAMP, 268 ALU_STAT_WRITE, 269 ALU_STAT_READ, 270 P_MII_TX_FLOW_CTRL, 271 P_MII_RX_FLOW_CTRL, 272 }; 273 274 enum ksz_shifts { 275 VLAN_TABLE_MEMBERSHIP_S, 276 VLAN_TABLE, 277 STATIC_MAC_FWD_PORTS, 278 STATIC_MAC_FID, 279 DYNAMIC_MAC_ENTRIES_H, 280 DYNAMIC_MAC_ENTRIES, 281 DYNAMIC_MAC_FID, 282 DYNAMIC_MAC_TIMESTAMP, 283 DYNAMIC_MAC_SRC_PORT, 284 ALU_STAT_INDEX, 285 }; 286 287 enum ksz_xmii_ctrl0 { 288 P_MII_100MBIT, 289 P_MII_10MBIT, 290 P_MII_FULL_DUPLEX, 291 P_MII_HALF_DUPLEX, 292 }; 293 294 enum ksz_xmii_ctrl1 { 295 P_RGMII_SEL, 296 P_RMII_SEL, 297 P_GMII_SEL, 298 P_MII_SEL, 299 P_GMII_1GBIT, 300 P_GMII_NOT_1GBIT, 301 }; 302 303 struct alu_struct { 304 /* entry 1 */ 305 u8 is_static:1; 306 u8 is_src_filter:1; 307 u8 is_dst_filter:1; 308 u8 prio_age:3; 309 u32 _reserv_0_1:23; 310 u8 mstp:3; 311 /* entry 2 */ 312 u8 is_override:1; 313 u8 is_use_fid:1; 314 u32 _reserv_1_1:23; 315 u8 port_forward:7; 316 /* entry 3 & 4*/ 317 u32 _reserv_2_1:9; 318 u8 fid:7; 319 u8 mac[ETH_ALEN]; 320 }; 321 322 struct ksz_dev_ops { 323 int (*setup)(struct dsa_switch *ds); 324 void (*teardown)(struct dsa_switch *ds); 325 u32 (*get_port_addr)(int port, int offset); 326 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 327 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 328 void (*port_cleanup)(struct ksz_device *dev, int port); 329 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 330 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 331 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 332 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 333 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 334 u64 *cnt); 335 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 336 u64 *dropped, u64 *cnt); 337 void (*r_mib_stat64)(struct ksz_device *dev, int port); 338 int (*vlan_filtering)(struct ksz_device *dev, int port, 339 bool flag, struct netlink_ext_ack *extack); 340 int (*vlan_add)(struct ksz_device *dev, int port, 341 const struct switchdev_obj_port_vlan *vlan, 342 struct netlink_ext_ack *extack); 343 int (*vlan_del)(struct ksz_device *dev, int port, 344 const struct switchdev_obj_port_vlan *vlan); 345 int (*mirror_add)(struct ksz_device *dev, int port, 346 struct dsa_mall_mirror_tc_entry *mirror, 347 bool ingress, struct netlink_ext_ack *extack); 348 void (*mirror_del)(struct ksz_device *dev, int port, 349 struct dsa_mall_mirror_tc_entry *mirror); 350 int (*fdb_add)(struct ksz_device *dev, int port, 351 const unsigned char *addr, u16 vid, struct dsa_db db); 352 int (*fdb_del)(struct ksz_device *dev, int port, 353 const unsigned char *addr, u16 vid, struct dsa_db db); 354 int (*fdb_dump)(struct ksz_device *dev, int port, 355 dsa_fdb_dump_cb_t *cb, void *data); 356 int (*mdb_add)(struct ksz_device *dev, int port, 357 const struct switchdev_obj_port_mdb *mdb, 358 struct dsa_db db); 359 int (*mdb_del)(struct ksz_device *dev, int port, 360 const struct switchdev_obj_port_mdb *mdb, 361 struct dsa_db db); 362 void (*get_caps)(struct ksz_device *dev, int port, 363 struct phylink_config *config); 364 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 365 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 366 void (*port_init_cnt)(struct ksz_device *dev, int port); 367 void (*phylink_mac_config)(struct ksz_device *dev, int port, 368 unsigned int mode, 369 const struct phylink_link_state *state); 370 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 371 unsigned int mode, 372 phy_interface_t interface, 373 struct phy_device *phydev, int speed, 374 int duplex, bool tx_pause, bool rx_pause); 375 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 376 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 377 void (*get_wol)(struct ksz_device *dev, int port, 378 struct ethtool_wolinfo *wol); 379 int (*set_wol)(struct ksz_device *dev, int port, 380 struct ethtool_wolinfo *wol); 381 void (*config_cpu_port)(struct dsa_switch *ds); 382 int (*enable_stp_addr)(struct ksz_device *dev); 383 int (*reset)(struct ksz_device *dev); 384 int (*init)(struct ksz_device *dev); 385 void (*exit)(struct ksz_device *dev); 386 }; 387 388 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 389 int ksz_switch_register(struct ksz_device *dev); 390 void ksz_switch_remove(struct ksz_device *dev); 391 392 void ksz_init_mib_timer(struct ksz_device *dev); 393 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 394 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 395 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 396 bool ksz_get_gbit(struct ksz_device *dev, int port); 397 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 398 extern const struct ksz_chip_data ksz_switch_chips[]; 399 400 /* Common register access functions */ 401 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 402 { 403 return dev->regmap[KSZ_REGMAP_8]; 404 } 405 406 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 407 { 408 return dev->regmap[KSZ_REGMAP_16]; 409 } 410 411 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 412 { 413 return dev->regmap[KSZ_REGMAP_32]; 414 } 415 416 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 417 { 418 unsigned int value; 419 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 420 421 if (ret) 422 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 423 ERR_PTR(ret)); 424 425 *val = value; 426 return ret; 427 } 428 429 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 430 { 431 unsigned int value; 432 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 433 434 if (ret) 435 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 436 ERR_PTR(ret)); 437 438 *val = value; 439 return ret; 440 } 441 442 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 443 { 444 unsigned int value; 445 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 446 447 if (ret) 448 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 449 ERR_PTR(ret)); 450 451 *val = value; 452 return ret; 453 } 454 455 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 456 { 457 u32 value[2]; 458 int ret; 459 460 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 461 if (ret) 462 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 463 ERR_PTR(ret)); 464 else 465 *val = (u64)value[0] << 32 | value[1]; 466 467 return ret; 468 } 469 470 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 471 { 472 int ret; 473 474 ret = regmap_write(ksz_regmap_8(dev), reg, value); 475 if (ret) 476 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 477 ERR_PTR(ret)); 478 479 return ret; 480 } 481 482 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 483 { 484 int ret; 485 486 ret = regmap_write(ksz_regmap_16(dev), reg, value); 487 if (ret) 488 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 489 ERR_PTR(ret)); 490 491 return ret; 492 } 493 494 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 495 { 496 int ret; 497 498 ret = regmap_write(ksz_regmap_32(dev), reg, value); 499 if (ret) 500 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 501 ERR_PTR(ret)); 502 503 return ret; 504 } 505 506 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 507 u16 value) 508 { 509 int ret; 510 511 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 512 if (ret) 513 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 514 ERR_PTR(ret)); 515 516 return ret; 517 } 518 519 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 520 u32 value) 521 { 522 int ret; 523 524 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 525 if (ret) 526 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 527 ERR_PTR(ret)); 528 529 return ret; 530 } 531 532 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 533 { 534 u32 val[2]; 535 536 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 537 value = swab64(value); 538 val[0] = swab32(value & 0xffffffffULL); 539 val[1] = swab32(value >> 32ULL); 540 541 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 542 } 543 544 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 545 { 546 int ret; 547 548 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 549 if (ret) 550 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 551 ERR_PTR(ret)); 552 553 return ret; 554 } 555 556 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 557 u8 *data) 558 { 559 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 560 } 561 562 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 563 u16 *data) 564 { 565 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 566 } 567 568 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 569 u32 *data) 570 { 571 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 572 } 573 574 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 575 u8 data) 576 { 577 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 578 } 579 580 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 581 u16 data) 582 { 583 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 584 data); 585 } 586 587 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 588 u32 data) 589 { 590 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 591 data); 592 } 593 594 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 595 u8 mask, u8 val) 596 { 597 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 598 mask, val); 599 } 600 601 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 602 u32 mask, u32 val) 603 { 604 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 605 mask, val); 606 } 607 608 static inline void ksz_regmap_lock(void *__mtx) 609 { 610 struct mutex *mtx = __mtx; 611 mutex_lock(mtx); 612 } 613 614 static inline void ksz_regmap_unlock(void *__mtx) 615 { 616 struct mutex *mtx = __mtx; 617 mutex_unlock(mtx); 618 } 619 620 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 621 { 622 return dev->chip_id == KSZ8795_CHIP_ID || 623 dev->chip_id == KSZ8794_CHIP_ID || 624 dev->chip_id == KSZ8765_CHIP_ID; 625 } 626 627 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 628 { 629 return dev->chip_id == KSZ8830_CHIP_ID; 630 } 631 632 static inline int is_lan937x(struct ksz_device *dev) 633 { 634 return dev->chip_id == LAN9370_CHIP_ID || 635 dev->chip_id == LAN9371_CHIP_ID || 636 dev->chip_id == LAN9372_CHIP_ID || 637 dev->chip_id == LAN9373_CHIP_ID || 638 dev->chip_id == LAN9374_CHIP_ID; 639 } 640 641 /* STP State Defines */ 642 #define PORT_TX_ENABLE BIT(2) 643 #define PORT_RX_ENABLE BIT(1) 644 #define PORT_LEARN_DISABLE BIT(0) 645 646 /* Switch ID Defines */ 647 #define REG_CHIP_ID0 0x00 648 649 #define SW_FAMILY_ID_M GENMASK(15, 8) 650 #define KSZ87_FAMILY_ID 0x87 651 #define KSZ88_FAMILY_ID 0x88 652 653 #define KSZ8_PORT_STATUS_0 0x08 654 #define KSZ8_PORT_FIBER_MODE BIT(7) 655 656 #define SW_CHIP_ID_M GENMASK(7, 4) 657 #define KSZ87_CHIP_ID_94 0x6 658 #define KSZ87_CHIP_ID_95 0x9 659 #define KSZ88_CHIP_ID_63 0x3 660 661 #define SW_REV_ID_M GENMASK(7, 4) 662 663 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 664 #define REG_CHIP_ID4 0x0f 665 #define SKU_ID_KSZ8563 0x3c 666 #define SKU_ID_KSZ9563 0x1c 667 668 /* Driver set switch broadcast storm protection at 10% rate. */ 669 #define BROADCAST_STORM_PROT_RATE 10 670 671 /* 148,800 frames * 67 ms / 100 */ 672 #define BROADCAST_STORM_VALUE 9969 673 674 #define BROADCAST_STORM_RATE_HI 0x07 675 #define BROADCAST_STORM_RATE_LO 0xFF 676 #define BROADCAST_STORM_RATE 0x07FF 677 678 #define MULTICAST_STORM_DISABLE BIT(6) 679 680 #define SW_START 0x01 681 682 /* xMII configuration */ 683 #define P_MII_DUPLEX_M BIT(6) 684 #define P_MII_100MBIT_M BIT(4) 685 686 #define P_GMII_1GBIT_M BIT(6) 687 #define P_RGMII_ID_IG_ENABLE BIT(4) 688 #define P_RGMII_ID_EG_ENABLE BIT(3) 689 #define P_MII_MAC_MODE BIT(2) 690 #define P_MII_SEL_M 0x3 691 692 /* Interrupt */ 693 #define REG_SW_PORT_INT_STATUS__1 0x001B 694 #define REG_SW_PORT_INT_MASK__1 0x001F 695 696 #define REG_PORT_INT_STATUS 0x001B 697 #define REG_PORT_INT_MASK 0x001F 698 699 #define PORT_SRC_PHY_INT 1 700 #define PORT_SRC_PTP_INT 2 701 702 #define KSZ8795_HUGE_PACKET_SIZE 2000 703 #define KSZ8863_HUGE_PACKET_SIZE 1916 704 #define KSZ8863_NORMAL_PACKET_SIZE 1536 705 #define KSZ8_LEGAL_PACKET_SIZE 1518 706 #define KSZ9477_MAX_FRAME_SIZE 9000 707 708 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 709 /* Drive Strength of I/O Pad 710 * 0: 8mA, 1: 16mA 711 */ 712 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 713 714 #define KSZ8795_REG_SW_CTRL_20 0xa3 715 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 716 #define SW_DRIVE_STRENGTH_M 0x7 717 #define SW_DRIVE_STRENGTH_2MA 0 718 #define SW_DRIVE_STRENGTH_4MA 1 719 #define SW_DRIVE_STRENGTH_8MA 2 720 #define SW_DRIVE_STRENGTH_12MA 3 721 #define SW_DRIVE_STRENGTH_16MA 4 722 #define SW_DRIVE_STRENGTH_20MA 5 723 #define SW_DRIVE_STRENGTH_24MA 6 724 #define SW_DRIVE_STRENGTH_28MA 7 725 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 726 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 727 728 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 729 #define KSZ9477_OUT_RATE_NO_LIMIT 0 730 731 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 732 733 #define KSZ9477_PORT_TC_MAP_S 4 734 #define KSZ9477_MAX_TC_PRIO 7 735 736 /* CBS related registers */ 737 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 738 739 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 740 741 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 742 #define MTI_SCHEDULE_STRICT_PRIO 0 743 #define MTI_SCHEDULE_WRR 2 744 #define MTI_SHAPING_M GENMASK(5, 4) 745 #define MTI_SHAPING_OFF 0 746 #define MTI_SHAPING_SRP 1 747 #define MTI_SHAPING_TIME_AWARE 2 748 749 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 750 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 751 752 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 753 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 754 755 /* Regmap tables generation */ 756 #define KSZ_SPI_OP_RD 3 757 #define KSZ_SPI_OP_WR 2 758 759 #define swabnot_used(x) 0 760 761 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 762 swab##swp((opcode) << ((regbits) + (regpad))) 763 764 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 765 { \ 766 .name = #width, \ 767 .val_bits = (width), \ 768 .reg_stride = 1, \ 769 .reg_bits = (regbits) + (regalign), \ 770 .pad_bits = (regpad), \ 771 .max_register = BIT(regbits) - 1, \ 772 .cache_type = REGCACHE_NONE, \ 773 .read_flag_mask = \ 774 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 775 regbits, regpad), \ 776 .write_flag_mask = \ 777 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 778 regbits, regpad), \ 779 .lock = ksz_regmap_lock, \ 780 .unlock = ksz_regmap_unlock, \ 781 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 782 .val_format_endian = REGMAP_ENDIAN_BIG \ 783 } 784 785 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 786 static const struct regmap_config ksz##_regmap_config[] = { \ 787 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 788 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 789 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 790 } 791 792 #endif 793