1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 #include <linux/platform_data/microchip-ksz.h> 18 19 #include "ksz_ptp.h" 20 21 #define KSZ_MAX_NUM_PORTS 8 22 23 struct ksz_device; 24 struct ksz_port; 25 struct phylink_mac_ops; 26 27 enum ksz_regmap_width { 28 KSZ_REGMAP_8, 29 KSZ_REGMAP_16, 30 KSZ_REGMAP_32, 31 __KSZ_NUM_REGMAPS, 32 }; 33 34 struct vlan_table { 35 u32 table[3]; 36 }; 37 38 struct ksz_port_mib { 39 struct mutex cnt_mutex; /* structure access */ 40 u8 cnt_ptr; 41 u64 *counters; 42 struct rtnl_link_stats64 stats64; 43 struct ethtool_pause_stats pause_stats; 44 struct spinlock stats64_lock; 45 }; 46 47 struct ksz_mib_names { 48 int index; 49 char string[ETH_GSTRING_LEN]; 50 }; 51 52 struct ksz_chip_data { 53 u32 chip_id; 54 const char *dev_name; 55 int num_vlans; 56 int num_alus; 57 int num_statics; 58 int cpu_ports; 59 int port_cnt; 60 u8 port_nirqs; 61 u8 num_tx_queues; 62 bool tc_cbs_supported; 63 bool tc_ets_supported; 64 const struct ksz_dev_ops *ops; 65 const struct phylink_mac_ops *phylink_mac_ops; 66 bool ksz87xx_eee_link_erratum; 67 const struct ksz_mib_names *mib_names; 68 int mib_cnt; 69 u8 reg_mib_cnt; 70 const u16 *regs; 71 const u32 *masks; 72 const u8 *shifts; 73 const u8 *xmii_ctrl0; 74 const u8 *xmii_ctrl1; 75 int stp_ctrl_reg; 76 int broadcast_ctrl_reg; 77 int multicast_ctrl_reg; 78 int start_ctrl_reg; 79 bool supports_mii[KSZ_MAX_NUM_PORTS]; 80 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 81 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 82 bool internal_phy[KSZ_MAX_NUM_PORTS]; 83 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 84 const struct regmap_access_table *wr_table; 85 const struct regmap_access_table *rd_table; 86 }; 87 88 struct ksz_irq { 89 u16 masked; 90 u16 reg_mask; 91 u16 reg_status; 92 struct irq_domain *domain; 93 int nirqs; 94 int irq_num; 95 char name[16]; 96 struct ksz_device *dev; 97 }; 98 99 struct ksz_ptp_irq { 100 struct ksz_port *port; 101 u16 ts_reg; 102 bool ts_en; 103 char name[16]; 104 int num; 105 }; 106 107 struct ksz_switch_macaddr { 108 unsigned char addr[ETH_ALEN]; 109 refcount_t refcount; 110 }; 111 112 struct ksz_port { 113 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 114 bool learning; 115 bool isolated; 116 int stp_state; 117 struct phy_device phydev; 118 119 u32 fiber:1; /* port is fiber */ 120 u32 force:1; 121 u32 read:1; /* read MIB counters in background */ 122 u32 freeze:1; /* MIB counter freeze is enabled */ 123 124 struct ksz_port_mib mib; 125 phy_interface_t interface; 126 u32 rgmii_tx_val; 127 u32 rgmii_rx_val; 128 struct ksz_device *ksz_dev; 129 void *acl_priv; 130 struct ksz_irq pirq; 131 u8 num; 132 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 133 struct hwtstamp_config tstamp_config; 134 bool hwts_tx_en; 135 bool hwts_rx_en; 136 struct ksz_irq ptpirq; 137 struct ksz_ptp_irq ptpmsg_irq[3]; 138 ktime_t tstamp_msg; 139 struct completion tstamp_msg_comp; 140 #endif 141 bool manual_flow; 142 }; 143 144 struct ksz_device { 145 struct dsa_switch *ds; 146 struct ksz_platform_data *pdata; 147 const struct ksz_chip_data *info; 148 149 struct mutex dev_mutex; /* device access */ 150 struct mutex regmap_mutex; /* regmap access */ 151 struct mutex alu_mutex; /* ALU access */ 152 struct mutex vlan_mutex; /* vlan access */ 153 const struct ksz_dev_ops *dev_ops; 154 155 struct device *dev; 156 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 157 158 void *priv; 159 int irq; 160 161 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 162 163 /* chip specific data */ 164 u32 chip_id; 165 u8 chip_rev; 166 int cpu_port; /* port connected to CPU */ 167 int phy_port_cnt; 168 phy_interface_t compat_interface; 169 bool synclko_125; 170 bool synclko_disable; 171 bool wakeup_source; 172 173 struct vlan_table *vlan_cache; 174 175 struct ksz_port *ports; 176 struct delayed_work mib_read; 177 unsigned long mib_read_interval; 178 u16 mirror_rx; 179 u16 mirror_tx; 180 u16 port_mask; 181 struct mutex lock_irq; /* IRQ Access */ 182 struct ksz_irq girq; 183 struct ksz_ptp_data ptp_data; 184 185 struct ksz_switch_macaddr *switch_macaddr; 186 struct net_device *hsr_dev; /* HSR */ 187 u8 hsr_ports; 188 }; 189 190 /* List of supported models */ 191 enum ksz_model { 192 KSZ8563, 193 KSZ8567, 194 KSZ8795, 195 KSZ8794, 196 KSZ8765, 197 KSZ8830, 198 KSZ9477, 199 KSZ9896, 200 KSZ9897, 201 KSZ9893, 202 KSZ9563, 203 KSZ9567, 204 LAN9370, 205 LAN9371, 206 LAN9372, 207 LAN9373, 208 LAN9374, 209 }; 210 211 enum ksz_regs { 212 REG_SW_MAC_ADDR, 213 REG_IND_CTRL_0, 214 REG_IND_DATA_8, 215 REG_IND_DATA_CHECK, 216 REG_IND_DATA_HI, 217 REG_IND_DATA_LO, 218 REG_IND_MIB_CHECK, 219 REG_IND_BYTE, 220 P_FORCE_CTRL, 221 P_LINK_STATUS, 222 P_LOCAL_CTRL, 223 P_NEG_RESTART_CTRL, 224 P_REMOTE_STATUS, 225 P_SPEED_STATUS, 226 S_TAIL_TAG_CTRL, 227 P_STP_CTRL, 228 S_START_CTRL, 229 S_BROADCAST_CTRL, 230 S_MULTICAST_CTRL, 231 P_XMII_CTRL_0, 232 P_XMII_CTRL_1, 233 }; 234 235 enum ksz_masks { 236 PORT_802_1P_REMAPPING, 237 SW_TAIL_TAG_ENABLE, 238 MIB_COUNTER_OVERFLOW, 239 MIB_COUNTER_VALID, 240 VLAN_TABLE_FID, 241 VLAN_TABLE_MEMBERSHIP, 242 VLAN_TABLE_VALID, 243 STATIC_MAC_TABLE_VALID, 244 STATIC_MAC_TABLE_USE_FID, 245 STATIC_MAC_TABLE_FID, 246 STATIC_MAC_TABLE_OVERRIDE, 247 STATIC_MAC_TABLE_FWD_PORTS, 248 DYNAMIC_MAC_TABLE_ENTRIES_H, 249 DYNAMIC_MAC_TABLE_MAC_EMPTY, 250 DYNAMIC_MAC_TABLE_NOT_READY, 251 DYNAMIC_MAC_TABLE_ENTRIES, 252 DYNAMIC_MAC_TABLE_FID, 253 DYNAMIC_MAC_TABLE_SRC_PORT, 254 DYNAMIC_MAC_TABLE_TIMESTAMP, 255 ALU_STAT_WRITE, 256 ALU_STAT_READ, 257 P_MII_TX_FLOW_CTRL, 258 P_MII_RX_FLOW_CTRL, 259 }; 260 261 enum ksz_shifts { 262 VLAN_TABLE_MEMBERSHIP_S, 263 VLAN_TABLE, 264 STATIC_MAC_FWD_PORTS, 265 STATIC_MAC_FID, 266 DYNAMIC_MAC_ENTRIES_H, 267 DYNAMIC_MAC_ENTRIES, 268 DYNAMIC_MAC_FID, 269 DYNAMIC_MAC_TIMESTAMP, 270 DYNAMIC_MAC_SRC_PORT, 271 ALU_STAT_INDEX, 272 }; 273 274 enum ksz_xmii_ctrl0 { 275 P_MII_100MBIT, 276 P_MII_10MBIT, 277 P_MII_FULL_DUPLEX, 278 P_MII_HALF_DUPLEX, 279 }; 280 281 enum ksz_xmii_ctrl1 { 282 P_RGMII_SEL, 283 P_RMII_SEL, 284 P_GMII_SEL, 285 P_MII_SEL, 286 P_GMII_1GBIT, 287 P_GMII_NOT_1GBIT, 288 }; 289 290 struct alu_struct { 291 /* entry 1 */ 292 u8 is_static:1; 293 u8 is_src_filter:1; 294 u8 is_dst_filter:1; 295 u8 prio_age:3; 296 u32 _reserv_0_1:23; 297 u8 mstp:3; 298 /* entry 2 */ 299 u8 is_override:1; 300 u8 is_use_fid:1; 301 u32 _reserv_1_1:23; 302 u8 port_forward:7; 303 /* entry 3 & 4*/ 304 u32 _reserv_2_1:9; 305 u8 fid:7; 306 u8 mac[ETH_ALEN]; 307 }; 308 309 struct ksz_dev_ops { 310 int (*setup)(struct dsa_switch *ds); 311 void (*teardown)(struct dsa_switch *ds); 312 u32 (*get_port_addr)(int port, int offset); 313 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 314 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 315 void (*port_cleanup)(struct ksz_device *dev, int port); 316 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 317 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 318 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 319 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 320 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 321 u64 *cnt); 322 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 323 u64 *dropped, u64 *cnt); 324 void (*r_mib_stat64)(struct ksz_device *dev, int port); 325 int (*vlan_filtering)(struct ksz_device *dev, int port, 326 bool flag, struct netlink_ext_ack *extack); 327 int (*vlan_add)(struct ksz_device *dev, int port, 328 const struct switchdev_obj_port_vlan *vlan, 329 struct netlink_ext_ack *extack); 330 int (*vlan_del)(struct ksz_device *dev, int port, 331 const struct switchdev_obj_port_vlan *vlan); 332 int (*mirror_add)(struct ksz_device *dev, int port, 333 struct dsa_mall_mirror_tc_entry *mirror, 334 bool ingress, struct netlink_ext_ack *extack); 335 void (*mirror_del)(struct ksz_device *dev, int port, 336 struct dsa_mall_mirror_tc_entry *mirror); 337 int (*fdb_add)(struct ksz_device *dev, int port, 338 const unsigned char *addr, u16 vid, struct dsa_db db); 339 int (*fdb_del)(struct ksz_device *dev, int port, 340 const unsigned char *addr, u16 vid, struct dsa_db db); 341 int (*fdb_dump)(struct ksz_device *dev, int port, 342 dsa_fdb_dump_cb_t *cb, void *data); 343 int (*mdb_add)(struct ksz_device *dev, int port, 344 const struct switchdev_obj_port_mdb *mdb, 345 struct dsa_db db); 346 int (*mdb_del)(struct ksz_device *dev, int port, 347 const struct switchdev_obj_port_mdb *mdb, 348 struct dsa_db db); 349 void (*get_caps)(struct ksz_device *dev, int port, 350 struct phylink_config *config); 351 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 352 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 353 void (*port_init_cnt)(struct ksz_device *dev, int port); 354 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 355 unsigned int mode, 356 phy_interface_t interface, 357 struct phy_device *phydev, int speed, 358 int duplex, bool tx_pause, bool rx_pause); 359 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 360 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 361 void (*get_wol)(struct ksz_device *dev, int port, 362 struct ethtool_wolinfo *wol); 363 int (*set_wol)(struct ksz_device *dev, int port, 364 struct ethtool_wolinfo *wol); 365 void (*wol_pre_shutdown)(struct ksz_device *dev, bool *wol_enabled); 366 void (*config_cpu_port)(struct dsa_switch *ds); 367 int (*enable_stp_addr)(struct ksz_device *dev); 368 int (*reset)(struct ksz_device *dev); 369 int (*init)(struct ksz_device *dev); 370 void (*exit)(struct ksz_device *dev); 371 }; 372 373 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 374 int ksz_switch_register(struct ksz_device *dev); 375 void ksz_switch_remove(struct ksz_device *dev); 376 377 void ksz_init_mib_timer(struct ksz_device *dev); 378 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port); 379 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 380 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 381 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 382 bool ksz_get_gbit(struct ksz_device *dev, int port); 383 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 384 extern const struct ksz_chip_data ksz_switch_chips[]; 385 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 386 struct netlink_ext_ack *extack); 387 void ksz_switch_macaddr_put(struct dsa_switch *ds); 388 void ksz_switch_shutdown(struct ksz_device *dev); 389 390 /* Common register access functions */ 391 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 392 { 393 return dev->regmap[KSZ_REGMAP_8]; 394 } 395 396 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 397 { 398 return dev->regmap[KSZ_REGMAP_16]; 399 } 400 401 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 402 { 403 return dev->regmap[KSZ_REGMAP_32]; 404 } 405 406 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 407 { 408 unsigned int value; 409 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 410 411 if (ret) 412 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 413 ERR_PTR(ret)); 414 415 *val = value; 416 return ret; 417 } 418 419 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 420 { 421 unsigned int value; 422 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 423 424 if (ret) 425 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 426 ERR_PTR(ret)); 427 428 *val = value; 429 return ret; 430 } 431 432 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 433 { 434 unsigned int value; 435 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 436 437 if (ret) 438 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 439 ERR_PTR(ret)); 440 441 *val = value; 442 return ret; 443 } 444 445 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 446 { 447 u32 value[2]; 448 int ret; 449 450 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 451 if (ret) 452 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 453 ERR_PTR(ret)); 454 else 455 *val = (u64)value[0] << 32 | value[1]; 456 457 return ret; 458 } 459 460 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 461 { 462 int ret; 463 464 ret = regmap_write(ksz_regmap_8(dev), reg, value); 465 if (ret) 466 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 467 ERR_PTR(ret)); 468 469 return ret; 470 } 471 472 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 473 { 474 int ret; 475 476 ret = regmap_write(ksz_regmap_16(dev), reg, value); 477 if (ret) 478 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 479 ERR_PTR(ret)); 480 481 return ret; 482 } 483 484 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 485 { 486 int ret; 487 488 ret = regmap_write(ksz_regmap_32(dev), reg, value); 489 if (ret) 490 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 491 ERR_PTR(ret)); 492 493 return ret; 494 } 495 496 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 497 u16 value) 498 { 499 int ret; 500 501 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 502 if (ret) 503 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 504 ERR_PTR(ret)); 505 506 return ret; 507 } 508 509 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 510 u32 value) 511 { 512 int ret; 513 514 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 515 if (ret) 516 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 517 ERR_PTR(ret)); 518 519 return ret; 520 } 521 522 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 523 { 524 u32 val[2]; 525 526 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 527 value = swab64(value); 528 val[0] = swab32(value & 0xffffffffULL); 529 val[1] = swab32(value >> 32ULL); 530 531 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 532 } 533 534 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 535 { 536 int ret; 537 538 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 539 if (ret) 540 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 541 ERR_PTR(ret)); 542 543 return ret; 544 } 545 546 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 547 u8 *data) 548 { 549 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 550 } 551 552 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 553 u16 *data) 554 { 555 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 556 } 557 558 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 559 u32 *data) 560 { 561 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 562 } 563 564 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 565 u8 data) 566 { 567 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 568 } 569 570 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 571 u16 data) 572 { 573 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 574 data); 575 } 576 577 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 578 u32 data) 579 { 580 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 581 data); 582 } 583 584 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 585 u8 mask, u8 val) 586 { 587 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 588 mask, val); 589 } 590 591 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 592 u32 mask, u32 val) 593 { 594 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 595 mask, val); 596 } 597 598 static inline void ksz_regmap_lock(void *__mtx) 599 { 600 struct mutex *mtx = __mtx; 601 mutex_lock(mtx); 602 } 603 604 static inline void ksz_regmap_unlock(void *__mtx) 605 { 606 struct mutex *mtx = __mtx; 607 mutex_unlock(mtx); 608 } 609 610 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 611 { 612 return dev->chip_id == KSZ8795_CHIP_ID || 613 dev->chip_id == KSZ8794_CHIP_ID || 614 dev->chip_id == KSZ8765_CHIP_ID; 615 } 616 617 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 618 { 619 return dev->chip_id == KSZ8830_CHIP_ID; 620 } 621 622 static inline int is_lan937x(struct ksz_device *dev) 623 { 624 return dev->chip_id == LAN9370_CHIP_ID || 625 dev->chip_id == LAN9371_CHIP_ID || 626 dev->chip_id == LAN9372_CHIP_ID || 627 dev->chip_id == LAN9373_CHIP_ID || 628 dev->chip_id == LAN9374_CHIP_ID; 629 } 630 631 /* STP State Defines */ 632 #define PORT_TX_ENABLE BIT(2) 633 #define PORT_RX_ENABLE BIT(1) 634 #define PORT_LEARN_DISABLE BIT(0) 635 636 /* Switch ID Defines */ 637 #define REG_CHIP_ID0 0x00 638 639 #define SW_FAMILY_ID_M GENMASK(15, 8) 640 #define KSZ87_FAMILY_ID 0x87 641 #define KSZ88_FAMILY_ID 0x88 642 643 #define KSZ8_PORT_STATUS_0 0x08 644 #define KSZ8_PORT_FIBER_MODE BIT(7) 645 646 #define SW_CHIP_ID_M GENMASK(7, 4) 647 #define KSZ87_CHIP_ID_94 0x6 648 #define KSZ87_CHIP_ID_95 0x9 649 #define KSZ88_CHIP_ID_63 0x3 650 651 #define SW_REV_ID_M GENMASK(7, 4) 652 653 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 654 #define REG_CHIP_ID4 0x0f 655 #define SKU_ID_KSZ8563 0x3c 656 #define SKU_ID_KSZ9563 0x1c 657 658 /* Driver set switch broadcast storm protection at 10% rate. */ 659 #define BROADCAST_STORM_PROT_RATE 10 660 661 /* 148,800 frames * 67 ms / 100 */ 662 #define BROADCAST_STORM_VALUE 9969 663 664 #define BROADCAST_STORM_RATE_HI 0x07 665 #define BROADCAST_STORM_RATE_LO 0xFF 666 #define BROADCAST_STORM_RATE 0x07FF 667 668 #define MULTICAST_STORM_DISABLE BIT(6) 669 670 #define SW_START 0x01 671 672 /* xMII configuration */ 673 #define P_MII_DUPLEX_M BIT(6) 674 #define P_MII_100MBIT_M BIT(4) 675 676 #define P_GMII_1GBIT_M BIT(6) 677 #define P_RGMII_ID_IG_ENABLE BIT(4) 678 #define P_RGMII_ID_EG_ENABLE BIT(3) 679 #define P_MII_MAC_MODE BIT(2) 680 #define P_MII_SEL_M 0x3 681 682 /* Interrupt */ 683 #define REG_SW_PORT_INT_STATUS__1 0x001B 684 #define REG_SW_PORT_INT_MASK__1 0x001F 685 686 #define REG_PORT_INT_STATUS 0x001B 687 #define REG_PORT_INT_MASK 0x001F 688 689 #define PORT_SRC_PHY_INT 1 690 #define PORT_SRC_PTP_INT 2 691 692 #define KSZ8795_HUGE_PACKET_SIZE 2000 693 #define KSZ8863_HUGE_PACKET_SIZE 1916 694 #define KSZ8863_NORMAL_PACKET_SIZE 1536 695 #define KSZ8_LEGAL_PACKET_SIZE 1518 696 #define KSZ9477_MAX_FRAME_SIZE 9000 697 698 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 699 /* Drive Strength of I/O Pad 700 * 0: 8mA, 1: 16mA 701 */ 702 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 703 704 #define KSZ8795_REG_SW_CTRL_20 0xa3 705 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 706 #define SW_DRIVE_STRENGTH_M 0x7 707 #define SW_DRIVE_STRENGTH_2MA 0 708 #define SW_DRIVE_STRENGTH_4MA 1 709 #define SW_DRIVE_STRENGTH_8MA 2 710 #define SW_DRIVE_STRENGTH_12MA 3 711 #define SW_DRIVE_STRENGTH_16MA 4 712 #define SW_DRIVE_STRENGTH_20MA 5 713 #define SW_DRIVE_STRENGTH_24MA 6 714 #define SW_DRIVE_STRENGTH_28MA 7 715 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 716 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 717 718 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 719 #define KSZ9477_OUT_RATE_NO_LIMIT 0 720 721 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 722 723 #define KSZ9477_PORT_TC_MAP_S 4 724 #define KSZ9477_MAX_TC_PRIO 7 725 726 /* CBS related registers */ 727 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 728 729 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 730 731 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 732 #define MTI_SCHEDULE_STRICT_PRIO 0 733 #define MTI_SCHEDULE_WRR 2 734 #define MTI_SHAPING_M GENMASK(5, 4) 735 #define MTI_SHAPING_OFF 0 736 #define MTI_SHAPING_SRP 1 737 #define MTI_SHAPING_TIME_AWARE 2 738 739 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 740 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 741 742 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 743 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 744 745 /* Regmap tables generation */ 746 #define KSZ_SPI_OP_RD 3 747 #define KSZ_SPI_OP_WR 2 748 749 #define swabnot_used(x) 0 750 751 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 752 swab##swp((opcode) << ((regbits) + (regpad))) 753 754 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 755 { \ 756 .name = #width, \ 757 .val_bits = (width), \ 758 .reg_stride = 1, \ 759 .reg_bits = (regbits) + (regalign), \ 760 .pad_bits = (regpad), \ 761 .max_register = BIT(regbits) - 1, \ 762 .cache_type = REGCACHE_NONE, \ 763 .read_flag_mask = \ 764 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 765 regbits, regpad), \ 766 .write_flag_mask = \ 767 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 768 regbits, regpad), \ 769 .lock = ksz_regmap_lock, \ 770 .unlock = ksz_regmap_unlock, \ 771 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 772 .val_format_endian = REGMAP_ENDIAN_BIG \ 773 } 774 775 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 776 static const struct regmap_config ksz##_regmap_config[] = { \ 777 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 778 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 779 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 780 } 781 782 #endif 783