1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2024 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 #include <linux/platform_data/microchip-ksz.h> 18 19 #include "ksz_ptp.h" 20 21 #define KSZ_MAX_NUM_PORTS 8 22 /* all KSZ switches count ports from 1 */ 23 #define KSZ_PORT_1 0 24 #define KSZ_PORT_2 1 25 #define KSZ_PORT_4 3 26 27 struct ksz_device; 28 struct ksz_port; 29 struct phylink_mac_ops; 30 31 enum ksz_regmap_width { 32 KSZ_REGMAP_8, 33 KSZ_REGMAP_16, 34 KSZ_REGMAP_32, 35 __KSZ_NUM_REGMAPS, 36 }; 37 38 struct vlan_table { 39 u32 table[3]; 40 }; 41 42 struct ksz_port_mib { 43 struct mutex cnt_mutex; /* structure access */ 44 u8 cnt_ptr; 45 u64 *counters; 46 struct rtnl_link_stats64 stats64; 47 struct ethtool_pause_stats pause_stats; 48 struct spinlock stats64_lock; 49 }; 50 51 struct ksz_mib_names { 52 int index; 53 char string[ETH_GSTRING_LEN]; 54 }; 55 56 struct ksz_chip_data { 57 u32 chip_id; 58 const char *dev_name; 59 int num_vlans; 60 int num_alus; 61 int num_statics; 62 int cpu_ports; 63 int port_cnt; 64 u8 port_nirqs; 65 u8 num_tx_queues; 66 u8 num_ipms; /* number of Internal Priority Maps */ 67 bool tc_cbs_supported; 68 69 /** 70 * @phy_side_mdio_supported: Indicates if the chip supports an additional 71 * side MDIO channel for accessing integrated PHYs. 72 */ 73 bool phy_side_mdio_supported; 74 const struct ksz_dev_ops *ops; 75 const struct phylink_mac_ops *phylink_mac_ops; 76 bool phy_errata_9477; 77 bool ksz87xx_eee_link_erratum; 78 const struct ksz_mib_names *mib_names; 79 int mib_cnt; 80 u8 reg_mib_cnt; 81 const u16 *regs; 82 const u32 *masks; 83 const u8 *shifts; 84 const u8 *xmii_ctrl0; 85 const u8 *xmii_ctrl1; 86 int stp_ctrl_reg; 87 int broadcast_ctrl_reg; 88 int multicast_ctrl_reg; 89 int start_ctrl_reg; 90 bool supports_mii[KSZ_MAX_NUM_PORTS]; 91 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 92 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 93 bool internal_phy[KSZ_MAX_NUM_PORTS]; 94 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 95 const struct regmap_access_table *wr_table; 96 const struct regmap_access_table *rd_table; 97 }; 98 99 struct ksz_irq { 100 u16 masked; 101 u16 reg_mask; 102 u16 reg_status; 103 struct irq_domain *domain; 104 int nirqs; 105 int irq_num; 106 char name[16]; 107 struct ksz_device *dev; 108 }; 109 110 struct ksz_ptp_irq { 111 struct ksz_port *port; 112 u16 ts_reg; 113 bool ts_en; 114 char name[16]; 115 int num; 116 }; 117 118 struct ksz_switch_macaddr { 119 unsigned char addr[ETH_ALEN]; 120 refcount_t refcount; 121 }; 122 123 struct ksz_port { 124 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 125 bool learning; 126 bool isolated; 127 int stp_state; 128 struct phy_device phydev; 129 130 u32 fiber:1; /* port is fiber */ 131 u32 force:1; 132 u32 read:1; /* read MIB counters in background */ 133 u32 freeze:1; /* MIB counter freeze is enabled */ 134 135 struct ksz_port_mib mib; 136 phy_interface_t interface; 137 u32 rgmii_tx_val; 138 u32 rgmii_rx_val; 139 struct ksz_device *ksz_dev; 140 void *acl_priv; 141 struct ksz_irq pirq; 142 u8 num; 143 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 144 struct hwtstamp_config tstamp_config; 145 bool hwts_tx_en; 146 bool hwts_rx_en; 147 struct ksz_irq ptpirq; 148 struct ksz_ptp_irq ptpmsg_irq[3]; 149 ktime_t tstamp_msg; 150 struct completion tstamp_msg_comp; 151 #endif 152 bool manual_flow; 153 }; 154 155 struct ksz_device { 156 struct dsa_switch *ds; 157 struct ksz_platform_data *pdata; 158 const struct ksz_chip_data *info; 159 160 struct mutex dev_mutex; /* device access */ 161 struct mutex regmap_mutex; /* regmap access */ 162 struct mutex alu_mutex; /* ALU access */ 163 struct mutex vlan_mutex; /* vlan access */ 164 const struct ksz_dev_ops *dev_ops; 165 166 struct device *dev; 167 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 168 169 void *priv; 170 int irq; 171 172 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 173 174 /* chip specific data */ 175 u32 chip_id; 176 u8 chip_rev; 177 int cpu_port; /* port connected to CPU */ 178 int phy_port_cnt; 179 phy_interface_t compat_interface; 180 bool synclko_125; 181 bool synclko_disable; 182 bool wakeup_source; 183 bool pme_active_high; 184 185 struct vlan_table *vlan_cache; 186 187 struct ksz_port *ports; 188 struct delayed_work mib_read; 189 unsigned long mib_read_interval; 190 u16 mirror_rx; 191 u16 mirror_tx; 192 u16 port_mask; 193 struct mutex lock_irq; /* IRQ Access */ 194 struct ksz_irq girq; 195 struct ksz_ptp_data ptp_data; 196 197 struct ksz_switch_macaddr *switch_macaddr; 198 struct net_device *hsr_dev; /* HSR */ 199 u8 hsr_ports; 200 201 /** 202 * @phy_addr_map: Array mapping switch ports to their corresponding PHY 203 * addresses. 204 */ 205 u8 phy_addr_map[KSZ_MAX_NUM_PORTS]; 206 207 /** 208 * @parent_mdio_bus: Pointer to the external MDIO bus controller. 209 * 210 * This points to an external MDIO bus controller that is used to access 211 * the PHYs integrated within the switch. Unlike an integrated MDIO 212 * bus, this external controller provides a direct path for managing 213 * the switch’s internal PHYs, bypassing the main SPI interface. 214 */ 215 struct mii_bus *parent_mdio_bus; 216 }; 217 218 /* List of supported models */ 219 enum ksz_model { 220 KSZ8563, 221 KSZ8567, 222 KSZ8795, 223 KSZ8794, 224 KSZ8765, 225 KSZ88X3, 226 KSZ8864, 227 KSZ8895, 228 KSZ9477, 229 KSZ9896, 230 KSZ9897, 231 KSZ9893, 232 KSZ9563, 233 KSZ9567, 234 LAN9370, 235 LAN9371, 236 LAN9372, 237 LAN9373, 238 LAN9374, 239 }; 240 241 enum ksz_regs { 242 REG_SW_MAC_ADDR, 243 REG_IND_CTRL_0, 244 REG_IND_DATA_8, 245 REG_IND_DATA_CHECK, 246 REG_IND_DATA_HI, 247 REG_IND_DATA_LO, 248 REG_IND_MIB_CHECK, 249 REG_IND_BYTE, 250 P_FORCE_CTRL, 251 P_LINK_STATUS, 252 P_LOCAL_CTRL, 253 P_NEG_RESTART_CTRL, 254 P_REMOTE_STATUS, 255 P_SPEED_STATUS, 256 S_TAIL_TAG_CTRL, 257 P_STP_CTRL, 258 S_START_CTRL, 259 S_BROADCAST_CTRL, 260 S_MULTICAST_CTRL, 261 P_XMII_CTRL_0, 262 P_XMII_CTRL_1, 263 REG_SW_PME_CTRL, 264 REG_PORT_PME_STATUS, 265 REG_PORT_PME_CTRL, 266 }; 267 268 enum ksz_masks { 269 PORT_802_1P_REMAPPING, 270 SW_TAIL_TAG_ENABLE, 271 MIB_COUNTER_OVERFLOW, 272 MIB_COUNTER_VALID, 273 VLAN_TABLE_FID, 274 VLAN_TABLE_MEMBERSHIP, 275 VLAN_TABLE_VALID, 276 STATIC_MAC_TABLE_VALID, 277 STATIC_MAC_TABLE_USE_FID, 278 STATIC_MAC_TABLE_FID, 279 STATIC_MAC_TABLE_OVERRIDE, 280 STATIC_MAC_TABLE_FWD_PORTS, 281 DYNAMIC_MAC_TABLE_ENTRIES_H, 282 DYNAMIC_MAC_TABLE_MAC_EMPTY, 283 DYNAMIC_MAC_TABLE_NOT_READY, 284 DYNAMIC_MAC_TABLE_ENTRIES, 285 DYNAMIC_MAC_TABLE_FID, 286 DYNAMIC_MAC_TABLE_SRC_PORT, 287 DYNAMIC_MAC_TABLE_TIMESTAMP, 288 ALU_STAT_WRITE, 289 ALU_STAT_READ, 290 P_MII_TX_FLOW_CTRL, 291 P_MII_RX_FLOW_CTRL, 292 }; 293 294 enum ksz_shifts { 295 VLAN_TABLE_MEMBERSHIP_S, 296 VLAN_TABLE, 297 STATIC_MAC_FWD_PORTS, 298 STATIC_MAC_FID, 299 DYNAMIC_MAC_ENTRIES_H, 300 DYNAMIC_MAC_ENTRIES, 301 DYNAMIC_MAC_FID, 302 DYNAMIC_MAC_TIMESTAMP, 303 DYNAMIC_MAC_SRC_PORT, 304 ALU_STAT_INDEX, 305 }; 306 307 enum ksz_xmii_ctrl0 { 308 P_MII_100MBIT, 309 P_MII_10MBIT, 310 P_MII_FULL_DUPLEX, 311 P_MII_HALF_DUPLEX, 312 }; 313 314 enum ksz_xmii_ctrl1 { 315 P_RGMII_SEL, 316 P_RMII_SEL, 317 P_GMII_SEL, 318 P_MII_SEL, 319 P_GMII_1GBIT, 320 P_GMII_NOT_1GBIT, 321 }; 322 323 struct alu_struct { 324 /* entry 1 */ 325 u8 is_static:1; 326 u8 is_src_filter:1; 327 u8 is_dst_filter:1; 328 u8 prio_age:3; 329 u32 _reserv_0_1:23; 330 u8 mstp:3; 331 /* entry 2 */ 332 u8 is_override:1; 333 u8 is_use_fid:1; 334 u32 _reserv_1_1:23; 335 u8 port_forward:7; 336 /* entry 3 & 4*/ 337 u32 _reserv_2_1:9; 338 u8 fid:7; 339 u8 mac[ETH_ALEN]; 340 }; 341 342 struct ksz_dev_ops { 343 int (*setup)(struct dsa_switch *ds); 344 void (*teardown)(struct dsa_switch *ds); 345 u32 (*get_port_addr)(int port, int offset); 346 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 347 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 348 void (*port_cleanup)(struct ksz_device *dev, int port); 349 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 350 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 351 352 /** 353 * @mdio_bus_preinit: Function pointer to pre-initialize the MDIO bus 354 * for accessing PHYs. 355 * @dev: Pointer to device structure. 356 * @side_mdio: Boolean indicating if the PHYs are accessed over a side 357 * MDIO bus. 358 * 359 * This function pointer is used to configure the MDIO bus for PHY 360 * access before initiating regular PHY operations. It enables either 361 * SPI/I2C or side MDIO access modes by unlocking necessary registers 362 * and setting up access permissions for the selected mode. 363 * 364 * Return: 365 * - 0 on success. 366 * - Negative error code on failure. 367 */ 368 int (*mdio_bus_preinit)(struct ksz_device *dev, bool side_mdio); 369 370 /** 371 * @create_phy_addr_map: Function pointer to create a port-to-PHY 372 * address map. 373 * @dev: Pointer to device structure. 374 * @side_mdio: Boolean indicating if the PHYs are accessed over a side 375 * MDIO bus. 376 * 377 * This function pointer is responsible for mapping switch ports to PHY 378 * addresses according to the configured access mode (SPI or side MDIO) 379 * and the device’s strap configuration. The mapping setup may vary 380 * depending on the chip variant and configuration. Ensures the correct 381 * address mapping for PHY communication. 382 * 383 * Return: 384 * - 0 on success. 385 * - Negative error code on failure (e.g., invalid configuration). 386 */ 387 int (*create_phy_addr_map)(struct ksz_device *dev, bool side_mdio); 388 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 389 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 390 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 391 u64 *cnt); 392 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 393 u64 *dropped, u64 *cnt); 394 void (*r_mib_stat64)(struct ksz_device *dev, int port); 395 int (*vlan_filtering)(struct ksz_device *dev, int port, 396 bool flag, struct netlink_ext_ack *extack); 397 int (*vlan_add)(struct ksz_device *dev, int port, 398 const struct switchdev_obj_port_vlan *vlan, 399 struct netlink_ext_ack *extack); 400 int (*vlan_del)(struct ksz_device *dev, int port, 401 const struct switchdev_obj_port_vlan *vlan); 402 int (*mirror_add)(struct ksz_device *dev, int port, 403 struct dsa_mall_mirror_tc_entry *mirror, 404 bool ingress, struct netlink_ext_ack *extack); 405 void (*mirror_del)(struct ksz_device *dev, int port, 406 struct dsa_mall_mirror_tc_entry *mirror); 407 int (*fdb_add)(struct ksz_device *dev, int port, 408 const unsigned char *addr, u16 vid, struct dsa_db db); 409 int (*fdb_del)(struct ksz_device *dev, int port, 410 const unsigned char *addr, u16 vid, struct dsa_db db); 411 int (*fdb_dump)(struct ksz_device *dev, int port, 412 dsa_fdb_dump_cb_t *cb, void *data); 413 int (*mdb_add)(struct ksz_device *dev, int port, 414 const struct switchdev_obj_port_mdb *mdb, 415 struct dsa_db db); 416 int (*mdb_del)(struct ksz_device *dev, int port, 417 const struct switchdev_obj_port_mdb *mdb, 418 struct dsa_db db); 419 void (*get_caps)(struct ksz_device *dev, int port, 420 struct phylink_config *config); 421 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 422 int (*pme_write8)(struct ksz_device *dev, u32 reg, u8 value); 423 int (*pme_pread8)(struct ksz_device *dev, int port, int offset, 424 u8 *data); 425 int (*pme_pwrite8)(struct ksz_device *dev, int port, int offset, 426 u8 data); 427 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 428 void (*port_init_cnt)(struct ksz_device *dev, int port); 429 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 430 unsigned int mode, 431 phy_interface_t interface, 432 struct phy_device *phydev, int speed, 433 int duplex, bool tx_pause, bool rx_pause); 434 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 435 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 436 void (*config_cpu_port)(struct dsa_switch *ds); 437 int (*enable_stp_addr)(struct ksz_device *dev); 438 int (*reset)(struct ksz_device *dev); 439 int (*init)(struct ksz_device *dev); 440 void (*exit)(struct ksz_device *dev); 441 }; 442 443 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 444 int ksz_switch_register(struct ksz_device *dev); 445 void ksz_switch_remove(struct ksz_device *dev); 446 447 void ksz_init_mib_timer(struct ksz_device *dev); 448 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port); 449 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 450 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 451 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 452 bool ksz_get_gbit(struct ksz_device *dev, int port); 453 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 454 extern const struct ksz_chip_data ksz_switch_chips[]; 455 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 456 struct netlink_ext_ack *extack); 457 void ksz_switch_macaddr_put(struct dsa_switch *ds); 458 void ksz_switch_shutdown(struct ksz_device *dev); 459 int ksz_handle_wake_reason(struct ksz_device *dev, int port); 460 461 /* Common register access functions */ 462 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 463 { 464 return dev->regmap[KSZ_REGMAP_8]; 465 } 466 467 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 468 { 469 return dev->regmap[KSZ_REGMAP_16]; 470 } 471 472 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 473 { 474 return dev->regmap[KSZ_REGMAP_32]; 475 } 476 477 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 478 { 479 unsigned int value; 480 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 481 482 if (ret) 483 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 484 ERR_PTR(ret)); 485 486 *val = value; 487 return ret; 488 } 489 490 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 491 { 492 unsigned int value; 493 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 494 495 if (ret) 496 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 497 ERR_PTR(ret)); 498 499 *val = value; 500 return ret; 501 } 502 503 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 504 { 505 unsigned int value; 506 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 507 508 if (ret) 509 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 510 ERR_PTR(ret)); 511 512 *val = value; 513 return ret; 514 } 515 516 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 517 { 518 u32 value[2]; 519 int ret; 520 521 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 522 if (ret) 523 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 524 ERR_PTR(ret)); 525 else 526 *val = (u64)value[0] << 32 | value[1]; 527 528 return ret; 529 } 530 531 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 532 { 533 int ret; 534 535 ret = regmap_write(ksz_regmap_8(dev), reg, value); 536 if (ret) 537 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 538 ERR_PTR(ret)); 539 540 return ret; 541 } 542 543 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 544 { 545 int ret; 546 547 ret = regmap_write(ksz_regmap_16(dev), reg, value); 548 if (ret) 549 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 550 ERR_PTR(ret)); 551 552 return ret; 553 } 554 555 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 556 { 557 int ret; 558 559 ret = regmap_write(ksz_regmap_32(dev), reg, value); 560 if (ret) 561 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 562 ERR_PTR(ret)); 563 564 return ret; 565 } 566 567 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 568 u16 value) 569 { 570 int ret; 571 572 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 573 if (ret) 574 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 575 ERR_PTR(ret)); 576 577 return ret; 578 } 579 580 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 581 u32 value) 582 { 583 int ret; 584 585 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 586 if (ret) 587 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 588 ERR_PTR(ret)); 589 590 return ret; 591 } 592 593 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 594 { 595 u32 val[2]; 596 597 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 598 value = swab64(value); 599 val[0] = swab32(value & 0xffffffffULL); 600 val[1] = swab32(value >> 32ULL); 601 602 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 603 } 604 605 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 606 { 607 int ret; 608 609 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 610 if (ret) 611 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 612 ERR_PTR(ret)); 613 614 return ret; 615 } 616 617 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 618 u8 *data) 619 { 620 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 621 } 622 623 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 624 u16 *data) 625 { 626 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 627 } 628 629 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 630 u32 *data) 631 { 632 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 633 } 634 635 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 636 u8 data) 637 { 638 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 639 } 640 641 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 642 u16 data) 643 { 644 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 645 data); 646 } 647 648 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 649 u32 data) 650 { 651 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 652 data); 653 } 654 655 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 656 u8 mask, u8 val) 657 { 658 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 659 mask, val); 660 } 661 662 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 663 u32 mask, u32 val) 664 { 665 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 666 mask, val); 667 } 668 669 static inline void ksz_regmap_lock(void *__mtx) 670 { 671 struct mutex *mtx = __mtx; 672 mutex_lock(mtx); 673 } 674 675 static inline void ksz_regmap_unlock(void *__mtx) 676 { 677 struct mutex *mtx = __mtx; 678 mutex_unlock(mtx); 679 } 680 681 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 682 { 683 return dev->chip_id == KSZ8795_CHIP_ID || 684 dev->chip_id == KSZ8794_CHIP_ID || 685 dev->chip_id == KSZ8765_CHIP_ID; 686 } 687 688 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 689 { 690 return dev->chip_id == KSZ88X3_CHIP_ID; 691 } 692 693 static inline bool ksz_is_8895_family(struct ksz_device *dev) 694 { 695 return dev->chip_id == KSZ8895_CHIP_ID || 696 dev->chip_id == KSZ8864_CHIP_ID; 697 } 698 699 static inline bool is_ksz8(struct ksz_device *dev) 700 { 701 return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev) || 702 ksz_is_8895_family(dev); 703 } 704 705 static inline bool is_ksz88xx(struct ksz_device *dev) 706 { 707 return ksz_is_ksz88x3(dev) || ksz_is_8895_family(dev); 708 } 709 710 static inline bool is_ksz9477(struct ksz_device *dev) 711 { 712 return dev->chip_id == KSZ9477_CHIP_ID; 713 } 714 715 static inline int is_lan937x(struct ksz_device *dev) 716 { 717 return dev->chip_id == LAN9370_CHIP_ID || 718 dev->chip_id == LAN9371_CHIP_ID || 719 dev->chip_id == LAN9372_CHIP_ID || 720 dev->chip_id == LAN9373_CHIP_ID || 721 dev->chip_id == LAN9374_CHIP_ID; 722 } 723 724 static inline bool is_lan937x_tx_phy(struct ksz_device *dev, int port) 725 { 726 return (dev->chip_id == LAN9371_CHIP_ID || 727 dev->chip_id == LAN9372_CHIP_ID) && port == KSZ_PORT_4; 728 } 729 730 /* STP State Defines */ 731 #define PORT_TX_ENABLE BIT(2) 732 #define PORT_RX_ENABLE BIT(1) 733 #define PORT_LEARN_DISABLE BIT(0) 734 735 /* Switch ID Defines */ 736 #define REG_CHIP_ID0 0x00 737 738 #define SW_FAMILY_ID_M GENMASK(15, 8) 739 #define KSZ87_FAMILY_ID 0x87 740 #define KSZ88_FAMILY_ID 0x88 741 #define KSZ8895_FAMILY_ID 0x95 742 743 #define KSZ8_PORT_STATUS_0 0x08 744 #define KSZ8_PORT_FIBER_MODE BIT(7) 745 746 #define SW_CHIP_ID_M GENMASK(7, 4) 747 #define KSZ87_CHIP_ID_94 0x6 748 #define KSZ87_CHIP_ID_95 0x9 749 #define KSZ88_CHIP_ID_63 0x3 750 #define KSZ8895_CHIP_ID_95 0x4 751 #define KSZ8895_CHIP_ID_95R 0x6 752 753 /* KSZ8895 specific register */ 754 #define REG_KSZ8864_CHIP_ID 0xFE 755 #define SW_KSZ8864 BIT(7) 756 757 #define SW_REV_ID_M GENMASK(7, 4) 758 759 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 760 #define REG_CHIP_ID4 0x0f 761 #define SKU_ID_KSZ8563 0x3c 762 #define SKU_ID_KSZ9563 0x1c 763 764 /* Driver set switch broadcast storm protection at 10% rate. */ 765 #define BROADCAST_STORM_PROT_RATE 10 766 767 /* 148,800 frames * 67 ms / 100 */ 768 #define BROADCAST_STORM_VALUE 9969 769 770 #define BROADCAST_STORM_RATE_HI 0x07 771 #define BROADCAST_STORM_RATE_LO 0xFF 772 #define BROADCAST_STORM_RATE 0x07FF 773 774 #define MULTICAST_STORM_DISABLE BIT(6) 775 776 #define SW_START 0x01 777 778 /* xMII configuration */ 779 #define P_MII_DUPLEX_M BIT(6) 780 #define P_MII_100MBIT_M BIT(4) 781 782 #define P_GMII_1GBIT_M BIT(6) 783 #define P_RGMII_ID_IG_ENABLE BIT(4) 784 #define P_RGMII_ID_EG_ENABLE BIT(3) 785 #define P_MII_MAC_MODE BIT(2) 786 #define P_MII_SEL_M 0x3 787 788 /* KSZ9477, KSZ87xx Wake-on-LAN (WoL) masks */ 789 #define PME_WOL_MAGICPKT BIT(2) 790 #define PME_WOL_LINKUP BIT(1) 791 #define PME_WOL_ENERGY BIT(0) 792 793 #define PME_ENABLE BIT(1) 794 #define PME_POLARITY BIT(0) 795 796 #define KSZ87XX_REG_INT_EN 0x7D 797 #define KSZ87XX_INT_PME_MASK BIT(4) 798 799 /* Interrupt */ 800 #define REG_SW_PORT_INT_STATUS__1 0x001B 801 #define REG_SW_PORT_INT_MASK__1 0x001F 802 803 #define REG_PORT_INT_STATUS 0x001B 804 #define REG_PORT_INT_MASK 0x001F 805 806 #define PORT_SRC_PHY_INT 1 807 #define PORT_SRC_PTP_INT 2 808 809 #define KSZ8795_HUGE_PACKET_SIZE 2000 810 #define KSZ8863_HUGE_PACKET_SIZE 1916 811 #define KSZ8863_NORMAL_PACKET_SIZE 1536 812 #define KSZ8_LEGAL_PACKET_SIZE 1518 813 #define KSZ9477_MAX_FRAME_SIZE 9000 814 815 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 816 /* Drive Strength of I/O Pad 817 * 0: 8mA, 1: 16mA 818 */ 819 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 820 821 #define KSZ8795_REG_SW_CTRL_20 0xa3 822 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 823 #define SW_DRIVE_STRENGTH_M 0x7 824 #define SW_DRIVE_STRENGTH_2MA 0 825 #define SW_DRIVE_STRENGTH_4MA 1 826 #define SW_DRIVE_STRENGTH_8MA 2 827 #define SW_DRIVE_STRENGTH_12MA 3 828 #define SW_DRIVE_STRENGTH_16MA 4 829 #define SW_DRIVE_STRENGTH_20MA 5 830 #define SW_DRIVE_STRENGTH_24MA 6 831 #define SW_DRIVE_STRENGTH_28MA 7 832 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 833 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 834 835 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 836 #define KSZ9477_OUT_RATE_NO_LIMIT 0 837 838 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 839 840 #define KSZ9477_PORT_TC_MAP_S 4 841 842 /* CBS related registers */ 843 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 844 845 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 846 847 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 848 #define MTI_SCHEDULE_STRICT_PRIO 0 849 #define MTI_SCHEDULE_WRR 2 850 #define MTI_SHAPING_M GENMASK(5, 4) 851 #define MTI_SHAPING_OFF 0 852 #define MTI_SHAPING_SRP 1 853 #define MTI_SHAPING_TIME_AWARE 2 854 855 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 856 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 857 858 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 859 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 860 861 /* Regmap tables generation */ 862 #define KSZ_SPI_OP_RD 3 863 #define KSZ_SPI_OP_WR 2 864 865 #define swabnot_used(x) 0 866 867 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 868 swab##swp((opcode) << ((regbits) + (regpad))) 869 870 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 871 { \ 872 .name = #width, \ 873 .val_bits = (width), \ 874 .reg_stride = 1, \ 875 .reg_bits = (regbits) + (regalign), \ 876 .pad_bits = (regpad), \ 877 .max_register = BIT(regbits) - 1, \ 878 .cache_type = REGCACHE_NONE, \ 879 .read_flag_mask = \ 880 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 881 regbits, regpad), \ 882 .write_flag_mask = \ 883 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 884 regbits, regpad), \ 885 .lock = ksz_regmap_lock, \ 886 .unlock = ksz_regmap_unlock, \ 887 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 888 .val_format_endian = REGMAP_ENDIAN_BIG \ 889 } 890 891 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 892 static const struct regmap_config ksz##_regmap_config[] = { \ 893 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 894 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 895 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 896 } 897 898 #endif 899