1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2024 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 #include <linux/platform_data/microchip-ksz.h> 18 19 #include "ksz_ptp.h" 20 21 #define KSZ_MAX_NUM_PORTS 8 22 /* all KSZ switches count ports from 1 */ 23 #define KSZ_PORT_1 0 24 #define KSZ_PORT_2 1 25 #define KSZ_PORT_4 3 26 27 struct ksz_device; 28 struct ksz_port; 29 struct phylink_mac_ops; 30 31 enum ksz_regmap_width { 32 KSZ_REGMAP_8, 33 KSZ_REGMAP_16, 34 KSZ_REGMAP_32, 35 __KSZ_NUM_REGMAPS, 36 }; 37 38 struct vlan_table { 39 u32 table[3]; 40 }; 41 42 struct ksz_port_mib { 43 struct mutex cnt_mutex; /* structure access */ 44 u8 cnt_ptr; 45 u64 *counters; 46 struct rtnl_link_stats64 stats64; 47 struct ethtool_pause_stats pause_stats; 48 struct spinlock stats64_lock; 49 }; 50 51 struct ksz_mib_names { 52 int index; 53 char string[ETH_GSTRING_LEN]; 54 }; 55 56 struct ksz_chip_data { 57 u32 chip_id; 58 const char *dev_name; 59 int num_vlans; 60 int num_alus; 61 int num_statics; 62 int cpu_ports; 63 int port_cnt; 64 u8 port_nirqs; 65 u8 num_tx_queues; 66 u8 num_ipms; /* number of Internal Priority Maps */ 67 bool tc_cbs_supported; 68 69 /** 70 * @phy_side_mdio_supported: Indicates if the chip supports an additional 71 * side MDIO channel for accessing integrated PHYs. 72 */ 73 bool phy_side_mdio_supported; 74 const struct ksz_dev_ops *ops; 75 const struct phylink_mac_ops *phylink_mac_ops; 76 bool phy_errata_9477; 77 bool ksz87xx_eee_link_erratum; 78 const struct ksz_mib_names *mib_names; 79 int mib_cnt; 80 u8 reg_mib_cnt; 81 const u16 *regs; 82 const u32 *masks; 83 const u8 *shifts; 84 const u8 *xmii_ctrl0; 85 const u8 *xmii_ctrl1; 86 int stp_ctrl_reg; 87 int broadcast_ctrl_reg; 88 int multicast_ctrl_reg; 89 int start_ctrl_reg; 90 bool supports_mii[KSZ_MAX_NUM_PORTS]; 91 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 92 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 93 bool internal_phy[KSZ_MAX_NUM_PORTS]; 94 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 95 const struct regmap_access_table *wr_table; 96 const struct regmap_access_table *rd_table; 97 }; 98 99 struct ksz_irq { 100 u16 masked; 101 u16 reg_mask; 102 u16 reg_status; 103 struct irq_domain *domain; 104 int nirqs; 105 int irq_num; 106 char name[16]; 107 struct ksz_device *dev; 108 }; 109 110 struct ksz_ptp_irq { 111 struct ksz_port *port; 112 u16 ts_reg; 113 bool ts_en; 114 char name[16]; 115 int num; 116 }; 117 118 struct ksz_switch_macaddr { 119 unsigned char addr[ETH_ALEN]; 120 refcount_t refcount; 121 }; 122 123 struct ksz_port { 124 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 125 bool learning; 126 bool isolated; 127 int stp_state; 128 struct phy_device phydev; 129 130 u32 fiber:1; /* port is fiber */ 131 u32 force:1; 132 u32 read:1; /* read MIB counters in background */ 133 u32 freeze:1; /* MIB counter freeze is enabled */ 134 135 struct ksz_port_mib mib; 136 phy_interface_t interface; 137 u32 rgmii_tx_val; 138 u32 rgmii_rx_val; 139 struct ksz_device *ksz_dev; 140 void *acl_priv; 141 struct ksz_irq pirq; 142 u8 num; 143 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 144 struct hwtstamp_config tstamp_config; 145 bool hwts_tx_en; 146 bool hwts_rx_en; 147 struct ksz_irq ptpirq; 148 struct ksz_ptp_irq ptpmsg_irq[3]; 149 ktime_t tstamp_msg; 150 struct completion tstamp_msg_comp; 151 #endif 152 bool manual_flow; 153 }; 154 155 struct ksz_device { 156 struct dsa_switch *ds; 157 struct ksz_platform_data *pdata; 158 const struct ksz_chip_data *info; 159 160 struct mutex dev_mutex; /* device access */ 161 struct mutex regmap_mutex; /* regmap access */ 162 struct mutex alu_mutex; /* ALU access */ 163 struct mutex vlan_mutex; /* vlan access */ 164 const struct ksz_dev_ops *dev_ops; 165 166 struct device *dev; 167 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 168 169 void *priv; 170 int irq; 171 172 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 173 174 /* chip specific data */ 175 u32 chip_id; 176 u8 chip_rev; 177 int cpu_port; /* port connected to CPU */ 178 int phy_port_cnt; 179 phy_interface_t compat_interface; 180 bool synclko_125; 181 bool synclko_disable; 182 bool wakeup_source; 183 bool pme_active_high; 184 185 struct vlan_table *vlan_cache; 186 187 struct ksz_port *ports; 188 struct delayed_work mib_read; 189 unsigned long mib_read_interval; 190 u16 mirror_rx; 191 u16 mirror_tx; 192 u16 port_mask; 193 struct mutex lock_irq; /* IRQ Access */ 194 struct ksz_irq girq; 195 struct ksz_ptp_data ptp_data; 196 197 struct ksz_switch_macaddr *switch_macaddr; 198 struct net_device *hsr_dev; /* HSR */ 199 u8 hsr_ports; 200 201 /** 202 * @phy_addr_map: Array mapping switch ports to their corresponding PHY 203 * addresses. 204 */ 205 u8 phy_addr_map[KSZ_MAX_NUM_PORTS]; 206 207 /** 208 * @parent_mdio_bus: Pointer to the external MDIO bus controller. 209 * 210 * This points to an external MDIO bus controller that is used to access 211 * the PHYs integrated within the switch. Unlike an integrated MDIO 212 * bus, this external controller provides a direct path for managing 213 * the switch’s internal PHYs, bypassing the main SPI interface. 214 */ 215 struct mii_bus *parent_mdio_bus; 216 }; 217 218 /* List of supported models */ 219 enum ksz_model { 220 KSZ8563, 221 KSZ8567, 222 KSZ8795, 223 KSZ8794, 224 KSZ8765, 225 KSZ88X3, 226 KSZ8864, 227 KSZ8895, 228 KSZ9477, 229 KSZ9896, 230 KSZ9897, 231 KSZ9893, 232 KSZ9563, 233 KSZ9567, 234 LAN9370, 235 LAN9371, 236 LAN9372, 237 LAN9373, 238 LAN9374, 239 LAN9646, 240 }; 241 242 enum ksz_regs { 243 REG_SW_MAC_ADDR, 244 REG_IND_CTRL_0, 245 REG_IND_DATA_8, 246 REG_IND_DATA_CHECK, 247 REG_IND_DATA_HI, 248 REG_IND_DATA_LO, 249 REG_IND_MIB_CHECK, 250 REG_IND_BYTE, 251 P_FORCE_CTRL, 252 P_LINK_STATUS, 253 P_LOCAL_CTRL, 254 P_NEG_RESTART_CTRL, 255 P_REMOTE_STATUS, 256 P_SPEED_STATUS, 257 S_TAIL_TAG_CTRL, 258 P_STP_CTRL, 259 S_START_CTRL, 260 S_BROADCAST_CTRL, 261 S_MULTICAST_CTRL, 262 P_XMII_CTRL_0, 263 P_XMII_CTRL_1, 264 REG_SW_PME_CTRL, 265 REG_PORT_PME_STATUS, 266 REG_PORT_PME_CTRL, 267 }; 268 269 enum ksz_masks { 270 PORT_802_1P_REMAPPING, 271 SW_TAIL_TAG_ENABLE, 272 MIB_COUNTER_OVERFLOW, 273 MIB_COUNTER_VALID, 274 VLAN_TABLE_FID, 275 VLAN_TABLE_MEMBERSHIP, 276 VLAN_TABLE_VALID, 277 STATIC_MAC_TABLE_VALID, 278 STATIC_MAC_TABLE_USE_FID, 279 STATIC_MAC_TABLE_FID, 280 STATIC_MAC_TABLE_OVERRIDE, 281 STATIC_MAC_TABLE_FWD_PORTS, 282 DYNAMIC_MAC_TABLE_ENTRIES_H, 283 DYNAMIC_MAC_TABLE_MAC_EMPTY, 284 DYNAMIC_MAC_TABLE_NOT_READY, 285 DYNAMIC_MAC_TABLE_ENTRIES, 286 DYNAMIC_MAC_TABLE_FID, 287 DYNAMIC_MAC_TABLE_SRC_PORT, 288 DYNAMIC_MAC_TABLE_TIMESTAMP, 289 ALU_STAT_WRITE, 290 ALU_STAT_READ, 291 P_MII_TX_FLOW_CTRL, 292 P_MII_RX_FLOW_CTRL, 293 }; 294 295 enum ksz_shifts { 296 VLAN_TABLE_MEMBERSHIP_S, 297 VLAN_TABLE, 298 STATIC_MAC_FWD_PORTS, 299 STATIC_MAC_FID, 300 DYNAMIC_MAC_ENTRIES_H, 301 DYNAMIC_MAC_ENTRIES, 302 DYNAMIC_MAC_FID, 303 DYNAMIC_MAC_TIMESTAMP, 304 DYNAMIC_MAC_SRC_PORT, 305 ALU_STAT_INDEX, 306 }; 307 308 enum ksz_xmii_ctrl0 { 309 P_MII_100MBIT, 310 P_MII_10MBIT, 311 P_MII_FULL_DUPLEX, 312 P_MII_HALF_DUPLEX, 313 }; 314 315 enum ksz_xmii_ctrl1 { 316 P_RGMII_SEL, 317 P_RMII_SEL, 318 P_GMII_SEL, 319 P_MII_SEL, 320 P_GMII_1GBIT, 321 P_GMII_NOT_1GBIT, 322 }; 323 324 struct alu_struct { 325 /* entry 1 */ 326 u8 is_static:1; 327 u8 is_src_filter:1; 328 u8 is_dst_filter:1; 329 u8 prio_age:3; 330 u32 _reserv_0_1:23; 331 u8 mstp:3; 332 /* entry 2 */ 333 u8 is_override:1; 334 u8 is_use_fid:1; 335 u32 _reserv_1_1:23; 336 u8 port_forward:7; 337 /* entry 3 & 4*/ 338 u32 _reserv_2_1:9; 339 u8 fid:7; 340 u8 mac[ETH_ALEN]; 341 }; 342 343 struct ksz_dev_ops { 344 int (*setup)(struct dsa_switch *ds); 345 void (*teardown)(struct dsa_switch *ds); 346 u32 (*get_port_addr)(int port, int offset); 347 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 348 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 349 void (*port_cleanup)(struct ksz_device *dev, int port); 350 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 351 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 352 353 /** 354 * @mdio_bus_preinit: Function pointer to pre-initialize the MDIO bus 355 * for accessing PHYs. 356 * @dev: Pointer to device structure. 357 * @side_mdio: Boolean indicating if the PHYs are accessed over a side 358 * MDIO bus. 359 * 360 * This function pointer is used to configure the MDIO bus for PHY 361 * access before initiating regular PHY operations. It enables either 362 * SPI/I2C or side MDIO access modes by unlocking necessary registers 363 * and setting up access permissions for the selected mode. 364 * 365 * Return: 366 * - 0 on success. 367 * - Negative error code on failure. 368 */ 369 int (*mdio_bus_preinit)(struct ksz_device *dev, bool side_mdio); 370 371 /** 372 * @create_phy_addr_map: Function pointer to create a port-to-PHY 373 * address map. 374 * @dev: Pointer to device structure. 375 * @side_mdio: Boolean indicating if the PHYs are accessed over a side 376 * MDIO bus. 377 * 378 * This function pointer is responsible for mapping switch ports to PHY 379 * addresses according to the configured access mode (SPI or side MDIO) 380 * and the device’s strap configuration. The mapping setup may vary 381 * depending on the chip variant and configuration. Ensures the correct 382 * address mapping for PHY communication. 383 * 384 * Return: 385 * - 0 on success. 386 * - Negative error code on failure (e.g., invalid configuration). 387 */ 388 int (*create_phy_addr_map)(struct ksz_device *dev, bool side_mdio); 389 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 390 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 391 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 392 u64 *cnt); 393 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 394 u64 *dropped, u64 *cnt); 395 void (*r_mib_stat64)(struct ksz_device *dev, int port); 396 int (*vlan_filtering)(struct ksz_device *dev, int port, 397 bool flag, struct netlink_ext_ack *extack); 398 int (*vlan_add)(struct ksz_device *dev, int port, 399 const struct switchdev_obj_port_vlan *vlan, 400 struct netlink_ext_ack *extack); 401 int (*vlan_del)(struct ksz_device *dev, int port, 402 const struct switchdev_obj_port_vlan *vlan); 403 int (*mirror_add)(struct ksz_device *dev, int port, 404 struct dsa_mall_mirror_tc_entry *mirror, 405 bool ingress, struct netlink_ext_ack *extack); 406 void (*mirror_del)(struct ksz_device *dev, int port, 407 struct dsa_mall_mirror_tc_entry *mirror); 408 int (*fdb_add)(struct ksz_device *dev, int port, 409 const unsigned char *addr, u16 vid, struct dsa_db db); 410 int (*fdb_del)(struct ksz_device *dev, int port, 411 const unsigned char *addr, u16 vid, struct dsa_db db); 412 int (*fdb_dump)(struct ksz_device *dev, int port, 413 dsa_fdb_dump_cb_t *cb, void *data); 414 int (*mdb_add)(struct ksz_device *dev, int port, 415 const struct switchdev_obj_port_mdb *mdb, 416 struct dsa_db db); 417 int (*mdb_del)(struct ksz_device *dev, int port, 418 const struct switchdev_obj_port_mdb *mdb, 419 struct dsa_db db); 420 void (*get_caps)(struct ksz_device *dev, int port, 421 struct phylink_config *config); 422 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 423 int (*pme_write8)(struct ksz_device *dev, u32 reg, u8 value); 424 int (*pme_pread8)(struct ksz_device *dev, int port, int offset, 425 u8 *data); 426 int (*pme_pwrite8)(struct ksz_device *dev, int port, int offset, 427 u8 data); 428 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 429 void (*port_init_cnt)(struct ksz_device *dev, int port); 430 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 431 unsigned int mode, 432 phy_interface_t interface, 433 struct phy_device *phydev, int speed, 434 int duplex, bool tx_pause, bool rx_pause); 435 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 436 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 437 void (*config_cpu_port)(struct dsa_switch *ds); 438 int (*enable_stp_addr)(struct ksz_device *dev); 439 int (*reset)(struct ksz_device *dev); 440 int (*init)(struct ksz_device *dev); 441 void (*exit)(struct ksz_device *dev); 442 }; 443 444 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 445 int ksz_switch_register(struct ksz_device *dev); 446 void ksz_switch_remove(struct ksz_device *dev); 447 int ksz_switch_suspend(struct device *dev); 448 int ksz_switch_resume(struct device *dev); 449 450 void ksz_init_mib_timer(struct ksz_device *dev); 451 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port); 452 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 453 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 454 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 455 bool ksz_get_gbit(struct ksz_device *dev, int port); 456 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 457 extern const struct ksz_chip_data ksz_switch_chips[]; 458 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 459 struct netlink_ext_ack *extack); 460 void ksz_switch_macaddr_put(struct dsa_switch *ds); 461 void ksz_switch_shutdown(struct ksz_device *dev); 462 int ksz_handle_wake_reason(struct ksz_device *dev, int port); 463 464 /* Common register access functions */ 465 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 466 { 467 return dev->regmap[KSZ_REGMAP_8]; 468 } 469 470 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 471 { 472 return dev->regmap[KSZ_REGMAP_16]; 473 } 474 475 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 476 { 477 return dev->regmap[KSZ_REGMAP_32]; 478 } 479 480 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 481 { 482 unsigned int value; 483 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 484 485 if (ret) 486 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 487 ERR_PTR(ret)); 488 489 *val = value; 490 return ret; 491 } 492 493 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 494 { 495 unsigned int value; 496 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 497 498 if (ret) 499 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 500 ERR_PTR(ret)); 501 502 *val = value; 503 return ret; 504 } 505 506 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 507 { 508 unsigned int value; 509 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 510 511 if (ret) 512 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 513 ERR_PTR(ret)); 514 515 *val = value; 516 return ret; 517 } 518 519 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 520 { 521 u32 value[2]; 522 int ret; 523 524 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 525 if (ret) 526 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 527 ERR_PTR(ret)); 528 else 529 *val = (u64)value[0] << 32 | value[1]; 530 531 return ret; 532 } 533 534 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 535 { 536 int ret; 537 538 ret = regmap_write(ksz_regmap_8(dev), reg, value); 539 if (ret) 540 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 541 ERR_PTR(ret)); 542 543 return ret; 544 } 545 546 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 547 { 548 int ret; 549 550 ret = regmap_write(ksz_regmap_16(dev), reg, value); 551 if (ret) 552 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 553 ERR_PTR(ret)); 554 555 return ret; 556 } 557 558 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 559 { 560 int ret; 561 562 ret = regmap_write(ksz_regmap_32(dev), reg, value); 563 if (ret) 564 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 565 ERR_PTR(ret)); 566 567 return ret; 568 } 569 570 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 571 u16 value) 572 { 573 int ret; 574 575 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 576 if (ret) 577 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 578 ERR_PTR(ret)); 579 580 return ret; 581 } 582 583 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 584 u32 value) 585 { 586 int ret; 587 588 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 589 if (ret) 590 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 591 ERR_PTR(ret)); 592 593 return ret; 594 } 595 596 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 597 { 598 u32 val[2]; 599 600 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 601 value = swab64(value); 602 val[0] = swab32(value & 0xffffffffULL); 603 val[1] = swab32(value >> 32ULL); 604 605 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 606 } 607 608 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 609 { 610 int ret; 611 612 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 613 if (ret) 614 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 615 ERR_PTR(ret)); 616 617 return ret; 618 } 619 620 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 621 u8 *data) 622 { 623 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 624 } 625 626 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 627 u16 *data) 628 { 629 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 630 } 631 632 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 633 u32 *data) 634 { 635 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 636 } 637 638 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 639 u8 data) 640 { 641 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 642 } 643 644 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 645 u16 data) 646 { 647 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 648 data); 649 } 650 651 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 652 u32 data) 653 { 654 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 655 data); 656 } 657 658 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 659 u8 mask, u8 val) 660 { 661 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 662 mask, val); 663 } 664 665 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 666 u32 mask, u32 val) 667 { 668 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 669 mask, val); 670 } 671 672 static inline void ksz_regmap_lock(void *__mtx) 673 { 674 struct mutex *mtx = __mtx; 675 mutex_lock(mtx); 676 } 677 678 static inline void ksz_regmap_unlock(void *__mtx) 679 { 680 struct mutex *mtx = __mtx; 681 mutex_unlock(mtx); 682 } 683 684 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 685 { 686 return dev->chip_id == KSZ8795_CHIP_ID || 687 dev->chip_id == KSZ8794_CHIP_ID || 688 dev->chip_id == KSZ8765_CHIP_ID; 689 } 690 691 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 692 { 693 return dev->chip_id == KSZ88X3_CHIP_ID; 694 } 695 696 static inline bool ksz_is_8895_family(struct ksz_device *dev) 697 { 698 return dev->chip_id == KSZ8895_CHIP_ID || 699 dev->chip_id == KSZ8864_CHIP_ID; 700 } 701 702 static inline bool is_ksz8(struct ksz_device *dev) 703 { 704 return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev) || 705 ksz_is_8895_family(dev); 706 } 707 708 static inline bool is_ksz88xx(struct ksz_device *dev) 709 { 710 return ksz_is_ksz88x3(dev) || ksz_is_8895_family(dev); 711 } 712 713 static inline bool is_ksz9477(struct ksz_device *dev) 714 { 715 return dev->chip_id == KSZ9477_CHIP_ID; 716 } 717 718 static inline int is_lan937x(struct ksz_device *dev) 719 { 720 return dev->chip_id == LAN9370_CHIP_ID || 721 dev->chip_id == LAN9371_CHIP_ID || 722 dev->chip_id == LAN9372_CHIP_ID || 723 dev->chip_id == LAN9373_CHIP_ID || 724 dev->chip_id == LAN9374_CHIP_ID; 725 } 726 727 static inline bool is_lan937x_tx_phy(struct ksz_device *dev, int port) 728 { 729 return (dev->chip_id == LAN9371_CHIP_ID || 730 dev->chip_id == LAN9372_CHIP_ID) && port == KSZ_PORT_4; 731 } 732 733 /* STP State Defines */ 734 #define PORT_TX_ENABLE BIT(2) 735 #define PORT_RX_ENABLE BIT(1) 736 #define PORT_LEARN_DISABLE BIT(0) 737 738 /* Switch ID Defines */ 739 #define REG_CHIP_ID0 0x00 740 741 #define SW_FAMILY_ID_M GENMASK(15, 8) 742 #define KSZ87_FAMILY_ID 0x87 743 #define KSZ88_FAMILY_ID 0x88 744 #define KSZ8895_FAMILY_ID 0x95 745 746 #define KSZ8_PORT_STATUS_0 0x08 747 #define KSZ8_PORT_FIBER_MODE BIT(7) 748 749 #define SW_CHIP_ID_M GENMASK(7, 4) 750 #define KSZ87_CHIP_ID_94 0x6 751 #define KSZ87_CHIP_ID_95 0x9 752 #define KSZ88_CHIP_ID_63 0x3 753 #define KSZ8895_CHIP_ID_95 0x4 754 #define KSZ8895_CHIP_ID_95R 0x6 755 756 /* KSZ8895 specific register */ 757 #define REG_KSZ8864_CHIP_ID 0xFE 758 #define SW_KSZ8864 BIT(7) 759 760 #define SW_REV_ID_M GENMASK(7, 4) 761 762 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 763 #define REG_CHIP_ID4 0x0f 764 #define SKU_ID_KSZ8563 0x3c 765 #define SKU_ID_KSZ9563 0x1c 766 767 /* Driver set switch broadcast storm protection at 10% rate. */ 768 #define BROADCAST_STORM_PROT_RATE 10 769 770 /* 148,800 frames * 67 ms / 100 */ 771 #define BROADCAST_STORM_VALUE 9969 772 773 #define BROADCAST_STORM_RATE_HI 0x07 774 #define BROADCAST_STORM_RATE_LO 0xFF 775 #define BROADCAST_STORM_RATE 0x07FF 776 777 #define MULTICAST_STORM_DISABLE BIT(6) 778 779 #define SW_START 0x01 780 781 /* xMII configuration */ 782 #define P_MII_DUPLEX_M BIT(6) 783 #define P_MII_100MBIT_M BIT(4) 784 785 #define P_GMII_1GBIT_M BIT(6) 786 #define P_RGMII_ID_IG_ENABLE BIT(4) 787 #define P_RGMII_ID_EG_ENABLE BIT(3) 788 #define P_MII_MAC_MODE BIT(2) 789 #define P_MII_SEL_M 0x3 790 791 /* KSZ9477, KSZ87xx Wake-on-LAN (WoL) masks */ 792 #define PME_WOL_MAGICPKT BIT(2) 793 #define PME_WOL_LINKUP BIT(1) 794 #define PME_WOL_ENERGY BIT(0) 795 796 #define PME_ENABLE BIT(1) 797 #define PME_POLARITY BIT(0) 798 799 #define KSZ87XX_REG_INT_EN 0x7D 800 #define KSZ87XX_INT_PME_MASK BIT(4) 801 802 /* Interrupt */ 803 #define REG_SW_PORT_INT_STATUS__1 0x001B 804 #define REG_SW_PORT_INT_MASK__1 0x001F 805 806 #define REG_PORT_INT_STATUS 0x001B 807 #define REG_PORT_INT_MASK 0x001F 808 809 #define PORT_SRC_PHY_INT 1 810 #define PORT_SRC_PTP_INT 2 811 812 #define KSZ8795_HUGE_PACKET_SIZE 2000 813 #define KSZ8863_HUGE_PACKET_SIZE 1916 814 #define KSZ8863_NORMAL_PACKET_SIZE 1536 815 #define KSZ8_LEGAL_PACKET_SIZE 1518 816 #define KSZ9477_MAX_FRAME_SIZE 9000 817 818 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 819 /* Drive Strength of I/O Pad 820 * 0: 8mA, 1: 16mA 821 */ 822 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 823 824 #define KSZ8795_REG_SW_CTRL_20 0xa3 825 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 826 #define SW_DRIVE_STRENGTH_M 0x7 827 #define SW_DRIVE_STRENGTH_2MA 0 828 #define SW_DRIVE_STRENGTH_4MA 1 829 #define SW_DRIVE_STRENGTH_8MA 2 830 #define SW_DRIVE_STRENGTH_12MA 3 831 #define SW_DRIVE_STRENGTH_16MA 4 832 #define SW_DRIVE_STRENGTH_20MA 5 833 #define SW_DRIVE_STRENGTH_24MA 6 834 #define SW_DRIVE_STRENGTH_28MA 7 835 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 836 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 837 838 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 839 #define KSZ9477_OUT_RATE_NO_LIMIT 0 840 841 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 842 843 #define KSZ9477_PORT_TC_MAP_S 4 844 845 /* CBS related registers */ 846 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 847 848 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 849 850 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 851 #define MTI_SCHEDULE_STRICT_PRIO 0 852 #define MTI_SCHEDULE_WRR 2 853 #define MTI_SHAPING_M GENMASK(5, 4) 854 #define MTI_SHAPING_OFF 0 855 #define MTI_SHAPING_SRP 1 856 #define MTI_SHAPING_TIME_AWARE 2 857 858 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 859 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 860 861 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 862 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 863 864 /* Regmap tables generation */ 865 #define KSZ_SPI_OP_RD 3 866 #define KSZ_SPI_OP_WR 2 867 868 #define swabnot_used(x) 0 869 870 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 871 swab##swp((opcode) << ((regbits) + (regpad))) 872 873 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 874 { \ 875 .name = #width, \ 876 .val_bits = (width), \ 877 .reg_stride = 1, \ 878 .reg_bits = (regbits) + (regalign), \ 879 .pad_bits = (regpad), \ 880 .max_register = BIT(regbits) - 1, \ 881 .cache_type = REGCACHE_NONE, \ 882 .read_flag_mask = \ 883 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 884 regbits, regpad), \ 885 .write_flag_mask = \ 886 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 887 regbits, regpad), \ 888 .lock = ksz_regmap_lock, \ 889 .unlock = ksz_regmap_unlock, \ 890 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 891 .val_format_endian = REGMAP_ENDIAN_BIG \ 892 } 893 894 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 895 static const struct regmap_config ksz##_regmap_config[] = { \ 896 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 897 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 898 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 899 } 900 901 #endif 902