1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 17 #define KSZ_MAX_NUM_PORTS 8 18 19 struct vlan_table { 20 u32 table[3]; 21 }; 22 23 struct ksz_port_mib { 24 struct mutex cnt_mutex; /* structure access */ 25 u8 cnt_ptr; 26 u64 *counters; 27 struct rtnl_link_stats64 stats64; 28 struct ethtool_pause_stats pause_stats; 29 struct spinlock stats64_lock; 30 }; 31 32 struct ksz_mib_names { 33 int index; 34 char string[ETH_GSTRING_LEN]; 35 }; 36 37 struct ksz_chip_data { 38 u32 chip_id; 39 const char *dev_name; 40 int num_vlans; 41 int num_alus; 42 int num_statics; 43 int cpu_ports; 44 int port_cnt; 45 const struct ksz_dev_ops *ops; 46 bool phy_errata_9477; 47 bool ksz87xx_eee_link_erratum; 48 const struct ksz_mib_names *mib_names; 49 int mib_cnt; 50 u8 reg_mib_cnt; 51 const u16 *regs; 52 const u32 *masks; 53 const u8 *shifts; 54 int stp_ctrl_reg; 55 int broadcast_ctrl_reg; 56 int multicast_ctrl_reg; 57 int start_ctrl_reg; 58 bool supports_mii[KSZ_MAX_NUM_PORTS]; 59 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 60 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 61 bool internal_phy[KSZ_MAX_NUM_PORTS]; 62 }; 63 64 struct ksz_port { 65 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 66 int stp_state; 67 struct phy_device phydev; 68 69 u32 on:1; /* port is not disabled by hardware */ 70 u32 phy:1; /* port has a PHY */ 71 u32 fiber:1; /* port is fiber */ 72 u32 sgmii:1; /* port is SGMII */ 73 u32 force:1; 74 u32 read:1; /* read MIB counters in background */ 75 u32 freeze:1; /* MIB counter freeze is enabled */ 76 77 struct ksz_port_mib mib; 78 phy_interface_t interface; 79 u16 max_frame; 80 }; 81 82 struct ksz_device { 83 struct dsa_switch *ds; 84 struct ksz_platform_data *pdata; 85 const struct ksz_chip_data *info; 86 87 struct mutex dev_mutex; /* device access */ 88 struct mutex regmap_mutex; /* regmap access */ 89 struct mutex alu_mutex; /* ALU access */ 90 struct mutex vlan_mutex; /* vlan access */ 91 const struct ksz_dev_ops *dev_ops; 92 93 struct device *dev; 94 struct regmap *regmap[3]; 95 96 void *priv; 97 98 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 99 100 /* chip specific data */ 101 u32 chip_id; 102 u8 chip_rev; 103 int cpu_port; /* port connected to CPU */ 104 int phy_port_cnt; 105 phy_interface_t compat_interface; 106 bool synclko_125; 107 bool synclko_disable; 108 109 struct vlan_table *vlan_cache; 110 111 struct ksz_port *ports; 112 struct delayed_work mib_read; 113 unsigned long mib_read_interval; 114 u16 mirror_rx; 115 u16 mirror_tx; 116 u32 features; /* chip specific features */ 117 u16 port_mask; 118 }; 119 120 /* List of supported models */ 121 enum ksz_model { 122 KSZ8795, 123 KSZ8794, 124 KSZ8765, 125 KSZ8830, 126 KSZ9477, 127 KSZ9897, 128 KSZ9893, 129 KSZ9567, 130 LAN9370, 131 LAN9371, 132 LAN9372, 133 LAN9373, 134 LAN9374, 135 }; 136 137 enum ksz_chip_id { 138 KSZ8795_CHIP_ID = 0x8795, 139 KSZ8794_CHIP_ID = 0x8794, 140 KSZ8765_CHIP_ID = 0x8765, 141 KSZ8830_CHIP_ID = 0x8830, 142 KSZ9477_CHIP_ID = 0x00947700, 143 KSZ9897_CHIP_ID = 0x00989700, 144 KSZ9893_CHIP_ID = 0x00989300, 145 KSZ9567_CHIP_ID = 0x00956700, 146 LAN9370_CHIP_ID = 0x00937000, 147 LAN9371_CHIP_ID = 0x00937100, 148 LAN9372_CHIP_ID = 0x00937200, 149 LAN9373_CHIP_ID = 0x00937300, 150 LAN9374_CHIP_ID = 0x00937400, 151 }; 152 153 enum ksz_regs { 154 REG_IND_CTRL_0, 155 REG_IND_DATA_8, 156 REG_IND_DATA_CHECK, 157 REG_IND_DATA_HI, 158 REG_IND_DATA_LO, 159 REG_IND_MIB_CHECK, 160 REG_IND_BYTE, 161 P_FORCE_CTRL, 162 P_LINK_STATUS, 163 P_LOCAL_CTRL, 164 P_NEG_RESTART_CTRL, 165 P_REMOTE_STATUS, 166 P_SPEED_STATUS, 167 S_TAIL_TAG_CTRL, 168 P_STP_CTRL, 169 S_START_CTRL, 170 S_BROADCAST_CTRL, 171 S_MULTICAST_CTRL, 172 }; 173 174 enum ksz_masks { 175 PORT_802_1P_REMAPPING, 176 SW_TAIL_TAG_ENABLE, 177 MIB_COUNTER_OVERFLOW, 178 MIB_COUNTER_VALID, 179 VLAN_TABLE_FID, 180 VLAN_TABLE_MEMBERSHIP, 181 VLAN_TABLE_VALID, 182 STATIC_MAC_TABLE_VALID, 183 STATIC_MAC_TABLE_USE_FID, 184 STATIC_MAC_TABLE_FID, 185 STATIC_MAC_TABLE_OVERRIDE, 186 STATIC_MAC_TABLE_FWD_PORTS, 187 DYNAMIC_MAC_TABLE_ENTRIES_H, 188 DYNAMIC_MAC_TABLE_MAC_EMPTY, 189 DYNAMIC_MAC_TABLE_NOT_READY, 190 DYNAMIC_MAC_TABLE_ENTRIES, 191 DYNAMIC_MAC_TABLE_FID, 192 DYNAMIC_MAC_TABLE_SRC_PORT, 193 DYNAMIC_MAC_TABLE_TIMESTAMP, 194 ALU_STAT_WRITE, 195 ALU_STAT_READ, 196 }; 197 198 enum ksz_shifts { 199 VLAN_TABLE_MEMBERSHIP_S, 200 VLAN_TABLE, 201 STATIC_MAC_FWD_PORTS, 202 STATIC_MAC_FID, 203 DYNAMIC_MAC_ENTRIES_H, 204 DYNAMIC_MAC_ENTRIES, 205 DYNAMIC_MAC_FID, 206 DYNAMIC_MAC_TIMESTAMP, 207 DYNAMIC_MAC_SRC_PORT, 208 ALU_STAT_INDEX, 209 }; 210 211 struct alu_struct { 212 /* entry 1 */ 213 u8 is_static:1; 214 u8 is_src_filter:1; 215 u8 is_dst_filter:1; 216 u8 prio_age:3; 217 u32 _reserv_0_1:23; 218 u8 mstp:3; 219 /* entry 2 */ 220 u8 is_override:1; 221 u8 is_use_fid:1; 222 u32 _reserv_1_1:23; 223 u8 port_forward:7; 224 /* entry 3 & 4*/ 225 u32 _reserv_2_1:9; 226 u8 fid:7; 227 u8 mac[ETH_ALEN]; 228 }; 229 230 struct ksz_dev_ops { 231 int (*setup)(struct dsa_switch *ds); 232 u32 (*get_port_addr)(int port, int offset); 233 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 234 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 235 void (*port_cleanup)(struct ksz_device *dev, int port); 236 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 237 void (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 238 void (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 239 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 240 u64 *cnt); 241 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 242 u64 *dropped, u64 *cnt); 243 void (*r_mib_stat64)(struct ksz_device *dev, int port); 244 int (*vlan_filtering)(struct ksz_device *dev, int port, 245 bool flag, struct netlink_ext_ack *extack); 246 int (*vlan_add)(struct ksz_device *dev, int port, 247 const struct switchdev_obj_port_vlan *vlan, 248 struct netlink_ext_ack *extack); 249 int (*vlan_del)(struct ksz_device *dev, int port, 250 const struct switchdev_obj_port_vlan *vlan); 251 int (*mirror_add)(struct ksz_device *dev, int port, 252 struct dsa_mall_mirror_tc_entry *mirror, 253 bool ingress, struct netlink_ext_ack *extack); 254 void (*mirror_del)(struct ksz_device *dev, int port, 255 struct dsa_mall_mirror_tc_entry *mirror); 256 int (*fdb_add)(struct ksz_device *dev, int port, 257 const unsigned char *addr, u16 vid, struct dsa_db db); 258 int (*fdb_del)(struct ksz_device *dev, int port, 259 const unsigned char *addr, u16 vid, struct dsa_db db); 260 int (*fdb_dump)(struct ksz_device *dev, int port, 261 dsa_fdb_dump_cb_t *cb, void *data); 262 int (*mdb_add)(struct ksz_device *dev, int port, 263 const struct switchdev_obj_port_mdb *mdb, 264 struct dsa_db db); 265 int (*mdb_del)(struct ksz_device *dev, int port, 266 const struct switchdev_obj_port_mdb *mdb, 267 struct dsa_db db); 268 void (*get_caps)(struct ksz_device *dev, int port, 269 struct phylink_config *config); 270 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 271 int (*max_mtu)(struct ksz_device *dev, int port); 272 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 273 void (*port_init_cnt)(struct ksz_device *dev, int port); 274 void (*phylink_mac_config)(struct ksz_device *dev, int port, 275 unsigned int mode, 276 const struct phylink_link_state *state); 277 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 278 unsigned int mode, 279 phy_interface_t interface, 280 struct phy_device *phydev, int speed, 281 int duplex, bool tx_pause, bool rx_pause); 282 void (*config_cpu_port)(struct dsa_switch *ds); 283 int (*enable_stp_addr)(struct ksz_device *dev); 284 int (*reset)(struct ksz_device *dev); 285 int (*init)(struct ksz_device *dev); 286 void (*exit)(struct ksz_device *dev); 287 }; 288 289 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 290 int ksz_switch_register(struct ksz_device *dev); 291 void ksz_switch_remove(struct ksz_device *dev); 292 293 void ksz_init_mib_timer(struct ksz_device *dev); 294 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 295 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 296 extern const struct ksz_chip_data ksz_switch_chips[]; 297 298 /* Common register access functions */ 299 300 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 301 { 302 unsigned int value; 303 int ret = regmap_read(dev->regmap[0], reg, &value); 304 305 *val = value; 306 return ret; 307 } 308 309 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 310 { 311 unsigned int value; 312 int ret = regmap_read(dev->regmap[1], reg, &value); 313 314 *val = value; 315 return ret; 316 } 317 318 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 319 { 320 unsigned int value; 321 int ret = regmap_read(dev->regmap[2], reg, &value); 322 323 *val = value; 324 return ret; 325 } 326 327 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 328 { 329 u32 value[2]; 330 int ret; 331 332 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); 333 if (!ret) 334 *val = (u64)value[0] << 32 | value[1]; 335 336 return ret; 337 } 338 339 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 340 { 341 return regmap_write(dev->regmap[0], reg, value); 342 } 343 344 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 345 { 346 return regmap_write(dev->regmap[1], reg, value); 347 } 348 349 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 350 { 351 return regmap_write(dev->regmap[2], reg, value); 352 } 353 354 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 355 { 356 u32 val[2]; 357 358 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 359 value = swab64(value); 360 val[0] = swab32(value & 0xffffffffULL); 361 val[1] = swab32(value >> 32ULL); 362 363 return regmap_bulk_write(dev->regmap[2], reg, val, 2); 364 } 365 366 static inline void ksz_pread8(struct ksz_device *dev, int port, int offset, 367 u8 *data) 368 { 369 ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 370 } 371 372 static inline void ksz_pread16(struct ksz_device *dev, int port, int offset, 373 u16 *data) 374 { 375 ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 376 } 377 378 static inline void ksz_pread32(struct ksz_device *dev, int port, int offset, 379 u32 *data) 380 { 381 ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 382 } 383 384 static inline void ksz_pwrite8(struct ksz_device *dev, int port, int offset, 385 u8 data) 386 { 387 ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 388 } 389 390 static inline void ksz_pwrite16(struct ksz_device *dev, int port, int offset, 391 u16 data) 392 { 393 ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), data); 394 } 395 396 static inline void ksz_pwrite32(struct ksz_device *dev, int port, int offset, 397 u32 data) 398 { 399 ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), data); 400 } 401 402 static inline void ksz_regmap_lock(void *__mtx) 403 { 404 struct mutex *mtx = __mtx; 405 mutex_lock(mtx); 406 } 407 408 static inline void ksz_regmap_unlock(void *__mtx) 409 { 410 struct mutex *mtx = __mtx; 411 mutex_unlock(mtx); 412 } 413 414 static inline int is_lan937x(struct ksz_device *dev) 415 { 416 return dev->chip_id == LAN9370_CHIP_ID || 417 dev->chip_id == LAN9371_CHIP_ID || 418 dev->chip_id == LAN9372_CHIP_ID || 419 dev->chip_id == LAN9373_CHIP_ID || 420 dev->chip_id == LAN9374_CHIP_ID; 421 } 422 423 /* STP State Defines */ 424 #define PORT_TX_ENABLE BIT(2) 425 #define PORT_RX_ENABLE BIT(1) 426 #define PORT_LEARN_DISABLE BIT(0) 427 428 /* Switch ID Defines */ 429 #define REG_CHIP_ID0 0x00 430 431 #define SW_FAMILY_ID_M GENMASK(15, 8) 432 #define KSZ87_FAMILY_ID 0x87 433 #define KSZ88_FAMILY_ID 0x88 434 435 #define KSZ8_PORT_STATUS_0 0x08 436 #define KSZ8_PORT_FIBER_MODE BIT(7) 437 438 #define SW_CHIP_ID_M GENMASK(7, 4) 439 #define KSZ87_CHIP_ID_94 0x6 440 #define KSZ87_CHIP_ID_95 0x9 441 #define KSZ88_CHIP_ID_63 0x3 442 443 #define SW_REV_ID_M GENMASK(7, 4) 444 445 /* Driver set switch broadcast storm protection at 10% rate. */ 446 #define BROADCAST_STORM_PROT_RATE 10 447 448 /* 148,800 frames * 67 ms / 100 */ 449 #define BROADCAST_STORM_VALUE 9969 450 451 #define BROADCAST_STORM_RATE_HI 0x07 452 #define BROADCAST_STORM_RATE_LO 0xFF 453 #define BROADCAST_STORM_RATE 0x07FF 454 455 #define MULTICAST_STORM_DISABLE BIT(6) 456 457 #define SW_START 0x01 458 459 /* Regmap tables generation */ 460 #define KSZ_SPI_OP_RD 3 461 #define KSZ_SPI_OP_WR 2 462 463 #define swabnot_used(x) 0 464 465 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 466 swab##swp((opcode) << ((regbits) + (regpad))) 467 468 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 469 { \ 470 .name = #width, \ 471 .val_bits = (width), \ 472 .reg_stride = 1, \ 473 .reg_bits = (regbits) + (regalign), \ 474 .pad_bits = (regpad), \ 475 .max_register = BIT(regbits) - 1, \ 476 .cache_type = REGCACHE_NONE, \ 477 .read_flag_mask = \ 478 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 479 regbits, regpad), \ 480 .write_flag_mask = \ 481 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 482 regbits, regpad), \ 483 .lock = ksz_regmap_lock, \ 484 .unlock = ksz_regmap_unlock, \ 485 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 486 .val_format_endian = REGMAP_ENDIAN_BIG \ 487 } 488 489 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 490 static const struct regmap_config ksz##_regmap_config[] = { \ 491 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 492 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 493 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 494 } 495 496 #endif 497