1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 18 #include "ksz_ptp.h" 19 20 #define KSZ_MAX_NUM_PORTS 8 21 22 struct ksz_device; 23 struct ksz_port; 24 25 enum ksz_regmap_width { 26 KSZ_REGMAP_8, 27 KSZ_REGMAP_16, 28 KSZ_REGMAP_32, 29 __KSZ_NUM_REGMAPS, 30 }; 31 32 struct vlan_table { 33 u32 table[3]; 34 }; 35 36 struct ksz_port_mib { 37 struct mutex cnt_mutex; /* structure access */ 38 u8 cnt_ptr; 39 u64 *counters; 40 struct rtnl_link_stats64 stats64; 41 struct ethtool_pause_stats pause_stats; 42 struct spinlock stats64_lock; 43 }; 44 45 struct ksz_mib_names { 46 int index; 47 char string[ETH_GSTRING_LEN]; 48 }; 49 50 struct ksz_chip_data { 51 u32 chip_id; 52 const char *dev_name; 53 int num_vlans; 54 int num_alus; 55 int num_statics; 56 int cpu_ports; 57 int port_cnt; 58 u8 port_nirqs; 59 u8 num_tx_queues; 60 bool tc_cbs_supported; 61 bool tc_ets_supported; 62 const struct ksz_dev_ops *ops; 63 bool ksz87xx_eee_link_erratum; 64 const struct ksz_mib_names *mib_names; 65 int mib_cnt; 66 u8 reg_mib_cnt; 67 const u16 *regs; 68 const u32 *masks; 69 const u8 *shifts; 70 const u8 *xmii_ctrl0; 71 const u8 *xmii_ctrl1; 72 int stp_ctrl_reg; 73 int broadcast_ctrl_reg; 74 int multicast_ctrl_reg; 75 int start_ctrl_reg; 76 bool supports_mii[KSZ_MAX_NUM_PORTS]; 77 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 78 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 79 bool internal_phy[KSZ_MAX_NUM_PORTS]; 80 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 81 const struct regmap_access_table *wr_table; 82 const struct regmap_access_table *rd_table; 83 }; 84 85 struct ksz_irq { 86 u16 masked; 87 u16 reg_mask; 88 u16 reg_status; 89 struct irq_domain *domain; 90 int nirqs; 91 int irq_num; 92 char name[16]; 93 struct ksz_device *dev; 94 }; 95 96 struct ksz_ptp_irq { 97 struct ksz_port *port; 98 u16 ts_reg; 99 bool ts_en; 100 char name[16]; 101 int num; 102 }; 103 104 struct ksz_switch_macaddr { 105 unsigned char addr[ETH_ALEN]; 106 refcount_t refcount; 107 }; 108 109 struct ksz_port { 110 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 111 bool learning; 112 int stp_state; 113 struct phy_device phydev; 114 115 u32 fiber:1; /* port is fiber */ 116 u32 force:1; 117 u32 read:1; /* read MIB counters in background */ 118 u32 freeze:1; /* MIB counter freeze is enabled */ 119 120 struct ksz_port_mib mib; 121 phy_interface_t interface; 122 u32 rgmii_tx_val; 123 u32 rgmii_rx_val; 124 struct ksz_device *ksz_dev; 125 void *acl_priv; 126 struct ksz_irq pirq; 127 u8 num; 128 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 129 struct hwtstamp_config tstamp_config; 130 bool hwts_tx_en; 131 bool hwts_rx_en; 132 struct ksz_irq ptpirq; 133 struct ksz_ptp_irq ptpmsg_irq[3]; 134 ktime_t tstamp_msg; 135 struct completion tstamp_msg_comp; 136 #endif 137 bool manual_flow; 138 }; 139 140 struct ksz_device { 141 struct dsa_switch *ds; 142 struct ksz_platform_data *pdata; 143 const struct ksz_chip_data *info; 144 145 struct mutex dev_mutex; /* device access */ 146 struct mutex regmap_mutex; /* regmap access */ 147 struct mutex alu_mutex; /* ALU access */ 148 struct mutex vlan_mutex; /* vlan access */ 149 const struct ksz_dev_ops *dev_ops; 150 151 struct device *dev; 152 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 153 154 void *priv; 155 int irq; 156 157 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 158 159 /* chip specific data */ 160 u32 chip_id; 161 u8 chip_rev; 162 int cpu_port; /* port connected to CPU */ 163 int phy_port_cnt; 164 phy_interface_t compat_interface; 165 bool synclko_125; 166 bool synclko_disable; 167 bool wakeup_source; 168 169 struct vlan_table *vlan_cache; 170 171 struct ksz_port *ports; 172 struct delayed_work mib_read; 173 unsigned long mib_read_interval; 174 u16 mirror_rx; 175 u16 mirror_tx; 176 u16 port_mask; 177 struct mutex lock_irq; /* IRQ Access */ 178 struct ksz_irq girq; 179 struct ksz_ptp_data ptp_data; 180 181 struct ksz_switch_macaddr *switch_macaddr; 182 struct net_device *hsr_dev; /* HSR */ 183 u8 hsr_ports; 184 }; 185 186 /* List of supported models */ 187 enum ksz_model { 188 KSZ8563, 189 KSZ8795, 190 KSZ8794, 191 KSZ8765, 192 KSZ8830, 193 KSZ9477, 194 KSZ9896, 195 KSZ9897, 196 KSZ9893, 197 KSZ9563, 198 KSZ9567, 199 LAN9370, 200 LAN9371, 201 LAN9372, 202 LAN9373, 203 LAN9374, 204 }; 205 206 enum ksz_chip_id { 207 KSZ8563_CHIP_ID = 0x8563, 208 KSZ8795_CHIP_ID = 0x8795, 209 KSZ8794_CHIP_ID = 0x8794, 210 KSZ8765_CHIP_ID = 0x8765, 211 KSZ8830_CHIP_ID = 0x8830, 212 KSZ9477_CHIP_ID = 0x00947700, 213 KSZ9896_CHIP_ID = 0x00989600, 214 KSZ9897_CHIP_ID = 0x00989700, 215 KSZ9893_CHIP_ID = 0x00989300, 216 KSZ9563_CHIP_ID = 0x00956300, 217 KSZ9567_CHIP_ID = 0x00956700, 218 LAN9370_CHIP_ID = 0x00937000, 219 LAN9371_CHIP_ID = 0x00937100, 220 LAN9372_CHIP_ID = 0x00937200, 221 LAN9373_CHIP_ID = 0x00937300, 222 LAN9374_CHIP_ID = 0x00937400, 223 }; 224 225 enum ksz_regs { 226 REG_SW_MAC_ADDR, 227 REG_IND_CTRL_0, 228 REG_IND_DATA_8, 229 REG_IND_DATA_CHECK, 230 REG_IND_DATA_HI, 231 REG_IND_DATA_LO, 232 REG_IND_MIB_CHECK, 233 REG_IND_BYTE, 234 P_FORCE_CTRL, 235 P_LINK_STATUS, 236 P_LOCAL_CTRL, 237 P_NEG_RESTART_CTRL, 238 P_REMOTE_STATUS, 239 P_SPEED_STATUS, 240 S_TAIL_TAG_CTRL, 241 P_STP_CTRL, 242 S_START_CTRL, 243 S_BROADCAST_CTRL, 244 S_MULTICAST_CTRL, 245 P_XMII_CTRL_0, 246 P_XMII_CTRL_1, 247 }; 248 249 enum ksz_masks { 250 PORT_802_1P_REMAPPING, 251 SW_TAIL_TAG_ENABLE, 252 MIB_COUNTER_OVERFLOW, 253 MIB_COUNTER_VALID, 254 VLAN_TABLE_FID, 255 VLAN_TABLE_MEMBERSHIP, 256 VLAN_TABLE_VALID, 257 STATIC_MAC_TABLE_VALID, 258 STATIC_MAC_TABLE_USE_FID, 259 STATIC_MAC_TABLE_FID, 260 STATIC_MAC_TABLE_OVERRIDE, 261 STATIC_MAC_TABLE_FWD_PORTS, 262 DYNAMIC_MAC_TABLE_ENTRIES_H, 263 DYNAMIC_MAC_TABLE_MAC_EMPTY, 264 DYNAMIC_MAC_TABLE_NOT_READY, 265 DYNAMIC_MAC_TABLE_ENTRIES, 266 DYNAMIC_MAC_TABLE_FID, 267 DYNAMIC_MAC_TABLE_SRC_PORT, 268 DYNAMIC_MAC_TABLE_TIMESTAMP, 269 ALU_STAT_WRITE, 270 ALU_STAT_READ, 271 P_MII_TX_FLOW_CTRL, 272 P_MII_RX_FLOW_CTRL, 273 }; 274 275 enum ksz_shifts { 276 VLAN_TABLE_MEMBERSHIP_S, 277 VLAN_TABLE, 278 STATIC_MAC_FWD_PORTS, 279 STATIC_MAC_FID, 280 DYNAMIC_MAC_ENTRIES_H, 281 DYNAMIC_MAC_ENTRIES, 282 DYNAMIC_MAC_FID, 283 DYNAMIC_MAC_TIMESTAMP, 284 DYNAMIC_MAC_SRC_PORT, 285 ALU_STAT_INDEX, 286 }; 287 288 enum ksz_xmii_ctrl0 { 289 P_MII_100MBIT, 290 P_MII_10MBIT, 291 P_MII_FULL_DUPLEX, 292 P_MII_HALF_DUPLEX, 293 }; 294 295 enum ksz_xmii_ctrl1 { 296 P_RGMII_SEL, 297 P_RMII_SEL, 298 P_GMII_SEL, 299 P_MII_SEL, 300 P_GMII_1GBIT, 301 P_GMII_NOT_1GBIT, 302 }; 303 304 struct alu_struct { 305 /* entry 1 */ 306 u8 is_static:1; 307 u8 is_src_filter:1; 308 u8 is_dst_filter:1; 309 u8 prio_age:3; 310 u32 _reserv_0_1:23; 311 u8 mstp:3; 312 /* entry 2 */ 313 u8 is_override:1; 314 u8 is_use_fid:1; 315 u32 _reserv_1_1:23; 316 u8 port_forward:7; 317 /* entry 3 & 4*/ 318 u32 _reserv_2_1:9; 319 u8 fid:7; 320 u8 mac[ETH_ALEN]; 321 }; 322 323 struct ksz_dev_ops { 324 int (*setup)(struct dsa_switch *ds); 325 void (*teardown)(struct dsa_switch *ds); 326 u32 (*get_port_addr)(int port, int offset); 327 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 328 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 329 void (*port_cleanup)(struct ksz_device *dev, int port); 330 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 331 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 332 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 333 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 334 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 335 u64 *cnt); 336 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 337 u64 *dropped, u64 *cnt); 338 void (*r_mib_stat64)(struct ksz_device *dev, int port); 339 int (*vlan_filtering)(struct ksz_device *dev, int port, 340 bool flag, struct netlink_ext_ack *extack); 341 int (*vlan_add)(struct ksz_device *dev, int port, 342 const struct switchdev_obj_port_vlan *vlan, 343 struct netlink_ext_ack *extack); 344 int (*vlan_del)(struct ksz_device *dev, int port, 345 const struct switchdev_obj_port_vlan *vlan); 346 int (*mirror_add)(struct ksz_device *dev, int port, 347 struct dsa_mall_mirror_tc_entry *mirror, 348 bool ingress, struct netlink_ext_ack *extack); 349 void (*mirror_del)(struct ksz_device *dev, int port, 350 struct dsa_mall_mirror_tc_entry *mirror); 351 int (*fdb_add)(struct ksz_device *dev, int port, 352 const unsigned char *addr, u16 vid, struct dsa_db db); 353 int (*fdb_del)(struct ksz_device *dev, int port, 354 const unsigned char *addr, u16 vid, struct dsa_db db); 355 int (*fdb_dump)(struct ksz_device *dev, int port, 356 dsa_fdb_dump_cb_t *cb, void *data); 357 int (*mdb_add)(struct ksz_device *dev, int port, 358 const struct switchdev_obj_port_mdb *mdb, 359 struct dsa_db db); 360 int (*mdb_del)(struct ksz_device *dev, int port, 361 const struct switchdev_obj_port_mdb *mdb, 362 struct dsa_db db); 363 void (*get_caps)(struct ksz_device *dev, int port, 364 struct phylink_config *config); 365 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 366 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 367 void (*port_init_cnt)(struct ksz_device *dev, int port); 368 void (*phylink_mac_config)(struct ksz_device *dev, int port, 369 unsigned int mode, 370 const struct phylink_link_state *state); 371 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 372 unsigned int mode, 373 phy_interface_t interface, 374 struct phy_device *phydev, int speed, 375 int duplex, bool tx_pause, bool rx_pause); 376 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 377 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 378 void (*get_wol)(struct ksz_device *dev, int port, 379 struct ethtool_wolinfo *wol); 380 int (*set_wol)(struct ksz_device *dev, int port, 381 struct ethtool_wolinfo *wol); 382 void (*wol_pre_shutdown)(struct ksz_device *dev, bool *wol_enabled); 383 void (*config_cpu_port)(struct dsa_switch *ds); 384 int (*enable_stp_addr)(struct ksz_device *dev); 385 int (*reset)(struct ksz_device *dev); 386 int (*init)(struct ksz_device *dev); 387 void (*exit)(struct ksz_device *dev); 388 }; 389 390 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 391 int ksz_switch_register(struct ksz_device *dev); 392 void ksz_switch_remove(struct ksz_device *dev); 393 394 void ksz_init_mib_timer(struct ksz_device *dev); 395 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port); 396 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 397 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 398 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 399 bool ksz_get_gbit(struct ksz_device *dev, int port); 400 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 401 extern const struct ksz_chip_data ksz_switch_chips[]; 402 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 403 struct netlink_ext_ack *extack); 404 void ksz_switch_macaddr_put(struct dsa_switch *ds); 405 void ksz_switch_shutdown(struct ksz_device *dev); 406 407 /* Common register access functions */ 408 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 409 { 410 return dev->regmap[KSZ_REGMAP_8]; 411 } 412 413 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 414 { 415 return dev->regmap[KSZ_REGMAP_16]; 416 } 417 418 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 419 { 420 return dev->regmap[KSZ_REGMAP_32]; 421 } 422 423 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 424 { 425 unsigned int value; 426 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 427 428 if (ret) 429 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 430 ERR_PTR(ret)); 431 432 *val = value; 433 return ret; 434 } 435 436 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 437 { 438 unsigned int value; 439 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 440 441 if (ret) 442 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 443 ERR_PTR(ret)); 444 445 *val = value; 446 return ret; 447 } 448 449 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 450 { 451 unsigned int value; 452 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 453 454 if (ret) 455 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 456 ERR_PTR(ret)); 457 458 *val = value; 459 return ret; 460 } 461 462 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 463 { 464 u32 value[2]; 465 int ret; 466 467 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 468 if (ret) 469 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 470 ERR_PTR(ret)); 471 else 472 *val = (u64)value[0] << 32 | value[1]; 473 474 return ret; 475 } 476 477 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 478 { 479 int ret; 480 481 ret = regmap_write(ksz_regmap_8(dev), reg, value); 482 if (ret) 483 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 484 ERR_PTR(ret)); 485 486 return ret; 487 } 488 489 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 490 { 491 int ret; 492 493 ret = regmap_write(ksz_regmap_16(dev), reg, value); 494 if (ret) 495 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 496 ERR_PTR(ret)); 497 498 return ret; 499 } 500 501 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 502 { 503 int ret; 504 505 ret = regmap_write(ksz_regmap_32(dev), reg, value); 506 if (ret) 507 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 508 ERR_PTR(ret)); 509 510 return ret; 511 } 512 513 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 514 u16 value) 515 { 516 int ret; 517 518 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 519 if (ret) 520 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 521 ERR_PTR(ret)); 522 523 return ret; 524 } 525 526 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 527 u32 value) 528 { 529 int ret; 530 531 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 532 if (ret) 533 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 534 ERR_PTR(ret)); 535 536 return ret; 537 } 538 539 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 540 { 541 u32 val[2]; 542 543 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 544 value = swab64(value); 545 val[0] = swab32(value & 0xffffffffULL); 546 val[1] = swab32(value >> 32ULL); 547 548 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 549 } 550 551 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 552 { 553 int ret; 554 555 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 556 if (ret) 557 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 558 ERR_PTR(ret)); 559 560 return ret; 561 } 562 563 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 564 u8 *data) 565 { 566 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 567 } 568 569 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 570 u16 *data) 571 { 572 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 573 } 574 575 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 576 u32 *data) 577 { 578 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 579 } 580 581 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 582 u8 data) 583 { 584 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 585 } 586 587 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 588 u16 data) 589 { 590 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 591 data); 592 } 593 594 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 595 u32 data) 596 { 597 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 598 data); 599 } 600 601 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 602 u8 mask, u8 val) 603 { 604 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 605 mask, val); 606 } 607 608 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 609 u32 mask, u32 val) 610 { 611 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 612 mask, val); 613 } 614 615 static inline void ksz_regmap_lock(void *__mtx) 616 { 617 struct mutex *mtx = __mtx; 618 mutex_lock(mtx); 619 } 620 621 static inline void ksz_regmap_unlock(void *__mtx) 622 { 623 struct mutex *mtx = __mtx; 624 mutex_unlock(mtx); 625 } 626 627 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 628 { 629 return dev->chip_id == KSZ8795_CHIP_ID || 630 dev->chip_id == KSZ8794_CHIP_ID || 631 dev->chip_id == KSZ8765_CHIP_ID; 632 } 633 634 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 635 { 636 return dev->chip_id == KSZ8830_CHIP_ID; 637 } 638 639 static inline int is_lan937x(struct ksz_device *dev) 640 { 641 return dev->chip_id == LAN9370_CHIP_ID || 642 dev->chip_id == LAN9371_CHIP_ID || 643 dev->chip_id == LAN9372_CHIP_ID || 644 dev->chip_id == LAN9373_CHIP_ID || 645 dev->chip_id == LAN9374_CHIP_ID; 646 } 647 648 /* STP State Defines */ 649 #define PORT_TX_ENABLE BIT(2) 650 #define PORT_RX_ENABLE BIT(1) 651 #define PORT_LEARN_DISABLE BIT(0) 652 653 /* Switch ID Defines */ 654 #define REG_CHIP_ID0 0x00 655 656 #define SW_FAMILY_ID_M GENMASK(15, 8) 657 #define KSZ87_FAMILY_ID 0x87 658 #define KSZ88_FAMILY_ID 0x88 659 660 #define KSZ8_PORT_STATUS_0 0x08 661 #define KSZ8_PORT_FIBER_MODE BIT(7) 662 663 #define SW_CHIP_ID_M GENMASK(7, 4) 664 #define KSZ87_CHIP_ID_94 0x6 665 #define KSZ87_CHIP_ID_95 0x9 666 #define KSZ88_CHIP_ID_63 0x3 667 668 #define SW_REV_ID_M GENMASK(7, 4) 669 670 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 671 #define REG_CHIP_ID4 0x0f 672 #define SKU_ID_KSZ8563 0x3c 673 #define SKU_ID_KSZ9563 0x1c 674 675 /* Driver set switch broadcast storm protection at 10% rate. */ 676 #define BROADCAST_STORM_PROT_RATE 10 677 678 /* 148,800 frames * 67 ms / 100 */ 679 #define BROADCAST_STORM_VALUE 9969 680 681 #define BROADCAST_STORM_RATE_HI 0x07 682 #define BROADCAST_STORM_RATE_LO 0xFF 683 #define BROADCAST_STORM_RATE 0x07FF 684 685 #define MULTICAST_STORM_DISABLE BIT(6) 686 687 #define SW_START 0x01 688 689 /* xMII configuration */ 690 #define P_MII_DUPLEX_M BIT(6) 691 #define P_MII_100MBIT_M BIT(4) 692 693 #define P_GMII_1GBIT_M BIT(6) 694 #define P_RGMII_ID_IG_ENABLE BIT(4) 695 #define P_RGMII_ID_EG_ENABLE BIT(3) 696 #define P_MII_MAC_MODE BIT(2) 697 #define P_MII_SEL_M 0x3 698 699 /* Interrupt */ 700 #define REG_SW_PORT_INT_STATUS__1 0x001B 701 #define REG_SW_PORT_INT_MASK__1 0x001F 702 703 #define REG_PORT_INT_STATUS 0x001B 704 #define REG_PORT_INT_MASK 0x001F 705 706 #define PORT_SRC_PHY_INT 1 707 #define PORT_SRC_PTP_INT 2 708 709 #define KSZ8795_HUGE_PACKET_SIZE 2000 710 #define KSZ8863_HUGE_PACKET_SIZE 1916 711 #define KSZ8863_NORMAL_PACKET_SIZE 1536 712 #define KSZ8_LEGAL_PACKET_SIZE 1518 713 #define KSZ9477_MAX_FRAME_SIZE 9000 714 715 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 716 /* Drive Strength of I/O Pad 717 * 0: 8mA, 1: 16mA 718 */ 719 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 720 721 #define KSZ8795_REG_SW_CTRL_20 0xa3 722 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 723 #define SW_DRIVE_STRENGTH_M 0x7 724 #define SW_DRIVE_STRENGTH_2MA 0 725 #define SW_DRIVE_STRENGTH_4MA 1 726 #define SW_DRIVE_STRENGTH_8MA 2 727 #define SW_DRIVE_STRENGTH_12MA 3 728 #define SW_DRIVE_STRENGTH_16MA 4 729 #define SW_DRIVE_STRENGTH_20MA 5 730 #define SW_DRIVE_STRENGTH_24MA 6 731 #define SW_DRIVE_STRENGTH_28MA 7 732 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 733 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 734 735 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 736 #define KSZ9477_OUT_RATE_NO_LIMIT 0 737 738 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 739 740 #define KSZ9477_PORT_TC_MAP_S 4 741 #define KSZ9477_MAX_TC_PRIO 7 742 743 /* CBS related registers */ 744 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 745 746 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 747 748 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 749 #define MTI_SCHEDULE_STRICT_PRIO 0 750 #define MTI_SCHEDULE_WRR 2 751 #define MTI_SHAPING_M GENMASK(5, 4) 752 #define MTI_SHAPING_OFF 0 753 #define MTI_SHAPING_SRP 1 754 #define MTI_SHAPING_TIME_AWARE 2 755 756 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 757 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 758 759 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 760 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 761 762 /* Regmap tables generation */ 763 #define KSZ_SPI_OP_RD 3 764 #define KSZ_SPI_OP_WR 2 765 766 #define swabnot_used(x) 0 767 768 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 769 swab##swp((opcode) << ((regbits) + (regpad))) 770 771 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 772 { \ 773 .name = #width, \ 774 .val_bits = (width), \ 775 .reg_stride = 1, \ 776 .reg_bits = (regbits) + (regalign), \ 777 .pad_bits = (regpad), \ 778 .max_register = BIT(regbits) - 1, \ 779 .cache_type = REGCACHE_NONE, \ 780 .read_flag_mask = \ 781 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 782 regbits, regpad), \ 783 .write_flag_mask = \ 784 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 785 regbits, regpad), \ 786 .lock = ksz_regmap_lock, \ 787 .unlock = ksz_regmap_unlock, \ 788 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 789 .val_format_endian = REGMAP_ENDIAN_BIG \ 790 } 791 792 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 793 static const struct regmap_config ksz##_regmap_config[] = { \ 794 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 795 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 796 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 797 } 798 799 #endif 800