1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2025 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/pcs/pcs-xpcs.h> 14 #include <linux/phy.h> 15 #include <linux/regmap.h> 16 #include <net/dsa.h> 17 #include <linux/irq.h> 18 #include <linux/platform_data/microchip-ksz.h> 19 20 #include "ksz_ptp.h" 21 22 #define KSZ_MAX_NUM_PORTS 8 23 /* all KSZ switches count ports from 1 */ 24 #define KSZ_PORT_1 0 25 #define KSZ_PORT_2 1 26 #define KSZ_PORT_4 3 27 28 struct ksz_device; 29 struct ksz_port; 30 struct phylink_mac_ops; 31 32 enum ksz_regmap_width { 33 KSZ_REGMAP_8, 34 KSZ_REGMAP_16, 35 KSZ_REGMAP_32, 36 __KSZ_NUM_REGMAPS, 37 }; 38 39 struct vlan_table { 40 u32 table[3]; 41 }; 42 43 struct ksz_port_mib { 44 struct mutex cnt_mutex; /* structure access */ 45 u8 cnt_ptr; 46 u64 *counters; 47 struct rtnl_link_stats64 stats64; 48 struct ethtool_pause_stats pause_stats; 49 struct spinlock stats64_lock; 50 }; 51 52 struct ksz_mib_names { 53 int index; 54 char string[ETH_GSTRING_LEN]; 55 }; 56 57 struct ksz_chip_data { 58 u32 chip_id; 59 const char *dev_name; 60 int num_vlans; 61 int num_alus; 62 int num_statics; 63 int cpu_ports; 64 int port_cnt; 65 u8 port_nirqs; 66 u8 num_tx_queues; 67 u8 num_ipms; /* number of Internal Priority Maps */ 68 bool tc_cbs_supported; 69 70 /** 71 * @phy_side_mdio_supported: Indicates if the chip supports an additional 72 * side MDIO channel for accessing integrated PHYs. 73 */ 74 bool phy_side_mdio_supported; 75 const struct ksz_dev_ops *ops; 76 const struct dsa_switch_ops *switch_ops; 77 const struct phylink_mac_ops *phylink_mac_ops; 78 bool phy_errata_9477; 79 bool ksz87xx_eee_link_erratum; 80 const struct ksz_mib_names *mib_names; 81 int mib_cnt; 82 u8 reg_mib_cnt; 83 const u16 *regs; 84 const u32 *masks; 85 const u8 *shifts; 86 const u8 *xmii_ctrl0; 87 const u8 *xmii_ctrl1; 88 int stp_ctrl_reg; 89 int broadcast_ctrl_reg; 90 int multicast_ctrl_reg; 91 int start_ctrl_reg; 92 bool supports_mii[KSZ_MAX_NUM_PORTS]; 93 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 94 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 95 bool internal_phy[KSZ_MAX_NUM_PORTS]; 96 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 97 bool ptp_capable; 98 u8 sgmii_port; 99 const struct regmap_access_table *wr_table; 100 const struct regmap_access_table *rd_table; 101 }; 102 103 struct ksz_irq { 104 u16 masked; 105 u16 reg_mask; 106 u16 reg_status; 107 struct irq_domain *domain; 108 int nirqs; 109 int irq_num; 110 char name[16]; 111 struct ksz_device *dev; 112 u16 irq0_offset; 113 }; 114 115 struct ksz_ptp_irq { 116 struct ksz_port *port; 117 u16 ts_reg; 118 bool ts_en; 119 char name[16]; 120 int num; 121 }; 122 123 struct ksz_switch_macaddr { 124 unsigned char addr[ETH_ALEN]; 125 refcount_t refcount; 126 }; 127 128 struct ksz_port { 129 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 130 bool learning; 131 bool isolated; 132 int stp_state; 133 int speed; 134 int duplex; 135 bool link; 136 137 u32 fiber:1; /* port is fiber */ 138 u32 force:1; 139 u32 read:1; /* read MIB counters in background */ 140 u32 freeze:1; /* MIB counter freeze is enabled */ 141 u32 sgmii_adv_write:1; 142 143 struct ksz_port_mib mib; 144 phy_interface_t interface; 145 u32 rgmii_tx_val; 146 u32 rgmii_rx_val; 147 struct ksz_device *ksz_dev; 148 void *acl_priv; 149 struct ksz_irq pirq; 150 u8 num; 151 struct phylink_pcs *pcs; 152 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 153 struct kernel_hwtstamp_config tstamp_config; 154 bool hwts_tx_en; 155 bool hwts_rx_en; 156 struct ksz_irq ptpirq; 157 struct ksz_ptp_irq ptpmsg_irq[3]; 158 ktime_t tstamp_msg; 159 struct completion tstamp_msg_comp; 160 #endif 161 bool manual_flow; 162 }; 163 164 struct ksz_device { 165 struct dsa_switch *ds; 166 struct ksz_platform_data *pdata; 167 const struct ksz_chip_data *info; 168 169 struct mutex dev_mutex; /* device access */ 170 struct mutex regmap_mutex; /* regmap access */ 171 struct mutex alu_mutex; /* ALU access */ 172 struct mutex vlan_mutex; /* vlan access */ 173 const struct ksz_dev_ops *dev_ops; 174 175 struct device *dev; 176 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 177 178 void *priv; 179 int irq; 180 181 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 182 183 /* chip specific data */ 184 u32 chip_id; 185 u8 chip_rev; 186 int cpu_port; /* port connected to CPU */ 187 int phy_port_cnt; 188 phy_interface_t compat_interface; 189 bool synclko_125; 190 bool synclko_disable; 191 bool wakeup_source; 192 bool pme_active_high; 193 194 struct vlan_table *vlan_cache; 195 196 struct ksz_port *ports; 197 struct delayed_work mib_read; 198 unsigned long mib_read_interval; 199 u16 mirror_rx; 200 u16 mirror_tx; 201 u16 port_mask; 202 struct mutex lock_irq; /* IRQ Access */ 203 struct ksz_irq girq; 204 struct ksz_ptp_data ptp_data; 205 206 struct ksz_switch_macaddr *switch_macaddr; 207 struct net_device *hsr_dev; /* HSR */ 208 u8 hsr_ports; 209 210 /** 211 * @phy_addr_map: Array mapping switch ports to their corresponding PHY 212 * addresses. 213 */ 214 u8 phy_addr_map[KSZ_MAX_NUM_PORTS]; 215 216 /** 217 * @parent_mdio_bus: Pointer to the external MDIO bus controller. 218 * 219 * This points to an external MDIO bus controller that is used to access 220 * the PHYs integrated within the switch. Unlike an integrated MDIO 221 * bus, this external controller provides a direct path for managing 222 * the switch’s internal PHYs, bypassing the main SPI interface. 223 */ 224 struct mii_bus *parent_mdio_bus; 225 }; 226 227 /* List of supported models */ 228 enum ksz_model { 229 KSZ8463, 230 KSZ8563, 231 KSZ8567, 232 KSZ8795, 233 KSZ8794, 234 KSZ8765, 235 KSZ88X3, 236 KSZ8864, 237 KSZ8895, 238 KSZ9477, 239 KSZ9896, 240 KSZ9897, 241 KSZ9893, 242 KSZ9563, 243 KSZ9567, 244 LAN9370, 245 LAN9371, 246 LAN9372, 247 LAN9373, 248 LAN9374, 249 LAN9646, 250 }; 251 252 enum ksz_regs { 253 REG_SW_MAC_ADDR, 254 REG_IND_CTRL_0, 255 REG_IND_DATA_8, 256 REG_IND_DATA_CHECK, 257 REG_IND_DATA_HI, 258 REG_IND_DATA_LO, 259 REG_IND_MIB_CHECK, 260 REG_IND_BYTE, 261 P_FORCE_CTRL, 262 P_LINK_STATUS, 263 P_LOCAL_CTRL, 264 P_NEG_RESTART_CTRL, 265 P_REMOTE_STATUS, 266 P_SPEED_STATUS, 267 S_TAIL_TAG_CTRL, 268 P_STP_CTRL, 269 S_START_CTRL, 270 S_BROADCAST_CTRL, 271 S_MULTICAST_CTRL, 272 P_XMII_CTRL_0, 273 P_XMII_CTRL_1, 274 REG_SW_PME_CTRL, 275 REG_PORT_PME_STATUS, 276 REG_PORT_PME_CTRL, 277 PTP_CLK_CTRL, 278 PTP_RTC_NANOSEC, 279 PTP_RTC_SEC, 280 PTP_RTC_SUB_NANOSEC, 281 PTP_SUBNANOSEC_RATE, 282 PTP_MSG_CONF1, 283 }; 284 285 enum ksz_masks { 286 PORT_802_1P_REMAPPING, 287 SW_TAIL_TAG_ENABLE, 288 MIB_COUNTER_OVERFLOW, 289 MIB_COUNTER_VALID, 290 VLAN_TABLE_FID, 291 VLAN_TABLE_MEMBERSHIP, 292 VLAN_TABLE_VALID, 293 STATIC_MAC_TABLE_VALID, 294 STATIC_MAC_TABLE_USE_FID, 295 STATIC_MAC_TABLE_FID, 296 STATIC_MAC_TABLE_OVERRIDE, 297 STATIC_MAC_TABLE_FWD_PORTS, 298 DYNAMIC_MAC_TABLE_ENTRIES_H, 299 DYNAMIC_MAC_TABLE_MAC_EMPTY, 300 DYNAMIC_MAC_TABLE_NOT_READY, 301 DYNAMIC_MAC_TABLE_ENTRIES, 302 DYNAMIC_MAC_TABLE_FID, 303 DYNAMIC_MAC_TABLE_SRC_PORT, 304 DYNAMIC_MAC_TABLE_TIMESTAMP, 305 ALU_STAT_WRITE, 306 ALU_STAT_READ, 307 ALU_STAT_DIRECT, 308 ALU_RESV_MCAST_ADDR, 309 P_MII_TX_FLOW_CTRL, 310 P_MII_RX_FLOW_CTRL, 311 }; 312 313 enum ksz_shifts { 314 VLAN_TABLE_MEMBERSHIP_S, 315 VLAN_TABLE, 316 STATIC_MAC_FWD_PORTS, 317 STATIC_MAC_FID, 318 DYNAMIC_MAC_ENTRIES_H, 319 DYNAMIC_MAC_ENTRIES, 320 DYNAMIC_MAC_FID, 321 DYNAMIC_MAC_TIMESTAMP, 322 DYNAMIC_MAC_SRC_PORT, 323 ALU_STAT_INDEX, 324 }; 325 326 enum ksz_xmii_ctrl0 { 327 P_MII_100MBIT, 328 P_MII_10MBIT, 329 P_MII_FULL_DUPLEX, 330 P_MII_HALF_DUPLEX, 331 }; 332 333 enum ksz_xmii_ctrl1 { 334 P_RGMII_SEL, 335 P_RMII_SEL, 336 P_GMII_SEL, 337 P_MII_SEL, 338 P_GMII_1GBIT, 339 P_GMII_NOT_1GBIT, 340 }; 341 342 struct alu_struct { 343 /* entry 1 */ 344 u8 is_static:1; 345 u8 is_src_filter:1; 346 u8 is_dst_filter:1; 347 u8 prio_age:3; 348 u32 _reserv_0_1:23; 349 u8 mstp:3; 350 /* entry 2 */ 351 u8 is_override:1; 352 u8 is_use_fid:1; 353 u32 _reserv_1_1:23; 354 u8 port_forward:7; 355 /* entry 3 & 4*/ 356 u32 _reserv_2_1:9; 357 u8 fid:7; 358 u8 mac[ETH_ALEN]; 359 }; 360 361 struct ksz_dev_ops { 362 u32 (*get_port_addr)(int port, int offset); 363 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 364 365 /** 366 * @mdio_bus_preinit: Function pointer to pre-initialize the MDIO bus 367 * for accessing PHYs. 368 * @dev: Pointer to device structure. 369 * @side_mdio: Boolean indicating if the PHYs are accessed over a side 370 * MDIO bus. 371 * 372 * This function pointer is used to configure the MDIO bus for PHY 373 * access before initiating regular PHY operations. It enables either 374 * SPI/I2C or side MDIO access modes by unlocking necessary registers 375 * and setting up access permissions for the selected mode. 376 * 377 * Return: 378 * - 0 on success. 379 * - Negative error code on failure. 380 */ 381 int (*mdio_bus_preinit)(struct ksz_device *dev, bool side_mdio); 382 383 /** 384 * @create_phy_addr_map: Function pointer to create a port-to-PHY 385 * address map. 386 * @dev: Pointer to device structure. 387 * @side_mdio: Boolean indicating if the PHYs are accessed over a side 388 * MDIO bus. 389 * 390 * This function pointer is responsible for mapping switch ports to PHY 391 * addresses according to the configured access mode (SPI or side MDIO) 392 * and the device’s strap configuration. The mapping setup may vary 393 * depending on the chip variant and configuration. Ensures the correct 394 * address mapping for PHY communication. 395 * 396 * Return: 397 * - 0 on success. 398 * - Negative error code on failure (e.g., invalid configuration). 399 */ 400 int (*create_phy_addr_map)(struct ksz_device *dev, bool side_mdio); 401 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 402 u64 *cnt); 403 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 404 u64 *dropped, u64 *cnt); 405 void (*r_mib_stat64)(struct ksz_device *dev, int port); 406 int (*pme_write8)(struct ksz_device *dev, u32 reg, u8 value); 407 int (*pme_pread8)(struct ksz_device *dev, int port, int offset, 408 u8 *data); 409 int (*pme_pwrite8)(struct ksz_device *dev, int port, int offset, 410 u8 data); 411 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 412 void (*port_init_cnt)(struct ksz_device *dev, int port); 413 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 414 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 415 int (*init)(struct ksz_device *dev); 416 }; 417 418 struct ksz_device *ksz_switch_alloc(struct device *base, 419 const struct ksz_chip_data *chip, 420 void *priv); 421 int ksz_switch_register(struct ksz_device *dev); 422 void ksz_switch_remove(struct ksz_device *dev); 423 int ksz_switch_suspend(struct device *dev); 424 int ksz_switch_resume(struct device *dev); 425 426 void ksz_teardown(struct dsa_switch *ds); 427 void ksz_port_teardown(struct dsa_switch *ds, int port); 428 429 void ksz_init_mib_timer(struct ksz_device *dev); 430 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port); 431 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 432 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 433 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 434 bool ksz_get_gbit(struct ksz_device *dev, int port); 435 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 436 extern const struct ksz_chip_data ksz_switch_chips[]; 437 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 438 struct netlink_ext_ack *extack); 439 void ksz_switch_macaddr_put(struct dsa_switch *ds); 440 void ksz_switch_shutdown(struct ksz_device *dev); 441 int ksz_handle_wake_reason(struct ksz_device *dev, int port); 442 443 u32 ksz_get_phy_flags(struct dsa_switch *ds, int port); 444 445 int ksz_sset_count(struct dsa_switch *ds, int port, int sset); 446 void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 447 uint64_t *buf); 448 void ksz_get_stats64(struct dsa_switch *ds, int port, 449 struct rtnl_link_stats64 *s); 450 void ksz_get_pause_stats(struct dsa_switch *ds, int port, 451 struct ethtool_pause_stats *pause_stats); 452 void ksz_get_strings(struct dsa_switch *ds, int port, 453 u32 stringset, uint8_t *buf); 454 455 int ksz_port_bridge_join(struct dsa_switch *ds, int port, 456 struct dsa_bridge bridge, 457 bool *tx_fwd_offload, 458 struct netlink_ext_ack *extack); 459 void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 460 struct dsa_bridge bridge); 461 int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 462 struct switchdev_brport_flags flags, 463 struct netlink_ext_ack *extack); 464 int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 465 struct switchdev_brport_flags flags, 466 struct netlink_ext_ack *extack); 467 468 void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 469 struct phylink_config *config); 470 void ksz_phylink_mac_disable_tx_lpi(struct phylink_config *config); 471 int ksz_phylink_mac_enable_tx_lpi(struct phylink_config *config, 472 u32 timer, bool tx_clock_stop); 473 void ksz_phylink_mac_config(struct phylink_config *config, 474 unsigned int mode, 475 const struct phylink_link_state *state); 476 void ksz_phylink_mac_link_down(struct phylink_config *config, 477 unsigned int mode, 478 phy_interface_t interface); 479 480 int ksz_max_mtu(struct dsa_switch *ds, int port); 481 482 bool ksz_support_eee(struct dsa_switch *ds, int port); 483 int ksz_set_mac_eee(struct dsa_switch *ds, int port, 484 struct ethtool_keee *e); 485 486 int ksz_cls_flower_add(struct dsa_switch *ds, int port, 487 struct flow_cls_offload *cls, bool ingress); 488 int ksz_cls_flower_del(struct dsa_switch *ds, int port, 489 struct flow_cls_offload *cls, bool ingress); 490 int ksz_setup_tc(struct dsa_switch *ds, int port, 491 enum tc_setup_type type, void *type_data); 492 493 void ksz_get_wol(struct dsa_switch *ds, int port, 494 struct ethtool_wolinfo *wol); 495 int ksz_set_wol(struct dsa_switch *ds, int port, 496 struct ethtool_wolinfo *wol); 497 int ksz_port_set_mac_address(struct dsa_switch *ds, int port, 498 const unsigned char *addr); 499 int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr, 500 struct netlink_ext_ack *extack); 501 int ksz_hsr_leave(struct dsa_switch *ds, int port, 502 struct net_device *hsr); 503 504 int ksz_suspend(struct dsa_switch *ds); 505 int ksz_resume(struct dsa_switch *ds); 506 507 int ksz_mdio_register(struct ksz_device *dev); 508 int ksz_pirq_setup(struct ksz_device *dev, u8 p); 509 int ksz_girq_setup(struct ksz_device *dev); 510 void ksz_irq_free(struct ksz_irq *kirq); 511 int ksz_parse_drive_strength(struct ksz_device *dev); 512 int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev, int port); 513 514 /* Common register access functions */ 515 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 516 { 517 return dev->regmap[KSZ_REGMAP_8]; 518 } 519 520 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 521 { 522 return dev->regmap[KSZ_REGMAP_16]; 523 } 524 525 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 526 { 527 return dev->regmap[KSZ_REGMAP_32]; 528 } 529 530 static inline bool ksz_is_ksz8463(struct ksz_device *dev) 531 { 532 return dev->chip_id == KSZ8463_CHIP_ID; 533 } 534 535 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 536 { 537 unsigned int value; 538 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 539 540 if (ret) 541 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 542 ERR_PTR(ret)); 543 544 *val = value; 545 return ret; 546 } 547 548 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 549 { 550 unsigned int value; 551 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 552 553 if (ret) 554 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 555 ERR_PTR(ret)); 556 557 *val = value; 558 return ret; 559 } 560 561 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 562 { 563 unsigned int value; 564 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 565 566 if (ret) 567 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 568 ERR_PTR(ret)); 569 570 *val = value; 571 return ret; 572 } 573 574 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 575 { 576 u32 value[2]; 577 int ret; 578 579 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 580 if (ret) 581 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 582 ERR_PTR(ret)); 583 else 584 *val = (u64)value[0] << 32 | value[1]; 585 586 return ret; 587 } 588 589 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 590 { 591 int ret; 592 593 ret = regmap_write(ksz_regmap_8(dev), reg, value); 594 if (ret) 595 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 596 ERR_PTR(ret)); 597 598 return ret; 599 } 600 601 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 602 { 603 int ret; 604 605 ret = regmap_write(ksz_regmap_16(dev), reg, value); 606 if (ret) 607 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 608 ERR_PTR(ret)); 609 610 return ret; 611 } 612 613 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 614 { 615 int ret; 616 617 ret = regmap_write(ksz_regmap_32(dev), reg, value); 618 if (ret) 619 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 620 ERR_PTR(ret)); 621 622 return ret; 623 } 624 625 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 626 u16 value) 627 { 628 int ret; 629 630 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 631 if (ret) 632 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 633 ERR_PTR(ret)); 634 635 return ret; 636 } 637 638 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 639 u32 value) 640 { 641 int ret; 642 643 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 644 if (ret) 645 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 646 ERR_PTR(ret)); 647 648 return ret; 649 } 650 651 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 652 { 653 u32 val[2]; 654 655 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 656 value = swab64(value); 657 val[0] = swab32(value & 0xffffffffULL); 658 val[1] = swab32(value >> 32ULL); 659 660 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 661 } 662 663 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 664 { 665 int ret; 666 667 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 668 if (ret) 669 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 670 ERR_PTR(ret)); 671 672 return ret; 673 } 674 675 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 676 u8 *data) 677 { 678 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 679 } 680 681 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 682 u16 *data) 683 { 684 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 685 } 686 687 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 688 u32 *data) 689 { 690 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 691 } 692 693 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 694 u8 data) 695 { 696 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 697 } 698 699 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 700 u16 data) 701 { 702 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 703 data); 704 } 705 706 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 707 u32 data) 708 { 709 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 710 data); 711 } 712 713 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 714 u8 mask, u8 val) 715 { 716 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 717 mask, val); 718 } 719 720 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 721 u32 mask, u32 val) 722 { 723 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 724 mask, val); 725 } 726 727 static inline void ksz_regmap_lock(void *__mtx) 728 { 729 struct mutex *mtx = __mtx; 730 mutex_lock(mtx); 731 } 732 733 static inline void ksz_regmap_unlock(void *__mtx) 734 { 735 struct mutex *mtx = __mtx; 736 mutex_unlock(mtx); 737 } 738 739 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 740 { 741 return dev->chip_id == KSZ8795_CHIP_ID || 742 dev->chip_id == KSZ8794_CHIP_ID || 743 dev->chip_id == KSZ8765_CHIP_ID; 744 } 745 746 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 747 { 748 return dev->chip_id == KSZ88X3_CHIP_ID; 749 } 750 751 static inline bool ksz_is_8895_family(struct ksz_device *dev) 752 { 753 return dev->chip_id == KSZ8895_CHIP_ID || 754 dev->chip_id == KSZ8864_CHIP_ID; 755 } 756 757 static inline bool is_ksz8(struct ksz_device *dev) 758 { 759 return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev) || 760 ksz_is_8895_family(dev) || ksz_is_ksz8463(dev); 761 } 762 763 static inline bool is_ksz88xx(struct ksz_device *dev) 764 { 765 return ksz_is_ksz88x3(dev) || ksz_is_8895_family(dev) || 766 ksz_is_ksz8463(dev); 767 } 768 769 static inline bool is_ksz9477(struct ksz_device *dev) 770 { 771 return dev->chip_id == KSZ9477_CHIP_ID; 772 } 773 774 static inline int is_lan937x(struct ksz_device *dev) 775 { 776 return dev->chip_id == LAN9370_CHIP_ID || 777 dev->chip_id == LAN9371_CHIP_ID || 778 dev->chip_id == LAN9372_CHIP_ID || 779 dev->chip_id == LAN9373_CHIP_ID || 780 dev->chip_id == LAN9374_CHIP_ID; 781 } 782 783 static inline bool is_lan937x_tx_phy(struct ksz_device *dev, int port) 784 { 785 return (dev->chip_id == LAN9371_CHIP_ID || 786 dev->chip_id == LAN9372_CHIP_ID) && port == KSZ_PORT_4; 787 } 788 789 static inline int ksz_get_sgmii_port(struct ksz_device *dev) 790 { 791 return dev->info->sgmii_port - 1; 792 } 793 794 static inline bool ksz_has_sgmii_port(struct ksz_device *dev) 795 { 796 return dev->info->sgmii_port > 0; 797 } 798 799 static inline bool ksz_is_sgmii_port(struct ksz_device *dev, int port) 800 { 801 return dev->info->sgmii_port == port + 1; 802 } 803 804 /* STP State Defines */ 805 #define PORT_TX_ENABLE BIT(2) 806 #define PORT_RX_ENABLE BIT(1) 807 #define PORT_LEARN_DISABLE BIT(0) 808 809 /* Switch ID Defines */ 810 #define REG_CHIP_ID0 0x00 811 812 #define SW_FAMILY_ID_M GENMASK(15, 8) 813 #define KSZ84_FAMILY_ID 0x84 814 #define KSZ87_FAMILY_ID 0x87 815 #define KSZ88_FAMILY_ID 0x88 816 #define KSZ8895_FAMILY_ID 0x95 817 818 #define KSZ8_PORT_STATUS_0 0x08 819 #define KSZ8_PORT_FIBER_MODE BIT(7) 820 821 #define SW_CHIP_ID_M GENMASK(7, 4) 822 #define KSZ87_CHIP_ID_94 0x6 823 #define KSZ87_CHIP_ID_95 0x9 824 #define KSZ88_CHIP_ID_63 0x3 825 #define KSZ8895_CHIP_ID_95 0x4 826 #define KSZ8895_CHIP_ID_95R 0x6 827 828 /* KSZ8895 specific register */ 829 #define REG_KSZ8864_CHIP_ID 0xFE 830 #define SW_KSZ8864 BIT(7) 831 832 #define SW_REV_ID_M GENMASK(7, 4) 833 834 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 835 #define REG_CHIP_ID4 0x0f 836 #define SKU_ID_KSZ8563 0x3c 837 #define SKU_ID_KSZ9563 0x1c 838 839 /* Driver set switch broadcast storm protection at 10% rate. */ 840 #define BROADCAST_STORM_PROT_RATE 10 841 842 /* 148,800 frames * 67 ms / 100 */ 843 #define BROADCAST_STORM_VALUE 9969 844 845 #define BROADCAST_STORM_RATE_HI 0x07 846 #define BROADCAST_STORM_RATE_LO 0xFF 847 #define BROADCAST_STORM_RATE 0x07FF 848 849 #define MULTICAST_STORM_DISABLE BIT(6) 850 851 #define SW_START 0x01 852 853 /* xMII configuration */ 854 #define P_MII_DUPLEX_M BIT(6) 855 #define P_MII_100MBIT_M BIT(4) 856 857 #define P_GMII_1GBIT_M BIT(6) 858 #define P_RGMII_ID_IG_ENABLE BIT(4) 859 #define P_RGMII_ID_EG_ENABLE BIT(3) 860 #define P_MII_MAC_MODE BIT(2) 861 #define P_MII_SEL_M 0x3 862 863 /* KSZ9477, KSZ87xx Wake-on-LAN (WoL) masks */ 864 #define PME_WOL_MAGICPKT BIT(2) 865 #define PME_WOL_LINKUP BIT(1) 866 #define PME_WOL_ENERGY BIT(0) 867 868 #define PME_ENABLE BIT(1) 869 #define PME_POLARITY BIT(0) 870 871 #define KSZ87XX_REG_INT_EN 0x7D 872 #define KSZ87XX_INT_PME_MASK BIT(4) 873 874 /* Interrupt */ 875 #define REG_SW_PORT_INT_STATUS__1 0x001B 876 #define REG_SW_PORT_INT_MASK__1 0x001F 877 878 #define REG_PORT_INT_STATUS 0x001B 879 #define REG_PORT_INT_MASK 0x001F 880 881 #define PORT_SRC_PHY_INT 1 882 #define PORT_SRC_PTP_INT 2 883 884 #define KSZ8795_HUGE_PACKET_SIZE 2000 885 #define KSZ8863_HUGE_PACKET_SIZE 1916 886 #define KSZ8863_NORMAL_PACKET_SIZE 1536 887 #define KSZ8_LEGAL_PACKET_SIZE 1518 888 #define KSZ9477_MAX_FRAME_SIZE 9000 889 890 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 891 /* Drive Strength of I/O Pad 892 * 0: 8mA, 1: 16mA 893 */ 894 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 895 896 #define KSZ8795_REG_SW_CTRL_20 0xa3 897 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 898 #define SW_DRIVE_STRENGTH_M 0x7 899 #define SW_DRIVE_STRENGTH_2MA 0 900 #define SW_DRIVE_STRENGTH_4MA 1 901 #define SW_DRIVE_STRENGTH_8MA 2 902 #define SW_DRIVE_STRENGTH_12MA 3 903 #define SW_DRIVE_STRENGTH_16MA 4 904 #define SW_DRIVE_STRENGTH_20MA 5 905 #define SW_DRIVE_STRENGTH_24MA 6 906 #define SW_DRIVE_STRENGTH_28MA 7 907 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 908 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 909 910 /* TXQ Split Control Register for per-port, per-queue configuration. 911 * Register 0xAF is TXQ Split for Q3 on Port 1. 912 * Register offset formula: 0xAF + (port * 4) + (3 - queue) 913 * where: port = 0..2, queue = 0..3 914 */ 915 #define KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue) \ 916 (0xAF + ((port) * 4) + (3 - (queue))) 917 918 /* Bit 7 selects between: 919 * 0 = Strict priority mode (highest-priority queue first) 920 * 1 = Weighted Fair Queuing (WFQ) mode: 921 * Queue weights: Q3:Q2:Q1:Q0 = 8:4:2:1 922 * If any queues are empty, weight is redistributed. 923 * 924 * Note: This is referred to as "Weighted Fair Queuing" (WFQ) in KSZ8863/8873 925 * documentation, and as "Weighted Round Robin" (WRR) in KSZ9477 family docs. 926 */ 927 #define KSZ8873_TXQ_WFQ_ENABLE BIT(7) 928 929 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 930 #define KSZ9477_OUT_RATE_NO_LIMIT 0 931 932 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 933 934 #define KSZ9477_PORT_TC_MAP_S 4 935 936 /* CBS related registers */ 937 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 938 939 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 940 941 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 942 #define MTI_SCHEDULE_STRICT_PRIO 0 943 #define MTI_SCHEDULE_WRR 2 944 #define MTI_SHAPING_M GENMASK(5, 4) 945 #define MTI_SHAPING_OFF 0 946 #define MTI_SHAPING_SRP 1 947 #define MTI_SHAPING_TIME_AWARE 2 948 949 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 950 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 951 952 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 953 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 954 955 /* Regmap tables generation */ 956 #define KSZ_SPI_OP_RD 3 957 #define KSZ_SPI_OP_WR 2 958 959 #define swabnot_used(x) 0 960 961 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 962 swab##swp((opcode) << ((regbits) + (regpad))) 963 964 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 965 { \ 966 .name = #width, \ 967 .val_bits = (width), \ 968 .reg_stride = 1, \ 969 .reg_bits = (regbits) + (regalign), \ 970 .pad_bits = (regpad), \ 971 .max_register = BIT(regbits) - 1, \ 972 .cache_type = REGCACHE_NONE, \ 973 .read_flag_mask = \ 974 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 975 regbits, regpad), \ 976 .write_flag_mask = \ 977 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 978 regbits, regpad), \ 979 .lock = ksz_regmap_lock, \ 980 .unlock = ksz_regmap_unlock, \ 981 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 982 .val_format_endian = REGMAP_ENDIAN_BIG \ 983 } 984 985 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 986 static const struct regmap_config ksz##_regmap_config[] = { \ 987 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 988 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 989 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 990 } 991 992 #define KSZ8463_REGMAP_ENTRY(width, regbits, regpad, regalign) \ 993 { \ 994 .name = #width, \ 995 .val_bits = (width), \ 996 .reg_stride = (width / 8), \ 997 .reg_bits = (regbits) + (regalign), \ 998 .pad_bits = (regpad), \ 999 .read = ksz8463_spi_read, \ 1000 .write = ksz8463_spi_write, \ 1001 .max_register = BIT(regbits) - 1, \ 1002 .cache_type = REGCACHE_NONE, \ 1003 .zero_flag_mask = 1, \ 1004 .use_single_read = 1, \ 1005 .use_single_write = 1, \ 1006 .lock = ksz_regmap_lock, \ 1007 .unlock = ksz_regmap_unlock, \ 1008 } 1009 1010 #define KSZ8463_REGMAP_TABLE(ksz, regbits, regpad, regalign) \ 1011 static const struct regmap_config ksz##_regmap_config[] = { \ 1012 [KSZ_REGMAP_8] = KSZ8463_REGMAP_ENTRY(8, (regbits), (regpad), (regalign)), \ 1013 [KSZ_REGMAP_16] = KSZ8463_REGMAP_ENTRY(16, (regbits), (regpad), (regalign)), \ 1014 [KSZ_REGMAP_32] = KSZ8463_REGMAP_ENTRY(32, (regbits), (regpad), (regalign)), \ 1015 } 1016 1017 #endif 1018