1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 17 #define KSZ_MAX_NUM_PORTS 8 18 19 struct vlan_table { 20 u32 table[3]; 21 }; 22 23 struct ksz_port_mib { 24 struct mutex cnt_mutex; /* structure access */ 25 u8 cnt_ptr; 26 u64 *counters; 27 struct rtnl_link_stats64 stats64; 28 struct spinlock stats64_lock; 29 }; 30 31 struct ksz_mib_names { 32 int index; 33 char string[ETH_GSTRING_LEN]; 34 }; 35 36 struct ksz_chip_data { 37 u32 chip_id; 38 const char *dev_name; 39 int num_vlans; 40 int num_alus; 41 int num_statics; 42 int cpu_ports; 43 int port_cnt; 44 const struct ksz_dev_ops *ops; 45 bool phy_errata_9477; 46 bool ksz87xx_eee_link_erratum; 47 const struct ksz_mib_names *mib_names; 48 int mib_cnt; 49 u8 reg_mib_cnt; 50 int stp_ctrl_reg; 51 int broadcast_ctrl_reg; 52 int multicast_ctrl_reg; 53 int start_ctrl_reg; 54 bool supports_mii[KSZ_MAX_NUM_PORTS]; 55 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 56 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 57 bool internal_phy[KSZ_MAX_NUM_PORTS]; 58 }; 59 60 struct ksz_port { 61 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 62 int stp_state; 63 struct phy_device phydev; 64 65 u32 on:1; /* port is not disabled by hardware */ 66 u32 phy:1; /* port has a PHY */ 67 u32 fiber:1; /* port is fiber */ 68 u32 sgmii:1; /* port is SGMII */ 69 u32 force:1; 70 u32 read:1; /* read MIB counters in background */ 71 u32 freeze:1; /* MIB counter freeze is enabled */ 72 73 struct ksz_port_mib mib; 74 phy_interface_t interface; 75 u16 max_frame; 76 }; 77 78 struct ksz_device { 79 struct dsa_switch *ds; 80 struct ksz_platform_data *pdata; 81 const struct ksz_chip_data *info; 82 83 struct mutex dev_mutex; /* device access */ 84 struct mutex regmap_mutex; /* regmap access */ 85 struct mutex alu_mutex; /* ALU access */ 86 struct mutex vlan_mutex; /* vlan access */ 87 const struct ksz_dev_ops *dev_ops; 88 89 struct device *dev; 90 struct regmap *regmap[3]; 91 92 void *priv; 93 94 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 95 96 /* chip specific data */ 97 u32 chip_id; 98 u8 chip_rev; 99 int cpu_port; /* port connected to CPU */ 100 int phy_port_cnt; 101 phy_interface_t compat_interface; 102 bool synclko_125; 103 bool synclko_disable; 104 105 struct vlan_table *vlan_cache; 106 107 struct ksz_port *ports; 108 struct delayed_work mib_read; 109 unsigned long mib_read_interval; 110 u16 mirror_rx; 111 u16 mirror_tx; 112 u32 features; /* chip specific features */ 113 u16 port_mask; 114 }; 115 116 /* List of supported models */ 117 enum ksz_model { 118 KSZ8795, 119 KSZ8794, 120 KSZ8765, 121 KSZ8830, 122 KSZ9477, 123 KSZ9897, 124 KSZ9893, 125 KSZ9567, 126 LAN9370, 127 LAN9371, 128 LAN9372, 129 LAN9373, 130 LAN9374, 131 }; 132 133 enum ksz_chip_id { 134 KSZ8795_CHIP_ID = 0x8795, 135 KSZ8794_CHIP_ID = 0x8794, 136 KSZ8765_CHIP_ID = 0x8765, 137 KSZ8830_CHIP_ID = 0x8830, 138 KSZ9477_CHIP_ID = 0x00947700, 139 KSZ9897_CHIP_ID = 0x00989700, 140 KSZ9893_CHIP_ID = 0x00989300, 141 KSZ9567_CHIP_ID = 0x00956700, 142 LAN9370_CHIP_ID = 0x00937000, 143 LAN9371_CHIP_ID = 0x00937100, 144 LAN9372_CHIP_ID = 0x00937200, 145 LAN9373_CHIP_ID = 0x00937300, 146 LAN9374_CHIP_ID = 0x00937400, 147 }; 148 149 struct alu_struct { 150 /* entry 1 */ 151 u8 is_static:1; 152 u8 is_src_filter:1; 153 u8 is_dst_filter:1; 154 u8 prio_age:3; 155 u32 _reserv_0_1:23; 156 u8 mstp:3; 157 /* entry 2 */ 158 u8 is_override:1; 159 u8 is_use_fid:1; 160 u32 _reserv_1_1:23; 161 u8 port_forward:7; 162 /* entry 3 & 4*/ 163 u32 _reserv_2_1:9; 164 u8 fid:7; 165 u8 mac[ETH_ALEN]; 166 }; 167 168 struct ksz_dev_ops { 169 int (*setup)(struct dsa_switch *ds); 170 u32 (*get_port_addr)(int port, int offset); 171 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 172 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 173 void (*port_cleanup)(struct ksz_device *dev, int port); 174 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 175 void (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 176 void (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 177 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 178 u64 *cnt); 179 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 180 u64 *dropped, u64 *cnt); 181 void (*r_mib_stat64)(struct ksz_device *dev, int port); 182 int (*vlan_filtering)(struct ksz_device *dev, int port, 183 bool flag, struct netlink_ext_ack *extack); 184 int (*vlan_add)(struct ksz_device *dev, int port, 185 const struct switchdev_obj_port_vlan *vlan, 186 struct netlink_ext_ack *extack); 187 int (*vlan_del)(struct ksz_device *dev, int port, 188 const struct switchdev_obj_port_vlan *vlan); 189 int (*mirror_add)(struct ksz_device *dev, int port, 190 struct dsa_mall_mirror_tc_entry *mirror, 191 bool ingress, struct netlink_ext_ack *extack); 192 void (*mirror_del)(struct ksz_device *dev, int port, 193 struct dsa_mall_mirror_tc_entry *mirror); 194 int (*fdb_add)(struct ksz_device *dev, int port, 195 const unsigned char *addr, u16 vid, struct dsa_db db); 196 int (*fdb_del)(struct ksz_device *dev, int port, 197 const unsigned char *addr, u16 vid, struct dsa_db db); 198 int (*fdb_dump)(struct ksz_device *dev, int port, 199 dsa_fdb_dump_cb_t *cb, void *data); 200 int (*mdb_add)(struct ksz_device *dev, int port, 201 const struct switchdev_obj_port_mdb *mdb, 202 struct dsa_db db); 203 int (*mdb_del)(struct ksz_device *dev, int port, 204 const struct switchdev_obj_port_mdb *mdb, 205 struct dsa_db db); 206 void (*get_caps)(struct ksz_device *dev, int port, 207 struct phylink_config *config); 208 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 209 int (*max_mtu)(struct ksz_device *dev, int port); 210 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 211 void (*port_init_cnt)(struct ksz_device *dev, int port); 212 void (*config_cpu_port)(struct dsa_switch *ds); 213 int (*enable_stp_addr)(struct ksz_device *dev); 214 int (*reset)(struct ksz_device *dev); 215 int (*init)(struct ksz_device *dev); 216 void (*exit)(struct ksz_device *dev); 217 }; 218 219 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 220 int ksz_switch_register(struct ksz_device *dev); 221 void ksz_switch_remove(struct ksz_device *dev); 222 223 void ksz_init_mib_timer(struct ksz_device *dev); 224 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 225 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 226 extern const struct ksz_chip_data ksz_switch_chips[]; 227 228 /* Common register access functions */ 229 230 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 231 { 232 unsigned int value; 233 int ret = regmap_read(dev->regmap[0], reg, &value); 234 235 *val = value; 236 return ret; 237 } 238 239 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 240 { 241 unsigned int value; 242 int ret = regmap_read(dev->regmap[1], reg, &value); 243 244 *val = value; 245 return ret; 246 } 247 248 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 249 { 250 unsigned int value; 251 int ret = regmap_read(dev->regmap[2], reg, &value); 252 253 *val = value; 254 return ret; 255 } 256 257 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 258 { 259 u32 value[2]; 260 int ret; 261 262 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); 263 if (!ret) 264 *val = (u64)value[0] << 32 | value[1]; 265 266 return ret; 267 } 268 269 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 270 { 271 return regmap_write(dev->regmap[0], reg, value); 272 } 273 274 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 275 { 276 return regmap_write(dev->regmap[1], reg, value); 277 } 278 279 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 280 { 281 return regmap_write(dev->regmap[2], reg, value); 282 } 283 284 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 285 { 286 u32 val[2]; 287 288 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 289 value = swab64(value); 290 val[0] = swab32(value & 0xffffffffULL); 291 val[1] = swab32(value >> 32ULL); 292 293 return regmap_bulk_write(dev->regmap[2], reg, val, 2); 294 } 295 296 static inline void ksz_pread8(struct ksz_device *dev, int port, int offset, 297 u8 *data) 298 { 299 ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 300 } 301 302 static inline void ksz_pread16(struct ksz_device *dev, int port, int offset, 303 u16 *data) 304 { 305 ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 306 } 307 308 static inline void ksz_pread32(struct ksz_device *dev, int port, int offset, 309 u32 *data) 310 { 311 ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 312 } 313 314 static inline void ksz_pwrite8(struct ksz_device *dev, int port, int offset, 315 u8 data) 316 { 317 ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 318 } 319 320 static inline void ksz_pwrite16(struct ksz_device *dev, int port, int offset, 321 u16 data) 322 { 323 ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), data); 324 } 325 326 static inline void ksz_pwrite32(struct ksz_device *dev, int port, int offset, 327 u32 data) 328 { 329 ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), data); 330 } 331 332 static inline void ksz_regmap_lock(void *__mtx) 333 { 334 struct mutex *mtx = __mtx; 335 mutex_lock(mtx); 336 } 337 338 static inline void ksz_regmap_unlock(void *__mtx) 339 { 340 struct mutex *mtx = __mtx; 341 mutex_unlock(mtx); 342 } 343 344 /* STP State Defines */ 345 #define PORT_TX_ENABLE BIT(2) 346 #define PORT_RX_ENABLE BIT(1) 347 #define PORT_LEARN_DISABLE BIT(0) 348 349 /* Switch ID Defines */ 350 #define REG_CHIP_ID0 0x00 351 352 #define SW_FAMILY_ID_M GENMASK(15, 8) 353 #define KSZ87_FAMILY_ID 0x87 354 #define KSZ88_FAMILY_ID 0x88 355 356 #define KSZ8_PORT_STATUS_0 0x08 357 #define KSZ8_PORT_FIBER_MODE BIT(7) 358 359 #define SW_CHIP_ID_M GENMASK(7, 4) 360 #define KSZ87_CHIP_ID_94 0x6 361 #define KSZ87_CHIP_ID_95 0x9 362 #define KSZ88_CHIP_ID_63 0x3 363 364 #define SW_REV_ID_M GENMASK(7, 4) 365 366 /* Driver set switch broadcast storm protection at 10% rate. */ 367 #define BROADCAST_STORM_PROT_RATE 10 368 369 /* 148,800 frames * 67 ms / 100 */ 370 #define BROADCAST_STORM_VALUE 9969 371 372 #define BROADCAST_STORM_RATE_HI 0x07 373 #define BROADCAST_STORM_RATE_LO 0xFF 374 #define BROADCAST_STORM_RATE 0x07FF 375 376 #define MULTICAST_STORM_DISABLE BIT(6) 377 378 #define SW_START 0x01 379 380 /* Regmap tables generation */ 381 #define KSZ_SPI_OP_RD 3 382 #define KSZ_SPI_OP_WR 2 383 384 #define swabnot_used(x) 0 385 386 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 387 swab##swp((opcode) << ((regbits) + (regpad))) 388 389 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 390 { \ 391 .name = #width, \ 392 .val_bits = (width), \ 393 .reg_stride = 1, \ 394 .reg_bits = (regbits) + (regalign), \ 395 .pad_bits = (regpad), \ 396 .max_register = BIT(regbits) - 1, \ 397 .cache_type = REGCACHE_NONE, \ 398 .read_flag_mask = \ 399 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 400 regbits, regpad), \ 401 .write_flag_mask = \ 402 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 403 regbits, regpad), \ 404 .lock = ksz_regmap_lock, \ 405 .unlock = ksz_regmap_unlock, \ 406 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 407 .val_format_endian = REGMAP_ENDIAN_BIG \ 408 } 409 410 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 411 static const struct regmap_config ksz##_regmap_config[] = { \ 412 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 413 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 414 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 415 } 416 417 #endif 418