1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 #include <linux/platform_data/microchip-ksz.h> 18 19 #include "ksz_ptp.h" 20 21 #define KSZ_MAX_NUM_PORTS 8 22 /* all KSZ switches count ports from 1 */ 23 #define KSZ_PORT_1 0 24 #define KSZ_PORT_2 1 25 #define KSZ_PORT_4 3 26 27 struct ksz_device; 28 struct ksz_port; 29 struct phylink_mac_ops; 30 31 enum ksz_regmap_width { 32 KSZ_REGMAP_8, 33 KSZ_REGMAP_16, 34 KSZ_REGMAP_32, 35 __KSZ_NUM_REGMAPS, 36 }; 37 38 struct vlan_table { 39 u32 table[3]; 40 }; 41 42 struct ksz_port_mib { 43 struct mutex cnt_mutex; /* structure access */ 44 u8 cnt_ptr; 45 u64 *counters; 46 struct rtnl_link_stats64 stats64; 47 struct ethtool_pause_stats pause_stats; 48 struct spinlock stats64_lock; 49 }; 50 51 struct ksz_mib_names { 52 int index; 53 char string[ETH_GSTRING_LEN]; 54 }; 55 56 struct ksz_chip_data { 57 u32 chip_id; 58 const char *dev_name; 59 int num_vlans; 60 int num_alus; 61 int num_statics; 62 int cpu_ports; 63 int port_cnt; 64 u8 port_nirqs; 65 u8 num_tx_queues; 66 u8 num_ipms; /* number of Internal Priority Maps */ 67 bool tc_cbs_supported; 68 const struct ksz_dev_ops *ops; 69 const struct phylink_mac_ops *phylink_mac_ops; 70 bool phy_errata_9477; 71 bool ksz87xx_eee_link_erratum; 72 const struct ksz_mib_names *mib_names; 73 int mib_cnt; 74 u8 reg_mib_cnt; 75 const u16 *regs; 76 const u32 *masks; 77 const u8 *shifts; 78 const u8 *xmii_ctrl0; 79 const u8 *xmii_ctrl1; 80 int stp_ctrl_reg; 81 int broadcast_ctrl_reg; 82 int multicast_ctrl_reg; 83 int start_ctrl_reg; 84 bool supports_mii[KSZ_MAX_NUM_PORTS]; 85 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 86 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 87 bool internal_phy[KSZ_MAX_NUM_PORTS]; 88 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 89 const struct regmap_access_table *wr_table; 90 const struct regmap_access_table *rd_table; 91 }; 92 93 struct ksz_irq { 94 u16 masked; 95 u16 reg_mask; 96 u16 reg_status; 97 struct irq_domain *domain; 98 int nirqs; 99 int irq_num; 100 char name[16]; 101 struct ksz_device *dev; 102 }; 103 104 struct ksz_ptp_irq { 105 struct ksz_port *port; 106 u16 ts_reg; 107 bool ts_en; 108 char name[16]; 109 int num; 110 }; 111 112 struct ksz_switch_macaddr { 113 unsigned char addr[ETH_ALEN]; 114 refcount_t refcount; 115 }; 116 117 struct ksz_port { 118 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 119 bool learning; 120 bool isolated; 121 int stp_state; 122 struct phy_device phydev; 123 124 u32 fiber:1; /* port is fiber */ 125 u32 force:1; 126 u32 read:1; /* read MIB counters in background */ 127 u32 freeze:1; /* MIB counter freeze is enabled */ 128 129 struct ksz_port_mib mib; 130 phy_interface_t interface; 131 u32 rgmii_tx_val; 132 u32 rgmii_rx_val; 133 struct ksz_device *ksz_dev; 134 void *acl_priv; 135 struct ksz_irq pirq; 136 u8 num; 137 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 138 struct hwtstamp_config tstamp_config; 139 bool hwts_tx_en; 140 bool hwts_rx_en; 141 struct ksz_irq ptpirq; 142 struct ksz_ptp_irq ptpmsg_irq[3]; 143 ktime_t tstamp_msg; 144 struct completion tstamp_msg_comp; 145 #endif 146 bool manual_flow; 147 }; 148 149 struct ksz_device { 150 struct dsa_switch *ds; 151 struct ksz_platform_data *pdata; 152 const struct ksz_chip_data *info; 153 154 struct mutex dev_mutex; /* device access */ 155 struct mutex regmap_mutex; /* regmap access */ 156 struct mutex alu_mutex; /* ALU access */ 157 struct mutex vlan_mutex; /* vlan access */ 158 const struct ksz_dev_ops *dev_ops; 159 160 struct device *dev; 161 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 162 163 void *priv; 164 int irq; 165 166 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 167 168 /* chip specific data */ 169 u32 chip_id; 170 u8 chip_rev; 171 int cpu_port; /* port connected to CPU */ 172 int phy_port_cnt; 173 phy_interface_t compat_interface; 174 bool synclko_125; 175 bool synclko_disable; 176 bool wakeup_source; 177 bool pme_active_high; 178 179 struct vlan_table *vlan_cache; 180 181 struct ksz_port *ports; 182 struct delayed_work mib_read; 183 unsigned long mib_read_interval; 184 u16 mirror_rx; 185 u16 mirror_tx; 186 u16 port_mask; 187 struct mutex lock_irq; /* IRQ Access */ 188 struct ksz_irq girq; 189 struct ksz_ptp_data ptp_data; 190 191 struct ksz_switch_macaddr *switch_macaddr; 192 struct net_device *hsr_dev; /* HSR */ 193 u8 hsr_ports; 194 }; 195 196 /* List of supported models */ 197 enum ksz_model { 198 KSZ8563, 199 KSZ8567, 200 KSZ8795, 201 KSZ8794, 202 KSZ8765, 203 KSZ8830, 204 KSZ9477, 205 KSZ9896, 206 KSZ9897, 207 KSZ9893, 208 KSZ9563, 209 KSZ9567, 210 LAN9370, 211 LAN9371, 212 LAN9372, 213 LAN9373, 214 LAN9374, 215 }; 216 217 enum ksz_regs { 218 REG_SW_MAC_ADDR, 219 REG_IND_CTRL_0, 220 REG_IND_DATA_8, 221 REG_IND_DATA_CHECK, 222 REG_IND_DATA_HI, 223 REG_IND_DATA_LO, 224 REG_IND_MIB_CHECK, 225 REG_IND_BYTE, 226 P_FORCE_CTRL, 227 P_LINK_STATUS, 228 P_LOCAL_CTRL, 229 P_NEG_RESTART_CTRL, 230 P_REMOTE_STATUS, 231 P_SPEED_STATUS, 232 S_TAIL_TAG_CTRL, 233 P_STP_CTRL, 234 S_START_CTRL, 235 S_BROADCAST_CTRL, 236 S_MULTICAST_CTRL, 237 P_XMII_CTRL_0, 238 P_XMII_CTRL_1, 239 REG_SW_PME_CTRL, 240 REG_PORT_PME_STATUS, 241 REG_PORT_PME_CTRL, 242 }; 243 244 enum ksz_masks { 245 PORT_802_1P_REMAPPING, 246 SW_TAIL_TAG_ENABLE, 247 MIB_COUNTER_OVERFLOW, 248 MIB_COUNTER_VALID, 249 VLAN_TABLE_FID, 250 VLAN_TABLE_MEMBERSHIP, 251 VLAN_TABLE_VALID, 252 STATIC_MAC_TABLE_VALID, 253 STATIC_MAC_TABLE_USE_FID, 254 STATIC_MAC_TABLE_FID, 255 STATIC_MAC_TABLE_OVERRIDE, 256 STATIC_MAC_TABLE_FWD_PORTS, 257 DYNAMIC_MAC_TABLE_ENTRIES_H, 258 DYNAMIC_MAC_TABLE_MAC_EMPTY, 259 DYNAMIC_MAC_TABLE_NOT_READY, 260 DYNAMIC_MAC_TABLE_ENTRIES, 261 DYNAMIC_MAC_TABLE_FID, 262 DYNAMIC_MAC_TABLE_SRC_PORT, 263 DYNAMIC_MAC_TABLE_TIMESTAMP, 264 ALU_STAT_WRITE, 265 ALU_STAT_READ, 266 P_MII_TX_FLOW_CTRL, 267 P_MII_RX_FLOW_CTRL, 268 }; 269 270 enum ksz_shifts { 271 VLAN_TABLE_MEMBERSHIP_S, 272 VLAN_TABLE, 273 STATIC_MAC_FWD_PORTS, 274 STATIC_MAC_FID, 275 DYNAMIC_MAC_ENTRIES_H, 276 DYNAMIC_MAC_ENTRIES, 277 DYNAMIC_MAC_FID, 278 DYNAMIC_MAC_TIMESTAMP, 279 DYNAMIC_MAC_SRC_PORT, 280 ALU_STAT_INDEX, 281 }; 282 283 enum ksz_xmii_ctrl0 { 284 P_MII_100MBIT, 285 P_MII_10MBIT, 286 P_MII_FULL_DUPLEX, 287 P_MII_HALF_DUPLEX, 288 }; 289 290 enum ksz_xmii_ctrl1 { 291 P_RGMII_SEL, 292 P_RMII_SEL, 293 P_GMII_SEL, 294 P_MII_SEL, 295 P_GMII_1GBIT, 296 P_GMII_NOT_1GBIT, 297 }; 298 299 struct alu_struct { 300 /* entry 1 */ 301 u8 is_static:1; 302 u8 is_src_filter:1; 303 u8 is_dst_filter:1; 304 u8 prio_age:3; 305 u32 _reserv_0_1:23; 306 u8 mstp:3; 307 /* entry 2 */ 308 u8 is_override:1; 309 u8 is_use_fid:1; 310 u32 _reserv_1_1:23; 311 u8 port_forward:7; 312 /* entry 3 & 4*/ 313 u32 _reserv_2_1:9; 314 u8 fid:7; 315 u8 mac[ETH_ALEN]; 316 }; 317 318 struct ksz_dev_ops { 319 int (*setup)(struct dsa_switch *ds); 320 void (*teardown)(struct dsa_switch *ds); 321 u32 (*get_port_addr)(int port, int offset); 322 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 323 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 324 void (*port_cleanup)(struct ksz_device *dev, int port); 325 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 326 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 327 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 328 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 329 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 330 u64 *cnt); 331 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 332 u64 *dropped, u64 *cnt); 333 void (*r_mib_stat64)(struct ksz_device *dev, int port); 334 int (*vlan_filtering)(struct ksz_device *dev, int port, 335 bool flag, struct netlink_ext_ack *extack); 336 int (*vlan_add)(struct ksz_device *dev, int port, 337 const struct switchdev_obj_port_vlan *vlan, 338 struct netlink_ext_ack *extack); 339 int (*vlan_del)(struct ksz_device *dev, int port, 340 const struct switchdev_obj_port_vlan *vlan); 341 int (*mirror_add)(struct ksz_device *dev, int port, 342 struct dsa_mall_mirror_tc_entry *mirror, 343 bool ingress, struct netlink_ext_ack *extack); 344 void (*mirror_del)(struct ksz_device *dev, int port, 345 struct dsa_mall_mirror_tc_entry *mirror); 346 int (*fdb_add)(struct ksz_device *dev, int port, 347 const unsigned char *addr, u16 vid, struct dsa_db db); 348 int (*fdb_del)(struct ksz_device *dev, int port, 349 const unsigned char *addr, u16 vid, struct dsa_db db); 350 int (*fdb_dump)(struct ksz_device *dev, int port, 351 dsa_fdb_dump_cb_t *cb, void *data); 352 int (*mdb_add)(struct ksz_device *dev, int port, 353 const struct switchdev_obj_port_mdb *mdb, 354 struct dsa_db db); 355 int (*mdb_del)(struct ksz_device *dev, int port, 356 const struct switchdev_obj_port_mdb *mdb, 357 struct dsa_db db); 358 void (*get_caps)(struct ksz_device *dev, int port, 359 struct phylink_config *config); 360 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 361 int (*pme_write8)(struct ksz_device *dev, u32 reg, u8 value); 362 int (*pme_pread8)(struct ksz_device *dev, int port, int offset, 363 u8 *data); 364 int (*pme_pwrite8)(struct ksz_device *dev, int port, int offset, 365 u8 data); 366 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 367 void (*port_init_cnt)(struct ksz_device *dev, int port); 368 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 369 unsigned int mode, 370 phy_interface_t interface, 371 struct phy_device *phydev, int speed, 372 int duplex, bool tx_pause, bool rx_pause); 373 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 374 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 375 void (*config_cpu_port)(struct dsa_switch *ds); 376 int (*enable_stp_addr)(struct ksz_device *dev); 377 int (*reset)(struct ksz_device *dev); 378 int (*init)(struct ksz_device *dev); 379 void (*exit)(struct ksz_device *dev); 380 }; 381 382 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 383 int ksz_switch_register(struct ksz_device *dev); 384 void ksz_switch_remove(struct ksz_device *dev); 385 386 void ksz_init_mib_timer(struct ksz_device *dev); 387 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port); 388 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 389 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 390 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 391 bool ksz_get_gbit(struct ksz_device *dev, int port); 392 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 393 extern const struct ksz_chip_data ksz_switch_chips[]; 394 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 395 struct netlink_ext_ack *extack); 396 void ksz_switch_macaddr_put(struct dsa_switch *ds); 397 void ksz_switch_shutdown(struct ksz_device *dev); 398 int ksz_handle_wake_reason(struct ksz_device *dev, int port); 399 400 /* Common register access functions */ 401 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 402 { 403 return dev->regmap[KSZ_REGMAP_8]; 404 } 405 406 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 407 { 408 return dev->regmap[KSZ_REGMAP_16]; 409 } 410 411 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 412 { 413 return dev->regmap[KSZ_REGMAP_32]; 414 } 415 416 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 417 { 418 unsigned int value; 419 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 420 421 if (ret) 422 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 423 ERR_PTR(ret)); 424 425 *val = value; 426 return ret; 427 } 428 429 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 430 { 431 unsigned int value; 432 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 433 434 if (ret) 435 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 436 ERR_PTR(ret)); 437 438 *val = value; 439 return ret; 440 } 441 442 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 443 { 444 unsigned int value; 445 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 446 447 if (ret) 448 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 449 ERR_PTR(ret)); 450 451 *val = value; 452 return ret; 453 } 454 455 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 456 { 457 u32 value[2]; 458 int ret; 459 460 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 461 if (ret) 462 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 463 ERR_PTR(ret)); 464 else 465 *val = (u64)value[0] << 32 | value[1]; 466 467 return ret; 468 } 469 470 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 471 { 472 int ret; 473 474 ret = regmap_write(ksz_regmap_8(dev), reg, value); 475 if (ret) 476 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 477 ERR_PTR(ret)); 478 479 return ret; 480 } 481 482 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 483 { 484 int ret; 485 486 ret = regmap_write(ksz_regmap_16(dev), reg, value); 487 if (ret) 488 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 489 ERR_PTR(ret)); 490 491 return ret; 492 } 493 494 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 495 { 496 int ret; 497 498 ret = regmap_write(ksz_regmap_32(dev), reg, value); 499 if (ret) 500 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 501 ERR_PTR(ret)); 502 503 return ret; 504 } 505 506 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 507 u16 value) 508 { 509 int ret; 510 511 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 512 if (ret) 513 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 514 ERR_PTR(ret)); 515 516 return ret; 517 } 518 519 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 520 u32 value) 521 { 522 int ret; 523 524 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 525 if (ret) 526 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 527 ERR_PTR(ret)); 528 529 return ret; 530 } 531 532 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 533 { 534 u32 val[2]; 535 536 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 537 value = swab64(value); 538 val[0] = swab32(value & 0xffffffffULL); 539 val[1] = swab32(value >> 32ULL); 540 541 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 542 } 543 544 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 545 { 546 int ret; 547 548 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 549 if (ret) 550 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 551 ERR_PTR(ret)); 552 553 return ret; 554 } 555 556 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 557 u8 *data) 558 { 559 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 560 } 561 562 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 563 u16 *data) 564 { 565 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 566 } 567 568 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 569 u32 *data) 570 { 571 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 572 } 573 574 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 575 u8 data) 576 { 577 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 578 } 579 580 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 581 u16 data) 582 { 583 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 584 data); 585 } 586 587 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 588 u32 data) 589 { 590 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 591 data); 592 } 593 594 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 595 u8 mask, u8 val) 596 { 597 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 598 mask, val); 599 } 600 601 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 602 u32 mask, u32 val) 603 { 604 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 605 mask, val); 606 } 607 608 static inline void ksz_regmap_lock(void *__mtx) 609 { 610 struct mutex *mtx = __mtx; 611 mutex_lock(mtx); 612 } 613 614 static inline void ksz_regmap_unlock(void *__mtx) 615 { 616 struct mutex *mtx = __mtx; 617 mutex_unlock(mtx); 618 } 619 620 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 621 { 622 return dev->chip_id == KSZ8795_CHIP_ID || 623 dev->chip_id == KSZ8794_CHIP_ID || 624 dev->chip_id == KSZ8765_CHIP_ID; 625 } 626 627 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 628 { 629 return dev->chip_id == KSZ8830_CHIP_ID; 630 } 631 632 static inline bool is_ksz8(struct ksz_device *dev) 633 { 634 return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev); 635 } 636 637 static inline bool is_ksz9477(struct ksz_device *dev) 638 { 639 return dev->chip_id == KSZ9477_CHIP_ID; 640 } 641 642 static inline int is_lan937x(struct ksz_device *dev) 643 { 644 return dev->chip_id == LAN9370_CHIP_ID || 645 dev->chip_id == LAN9371_CHIP_ID || 646 dev->chip_id == LAN9372_CHIP_ID || 647 dev->chip_id == LAN9373_CHIP_ID || 648 dev->chip_id == LAN9374_CHIP_ID; 649 } 650 651 static inline bool is_lan937x_tx_phy(struct ksz_device *dev, int port) 652 { 653 return (dev->chip_id == LAN9371_CHIP_ID || 654 dev->chip_id == LAN9372_CHIP_ID) && port == KSZ_PORT_4; 655 } 656 657 /* STP State Defines */ 658 #define PORT_TX_ENABLE BIT(2) 659 #define PORT_RX_ENABLE BIT(1) 660 #define PORT_LEARN_DISABLE BIT(0) 661 662 /* Switch ID Defines */ 663 #define REG_CHIP_ID0 0x00 664 665 #define SW_FAMILY_ID_M GENMASK(15, 8) 666 #define KSZ87_FAMILY_ID 0x87 667 #define KSZ88_FAMILY_ID 0x88 668 669 #define KSZ8_PORT_STATUS_0 0x08 670 #define KSZ8_PORT_FIBER_MODE BIT(7) 671 672 #define SW_CHIP_ID_M GENMASK(7, 4) 673 #define KSZ87_CHIP_ID_94 0x6 674 #define KSZ87_CHIP_ID_95 0x9 675 #define KSZ88_CHIP_ID_63 0x3 676 677 #define SW_REV_ID_M GENMASK(7, 4) 678 679 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 680 #define REG_CHIP_ID4 0x0f 681 #define SKU_ID_KSZ8563 0x3c 682 #define SKU_ID_KSZ9563 0x1c 683 684 /* Driver set switch broadcast storm protection at 10% rate. */ 685 #define BROADCAST_STORM_PROT_RATE 10 686 687 /* 148,800 frames * 67 ms / 100 */ 688 #define BROADCAST_STORM_VALUE 9969 689 690 #define BROADCAST_STORM_RATE_HI 0x07 691 #define BROADCAST_STORM_RATE_LO 0xFF 692 #define BROADCAST_STORM_RATE 0x07FF 693 694 #define MULTICAST_STORM_DISABLE BIT(6) 695 696 #define SW_START 0x01 697 698 /* xMII configuration */ 699 #define P_MII_DUPLEX_M BIT(6) 700 #define P_MII_100MBIT_M BIT(4) 701 702 #define P_GMII_1GBIT_M BIT(6) 703 #define P_RGMII_ID_IG_ENABLE BIT(4) 704 #define P_RGMII_ID_EG_ENABLE BIT(3) 705 #define P_MII_MAC_MODE BIT(2) 706 #define P_MII_SEL_M 0x3 707 708 /* KSZ9477, KSZ87xx Wake-on-LAN (WoL) masks */ 709 #define PME_WOL_MAGICPKT BIT(2) 710 #define PME_WOL_LINKUP BIT(1) 711 #define PME_WOL_ENERGY BIT(0) 712 713 #define PME_ENABLE BIT(1) 714 #define PME_POLARITY BIT(0) 715 716 #define KSZ87XX_REG_INT_EN 0x7D 717 #define KSZ87XX_INT_PME_MASK BIT(4) 718 719 /* Interrupt */ 720 #define REG_SW_PORT_INT_STATUS__1 0x001B 721 #define REG_SW_PORT_INT_MASK__1 0x001F 722 723 #define REG_PORT_INT_STATUS 0x001B 724 #define REG_PORT_INT_MASK 0x001F 725 726 #define PORT_SRC_PHY_INT 1 727 #define PORT_SRC_PTP_INT 2 728 729 #define KSZ8795_HUGE_PACKET_SIZE 2000 730 #define KSZ8863_HUGE_PACKET_SIZE 1916 731 #define KSZ8863_NORMAL_PACKET_SIZE 1536 732 #define KSZ8_LEGAL_PACKET_SIZE 1518 733 #define KSZ9477_MAX_FRAME_SIZE 9000 734 735 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 736 /* Drive Strength of I/O Pad 737 * 0: 8mA, 1: 16mA 738 */ 739 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 740 741 #define KSZ8795_REG_SW_CTRL_20 0xa3 742 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 743 #define SW_DRIVE_STRENGTH_M 0x7 744 #define SW_DRIVE_STRENGTH_2MA 0 745 #define SW_DRIVE_STRENGTH_4MA 1 746 #define SW_DRIVE_STRENGTH_8MA 2 747 #define SW_DRIVE_STRENGTH_12MA 3 748 #define SW_DRIVE_STRENGTH_16MA 4 749 #define SW_DRIVE_STRENGTH_20MA 5 750 #define SW_DRIVE_STRENGTH_24MA 6 751 #define SW_DRIVE_STRENGTH_28MA 7 752 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 753 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 754 755 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 756 #define KSZ9477_OUT_RATE_NO_LIMIT 0 757 758 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 759 760 #define KSZ9477_PORT_TC_MAP_S 4 761 762 /* CBS related registers */ 763 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 764 765 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 766 767 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 768 #define MTI_SCHEDULE_STRICT_PRIO 0 769 #define MTI_SCHEDULE_WRR 2 770 #define MTI_SHAPING_M GENMASK(5, 4) 771 #define MTI_SHAPING_OFF 0 772 #define MTI_SHAPING_SRP 1 773 #define MTI_SHAPING_TIME_AWARE 2 774 775 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 776 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 777 778 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 779 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 780 781 /* Regmap tables generation */ 782 #define KSZ_SPI_OP_RD 3 783 #define KSZ_SPI_OP_WR 2 784 785 #define swabnot_used(x) 0 786 787 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 788 swab##swp((opcode) << ((regbits) + (regpad))) 789 790 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 791 { \ 792 .name = #width, \ 793 .val_bits = (width), \ 794 .reg_stride = 1, \ 795 .reg_bits = (regbits) + (regalign), \ 796 .pad_bits = (regpad), \ 797 .max_register = BIT(regbits) - 1, \ 798 .cache_type = REGCACHE_NONE, \ 799 .read_flag_mask = \ 800 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 801 regbits, regpad), \ 802 .write_flag_mask = \ 803 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 804 regbits, regpad), \ 805 .lock = ksz_regmap_lock, \ 806 .unlock = ksz_regmap_unlock, \ 807 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 808 .val_format_endian = REGMAP_ENDIAN_BIG \ 809 } 810 811 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 812 static const struct regmap_config ksz##_regmap_config[] = { \ 813 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 814 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 815 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 816 } 817 818 #endif 819