1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 #include <linux/platform_data/microchip-ksz.h> 18 19 #include "ksz_ptp.h" 20 21 #define KSZ_MAX_NUM_PORTS 8 22 23 struct ksz_device; 24 struct ksz_port; 25 26 enum ksz_regmap_width { 27 KSZ_REGMAP_8, 28 KSZ_REGMAP_16, 29 KSZ_REGMAP_32, 30 __KSZ_NUM_REGMAPS, 31 }; 32 33 struct vlan_table { 34 u32 table[3]; 35 }; 36 37 struct ksz_port_mib { 38 struct mutex cnt_mutex; /* structure access */ 39 u8 cnt_ptr; 40 u64 *counters; 41 struct rtnl_link_stats64 stats64; 42 struct ethtool_pause_stats pause_stats; 43 struct spinlock stats64_lock; 44 }; 45 46 struct ksz_mib_names { 47 int index; 48 char string[ETH_GSTRING_LEN]; 49 }; 50 51 struct ksz_chip_data { 52 u32 chip_id; 53 const char *dev_name; 54 int num_vlans; 55 int num_alus; 56 int num_statics; 57 int cpu_ports; 58 int port_cnt; 59 u8 port_nirqs; 60 u8 num_tx_queues; 61 bool tc_cbs_supported; 62 bool tc_ets_supported; 63 const struct ksz_dev_ops *ops; 64 bool ksz87xx_eee_link_erratum; 65 const struct ksz_mib_names *mib_names; 66 int mib_cnt; 67 u8 reg_mib_cnt; 68 const u16 *regs; 69 const u32 *masks; 70 const u8 *shifts; 71 const u8 *xmii_ctrl0; 72 const u8 *xmii_ctrl1; 73 int stp_ctrl_reg; 74 int broadcast_ctrl_reg; 75 int multicast_ctrl_reg; 76 int start_ctrl_reg; 77 bool supports_mii[KSZ_MAX_NUM_PORTS]; 78 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 79 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 80 bool internal_phy[KSZ_MAX_NUM_PORTS]; 81 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 82 const struct regmap_access_table *wr_table; 83 const struct regmap_access_table *rd_table; 84 }; 85 86 struct ksz_irq { 87 u16 masked; 88 u16 reg_mask; 89 u16 reg_status; 90 struct irq_domain *domain; 91 int nirqs; 92 int irq_num; 93 char name[16]; 94 struct ksz_device *dev; 95 }; 96 97 struct ksz_ptp_irq { 98 struct ksz_port *port; 99 u16 ts_reg; 100 bool ts_en; 101 char name[16]; 102 int num; 103 }; 104 105 struct ksz_switch_macaddr { 106 unsigned char addr[ETH_ALEN]; 107 refcount_t refcount; 108 }; 109 110 struct ksz_port { 111 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 112 bool learning; 113 bool isolated; 114 int stp_state; 115 struct phy_device phydev; 116 117 u32 fiber:1; /* port is fiber */ 118 u32 force:1; 119 u32 read:1; /* read MIB counters in background */ 120 u32 freeze:1; /* MIB counter freeze is enabled */ 121 122 struct ksz_port_mib mib; 123 phy_interface_t interface; 124 u32 rgmii_tx_val; 125 u32 rgmii_rx_val; 126 struct ksz_device *ksz_dev; 127 void *acl_priv; 128 struct ksz_irq pirq; 129 u8 num; 130 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 131 struct hwtstamp_config tstamp_config; 132 bool hwts_tx_en; 133 bool hwts_rx_en; 134 struct ksz_irq ptpirq; 135 struct ksz_ptp_irq ptpmsg_irq[3]; 136 ktime_t tstamp_msg; 137 struct completion tstamp_msg_comp; 138 #endif 139 bool manual_flow; 140 }; 141 142 struct ksz_device { 143 struct dsa_switch *ds; 144 struct ksz_platform_data *pdata; 145 const struct ksz_chip_data *info; 146 147 struct mutex dev_mutex; /* device access */ 148 struct mutex regmap_mutex; /* regmap access */ 149 struct mutex alu_mutex; /* ALU access */ 150 struct mutex vlan_mutex; /* vlan access */ 151 const struct ksz_dev_ops *dev_ops; 152 153 struct device *dev; 154 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 155 156 void *priv; 157 int irq; 158 159 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 160 161 /* chip specific data */ 162 u32 chip_id; 163 u8 chip_rev; 164 int cpu_port; /* port connected to CPU */ 165 int phy_port_cnt; 166 phy_interface_t compat_interface; 167 bool synclko_125; 168 bool synclko_disable; 169 bool wakeup_source; 170 171 struct vlan_table *vlan_cache; 172 173 struct ksz_port *ports; 174 struct delayed_work mib_read; 175 unsigned long mib_read_interval; 176 u16 mirror_rx; 177 u16 mirror_tx; 178 u16 port_mask; 179 struct mutex lock_irq; /* IRQ Access */ 180 struct ksz_irq girq; 181 struct ksz_ptp_data ptp_data; 182 183 struct ksz_switch_macaddr *switch_macaddr; 184 struct net_device *hsr_dev; /* HSR */ 185 u8 hsr_ports; 186 }; 187 188 /* List of supported models */ 189 enum ksz_model { 190 KSZ8563, 191 KSZ8567, 192 KSZ8795, 193 KSZ8794, 194 KSZ8765, 195 KSZ8830, 196 KSZ9477, 197 KSZ9896, 198 KSZ9897, 199 KSZ9893, 200 KSZ9563, 201 KSZ9567, 202 LAN9370, 203 LAN9371, 204 LAN9372, 205 LAN9373, 206 LAN9374, 207 }; 208 209 enum ksz_regs { 210 REG_SW_MAC_ADDR, 211 REG_IND_CTRL_0, 212 REG_IND_DATA_8, 213 REG_IND_DATA_CHECK, 214 REG_IND_DATA_HI, 215 REG_IND_DATA_LO, 216 REG_IND_MIB_CHECK, 217 REG_IND_BYTE, 218 P_FORCE_CTRL, 219 P_LINK_STATUS, 220 P_LOCAL_CTRL, 221 P_NEG_RESTART_CTRL, 222 P_REMOTE_STATUS, 223 P_SPEED_STATUS, 224 S_TAIL_TAG_CTRL, 225 P_STP_CTRL, 226 S_START_CTRL, 227 S_BROADCAST_CTRL, 228 S_MULTICAST_CTRL, 229 P_XMII_CTRL_0, 230 P_XMII_CTRL_1, 231 }; 232 233 enum ksz_masks { 234 PORT_802_1P_REMAPPING, 235 SW_TAIL_TAG_ENABLE, 236 MIB_COUNTER_OVERFLOW, 237 MIB_COUNTER_VALID, 238 VLAN_TABLE_FID, 239 VLAN_TABLE_MEMBERSHIP, 240 VLAN_TABLE_VALID, 241 STATIC_MAC_TABLE_VALID, 242 STATIC_MAC_TABLE_USE_FID, 243 STATIC_MAC_TABLE_FID, 244 STATIC_MAC_TABLE_OVERRIDE, 245 STATIC_MAC_TABLE_FWD_PORTS, 246 DYNAMIC_MAC_TABLE_ENTRIES_H, 247 DYNAMIC_MAC_TABLE_MAC_EMPTY, 248 DYNAMIC_MAC_TABLE_NOT_READY, 249 DYNAMIC_MAC_TABLE_ENTRIES, 250 DYNAMIC_MAC_TABLE_FID, 251 DYNAMIC_MAC_TABLE_SRC_PORT, 252 DYNAMIC_MAC_TABLE_TIMESTAMP, 253 ALU_STAT_WRITE, 254 ALU_STAT_READ, 255 P_MII_TX_FLOW_CTRL, 256 P_MII_RX_FLOW_CTRL, 257 }; 258 259 enum ksz_shifts { 260 VLAN_TABLE_MEMBERSHIP_S, 261 VLAN_TABLE, 262 STATIC_MAC_FWD_PORTS, 263 STATIC_MAC_FID, 264 DYNAMIC_MAC_ENTRIES_H, 265 DYNAMIC_MAC_ENTRIES, 266 DYNAMIC_MAC_FID, 267 DYNAMIC_MAC_TIMESTAMP, 268 DYNAMIC_MAC_SRC_PORT, 269 ALU_STAT_INDEX, 270 }; 271 272 enum ksz_xmii_ctrl0 { 273 P_MII_100MBIT, 274 P_MII_10MBIT, 275 P_MII_FULL_DUPLEX, 276 P_MII_HALF_DUPLEX, 277 }; 278 279 enum ksz_xmii_ctrl1 { 280 P_RGMII_SEL, 281 P_RMII_SEL, 282 P_GMII_SEL, 283 P_MII_SEL, 284 P_GMII_1GBIT, 285 P_GMII_NOT_1GBIT, 286 }; 287 288 struct alu_struct { 289 /* entry 1 */ 290 u8 is_static:1; 291 u8 is_src_filter:1; 292 u8 is_dst_filter:1; 293 u8 prio_age:3; 294 u32 _reserv_0_1:23; 295 u8 mstp:3; 296 /* entry 2 */ 297 u8 is_override:1; 298 u8 is_use_fid:1; 299 u32 _reserv_1_1:23; 300 u8 port_forward:7; 301 /* entry 3 & 4*/ 302 u32 _reserv_2_1:9; 303 u8 fid:7; 304 u8 mac[ETH_ALEN]; 305 }; 306 307 struct ksz_dev_ops { 308 int (*setup)(struct dsa_switch *ds); 309 void (*teardown)(struct dsa_switch *ds); 310 u32 (*get_port_addr)(int port, int offset); 311 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 312 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 313 void (*port_cleanup)(struct ksz_device *dev, int port); 314 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 315 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 316 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 317 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 318 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 319 u64 *cnt); 320 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 321 u64 *dropped, u64 *cnt); 322 void (*r_mib_stat64)(struct ksz_device *dev, int port); 323 int (*vlan_filtering)(struct ksz_device *dev, int port, 324 bool flag, struct netlink_ext_ack *extack); 325 int (*vlan_add)(struct ksz_device *dev, int port, 326 const struct switchdev_obj_port_vlan *vlan, 327 struct netlink_ext_ack *extack); 328 int (*vlan_del)(struct ksz_device *dev, int port, 329 const struct switchdev_obj_port_vlan *vlan); 330 int (*mirror_add)(struct ksz_device *dev, int port, 331 struct dsa_mall_mirror_tc_entry *mirror, 332 bool ingress, struct netlink_ext_ack *extack); 333 void (*mirror_del)(struct ksz_device *dev, int port, 334 struct dsa_mall_mirror_tc_entry *mirror); 335 int (*fdb_add)(struct ksz_device *dev, int port, 336 const unsigned char *addr, u16 vid, struct dsa_db db); 337 int (*fdb_del)(struct ksz_device *dev, int port, 338 const unsigned char *addr, u16 vid, struct dsa_db db); 339 int (*fdb_dump)(struct ksz_device *dev, int port, 340 dsa_fdb_dump_cb_t *cb, void *data); 341 int (*mdb_add)(struct ksz_device *dev, int port, 342 const struct switchdev_obj_port_mdb *mdb, 343 struct dsa_db db); 344 int (*mdb_del)(struct ksz_device *dev, int port, 345 const struct switchdev_obj_port_mdb *mdb, 346 struct dsa_db db); 347 void (*get_caps)(struct ksz_device *dev, int port, 348 struct phylink_config *config); 349 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 350 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 351 void (*port_init_cnt)(struct ksz_device *dev, int port); 352 void (*phylink_mac_config)(struct ksz_device *dev, int port, 353 unsigned int mode, 354 const struct phylink_link_state *state); 355 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 356 unsigned int mode, 357 phy_interface_t interface, 358 struct phy_device *phydev, int speed, 359 int duplex, bool tx_pause, bool rx_pause); 360 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 361 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 362 void (*get_wol)(struct ksz_device *dev, int port, 363 struct ethtool_wolinfo *wol); 364 int (*set_wol)(struct ksz_device *dev, int port, 365 struct ethtool_wolinfo *wol); 366 void (*wol_pre_shutdown)(struct ksz_device *dev, bool *wol_enabled); 367 void (*config_cpu_port)(struct dsa_switch *ds); 368 int (*enable_stp_addr)(struct ksz_device *dev); 369 int (*reset)(struct ksz_device *dev); 370 int (*init)(struct ksz_device *dev); 371 void (*exit)(struct ksz_device *dev); 372 }; 373 374 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 375 int ksz_switch_register(struct ksz_device *dev); 376 void ksz_switch_remove(struct ksz_device *dev); 377 378 void ksz_init_mib_timer(struct ksz_device *dev); 379 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port); 380 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 381 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 382 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 383 bool ksz_get_gbit(struct ksz_device *dev, int port); 384 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 385 extern const struct ksz_chip_data ksz_switch_chips[]; 386 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 387 struct netlink_ext_ack *extack); 388 void ksz_switch_macaddr_put(struct dsa_switch *ds); 389 void ksz_switch_shutdown(struct ksz_device *dev); 390 391 /* Common register access functions */ 392 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 393 { 394 return dev->regmap[KSZ_REGMAP_8]; 395 } 396 397 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 398 { 399 return dev->regmap[KSZ_REGMAP_16]; 400 } 401 402 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 403 { 404 return dev->regmap[KSZ_REGMAP_32]; 405 } 406 407 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 408 { 409 unsigned int value; 410 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 411 412 if (ret) 413 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 414 ERR_PTR(ret)); 415 416 *val = value; 417 return ret; 418 } 419 420 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 421 { 422 unsigned int value; 423 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 424 425 if (ret) 426 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 427 ERR_PTR(ret)); 428 429 *val = value; 430 return ret; 431 } 432 433 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 434 { 435 unsigned int value; 436 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 437 438 if (ret) 439 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 440 ERR_PTR(ret)); 441 442 *val = value; 443 return ret; 444 } 445 446 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 447 { 448 u32 value[2]; 449 int ret; 450 451 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 452 if (ret) 453 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 454 ERR_PTR(ret)); 455 else 456 *val = (u64)value[0] << 32 | value[1]; 457 458 return ret; 459 } 460 461 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 462 { 463 int ret; 464 465 ret = regmap_write(ksz_regmap_8(dev), reg, value); 466 if (ret) 467 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 468 ERR_PTR(ret)); 469 470 return ret; 471 } 472 473 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 474 { 475 int ret; 476 477 ret = regmap_write(ksz_regmap_16(dev), reg, value); 478 if (ret) 479 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 480 ERR_PTR(ret)); 481 482 return ret; 483 } 484 485 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 486 { 487 int ret; 488 489 ret = regmap_write(ksz_regmap_32(dev), reg, value); 490 if (ret) 491 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 492 ERR_PTR(ret)); 493 494 return ret; 495 } 496 497 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 498 u16 value) 499 { 500 int ret; 501 502 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 503 if (ret) 504 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 505 ERR_PTR(ret)); 506 507 return ret; 508 } 509 510 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 511 u32 value) 512 { 513 int ret; 514 515 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 516 if (ret) 517 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 518 ERR_PTR(ret)); 519 520 return ret; 521 } 522 523 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 524 { 525 u32 val[2]; 526 527 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 528 value = swab64(value); 529 val[0] = swab32(value & 0xffffffffULL); 530 val[1] = swab32(value >> 32ULL); 531 532 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 533 } 534 535 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 536 { 537 int ret; 538 539 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 540 if (ret) 541 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 542 ERR_PTR(ret)); 543 544 return ret; 545 } 546 547 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 548 u8 *data) 549 { 550 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 551 } 552 553 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 554 u16 *data) 555 { 556 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 557 } 558 559 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 560 u32 *data) 561 { 562 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 563 } 564 565 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 566 u8 data) 567 { 568 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 569 } 570 571 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 572 u16 data) 573 { 574 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 575 data); 576 } 577 578 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 579 u32 data) 580 { 581 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 582 data); 583 } 584 585 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 586 u8 mask, u8 val) 587 { 588 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 589 mask, val); 590 } 591 592 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 593 u32 mask, u32 val) 594 { 595 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 596 mask, val); 597 } 598 599 static inline void ksz_regmap_lock(void *__mtx) 600 { 601 struct mutex *mtx = __mtx; 602 mutex_lock(mtx); 603 } 604 605 static inline void ksz_regmap_unlock(void *__mtx) 606 { 607 struct mutex *mtx = __mtx; 608 mutex_unlock(mtx); 609 } 610 611 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 612 { 613 return dev->chip_id == KSZ8795_CHIP_ID || 614 dev->chip_id == KSZ8794_CHIP_ID || 615 dev->chip_id == KSZ8765_CHIP_ID; 616 } 617 618 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 619 { 620 return dev->chip_id == KSZ8830_CHIP_ID; 621 } 622 623 static inline int is_lan937x(struct ksz_device *dev) 624 { 625 return dev->chip_id == LAN9370_CHIP_ID || 626 dev->chip_id == LAN9371_CHIP_ID || 627 dev->chip_id == LAN9372_CHIP_ID || 628 dev->chip_id == LAN9373_CHIP_ID || 629 dev->chip_id == LAN9374_CHIP_ID; 630 } 631 632 /* STP State Defines */ 633 #define PORT_TX_ENABLE BIT(2) 634 #define PORT_RX_ENABLE BIT(1) 635 #define PORT_LEARN_DISABLE BIT(0) 636 637 /* Switch ID Defines */ 638 #define REG_CHIP_ID0 0x00 639 640 #define SW_FAMILY_ID_M GENMASK(15, 8) 641 #define KSZ87_FAMILY_ID 0x87 642 #define KSZ88_FAMILY_ID 0x88 643 644 #define KSZ8_PORT_STATUS_0 0x08 645 #define KSZ8_PORT_FIBER_MODE BIT(7) 646 647 #define SW_CHIP_ID_M GENMASK(7, 4) 648 #define KSZ87_CHIP_ID_94 0x6 649 #define KSZ87_CHIP_ID_95 0x9 650 #define KSZ88_CHIP_ID_63 0x3 651 652 #define SW_REV_ID_M GENMASK(7, 4) 653 654 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 655 #define REG_CHIP_ID4 0x0f 656 #define SKU_ID_KSZ8563 0x3c 657 #define SKU_ID_KSZ9563 0x1c 658 659 /* Driver set switch broadcast storm protection at 10% rate. */ 660 #define BROADCAST_STORM_PROT_RATE 10 661 662 /* 148,800 frames * 67 ms / 100 */ 663 #define BROADCAST_STORM_VALUE 9969 664 665 #define BROADCAST_STORM_RATE_HI 0x07 666 #define BROADCAST_STORM_RATE_LO 0xFF 667 #define BROADCAST_STORM_RATE 0x07FF 668 669 #define MULTICAST_STORM_DISABLE BIT(6) 670 671 #define SW_START 0x01 672 673 /* xMII configuration */ 674 #define P_MII_DUPLEX_M BIT(6) 675 #define P_MII_100MBIT_M BIT(4) 676 677 #define P_GMII_1GBIT_M BIT(6) 678 #define P_RGMII_ID_IG_ENABLE BIT(4) 679 #define P_RGMII_ID_EG_ENABLE BIT(3) 680 #define P_MII_MAC_MODE BIT(2) 681 #define P_MII_SEL_M 0x3 682 683 /* Interrupt */ 684 #define REG_SW_PORT_INT_STATUS__1 0x001B 685 #define REG_SW_PORT_INT_MASK__1 0x001F 686 687 #define REG_PORT_INT_STATUS 0x001B 688 #define REG_PORT_INT_MASK 0x001F 689 690 #define PORT_SRC_PHY_INT 1 691 #define PORT_SRC_PTP_INT 2 692 693 #define KSZ8795_HUGE_PACKET_SIZE 2000 694 #define KSZ8863_HUGE_PACKET_SIZE 1916 695 #define KSZ8863_NORMAL_PACKET_SIZE 1536 696 #define KSZ8_LEGAL_PACKET_SIZE 1518 697 #define KSZ9477_MAX_FRAME_SIZE 9000 698 699 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 700 /* Drive Strength of I/O Pad 701 * 0: 8mA, 1: 16mA 702 */ 703 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 704 705 #define KSZ8795_REG_SW_CTRL_20 0xa3 706 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 707 #define SW_DRIVE_STRENGTH_M 0x7 708 #define SW_DRIVE_STRENGTH_2MA 0 709 #define SW_DRIVE_STRENGTH_4MA 1 710 #define SW_DRIVE_STRENGTH_8MA 2 711 #define SW_DRIVE_STRENGTH_12MA 3 712 #define SW_DRIVE_STRENGTH_16MA 4 713 #define SW_DRIVE_STRENGTH_20MA 5 714 #define SW_DRIVE_STRENGTH_24MA 6 715 #define SW_DRIVE_STRENGTH_28MA 7 716 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 717 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 718 719 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 720 #define KSZ9477_OUT_RATE_NO_LIMIT 0 721 722 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 723 724 #define KSZ9477_PORT_TC_MAP_S 4 725 #define KSZ9477_MAX_TC_PRIO 7 726 727 /* CBS related registers */ 728 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 729 730 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 731 732 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 733 #define MTI_SCHEDULE_STRICT_PRIO 0 734 #define MTI_SCHEDULE_WRR 2 735 #define MTI_SHAPING_M GENMASK(5, 4) 736 #define MTI_SHAPING_OFF 0 737 #define MTI_SHAPING_SRP 1 738 #define MTI_SHAPING_TIME_AWARE 2 739 740 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 741 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 742 743 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 744 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 745 746 /* Regmap tables generation */ 747 #define KSZ_SPI_OP_RD 3 748 #define KSZ_SPI_OP_WR 2 749 750 #define swabnot_used(x) 0 751 752 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 753 swab##swp((opcode) << ((regbits) + (regpad))) 754 755 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 756 { \ 757 .name = #width, \ 758 .val_bits = (width), \ 759 .reg_stride = 1, \ 760 .reg_bits = (regbits) + (regalign), \ 761 .pad_bits = (regpad), \ 762 .max_register = BIT(regbits) - 1, \ 763 .cache_type = REGCACHE_NONE, \ 764 .read_flag_mask = \ 765 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 766 regbits, regpad), \ 767 .write_flag_mask = \ 768 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 769 regbits, regpad), \ 770 .lock = ksz_regmap_lock, \ 771 .unlock = ksz_regmap_unlock, \ 772 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 773 .val_format_endian = REGMAP_ENDIAN_BIG \ 774 } 775 776 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 777 static const struct regmap_config ksz##_regmap_config[] = { \ 778 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 779 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 780 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 781 } 782 783 #endif 784