1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 18 #define KSZ_MAX_NUM_PORTS 8 19 20 struct ksz_device; 21 22 struct vlan_table { 23 u32 table[3]; 24 }; 25 26 struct ksz_port_mib { 27 struct mutex cnt_mutex; /* structure access */ 28 u8 cnt_ptr; 29 u64 *counters; 30 struct rtnl_link_stats64 stats64; 31 struct ethtool_pause_stats pause_stats; 32 struct spinlock stats64_lock; 33 }; 34 35 struct ksz_mib_names { 36 int index; 37 char string[ETH_GSTRING_LEN]; 38 }; 39 40 struct ksz_chip_data { 41 u32 chip_id; 42 const char *dev_name; 43 int num_vlans; 44 int num_alus; 45 int num_statics; 46 int cpu_ports; 47 int port_cnt; 48 const struct ksz_dev_ops *ops; 49 bool phy_errata_9477; 50 bool ksz87xx_eee_link_erratum; 51 const struct ksz_mib_names *mib_names; 52 int mib_cnt; 53 u8 reg_mib_cnt; 54 const u16 *regs; 55 const u32 *masks; 56 const u8 *shifts; 57 const u8 *xmii_ctrl0; 58 const u8 *xmii_ctrl1; 59 int stp_ctrl_reg; 60 int broadcast_ctrl_reg; 61 int multicast_ctrl_reg; 62 int start_ctrl_reg; 63 bool supports_mii[KSZ_MAX_NUM_PORTS]; 64 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 65 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 66 bool internal_phy[KSZ_MAX_NUM_PORTS]; 67 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 68 const struct regmap_access_table *wr_table; 69 const struct regmap_access_table *rd_table; 70 }; 71 72 struct ksz_irq { 73 u16 masked; 74 struct irq_chip chip; 75 struct irq_domain *domain; 76 int nirqs; 77 char name[16]; 78 }; 79 80 struct ksz_port { 81 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 82 bool learning; 83 int stp_state; 84 struct phy_device phydev; 85 86 u32 on:1; /* port is not disabled by hardware */ 87 u32 fiber:1; /* port is fiber */ 88 u32 force:1; 89 u32 read:1; /* read MIB counters in background */ 90 u32 freeze:1; /* MIB counter freeze is enabled */ 91 92 struct ksz_port_mib mib; 93 phy_interface_t interface; 94 u16 max_frame; 95 u32 rgmii_tx_val; 96 u32 rgmii_rx_val; 97 struct ksz_device *ksz_dev; 98 struct ksz_irq pirq; 99 u8 num; 100 }; 101 102 struct ksz_device { 103 struct dsa_switch *ds; 104 struct ksz_platform_data *pdata; 105 const struct ksz_chip_data *info; 106 107 struct mutex dev_mutex; /* device access */ 108 struct mutex regmap_mutex; /* regmap access */ 109 struct mutex alu_mutex; /* ALU access */ 110 struct mutex vlan_mutex; /* vlan access */ 111 const struct ksz_dev_ops *dev_ops; 112 113 struct device *dev; 114 struct regmap *regmap[3]; 115 116 void *priv; 117 int irq; 118 119 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 120 121 /* chip specific data */ 122 u32 chip_id; 123 u8 chip_rev; 124 int cpu_port; /* port connected to CPU */ 125 int phy_port_cnt; 126 phy_interface_t compat_interface; 127 bool synclko_125; 128 bool synclko_disable; 129 130 struct vlan_table *vlan_cache; 131 132 struct ksz_port *ports; 133 struct delayed_work mib_read; 134 unsigned long mib_read_interval; 135 u16 mirror_rx; 136 u16 mirror_tx; 137 u16 port_mask; 138 struct mutex lock_irq; /* IRQ Access */ 139 struct ksz_irq girq; 140 }; 141 142 /* List of supported models */ 143 enum ksz_model { 144 KSZ8563, 145 KSZ8795, 146 KSZ8794, 147 KSZ8765, 148 KSZ8830, 149 KSZ9477, 150 KSZ9896, 151 KSZ9897, 152 KSZ9893, 153 KSZ9567, 154 LAN9370, 155 LAN9371, 156 LAN9372, 157 LAN9373, 158 LAN9374, 159 }; 160 161 enum ksz_chip_id { 162 KSZ8563_CHIP_ID = 0x8563, 163 KSZ8795_CHIP_ID = 0x8795, 164 KSZ8794_CHIP_ID = 0x8794, 165 KSZ8765_CHIP_ID = 0x8765, 166 KSZ8830_CHIP_ID = 0x8830, 167 KSZ9477_CHIP_ID = 0x00947700, 168 KSZ9896_CHIP_ID = 0x00989600, 169 KSZ9897_CHIP_ID = 0x00989700, 170 KSZ9893_CHIP_ID = 0x00989300, 171 KSZ9567_CHIP_ID = 0x00956700, 172 LAN9370_CHIP_ID = 0x00937000, 173 LAN9371_CHIP_ID = 0x00937100, 174 LAN9372_CHIP_ID = 0x00937200, 175 LAN9373_CHIP_ID = 0x00937300, 176 LAN9374_CHIP_ID = 0x00937400, 177 }; 178 179 enum ksz_regs { 180 REG_IND_CTRL_0, 181 REG_IND_DATA_8, 182 REG_IND_DATA_CHECK, 183 REG_IND_DATA_HI, 184 REG_IND_DATA_LO, 185 REG_IND_MIB_CHECK, 186 REG_IND_BYTE, 187 P_FORCE_CTRL, 188 P_LINK_STATUS, 189 P_LOCAL_CTRL, 190 P_NEG_RESTART_CTRL, 191 P_REMOTE_STATUS, 192 P_SPEED_STATUS, 193 S_TAIL_TAG_CTRL, 194 P_STP_CTRL, 195 S_START_CTRL, 196 S_BROADCAST_CTRL, 197 S_MULTICAST_CTRL, 198 P_XMII_CTRL_0, 199 P_XMII_CTRL_1, 200 }; 201 202 enum ksz_masks { 203 PORT_802_1P_REMAPPING, 204 SW_TAIL_TAG_ENABLE, 205 MIB_COUNTER_OVERFLOW, 206 MIB_COUNTER_VALID, 207 VLAN_TABLE_FID, 208 VLAN_TABLE_MEMBERSHIP, 209 VLAN_TABLE_VALID, 210 STATIC_MAC_TABLE_VALID, 211 STATIC_MAC_TABLE_USE_FID, 212 STATIC_MAC_TABLE_FID, 213 STATIC_MAC_TABLE_OVERRIDE, 214 STATIC_MAC_TABLE_FWD_PORTS, 215 DYNAMIC_MAC_TABLE_ENTRIES_H, 216 DYNAMIC_MAC_TABLE_MAC_EMPTY, 217 DYNAMIC_MAC_TABLE_NOT_READY, 218 DYNAMIC_MAC_TABLE_ENTRIES, 219 DYNAMIC_MAC_TABLE_FID, 220 DYNAMIC_MAC_TABLE_SRC_PORT, 221 DYNAMIC_MAC_TABLE_TIMESTAMP, 222 ALU_STAT_WRITE, 223 ALU_STAT_READ, 224 P_MII_TX_FLOW_CTRL, 225 P_MII_RX_FLOW_CTRL, 226 }; 227 228 enum ksz_shifts { 229 VLAN_TABLE_MEMBERSHIP_S, 230 VLAN_TABLE, 231 STATIC_MAC_FWD_PORTS, 232 STATIC_MAC_FID, 233 DYNAMIC_MAC_ENTRIES_H, 234 DYNAMIC_MAC_ENTRIES, 235 DYNAMIC_MAC_FID, 236 DYNAMIC_MAC_TIMESTAMP, 237 DYNAMIC_MAC_SRC_PORT, 238 ALU_STAT_INDEX, 239 }; 240 241 enum ksz_xmii_ctrl0 { 242 P_MII_100MBIT, 243 P_MII_10MBIT, 244 P_MII_FULL_DUPLEX, 245 P_MII_HALF_DUPLEX, 246 }; 247 248 enum ksz_xmii_ctrl1 { 249 P_RGMII_SEL, 250 P_RMII_SEL, 251 P_GMII_SEL, 252 P_MII_SEL, 253 P_GMII_1GBIT, 254 P_GMII_NOT_1GBIT, 255 }; 256 257 struct alu_struct { 258 /* entry 1 */ 259 u8 is_static:1; 260 u8 is_src_filter:1; 261 u8 is_dst_filter:1; 262 u8 prio_age:3; 263 u32 _reserv_0_1:23; 264 u8 mstp:3; 265 /* entry 2 */ 266 u8 is_override:1; 267 u8 is_use_fid:1; 268 u32 _reserv_1_1:23; 269 u8 port_forward:7; 270 /* entry 3 & 4*/ 271 u32 _reserv_2_1:9; 272 u8 fid:7; 273 u8 mac[ETH_ALEN]; 274 }; 275 276 struct ksz_dev_ops { 277 int (*setup)(struct dsa_switch *ds); 278 void (*teardown)(struct dsa_switch *ds); 279 u32 (*get_port_addr)(int port, int offset); 280 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 281 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 282 void (*port_cleanup)(struct ksz_device *dev, int port); 283 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 284 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 285 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 286 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 287 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 288 u64 *cnt); 289 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 290 u64 *dropped, u64 *cnt); 291 void (*r_mib_stat64)(struct ksz_device *dev, int port); 292 int (*vlan_filtering)(struct ksz_device *dev, int port, 293 bool flag, struct netlink_ext_ack *extack); 294 int (*vlan_add)(struct ksz_device *dev, int port, 295 const struct switchdev_obj_port_vlan *vlan, 296 struct netlink_ext_ack *extack); 297 int (*vlan_del)(struct ksz_device *dev, int port, 298 const struct switchdev_obj_port_vlan *vlan); 299 int (*mirror_add)(struct ksz_device *dev, int port, 300 struct dsa_mall_mirror_tc_entry *mirror, 301 bool ingress, struct netlink_ext_ack *extack); 302 void (*mirror_del)(struct ksz_device *dev, int port, 303 struct dsa_mall_mirror_tc_entry *mirror); 304 int (*fdb_add)(struct ksz_device *dev, int port, 305 const unsigned char *addr, u16 vid, struct dsa_db db); 306 int (*fdb_del)(struct ksz_device *dev, int port, 307 const unsigned char *addr, u16 vid, struct dsa_db db); 308 int (*fdb_dump)(struct ksz_device *dev, int port, 309 dsa_fdb_dump_cb_t *cb, void *data); 310 int (*mdb_add)(struct ksz_device *dev, int port, 311 const struct switchdev_obj_port_mdb *mdb, 312 struct dsa_db db); 313 int (*mdb_del)(struct ksz_device *dev, int port, 314 const struct switchdev_obj_port_mdb *mdb, 315 struct dsa_db db); 316 void (*get_caps)(struct ksz_device *dev, int port, 317 struct phylink_config *config); 318 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 319 int (*max_mtu)(struct ksz_device *dev, int port); 320 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 321 void (*port_init_cnt)(struct ksz_device *dev, int port); 322 void (*phylink_mac_config)(struct ksz_device *dev, int port, 323 unsigned int mode, 324 const struct phylink_link_state *state); 325 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 326 unsigned int mode, 327 phy_interface_t interface, 328 struct phy_device *phydev, int speed, 329 int duplex, bool tx_pause, bool rx_pause); 330 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 331 void (*config_cpu_port)(struct dsa_switch *ds); 332 int (*enable_stp_addr)(struct ksz_device *dev); 333 int (*reset)(struct ksz_device *dev); 334 int (*init)(struct ksz_device *dev); 335 void (*exit)(struct ksz_device *dev); 336 }; 337 338 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 339 int ksz_switch_register(struct ksz_device *dev); 340 void ksz_switch_remove(struct ksz_device *dev); 341 342 void ksz_init_mib_timer(struct ksz_device *dev); 343 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 344 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 345 bool ksz_get_gbit(struct ksz_device *dev, int port); 346 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 347 extern const struct ksz_chip_data ksz_switch_chips[]; 348 349 /* Common register access functions */ 350 351 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 352 { 353 unsigned int value; 354 int ret = regmap_read(dev->regmap[0], reg, &value); 355 356 if (ret) 357 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 358 ERR_PTR(ret)); 359 360 *val = value; 361 return ret; 362 } 363 364 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 365 { 366 unsigned int value; 367 int ret = regmap_read(dev->regmap[1], reg, &value); 368 369 if (ret) 370 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 371 ERR_PTR(ret)); 372 373 *val = value; 374 return ret; 375 } 376 377 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 378 { 379 unsigned int value; 380 int ret = regmap_read(dev->regmap[2], reg, &value); 381 382 if (ret) 383 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 384 ERR_PTR(ret)); 385 386 *val = value; 387 return ret; 388 } 389 390 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 391 { 392 u32 value[2]; 393 int ret; 394 395 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); 396 if (ret) 397 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 398 ERR_PTR(ret)); 399 else 400 *val = (u64)value[0] << 32 | value[1]; 401 402 return ret; 403 } 404 405 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 406 { 407 int ret; 408 409 ret = regmap_write(dev->regmap[0], reg, value); 410 if (ret) 411 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 412 ERR_PTR(ret)); 413 414 return ret; 415 } 416 417 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 418 { 419 int ret; 420 421 ret = regmap_write(dev->regmap[1], reg, value); 422 if (ret) 423 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 424 ERR_PTR(ret)); 425 426 return ret; 427 } 428 429 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 430 { 431 int ret; 432 433 ret = regmap_write(dev->regmap[2], reg, value); 434 if (ret) 435 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 436 ERR_PTR(ret)); 437 438 return ret; 439 } 440 441 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 442 { 443 u32 val[2]; 444 445 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 446 value = swab64(value); 447 val[0] = swab32(value & 0xffffffffULL); 448 val[1] = swab32(value >> 32ULL); 449 450 return regmap_bulk_write(dev->regmap[2], reg, val, 2); 451 } 452 453 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 454 u8 *data) 455 { 456 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 457 } 458 459 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 460 u16 *data) 461 { 462 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 463 } 464 465 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 466 u32 *data) 467 { 468 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 469 } 470 471 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 472 u8 data) 473 { 474 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 475 } 476 477 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 478 u16 data) 479 { 480 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 481 data); 482 } 483 484 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 485 u32 data) 486 { 487 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 488 data); 489 } 490 491 static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset, 492 u8 mask, u8 val) 493 { 494 regmap_update_bits(dev->regmap[0], 495 dev->dev_ops->get_port_addr(port, offset), 496 mask, val); 497 } 498 499 static inline void ksz_regmap_lock(void *__mtx) 500 { 501 struct mutex *mtx = __mtx; 502 mutex_lock(mtx); 503 } 504 505 static inline void ksz_regmap_unlock(void *__mtx) 506 { 507 struct mutex *mtx = __mtx; 508 mutex_unlock(mtx); 509 } 510 511 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 512 { 513 return dev->chip_id == KSZ8830_CHIP_ID; 514 } 515 516 static inline int is_lan937x(struct ksz_device *dev) 517 { 518 return dev->chip_id == LAN9370_CHIP_ID || 519 dev->chip_id == LAN9371_CHIP_ID || 520 dev->chip_id == LAN9372_CHIP_ID || 521 dev->chip_id == LAN9373_CHIP_ID || 522 dev->chip_id == LAN9374_CHIP_ID; 523 } 524 525 /* STP State Defines */ 526 #define PORT_TX_ENABLE BIT(2) 527 #define PORT_RX_ENABLE BIT(1) 528 #define PORT_LEARN_DISABLE BIT(0) 529 530 /* Switch ID Defines */ 531 #define REG_CHIP_ID0 0x00 532 533 #define SW_FAMILY_ID_M GENMASK(15, 8) 534 #define KSZ87_FAMILY_ID 0x87 535 #define KSZ88_FAMILY_ID 0x88 536 537 #define KSZ8_PORT_STATUS_0 0x08 538 #define KSZ8_PORT_FIBER_MODE BIT(7) 539 540 #define SW_CHIP_ID_M GENMASK(7, 4) 541 #define KSZ87_CHIP_ID_94 0x6 542 #define KSZ87_CHIP_ID_95 0x9 543 #define KSZ88_CHIP_ID_63 0x3 544 545 #define SW_REV_ID_M GENMASK(7, 4) 546 547 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 548 #define REG_CHIP_ID4 0x0f 549 #define SKU_ID_KSZ8563 0x3c 550 551 /* Driver set switch broadcast storm protection at 10% rate. */ 552 #define BROADCAST_STORM_PROT_RATE 10 553 554 /* 148,800 frames * 67 ms / 100 */ 555 #define BROADCAST_STORM_VALUE 9969 556 557 #define BROADCAST_STORM_RATE_HI 0x07 558 #define BROADCAST_STORM_RATE_LO 0xFF 559 #define BROADCAST_STORM_RATE 0x07FF 560 561 #define MULTICAST_STORM_DISABLE BIT(6) 562 563 #define SW_START 0x01 564 565 /* xMII configuration */ 566 #define P_MII_DUPLEX_M BIT(6) 567 #define P_MII_100MBIT_M BIT(4) 568 569 #define P_GMII_1GBIT_M BIT(6) 570 #define P_RGMII_ID_IG_ENABLE BIT(4) 571 #define P_RGMII_ID_EG_ENABLE BIT(3) 572 #define P_MII_MAC_MODE BIT(2) 573 #define P_MII_SEL_M 0x3 574 575 /* Regmap tables generation */ 576 #define KSZ_SPI_OP_RD 3 577 #define KSZ_SPI_OP_WR 2 578 579 #define swabnot_used(x) 0 580 581 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 582 swab##swp((opcode) << ((regbits) + (regpad))) 583 584 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 585 { \ 586 .name = #width, \ 587 .val_bits = (width), \ 588 .reg_stride = 1, \ 589 .reg_bits = (regbits) + (regalign), \ 590 .pad_bits = (regpad), \ 591 .max_register = BIT(regbits) - 1, \ 592 .cache_type = REGCACHE_NONE, \ 593 .read_flag_mask = \ 594 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 595 regbits, regpad), \ 596 .write_flag_mask = \ 597 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 598 regbits, regpad), \ 599 .lock = ksz_regmap_lock, \ 600 .unlock = ksz_regmap_unlock, \ 601 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 602 .val_format_endian = REGMAP_ENDIAN_BIG \ 603 } 604 605 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 606 static const struct regmap_config ksz##_regmap_config[] = { \ 607 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 608 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 609 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 610 } 611 612 #endif 613