1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 #include <linux/platform_data/microchip-ksz.h> 18 19 #include "ksz_ptp.h" 20 21 #define KSZ_MAX_NUM_PORTS 8 22 /* all KSZ switches count ports from 1 */ 23 #define KSZ_PORT_1 0 24 #define KSZ_PORT_2 1 25 26 struct ksz_device; 27 struct ksz_port; 28 struct phylink_mac_ops; 29 30 enum ksz_regmap_width { 31 KSZ_REGMAP_8, 32 KSZ_REGMAP_16, 33 KSZ_REGMAP_32, 34 __KSZ_NUM_REGMAPS, 35 }; 36 37 struct vlan_table { 38 u32 table[3]; 39 }; 40 41 struct ksz_port_mib { 42 struct mutex cnt_mutex; /* structure access */ 43 u8 cnt_ptr; 44 u64 *counters; 45 struct rtnl_link_stats64 stats64; 46 struct ethtool_pause_stats pause_stats; 47 struct spinlock stats64_lock; 48 }; 49 50 struct ksz_mib_names { 51 int index; 52 char string[ETH_GSTRING_LEN]; 53 }; 54 55 struct ksz_chip_data { 56 u32 chip_id; 57 const char *dev_name; 58 int num_vlans; 59 int num_alus; 60 int num_statics; 61 int cpu_ports; 62 int port_cnt; 63 u8 port_nirqs; 64 u8 num_tx_queues; 65 u8 num_ipms; /* number of Internal Priority Maps */ 66 bool tc_cbs_supported; 67 const struct ksz_dev_ops *ops; 68 const struct phylink_mac_ops *phylink_mac_ops; 69 bool phy_errata_9477; 70 bool ksz87xx_eee_link_erratum; 71 const struct ksz_mib_names *mib_names; 72 int mib_cnt; 73 u8 reg_mib_cnt; 74 const u16 *regs; 75 const u32 *masks; 76 const u8 *shifts; 77 const u8 *xmii_ctrl0; 78 const u8 *xmii_ctrl1; 79 int stp_ctrl_reg; 80 int broadcast_ctrl_reg; 81 int multicast_ctrl_reg; 82 int start_ctrl_reg; 83 bool supports_mii[KSZ_MAX_NUM_PORTS]; 84 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 85 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 86 bool internal_phy[KSZ_MAX_NUM_PORTS]; 87 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 88 const struct regmap_access_table *wr_table; 89 const struct regmap_access_table *rd_table; 90 }; 91 92 struct ksz_irq { 93 u16 masked; 94 u16 reg_mask; 95 u16 reg_status; 96 struct irq_domain *domain; 97 int nirqs; 98 int irq_num; 99 char name[16]; 100 struct ksz_device *dev; 101 }; 102 103 struct ksz_ptp_irq { 104 struct ksz_port *port; 105 u16 ts_reg; 106 bool ts_en; 107 char name[16]; 108 int num; 109 }; 110 111 struct ksz_switch_macaddr { 112 unsigned char addr[ETH_ALEN]; 113 refcount_t refcount; 114 }; 115 116 struct ksz_port { 117 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 118 bool learning; 119 bool isolated; 120 int stp_state; 121 struct phy_device phydev; 122 123 u32 fiber:1; /* port is fiber */ 124 u32 force:1; 125 u32 read:1; /* read MIB counters in background */ 126 u32 freeze:1; /* MIB counter freeze is enabled */ 127 128 struct ksz_port_mib mib; 129 phy_interface_t interface; 130 u32 rgmii_tx_val; 131 u32 rgmii_rx_val; 132 struct ksz_device *ksz_dev; 133 void *acl_priv; 134 struct ksz_irq pirq; 135 u8 num; 136 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 137 struct hwtstamp_config tstamp_config; 138 bool hwts_tx_en; 139 bool hwts_rx_en; 140 struct ksz_irq ptpirq; 141 struct ksz_ptp_irq ptpmsg_irq[3]; 142 ktime_t tstamp_msg; 143 struct completion tstamp_msg_comp; 144 #endif 145 bool manual_flow; 146 }; 147 148 struct ksz_device { 149 struct dsa_switch *ds; 150 struct ksz_platform_data *pdata; 151 const struct ksz_chip_data *info; 152 153 struct mutex dev_mutex; /* device access */ 154 struct mutex regmap_mutex; /* regmap access */ 155 struct mutex alu_mutex; /* ALU access */ 156 struct mutex vlan_mutex; /* vlan access */ 157 const struct ksz_dev_ops *dev_ops; 158 159 struct device *dev; 160 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 161 162 void *priv; 163 int irq; 164 165 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 166 167 /* chip specific data */ 168 u32 chip_id; 169 u8 chip_rev; 170 int cpu_port; /* port connected to CPU */ 171 int phy_port_cnt; 172 phy_interface_t compat_interface; 173 bool synclko_125; 174 bool synclko_disable; 175 bool wakeup_source; 176 177 struct vlan_table *vlan_cache; 178 179 struct ksz_port *ports; 180 struct delayed_work mib_read; 181 unsigned long mib_read_interval; 182 u16 mirror_rx; 183 u16 mirror_tx; 184 u16 port_mask; 185 struct mutex lock_irq; /* IRQ Access */ 186 struct ksz_irq girq; 187 struct ksz_ptp_data ptp_data; 188 189 struct ksz_switch_macaddr *switch_macaddr; 190 struct net_device *hsr_dev; /* HSR */ 191 u8 hsr_ports; 192 }; 193 194 /* List of supported models */ 195 enum ksz_model { 196 KSZ8563, 197 KSZ8567, 198 KSZ8795, 199 KSZ8794, 200 KSZ8765, 201 KSZ8830, 202 KSZ9477, 203 KSZ9896, 204 KSZ9897, 205 KSZ9893, 206 KSZ9563, 207 KSZ9567, 208 LAN9370, 209 LAN9371, 210 LAN9372, 211 LAN9373, 212 LAN9374, 213 }; 214 215 enum ksz_regs { 216 REG_SW_MAC_ADDR, 217 REG_IND_CTRL_0, 218 REG_IND_DATA_8, 219 REG_IND_DATA_CHECK, 220 REG_IND_DATA_HI, 221 REG_IND_DATA_LO, 222 REG_IND_MIB_CHECK, 223 REG_IND_BYTE, 224 P_FORCE_CTRL, 225 P_LINK_STATUS, 226 P_LOCAL_CTRL, 227 P_NEG_RESTART_CTRL, 228 P_REMOTE_STATUS, 229 P_SPEED_STATUS, 230 S_TAIL_TAG_CTRL, 231 P_STP_CTRL, 232 S_START_CTRL, 233 S_BROADCAST_CTRL, 234 S_MULTICAST_CTRL, 235 P_XMII_CTRL_0, 236 P_XMII_CTRL_1, 237 }; 238 239 enum ksz_masks { 240 PORT_802_1P_REMAPPING, 241 SW_TAIL_TAG_ENABLE, 242 MIB_COUNTER_OVERFLOW, 243 MIB_COUNTER_VALID, 244 VLAN_TABLE_FID, 245 VLAN_TABLE_MEMBERSHIP, 246 VLAN_TABLE_VALID, 247 STATIC_MAC_TABLE_VALID, 248 STATIC_MAC_TABLE_USE_FID, 249 STATIC_MAC_TABLE_FID, 250 STATIC_MAC_TABLE_OVERRIDE, 251 STATIC_MAC_TABLE_FWD_PORTS, 252 DYNAMIC_MAC_TABLE_ENTRIES_H, 253 DYNAMIC_MAC_TABLE_MAC_EMPTY, 254 DYNAMIC_MAC_TABLE_NOT_READY, 255 DYNAMIC_MAC_TABLE_ENTRIES, 256 DYNAMIC_MAC_TABLE_FID, 257 DYNAMIC_MAC_TABLE_SRC_PORT, 258 DYNAMIC_MAC_TABLE_TIMESTAMP, 259 ALU_STAT_WRITE, 260 ALU_STAT_READ, 261 P_MII_TX_FLOW_CTRL, 262 P_MII_RX_FLOW_CTRL, 263 }; 264 265 enum ksz_shifts { 266 VLAN_TABLE_MEMBERSHIP_S, 267 VLAN_TABLE, 268 STATIC_MAC_FWD_PORTS, 269 STATIC_MAC_FID, 270 DYNAMIC_MAC_ENTRIES_H, 271 DYNAMIC_MAC_ENTRIES, 272 DYNAMIC_MAC_FID, 273 DYNAMIC_MAC_TIMESTAMP, 274 DYNAMIC_MAC_SRC_PORT, 275 ALU_STAT_INDEX, 276 }; 277 278 enum ksz_xmii_ctrl0 { 279 P_MII_100MBIT, 280 P_MII_10MBIT, 281 P_MII_FULL_DUPLEX, 282 P_MII_HALF_DUPLEX, 283 }; 284 285 enum ksz_xmii_ctrl1 { 286 P_RGMII_SEL, 287 P_RMII_SEL, 288 P_GMII_SEL, 289 P_MII_SEL, 290 P_GMII_1GBIT, 291 P_GMII_NOT_1GBIT, 292 }; 293 294 struct alu_struct { 295 /* entry 1 */ 296 u8 is_static:1; 297 u8 is_src_filter:1; 298 u8 is_dst_filter:1; 299 u8 prio_age:3; 300 u32 _reserv_0_1:23; 301 u8 mstp:3; 302 /* entry 2 */ 303 u8 is_override:1; 304 u8 is_use_fid:1; 305 u32 _reserv_1_1:23; 306 u8 port_forward:7; 307 /* entry 3 & 4*/ 308 u32 _reserv_2_1:9; 309 u8 fid:7; 310 u8 mac[ETH_ALEN]; 311 }; 312 313 struct ksz_dev_ops { 314 int (*setup)(struct dsa_switch *ds); 315 void (*teardown)(struct dsa_switch *ds); 316 u32 (*get_port_addr)(int port, int offset); 317 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 318 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 319 void (*port_cleanup)(struct ksz_device *dev, int port); 320 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 321 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 322 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 323 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 324 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 325 u64 *cnt); 326 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 327 u64 *dropped, u64 *cnt); 328 void (*r_mib_stat64)(struct ksz_device *dev, int port); 329 int (*vlan_filtering)(struct ksz_device *dev, int port, 330 bool flag, struct netlink_ext_ack *extack); 331 int (*vlan_add)(struct ksz_device *dev, int port, 332 const struct switchdev_obj_port_vlan *vlan, 333 struct netlink_ext_ack *extack); 334 int (*vlan_del)(struct ksz_device *dev, int port, 335 const struct switchdev_obj_port_vlan *vlan); 336 int (*mirror_add)(struct ksz_device *dev, int port, 337 struct dsa_mall_mirror_tc_entry *mirror, 338 bool ingress, struct netlink_ext_ack *extack); 339 void (*mirror_del)(struct ksz_device *dev, int port, 340 struct dsa_mall_mirror_tc_entry *mirror); 341 int (*fdb_add)(struct ksz_device *dev, int port, 342 const unsigned char *addr, u16 vid, struct dsa_db db); 343 int (*fdb_del)(struct ksz_device *dev, int port, 344 const unsigned char *addr, u16 vid, struct dsa_db db); 345 int (*fdb_dump)(struct ksz_device *dev, int port, 346 dsa_fdb_dump_cb_t *cb, void *data); 347 int (*mdb_add)(struct ksz_device *dev, int port, 348 const struct switchdev_obj_port_mdb *mdb, 349 struct dsa_db db); 350 int (*mdb_del)(struct ksz_device *dev, int port, 351 const struct switchdev_obj_port_mdb *mdb, 352 struct dsa_db db); 353 void (*get_caps)(struct ksz_device *dev, int port, 354 struct phylink_config *config); 355 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 356 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 357 void (*port_init_cnt)(struct ksz_device *dev, int port); 358 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 359 unsigned int mode, 360 phy_interface_t interface, 361 struct phy_device *phydev, int speed, 362 int duplex, bool tx_pause, bool rx_pause); 363 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 364 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 365 void (*get_wol)(struct ksz_device *dev, int port, 366 struct ethtool_wolinfo *wol); 367 int (*set_wol)(struct ksz_device *dev, int port, 368 struct ethtool_wolinfo *wol); 369 void (*wol_pre_shutdown)(struct ksz_device *dev, bool *wol_enabled); 370 void (*config_cpu_port)(struct dsa_switch *ds); 371 int (*enable_stp_addr)(struct ksz_device *dev); 372 int (*reset)(struct ksz_device *dev); 373 int (*init)(struct ksz_device *dev); 374 void (*exit)(struct ksz_device *dev); 375 }; 376 377 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 378 int ksz_switch_register(struct ksz_device *dev); 379 void ksz_switch_remove(struct ksz_device *dev); 380 381 void ksz_init_mib_timer(struct ksz_device *dev); 382 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port); 383 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 384 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 385 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 386 bool ksz_get_gbit(struct ksz_device *dev, int port); 387 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 388 extern const struct ksz_chip_data ksz_switch_chips[]; 389 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 390 struct netlink_ext_ack *extack); 391 void ksz_switch_macaddr_put(struct dsa_switch *ds); 392 void ksz_switch_shutdown(struct ksz_device *dev); 393 394 /* Common register access functions */ 395 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 396 { 397 return dev->regmap[KSZ_REGMAP_8]; 398 } 399 400 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 401 { 402 return dev->regmap[KSZ_REGMAP_16]; 403 } 404 405 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 406 { 407 return dev->regmap[KSZ_REGMAP_32]; 408 } 409 410 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 411 { 412 unsigned int value; 413 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 414 415 if (ret) 416 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 417 ERR_PTR(ret)); 418 419 *val = value; 420 return ret; 421 } 422 423 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 424 { 425 unsigned int value; 426 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 427 428 if (ret) 429 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 430 ERR_PTR(ret)); 431 432 *val = value; 433 return ret; 434 } 435 436 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 437 { 438 unsigned int value; 439 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 440 441 if (ret) 442 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 443 ERR_PTR(ret)); 444 445 *val = value; 446 return ret; 447 } 448 449 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 450 { 451 u32 value[2]; 452 int ret; 453 454 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 455 if (ret) 456 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 457 ERR_PTR(ret)); 458 else 459 *val = (u64)value[0] << 32 | value[1]; 460 461 return ret; 462 } 463 464 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 465 { 466 int ret; 467 468 ret = regmap_write(ksz_regmap_8(dev), reg, value); 469 if (ret) 470 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 471 ERR_PTR(ret)); 472 473 return ret; 474 } 475 476 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 477 { 478 int ret; 479 480 ret = regmap_write(ksz_regmap_16(dev), reg, value); 481 if (ret) 482 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 483 ERR_PTR(ret)); 484 485 return ret; 486 } 487 488 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 489 { 490 int ret; 491 492 ret = regmap_write(ksz_regmap_32(dev), reg, value); 493 if (ret) 494 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 495 ERR_PTR(ret)); 496 497 return ret; 498 } 499 500 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 501 u16 value) 502 { 503 int ret; 504 505 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 506 if (ret) 507 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 508 ERR_PTR(ret)); 509 510 return ret; 511 } 512 513 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 514 u32 value) 515 { 516 int ret; 517 518 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 519 if (ret) 520 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 521 ERR_PTR(ret)); 522 523 return ret; 524 } 525 526 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 527 { 528 u32 val[2]; 529 530 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 531 value = swab64(value); 532 val[0] = swab32(value & 0xffffffffULL); 533 val[1] = swab32(value >> 32ULL); 534 535 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 536 } 537 538 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 539 { 540 int ret; 541 542 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 543 if (ret) 544 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 545 ERR_PTR(ret)); 546 547 return ret; 548 } 549 550 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 551 u8 *data) 552 { 553 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 554 } 555 556 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 557 u16 *data) 558 { 559 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 560 } 561 562 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 563 u32 *data) 564 { 565 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 566 } 567 568 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 569 u8 data) 570 { 571 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 572 } 573 574 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 575 u16 data) 576 { 577 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 578 data); 579 } 580 581 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 582 u32 data) 583 { 584 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 585 data); 586 } 587 588 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 589 u8 mask, u8 val) 590 { 591 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 592 mask, val); 593 } 594 595 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 596 u32 mask, u32 val) 597 { 598 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 599 mask, val); 600 } 601 602 static inline void ksz_regmap_lock(void *__mtx) 603 { 604 struct mutex *mtx = __mtx; 605 mutex_lock(mtx); 606 } 607 608 static inline void ksz_regmap_unlock(void *__mtx) 609 { 610 struct mutex *mtx = __mtx; 611 mutex_unlock(mtx); 612 } 613 614 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 615 { 616 return dev->chip_id == KSZ8795_CHIP_ID || 617 dev->chip_id == KSZ8794_CHIP_ID || 618 dev->chip_id == KSZ8765_CHIP_ID; 619 } 620 621 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 622 { 623 return dev->chip_id == KSZ8830_CHIP_ID; 624 } 625 626 static inline bool is_ksz8(struct ksz_device *dev) 627 { 628 return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev); 629 } 630 631 static inline int is_lan937x(struct ksz_device *dev) 632 { 633 return dev->chip_id == LAN9370_CHIP_ID || 634 dev->chip_id == LAN9371_CHIP_ID || 635 dev->chip_id == LAN9372_CHIP_ID || 636 dev->chip_id == LAN9373_CHIP_ID || 637 dev->chip_id == LAN9374_CHIP_ID; 638 } 639 640 /* STP State Defines */ 641 #define PORT_TX_ENABLE BIT(2) 642 #define PORT_RX_ENABLE BIT(1) 643 #define PORT_LEARN_DISABLE BIT(0) 644 645 /* Switch ID Defines */ 646 #define REG_CHIP_ID0 0x00 647 648 #define SW_FAMILY_ID_M GENMASK(15, 8) 649 #define KSZ87_FAMILY_ID 0x87 650 #define KSZ88_FAMILY_ID 0x88 651 652 #define KSZ8_PORT_STATUS_0 0x08 653 #define KSZ8_PORT_FIBER_MODE BIT(7) 654 655 #define SW_CHIP_ID_M GENMASK(7, 4) 656 #define KSZ87_CHIP_ID_94 0x6 657 #define KSZ87_CHIP_ID_95 0x9 658 #define KSZ88_CHIP_ID_63 0x3 659 660 #define SW_REV_ID_M GENMASK(7, 4) 661 662 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 663 #define REG_CHIP_ID4 0x0f 664 #define SKU_ID_KSZ8563 0x3c 665 #define SKU_ID_KSZ9563 0x1c 666 667 /* Driver set switch broadcast storm protection at 10% rate. */ 668 #define BROADCAST_STORM_PROT_RATE 10 669 670 /* 148,800 frames * 67 ms / 100 */ 671 #define BROADCAST_STORM_VALUE 9969 672 673 #define BROADCAST_STORM_RATE_HI 0x07 674 #define BROADCAST_STORM_RATE_LO 0xFF 675 #define BROADCAST_STORM_RATE 0x07FF 676 677 #define MULTICAST_STORM_DISABLE BIT(6) 678 679 #define SW_START 0x01 680 681 /* xMII configuration */ 682 #define P_MII_DUPLEX_M BIT(6) 683 #define P_MII_100MBIT_M BIT(4) 684 685 #define P_GMII_1GBIT_M BIT(6) 686 #define P_RGMII_ID_IG_ENABLE BIT(4) 687 #define P_RGMII_ID_EG_ENABLE BIT(3) 688 #define P_MII_MAC_MODE BIT(2) 689 #define P_MII_SEL_M 0x3 690 691 /* Interrupt */ 692 #define REG_SW_PORT_INT_STATUS__1 0x001B 693 #define REG_SW_PORT_INT_MASK__1 0x001F 694 695 #define REG_PORT_INT_STATUS 0x001B 696 #define REG_PORT_INT_MASK 0x001F 697 698 #define PORT_SRC_PHY_INT 1 699 #define PORT_SRC_PTP_INT 2 700 701 #define KSZ8795_HUGE_PACKET_SIZE 2000 702 #define KSZ8863_HUGE_PACKET_SIZE 1916 703 #define KSZ8863_NORMAL_PACKET_SIZE 1536 704 #define KSZ8_LEGAL_PACKET_SIZE 1518 705 #define KSZ9477_MAX_FRAME_SIZE 9000 706 707 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 708 /* Drive Strength of I/O Pad 709 * 0: 8mA, 1: 16mA 710 */ 711 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 712 713 #define KSZ8795_REG_SW_CTRL_20 0xa3 714 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 715 #define SW_DRIVE_STRENGTH_M 0x7 716 #define SW_DRIVE_STRENGTH_2MA 0 717 #define SW_DRIVE_STRENGTH_4MA 1 718 #define SW_DRIVE_STRENGTH_8MA 2 719 #define SW_DRIVE_STRENGTH_12MA 3 720 #define SW_DRIVE_STRENGTH_16MA 4 721 #define SW_DRIVE_STRENGTH_20MA 5 722 #define SW_DRIVE_STRENGTH_24MA 6 723 #define SW_DRIVE_STRENGTH_28MA 7 724 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 725 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 726 727 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 728 #define KSZ9477_OUT_RATE_NO_LIMIT 0 729 730 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 731 732 #define KSZ9477_PORT_TC_MAP_S 4 733 734 /* CBS related registers */ 735 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 736 737 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 738 739 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 740 #define MTI_SCHEDULE_STRICT_PRIO 0 741 #define MTI_SCHEDULE_WRR 2 742 #define MTI_SHAPING_M GENMASK(5, 4) 743 #define MTI_SHAPING_OFF 0 744 #define MTI_SHAPING_SRP 1 745 #define MTI_SHAPING_TIME_AWARE 2 746 747 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 748 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 749 750 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 751 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 752 753 /* Regmap tables generation */ 754 #define KSZ_SPI_OP_RD 3 755 #define KSZ_SPI_OP_WR 2 756 757 #define swabnot_used(x) 0 758 759 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 760 swab##swp((opcode) << ((regbits) + (regpad))) 761 762 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 763 { \ 764 .name = #width, \ 765 .val_bits = (width), \ 766 .reg_stride = 1, \ 767 .reg_bits = (regbits) + (regalign), \ 768 .pad_bits = (regpad), \ 769 .max_register = BIT(regbits) - 1, \ 770 .cache_type = REGCACHE_NONE, \ 771 .read_flag_mask = \ 772 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 773 regbits, regpad), \ 774 .write_flag_mask = \ 775 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 776 regbits, regpad), \ 777 .lock = ksz_regmap_lock, \ 778 .unlock = ksz_regmap_unlock, \ 779 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 780 .val_format_endian = REGMAP_ENDIAN_BIG \ 781 } 782 783 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 784 static const struct regmap_config ksz##_regmap_config[] = { \ 785 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 786 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 787 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 788 } 789 790 #endif 791