1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 #include <linux/platform_data/microchip-ksz.h> 18 19 #include "ksz_ptp.h" 20 21 #define KSZ_MAX_NUM_PORTS 8 22 /* all KSZ switches count ports from 1 */ 23 #define KSZ_PORT_1 0 24 #define KSZ_PORT_2 1 25 #define KSZ_PORT_4 3 26 27 struct ksz_device; 28 struct ksz_port; 29 struct phylink_mac_ops; 30 31 enum ksz_regmap_width { 32 KSZ_REGMAP_8, 33 KSZ_REGMAP_16, 34 KSZ_REGMAP_32, 35 __KSZ_NUM_REGMAPS, 36 }; 37 38 struct vlan_table { 39 u32 table[3]; 40 }; 41 42 struct ksz_port_mib { 43 struct mutex cnt_mutex; /* structure access */ 44 u8 cnt_ptr; 45 u64 *counters; 46 struct rtnl_link_stats64 stats64; 47 struct ethtool_pause_stats pause_stats; 48 struct spinlock stats64_lock; 49 }; 50 51 struct ksz_mib_names { 52 int index; 53 char string[ETH_GSTRING_LEN]; 54 }; 55 56 struct ksz_chip_data { 57 u32 chip_id; 58 const char *dev_name; 59 int num_vlans; 60 int num_alus; 61 int num_statics; 62 int cpu_ports; 63 int port_cnt; 64 u8 port_nirqs; 65 u8 num_tx_queues; 66 u8 num_ipms; /* number of Internal Priority Maps */ 67 bool tc_cbs_supported; 68 const struct ksz_dev_ops *ops; 69 const struct phylink_mac_ops *phylink_mac_ops; 70 bool phy_errata_9477; 71 bool ksz87xx_eee_link_erratum; 72 const struct ksz_mib_names *mib_names; 73 int mib_cnt; 74 u8 reg_mib_cnt; 75 const u16 *regs; 76 const u32 *masks; 77 const u8 *shifts; 78 const u8 *xmii_ctrl0; 79 const u8 *xmii_ctrl1; 80 int stp_ctrl_reg; 81 int broadcast_ctrl_reg; 82 int multicast_ctrl_reg; 83 int start_ctrl_reg; 84 bool supports_mii[KSZ_MAX_NUM_PORTS]; 85 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 86 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 87 bool internal_phy[KSZ_MAX_NUM_PORTS]; 88 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 89 const struct regmap_access_table *wr_table; 90 const struct regmap_access_table *rd_table; 91 }; 92 93 struct ksz_irq { 94 u16 masked; 95 u16 reg_mask; 96 u16 reg_status; 97 struct irq_domain *domain; 98 int nirqs; 99 int irq_num; 100 char name[16]; 101 struct ksz_device *dev; 102 }; 103 104 struct ksz_ptp_irq { 105 struct ksz_port *port; 106 u16 ts_reg; 107 bool ts_en; 108 char name[16]; 109 int num; 110 }; 111 112 struct ksz_switch_macaddr { 113 unsigned char addr[ETH_ALEN]; 114 refcount_t refcount; 115 }; 116 117 struct ksz_port { 118 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 119 bool learning; 120 bool isolated; 121 int stp_state; 122 struct phy_device phydev; 123 124 u32 fiber:1; /* port is fiber */ 125 u32 force:1; 126 u32 read:1; /* read MIB counters in background */ 127 u32 freeze:1; /* MIB counter freeze is enabled */ 128 129 struct ksz_port_mib mib; 130 phy_interface_t interface; 131 u32 rgmii_tx_val; 132 u32 rgmii_rx_val; 133 struct ksz_device *ksz_dev; 134 void *acl_priv; 135 struct ksz_irq pirq; 136 u8 num; 137 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 138 struct hwtstamp_config tstamp_config; 139 bool hwts_tx_en; 140 bool hwts_rx_en; 141 struct ksz_irq ptpirq; 142 struct ksz_ptp_irq ptpmsg_irq[3]; 143 ktime_t tstamp_msg; 144 struct completion tstamp_msg_comp; 145 #endif 146 bool manual_flow; 147 }; 148 149 struct ksz_device { 150 struct dsa_switch *ds; 151 struct ksz_platform_data *pdata; 152 const struct ksz_chip_data *info; 153 154 struct mutex dev_mutex; /* device access */ 155 struct mutex regmap_mutex; /* regmap access */ 156 struct mutex alu_mutex; /* ALU access */ 157 struct mutex vlan_mutex; /* vlan access */ 158 const struct ksz_dev_ops *dev_ops; 159 160 struct device *dev; 161 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 162 163 void *priv; 164 int irq; 165 166 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 167 168 /* chip specific data */ 169 u32 chip_id; 170 u8 chip_rev; 171 int cpu_port; /* port connected to CPU */ 172 int phy_port_cnt; 173 phy_interface_t compat_interface; 174 bool synclko_125; 175 bool synclko_disable; 176 bool wakeup_source; 177 178 struct vlan_table *vlan_cache; 179 180 struct ksz_port *ports; 181 struct delayed_work mib_read; 182 unsigned long mib_read_interval; 183 u16 mirror_rx; 184 u16 mirror_tx; 185 u16 port_mask; 186 struct mutex lock_irq; /* IRQ Access */ 187 struct ksz_irq girq; 188 struct ksz_ptp_data ptp_data; 189 190 struct ksz_switch_macaddr *switch_macaddr; 191 struct net_device *hsr_dev; /* HSR */ 192 u8 hsr_ports; 193 }; 194 195 /* List of supported models */ 196 enum ksz_model { 197 KSZ8563, 198 KSZ8567, 199 KSZ8795, 200 KSZ8794, 201 KSZ8765, 202 KSZ8830, 203 KSZ9477, 204 KSZ9896, 205 KSZ9897, 206 KSZ9893, 207 KSZ9563, 208 KSZ9567, 209 LAN9370, 210 LAN9371, 211 LAN9372, 212 LAN9373, 213 LAN9374, 214 }; 215 216 enum ksz_regs { 217 REG_SW_MAC_ADDR, 218 REG_IND_CTRL_0, 219 REG_IND_DATA_8, 220 REG_IND_DATA_CHECK, 221 REG_IND_DATA_HI, 222 REG_IND_DATA_LO, 223 REG_IND_MIB_CHECK, 224 REG_IND_BYTE, 225 P_FORCE_CTRL, 226 P_LINK_STATUS, 227 P_LOCAL_CTRL, 228 P_NEG_RESTART_CTRL, 229 P_REMOTE_STATUS, 230 P_SPEED_STATUS, 231 S_TAIL_TAG_CTRL, 232 P_STP_CTRL, 233 S_START_CTRL, 234 S_BROADCAST_CTRL, 235 S_MULTICAST_CTRL, 236 P_XMII_CTRL_0, 237 P_XMII_CTRL_1, 238 }; 239 240 enum ksz_masks { 241 PORT_802_1P_REMAPPING, 242 SW_TAIL_TAG_ENABLE, 243 MIB_COUNTER_OVERFLOW, 244 MIB_COUNTER_VALID, 245 VLAN_TABLE_FID, 246 VLAN_TABLE_MEMBERSHIP, 247 VLAN_TABLE_VALID, 248 STATIC_MAC_TABLE_VALID, 249 STATIC_MAC_TABLE_USE_FID, 250 STATIC_MAC_TABLE_FID, 251 STATIC_MAC_TABLE_OVERRIDE, 252 STATIC_MAC_TABLE_FWD_PORTS, 253 DYNAMIC_MAC_TABLE_ENTRIES_H, 254 DYNAMIC_MAC_TABLE_MAC_EMPTY, 255 DYNAMIC_MAC_TABLE_NOT_READY, 256 DYNAMIC_MAC_TABLE_ENTRIES, 257 DYNAMIC_MAC_TABLE_FID, 258 DYNAMIC_MAC_TABLE_SRC_PORT, 259 DYNAMIC_MAC_TABLE_TIMESTAMP, 260 ALU_STAT_WRITE, 261 ALU_STAT_READ, 262 P_MII_TX_FLOW_CTRL, 263 P_MII_RX_FLOW_CTRL, 264 }; 265 266 enum ksz_shifts { 267 VLAN_TABLE_MEMBERSHIP_S, 268 VLAN_TABLE, 269 STATIC_MAC_FWD_PORTS, 270 STATIC_MAC_FID, 271 DYNAMIC_MAC_ENTRIES_H, 272 DYNAMIC_MAC_ENTRIES, 273 DYNAMIC_MAC_FID, 274 DYNAMIC_MAC_TIMESTAMP, 275 DYNAMIC_MAC_SRC_PORT, 276 ALU_STAT_INDEX, 277 }; 278 279 enum ksz_xmii_ctrl0 { 280 P_MII_100MBIT, 281 P_MII_10MBIT, 282 P_MII_FULL_DUPLEX, 283 P_MII_HALF_DUPLEX, 284 }; 285 286 enum ksz_xmii_ctrl1 { 287 P_RGMII_SEL, 288 P_RMII_SEL, 289 P_GMII_SEL, 290 P_MII_SEL, 291 P_GMII_1GBIT, 292 P_GMII_NOT_1GBIT, 293 }; 294 295 struct alu_struct { 296 /* entry 1 */ 297 u8 is_static:1; 298 u8 is_src_filter:1; 299 u8 is_dst_filter:1; 300 u8 prio_age:3; 301 u32 _reserv_0_1:23; 302 u8 mstp:3; 303 /* entry 2 */ 304 u8 is_override:1; 305 u8 is_use_fid:1; 306 u32 _reserv_1_1:23; 307 u8 port_forward:7; 308 /* entry 3 & 4*/ 309 u32 _reserv_2_1:9; 310 u8 fid:7; 311 u8 mac[ETH_ALEN]; 312 }; 313 314 struct ksz_dev_ops { 315 int (*setup)(struct dsa_switch *ds); 316 void (*teardown)(struct dsa_switch *ds); 317 u32 (*get_port_addr)(int port, int offset); 318 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 319 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 320 void (*port_cleanup)(struct ksz_device *dev, int port); 321 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 322 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 323 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 324 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 325 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 326 u64 *cnt); 327 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 328 u64 *dropped, u64 *cnt); 329 void (*r_mib_stat64)(struct ksz_device *dev, int port); 330 int (*vlan_filtering)(struct ksz_device *dev, int port, 331 bool flag, struct netlink_ext_ack *extack); 332 int (*vlan_add)(struct ksz_device *dev, int port, 333 const struct switchdev_obj_port_vlan *vlan, 334 struct netlink_ext_ack *extack); 335 int (*vlan_del)(struct ksz_device *dev, int port, 336 const struct switchdev_obj_port_vlan *vlan); 337 int (*mirror_add)(struct ksz_device *dev, int port, 338 struct dsa_mall_mirror_tc_entry *mirror, 339 bool ingress, struct netlink_ext_ack *extack); 340 void (*mirror_del)(struct ksz_device *dev, int port, 341 struct dsa_mall_mirror_tc_entry *mirror); 342 int (*fdb_add)(struct ksz_device *dev, int port, 343 const unsigned char *addr, u16 vid, struct dsa_db db); 344 int (*fdb_del)(struct ksz_device *dev, int port, 345 const unsigned char *addr, u16 vid, struct dsa_db db); 346 int (*fdb_dump)(struct ksz_device *dev, int port, 347 dsa_fdb_dump_cb_t *cb, void *data); 348 int (*mdb_add)(struct ksz_device *dev, int port, 349 const struct switchdev_obj_port_mdb *mdb, 350 struct dsa_db db); 351 int (*mdb_del)(struct ksz_device *dev, int port, 352 const struct switchdev_obj_port_mdb *mdb, 353 struct dsa_db db); 354 void (*get_caps)(struct ksz_device *dev, int port, 355 struct phylink_config *config); 356 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 357 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 358 void (*port_init_cnt)(struct ksz_device *dev, int port); 359 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 360 unsigned int mode, 361 phy_interface_t interface, 362 struct phy_device *phydev, int speed, 363 int duplex, bool tx_pause, bool rx_pause); 364 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 365 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 366 void (*get_wol)(struct ksz_device *dev, int port, 367 struct ethtool_wolinfo *wol); 368 int (*set_wol)(struct ksz_device *dev, int port, 369 struct ethtool_wolinfo *wol); 370 void (*wol_pre_shutdown)(struct ksz_device *dev, bool *wol_enabled); 371 void (*config_cpu_port)(struct dsa_switch *ds); 372 int (*enable_stp_addr)(struct ksz_device *dev); 373 int (*reset)(struct ksz_device *dev); 374 int (*init)(struct ksz_device *dev); 375 void (*exit)(struct ksz_device *dev); 376 }; 377 378 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 379 int ksz_switch_register(struct ksz_device *dev); 380 void ksz_switch_remove(struct ksz_device *dev); 381 382 void ksz_init_mib_timer(struct ksz_device *dev); 383 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port); 384 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 385 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 386 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 387 bool ksz_get_gbit(struct ksz_device *dev, int port); 388 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 389 extern const struct ksz_chip_data ksz_switch_chips[]; 390 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 391 struct netlink_ext_ack *extack); 392 void ksz_switch_macaddr_put(struct dsa_switch *ds); 393 void ksz_switch_shutdown(struct ksz_device *dev); 394 395 /* Common register access functions */ 396 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 397 { 398 return dev->regmap[KSZ_REGMAP_8]; 399 } 400 401 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 402 { 403 return dev->regmap[KSZ_REGMAP_16]; 404 } 405 406 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 407 { 408 return dev->regmap[KSZ_REGMAP_32]; 409 } 410 411 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 412 { 413 unsigned int value; 414 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 415 416 if (ret) 417 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 418 ERR_PTR(ret)); 419 420 *val = value; 421 return ret; 422 } 423 424 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 425 { 426 unsigned int value; 427 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 428 429 if (ret) 430 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 431 ERR_PTR(ret)); 432 433 *val = value; 434 return ret; 435 } 436 437 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 438 { 439 unsigned int value; 440 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 441 442 if (ret) 443 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 444 ERR_PTR(ret)); 445 446 *val = value; 447 return ret; 448 } 449 450 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 451 { 452 u32 value[2]; 453 int ret; 454 455 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 456 if (ret) 457 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 458 ERR_PTR(ret)); 459 else 460 *val = (u64)value[0] << 32 | value[1]; 461 462 return ret; 463 } 464 465 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 466 { 467 int ret; 468 469 ret = regmap_write(ksz_regmap_8(dev), reg, value); 470 if (ret) 471 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 472 ERR_PTR(ret)); 473 474 return ret; 475 } 476 477 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 478 { 479 int ret; 480 481 ret = regmap_write(ksz_regmap_16(dev), reg, value); 482 if (ret) 483 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 484 ERR_PTR(ret)); 485 486 return ret; 487 } 488 489 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 490 { 491 int ret; 492 493 ret = regmap_write(ksz_regmap_32(dev), reg, value); 494 if (ret) 495 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 496 ERR_PTR(ret)); 497 498 return ret; 499 } 500 501 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 502 u16 value) 503 { 504 int ret; 505 506 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 507 if (ret) 508 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 509 ERR_PTR(ret)); 510 511 return ret; 512 } 513 514 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 515 u32 value) 516 { 517 int ret; 518 519 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 520 if (ret) 521 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 522 ERR_PTR(ret)); 523 524 return ret; 525 } 526 527 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 528 { 529 u32 val[2]; 530 531 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 532 value = swab64(value); 533 val[0] = swab32(value & 0xffffffffULL); 534 val[1] = swab32(value >> 32ULL); 535 536 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 537 } 538 539 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 540 { 541 int ret; 542 543 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 544 if (ret) 545 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 546 ERR_PTR(ret)); 547 548 return ret; 549 } 550 551 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 552 u8 *data) 553 { 554 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 555 } 556 557 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 558 u16 *data) 559 { 560 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 561 } 562 563 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 564 u32 *data) 565 { 566 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 567 } 568 569 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 570 u8 data) 571 { 572 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 573 } 574 575 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 576 u16 data) 577 { 578 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 579 data); 580 } 581 582 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 583 u32 data) 584 { 585 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 586 data); 587 } 588 589 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 590 u8 mask, u8 val) 591 { 592 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 593 mask, val); 594 } 595 596 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 597 u32 mask, u32 val) 598 { 599 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 600 mask, val); 601 } 602 603 static inline void ksz_regmap_lock(void *__mtx) 604 { 605 struct mutex *mtx = __mtx; 606 mutex_lock(mtx); 607 } 608 609 static inline void ksz_regmap_unlock(void *__mtx) 610 { 611 struct mutex *mtx = __mtx; 612 mutex_unlock(mtx); 613 } 614 615 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 616 { 617 return dev->chip_id == KSZ8795_CHIP_ID || 618 dev->chip_id == KSZ8794_CHIP_ID || 619 dev->chip_id == KSZ8765_CHIP_ID; 620 } 621 622 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 623 { 624 return dev->chip_id == KSZ8830_CHIP_ID; 625 } 626 627 static inline bool is_ksz8(struct ksz_device *dev) 628 { 629 return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev); 630 } 631 632 static inline int is_lan937x(struct ksz_device *dev) 633 { 634 return dev->chip_id == LAN9370_CHIP_ID || 635 dev->chip_id == LAN9371_CHIP_ID || 636 dev->chip_id == LAN9372_CHIP_ID || 637 dev->chip_id == LAN9373_CHIP_ID || 638 dev->chip_id == LAN9374_CHIP_ID; 639 } 640 641 static inline bool is_lan937x_tx_phy(struct ksz_device *dev, int port) 642 { 643 return (dev->chip_id == LAN9371_CHIP_ID || 644 dev->chip_id == LAN9372_CHIP_ID) && port == KSZ_PORT_4; 645 } 646 647 /* STP State Defines */ 648 #define PORT_TX_ENABLE BIT(2) 649 #define PORT_RX_ENABLE BIT(1) 650 #define PORT_LEARN_DISABLE BIT(0) 651 652 /* Switch ID Defines */ 653 #define REG_CHIP_ID0 0x00 654 655 #define SW_FAMILY_ID_M GENMASK(15, 8) 656 #define KSZ87_FAMILY_ID 0x87 657 #define KSZ88_FAMILY_ID 0x88 658 659 #define KSZ8_PORT_STATUS_0 0x08 660 #define KSZ8_PORT_FIBER_MODE BIT(7) 661 662 #define SW_CHIP_ID_M GENMASK(7, 4) 663 #define KSZ87_CHIP_ID_94 0x6 664 #define KSZ87_CHIP_ID_95 0x9 665 #define KSZ88_CHIP_ID_63 0x3 666 667 #define SW_REV_ID_M GENMASK(7, 4) 668 669 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 670 #define REG_CHIP_ID4 0x0f 671 #define SKU_ID_KSZ8563 0x3c 672 #define SKU_ID_KSZ9563 0x1c 673 674 /* Driver set switch broadcast storm protection at 10% rate. */ 675 #define BROADCAST_STORM_PROT_RATE 10 676 677 /* 148,800 frames * 67 ms / 100 */ 678 #define BROADCAST_STORM_VALUE 9969 679 680 #define BROADCAST_STORM_RATE_HI 0x07 681 #define BROADCAST_STORM_RATE_LO 0xFF 682 #define BROADCAST_STORM_RATE 0x07FF 683 684 #define MULTICAST_STORM_DISABLE BIT(6) 685 686 #define SW_START 0x01 687 688 /* xMII configuration */ 689 #define P_MII_DUPLEX_M BIT(6) 690 #define P_MII_100MBIT_M BIT(4) 691 692 #define P_GMII_1GBIT_M BIT(6) 693 #define P_RGMII_ID_IG_ENABLE BIT(4) 694 #define P_RGMII_ID_EG_ENABLE BIT(3) 695 #define P_MII_MAC_MODE BIT(2) 696 #define P_MII_SEL_M 0x3 697 698 /* Interrupt */ 699 #define REG_SW_PORT_INT_STATUS__1 0x001B 700 #define REG_SW_PORT_INT_MASK__1 0x001F 701 702 #define REG_PORT_INT_STATUS 0x001B 703 #define REG_PORT_INT_MASK 0x001F 704 705 #define PORT_SRC_PHY_INT 1 706 #define PORT_SRC_PTP_INT 2 707 708 #define KSZ8795_HUGE_PACKET_SIZE 2000 709 #define KSZ8863_HUGE_PACKET_SIZE 1916 710 #define KSZ8863_NORMAL_PACKET_SIZE 1536 711 #define KSZ8_LEGAL_PACKET_SIZE 1518 712 #define KSZ9477_MAX_FRAME_SIZE 9000 713 714 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 715 /* Drive Strength of I/O Pad 716 * 0: 8mA, 1: 16mA 717 */ 718 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 719 720 #define KSZ8795_REG_SW_CTRL_20 0xa3 721 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 722 #define SW_DRIVE_STRENGTH_M 0x7 723 #define SW_DRIVE_STRENGTH_2MA 0 724 #define SW_DRIVE_STRENGTH_4MA 1 725 #define SW_DRIVE_STRENGTH_8MA 2 726 #define SW_DRIVE_STRENGTH_12MA 3 727 #define SW_DRIVE_STRENGTH_16MA 4 728 #define SW_DRIVE_STRENGTH_20MA 5 729 #define SW_DRIVE_STRENGTH_24MA 6 730 #define SW_DRIVE_STRENGTH_28MA 7 731 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 732 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 733 734 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 735 #define KSZ9477_OUT_RATE_NO_LIMIT 0 736 737 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 738 739 #define KSZ9477_PORT_TC_MAP_S 4 740 741 /* CBS related registers */ 742 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 743 744 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 745 746 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 747 #define MTI_SCHEDULE_STRICT_PRIO 0 748 #define MTI_SCHEDULE_WRR 2 749 #define MTI_SHAPING_M GENMASK(5, 4) 750 #define MTI_SHAPING_OFF 0 751 #define MTI_SHAPING_SRP 1 752 #define MTI_SHAPING_TIME_AWARE 2 753 754 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 755 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 756 757 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 758 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 759 760 /* Regmap tables generation */ 761 #define KSZ_SPI_OP_RD 3 762 #define KSZ_SPI_OP_WR 2 763 764 #define swabnot_used(x) 0 765 766 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 767 swab##swp((opcode) << ((regbits) + (regpad))) 768 769 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 770 { \ 771 .name = #width, \ 772 .val_bits = (width), \ 773 .reg_stride = 1, \ 774 .reg_bits = (regbits) + (regalign), \ 775 .pad_bits = (regpad), \ 776 .max_register = BIT(regbits) - 1, \ 777 .cache_type = REGCACHE_NONE, \ 778 .read_flag_mask = \ 779 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 780 regbits, regpad), \ 781 .write_flag_mask = \ 782 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 783 regbits, regpad), \ 784 .lock = ksz_regmap_lock, \ 785 .unlock = ksz_regmap_unlock, \ 786 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 787 .val_format_endian = REGMAP_ENDIAN_BIG \ 788 } 789 790 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 791 static const struct regmap_config ksz##_regmap_config[] = { \ 792 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 793 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 794 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 795 } 796 797 #endif 798