1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2024 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 #include <linux/platform_data/microchip-ksz.h> 18 19 #include "ksz_ptp.h" 20 21 #define KSZ_MAX_NUM_PORTS 8 22 /* all KSZ switches count ports from 1 */ 23 #define KSZ_PORT_1 0 24 #define KSZ_PORT_2 1 25 #define KSZ_PORT_4 3 26 27 struct ksz_device; 28 struct ksz_port; 29 struct phylink_mac_ops; 30 31 enum ksz_regmap_width { 32 KSZ_REGMAP_8, 33 KSZ_REGMAP_16, 34 KSZ_REGMAP_32, 35 __KSZ_NUM_REGMAPS, 36 }; 37 38 struct vlan_table { 39 u32 table[3]; 40 }; 41 42 struct ksz_port_mib { 43 struct mutex cnt_mutex; /* structure access */ 44 u8 cnt_ptr; 45 u64 *counters; 46 struct rtnl_link_stats64 stats64; 47 struct ethtool_pause_stats pause_stats; 48 struct spinlock stats64_lock; 49 }; 50 51 struct ksz_mib_names { 52 int index; 53 char string[ETH_GSTRING_LEN]; 54 }; 55 56 struct ksz_chip_data { 57 u32 chip_id; 58 const char *dev_name; 59 int num_vlans; 60 int num_alus; 61 int num_statics; 62 int cpu_ports; 63 int port_cnt; 64 u8 port_nirqs; 65 u8 num_tx_queues; 66 u8 num_ipms; /* number of Internal Priority Maps */ 67 bool tc_cbs_supported; 68 69 /** 70 * @phy_side_mdio_supported: Indicates if the chip supports an additional 71 * side MDIO channel for accessing integrated PHYs. 72 */ 73 bool phy_side_mdio_supported; 74 const struct ksz_dev_ops *ops; 75 const struct phylink_mac_ops *phylink_mac_ops; 76 bool phy_errata_9477; 77 bool ksz87xx_eee_link_erratum; 78 const struct ksz_mib_names *mib_names; 79 int mib_cnt; 80 u8 reg_mib_cnt; 81 const u16 *regs; 82 const u32 *masks; 83 const u8 *shifts; 84 const u8 *xmii_ctrl0; 85 const u8 *xmii_ctrl1; 86 int stp_ctrl_reg; 87 int broadcast_ctrl_reg; 88 int multicast_ctrl_reg; 89 int start_ctrl_reg; 90 bool supports_mii[KSZ_MAX_NUM_PORTS]; 91 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 92 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 93 bool internal_phy[KSZ_MAX_NUM_PORTS]; 94 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 95 bool ptp_capable; 96 const struct regmap_access_table *wr_table; 97 const struct regmap_access_table *rd_table; 98 }; 99 100 struct ksz_irq { 101 u16 masked; 102 u16 reg_mask; 103 u16 reg_status; 104 struct irq_domain *domain; 105 int nirqs; 106 int irq_num; 107 char name[16]; 108 struct ksz_device *dev; 109 }; 110 111 struct ksz_ptp_irq { 112 struct ksz_port *port; 113 u16 ts_reg; 114 bool ts_en; 115 char name[16]; 116 int num; 117 }; 118 119 struct ksz_switch_macaddr { 120 unsigned char addr[ETH_ALEN]; 121 refcount_t refcount; 122 }; 123 124 struct ksz_port { 125 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 126 bool learning; 127 bool isolated; 128 int stp_state; 129 struct phy_device phydev; 130 131 u32 fiber:1; /* port is fiber */ 132 u32 force:1; 133 u32 read:1; /* read MIB counters in background */ 134 u32 freeze:1; /* MIB counter freeze is enabled */ 135 136 struct ksz_port_mib mib; 137 phy_interface_t interface; 138 u32 rgmii_tx_val; 139 u32 rgmii_rx_val; 140 struct ksz_device *ksz_dev; 141 void *acl_priv; 142 struct ksz_irq pirq; 143 u8 num; 144 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 145 struct hwtstamp_config tstamp_config; 146 bool hwts_tx_en; 147 bool hwts_rx_en; 148 struct ksz_irq ptpirq; 149 struct ksz_ptp_irq ptpmsg_irq[3]; 150 ktime_t tstamp_msg; 151 struct completion tstamp_msg_comp; 152 #endif 153 bool manual_flow; 154 }; 155 156 struct ksz_device { 157 struct dsa_switch *ds; 158 struct ksz_platform_data *pdata; 159 const struct ksz_chip_data *info; 160 161 struct mutex dev_mutex; /* device access */ 162 struct mutex regmap_mutex; /* regmap access */ 163 struct mutex alu_mutex; /* ALU access */ 164 struct mutex vlan_mutex; /* vlan access */ 165 const struct ksz_dev_ops *dev_ops; 166 167 struct device *dev; 168 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 169 170 void *priv; 171 int irq; 172 173 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 174 175 /* chip specific data */ 176 u32 chip_id; 177 u8 chip_rev; 178 int cpu_port; /* port connected to CPU */ 179 int phy_port_cnt; 180 phy_interface_t compat_interface; 181 bool synclko_125; 182 bool synclko_disable; 183 bool wakeup_source; 184 bool pme_active_high; 185 186 struct vlan_table *vlan_cache; 187 188 struct ksz_port *ports; 189 struct delayed_work mib_read; 190 unsigned long mib_read_interval; 191 u16 mirror_rx; 192 u16 mirror_tx; 193 u16 port_mask; 194 struct mutex lock_irq; /* IRQ Access */ 195 struct ksz_irq girq; 196 struct ksz_ptp_data ptp_data; 197 198 struct ksz_switch_macaddr *switch_macaddr; 199 struct net_device *hsr_dev; /* HSR */ 200 u8 hsr_ports; 201 202 /** 203 * @phy_addr_map: Array mapping switch ports to their corresponding PHY 204 * addresses. 205 */ 206 u8 phy_addr_map[KSZ_MAX_NUM_PORTS]; 207 208 /** 209 * @parent_mdio_bus: Pointer to the external MDIO bus controller. 210 * 211 * This points to an external MDIO bus controller that is used to access 212 * the PHYs integrated within the switch. Unlike an integrated MDIO 213 * bus, this external controller provides a direct path for managing 214 * the switch’s internal PHYs, bypassing the main SPI interface. 215 */ 216 struct mii_bus *parent_mdio_bus; 217 }; 218 219 /* List of supported models */ 220 enum ksz_model { 221 KSZ8563, 222 KSZ8567, 223 KSZ8795, 224 KSZ8794, 225 KSZ8765, 226 KSZ88X3, 227 KSZ8864, 228 KSZ8895, 229 KSZ9477, 230 KSZ9896, 231 KSZ9897, 232 KSZ9893, 233 KSZ9563, 234 KSZ9567, 235 LAN9370, 236 LAN9371, 237 LAN9372, 238 LAN9373, 239 LAN9374, 240 LAN9646, 241 }; 242 243 enum ksz_regs { 244 REG_SW_MAC_ADDR, 245 REG_IND_CTRL_0, 246 REG_IND_DATA_8, 247 REG_IND_DATA_CHECK, 248 REG_IND_DATA_HI, 249 REG_IND_DATA_LO, 250 REG_IND_MIB_CHECK, 251 REG_IND_BYTE, 252 P_FORCE_CTRL, 253 P_LINK_STATUS, 254 P_LOCAL_CTRL, 255 P_NEG_RESTART_CTRL, 256 P_REMOTE_STATUS, 257 P_SPEED_STATUS, 258 S_TAIL_TAG_CTRL, 259 P_STP_CTRL, 260 S_START_CTRL, 261 S_BROADCAST_CTRL, 262 S_MULTICAST_CTRL, 263 P_XMII_CTRL_0, 264 P_XMII_CTRL_1, 265 REG_SW_PME_CTRL, 266 REG_PORT_PME_STATUS, 267 REG_PORT_PME_CTRL, 268 }; 269 270 enum ksz_masks { 271 PORT_802_1P_REMAPPING, 272 SW_TAIL_TAG_ENABLE, 273 MIB_COUNTER_OVERFLOW, 274 MIB_COUNTER_VALID, 275 VLAN_TABLE_FID, 276 VLAN_TABLE_MEMBERSHIP, 277 VLAN_TABLE_VALID, 278 STATIC_MAC_TABLE_VALID, 279 STATIC_MAC_TABLE_USE_FID, 280 STATIC_MAC_TABLE_FID, 281 STATIC_MAC_TABLE_OVERRIDE, 282 STATIC_MAC_TABLE_FWD_PORTS, 283 DYNAMIC_MAC_TABLE_ENTRIES_H, 284 DYNAMIC_MAC_TABLE_MAC_EMPTY, 285 DYNAMIC_MAC_TABLE_NOT_READY, 286 DYNAMIC_MAC_TABLE_ENTRIES, 287 DYNAMIC_MAC_TABLE_FID, 288 DYNAMIC_MAC_TABLE_SRC_PORT, 289 DYNAMIC_MAC_TABLE_TIMESTAMP, 290 ALU_STAT_WRITE, 291 ALU_STAT_READ, 292 P_MII_TX_FLOW_CTRL, 293 P_MII_RX_FLOW_CTRL, 294 }; 295 296 enum ksz_shifts { 297 VLAN_TABLE_MEMBERSHIP_S, 298 VLAN_TABLE, 299 STATIC_MAC_FWD_PORTS, 300 STATIC_MAC_FID, 301 DYNAMIC_MAC_ENTRIES_H, 302 DYNAMIC_MAC_ENTRIES, 303 DYNAMIC_MAC_FID, 304 DYNAMIC_MAC_TIMESTAMP, 305 DYNAMIC_MAC_SRC_PORT, 306 ALU_STAT_INDEX, 307 }; 308 309 enum ksz_xmii_ctrl0 { 310 P_MII_100MBIT, 311 P_MII_10MBIT, 312 P_MII_FULL_DUPLEX, 313 P_MII_HALF_DUPLEX, 314 }; 315 316 enum ksz_xmii_ctrl1 { 317 P_RGMII_SEL, 318 P_RMII_SEL, 319 P_GMII_SEL, 320 P_MII_SEL, 321 P_GMII_1GBIT, 322 P_GMII_NOT_1GBIT, 323 }; 324 325 struct alu_struct { 326 /* entry 1 */ 327 u8 is_static:1; 328 u8 is_src_filter:1; 329 u8 is_dst_filter:1; 330 u8 prio_age:3; 331 u32 _reserv_0_1:23; 332 u8 mstp:3; 333 /* entry 2 */ 334 u8 is_override:1; 335 u8 is_use_fid:1; 336 u32 _reserv_1_1:23; 337 u8 port_forward:7; 338 /* entry 3 & 4*/ 339 u32 _reserv_2_1:9; 340 u8 fid:7; 341 u8 mac[ETH_ALEN]; 342 }; 343 344 struct ksz_dev_ops { 345 int (*setup)(struct dsa_switch *ds); 346 void (*teardown)(struct dsa_switch *ds); 347 u32 (*get_port_addr)(int port, int offset); 348 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 349 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 350 void (*port_cleanup)(struct ksz_device *dev, int port); 351 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 352 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 353 354 /** 355 * @mdio_bus_preinit: Function pointer to pre-initialize the MDIO bus 356 * for accessing PHYs. 357 * @dev: Pointer to device structure. 358 * @side_mdio: Boolean indicating if the PHYs are accessed over a side 359 * MDIO bus. 360 * 361 * This function pointer is used to configure the MDIO bus for PHY 362 * access before initiating regular PHY operations. It enables either 363 * SPI/I2C or side MDIO access modes by unlocking necessary registers 364 * and setting up access permissions for the selected mode. 365 * 366 * Return: 367 * - 0 on success. 368 * - Negative error code on failure. 369 */ 370 int (*mdio_bus_preinit)(struct ksz_device *dev, bool side_mdio); 371 372 /** 373 * @create_phy_addr_map: Function pointer to create a port-to-PHY 374 * address map. 375 * @dev: Pointer to device structure. 376 * @side_mdio: Boolean indicating if the PHYs are accessed over a side 377 * MDIO bus. 378 * 379 * This function pointer is responsible for mapping switch ports to PHY 380 * addresses according to the configured access mode (SPI or side MDIO) 381 * and the device’s strap configuration. The mapping setup may vary 382 * depending on the chip variant and configuration. Ensures the correct 383 * address mapping for PHY communication. 384 * 385 * Return: 386 * - 0 on success. 387 * - Negative error code on failure (e.g., invalid configuration). 388 */ 389 int (*create_phy_addr_map)(struct ksz_device *dev, bool side_mdio); 390 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 391 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 392 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 393 u64 *cnt); 394 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 395 u64 *dropped, u64 *cnt); 396 void (*r_mib_stat64)(struct ksz_device *dev, int port); 397 int (*vlan_filtering)(struct ksz_device *dev, int port, 398 bool flag, struct netlink_ext_ack *extack); 399 int (*vlan_add)(struct ksz_device *dev, int port, 400 const struct switchdev_obj_port_vlan *vlan, 401 struct netlink_ext_ack *extack); 402 int (*vlan_del)(struct ksz_device *dev, int port, 403 const struct switchdev_obj_port_vlan *vlan); 404 int (*mirror_add)(struct ksz_device *dev, int port, 405 struct dsa_mall_mirror_tc_entry *mirror, 406 bool ingress, struct netlink_ext_ack *extack); 407 void (*mirror_del)(struct ksz_device *dev, int port, 408 struct dsa_mall_mirror_tc_entry *mirror); 409 int (*fdb_add)(struct ksz_device *dev, int port, 410 const unsigned char *addr, u16 vid, struct dsa_db db); 411 int (*fdb_del)(struct ksz_device *dev, int port, 412 const unsigned char *addr, u16 vid, struct dsa_db db); 413 int (*fdb_dump)(struct ksz_device *dev, int port, 414 dsa_fdb_dump_cb_t *cb, void *data); 415 int (*mdb_add)(struct ksz_device *dev, int port, 416 const struct switchdev_obj_port_mdb *mdb, 417 struct dsa_db db); 418 int (*mdb_del)(struct ksz_device *dev, int port, 419 const struct switchdev_obj_port_mdb *mdb, 420 struct dsa_db db); 421 void (*get_caps)(struct ksz_device *dev, int port, 422 struct phylink_config *config); 423 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 424 int (*pme_write8)(struct ksz_device *dev, u32 reg, u8 value); 425 int (*pme_pread8)(struct ksz_device *dev, int port, int offset, 426 u8 *data); 427 int (*pme_pwrite8)(struct ksz_device *dev, int port, int offset, 428 u8 data); 429 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 430 void (*port_init_cnt)(struct ksz_device *dev, int port); 431 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 432 unsigned int mode, 433 phy_interface_t interface, 434 struct phy_device *phydev, int speed, 435 int duplex, bool tx_pause, bool rx_pause); 436 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 437 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 438 void (*config_cpu_port)(struct dsa_switch *ds); 439 int (*enable_stp_addr)(struct ksz_device *dev); 440 int (*reset)(struct ksz_device *dev); 441 int (*init)(struct ksz_device *dev); 442 void (*exit)(struct ksz_device *dev); 443 }; 444 445 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 446 int ksz_switch_register(struct ksz_device *dev); 447 void ksz_switch_remove(struct ksz_device *dev); 448 int ksz_switch_suspend(struct device *dev); 449 int ksz_switch_resume(struct device *dev); 450 451 void ksz_init_mib_timer(struct ksz_device *dev); 452 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port); 453 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 454 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 455 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 456 bool ksz_get_gbit(struct ksz_device *dev, int port); 457 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 458 extern const struct ksz_chip_data ksz_switch_chips[]; 459 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 460 struct netlink_ext_ack *extack); 461 void ksz_switch_macaddr_put(struct dsa_switch *ds); 462 void ksz_switch_shutdown(struct ksz_device *dev); 463 int ksz_handle_wake_reason(struct ksz_device *dev, int port); 464 465 /* Common register access functions */ 466 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 467 { 468 return dev->regmap[KSZ_REGMAP_8]; 469 } 470 471 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 472 { 473 return dev->regmap[KSZ_REGMAP_16]; 474 } 475 476 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 477 { 478 return dev->regmap[KSZ_REGMAP_32]; 479 } 480 481 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 482 { 483 unsigned int value; 484 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 485 486 if (ret) 487 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 488 ERR_PTR(ret)); 489 490 *val = value; 491 return ret; 492 } 493 494 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 495 { 496 unsigned int value; 497 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 498 499 if (ret) 500 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 501 ERR_PTR(ret)); 502 503 *val = value; 504 return ret; 505 } 506 507 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 508 { 509 unsigned int value; 510 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 511 512 if (ret) 513 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 514 ERR_PTR(ret)); 515 516 *val = value; 517 return ret; 518 } 519 520 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 521 { 522 u32 value[2]; 523 int ret; 524 525 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 526 if (ret) 527 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 528 ERR_PTR(ret)); 529 else 530 *val = (u64)value[0] << 32 | value[1]; 531 532 return ret; 533 } 534 535 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 536 { 537 int ret; 538 539 ret = regmap_write(ksz_regmap_8(dev), reg, value); 540 if (ret) 541 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 542 ERR_PTR(ret)); 543 544 return ret; 545 } 546 547 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 548 { 549 int ret; 550 551 ret = regmap_write(ksz_regmap_16(dev), reg, value); 552 if (ret) 553 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 554 ERR_PTR(ret)); 555 556 return ret; 557 } 558 559 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 560 { 561 int ret; 562 563 ret = regmap_write(ksz_regmap_32(dev), reg, value); 564 if (ret) 565 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 566 ERR_PTR(ret)); 567 568 return ret; 569 } 570 571 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 572 u16 value) 573 { 574 int ret; 575 576 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 577 if (ret) 578 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 579 ERR_PTR(ret)); 580 581 return ret; 582 } 583 584 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 585 u32 value) 586 { 587 int ret; 588 589 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 590 if (ret) 591 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 592 ERR_PTR(ret)); 593 594 return ret; 595 } 596 597 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 598 { 599 u32 val[2]; 600 601 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 602 value = swab64(value); 603 val[0] = swab32(value & 0xffffffffULL); 604 val[1] = swab32(value >> 32ULL); 605 606 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 607 } 608 609 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 610 { 611 int ret; 612 613 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 614 if (ret) 615 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 616 ERR_PTR(ret)); 617 618 return ret; 619 } 620 621 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 622 u8 *data) 623 { 624 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 625 } 626 627 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 628 u16 *data) 629 { 630 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 631 } 632 633 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 634 u32 *data) 635 { 636 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 637 } 638 639 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 640 u8 data) 641 { 642 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 643 } 644 645 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 646 u16 data) 647 { 648 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 649 data); 650 } 651 652 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 653 u32 data) 654 { 655 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 656 data); 657 } 658 659 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 660 u8 mask, u8 val) 661 { 662 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 663 mask, val); 664 } 665 666 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 667 u32 mask, u32 val) 668 { 669 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 670 mask, val); 671 } 672 673 static inline void ksz_regmap_lock(void *__mtx) 674 { 675 struct mutex *mtx = __mtx; 676 mutex_lock(mtx); 677 } 678 679 static inline void ksz_regmap_unlock(void *__mtx) 680 { 681 struct mutex *mtx = __mtx; 682 mutex_unlock(mtx); 683 } 684 685 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 686 { 687 return dev->chip_id == KSZ8795_CHIP_ID || 688 dev->chip_id == KSZ8794_CHIP_ID || 689 dev->chip_id == KSZ8765_CHIP_ID; 690 } 691 692 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 693 { 694 return dev->chip_id == KSZ88X3_CHIP_ID; 695 } 696 697 static inline bool ksz_is_8895_family(struct ksz_device *dev) 698 { 699 return dev->chip_id == KSZ8895_CHIP_ID || 700 dev->chip_id == KSZ8864_CHIP_ID; 701 } 702 703 static inline bool is_ksz8(struct ksz_device *dev) 704 { 705 return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev) || 706 ksz_is_8895_family(dev); 707 } 708 709 static inline bool is_ksz88xx(struct ksz_device *dev) 710 { 711 return ksz_is_ksz88x3(dev) || ksz_is_8895_family(dev); 712 } 713 714 static inline bool is_ksz9477(struct ksz_device *dev) 715 { 716 return dev->chip_id == KSZ9477_CHIP_ID; 717 } 718 719 static inline int is_lan937x(struct ksz_device *dev) 720 { 721 return dev->chip_id == LAN9370_CHIP_ID || 722 dev->chip_id == LAN9371_CHIP_ID || 723 dev->chip_id == LAN9372_CHIP_ID || 724 dev->chip_id == LAN9373_CHIP_ID || 725 dev->chip_id == LAN9374_CHIP_ID; 726 } 727 728 static inline bool is_lan937x_tx_phy(struct ksz_device *dev, int port) 729 { 730 return (dev->chip_id == LAN9371_CHIP_ID || 731 dev->chip_id == LAN9372_CHIP_ID) && port == KSZ_PORT_4; 732 } 733 734 /* STP State Defines */ 735 #define PORT_TX_ENABLE BIT(2) 736 #define PORT_RX_ENABLE BIT(1) 737 #define PORT_LEARN_DISABLE BIT(0) 738 739 /* Switch ID Defines */ 740 #define REG_CHIP_ID0 0x00 741 742 #define SW_FAMILY_ID_M GENMASK(15, 8) 743 #define KSZ87_FAMILY_ID 0x87 744 #define KSZ88_FAMILY_ID 0x88 745 #define KSZ8895_FAMILY_ID 0x95 746 747 #define KSZ8_PORT_STATUS_0 0x08 748 #define KSZ8_PORT_FIBER_MODE BIT(7) 749 750 #define SW_CHIP_ID_M GENMASK(7, 4) 751 #define KSZ87_CHIP_ID_94 0x6 752 #define KSZ87_CHIP_ID_95 0x9 753 #define KSZ88_CHIP_ID_63 0x3 754 #define KSZ8895_CHIP_ID_95 0x4 755 #define KSZ8895_CHIP_ID_95R 0x6 756 757 /* KSZ8895 specific register */ 758 #define REG_KSZ8864_CHIP_ID 0xFE 759 #define SW_KSZ8864 BIT(7) 760 761 #define SW_REV_ID_M GENMASK(7, 4) 762 763 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 764 #define REG_CHIP_ID4 0x0f 765 #define SKU_ID_KSZ8563 0x3c 766 #define SKU_ID_KSZ9563 0x1c 767 768 /* Driver set switch broadcast storm protection at 10% rate. */ 769 #define BROADCAST_STORM_PROT_RATE 10 770 771 /* 148,800 frames * 67 ms / 100 */ 772 #define BROADCAST_STORM_VALUE 9969 773 774 #define BROADCAST_STORM_RATE_HI 0x07 775 #define BROADCAST_STORM_RATE_LO 0xFF 776 #define BROADCAST_STORM_RATE 0x07FF 777 778 #define MULTICAST_STORM_DISABLE BIT(6) 779 780 #define SW_START 0x01 781 782 /* xMII configuration */ 783 #define P_MII_DUPLEX_M BIT(6) 784 #define P_MII_100MBIT_M BIT(4) 785 786 #define P_GMII_1GBIT_M BIT(6) 787 #define P_RGMII_ID_IG_ENABLE BIT(4) 788 #define P_RGMII_ID_EG_ENABLE BIT(3) 789 #define P_MII_MAC_MODE BIT(2) 790 #define P_MII_SEL_M 0x3 791 792 /* KSZ9477, KSZ87xx Wake-on-LAN (WoL) masks */ 793 #define PME_WOL_MAGICPKT BIT(2) 794 #define PME_WOL_LINKUP BIT(1) 795 #define PME_WOL_ENERGY BIT(0) 796 797 #define PME_ENABLE BIT(1) 798 #define PME_POLARITY BIT(0) 799 800 #define KSZ87XX_REG_INT_EN 0x7D 801 #define KSZ87XX_INT_PME_MASK BIT(4) 802 803 /* Interrupt */ 804 #define REG_SW_PORT_INT_STATUS__1 0x001B 805 #define REG_SW_PORT_INT_MASK__1 0x001F 806 807 #define REG_PORT_INT_STATUS 0x001B 808 #define REG_PORT_INT_MASK 0x001F 809 810 #define PORT_SRC_PHY_INT 1 811 #define PORT_SRC_PTP_INT 2 812 813 #define KSZ8795_HUGE_PACKET_SIZE 2000 814 #define KSZ8863_HUGE_PACKET_SIZE 1916 815 #define KSZ8863_NORMAL_PACKET_SIZE 1536 816 #define KSZ8_LEGAL_PACKET_SIZE 1518 817 #define KSZ9477_MAX_FRAME_SIZE 9000 818 819 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 820 /* Drive Strength of I/O Pad 821 * 0: 8mA, 1: 16mA 822 */ 823 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 824 825 #define KSZ8795_REG_SW_CTRL_20 0xa3 826 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 827 #define SW_DRIVE_STRENGTH_M 0x7 828 #define SW_DRIVE_STRENGTH_2MA 0 829 #define SW_DRIVE_STRENGTH_4MA 1 830 #define SW_DRIVE_STRENGTH_8MA 2 831 #define SW_DRIVE_STRENGTH_12MA 3 832 #define SW_DRIVE_STRENGTH_16MA 4 833 #define SW_DRIVE_STRENGTH_20MA 5 834 #define SW_DRIVE_STRENGTH_24MA 6 835 #define SW_DRIVE_STRENGTH_28MA 7 836 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 837 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 838 839 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 840 #define KSZ9477_OUT_RATE_NO_LIMIT 0 841 842 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 843 844 #define KSZ9477_PORT_TC_MAP_S 4 845 846 /* CBS related registers */ 847 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 848 849 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 850 851 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 852 #define MTI_SCHEDULE_STRICT_PRIO 0 853 #define MTI_SCHEDULE_WRR 2 854 #define MTI_SHAPING_M GENMASK(5, 4) 855 #define MTI_SHAPING_OFF 0 856 #define MTI_SHAPING_SRP 1 857 #define MTI_SHAPING_TIME_AWARE 2 858 859 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 860 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 861 862 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 863 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 864 865 /* Regmap tables generation */ 866 #define KSZ_SPI_OP_RD 3 867 #define KSZ_SPI_OP_WR 2 868 869 #define swabnot_used(x) 0 870 871 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 872 swab##swp((opcode) << ((regbits) + (regpad))) 873 874 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 875 { \ 876 .name = #width, \ 877 .val_bits = (width), \ 878 .reg_stride = 1, \ 879 .reg_bits = (regbits) + (regalign), \ 880 .pad_bits = (regpad), \ 881 .max_register = BIT(regbits) - 1, \ 882 .cache_type = REGCACHE_NONE, \ 883 .read_flag_mask = \ 884 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 885 regbits, regpad), \ 886 .write_flag_mask = \ 887 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 888 regbits, regpad), \ 889 .lock = ksz_regmap_lock, \ 890 .unlock = ksz_regmap_unlock, \ 891 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 892 .val_format_endian = REGMAP_ENDIAN_BIG \ 893 } 894 895 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 896 static const struct regmap_config ksz##_regmap_config[] = { \ 897 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 898 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 899 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 900 } 901 902 #endif 903