1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 #include <linux/platform_data/microchip-ksz.h> 18 19 #include "ksz_ptp.h" 20 21 #define KSZ_MAX_NUM_PORTS 8 22 23 struct ksz_device; 24 struct ksz_port; 25 26 enum ksz_regmap_width { 27 KSZ_REGMAP_8, 28 KSZ_REGMAP_16, 29 KSZ_REGMAP_32, 30 __KSZ_NUM_REGMAPS, 31 }; 32 33 struct vlan_table { 34 u32 table[3]; 35 }; 36 37 struct ksz_port_mib { 38 struct mutex cnt_mutex; /* structure access */ 39 u8 cnt_ptr; 40 u64 *counters; 41 struct rtnl_link_stats64 stats64; 42 struct ethtool_pause_stats pause_stats; 43 struct spinlock stats64_lock; 44 }; 45 46 struct ksz_mib_names { 47 int index; 48 char string[ETH_GSTRING_LEN]; 49 }; 50 51 struct ksz_chip_data { 52 u32 chip_id; 53 const char *dev_name; 54 int num_vlans; 55 int num_alus; 56 int num_statics; 57 int cpu_ports; 58 int port_cnt; 59 u8 port_nirqs; 60 u8 num_tx_queues; 61 bool tc_cbs_supported; 62 bool tc_ets_supported; 63 const struct ksz_dev_ops *ops; 64 bool ksz87xx_eee_link_erratum; 65 const struct ksz_mib_names *mib_names; 66 int mib_cnt; 67 u8 reg_mib_cnt; 68 const u16 *regs; 69 const u32 *masks; 70 const u8 *shifts; 71 const u8 *xmii_ctrl0; 72 const u8 *xmii_ctrl1; 73 int stp_ctrl_reg; 74 int broadcast_ctrl_reg; 75 int multicast_ctrl_reg; 76 int start_ctrl_reg; 77 bool supports_mii[KSZ_MAX_NUM_PORTS]; 78 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 79 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 80 bool internal_phy[KSZ_MAX_NUM_PORTS]; 81 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 82 const struct regmap_access_table *wr_table; 83 const struct regmap_access_table *rd_table; 84 }; 85 86 struct ksz_irq { 87 u16 masked; 88 u16 reg_mask; 89 u16 reg_status; 90 struct irq_domain *domain; 91 int nirqs; 92 int irq_num; 93 char name[16]; 94 struct ksz_device *dev; 95 }; 96 97 struct ksz_ptp_irq { 98 struct ksz_port *port; 99 u16 ts_reg; 100 bool ts_en; 101 char name[16]; 102 int num; 103 }; 104 105 struct ksz_switch_macaddr { 106 unsigned char addr[ETH_ALEN]; 107 refcount_t refcount; 108 }; 109 110 struct ksz_port { 111 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 112 bool learning; 113 int stp_state; 114 struct phy_device phydev; 115 116 u32 fiber:1; /* port is fiber */ 117 u32 force:1; 118 u32 read:1; /* read MIB counters in background */ 119 u32 freeze:1; /* MIB counter freeze is enabled */ 120 121 struct ksz_port_mib mib; 122 phy_interface_t interface; 123 u32 rgmii_tx_val; 124 u32 rgmii_rx_val; 125 struct ksz_device *ksz_dev; 126 void *acl_priv; 127 struct ksz_irq pirq; 128 u8 num; 129 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 130 struct hwtstamp_config tstamp_config; 131 bool hwts_tx_en; 132 bool hwts_rx_en; 133 struct ksz_irq ptpirq; 134 struct ksz_ptp_irq ptpmsg_irq[3]; 135 ktime_t tstamp_msg; 136 struct completion tstamp_msg_comp; 137 #endif 138 bool manual_flow; 139 }; 140 141 struct ksz_device { 142 struct dsa_switch *ds; 143 struct ksz_platform_data *pdata; 144 const struct ksz_chip_data *info; 145 146 struct mutex dev_mutex; /* device access */ 147 struct mutex regmap_mutex; /* regmap access */ 148 struct mutex alu_mutex; /* ALU access */ 149 struct mutex vlan_mutex; /* vlan access */ 150 const struct ksz_dev_ops *dev_ops; 151 152 struct device *dev; 153 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 154 155 void *priv; 156 int irq; 157 158 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 159 160 /* chip specific data */ 161 u32 chip_id; 162 u8 chip_rev; 163 int cpu_port; /* port connected to CPU */ 164 int phy_port_cnt; 165 phy_interface_t compat_interface; 166 bool synclko_125; 167 bool synclko_disable; 168 bool wakeup_source; 169 170 struct vlan_table *vlan_cache; 171 172 struct ksz_port *ports; 173 struct delayed_work mib_read; 174 unsigned long mib_read_interval; 175 u16 mirror_rx; 176 u16 mirror_tx; 177 u16 port_mask; 178 struct mutex lock_irq; /* IRQ Access */ 179 struct ksz_irq girq; 180 struct ksz_ptp_data ptp_data; 181 182 struct ksz_switch_macaddr *switch_macaddr; 183 struct net_device *hsr_dev; /* HSR */ 184 u8 hsr_ports; 185 }; 186 187 /* List of supported models */ 188 enum ksz_model { 189 KSZ8563, 190 KSZ8567, 191 KSZ8795, 192 KSZ8794, 193 KSZ8765, 194 KSZ8830, 195 KSZ9477, 196 KSZ9896, 197 KSZ9897, 198 KSZ9893, 199 KSZ9563, 200 KSZ9567, 201 LAN9370, 202 LAN9371, 203 LAN9372, 204 LAN9373, 205 LAN9374, 206 }; 207 208 enum ksz_regs { 209 REG_SW_MAC_ADDR, 210 REG_IND_CTRL_0, 211 REG_IND_DATA_8, 212 REG_IND_DATA_CHECK, 213 REG_IND_DATA_HI, 214 REG_IND_DATA_LO, 215 REG_IND_MIB_CHECK, 216 REG_IND_BYTE, 217 P_FORCE_CTRL, 218 P_LINK_STATUS, 219 P_LOCAL_CTRL, 220 P_NEG_RESTART_CTRL, 221 P_REMOTE_STATUS, 222 P_SPEED_STATUS, 223 S_TAIL_TAG_CTRL, 224 P_STP_CTRL, 225 S_START_CTRL, 226 S_BROADCAST_CTRL, 227 S_MULTICAST_CTRL, 228 P_XMII_CTRL_0, 229 P_XMII_CTRL_1, 230 }; 231 232 enum ksz_masks { 233 PORT_802_1P_REMAPPING, 234 SW_TAIL_TAG_ENABLE, 235 MIB_COUNTER_OVERFLOW, 236 MIB_COUNTER_VALID, 237 VLAN_TABLE_FID, 238 VLAN_TABLE_MEMBERSHIP, 239 VLAN_TABLE_VALID, 240 STATIC_MAC_TABLE_VALID, 241 STATIC_MAC_TABLE_USE_FID, 242 STATIC_MAC_TABLE_FID, 243 STATIC_MAC_TABLE_OVERRIDE, 244 STATIC_MAC_TABLE_FWD_PORTS, 245 DYNAMIC_MAC_TABLE_ENTRIES_H, 246 DYNAMIC_MAC_TABLE_MAC_EMPTY, 247 DYNAMIC_MAC_TABLE_NOT_READY, 248 DYNAMIC_MAC_TABLE_ENTRIES, 249 DYNAMIC_MAC_TABLE_FID, 250 DYNAMIC_MAC_TABLE_SRC_PORT, 251 DYNAMIC_MAC_TABLE_TIMESTAMP, 252 ALU_STAT_WRITE, 253 ALU_STAT_READ, 254 P_MII_TX_FLOW_CTRL, 255 P_MII_RX_FLOW_CTRL, 256 }; 257 258 enum ksz_shifts { 259 VLAN_TABLE_MEMBERSHIP_S, 260 VLAN_TABLE, 261 STATIC_MAC_FWD_PORTS, 262 STATIC_MAC_FID, 263 DYNAMIC_MAC_ENTRIES_H, 264 DYNAMIC_MAC_ENTRIES, 265 DYNAMIC_MAC_FID, 266 DYNAMIC_MAC_TIMESTAMP, 267 DYNAMIC_MAC_SRC_PORT, 268 ALU_STAT_INDEX, 269 }; 270 271 enum ksz_xmii_ctrl0 { 272 P_MII_100MBIT, 273 P_MII_10MBIT, 274 P_MII_FULL_DUPLEX, 275 P_MII_HALF_DUPLEX, 276 }; 277 278 enum ksz_xmii_ctrl1 { 279 P_RGMII_SEL, 280 P_RMII_SEL, 281 P_GMII_SEL, 282 P_MII_SEL, 283 P_GMII_1GBIT, 284 P_GMII_NOT_1GBIT, 285 }; 286 287 struct alu_struct { 288 /* entry 1 */ 289 u8 is_static:1; 290 u8 is_src_filter:1; 291 u8 is_dst_filter:1; 292 u8 prio_age:3; 293 u32 _reserv_0_1:23; 294 u8 mstp:3; 295 /* entry 2 */ 296 u8 is_override:1; 297 u8 is_use_fid:1; 298 u32 _reserv_1_1:23; 299 u8 port_forward:7; 300 /* entry 3 & 4*/ 301 u32 _reserv_2_1:9; 302 u8 fid:7; 303 u8 mac[ETH_ALEN]; 304 }; 305 306 struct ksz_dev_ops { 307 int (*setup)(struct dsa_switch *ds); 308 void (*teardown)(struct dsa_switch *ds); 309 u32 (*get_port_addr)(int port, int offset); 310 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 311 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 312 void (*port_cleanup)(struct ksz_device *dev, int port); 313 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 314 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 315 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 316 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 317 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 318 u64 *cnt); 319 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 320 u64 *dropped, u64 *cnt); 321 void (*r_mib_stat64)(struct ksz_device *dev, int port); 322 int (*vlan_filtering)(struct ksz_device *dev, int port, 323 bool flag, struct netlink_ext_ack *extack); 324 int (*vlan_add)(struct ksz_device *dev, int port, 325 const struct switchdev_obj_port_vlan *vlan, 326 struct netlink_ext_ack *extack); 327 int (*vlan_del)(struct ksz_device *dev, int port, 328 const struct switchdev_obj_port_vlan *vlan); 329 int (*mirror_add)(struct ksz_device *dev, int port, 330 struct dsa_mall_mirror_tc_entry *mirror, 331 bool ingress, struct netlink_ext_ack *extack); 332 void (*mirror_del)(struct ksz_device *dev, int port, 333 struct dsa_mall_mirror_tc_entry *mirror); 334 int (*fdb_add)(struct ksz_device *dev, int port, 335 const unsigned char *addr, u16 vid, struct dsa_db db); 336 int (*fdb_del)(struct ksz_device *dev, int port, 337 const unsigned char *addr, u16 vid, struct dsa_db db); 338 int (*fdb_dump)(struct ksz_device *dev, int port, 339 dsa_fdb_dump_cb_t *cb, void *data); 340 int (*mdb_add)(struct ksz_device *dev, int port, 341 const struct switchdev_obj_port_mdb *mdb, 342 struct dsa_db db); 343 int (*mdb_del)(struct ksz_device *dev, int port, 344 const struct switchdev_obj_port_mdb *mdb, 345 struct dsa_db db); 346 void (*get_caps)(struct ksz_device *dev, int port, 347 struct phylink_config *config); 348 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 349 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 350 void (*port_init_cnt)(struct ksz_device *dev, int port); 351 void (*phylink_mac_config)(struct ksz_device *dev, int port, 352 unsigned int mode, 353 const struct phylink_link_state *state); 354 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 355 unsigned int mode, 356 phy_interface_t interface, 357 struct phy_device *phydev, int speed, 358 int duplex, bool tx_pause, bool rx_pause); 359 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 360 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 361 void (*get_wol)(struct ksz_device *dev, int port, 362 struct ethtool_wolinfo *wol); 363 int (*set_wol)(struct ksz_device *dev, int port, 364 struct ethtool_wolinfo *wol); 365 void (*wol_pre_shutdown)(struct ksz_device *dev, bool *wol_enabled); 366 void (*config_cpu_port)(struct dsa_switch *ds); 367 int (*enable_stp_addr)(struct ksz_device *dev); 368 int (*reset)(struct ksz_device *dev); 369 int (*init)(struct ksz_device *dev); 370 void (*exit)(struct ksz_device *dev); 371 }; 372 373 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 374 int ksz_switch_register(struct ksz_device *dev); 375 void ksz_switch_remove(struct ksz_device *dev); 376 377 void ksz_init_mib_timer(struct ksz_device *dev); 378 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port); 379 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 380 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 381 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 382 bool ksz_get_gbit(struct ksz_device *dev, int port); 383 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 384 extern const struct ksz_chip_data ksz_switch_chips[]; 385 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 386 struct netlink_ext_ack *extack); 387 void ksz_switch_macaddr_put(struct dsa_switch *ds); 388 void ksz_switch_shutdown(struct ksz_device *dev); 389 390 /* Common register access functions */ 391 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 392 { 393 return dev->regmap[KSZ_REGMAP_8]; 394 } 395 396 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 397 { 398 return dev->regmap[KSZ_REGMAP_16]; 399 } 400 401 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 402 { 403 return dev->regmap[KSZ_REGMAP_32]; 404 } 405 406 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 407 { 408 unsigned int value; 409 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 410 411 if (ret) 412 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 413 ERR_PTR(ret)); 414 415 *val = value; 416 return ret; 417 } 418 419 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 420 { 421 unsigned int value; 422 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 423 424 if (ret) 425 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 426 ERR_PTR(ret)); 427 428 *val = value; 429 return ret; 430 } 431 432 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 433 { 434 unsigned int value; 435 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 436 437 if (ret) 438 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 439 ERR_PTR(ret)); 440 441 *val = value; 442 return ret; 443 } 444 445 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 446 { 447 u32 value[2]; 448 int ret; 449 450 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 451 if (ret) 452 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 453 ERR_PTR(ret)); 454 else 455 *val = (u64)value[0] << 32 | value[1]; 456 457 return ret; 458 } 459 460 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 461 { 462 int ret; 463 464 ret = regmap_write(ksz_regmap_8(dev), reg, value); 465 if (ret) 466 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 467 ERR_PTR(ret)); 468 469 return ret; 470 } 471 472 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 473 { 474 int ret; 475 476 ret = regmap_write(ksz_regmap_16(dev), reg, value); 477 if (ret) 478 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 479 ERR_PTR(ret)); 480 481 return ret; 482 } 483 484 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 485 { 486 int ret; 487 488 ret = regmap_write(ksz_regmap_32(dev), reg, value); 489 if (ret) 490 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 491 ERR_PTR(ret)); 492 493 return ret; 494 } 495 496 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 497 u16 value) 498 { 499 int ret; 500 501 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 502 if (ret) 503 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 504 ERR_PTR(ret)); 505 506 return ret; 507 } 508 509 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 510 u32 value) 511 { 512 int ret; 513 514 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 515 if (ret) 516 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 517 ERR_PTR(ret)); 518 519 return ret; 520 } 521 522 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 523 { 524 u32 val[2]; 525 526 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 527 value = swab64(value); 528 val[0] = swab32(value & 0xffffffffULL); 529 val[1] = swab32(value >> 32ULL); 530 531 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 532 } 533 534 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 535 { 536 int ret; 537 538 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 539 if (ret) 540 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 541 ERR_PTR(ret)); 542 543 return ret; 544 } 545 546 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 547 u8 *data) 548 { 549 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 550 } 551 552 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 553 u16 *data) 554 { 555 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 556 } 557 558 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 559 u32 *data) 560 { 561 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 562 } 563 564 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 565 u8 data) 566 { 567 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 568 } 569 570 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 571 u16 data) 572 { 573 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 574 data); 575 } 576 577 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 578 u32 data) 579 { 580 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 581 data); 582 } 583 584 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 585 u8 mask, u8 val) 586 { 587 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 588 mask, val); 589 } 590 591 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 592 u32 mask, u32 val) 593 { 594 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 595 mask, val); 596 } 597 598 static inline void ksz_regmap_lock(void *__mtx) 599 { 600 struct mutex *mtx = __mtx; 601 mutex_lock(mtx); 602 } 603 604 static inline void ksz_regmap_unlock(void *__mtx) 605 { 606 struct mutex *mtx = __mtx; 607 mutex_unlock(mtx); 608 } 609 610 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 611 { 612 return dev->chip_id == KSZ8795_CHIP_ID || 613 dev->chip_id == KSZ8794_CHIP_ID || 614 dev->chip_id == KSZ8765_CHIP_ID; 615 } 616 617 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 618 { 619 return dev->chip_id == KSZ8830_CHIP_ID; 620 } 621 622 static inline int is_lan937x(struct ksz_device *dev) 623 { 624 return dev->chip_id == LAN9370_CHIP_ID || 625 dev->chip_id == LAN9371_CHIP_ID || 626 dev->chip_id == LAN9372_CHIP_ID || 627 dev->chip_id == LAN9373_CHIP_ID || 628 dev->chip_id == LAN9374_CHIP_ID; 629 } 630 631 /* STP State Defines */ 632 #define PORT_TX_ENABLE BIT(2) 633 #define PORT_RX_ENABLE BIT(1) 634 #define PORT_LEARN_DISABLE BIT(0) 635 636 /* Switch ID Defines */ 637 #define REG_CHIP_ID0 0x00 638 639 #define SW_FAMILY_ID_M GENMASK(15, 8) 640 #define KSZ87_FAMILY_ID 0x87 641 #define KSZ88_FAMILY_ID 0x88 642 643 #define KSZ8_PORT_STATUS_0 0x08 644 #define KSZ8_PORT_FIBER_MODE BIT(7) 645 646 #define SW_CHIP_ID_M GENMASK(7, 4) 647 #define KSZ87_CHIP_ID_94 0x6 648 #define KSZ87_CHIP_ID_95 0x9 649 #define KSZ88_CHIP_ID_63 0x3 650 651 #define SW_REV_ID_M GENMASK(7, 4) 652 653 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 654 #define REG_CHIP_ID4 0x0f 655 #define SKU_ID_KSZ8563 0x3c 656 #define SKU_ID_KSZ9563 0x1c 657 658 /* Driver set switch broadcast storm protection at 10% rate. */ 659 #define BROADCAST_STORM_PROT_RATE 10 660 661 /* 148,800 frames * 67 ms / 100 */ 662 #define BROADCAST_STORM_VALUE 9969 663 664 #define BROADCAST_STORM_RATE_HI 0x07 665 #define BROADCAST_STORM_RATE_LO 0xFF 666 #define BROADCAST_STORM_RATE 0x07FF 667 668 #define MULTICAST_STORM_DISABLE BIT(6) 669 670 #define SW_START 0x01 671 672 /* xMII configuration */ 673 #define P_MII_DUPLEX_M BIT(6) 674 #define P_MII_100MBIT_M BIT(4) 675 676 #define P_GMII_1GBIT_M BIT(6) 677 #define P_RGMII_ID_IG_ENABLE BIT(4) 678 #define P_RGMII_ID_EG_ENABLE BIT(3) 679 #define P_MII_MAC_MODE BIT(2) 680 #define P_MII_SEL_M 0x3 681 682 /* Interrupt */ 683 #define REG_SW_PORT_INT_STATUS__1 0x001B 684 #define REG_SW_PORT_INT_MASK__1 0x001F 685 686 #define REG_PORT_INT_STATUS 0x001B 687 #define REG_PORT_INT_MASK 0x001F 688 689 #define PORT_SRC_PHY_INT 1 690 #define PORT_SRC_PTP_INT 2 691 692 #define KSZ8795_HUGE_PACKET_SIZE 2000 693 #define KSZ8863_HUGE_PACKET_SIZE 1916 694 #define KSZ8863_NORMAL_PACKET_SIZE 1536 695 #define KSZ8_LEGAL_PACKET_SIZE 1518 696 #define KSZ9477_MAX_FRAME_SIZE 9000 697 698 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 699 /* Drive Strength of I/O Pad 700 * 0: 8mA, 1: 16mA 701 */ 702 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 703 704 #define KSZ8795_REG_SW_CTRL_20 0xa3 705 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 706 #define SW_DRIVE_STRENGTH_M 0x7 707 #define SW_DRIVE_STRENGTH_2MA 0 708 #define SW_DRIVE_STRENGTH_4MA 1 709 #define SW_DRIVE_STRENGTH_8MA 2 710 #define SW_DRIVE_STRENGTH_12MA 3 711 #define SW_DRIVE_STRENGTH_16MA 4 712 #define SW_DRIVE_STRENGTH_20MA 5 713 #define SW_DRIVE_STRENGTH_24MA 6 714 #define SW_DRIVE_STRENGTH_28MA 7 715 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 716 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 717 718 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 719 #define KSZ9477_OUT_RATE_NO_LIMIT 0 720 721 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 722 723 #define KSZ9477_PORT_TC_MAP_S 4 724 #define KSZ9477_MAX_TC_PRIO 7 725 726 /* CBS related registers */ 727 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 728 729 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 730 731 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 732 #define MTI_SCHEDULE_STRICT_PRIO 0 733 #define MTI_SCHEDULE_WRR 2 734 #define MTI_SHAPING_M GENMASK(5, 4) 735 #define MTI_SHAPING_OFF 0 736 #define MTI_SHAPING_SRP 1 737 #define MTI_SHAPING_TIME_AWARE 2 738 739 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 740 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 741 742 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 743 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 744 745 /* Regmap tables generation */ 746 #define KSZ_SPI_OP_RD 3 747 #define KSZ_SPI_OP_WR 2 748 749 #define swabnot_used(x) 0 750 751 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 752 swab##swp((opcode) << ((regbits) + (regpad))) 753 754 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 755 { \ 756 .name = #width, \ 757 .val_bits = (width), \ 758 .reg_stride = 1, \ 759 .reg_bits = (regbits) + (regalign), \ 760 .pad_bits = (regpad), \ 761 .max_register = BIT(regbits) - 1, \ 762 .cache_type = REGCACHE_NONE, \ 763 .read_flag_mask = \ 764 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 765 regbits, regpad), \ 766 .write_flag_mask = \ 767 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 768 regbits, regpad), \ 769 .lock = ksz_regmap_lock, \ 770 .unlock = ksz_regmap_unlock, \ 771 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 772 .val_format_endian = REGMAP_ENDIAN_BIG \ 773 } 774 775 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 776 static const struct regmap_config ksz##_regmap_config[] = { \ 777 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 778 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 779 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 780 } 781 782 #endif 783