1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2025 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/pcs/pcs-xpcs.h> 14 #include <linux/phy.h> 15 #include <linux/regmap.h> 16 #include <net/dsa.h> 17 #include <linux/irq.h> 18 #include <linux/platform_data/microchip-ksz.h> 19 20 #include "ksz_ptp.h" 21 22 #define KSZ_MAX_NUM_PORTS 8 23 /* all KSZ switches count ports from 1 */ 24 #define KSZ_PORT_1 0 25 #define KSZ_PORT_2 1 26 #define KSZ_PORT_4 3 27 28 struct ksz_device; 29 struct ksz_port; 30 struct phylink_mac_ops; 31 32 enum ksz_regmap_width { 33 KSZ_REGMAP_8, 34 KSZ_REGMAP_16, 35 KSZ_REGMAP_32, 36 __KSZ_NUM_REGMAPS, 37 }; 38 39 struct vlan_table { 40 u32 table[3]; 41 }; 42 43 struct ksz_port_mib { 44 struct mutex cnt_mutex; /* structure access */ 45 u8 cnt_ptr; 46 u64 *counters; 47 struct rtnl_link_stats64 stats64; 48 struct ethtool_pause_stats pause_stats; 49 struct spinlock stats64_lock; 50 }; 51 52 struct ksz_mib_names { 53 int index; 54 char string[ETH_GSTRING_LEN]; 55 }; 56 57 struct ksz_chip_data { 58 u32 chip_id; 59 const char *dev_name; 60 int num_vlans; 61 int num_alus; 62 int num_statics; 63 int cpu_ports; 64 int port_cnt; 65 u8 port_nirqs; 66 u8 num_tx_queues; 67 u8 num_ipms; /* number of Internal Priority Maps */ 68 bool tc_cbs_supported; 69 70 /** 71 * @phy_side_mdio_supported: Indicates if the chip supports an additional 72 * side MDIO channel for accessing integrated PHYs. 73 */ 74 bool phy_side_mdio_supported; 75 const struct ksz_dev_ops *ops; 76 const struct dsa_switch_ops *switch_ops; 77 const struct phylink_mac_ops *phylink_mac_ops; 78 bool phy_errata_9477; 79 bool ksz87xx_eee_link_erratum; 80 const struct ksz_mib_names *mib_names; 81 int mib_cnt; 82 u8 reg_mib_cnt; 83 const u16 *regs; 84 const u32 *masks; 85 const u8 *shifts; 86 const u8 *xmii_ctrl0; 87 const u8 *xmii_ctrl1; 88 int stp_ctrl_reg; 89 int broadcast_ctrl_reg; 90 int multicast_ctrl_reg; 91 int start_ctrl_reg; 92 bool supports_mii[KSZ_MAX_NUM_PORTS]; 93 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 94 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 95 bool internal_phy[KSZ_MAX_NUM_PORTS]; 96 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 97 bool ptp_capable; 98 u8 sgmii_port; 99 const struct regmap_access_table *wr_table; 100 const struct regmap_access_table *rd_table; 101 }; 102 103 struct ksz_irq { 104 u16 masked; 105 u16 reg_mask; 106 u16 reg_status; 107 struct irq_domain *domain; 108 int nirqs; 109 int irq_num; 110 char name[16]; 111 struct ksz_device *dev; 112 u16 irq0_offset; 113 }; 114 115 struct ksz_ptp_irq { 116 struct ksz_port *port; 117 u16 ts_reg; 118 bool ts_en; 119 char name[16]; 120 int num; 121 }; 122 123 struct ksz_switch_macaddr { 124 unsigned char addr[ETH_ALEN]; 125 refcount_t refcount; 126 }; 127 128 struct ksz_port { 129 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 130 bool learning; 131 bool isolated; 132 int stp_state; 133 int speed; 134 int duplex; 135 bool link; 136 137 u32 fiber:1; /* port is fiber */ 138 u32 force:1; 139 u32 read:1; /* read MIB counters in background */ 140 u32 freeze:1; /* MIB counter freeze is enabled */ 141 u32 sgmii_adv_write:1; 142 143 struct ksz_port_mib mib; 144 phy_interface_t interface; 145 u32 rgmii_tx_val; 146 u32 rgmii_rx_val; 147 struct ksz_device *ksz_dev; 148 void *acl_priv; 149 struct ksz_irq pirq; 150 u8 num; 151 struct phylink_pcs *pcs; 152 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 153 struct kernel_hwtstamp_config tstamp_config; 154 bool hwts_tx_en; 155 bool hwts_rx_en; 156 struct ksz_irq ptpirq; 157 struct ksz_ptp_irq ptpmsg_irq[3]; 158 ktime_t tstamp_msg; 159 struct completion tstamp_msg_comp; 160 #endif 161 bool manual_flow; 162 }; 163 164 struct ksz_device { 165 struct dsa_switch *ds; 166 struct ksz_platform_data *pdata; 167 const struct ksz_chip_data *info; 168 169 struct mutex dev_mutex; /* device access */ 170 struct mutex regmap_mutex; /* regmap access */ 171 struct mutex alu_mutex; /* ALU access */ 172 struct mutex vlan_mutex; /* vlan access */ 173 const struct ksz_dev_ops *dev_ops; 174 175 struct device *dev; 176 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 177 178 void *priv; 179 int irq; 180 181 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 182 183 /* chip specific data */ 184 u32 chip_id; 185 u8 chip_rev; 186 int cpu_port; /* port connected to CPU */ 187 int phy_port_cnt; 188 phy_interface_t compat_interface; 189 bool synclko_125; 190 bool synclko_disable; 191 bool wakeup_source; 192 bool pme_active_high; 193 194 struct vlan_table *vlan_cache; 195 196 struct ksz_port *ports; 197 struct delayed_work mib_read; 198 unsigned long mib_read_interval; 199 u16 mirror_rx; 200 u16 mirror_tx; 201 u16 port_mask; 202 struct mutex lock_irq; /* IRQ Access */ 203 struct ksz_irq girq; 204 struct ksz_ptp_data ptp_data; 205 206 struct ksz_switch_macaddr *switch_macaddr; 207 struct net_device *hsr_dev; /* HSR */ 208 u8 hsr_ports; 209 210 /** 211 * @phy_addr_map: Array mapping switch ports to their corresponding PHY 212 * addresses. 213 */ 214 u8 phy_addr_map[KSZ_MAX_NUM_PORTS]; 215 216 /** 217 * @parent_mdio_bus: Pointer to the external MDIO bus controller. 218 * 219 * This points to an external MDIO bus controller that is used to access 220 * the PHYs integrated within the switch. Unlike an integrated MDIO 221 * bus, this external controller provides a direct path for managing 222 * the switch’s internal PHYs, bypassing the main SPI interface. 223 */ 224 struct mii_bus *parent_mdio_bus; 225 }; 226 227 /* List of supported models */ 228 enum ksz_model { 229 KSZ8463, 230 KSZ8563, 231 KSZ8567, 232 KSZ8795, 233 KSZ8794, 234 KSZ8765, 235 KSZ88X3, 236 KSZ8864, 237 KSZ8895, 238 KSZ9477, 239 KSZ9896, 240 KSZ9897, 241 KSZ9893, 242 KSZ9563, 243 KSZ9567, 244 LAN9370, 245 LAN9371, 246 LAN9372, 247 LAN9373, 248 LAN9374, 249 LAN9646, 250 }; 251 252 enum ksz_regs { 253 REG_SW_MAC_ADDR, 254 REG_IND_CTRL_0, 255 REG_IND_DATA_8, 256 REG_IND_DATA_CHECK, 257 REG_IND_DATA_HI, 258 REG_IND_DATA_LO, 259 REG_IND_MIB_CHECK, 260 REG_IND_BYTE, 261 P_FORCE_CTRL, 262 P_LINK_STATUS, 263 P_LOCAL_CTRL, 264 P_NEG_RESTART_CTRL, 265 P_REMOTE_STATUS, 266 P_SPEED_STATUS, 267 S_TAIL_TAG_CTRL, 268 P_STP_CTRL, 269 S_START_CTRL, 270 S_BROADCAST_CTRL, 271 S_MULTICAST_CTRL, 272 P_XMII_CTRL_0, 273 P_XMII_CTRL_1, 274 REG_SW_PME_CTRL, 275 REG_PORT_PME_STATUS, 276 REG_PORT_PME_CTRL, 277 PTP_CLK_CTRL, 278 PTP_RTC_NANOSEC, 279 PTP_RTC_SEC, 280 PTP_RTC_SUB_NANOSEC, 281 PTP_SUBNANOSEC_RATE, 282 PTP_MSG_CONF1, 283 }; 284 285 enum ksz_masks { 286 PORT_802_1P_REMAPPING, 287 SW_TAIL_TAG_ENABLE, 288 MIB_COUNTER_OVERFLOW, 289 MIB_COUNTER_VALID, 290 VLAN_TABLE_FID, 291 VLAN_TABLE_MEMBERSHIP, 292 VLAN_TABLE_VALID, 293 STATIC_MAC_TABLE_VALID, 294 STATIC_MAC_TABLE_USE_FID, 295 STATIC_MAC_TABLE_FID, 296 STATIC_MAC_TABLE_OVERRIDE, 297 STATIC_MAC_TABLE_FWD_PORTS, 298 DYNAMIC_MAC_TABLE_ENTRIES_H, 299 DYNAMIC_MAC_TABLE_MAC_EMPTY, 300 DYNAMIC_MAC_TABLE_NOT_READY, 301 DYNAMIC_MAC_TABLE_ENTRIES, 302 DYNAMIC_MAC_TABLE_FID, 303 DYNAMIC_MAC_TABLE_SRC_PORT, 304 DYNAMIC_MAC_TABLE_TIMESTAMP, 305 ALU_STAT_WRITE, 306 ALU_STAT_READ, 307 ALU_STAT_DIRECT, 308 ALU_RESV_MCAST_ADDR, 309 P_MII_TX_FLOW_CTRL, 310 P_MII_RX_FLOW_CTRL, 311 }; 312 313 enum ksz_shifts { 314 VLAN_TABLE_MEMBERSHIP_S, 315 VLAN_TABLE, 316 STATIC_MAC_FWD_PORTS, 317 STATIC_MAC_FID, 318 DYNAMIC_MAC_ENTRIES_H, 319 DYNAMIC_MAC_ENTRIES, 320 DYNAMIC_MAC_FID, 321 DYNAMIC_MAC_TIMESTAMP, 322 DYNAMIC_MAC_SRC_PORT, 323 ALU_STAT_INDEX, 324 }; 325 326 enum ksz_xmii_ctrl0 { 327 P_MII_100MBIT, 328 P_MII_10MBIT, 329 P_MII_FULL_DUPLEX, 330 P_MII_HALF_DUPLEX, 331 }; 332 333 enum ksz_xmii_ctrl1 { 334 P_RGMII_SEL, 335 P_RMII_SEL, 336 P_GMII_SEL, 337 P_MII_SEL, 338 P_GMII_1GBIT, 339 P_GMII_NOT_1GBIT, 340 }; 341 342 struct alu_struct { 343 /* entry 1 */ 344 u8 is_static:1; 345 u8 is_src_filter:1; 346 u8 is_dst_filter:1; 347 u8 prio_age:3; 348 u32 _reserv_0_1:23; 349 u8 mstp:3; 350 /* entry 2 */ 351 u8 is_override:1; 352 u8 is_use_fid:1; 353 u32 _reserv_1_1:23; 354 u8 port_forward:7; 355 /* entry 3 & 4*/ 356 u32 _reserv_2_1:9; 357 u8 fid:7; 358 u8 mac[ETH_ALEN]; 359 }; 360 361 struct ksz_dev_ops { 362 int (*setup)(struct dsa_switch *ds); 363 void (*teardown)(struct dsa_switch *ds); 364 u32 (*get_port_addr)(int port, int offset); 365 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 366 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 367 368 /** 369 * @mdio_bus_preinit: Function pointer to pre-initialize the MDIO bus 370 * for accessing PHYs. 371 * @dev: Pointer to device structure. 372 * @side_mdio: Boolean indicating if the PHYs are accessed over a side 373 * MDIO bus. 374 * 375 * This function pointer is used to configure the MDIO bus for PHY 376 * access before initiating regular PHY operations. It enables either 377 * SPI/I2C or side MDIO access modes by unlocking necessary registers 378 * and setting up access permissions for the selected mode. 379 * 380 * Return: 381 * - 0 on success. 382 * - Negative error code on failure. 383 */ 384 int (*mdio_bus_preinit)(struct ksz_device *dev, bool side_mdio); 385 386 /** 387 * @create_phy_addr_map: Function pointer to create a port-to-PHY 388 * address map. 389 * @dev: Pointer to device structure. 390 * @side_mdio: Boolean indicating if the PHYs are accessed over a side 391 * MDIO bus. 392 * 393 * This function pointer is responsible for mapping switch ports to PHY 394 * addresses according to the configured access mode (SPI or side MDIO) 395 * and the device’s strap configuration. The mapping setup may vary 396 * depending on the chip variant and configuration. Ensures the correct 397 * address mapping for PHY communication. 398 * 399 * Return: 400 * - 0 on success. 401 * - Negative error code on failure (e.g., invalid configuration). 402 */ 403 int (*create_phy_addr_map)(struct ksz_device *dev, bool side_mdio); 404 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 405 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 406 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 407 u64 *cnt); 408 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 409 u64 *dropped, u64 *cnt); 410 void (*r_mib_stat64)(struct ksz_device *dev, int port); 411 int (*pme_write8)(struct ksz_device *dev, u32 reg, u8 value); 412 int (*pme_pread8)(struct ksz_device *dev, int port, int offset, 413 u8 *data); 414 int (*pme_pwrite8)(struct ksz_device *dev, int port, int offset, 415 u8 data); 416 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 417 void (*port_init_cnt)(struct ksz_device *dev, int port); 418 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 419 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 420 void (*config_cpu_port)(struct dsa_switch *ds); 421 int (*enable_stp_addr)(struct ksz_device *dev); 422 int (*reset)(struct ksz_device *dev); 423 int (*init)(struct ksz_device *dev); 424 void (*exit)(struct ksz_device *dev); 425 426 int (*pcs_create)(struct ksz_device *dev); 427 }; 428 429 struct ksz_device *ksz_switch_alloc(struct device *base, 430 const struct ksz_chip_data *chip, 431 void *priv); 432 int ksz_switch_register(struct ksz_device *dev); 433 void ksz_switch_remove(struct ksz_device *dev); 434 int ksz_switch_suspend(struct device *dev); 435 int ksz_switch_resume(struct device *dev); 436 437 int ksz_setup(struct dsa_switch *ds); 438 void ksz_teardown(struct dsa_switch *ds); 439 int ksz_port_setup(struct dsa_switch *ds, int port); 440 void ksz_port_teardown(struct dsa_switch *ds, int port); 441 442 void ksz_init_mib_timer(struct ksz_device *dev); 443 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port); 444 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 445 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 446 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 447 bool ksz_get_gbit(struct ksz_device *dev, int port); 448 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 449 extern const struct ksz_chip_data ksz_switch_chips[]; 450 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 451 struct netlink_ext_ack *extack); 452 void ksz_switch_macaddr_put(struct dsa_switch *ds); 453 void ksz_switch_shutdown(struct ksz_device *dev); 454 int ksz_handle_wake_reason(struct ksz_device *dev, int port); 455 456 int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg); 457 int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val); 458 u32 ksz_get_phy_flags(struct dsa_switch *ds, int port); 459 460 int ksz_sset_count(struct dsa_switch *ds, int port, int sset); 461 void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 462 uint64_t *buf); 463 void ksz_get_stats64(struct dsa_switch *ds, int port, 464 struct rtnl_link_stats64 *s); 465 void ksz_get_pause_stats(struct dsa_switch *ds, int port, 466 struct ethtool_pause_stats *pause_stats); 467 void ksz_get_strings(struct dsa_switch *ds, int port, 468 u32 stringset, uint8_t *buf); 469 470 int ksz_port_bridge_join(struct dsa_switch *ds, int port, 471 struct dsa_bridge bridge, 472 bool *tx_fwd_offload, 473 struct netlink_ext_ack *extack); 474 void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 475 struct dsa_bridge bridge); 476 int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 477 struct switchdev_brport_flags flags, 478 struct netlink_ext_ack *extack); 479 int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 480 struct switchdev_brport_flags flags, 481 struct netlink_ext_ack *extack); 482 483 void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 484 struct phylink_config *config); 485 void ksz_phylink_mac_disable_tx_lpi(struct phylink_config *config); 486 int ksz_phylink_mac_enable_tx_lpi(struct phylink_config *config, 487 u32 timer, bool tx_clock_stop); 488 void ksz_phylink_mac_config(struct phylink_config *config, 489 unsigned int mode, 490 const struct phylink_link_state *state); 491 void ksz_phylink_mac_link_down(struct phylink_config *config, 492 unsigned int mode, 493 phy_interface_t interface); 494 495 int ksz_max_mtu(struct dsa_switch *ds, int port); 496 497 bool ksz_support_eee(struct dsa_switch *ds, int port); 498 int ksz_set_mac_eee(struct dsa_switch *ds, int port, 499 struct ethtool_keee *e); 500 501 int ksz_cls_flower_add(struct dsa_switch *ds, int port, 502 struct flow_cls_offload *cls, bool ingress); 503 int ksz_cls_flower_del(struct dsa_switch *ds, int port, 504 struct flow_cls_offload *cls, bool ingress); 505 int ksz_setup_tc(struct dsa_switch *ds, int port, 506 enum tc_setup_type type, void *type_data); 507 508 void ksz_get_wol(struct dsa_switch *ds, int port, 509 struct ethtool_wolinfo *wol); 510 int ksz_set_wol(struct dsa_switch *ds, int port, 511 struct ethtool_wolinfo *wol); 512 int ksz_port_set_mac_address(struct dsa_switch *ds, int port, 513 const unsigned char *addr); 514 int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr, 515 struct netlink_ext_ack *extack); 516 int ksz_hsr_leave(struct dsa_switch *ds, int port, 517 struct net_device *hsr); 518 519 int ksz_suspend(struct dsa_switch *ds); 520 int ksz_resume(struct dsa_switch *ds); 521 522 /* Common register access functions */ 523 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 524 { 525 return dev->regmap[KSZ_REGMAP_8]; 526 } 527 528 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 529 { 530 return dev->regmap[KSZ_REGMAP_16]; 531 } 532 533 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 534 { 535 return dev->regmap[KSZ_REGMAP_32]; 536 } 537 538 static inline bool ksz_is_ksz8463(struct ksz_device *dev) 539 { 540 return dev->chip_id == KSZ8463_CHIP_ID; 541 } 542 543 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 544 { 545 unsigned int value; 546 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 547 548 if (ret) 549 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 550 ERR_PTR(ret)); 551 552 *val = value; 553 return ret; 554 } 555 556 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 557 { 558 unsigned int value; 559 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 560 561 if (ret) 562 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 563 ERR_PTR(ret)); 564 565 *val = value; 566 return ret; 567 } 568 569 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 570 { 571 unsigned int value; 572 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 573 574 if (ret) 575 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 576 ERR_PTR(ret)); 577 578 *val = value; 579 return ret; 580 } 581 582 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 583 { 584 u32 value[2]; 585 int ret; 586 587 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 588 if (ret) 589 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 590 ERR_PTR(ret)); 591 else 592 *val = (u64)value[0] << 32 | value[1]; 593 594 return ret; 595 } 596 597 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 598 { 599 int ret; 600 601 ret = regmap_write(ksz_regmap_8(dev), reg, value); 602 if (ret) 603 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 604 ERR_PTR(ret)); 605 606 return ret; 607 } 608 609 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 610 { 611 int ret; 612 613 ret = regmap_write(ksz_regmap_16(dev), reg, value); 614 if (ret) 615 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 616 ERR_PTR(ret)); 617 618 return ret; 619 } 620 621 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 622 { 623 int ret; 624 625 ret = regmap_write(ksz_regmap_32(dev), reg, value); 626 if (ret) 627 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 628 ERR_PTR(ret)); 629 630 return ret; 631 } 632 633 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 634 u16 value) 635 { 636 int ret; 637 638 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 639 if (ret) 640 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 641 ERR_PTR(ret)); 642 643 return ret; 644 } 645 646 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 647 u32 value) 648 { 649 int ret; 650 651 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 652 if (ret) 653 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 654 ERR_PTR(ret)); 655 656 return ret; 657 } 658 659 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 660 { 661 u32 val[2]; 662 663 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 664 value = swab64(value); 665 val[0] = swab32(value & 0xffffffffULL); 666 val[1] = swab32(value >> 32ULL); 667 668 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 669 } 670 671 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 672 { 673 int ret; 674 675 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 676 if (ret) 677 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 678 ERR_PTR(ret)); 679 680 return ret; 681 } 682 683 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 684 u8 *data) 685 { 686 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 687 } 688 689 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 690 u16 *data) 691 { 692 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 693 } 694 695 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 696 u32 *data) 697 { 698 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 699 } 700 701 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 702 u8 data) 703 { 704 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 705 } 706 707 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 708 u16 data) 709 { 710 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 711 data); 712 } 713 714 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 715 u32 data) 716 { 717 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 718 data); 719 } 720 721 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 722 u8 mask, u8 val) 723 { 724 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 725 mask, val); 726 } 727 728 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 729 u32 mask, u32 val) 730 { 731 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 732 mask, val); 733 } 734 735 static inline void ksz_regmap_lock(void *__mtx) 736 { 737 struct mutex *mtx = __mtx; 738 mutex_lock(mtx); 739 } 740 741 static inline void ksz_regmap_unlock(void *__mtx) 742 { 743 struct mutex *mtx = __mtx; 744 mutex_unlock(mtx); 745 } 746 747 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 748 { 749 return dev->chip_id == KSZ8795_CHIP_ID || 750 dev->chip_id == KSZ8794_CHIP_ID || 751 dev->chip_id == KSZ8765_CHIP_ID; 752 } 753 754 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 755 { 756 return dev->chip_id == KSZ88X3_CHIP_ID; 757 } 758 759 static inline bool ksz_is_8895_family(struct ksz_device *dev) 760 { 761 return dev->chip_id == KSZ8895_CHIP_ID || 762 dev->chip_id == KSZ8864_CHIP_ID; 763 } 764 765 static inline bool is_ksz8(struct ksz_device *dev) 766 { 767 return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev) || 768 ksz_is_8895_family(dev) || ksz_is_ksz8463(dev); 769 } 770 771 static inline bool is_ksz88xx(struct ksz_device *dev) 772 { 773 return ksz_is_ksz88x3(dev) || ksz_is_8895_family(dev) || 774 ksz_is_ksz8463(dev); 775 } 776 777 static inline bool is_ksz9477(struct ksz_device *dev) 778 { 779 return dev->chip_id == KSZ9477_CHIP_ID; 780 } 781 782 static inline int is_lan937x(struct ksz_device *dev) 783 { 784 return dev->chip_id == LAN9370_CHIP_ID || 785 dev->chip_id == LAN9371_CHIP_ID || 786 dev->chip_id == LAN9372_CHIP_ID || 787 dev->chip_id == LAN9373_CHIP_ID || 788 dev->chip_id == LAN9374_CHIP_ID; 789 } 790 791 static inline bool is_lan937x_tx_phy(struct ksz_device *dev, int port) 792 { 793 return (dev->chip_id == LAN9371_CHIP_ID || 794 dev->chip_id == LAN9372_CHIP_ID) && port == KSZ_PORT_4; 795 } 796 797 static inline int ksz_get_sgmii_port(struct ksz_device *dev) 798 { 799 return dev->info->sgmii_port - 1; 800 } 801 802 static inline bool ksz_has_sgmii_port(struct ksz_device *dev) 803 { 804 return dev->info->sgmii_port > 0; 805 } 806 807 static inline bool ksz_is_sgmii_port(struct ksz_device *dev, int port) 808 { 809 return dev->info->sgmii_port == port + 1; 810 } 811 812 /* STP State Defines */ 813 #define PORT_TX_ENABLE BIT(2) 814 #define PORT_RX_ENABLE BIT(1) 815 #define PORT_LEARN_DISABLE BIT(0) 816 817 /* Switch ID Defines */ 818 #define REG_CHIP_ID0 0x00 819 820 #define SW_FAMILY_ID_M GENMASK(15, 8) 821 #define KSZ84_FAMILY_ID 0x84 822 #define KSZ87_FAMILY_ID 0x87 823 #define KSZ88_FAMILY_ID 0x88 824 #define KSZ8895_FAMILY_ID 0x95 825 826 #define KSZ8_PORT_STATUS_0 0x08 827 #define KSZ8_PORT_FIBER_MODE BIT(7) 828 829 #define SW_CHIP_ID_M GENMASK(7, 4) 830 #define KSZ87_CHIP_ID_94 0x6 831 #define KSZ87_CHIP_ID_95 0x9 832 #define KSZ88_CHIP_ID_63 0x3 833 #define KSZ8895_CHIP_ID_95 0x4 834 #define KSZ8895_CHIP_ID_95R 0x6 835 836 /* KSZ8895 specific register */ 837 #define REG_KSZ8864_CHIP_ID 0xFE 838 #define SW_KSZ8864 BIT(7) 839 840 #define SW_REV_ID_M GENMASK(7, 4) 841 842 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 843 #define REG_CHIP_ID4 0x0f 844 #define SKU_ID_KSZ8563 0x3c 845 #define SKU_ID_KSZ9563 0x1c 846 847 /* Driver set switch broadcast storm protection at 10% rate. */ 848 #define BROADCAST_STORM_PROT_RATE 10 849 850 /* 148,800 frames * 67 ms / 100 */ 851 #define BROADCAST_STORM_VALUE 9969 852 853 #define BROADCAST_STORM_RATE_HI 0x07 854 #define BROADCAST_STORM_RATE_LO 0xFF 855 #define BROADCAST_STORM_RATE 0x07FF 856 857 #define MULTICAST_STORM_DISABLE BIT(6) 858 859 #define SW_START 0x01 860 861 /* xMII configuration */ 862 #define P_MII_DUPLEX_M BIT(6) 863 #define P_MII_100MBIT_M BIT(4) 864 865 #define P_GMII_1GBIT_M BIT(6) 866 #define P_RGMII_ID_IG_ENABLE BIT(4) 867 #define P_RGMII_ID_EG_ENABLE BIT(3) 868 #define P_MII_MAC_MODE BIT(2) 869 #define P_MII_SEL_M 0x3 870 871 /* KSZ9477, KSZ87xx Wake-on-LAN (WoL) masks */ 872 #define PME_WOL_MAGICPKT BIT(2) 873 #define PME_WOL_LINKUP BIT(1) 874 #define PME_WOL_ENERGY BIT(0) 875 876 #define PME_ENABLE BIT(1) 877 #define PME_POLARITY BIT(0) 878 879 #define KSZ87XX_REG_INT_EN 0x7D 880 #define KSZ87XX_INT_PME_MASK BIT(4) 881 882 /* Interrupt */ 883 #define REG_SW_PORT_INT_STATUS__1 0x001B 884 #define REG_SW_PORT_INT_MASK__1 0x001F 885 886 #define REG_PORT_INT_STATUS 0x001B 887 #define REG_PORT_INT_MASK 0x001F 888 889 #define PORT_SRC_PHY_INT 1 890 #define PORT_SRC_PTP_INT 2 891 892 #define KSZ8795_HUGE_PACKET_SIZE 2000 893 #define KSZ8863_HUGE_PACKET_SIZE 1916 894 #define KSZ8863_NORMAL_PACKET_SIZE 1536 895 #define KSZ8_LEGAL_PACKET_SIZE 1518 896 #define KSZ9477_MAX_FRAME_SIZE 9000 897 898 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 899 /* Drive Strength of I/O Pad 900 * 0: 8mA, 1: 16mA 901 */ 902 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 903 904 #define KSZ8795_REG_SW_CTRL_20 0xa3 905 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 906 #define SW_DRIVE_STRENGTH_M 0x7 907 #define SW_DRIVE_STRENGTH_2MA 0 908 #define SW_DRIVE_STRENGTH_4MA 1 909 #define SW_DRIVE_STRENGTH_8MA 2 910 #define SW_DRIVE_STRENGTH_12MA 3 911 #define SW_DRIVE_STRENGTH_16MA 4 912 #define SW_DRIVE_STRENGTH_20MA 5 913 #define SW_DRIVE_STRENGTH_24MA 6 914 #define SW_DRIVE_STRENGTH_28MA 7 915 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 916 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 917 918 /* TXQ Split Control Register for per-port, per-queue configuration. 919 * Register 0xAF is TXQ Split for Q3 on Port 1. 920 * Register offset formula: 0xAF + (port * 4) + (3 - queue) 921 * where: port = 0..2, queue = 0..3 922 */ 923 #define KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue) \ 924 (0xAF + ((port) * 4) + (3 - (queue))) 925 926 /* Bit 7 selects between: 927 * 0 = Strict priority mode (highest-priority queue first) 928 * 1 = Weighted Fair Queuing (WFQ) mode: 929 * Queue weights: Q3:Q2:Q1:Q0 = 8:4:2:1 930 * If any queues are empty, weight is redistributed. 931 * 932 * Note: This is referred to as "Weighted Fair Queuing" (WFQ) in KSZ8863/8873 933 * documentation, and as "Weighted Round Robin" (WRR) in KSZ9477 family docs. 934 */ 935 #define KSZ8873_TXQ_WFQ_ENABLE BIT(7) 936 937 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 938 #define KSZ9477_OUT_RATE_NO_LIMIT 0 939 940 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 941 942 #define KSZ9477_PORT_TC_MAP_S 4 943 944 /* CBS related registers */ 945 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 946 947 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 948 949 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 950 #define MTI_SCHEDULE_STRICT_PRIO 0 951 #define MTI_SCHEDULE_WRR 2 952 #define MTI_SHAPING_M GENMASK(5, 4) 953 #define MTI_SHAPING_OFF 0 954 #define MTI_SHAPING_SRP 1 955 #define MTI_SHAPING_TIME_AWARE 2 956 957 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 958 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 959 960 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 961 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 962 963 /* Regmap tables generation */ 964 #define KSZ_SPI_OP_RD 3 965 #define KSZ_SPI_OP_WR 2 966 967 #define swabnot_used(x) 0 968 969 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 970 swab##swp((opcode) << ((regbits) + (regpad))) 971 972 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 973 { \ 974 .name = #width, \ 975 .val_bits = (width), \ 976 .reg_stride = 1, \ 977 .reg_bits = (regbits) + (regalign), \ 978 .pad_bits = (regpad), \ 979 .max_register = BIT(regbits) - 1, \ 980 .cache_type = REGCACHE_NONE, \ 981 .read_flag_mask = \ 982 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 983 regbits, regpad), \ 984 .write_flag_mask = \ 985 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 986 regbits, regpad), \ 987 .lock = ksz_regmap_lock, \ 988 .unlock = ksz_regmap_unlock, \ 989 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 990 .val_format_endian = REGMAP_ENDIAN_BIG \ 991 } 992 993 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 994 static const struct regmap_config ksz##_regmap_config[] = { \ 995 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 996 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 997 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 998 } 999 1000 #define KSZ8463_REGMAP_ENTRY(width, regbits, regpad, regalign) \ 1001 { \ 1002 .name = #width, \ 1003 .val_bits = (width), \ 1004 .reg_stride = (width / 8), \ 1005 .reg_bits = (regbits) + (regalign), \ 1006 .pad_bits = (regpad), \ 1007 .read = ksz8463_spi_read, \ 1008 .write = ksz8463_spi_write, \ 1009 .max_register = BIT(regbits) - 1, \ 1010 .cache_type = REGCACHE_NONE, \ 1011 .zero_flag_mask = 1, \ 1012 .use_single_read = 1, \ 1013 .use_single_write = 1, \ 1014 .lock = ksz_regmap_lock, \ 1015 .unlock = ksz_regmap_unlock, \ 1016 } 1017 1018 #define KSZ8463_REGMAP_TABLE(ksz, regbits, regpad, regalign) \ 1019 static const struct regmap_config ksz##_regmap_config[] = { \ 1020 [KSZ_REGMAP_8] = KSZ8463_REGMAP_ENTRY(8, (regbits), (regpad), (regalign)), \ 1021 [KSZ_REGMAP_16] = KSZ8463_REGMAP_ENTRY(16, (regbits), (regpad), (regalign)), \ 1022 [KSZ_REGMAP_32] = KSZ8463_REGMAP_ENTRY(32, (regbits), (regpad), (regalign)), \ 1023 } 1024 1025 #endif 1026