1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 18 #include "ksz_ptp.h" 19 20 #define KSZ_MAX_NUM_PORTS 8 21 22 struct ksz_device; 23 struct ksz_port; 24 25 enum ksz_regmap_width { 26 KSZ_REGMAP_8, 27 KSZ_REGMAP_16, 28 KSZ_REGMAP_32, 29 __KSZ_NUM_REGMAPS, 30 }; 31 32 struct vlan_table { 33 u32 table[3]; 34 }; 35 36 struct ksz_port_mib { 37 struct mutex cnt_mutex; /* structure access */ 38 u8 cnt_ptr; 39 u64 *counters; 40 struct rtnl_link_stats64 stats64; 41 struct ethtool_pause_stats pause_stats; 42 struct spinlock stats64_lock; 43 }; 44 45 struct ksz_mib_names { 46 int index; 47 char string[ETH_GSTRING_LEN]; 48 }; 49 50 struct ksz_chip_data { 51 u32 chip_id; 52 const char *dev_name; 53 int num_vlans; 54 int num_alus; 55 int num_statics; 56 int cpu_ports; 57 int port_cnt; 58 u8 port_nirqs; 59 u8 num_tx_queues; 60 bool tc_cbs_supported; 61 bool tc_ets_supported; 62 const struct ksz_dev_ops *ops; 63 bool ksz87xx_eee_link_erratum; 64 const struct ksz_mib_names *mib_names; 65 int mib_cnt; 66 u8 reg_mib_cnt; 67 const u16 *regs; 68 const u32 *masks; 69 const u8 *shifts; 70 const u8 *xmii_ctrl0; 71 const u8 *xmii_ctrl1; 72 int stp_ctrl_reg; 73 int broadcast_ctrl_reg; 74 int multicast_ctrl_reg; 75 int start_ctrl_reg; 76 bool supports_mii[KSZ_MAX_NUM_PORTS]; 77 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 78 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 79 bool internal_phy[KSZ_MAX_NUM_PORTS]; 80 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 81 const struct regmap_access_table *wr_table; 82 const struct regmap_access_table *rd_table; 83 }; 84 85 struct ksz_irq { 86 u16 masked; 87 u16 reg_mask; 88 u16 reg_status; 89 struct irq_domain *domain; 90 int nirqs; 91 int irq_num; 92 char name[16]; 93 struct ksz_device *dev; 94 }; 95 96 struct ksz_ptp_irq { 97 struct ksz_port *port; 98 u16 ts_reg; 99 bool ts_en; 100 char name[16]; 101 int num; 102 }; 103 104 struct ksz_switch_macaddr { 105 unsigned char addr[ETH_ALEN]; 106 refcount_t refcount; 107 }; 108 109 struct ksz_port { 110 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 111 bool learning; 112 int stp_state; 113 struct phy_device phydev; 114 115 u32 fiber:1; /* port is fiber */ 116 u32 force:1; 117 u32 read:1; /* read MIB counters in background */ 118 u32 freeze:1; /* MIB counter freeze is enabled */ 119 120 struct ksz_port_mib mib; 121 phy_interface_t interface; 122 u32 rgmii_tx_val; 123 u32 rgmii_rx_val; 124 struct ksz_device *ksz_dev; 125 void *acl_priv; 126 struct ksz_irq pirq; 127 u8 num; 128 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 129 struct hwtstamp_config tstamp_config; 130 bool hwts_tx_en; 131 bool hwts_rx_en; 132 struct ksz_irq ptpirq; 133 struct ksz_ptp_irq ptpmsg_irq[3]; 134 ktime_t tstamp_msg; 135 struct completion tstamp_msg_comp; 136 #endif 137 }; 138 139 struct ksz_device { 140 struct dsa_switch *ds; 141 struct ksz_platform_data *pdata; 142 const struct ksz_chip_data *info; 143 144 struct mutex dev_mutex; /* device access */ 145 struct mutex regmap_mutex; /* regmap access */ 146 struct mutex alu_mutex; /* ALU access */ 147 struct mutex vlan_mutex; /* vlan access */ 148 const struct ksz_dev_ops *dev_ops; 149 150 struct device *dev; 151 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 152 153 void *priv; 154 int irq; 155 156 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 157 158 /* chip specific data */ 159 u32 chip_id; 160 u8 chip_rev; 161 int cpu_port; /* port connected to CPU */ 162 int phy_port_cnt; 163 phy_interface_t compat_interface; 164 bool synclko_125; 165 bool synclko_disable; 166 167 struct vlan_table *vlan_cache; 168 169 struct ksz_port *ports; 170 struct delayed_work mib_read; 171 unsigned long mib_read_interval; 172 u16 mirror_rx; 173 u16 mirror_tx; 174 u16 port_mask; 175 struct mutex lock_irq; /* IRQ Access */ 176 struct ksz_irq girq; 177 struct ksz_ptp_data ptp_data; 178 179 struct ksz_switch_macaddr *switch_macaddr; 180 struct net_device *hsr_dev; /* HSR */ 181 u8 hsr_ports; 182 }; 183 184 /* List of supported models */ 185 enum ksz_model { 186 KSZ8563, 187 KSZ8795, 188 KSZ8794, 189 KSZ8765, 190 KSZ8830, 191 KSZ9477, 192 KSZ9896, 193 KSZ9897, 194 KSZ9893, 195 KSZ9563, 196 KSZ9567, 197 LAN9370, 198 LAN9371, 199 LAN9372, 200 LAN9373, 201 LAN9374, 202 }; 203 204 enum ksz_chip_id { 205 KSZ8563_CHIP_ID = 0x8563, 206 KSZ8795_CHIP_ID = 0x8795, 207 KSZ8794_CHIP_ID = 0x8794, 208 KSZ8765_CHIP_ID = 0x8765, 209 KSZ8830_CHIP_ID = 0x8830, 210 KSZ9477_CHIP_ID = 0x00947700, 211 KSZ9896_CHIP_ID = 0x00989600, 212 KSZ9897_CHIP_ID = 0x00989700, 213 KSZ9893_CHIP_ID = 0x00989300, 214 KSZ9563_CHIP_ID = 0x00956300, 215 KSZ9567_CHIP_ID = 0x00956700, 216 LAN9370_CHIP_ID = 0x00937000, 217 LAN9371_CHIP_ID = 0x00937100, 218 LAN9372_CHIP_ID = 0x00937200, 219 LAN9373_CHIP_ID = 0x00937300, 220 LAN9374_CHIP_ID = 0x00937400, 221 }; 222 223 enum ksz_regs { 224 REG_SW_MAC_ADDR, 225 REG_IND_CTRL_0, 226 REG_IND_DATA_8, 227 REG_IND_DATA_CHECK, 228 REG_IND_DATA_HI, 229 REG_IND_DATA_LO, 230 REG_IND_MIB_CHECK, 231 REG_IND_BYTE, 232 P_FORCE_CTRL, 233 P_LINK_STATUS, 234 P_LOCAL_CTRL, 235 P_NEG_RESTART_CTRL, 236 P_REMOTE_STATUS, 237 P_SPEED_STATUS, 238 S_TAIL_TAG_CTRL, 239 P_STP_CTRL, 240 S_START_CTRL, 241 S_BROADCAST_CTRL, 242 S_MULTICAST_CTRL, 243 P_XMII_CTRL_0, 244 P_XMII_CTRL_1, 245 }; 246 247 enum ksz_masks { 248 PORT_802_1P_REMAPPING, 249 SW_TAIL_TAG_ENABLE, 250 MIB_COUNTER_OVERFLOW, 251 MIB_COUNTER_VALID, 252 VLAN_TABLE_FID, 253 VLAN_TABLE_MEMBERSHIP, 254 VLAN_TABLE_VALID, 255 STATIC_MAC_TABLE_VALID, 256 STATIC_MAC_TABLE_USE_FID, 257 STATIC_MAC_TABLE_FID, 258 STATIC_MAC_TABLE_OVERRIDE, 259 STATIC_MAC_TABLE_FWD_PORTS, 260 DYNAMIC_MAC_TABLE_ENTRIES_H, 261 DYNAMIC_MAC_TABLE_MAC_EMPTY, 262 DYNAMIC_MAC_TABLE_NOT_READY, 263 DYNAMIC_MAC_TABLE_ENTRIES, 264 DYNAMIC_MAC_TABLE_FID, 265 DYNAMIC_MAC_TABLE_SRC_PORT, 266 DYNAMIC_MAC_TABLE_TIMESTAMP, 267 ALU_STAT_WRITE, 268 ALU_STAT_READ, 269 P_MII_TX_FLOW_CTRL, 270 P_MII_RX_FLOW_CTRL, 271 }; 272 273 enum ksz_shifts { 274 VLAN_TABLE_MEMBERSHIP_S, 275 VLAN_TABLE, 276 STATIC_MAC_FWD_PORTS, 277 STATIC_MAC_FID, 278 DYNAMIC_MAC_ENTRIES_H, 279 DYNAMIC_MAC_ENTRIES, 280 DYNAMIC_MAC_FID, 281 DYNAMIC_MAC_TIMESTAMP, 282 DYNAMIC_MAC_SRC_PORT, 283 ALU_STAT_INDEX, 284 }; 285 286 enum ksz_xmii_ctrl0 { 287 P_MII_100MBIT, 288 P_MII_10MBIT, 289 P_MII_FULL_DUPLEX, 290 P_MII_HALF_DUPLEX, 291 }; 292 293 enum ksz_xmii_ctrl1 { 294 P_RGMII_SEL, 295 P_RMII_SEL, 296 P_GMII_SEL, 297 P_MII_SEL, 298 P_GMII_1GBIT, 299 P_GMII_NOT_1GBIT, 300 }; 301 302 struct alu_struct { 303 /* entry 1 */ 304 u8 is_static:1; 305 u8 is_src_filter:1; 306 u8 is_dst_filter:1; 307 u8 prio_age:3; 308 u32 _reserv_0_1:23; 309 u8 mstp:3; 310 /* entry 2 */ 311 u8 is_override:1; 312 u8 is_use_fid:1; 313 u32 _reserv_1_1:23; 314 u8 port_forward:7; 315 /* entry 3 & 4*/ 316 u32 _reserv_2_1:9; 317 u8 fid:7; 318 u8 mac[ETH_ALEN]; 319 }; 320 321 struct ksz_dev_ops { 322 int (*setup)(struct dsa_switch *ds); 323 void (*teardown)(struct dsa_switch *ds); 324 u32 (*get_port_addr)(int port, int offset); 325 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 326 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 327 void (*port_cleanup)(struct ksz_device *dev, int port); 328 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 329 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 330 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 331 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 332 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 333 u64 *cnt); 334 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 335 u64 *dropped, u64 *cnt); 336 void (*r_mib_stat64)(struct ksz_device *dev, int port); 337 int (*vlan_filtering)(struct ksz_device *dev, int port, 338 bool flag, struct netlink_ext_ack *extack); 339 int (*vlan_add)(struct ksz_device *dev, int port, 340 const struct switchdev_obj_port_vlan *vlan, 341 struct netlink_ext_ack *extack); 342 int (*vlan_del)(struct ksz_device *dev, int port, 343 const struct switchdev_obj_port_vlan *vlan); 344 int (*mirror_add)(struct ksz_device *dev, int port, 345 struct dsa_mall_mirror_tc_entry *mirror, 346 bool ingress, struct netlink_ext_ack *extack); 347 void (*mirror_del)(struct ksz_device *dev, int port, 348 struct dsa_mall_mirror_tc_entry *mirror); 349 int (*fdb_add)(struct ksz_device *dev, int port, 350 const unsigned char *addr, u16 vid, struct dsa_db db); 351 int (*fdb_del)(struct ksz_device *dev, int port, 352 const unsigned char *addr, u16 vid, struct dsa_db db); 353 int (*fdb_dump)(struct ksz_device *dev, int port, 354 dsa_fdb_dump_cb_t *cb, void *data); 355 int (*mdb_add)(struct ksz_device *dev, int port, 356 const struct switchdev_obj_port_mdb *mdb, 357 struct dsa_db db); 358 int (*mdb_del)(struct ksz_device *dev, int port, 359 const struct switchdev_obj_port_mdb *mdb, 360 struct dsa_db db); 361 void (*get_caps)(struct ksz_device *dev, int port, 362 struct phylink_config *config); 363 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 364 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 365 void (*port_init_cnt)(struct ksz_device *dev, int port); 366 void (*phylink_mac_config)(struct ksz_device *dev, int port, 367 unsigned int mode, 368 const struct phylink_link_state *state); 369 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 370 unsigned int mode, 371 phy_interface_t interface, 372 struct phy_device *phydev, int speed, 373 int duplex, bool tx_pause, bool rx_pause); 374 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 375 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 376 void (*config_cpu_port)(struct dsa_switch *ds); 377 int (*enable_stp_addr)(struct ksz_device *dev); 378 int (*reset)(struct ksz_device *dev); 379 int (*init)(struct ksz_device *dev); 380 void (*exit)(struct ksz_device *dev); 381 }; 382 383 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 384 int ksz_switch_register(struct ksz_device *dev); 385 void ksz_switch_remove(struct ksz_device *dev); 386 387 void ksz_init_mib_timer(struct ksz_device *dev); 388 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 389 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 390 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 391 bool ksz_get_gbit(struct ksz_device *dev, int port); 392 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 393 extern const struct ksz_chip_data ksz_switch_chips[]; 394 395 /* Common register access functions */ 396 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 397 { 398 return dev->regmap[KSZ_REGMAP_8]; 399 } 400 401 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 402 { 403 return dev->regmap[KSZ_REGMAP_16]; 404 } 405 406 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 407 { 408 return dev->regmap[KSZ_REGMAP_32]; 409 } 410 411 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 412 { 413 unsigned int value; 414 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 415 416 if (ret) 417 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 418 ERR_PTR(ret)); 419 420 *val = value; 421 return ret; 422 } 423 424 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 425 { 426 unsigned int value; 427 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 428 429 if (ret) 430 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 431 ERR_PTR(ret)); 432 433 *val = value; 434 return ret; 435 } 436 437 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 438 { 439 unsigned int value; 440 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 441 442 if (ret) 443 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 444 ERR_PTR(ret)); 445 446 *val = value; 447 return ret; 448 } 449 450 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 451 { 452 u32 value[2]; 453 int ret; 454 455 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 456 if (ret) 457 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 458 ERR_PTR(ret)); 459 else 460 *val = (u64)value[0] << 32 | value[1]; 461 462 return ret; 463 } 464 465 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 466 { 467 int ret; 468 469 ret = regmap_write(ksz_regmap_8(dev), reg, value); 470 if (ret) 471 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 472 ERR_PTR(ret)); 473 474 return ret; 475 } 476 477 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 478 { 479 int ret; 480 481 ret = regmap_write(ksz_regmap_16(dev), reg, value); 482 if (ret) 483 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 484 ERR_PTR(ret)); 485 486 return ret; 487 } 488 489 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 490 { 491 int ret; 492 493 ret = regmap_write(ksz_regmap_32(dev), reg, value); 494 if (ret) 495 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 496 ERR_PTR(ret)); 497 498 return ret; 499 } 500 501 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 502 u16 value) 503 { 504 int ret; 505 506 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 507 if (ret) 508 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 509 ERR_PTR(ret)); 510 511 return ret; 512 } 513 514 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 515 u32 value) 516 { 517 int ret; 518 519 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 520 if (ret) 521 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 522 ERR_PTR(ret)); 523 524 return ret; 525 } 526 527 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 528 { 529 u32 val[2]; 530 531 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 532 value = swab64(value); 533 val[0] = swab32(value & 0xffffffffULL); 534 val[1] = swab32(value >> 32ULL); 535 536 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 537 } 538 539 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 540 { 541 int ret; 542 543 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 544 if (ret) 545 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 546 ERR_PTR(ret)); 547 548 return ret; 549 } 550 551 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 552 u8 *data) 553 { 554 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 555 } 556 557 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 558 u16 *data) 559 { 560 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 561 } 562 563 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 564 u32 *data) 565 { 566 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 567 } 568 569 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 570 u8 data) 571 { 572 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 573 } 574 575 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 576 u16 data) 577 { 578 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 579 data); 580 } 581 582 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 583 u32 data) 584 { 585 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 586 data); 587 } 588 589 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 590 u8 mask, u8 val) 591 { 592 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 593 mask, val); 594 } 595 596 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 597 u32 mask, u32 val) 598 { 599 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 600 mask, val); 601 } 602 603 static inline void ksz_regmap_lock(void *__mtx) 604 { 605 struct mutex *mtx = __mtx; 606 mutex_lock(mtx); 607 } 608 609 static inline void ksz_regmap_unlock(void *__mtx) 610 { 611 struct mutex *mtx = __mtx; 612 mutex_unlock(mtx); 613 } 614 615 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 616 { 617 return dev->chip_id == KSZ8795_CHIP_ID || 618 dev->chip_id == KSZ8794_CHIP_ID || 619 dev->chip_id == KSZ8765_CHIP_ID; 620 } 621 622 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 623 { 624 return dev->chip_id == KSZ8830_CHIP_ID; 625 } 626 627 static inline int is_lan937x(struct ksz_device *dev) 628 { 629 return dev->chip_id == LAN9370_CHIP_ID || 630 dev->chip_id == LAN9371_CHIP_ID || 631 dev->chip_id == LAN9372_CHIP_ID || 632 dev->chip_id == LAN9373_CHIP_ID || 633 dev->chip_id == LAN9374_CHIP_ID; 634 } 635 636 /* STP State Defines */ 637 #define PORT_TX_ENABLE BIT(2) 638 #define PORT_RX_ENABLE BIT(1) 639 #define PORT_LEARN_DISABLE BIT(0) 640 641 /* Switch ID Defines */ 642 #define REG_CHIP_ID0 0x00 643 644 #define SW_FAMILY_ID_M GENMASK(15, 8) 645 #define KSZ87_FAMILY_ID 0x87 646 #define KSZ88_FAMILY_ID 0x88 647 648 #define KSZ8_PORT_STATUS_0 0x08 649 #define KSZ8_PORT_FIBER_MODE BIT(7) 650 651 #define SW_CHIP_ID_M GENMASK(7, 4) 652 #define KSZ87_CHIP_ID_94 0x6 653 #define KSZ87_CHIP_ID_95 0x9 654 #define KSZ88_CHIP_ID_63 0x3 655 656 #define SW_REV_ID_M GENMASK(7, 4) 657 658 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 659 #define REG_CHIP_ID4 0x0f 660 #define SKU_ID_KSZ8563 0x3c 661 #define SKU_ID_KSZ9563 0x1c 662 663 /* Driver set switch broadcast storm protection at 10% rate. */ 664 #define BROADCAST_STORM_PROT_RATE 10 665 666 /* 148,800 frames * 67 ms / 100 */ 667 #define BROADCAST_STORM_VALUE 9969 668 669 #define BROADCAST_STORM_RATE_HI 0x07 670 #define BROADCAST_STORM_RATE_LO 0xFF 671 #define BROADCAST_STORM_RATE 0x07FF 672 673 #define MULTICAST_STORM_DISABLE BIT(6) 674 675 #define SW_START 0x01 676 677 /* xMII configuration */ 678 #define P_MII_DUPLEX_M BIT(6) 679 #define P_MII_100MBIT_M BIT(4) 680 681 #define P_GMII_1GBIT_M BIT(6) 682 #define P_RGMII_ID_IG_ENABLE BIT(4) 683 #define P_RGMII_ID_EG_ENABLE BIT(3) 684 #define P_MII_MAC_MODE BIT(2) 685 #define P_MII_SEL_M 0x3 686 687 /* Interrupt */ 688 #define REG_SW_PORT_INT_STATUS__1 0x001B 689 #define REG_SW_PORT_INT_MASK__1 0x001F 690 691 #define REG_PORT_INT_STATUS 0x001B 692 #define REG_PORT_INT_MASK 0x001F 693 694 #define PORT_SRC_PHY_INT 1 695 #define PORT_SRC_PTP_INT 2 696 697 #define KSZ8795_HUGE_PACKET_SIZE 2000 698 #define KSZ8863_HUGE_PACKET_SIZE 1916 699 #define KSZ8863_NORMAL_PACKET_SIZE 1536 700 #define KSZ8_LEGAL_PACKET_SIZE 1518 701 #define KSZ9477_MAX_FRAME_SIZE 9000 702 703 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 704 /* Drive Strength of I/O Pad 705 * 0: 8mA, 1: 16mA 706 */ 707 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 708 709 #define KSZ8795_REG_SW_CTRL_20 0xa3 710 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 711 #define SW_DRIVE_STRENGTH_M 0x7 712 #define SW_DRIVE_STRENGTH_2MA 0 713 #define SW_DRIVE_STRENGTH_4MA 1 714 #define SW_DRIVE_STRENGTH_8MA 2 715 #define SW_DRIVE_STRENGTH_12MA 3 716 #define SW_DRIVE_STRENGTH_16MA 4 717 #define SW_DRIVE_STRENGTH_20MA 5 718 #define SW_DRIVE_STRENGTH_24MA 6 719 #define SW_DRIVE_STRENGTH_28MA 7 720 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 721 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 722 723 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 724 #define KSZ9477_OUT_RATE_NO_LIMIT 0 725 726 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 727 728 #define KSZ9477_PORT_TC_MAP_S 4 729 #define KSZ9477_MAX_TC_PRIO 7 730 731 /* CBS related registers */ 732 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 733 734 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 735 736 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 737 #define MTI_SCHEDULE_STRICT_PRIO 0 738 #define MTI_SCHEDULE_WRR 2 739 #define MTI_SHAPING_M GENMASK(5, 4) 740 #define MTI_SHAPING_OFF 0 741 #define MTI_SHAPING_SRP 1 742 #define MTI_SHAPING_TIME_AWARE 2 743 744 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 745 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 746 747 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 748 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 749 750 /* Regmap tables generation */ 751 #define KSZ_SPI_OP_RD 3 752 #define KSZ_SPI_OP_WR 2 753 754 #define swabnot_used(x) 0 755 756 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 757 swab##swp((opcode) << ((regbits) + (regpad))) 758 759 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 760 { \ 761 .name = #width, \ 762 .val_bits = (width), \ 763 .reg_stride = 1, \ 764 .reg_bits = (regbits) + (regalign), \ 765 .pad_bits = (regpad), \ 766 .max_register = BIT(regbits) - 1, \ 767 .cache_type = REGCACHE_NONE, \ 768 .read_flag_mask = \ 769 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 770 regbits, regpad), \ 771 .write_flag_mask = \ 772 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 773 regbits, regpad), \ 774 .lock = ksz_regmap_lock, \ 775 .unlock = ksz_regmap_unlock, \ 776 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 777 .val_format_endian = REGMAP_ENDIAN_BIG \ 778 } 779 780 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 781 static const struct regmap_config ksz##_regmap_config[] = { \ 782 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 783 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 784 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 785 } 786 787 #endif 788