1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/of.h> 22 #include <linux/of_mdio.h> 23 #include <linux/of_net.h> 24 #include <linux/micrel_phy.h> 25 #include <net/dsa.h> 26 #include <net/pkt_cls.h> 27 #include <net/switchdev.h> 28 29 #include "ksz_common.h" 30 #include "ksz_ptp.h" 31 #include "ksz8.h" 32 #include "ksz9477.h" 33 #include "lan937x.h" 34 35 #define MIB_COUNTER_NUM 0x20 36 37 struct ksz_stats_raw { 38 u64 rx_hi; 39 u64 rx_undersize; 40 u64 rx_fragments; 41 u64 rx_oversize; 42 u64 rx_jabbers; 43 u64 rx_symbol_err; 44 u64 rx_crc_err; 45 u64 rx_align_err; 46 u64 rx_mac_ctrl; 47 u64 rx_pause; 48 u64 rx_bcast; 49 u64 rx_mcast; 50 u64 rx_ucast; 51 u64 rx_64_or_less; 52 u64 rx_65_127; 53 u64 rx_128_255; 54 u64 rx_256_511; 55 u64 rx_512_1023; 56 u64 rx_1024_1522; 57 u64 rx_1523_2000; 58 u64 rx_2001; 59 u64 tx_hi; 60 u64 tx_late_col; 61 u64 tx_pause; 62 u64 tx_bcast; 63 u64 tx_mcast; 64 u64 tx_ucast; 65 u64 tx_deferred; 66 u64 tx_total_col; 67 u64 tx_exc_col; 68 u64 tx_single_col; 69 u64 tx_mult_col; 70 u64 rx_total; 71 u64 tx_total; 72 u64 rx_discards; 73 u64 tx_discards; 74 }; 75 76 struct ksz88xx_stats_raw { 77 u64 rx; 78 u64 rx_hi; 79 u64 rx_undersize; 80 u64 rx_fragments; 81 u64 rx_oversize; 82 u64 rx_jabbers; 83 u64 rx_symbol_err; 84 u64 rx_crc_err; 85 u64 rx_align_err; 86 u64 rx_mac_ctrl; 87 u64 rx_pause; 88 u64 rx_bcast; 89 u64 rx_mcast; 90 u64 rx_ucast; 91 u64 rx_64_or_less; 92 u64 rx_65_127; 93 u64 rx_128_255; 94 u64 rx_256_511; 95 u64 rx_512_1023; 96 u64 rx_1024_1522; 97 u64 tx; 98 u64 tx_hi; 99 u64 tx_late_col; 100 u64 tx_pause; 101 u64 tx_bcast; 102 u64 tx_mcast; 103 u64 tx_ucast; 104 u64 tx_deferred; 105 u64 tx_total_col; 106 u64 tx_exc_col; 107 u64 tx_single_col; 108 u64 tx_mult_col; 109 u64 rx_discards; 110 u64 tx_discards; 111 }; 112 113 static const struct ksz_mib_names ksz88xx_mib_names[] = { 114 { 0x00, "rx" }, 115 { 0x01, "rx_hi" }, 116 { 0x02, "rx_undersize" }, 117 { 0x03, "rx_fragments" }, 118 { 0x04, "rx_oversize" }, 119 { 0x05, "rx_jabbers" }, 120 { 0x06, "rx_symbol_err" }, 121 { 0x07, "rx_crc_err" }, 122 { 0x08, "rx_align_err" }, 123 { 0x09, "rx_mac_ctrl" }, 124 { 0x0a, "rx_pause" }, 125 { 0x0b, "rx_bcast" }, 126 { 0x0c, "rx_mcast" }, 127 { 0x0d, "rx_ucast" }, 128 { 0x0e, "rx_64_or_less" }, 129 { 0x0f, "rx_65_127" }, 130 { 0x10, "rx_128_255" }, 131 { 0x11, "rx_256_511" }, 132 { 0x12, "rx_512_1023" }, 133 { 0x13, "rx_1024_1522" }, 134 { 0x14, "tx" }, 135 { 0x15, "tx_hi" }, 136 { 0x16, "tx_late_col" }, 137 { 0x17, "tx_pause" }, 138 { 0x18, "tx_bcast" }, 139 { 0x19, "tx_mcast" }, 140 { 0x1a, "tx_ucast" }, 141 { 0x1b, "tx_deferred" }, 142 { 0x1c, "tx_total_col" }, 143 { 0x1d, "tx_exc_col" }, 144 { 0x1e, "tx_single_col" }, 145 { 0x1f, "tx_mult_col" }, 146 { 0x100, "rx_discards" }, 147 { 0x101, "tx_discards" }, 148 }; 149 150 static const struct ksz_mib_names ksz9477_mib_names[] = { 151 { 0x00, "rx_hi" }, 152 { 0x01, "rx_undersize" }, 153 { 0x02, "rx_fragments" }, 154 { 0x03, "rx_oversize" }, 155 { 0x04, "rx_jabbers" }, 156 { 0x05, "rx_symbol_err" }, 157 { 0x06, "rx_crc_err" }, 158 { 0x07, "rx_align_err" }, 159 { 0x08, "rx_mac_ctrl" }, 160 { 0x09, "rx_pause" }, 161 { 0x0A, "rx_bcast" }, 162 { 0x0B, "rx_mcast" }, 163 { 0x0C, "rx_ucast" }, 164 { 0x0D, "rx_64_or_less" }, 165 { 0x0E, "rx_65_127" }, 166 { 0x0F, "rx_128_255" }, 167 { 0x10, "rx_256_511" }, 168 { 0x11, "rx_512_1023" }, 169 { 0x12, "rx_1024_1522" }, 170 { 0x13, "rx_1523_2000" }, 171 { 0x14, "rx_2001" }, 172 { 0x15, "tx_hi" }, 173 { 0x16, "tx_late_col" }, 174 { 0x17, "tx_pause" }, 175 { 0x18, "tx_bcast" }, 176 { 0x19, "tx_mcast" }, 177 { 0x1A, "tx_ucast" }, 178 { 0x1B, "tx_deferred" }, 179 { 0x1C, "tx_total_col" }, 180 { 0x1D, "tx_exc_col" }, 181 { 0x1E, "tx_single_col" }, 182 { 0x1F, "tx_mult_col" }, 183 { 0x80, "rx_total" }, 184 { 0x81, "tx_total" }, 185 { 0x82, "rx_discards" }, 186 { 0x83, "tx_discards" }, 187 }; 188 189 struct ksz_driver_strength_prop { 190 const char *name; 191 int offset; 192 int value; 193 }; 194 195 enum ksz_driver_strength_type { 196 KSZ_DRIVER_STRENGTH_HI, 197 KSZ_DRIVER_STRENGTH_LO, 198 KSZ_DRIVER_STRENGTH_IO, 199 }; 200 201 /** 202 * struct ksz_drive_strength - drive strength mapping 203 * @reg_val: register value 204 * @microamp: microamp value 205 */ 206 struct ksz_drive_strength { 207 u32 reg_val; 208 u32 microamp; 209 }; 210 211 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants 212 * 213 * This values are not documented in KSZ9477 variants but confirmed by 214 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893 215 * and KSZ8563 are using same register (drive strength) settings like KSZ8795. 216 * 217 * Documentation in KSZ8795CLX provides more information with some 218 * recommendations: 219 * - for high speed signals 220 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using 221 * 2.5V or 3.3V VDDIO. 222 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with 223 * using 1.8V VDDIO. 224 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V 225 * or 3.3V VDDIO. 226 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO. 227 * 5. In same interface, the heavy loading should use higher one of the 228 * drive current strength. 229 * - for low speed signals 230 * 1. 3.3V VDDIO, use either 4 mA or 8 mA. 231 * 2. 2.5V VDDIO, use either 8 mA or 12 mA. 232 * 3. 1.8V VDDIO, use either 12 mA or 16 mA. 233 * 4. If it is heavy loading, can use higher drive current strength. 234 */ 235 static const struct ksz_drive_strength ksz9477_drive_strengths[] = { 236 { SW_DRIVE_STRENGTH_2MA, 2000 }, 237 { SW_DRIVE_STRENGTH_4MA, 4000 }, 238 { SW_DRIVE_STRENGTH_8MA, 8000 }, 239 { SW_DRIVE_STRENGTH_12MA, 12000 }, 240 { SW_DRIVE_STRENGTH_16MA, 16000 }, 241 { SW_DRIVE_STRENGTH_20MA, 20000 }, 242 { SW_DRIVE_STRENGTH_24MA, 24000 }, 243 { SW_DRIVE_STRENGTH_28MA, 28000 }, 244 }; 245 246 /* ksz8830_drive_strengths - Drive strength mapping for KSZ8830, KSZ8873, .. 247 * variants. 248 * This values are documented in KSZ8873 and KSZ8863 datasheets. 249 */ 250 static const struct ksz_drive_strength ksz8830_drive_strengths[] = { 251 { 0, 8000 }, 252 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 }, 253 }; 254 255 static const struct ksz_dev_ops ksz8_dev_ops = { 256 .setup = ksz8_setup, 257 .get_port_addr = ksz8_get_port_addr, 258 .cfg_port_member = ksz8_cfg_port_member, 259 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 260 .port_setup = ksz8_port_setup, 261 .r_phy = ksz8_r_phy, 262 .w_phy = ksz8_w_phy, 263 .r_mib_cnt = ksz8_r_mib_cnt, 264 .r_mib_pkt = ksz8_r_mib_pkt, 265 .r_mib_stat64 = ksz88xx_r_mib_stats64, 266 .freeze_mib = ksz8_freeze_mib, 267 .port_init_cnt = ksz8_port_init_cnt, 268 .fdb_dump = ksz8_fdb_dump, 269 .fdb_add = ksz8_fdb_add, 270 .fdb_del = ksz8_fdb_del, 271 .mdb_add = ksz8_mdb_add, 272 .mdb_del = ksz8_mdb_del, 273 .vlan_filtering = ksz8_port_vlan_filtering, 274 .vlan_add = ksz8_port_vlan_add, 275 .vlan_del = ksz8_port_vlan_del, 276 .mirror_add = ksz8_port_mirror_add, 277 .mirror_del = ksz8_port_mirror_del, 278 .get_caps = ksz8_get_caps, 279 .config_cpu_port = ksz8_config_cpu_port, 280 .enable_stp_addr = ksz8_enable_stp_addr, 281 .reset = ksz8_reset_switch, 282 .init = ksz8_switch_init, 283 .exit = ksz8_switch_exit, 284 .change_mtu = ksz8_change_mtu, 285 }; 286 287 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 288 unsigned int mode, 289 phy_interface_t interface, 290 struct phy_device *phydev, int speed, 291 int duplex, bool tx_pause, 292 bool rx_pause); 293 294 static const struct ksz_dev_ops ksz9477_dev_ops = { 295 .setup = ksz9477_setup, 296 .get_port_addr = ksz9477_get_port_addr, 297 .cfg_port_member = ksz9477_cfg_port_member, 298 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 299 .port_setup = ksz9477_port_setup, 300 .set_ageing_time = ksz9477_set_ageing_time, 301 .r_phy = ksz9477_r_phy, 302 .w_phy = ksz9477_w_phy, 303 .r_mib_cnt = ksz9477_r_mib_cnt, 304 .r_mib_pkt = ksz9477_r_mib_pkt, 305 .r_mib_stat64 = ksz_r_mib_stats64, 306 .freeze_mib = ksz9477_freeze_mib, 307 .port_init_cnt = ksz9477_port_init_cnt, 308 .vlan_filtering = ksz9477_port_vlan_filtering, 309 .vlan_add = ksz9477_port_vlan_add, 310 .vlan_del = ksz9477_port_vlan_del, 311 .mirror_add = ksz9477_port_mirror_add, 312 .mirror_del = ksz9477_port_mirror_del, 313 .get_caps = ksz9477_get_caps, 314 .fdb_dump = ksz9477_fdb_dump, 315 .fdb_add = ksz9477_fdb_add, 316 .fdb_del = ksz9477_fdb_del, 317 .mdb_add = ksz9477_mdb_add, 318 .mdb_del = ksz9477_mdb_del, 319 .change_mtu = ksz9477_change_mtu, 320 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 321 .config_cpu_port = ksz9477_config_cpu_port, 322 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc, 323 .enable_stp_addr = ksz9477_enable_stp_addr, 324 .reset = ksz9477_reset_switch, 325 .init = ksz9477_switch_init, 326 .exit = ksz9477_switch_exit, 327 }; 328 329 static const struct ksz_dev_ops lan937x_dev_ops = { 330 .setup = lan937x_setup, 331 .teardown = lan937x_teardown, 332 .get_port_addr = ksz9477_get_port_addr, 333 .cfg_port_member = ksz9477_cfg_port_member, 334 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 335 .port_setup = lan937x_port_setup, 336 .set_ageing_time = lan937x_set_ageing_time, 337 .r_phy = lan937x_r_phy, 338 .w_phy = lan937x_w_phy, 339 .r_mib_cnt = ksz9477_r_mib_cnt, 340 .r_mib_pkt = ksz9477_r_mib_pkt, 341 .r_mib_stat64 = ksz_r_mib_stats64, 342 .freeze_mib = ksz9477_freeze_mib, 343 .port_init_cnt = ksz9477_port_init_cnt, 344 .vlan_filtering = ksz9477_port_vlan_filtering, 345 .vlan_add = ksz9477_port_vlan_add, 346 .vlan_del = ksz9477_port_vlan_del, 347 .mirror_add = ksz9477_port_mirror_add, 348 .mirror_del = ksz9477_port_mirror_del, 349 .get_caps = lan937x_phylink_get_caps, 350 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 351 .fdb_dump = ksz9477_fdb_dump, 352 .fdb_add = ksz9477_fdb_add, 353 .fdb_del = ksz9477_fdb_del, 354 .mdb_add = ksz9477_mdb_add, 355 .mdb_del = ksz9477_mdb_del, 356 .change_mtu = lan937x_change_mtu, 357 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 358 .config_cpu_port = lan937x_config_cpu_port, 359 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 360 .enable_stp_addr = ksz9477_enable_stp_addr, 361 .reset = lan937x_reset_switch, 362 .init = lan937x_switch_init, 363 .exit = lan937x_switch_exit, 364 }; 365 366 static const u16 ksz8795_regs[] = { 367 [REG_IND_CTRL_0] = 0x6E, 368 [REG_IND_DATA_8] = 0x70, 369 [REG_IND_DATA_CHECK] = 0x72, 370 [REG_IND_DATA_HI] = 0x71, 371 [REG_IND_DATA_LO] = 0x75, 372 [REG_IND_MIB_CHECK] = 0x74, 373 [REG_IND_BYTE] = 0xA0, 374 [P_FORCE_CTRL] = 0x0C, 375 [P_LINK_STATUS] = 0x0E, 376 [P_LOCAL_CTRL] = 0x07, 377 [P_NEG_RESTART_CTRL] = 0x0D, 378 [P_REMOTE_STATUS] = 0x08, 379 [P_SPEED_STATUS] = 0x09, 380 [S_TAIL_TAG_CTRL] = 0x0C, 381 [P_STP_CTRL] = 0x02, 382 [S_START_CTRL] = 0x01, 383 [S_BROADCAST_CTRL] = 0x06, 384 [S_MULTICAST_CTRL] = 0x04, 385 [P_XMII_CTRL_0] = 0x06, 386 [P_XMII_CTRL_1] = 0x06, 387 }; 388 389 static const u32 ksz8795_masks[] = { 390 [PORT_802_1P_REMAPPING] = BIT(7), 391 [SW_TAIL_TAG_ENABLE] = BIT(1), 392 [MIB_COUNTER_OVERFLOW] = BIT(6), 393 [MIB_COUNTER_VALID] = BIT(5), 394 [VLAN_TABLE_FID] = GENMASK(6, 0), 395 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 396 [VLAN_TABLE_VALID] = BIT(12), 397 [STATIC_MAC_TABLE_VALID] = BIT(21), 398 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 399 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 400 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 401 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 402 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 403 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 404 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 405 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 406 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 407 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 408 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 409 [P_MII_TX_FLOW_CTRL] = BIT(5), 410 [P_MII_RX_FLOW_CTRL] = BIT(5), 411 }; 412 413 static const u8 ksz8795_xmii_ctrl0[] = { 414 [P_MII_100MBIT] = 0, 415 [P_MII_10MBIT] = 1, 416 [P_MII_FULL_DUPLEX] = 0, 417 [P_MII_HALF_DUPLEX] = 1, 418 }; 419 420 static const u8 ksz8795_xmii_ctrl1[] = { 421 [P_RGMII_SEL] = 3, 422 [P_GMII_SEL] = 2, 423 [P_RMII_SEL] = 1, 424 [P_MII_SEL] = 0, 425 [P_GMII_1GBIT] = 1, 426 [P_GMII_NOT_1GBIT] = 0, 427 }; 428 429 static const u8 ksz8795_shifts[] = { 430 [VLAN_TABLE_MEMBERSHIP_S] = 7, 431 [VLAN_TABLE] = 16, 432 [STATIC_MAC_FWD_PORTS] = 16, 433 [STATIC_MAC_FID] = 24, 434 [DYNAMIC_MAC_ENTRIES_H] = 3, 435 [DYNAMIC_MAC_ENTRIES] = 29, 436 [DYNAMIC_MAC_FID] = 16, 437 [DYNAMIC_MAC_TIMESTAMP] = 27, 438 [DYNAMIC_MAC_SRC_PORT] = 24, 439 }; 440 441 static const u16 ksz8863_regs[] = { 442 [REG_IND_CTRL_0] = 0x79, 443 [REG_IND_DATA_8] = 0x7B, 444 [REG_IND_DATA_CHECK] = 0x7B, 445 [REG_IND_DATA_HI] = 0x7C, 446 [REG_IND_DATA_LO] = 0x80, 447 [REG_IND_MIB_CHECK] = 0x80, 448 [P_FORCE_CTRL] = 0x0C, 449 [P_LINK_STATUS] = 0x0E, 450 [P_LOCAL_CTRL] = 0x0C, 451 [P_NEG_RESTART_CTRL] = 0x0D, 452 [P_REMOTE_STATUS] = 0x0E, 453 [P_SPEED_STATUS] = 0x0F, 454 [S_TAIL_TAG_CTRL] = 0x03, 455 [P_STP_CTRL] = 0x02, 456 [S_START_CTRL] = 0x01, 457 [S_BROADCAST_CTRL] = 0x06, 458 [S_MULTICAST_CTRL] = 0x04, 459 }; 460 461 static const u32 ksz8863_masks[] = { 462 [PORT_802_1P_REMAPPING] = BIT(3), 463 [SW_TAIL_TAG_ENABLE] = BIT(6), 464 [MIB_COUNTER_OVERFLOW] = BIT(7), 465 [MIB_COUNTER_VALID] = BIT(6), 466 [VLAN_TABLE_FID] = GENMASK(15, 12), 467 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 468 [VLAN_TABLE_VALID] = BIT(19), 469 [STATIC_MAC_TABLE_VALID] = BIT(19), 470 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 471 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 472 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 473 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 474 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 475 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 476 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 477 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 478 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 479 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 480 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 481 }; 482 483 static u8 ksz8863_shifts[] = { 484 [VLAN_TABLE_MEMBERSHIP_S] = 16, 485 [STATIC_MAC_FWD_PORTS] = 16, 486 [STATIC_MAC_FID] = 22, 487 [DYNAMIC_MAC_ENTRIES_H] = 8, 488 [DYNAMIC_MAC_ENTRIES] = 24, 489 [DYNAMIC_MAC_FID] = 16, 490 [DYNAMIC_MAC_TIMESTAMP] = 22, 491 [DYNAMIC_MAC_SRC_PORT] = 20, 492 }; 493 494 static const u16 ksz9477_regs[] = { 495 [P_STP_CTRL] = 0x0B04, 496 [S_START_CTRL] = 0x0300, 497 [S_BROADCAST_CTRL] = 0x0332, 498 [S_MULTICAST_CTRL] = 0x0331, 499 [P_XMII_CTRL_0] = 0x0300, 500 [P_XMII_CTRL_1] = 0x0301, 501 }; 502 503 static const u32 ksz9477_masks[] = { 504 [ALU_STAT_WRITE] = 0, 505 [ALU_STAT_READ] = 1, 506 [P_MII_TX_FLOW_CTRL] = BIT(5), 507 [P_MII_RX_FLOW_CTRL] = BIT(3), 508 }; 509 510 static const u8 ksz9477_shifts[] = { 511 [ALU_STAT_INDEX] = 16, 512 }; 513 514 static const u8 ksz9477_xmii_ctrl0[] = { 515 [P_MII_100MBIT] = 1, 516 [P_MII_10MBIT] = 0, 517 [P_MII_FULL_DUPLEX] = 1, 518 [P_MII_HALF_DUPLEX] = 0, 519 }; 520 521 static const u8 ksz9477_xmii_ctrl1[] = { 522 [P_RGMII_SEL] = 0, 523 [P_RMII_SEL] = 1, 524 [P_GMII_SEL] = 2, 525 [P_MII_SEL] = 3, 526 [P_GMII_1GBIT] = 0, 527 [P_GMII_NOT_1GBIT] = 1, 528 }; 529 530 static const u32 lan937x_masks[] = { 531 [ALU_STAT_WRITE] = 1, 532 [ALU_STAT_READ] = 2, 533 [P_MII_TX_FLOW_CTRL] = BIT(5), 534 [P_MII_RX_FLOW_CTRL] = BIT(3), 535 }; 536 537 static const u8 lan937x_shifts[] = { 538 [ALU_STAT_INDEX] = 8, 539 }; 540 541 static const struct regmap_range ksz8563_valid_regs[] = { 542 regmap_reg_range(0x0000, 0x0003), 543 regmap_reg_range(0x0006, 0x0006), 544 regmap_reg_range(0x000f, 0x001f), 545 regmap_reg_range(0x0100, 0x0100), 546 regmap_reg_range(0x0104, 0x0107), 547 regmap_reg_range(0x010d, 0x010d), 548 regmap_reg_range(0x0110, 0x0113), 549 regmap_reg_range(0x0120, 0x012b), 550 regmap_reg_range(0x0201, 0x0201), 551 regmap_reg_range(0x0210, 0x0213), 552 regmap_reg_range(0x0300, 0x0300), 553 regmap_reg_range(0x0302, 0x031b), 554 regmap_reg_range(0x0320, 0x032b), 555 regmap_reg_range(0x0330, 0x0336), 556 regmap_reg_range(0x0338, 0x033e), 557 regmap_reg_range(0x0340, 0x035f), 558 regmap_reg_range(0x0370, 0x0370), 559 regmap_reg_range(0x0378, 0x0378), 560 regmap_reg_range(0x037c, 0x037d), 561 regmap_reg_range(0x0390, 0x0393), 562 regmap_reg_range(0x0400, 0x040e), 563 regmap_reg_range(0x0410, 0x042f), 564 regmap_reg_range(0x0500, 0x0519), 565 regmap_reg_range(0x0520, 0x054b), 566 regmap_reg_range(0x0550, 0x05b3), 567 568 /* port 1 */ 569 regmap_reg_range(0x1000, 0x1001), 570 regmap_reg_range(0x1004, 0x100b), 571 regmap_reg_range(0x1013, 0x1013), 572 regmap_reg_range(0x1017, 0x1017), 573 regmap_reg_range(0x101b, 0x101b), 574 regmap_reg_range(0x101f, 0x1021), 575 regmap_reg_range(0x1030, 0x1030), 576 regmap_reg_range(0x1100, 0x1111), 577 regmap_reg_range(0x111a, 0x111d), 578 regmap_reg_range(0x1122, 0x1127), 579 regmap_reg_range(0x112a, 0x112b), 580 regmap_reg_range(0x1136, 0x1139), 581 regmap_reg_range(0x113e, 0x113f), 582 regmap_reg_range(0x1400, 0x1401), 583 regmap_reg_range(0x1403, 0x1403), 584 regmap_reg_range(0x1410, 0x1417), 585 regmap_reg_range(0x1420, 0x1423), 586 regmap_reg_range(0x1500, 0x1507), 587 regmap_reg_range(0x1600, 0x1612), 588 regmap_reg_range(0x1800, 0x180f), 589 regmap_reg_range(0x1900, 0x1907), 590 regmap_reg_range(0x1914, 0x191b), 591 regmap_reg_range(0x1a00, 0x1a03), 592 regmap_reg_range(0x1a04, 0x1a08), 593 regmap_reg_range(0x1b00, 0x1b01), 594 regmap_reg_range(0x1b04, 0x1b04), 595 regmap_reg_range(0x1c00, 0x1c05), 596 regmap_reg_range(0x1c08, 0x1c1b), 597 598 /* port 2 */ 599 regmap_reg_range(0x2000, 0x2001), 600 regmap_reg_range(0x2004, 0x200b), 601 regmap_reg_range(0x2013, 0x2013), 602 regmap_reg_range(0x2017, 0x2017), 603 regmap_reg_range(0x201b, 0x201b), 604 regmap_reg_range(0x201f, 0x2021), 605 regmap_reg_range(0x2030, 0x2030), 606 regmap_reg_range(0x2100, 0x2111), 607 regmap_reg_range(0x211a, 0x211d), 608 regmap_reg_range(0x2122, 0x2127), 609 regmap_reg_range(0x212a, 0x212b), 610 regmap_reg_range(0x2136, 0x2139), 611 regmap_reg_range(0x213e, 0x213f), 612 regmap_reg_range(0x2400, 0x2401), 613 regmap_reg_range(0x2403, 0x2403), 614 regmap_reg_range(0x2410, 0x2417), 615 regmap_reg_range(0x2420, 0x2423), 616 regmap_reg_range(0x2500, 0x2507), 617 regmap_reg_range(0x2600, 0x2612), 618 regmap_reg_range(0x2800, 0x280f), 619 regmap_reg_range(0x2900, 0x2907), 620 regmap_reg_range(0x2914, 0x291b), 621 regmap_reg_range(0x2a00, 0x2a03), 622 regmap_reg_range(0x2a04, 0x2a08), 623 regmap_reg_range(0x2b00, 0x2b01), 624 regmap_reg_range(0x2b04, 0x2b04), 625 regmap_reg_range(0x2c00, 0x2c05), 626 regmap_reg_range(0x2c08, 0x2c1b), 627 628 /* port 3 */ 629 regmap_reg_range(0x3000, 0x3001), 630 regmap_reg_range(0x3004, 0x300b), 631 regmap_reg_range(0x3013, 0x3013), 632 regmap_reg_range(0x3017, 0x3017), 633 regmap_reg_range(0x301b, 0x301b), 634 regmap_reg_range(0x301f, 0x3021), 635 regmap_reg_range(0x3030, 0x3030), 636 regmap_reg_range(0x3300, 0x3301), 637 regmap_reg_range(0x3303, 0x3303), 638 regmap_reg_range(0x3400, 0x3401), 639 regmap_reg_range(0x3403, 0x3403), 640 regmap_reg_range(0x3410, 0x3417), 641 regmap_reg_range(0x3420, 0x3423), 642 regmap_reg_range(0x3500, 0x3507), 643 regmap_reg_range(0x3600, 0x3612), 644 regmap_reg_range(0x3800, 0x380f), 645 regmap_reg_range(0x3900, 0x3907), 646 regmap_reg_range(0x3914, 0x391b), 647 regmap_reg_range(0x3a00, 0x3a03), 648 regmap_reg_range(0x3a04, 0x3a08), 649 regmap_reg_range(0x3b00, 0x3b01), 650 regmap_reg_range(0x3b04, 0x3b04), 651 regmap_reg_range(0x3c00, 0x3c05), 652 regmap_reg_range(0x3c08, 0x3c1b), 653 }; 654 655 static const struct regmap_access_table ksz8563_register_set = { 656 .yes_ranges = ksz8563_valid_regs, 657 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 658 }; 659 660 static const struct regmap_range ksz9477_valid_regs[] = { 661 regmap_reg_range(0x0000, 0x0003), 662 regmap_reg_range(0x0006, 0x0006), 663 regmap_reg_range(0x0010, 0x001f), 664 regmap_reg_range(0x0100, 0x0100), 665 regmap_reg_range(0x0103, 0x0107), 666 regmap_reg_range(0x010d, 0x010d), 667 regmap_reg_range(0x0110, 0x0113), 668 regmap_reg_range(0x0120, 0x012b), 669 regmap_reg_range(0x0201, 0x0201), 670 regmap_reg_range(0x0210, 0x0213), 671 regmap_reg_range(0x0300, 0x0300), 672 regmap_reg_range(0x0302, 0x031b), 673 regmap_reg_range(0x0320, 0x032b), 674 regmap_reg_range(0x0330, 0x0336), 675 regmap_reg_range(0x0338, 0x033b), 676 regmap_reg_range(0x033e, 0x033e), 677 regmap_reg_range(0x0340, 0x035f), 678 regmap_reg_range(0x0370, 0x0370), 679 regmap_reg_range(0x0378, 0x0378), 680 regmap_reg_range(0x037c, 0x037d), 681 regmap_reg_range(0x0390, 0x0393), 682 regmap_reg_range(0x0400, 0x040e), 683 regmap_reg_range(0x0410, 0x042f), 684 regmap_reg_range(0x0444, 0x044b), 685 regmap_reg_range(0x0450, 0x046f), 686 regmap_reg_range(0x0500, 0x0519), 687 regmap_reg_range(0x0520, 0x054b), 688 regmap_reg_range(0x0550, 0x05b3), 689 regmap_reg_range(0x0604, 0x060b), 690 regmap_reg_range(0x0610, 0x0612), 691 regmap_reg_range(0x0614, 0x062c), 692 regmap_reg_range(0x0640, 0x0645), 693 regmap_reg_range(0x0648, 0x064d), 694 695 /* port 1 */ 696 regmap_reg_range(0x1000, 0x1001), 697 regmap_reg_range(0x1013, 0x1013), 698 regmap_reg_range(0x1017, 0x1017), 699 regmap_reg_range(0x101b, 0x101b), 700 regmap_reg_range(0x101f, 0x1020), 701 regmap_reg_range(0x1030, 0x1030), 702 regmap_reg_range(0x1100, 0x1115), 703 regmap_reg_range(0x111a, 0x111f), 704 regmap_reg_range(0x1120, 0x112b), 705 regmap_reg_range(0x1134, 0x113b), 706 regmap_reg_range(0x113c, 0x113f), 707 regmap_reg_range(0x1400, 0x1401), 708 regmap_reg_range(0x1403, 0x1403), 709 regmap_reg_range(0x1410, 0x1417), 710 regmap_reg_range(0x1420, 0x1423), 711 regmap_reg_range(0x1500, 0x1507), 712 regmap_reg_range(0x1600, 0x1613), 713 regmap_reg_range(0x1800, 0x180f), 714 regmap_reg_range(0x1820, 0x1827), 715 regmap_reg_range(0x1830, 0x1837), 716 regmap_reg_range(0x1840, 0x184b), 717 regmap_reg_range(0x1900, 0x1907), 718 regmap_reg_range(0x1914, 0x191b), 719 regmap_reg_range(0x1920, 0x1920), 720 regmap_reg_range(0x1923, 0x1927), 721 regmap_reg_range(0x1a00, 0x1a03), 722 regmap_reg_range(0x1a04, 0x1a07), 723 regmap_reg_range(0x1b00, 0x1b01), 724 regmap_reg_range(0x1b04, 0x1b04), 725 regmap_reg_range(0x1c00, 0x1c05), 726 regmap_reg_range(0x1c08, 0x1c1b), 727 728 /* port 2 */ 729 regmap_reg_range(0x2000, 0x2001), 730 regmap_reg_range(0x2013, 0x2013), 731 regmap_reg_range(0x2017, 0x2017), 732 regmap_reg_range(0x201b, 0x201b), 733 regmap_reg_range(0x201f, 0x2020), 734 regmap_reg_range(0x2030, 0x2030), 735 regmap_reg_range(0x2100, 0x2115), 736 regmap_reg_range(0x211a, 0x211f), 737 regmap_reg_range(0x2120, 0x212b), 738 regmap_reg_range(0x2134, 0x213b), 739 regmap_reg_range(0x213c, 0x213f), 740 regmap_reg_range(0x2400, 0x2401), 741 regmap_reg_range(0x2403, 0x2403), 742 regmap_reg_range(0x2410, 0x2417), 743 regmap_reg_range(0x2420, 0x2423), 744 regmap_reg_range(0x2500, 0x2507), 745 regmap_reg_range(0x2600, 0x2613), 746 regmap_reg_range(0x2800, 0x280f), 747 regmap_reg_range(0x2820, 0x2827), 748 regmap_reg_range(0x2830, 0x2837), 749 regmap_reg_range(0x2840, 0x284b), 750 regmap_reg_range(0x2900, 0x2907), 751 regmap_reg_range(0x2914, 0x291b), 752 regmap_reg_range(0x2920, 0x2920), 753 regmap_reg_range(0x2923, 0x2927), 754 regmap_reg_range(0x2a00, 0x2a03), 755 regmap_reg_range(0x2a04, 0x2a07), 756 regmap_reg_range(0x2b00, 0x2b01), 757 regmap_reg_range(0x2b04, 0x2b04), 758 regmap_reg_range(0x2c00, 0x2c05), 759 regmap_reg_range(0x2c08, 0x2c1b), 760 761 /* port 3 */ 762 regmap_reg_range(0x3000, 0x3001), 763 regmap_reg_range(0x3013, 0x3013), 764 regmap_reg_range(0x3017, 0x3017), 765 regmap_reg_range(0x301b, 0x301b), 766 regmap_reg_range(0x301f, 0x3020), 767 regmap_reg_range(0x3030, 0x3030), 768 regmap_reg_range(0x3100, 0x3115), 769 regmap_reg_range(0x311a, 0x311f), 770 regmap_reg_range(0x3120, 0x312b), 771 regmap_reg_range(0x3134, 0x313b), 772 regmap_reg_range(0x313c, 0x313f), 773 regmap_reg_range(0x3400, 0x3401), 774 regmap_reg_range(0x3403, 0x3403), 775 regmap_reg_range(0x3410, 0x3417), 776 regmap_reg_range(0x3420, 0x3423), 777 regmap_reg_range(0x3500, 0x3507), 778 regmap_reg_range(0x3600, 0x3613), 779 regmap_reg_range(0x3800, 0x380f), 780 regmap_reg_range(0x3820, 0x3827), 781 regmap_reg_range(0x3830, 0x3837), 782 regmap_reg_range(0x3840, 0x384b), 783 regmap_reg_range(0x3900, 0x3907), 784 regmap_reg_range(0x3914, 0x391b), 785 regmap_reg_range(0x3920, 0x3920), 786 regmap_reg_range(0x3923, 0x3927), 787 regmap_reg_range(0x3a00, 0x3a03), 788 regmap_reg_range(0x3a04, 0x3a07), 789 regmap_reg_range(0x3b00, 0x3b01), 790 regmap_reg_range(0x3b04, 0x3b04), 791 regmap_reg_range(0x3c00, 0x3c05), 792 regmap_reg_range(0x3c08, 0x3c1b), 793 794 /* port 4 */ 795 regmap_reg_range(0x4000, 0x4001), 796 regmap_reg_range(0x4013, 0x4013), 797 regmap_reg_range(0x4017, 0x4017), 798 regmap_reg_range(0x401b, 0x401b), 799 regmap_reg_range(0x401f, 0x4020), 800 regmap_reg_range(0x4030, 0x4030), 801 regmap_reg_range(0x4100, 0x4115), 802 regmap_reg_range(0x411a, 0x411f), 803 regmap_reg_range(0x4120, 0x412b), 804 regmap_reg_range(0x4134, 0x413b), 805 regmap_reg_range(0x413c, 0x413f), 806 regmap_reg_range(0x4400, 0x4401), 807 regmap_reg_range(0x4403, 0x4403), 808 regmap_reg_range(0x4410, 0x4417), 809 regmap_reg_range(0x4420, 0x4423), 810 regmap_reg_range(0x4500, 0x4507), 811 regmap_reg_range(0x4600, 0x4613), 812 regmap_reg_range(0x4800, 0x480f), 813 regmap_reg_range(0x4820, 0x4827), 814 regmap_reg_range(0x4830, 0x4837), 815 regmap_reg_range(0x4840, 0x484b), 816 regmap_reg_range(0x4900, 0x4907), 817 regmap_reg_range(0x4914, 0x491b), 818 regmap_reg_range(0x4920, 0x4920), 819 regmap_reg_range(0x4923, 0x4927), 820 regmap_reg_range(0x4a00, 0x4a03), 821 regmap_reg_range(0x4a04, 0x4a07), 822 regmap_reg_range(0x4b00, 0x4b01), 823 regmap_reg_range(0x4b04, 0x4b04), 824 regmap_reg_range(0x4c00, 0x4c05), 825 regmap_reg_range(0x4c08, 0x4c1b), 826 827 /* port 5 */ 828 regmap_reg_range(0x5000, 0x5001), 829 regmap_reg_range(0x5013, 0x5013), 830 regmap_reg_range(0x5017, 0x5017), 831 regmap_reg_range(0x501b, 0x501b), 832 regmap_reg_range(0x501f, 0x5020), 833 regmap_reg_range(0x5030, 0x5030), 834 regmap_reg_range(0x5100, 0x5115), 835 regmap_reg_range(0x511a, 0x511f), 836 regmap_reg_range(0x5120, 0x512b), 837 regmap_reg_range(0x5134, 0x513b), 838 regmap_reg_range(0x513c, 0x513f), 839 regmap_reg_range(0x5400, 0x5401), 840 regmap_reg_range(0x5403, 0x5403), 841 regmap_reg_range(0x5410, 0x5417), 842 regmap_reg_range(0x5420, 0x5423), 843 regmap_reg_range(0x5500, 0x5507), 844 regmap_reg_range(0x5600, 0x5613), 845 regmap_reg_range(0x5800, 0x580f), 846 regmap_reg_range(0x5820, 0x5827), 847 regmap_reg_range(0x5830, 0x5837), 848 regmap_reg_range(0x5840, 0x584b), 849 regmap_reg_range(0x5900, 0x5907), 850 regmap_reg_range(0x5914, 0x591b), 851 regmap_reg_range(0x5920, 0x5920), 852 regmap_reg_range(0x5923, 0x5927), 853 regmap_reg_range(0x5a00, 0x5a03), 854 regmap_reg_range(0x5a04, 0x5a07), 855 regmap_reg_range(0x5b00, 0x5b01), 856 regmap_reg_range(0x5b04, 0x5b04), 857 regmap_reg_range(0x5c00, 0x5c05), 858 regmap_reg_range(0x5c08, 0x5c1b), 859 860 /* port 6 */ 861 regmap_reg_range(0x6000, 0x6001), 862 regmap_reg_range(0x6013, 0x6013), 863 regmap_reg_range(0x6017, 0x6017), 864 regmap_reg_range(0x601b, 0x601b), 865 regmap_reg_range(0x601f, 0x6020), 866 regmap_reg_range(0x6030, 0x6030), 867 regmap_reg_range(0x6300, 0x6301), 868 regmap_reg_range(0x6400, 0x6401), 869 regmap_reg_range(0x6403, 0x6403), 870 regmap_reg_range(0x6410, 0x6417), 871 regmap_reg_range(0x6420, 0x6423), 872 regmap_reg_range(0x6500, 0x6507), 873 regmap_reg_range(0x6600, 0x6613), 874 regmap_reg_range(0x6800, 0x680f), 875 regmap_reg_range(0x6820, 0x6827), 876 regmap_reg_range(0x6830, 0x6837), 877 regmap_reg_range(0x6840, 0x684b), 878 regmap_reg_range(0x6900, 0x6907), 879 regmap_reg_range(0x6914, 0x691b), 880 regmap_reg_range(0x6920, 0x6920), 881 regmap_reg_range(0x6923, 0x6927), 882 regmap_reg_range(0x6a00, 0x6a03), 883 regmap_reg_range(0x6a04, 0x6a07), 884 regmap_reg_range(0x6b00, 0x6b01), 885 regmap_reg_range(0x6b04, 0x6b04), 886 regmap_reg_range(0x6c00, 0x6c05), 887 regmap_reg_range(0x6c08, 0x6c1b), 888 889 /* port 7 */ 890 regmap_reg_range(0x7000, 0x7001), 891 regmap_reg_range(0x7013, 0x7013), 892 regmap_reg_range(0x7017, 0x7017), 893 regmap_reg_range(0x701b, 0x701b), 894 regmap_reg_range(0x701f, 0x7020), 895 regmap_reg_range(0x7030, 0x7030), 896 regmap_reg_range(0x7200, 0x7203), 897 regmap_reg_range(0x7206, 0x7207), 898 regmap_reg_range(0x7300, 0x7301), 899 regmap_reg_range(0x7400, 0x7401), 900 regmap_reg_range(0x7403, 0x7403), 901 regmap_reg_range(0x7410, 0x7417), 902 regmap_reg_range(0x7420, 0x7423), 903 regmap_reg_range(0x7500, 0x7507), 904 regmap_reg_range(0x7600, 0x7613), 905 regmap_reg_range(0x7800, 0x780f), 906 regmap_reg_range(0x7820, 0x7827), 907 regmap_reg_range(0x7830, 0x7837), 908 regmap_reg_range(0x7840, 0x784b), 909 regmap_reg_range(0x7900, 0x7907), 910 regmap_reg_range(0x7914, 0x791b), 911 regmap_reg_range(0x7920, 0x7920), 912 regmap_reg_range(0x7923, 0x7927), 913 regmap_reg_range(0x7a00, 0x7a03), 914 regmap_reg_range(0x7a04, 0x7a07), 915 regmap_reg_range(0x7b00, 0x7b01), 916 regmap_reg_range(0x7b04, 0x7b04), 917 regmap_reg_range(0x7c00, 0x7c05), 918 regmap_reg_range(0x7c08, 0x7c1b), 919 }; 920 921 static const struct regmap_access_table ksz9477_register_set = { 922 .yes_ranges = ksz9477_valid_regs, 923 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 924 }; 925 926 static const struct regmap_range ksz9896_valid_regs[] = { 927 regmap_reg_range(0x0000, 0x0003), 928 regmap_reg_range(0x0006, 0x0006), 929 regmap_reg_range(0x0010, 0x001f), 930 regmap_reg_range(0x0100, 0x0100), 931 regmap_reg_range(0x0103, 0x0107), 932 regmap_reg_range(0x010d, 0x010d), 933 regmap_reg_range(0x0110, 0x0113), 934 regmap_reg_range(0x0120, 0x0127), 935 regmap_reg_range(0x0201, 0x0201), 936 regmap_reg_range(0x0210, 0x0213), 937 regmap_reg_range(0x0300, 0x0300), 938 regmap_reg_range(0x0302, 0x030b), 939 regmap_reg_range(0x0310, 0x031b), 940 regmap_reg_range(0x0320, 0x032b), 941 regmap_reg_range(0x0330, 0x0336), 942 regmap_reg_range(0x0338, 0x033b), 943 regmap_reg_range(0x033e, 0x033e), 944 regmap_reg_range(0x0340, 0x035f), 945 regmap_reg_range(0x0370, 0x0370), 946 regmap_reg_range(0x0378, 0x0378), 947 regmap_reg_range(0x037c, 0x037d), 948 regmap_reg_range(0x0390, 0x0393), 949 regmap_reg_range(0x0400, 0x040e), 950 regmap_reg_range(0x0410, 0x042f), 951 952 /* port 1 */ 953 regmap_reg_range(0x1000, 0x1001), 954 regmap_reg_range(0x1013, 0x1013), 955 regmap_reg_range(0x1017, 0x1017), 956 regmap_reg_range(0x101b, 0x101b), 957 regmap_reg_range(0x101f, 0x1020), 958 regmap_reg_range(0x1030, 0x1030), 959 regmap_reg_range(0x1100, 0x1115), 960 regmap_reg_range(0x111a, 0x111f), 961 regmap_reg_range(0x1122, 0x1127), 962 regmap_reg_range(0x112a, 0x112b), 963 regmap_reg_range(0x1136, 0x1139), 964 regmap_reg_range(0x113e, 0x113f), 965 regmap_reg_range(0x1400, 0x1401), 966 regmap_reg_range(0x1403, 0x1403), 967 regmap_reg_range(0x1410, 0x1417), 968 regmap_reg_range(0x1420, 0x1423), 969 regmap_reg_range(0x1500, 0x1507), 970 regmap_reg_range(0x1600, 0x1612), 971 regmap_reg_range(0x1800, 0x180f), 972 regmap_reg_range(0x1820, 0x1827), 973 regmap_reg_range(0x1830, 0x1837), 974 regmap_reg_range(0x1840, 0x184b), 975 regmap_reg_range(0x1900, 0x1907), 976 regmap_reg_range(0x1914, 0x1915), 977 regmap_reg_range(0x1a00, 0x1a03), 978 regmap_reg_range(0x1a04, 0x1a07), 979 regmap_reg_range(0x1b00, 0x1b01), 980 regmap_reg_range(0x1b04, 0x1b04), 981 982 /* port 2 */ 983 regmap_reg_range(0x2000, 0x2001), 984 regmap_reg_range(0x2013, 0x2013), 985 regmap_reg_range(0x2017, 0x2017), 986 regmap_reg_range(0x201b, 0x201b), 987 regmap_reg_range(0x201f, 0x2020), 988 regmap_reg_range(0x2030, 0x2030), 989 regmap_reg_range(0x2100, 0x2115), 990 regmap_reg_range(0x211a, 0x211f), 991 regmap_reg_range(0x2122, 0x2127), 992 regmap_reg_range(0x212a, 0x212b), 993 regmap_reg_range(0x2136, 0x2139), 994 regmap_reg_range(0x213e, 0x213f), 995 regmap_reg_range(0x2400, 0x2401), 996 regmap_reg_range(0x2403, 0x2403), 997 regmap_reg_range(0x2410, 0x2417), 998 regmap_reg_range(0x2420, 0x2423), 999 regmap_reg_range(0x2500, 0x2507), 1000 regmap_reg_range(0x2600, 0x2612), 1001 regmap_reg_range(0x2800, 0x280f), 1002 regmap_reg_range(0x2820, 0x2827), 1003 regmap_reg_range(0x2830, 0x2837), 1004 regmap_reg_range(0x2840, 0x284b), 1005 regmap_reg_range(0x2900, 0x2907), 1006 regmap_reg_range(0x2914, 0x2915), 1007 regmap_reg_range(0x2a00, 0x2a03), 1008 regmap_reg_range(0x2a04, 0x2a07), 1009 regmap_reg_range(0x2b00, 0x2b01), 1010 regmap_reg_range(0x2b04, 0x2b04), 1011 1012 /* port 3 */ 1013 regmap_reg_range(0x3000, 0x3001), 1014 regmap_reg_range(0x3013, 0x3013), 1015 regmap_reg_range(0x3017, 0x3017), 1016 regmap_reg_range(0x301b, 0x301b), 1017 regmap_reg_range(0x301f, 0x3020), 1018 regmap_reg_range(0x3030, 0x3030), 1019 regmap_reg_range(0x3100, 0x3115), 1020 regmap_reg_range(0x311a, 0x311f), 1021 regmap_reg_range(0x3122, 0x3127), 1022 regmap_reg_range(0x312a, 0x312b), 1023 regmap_reg_range(0x3136, 0x3139), 1024 regmap_reg_range(0x313e, 0x313f), 1025 regmap_reg_range(0x3400, 0x3401), 1026 regmap_reg_range(0x3403, 0x3403), 1027 regmap_reg_range(0x3410, 0x3417), 1028 regmap_reg_range(0x3420, 0x3423), 1029 regmap_reg_range(0x3500, 0x3507), 1030 regmap_reg_range(0x3600, 0x3612), 1031 regmap_reg_range(0x3800, 0x380f), 1032 regmap_reg_range(0x3820, 0x3827), 1033 regmap_reg_range(0x3830, 0x3837), 1034 regmap_reg_range(0x3840, 0x384b), 1035 regmap_reg_range(0x3900, 0x3907), 1036 regmap_reg_range(0x3914, 0x3915), 1037 regmap_reg_range(0x3a00, 0x3a03), 1038 regmap_reg_range(0x3a04, 0x3a07), 1039 regmap_reg_range(0x3b00, 0x3b01), 1040 regmap_reg_range(0x3b04, 0x3b04), 1041 1042 /* port 4 */ 1043 regmap_reg_range(0x4000, 0x4001), 1044 regmap_reg_range(0x4013, 0x4013), 1045 regmap_reg_range(0x4017, 0x4017), 1046 regmap_reg_range(0x401b, 0x401b), 1047 regmap_reg_range(0x401f, 0x4020), 1048 regmap_reg_range(0x4030, 0x4030), 1049 regmap_reg_range(0x4100, 0x4115), 1050 regmap_reg_range(0x411a, 0x411f), 1051 regmap_reg_range(0x4122, 0x4127), 1052 regmap_reg_range(0x412a, 0x412b), 1053 regmap_reg_range(0x4136, 0x4139), 1054 regmap_reg_range(0x413e, 0x413f), 1055 regmap_reg_range(0x4400, 0x4401), 1056 regmap_reg_range(0x4403, 0x4403), 1057 regmap_reg_range(0x4410, 0x4417), 1058 regmap_reg_range(0x4420, 0x4423), 1059 regmap_reg_range(0x4500, 0x4507), 1060 regmap_reg_range(0x4600, 0x4612), 1061 regmap_reg_range(0x4800, 0x480f), 1062 regmap_reg_range(0x4820, 0x4827), 1063 regmap_reg_range(0x4830, 0x4837), 1064 regmap_reg_range(0x4840, 0x484b), 1065 regmap_reg_range(0x4900, 0x4907), 1066 regmap_reg_range(0x4914, 0x4915), 1067 regmap_reg_range(0x4a00, 0x4a03), 1068 regmap_reg_range(0x4a04, 0x4a07), 1069 regmap_reg_range(0x4b00, 0x4b01), 1070 regmap_reg_range(0x4b04, 0x4b04), 1071 1072 /* port 5 */ 1073 regmap_reg_range(0x5000, 0x5001), 1074 regmap_reg_range(0x5013, 0x5013), 1075 regmap_reg_range(0x5017, 0x5017), 1076 regmap_reg_range(0x501b, 0x501b), 1077 regmap_reg_range(0x501f, 0x5020), 1078 regmap_reg_range(0x5030, 0x5030), 1079 regmap_reg_range(0x5100, 0x5115), 1080 regmap_reg_range(0x511a, 0x511f), 1081 regmap_reg_range(0x5122, 0x5127), 1082 regmap_reg_range(0x512a, 0x512b), 1083 regmap_reg_range(0x5136, 0x5139), 1084 regmap_reg_range(0x513e, 0x513f), 1085 regmap_reg_range(0x5400, 0x5401), 1086 regmap_reg_range(0x5403, 0x5403), 1087 regmap_reg_range(0x5410, 0x5417), 1088 regmap_reg_range(0x5420, 0x5423), 1089 regmap_reg_range(0x5500, 0x5507), 1090 regmap_reg_range(0x5600, 0x5612), 1091 regmap_reg_range(0x5800, 0x580f), 1092 regmap_reg_range(0x5820, 0x5827), 1093 regmap_reg_range(0x5830, 0x5837), 1094 regmap_reg_range(0x5840, 0x584b), 1095 regmap_reg_range(0x5900, 0x5907), 1096 regmap_reg_range(0x5914, 0x5915), 1097 regmap_reg_range(0x5a00, 0x5a03), 1098 regmap_reg_range(0x5a04, 0x5a07), 1099 regmap_reg_range(0x5b00, 0x5b01), 1100 regmap_reg_range(0x5b04, 0x5b04), 1101 1102 /* port 6 */ 1103 regmap_reg_range(0x6000, 0x6001), 1104 regmap_reg_range(0x6013, 0x6013), 1105 regmap_reg_range(0x6017, 0x6017), 1106 regmap_reg_range(0x601b, 0x601b), 1107 regmap_reg_range(0x601f, 0x6020), 1108 regmap_reg_range(0x6030, 0x6030), 1109 regmap_reg_range(0x6100, 0x6115), 1110 regmap_reg_range(0x611a, 0x611f), 1111 regmap_reg_range(0x6122, 0x6127), 1112 regmap_reg_range(0x612a, 0x612b), 1113 regmap_reg_range(0x6136, 0x6139), 1114 regmap_reg_range(0x613e, 0x613f), 1115 regmap_reg_range(0x6300, 0x6301), 1116 regmap_reg_range(0x6400, 0x6401), 1117 regmap_reg_range(0x6403, 0x6403), 1118 regmap_reg_range(0x6410, 0x6417), 1119 regmap_reg_range(0x6420, 0x6423), 1120 regmap_reg_range(0x6500, 0x6507), 1121 regmap_reg_range(0x6600, 0x6612), 1122 regmap_reg_range(0x6800, 0x680f), 1123 regmap_reg_range(0x6820, 0x6827), 1124 regmap_reg_range(0x6830, 0x6837), 1125 regmap_reg_range(0x6840, 0x684b), 1126 regmap_reg_range(0x6900, 0x6907), 1127 regmap_reg_range(0x6914, 0x6915), 1128 regmap_reg_range(0x6a00, 0x6a03), 1129 regmap_reg_range(0x6a04, 0x6a07), 1130 regmap_reg_range(0x6b00, 0x6b01), 1131 regmap_reg_range(0x6b04, 0x6b04), 1132 }; 1133 1134 static const struct regmap_access_table ksz9896_register_set = { 1135 .yes_ranges = ksz9896_valid_regs, 1136 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1137 }; 1138 1139 static const struct regmap_range ksz8873_valid_regs[] = { 1140 regmap_reg_range(0x00, 0x01), 1141 /* global control register */ 1142 regmap_reg_range(0x02, 0x0f), 1143 1144 /* port registers */ 1145 regmap_reg_range(0x10, 0x1d), 1146 regmap_reg_range(0x1e, 0x1f), 1147 regmap_reg_range(0x20, 0x2d), 1148 regmap_reg_range(0x2e, 0x2f), 1149 regmap_reg_range(0x30, 0x39), 1150 regmap_reg_range(0x3f, 0x3f), 1151 1152 /* advanced control registers */ 1153 regmap_reg_range(0x60, 0x6f), 1154 regmap_reg_range(0x70, 0x75), 1155 regmap_reg_range(0x76, 0x78), 1156 regmap_reg_range(0x79, 0x7a), 1157 regmap_reg_range(0x7b, 0x83), 1158 regmap_reg_range(0x8e, 0x99), 1159 regmap_reg_range(0x9a, 0xa5), 1160 regmap_reg_range(0xa6, 0xa6), 1161 regmap_reg_range(0xa7, 0xaa), 1162 regmap_reg_range(0xab, 0xae), 1163 regmap_reg_range(0xaf, 0xba), 1164 regmap_reg_range(0xbb, 0xbc), 1165 regmap_reg_range(0xbd, 0xbd), 1166 regmap_reg_range(0xc0, 0xc0), 1167 regmap_reg_range(0xc2, 0xc2), 1168 regmap_reg_range(0xc3, 0xc3), 1169 regmap_reg_range(0xc4, 0xc4), 1170 regmap_reg_range(0xc6, 0xc6), 1171 }; 1172 1173 static const struct regmap_access_table ksz8873_register_set = { 1174 .yes_ranges = ksz8873_valid_regs, 1175 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), 1176 }; 1177 1178 const struct ksz_chip_data ksz_switch_chips[] = { 1179 [KSZ8563] = { 1180 .chip_id = KSZ8563_CHIP_ID, 1181 .dev_name = "KSZ8563", 1182 .num_vlans = 4096, 1183 .num_alus = 4096, 1184 .num_statics = 16, 1185 .cpu_ports = 0x07, /* can be configured as cpu port */ 1186 .port_cnt = 3, /* total port count */ 1187 .port_nirqs = 3, 1188 .num_tx_queues = 4, 1189 .tc_cbs_supported = true, 1190 .tc_ets_supported = true, 1191 .ops = &ksz9477_dev_ops, 1192 .mib_names = ksz9477_mib_names, 1193 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1194 .reg_mib_cnt = MIB_COUNTER_NUM, 1195 .regs = ksz9477_regs, 1196 .masks = ksz9477_masks, 1197 .shifts = ksz9477_shifts, 1198 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1199 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1200 .supports_mii = {false, false, true}, 1201 .supports_rmii = {false, false, true}, 1202 .supports_rgmii = {false, false, true}, 1203 .internal_phy = {true, true, false}, 1204 .gbit_capable = {false, false, true}, 1205 .wr_table = &ksz8563_register_set, 1206 .rd_table = &ksz8563_register_set, 1207 }, 1208 1209 [KSZ8795] = { 1210 .chip_id = KSZ8795_CHIP_ID, 1211 .dev_name = "KSZ8795", 1212 .num_vlans = 4096, 1213 .num_alus = 0, 1214 .num_statics = 8, 1215 .cpu_ports = 0x10, /* can be configured as cpu port */ 1216 .port_cnt = 5, /* total cpu and user ports */ 1217 .num_tx_queues = 4, 1218 .ops = &ksz8_dev_ops, 1219 .ksz87xx_eee_link_erratum = true, 1220 .mib_names = ksz9477_mib_names, 1221 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1222 .reg_mib_cnt = MIB_COUNTER_NUM, 1223 .regs = ksz8795_regs, 1224 .masks = ksz8795_masks, 1225 .shifts = ksz8795_shifts, 1226 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1227 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1228 .supports_mii = {false, false, false, false, true}, 1229 .supports_rmii = {false, false, false, false, true}, 1230 .supports_rgmii = {false, false, false, false, true}, 1231 .internal_phy = {true, true, true, true, false}, 1232 }, 1233 1234 [KSZ8794] = { 1235 /* WARNING 1236 * ======= 1237 * KSZ8794 is similar to KSZ8795, except the port map 1238 * contains a gap between external and CPU ports, the 1239 * port map is NOT continuous. The per-port register 1240 * map is shifted accordingly too, i.e. registers at 1241 * offset 0x40 are NOT used on KSZ8794 and they ARE 1242 * used on KSZ8795 for external port 3. 1243 * external cpu 1244 * KSZ8794 0,1,2 4 1245 * KSZ8795 0,1,2,3 4 1246 * KSZ8765 0,1,2,3 4 1247 * port_cnt is configured as 5, even though it is 4 1248 */ 1249 .chip_id = KSZ8794_CHIP_ID, 1250 .dev_name = "KSZ8794", 1251 .num_vlans = 4096, 1252 .num_alus = 0, 1253 .num_statics = 8, 1254 .cpu_ports = 0x10, /* can be configured as cpu port */ 1255 .port_cnt = 5, /* total cpu and user ports */ 1256 .num_tx_queues = 4, 1257 .ops = &ksz8_dev_ops, 1258 .ksz87xx_eee_link_erratum = true, 1259 .mib_names = ksz9477_mib_names, 1260 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1261 .reg_mib_cnt = MIB_COUNTER_NUM, 1262 .regs = ksz8795_regs, 1263 .masks = ksz8795_masks, 1264 .shifts = ksz8795_shifts, 1265 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1266 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1267 .supports_mii = {false, false, false, false, true}, 1268 .supports_rmii = {false, false, false, false, true}, 1269 .supports_rgmii = {false, false, false, false, true}, 1270 .internal_phy = {true, true, true, false, false}, 1271 }, 1272 1273 [KSZ8765] = { 1274 .chip_id = KSZ8765_CHIP_ID, 1275 .dev_name = "KSZ8765", 1276 .num_vlans = 4096, 1277 .num_alus = 0, 1278 .num_statics = 8, 1279 .cpu_ports = 0x10, /* can be configured as cpu port */ 1280 .port_cnt = 5, /* total cpu and user ports */ 1281 .num_tx_queues = 4, 1282 .ops = &ksz8_dev_ops, 1283 .ksz87xx_eee_link_erratum = true, 1284 .mib_names = ksz9477_mib_names, 1285 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1286 .reg_mib_cnt = MIB_COUNTER_NUM, 1287 .regs = ksz8795_regs, 1288 .masks = ksz8795_masks, 1289 .shifts = ksz8795_shifts, 1290 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1291 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1292 .supports_mii = {false, false, false, false, true}, 1293 .supports_rmii = {false, false, false, false, true}, 1294 .supports_rgmii = {false, false, false, false, true}, 1295 .internal_phy = {true, true, true, true, false}, 1296 }, 1297 1298 [KSZ8830] = { 1299 .chip_id = KSZ8830_CHIP_ID, 1300 .dev_name = "KSZ8863/KSZ8873", 1301 .num_vlans = 16, 1302 .num_alus = 0, 1303 .num_statics = 8, 1304 .cpu_ports = 0x4, /* can be configured as cpu port */ 1305 .port_cnt = 3, 1306 .num_tx_queues = 4, 1307 .ops = &ksz8_dev_ops, 1308 .mib_names = ksz88xx_mib_names, 1309 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1310 .reg_mib_cnt = MIB_COUNTER_NUM, 1311 .regs = ksz8863_regs, 1312 .masks = ksz8863_masks, 1313 .shifts = ksz8863_shifts, 1314 .supports_mii = {false, false, true}, 1315 .supports_rmii = {false, false, true}, 1316 .internal_phy = {true, true, false}, 1317 .wr_table = &ksz8873_register_set, 1318 .rd_table = &ksz8873_register_set, 1319 }, 1320 1321 [KSZ9477] = { 1322 .chip_id = KSZ9477_CHIP_ID, 1323 .dev_name = "KSZ9477", 1324 .num_vlans = 4096, 1325 .num_alus = 4096, 1326 .num_statics = 16, 1327 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1328 .port_cnt = 7, /* total physical port count */ 1329 .port_nirqs = 4, 1330 .num_tx_queues = 4, 1331 .tc_cbs_supported = true, 1332 .tc_ets_supported = true, 1333 .ops = &ksz9477_dev_ops, 1334 .mib_names = ksz9477_mib_names, 1335 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1336 .reg_mib_cnt = MIB_COUNTER_NUM, 1337 .regs = ksz9477_regs, 1338 .masks = ksz9477_masks, 1339 .shifts = ksz9477_shifts, 1340 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1341 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1342 .supports_mii = {false, false, false, false, 1343 false, true, false}, 1344 .supports_rmii = {false, false, false, false, 1345 false, true, false}, 1346 .supports_rgmii = {false, false, false, false, 1347 false, true, false}, 1348 .internal_phy = {true, true, true, true, 1349 true, false, false}, 1350 .gbit_capable = {true, true, true, true, true, true, true}, 1351 .wr_table = &ksz9477_register_set, 1352 .rd_table = &ksz9477_register_set, 1353 }, 1354 1355 [KSZ9896] = { 1356 .chip_id = KSZ9896_CHIP_ID, 1357 .dev_name = "KSZ9896", 1358 .num_vlans = 4096, 1359 .num_alus = 4096, 1360 .num_statics = 16, 1361 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1362 .port_cnt = 6, /* total physical port count */ 1363 .port_nirqs = 2, 1364 .num_tx_queues = 4, 1365 .ops = &ksz9477_dev_ops, 1366 .mib_names = ksz9477_mib_names, 1367 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1368 .reg_mib_cnt = MIB_COUNTER_NUM, 1369 .regs = ksz9477_regs, 1370 .masks = ksz9477_masks, 1371 .shifts = ksz9477_shifts, 1372 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1373 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1374 .supports_mii = {false, false, false, false, 1375 false, true}, 1376 .supports_rmii = {false, false, false, false, 1377 false, true}, 1378 .supports_rgmii = {false, false, false, false, 1379 false, true}, 1380 .internal_phy = {true, true, true, true, 1381 true, false}, 1382 .gbit_capable = {true, true, true, true, true, true}, 1383 .wr_table = &ksz9896_register_set, 1384 .rd_table = &ksz9896_register_set, 1385 }, 1386 1387 [KSZ9897] = { 1388 .chip_id = KSZ9897_CHIP_ID, 1389 .dev_name = "KSZ9897", 1390 .num_vlans = 4096, 1391 .num_alus = 4096, 1392 .num_statics = 16, 1393 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1394 .port_cnt = 7, /* total physical port count */ 1395 .port_nirqs = 2, 1396 .num_tx_queues = 4, 1397 .ops = &ksz9477_dev_ops, 1398 .mib_names = ksz9477_mib_names, 1399 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1400 .reg_mib_cnt = MIB_COUNTER_NUM, 1401 .regs = ksz9477_regs, 1402 .masks = ksz9477_masks, 1403 .shifts = ksz9477_shifts, 1404 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1405 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1406 .supports_mii = {false, false, false, false, 1407 false, true, true}, 1408 .supports_rmii = {false, false, false, false, 1409 false, true, true}, 1410 .supports_rgmii = {false, false, false, false, 1411 false, true, true}, 1412 .internal_phy = {true, true, true, true, 1413 true, false, false}, 1414 .gbit_capable = {true, true, true, true, true, true, true}, 1415 }, 1416 1417 [KSZ9893] = { 1418 .chip_id = KSZ9893_CHIP_ID, 1419 .dev_name = "KSZ9893", 1420 .num_vlans = 4096, 1421 .num_alus = 4096, 1422 .num_statics = 16, 1423 .cpu_ports = 0x07, /* can be configured as cpu port */ 1424 .port_cnt = 3, /* total port count */ 1425 .port_nirqs = 2, 1426 .num_tx_queues = 4, 1427 .ops = &ksz9477_dev_ops, 1428 .mib_names = ksz9477_mib_names, 1429 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1430 .reg_mib_cnt = MIB_COUNTER_NUM, 1431 .regs = ksz9477_regs, 1432 .masks = ksz9477_masks, 1433 .shifts = ksz9477_shifts, 1434 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1435 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1436 .supports_mii = {false, false, true}, 1437 .supports_rmii = {false, false, true}, 1438 .supports_rgmii = {false, false, true}, 1439 .internal_phy = {true, true, false}, 1440 .gbit_capable = {true, true, true}, 1441 }, 1442 1443 [KSZ9563] = { 1444 .chip_id = KSZ9563_CHIP_ID, 1445 .dev_name = "KSZ9563", 1446 .num_vlans = 4096, 1447 .num_alus = 4096, 1448 .num_statics = 16, 1449 .cpu_ports = 0x07, /* can be configured as cpu port */ 1450 .port_cnt = 3, /* total port count */ 1451 .port_nirqs = 3, 1452 .num_tx_queues = 4, 1453 .tc_cbs_supported = true, 1454 .tc_ets_supported = true, 1455 .ops = &ksz9477_dev_ops, 1456 .mib_names = ksz9477_mib_names, 1457 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1458 .reg_mib_cnt = MIB_COUNTER_NUM, 1459 .regs = ksz9477_regs, 1460 .masks = ksz9477_masks, 1461 .shifts = ksz9477_shifts, 1462 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1463 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1464 .supports_mii = {false, false, true}, 1465 .supports_rmii = {false, false, true}, 1466 .supports_rgmii = {false, false, true}, 1467 .internal_phy = {true, true, false}, 1468 .gbit_capable = {true, true, true}, 1469 }, 1470 1471 [KSZ9567] = { 1472 .chip_id = KSZ9567_CHIP_ID, 1473 .dev_name = "KSZ9567", 1474 .num_vlans = 4096, 1475 .num_alus = 4096, 1476 .num_statics = 16, 1477 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1478 .port_cnt = 7, /* total physical port count */ 1479 .port_nirqs = 3, 1480 .num_tx_queues = 4, 1481 .tc_cbs_supported = true, 1482 .tc_ets_supported = true, 1483 .ops = &ksz9477_dev_ops, 1484 .mib_names = ksz9477_mib_names, 1485 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1486 .reg_mib_cnt = MIB_COUNTER_NUM, 1487 .regs = ksz9477_regs, 1488 .masks = ksz9477_masks, 1489 .shifts = ksz9477_shifts, 1490 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1491 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1492 .supports_mii = {false, false, false, false, 1493 false, true, true}, 1494 .supports_rmii = {false, false, false, false, 1495 false, true, true}, 1496 .supports_rgmii = {false, false, false, false, 1497 false, true, true}, 1498 .internal_phy = {true, true, true, true, 1499 true, false, false}, 1500 .gbit_capable = {true, true, true, true, true, true, true}, 1501 }, 1502 1503 [LAN9370] = { 1504 .chip_id = LAN9370_CHIP_ID, 1505 .dev_name = "LAN9370", 1506 .num_vlans = 4096, 1507 .num_alus = 1024, 1508 .num_statics = 256, 1509 .cpu_ports = 0x10, /* can be configured as cpu port */ 1510 .port_cnt = 5, /* total physical port count */ 1511 .port_nirqs = 6, 1512 .num_tx_queues = 8, 1513 .tc_cbs_supported = true, 1514 .tc_ets_supported = true, 1515 .ops = &lan937x_dev_ops, 1516 .mib_names = ksz9477_mib_names, 1517 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1518 .reg_mib_cnt = MIB_COUNTER_NUM, 1519 .regs = ksz9477_regs, 1520 .masks = lan937x_masks, 1521 .shifts = lan937x_shifts, 1522 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1523 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1524 .supports_mii = {false, false, false, false, true}, 1525 .supports_rmii = {false, false, false, false, true}, 1526 .supports_rgmii = {false, false, false, false, true}, 1527 .internal_phy = {true, true, true, true, false}, 1528 }, 1529 1530 [LAN9371] = { 1531 .chip_id = LAN9371_CHIP_ID, 1532 .dev_name = "LAN9371", 1533 .num_vlans = 4096, 1534 .num_alus = 1024, 1535 .num_statics = 256, 1536 .cpu_ports = 0x30, /* can be configured as cpu port */ 1537 .port_cnt = 6, /* total physical port count */ 1538 .port_nirqs = 6, 1539 .num_tx_queues = 8, 1540 .tc_cbs_supported = true, 1541 .tc_ets_supported = true, 1542 .ops = &lan937x_dev_ops, 1543 .mib_names = ksz9477_mib_names, 1544 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1545 .reg_mib_cnt = MIB_COUNTER_NUM, 1546 .regs = ksz9477_regs, 1547 .masks = lan937x_masks, 1548 .shifts = lan937x_shifts, 1549 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1550 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1551 .supports_mii = {false, false, false, false, true, true}, 1552 .supports_rmii = {false, false, false, false, true, true}, 1553 .supports_rgmii = {false, false, false, false, true, true}, 1554 .internal_phy = {true, true, true, true, false, false}, 1555 }, 1556 1557 [LAN9372] = { 1558 .chip_id = LAN9372_CHIP_ID, 1559 .dev_name = "LAN9372", 1560 .num_vlans = 4096, 1561 .num_alus = 1024, 1562 .num_statics = 256, 1563 .cpu_ports = 0x30, /* can be configured as cpu port */ 1564 .port_cnt = 8, /* total physical port count */ 1565 .port_nirqs = 6, 1566 .num_tx_queues = 8, 1567 .tc_cbs_supported = true, 1568 .tc_ets_supported = true, 1569 .ops = &lan937x_dev_ops, 1570 .mib_names = ksz9477_mib_names, 1571 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1572 .reg_mib_cnt = MIB_COUNTER_NUM, 1573 .regs = ksz9477_regs, 1574 .masks = lan937x_masks, 1575 .shifts = lan937x_shifts, 1576 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1577 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1578 .supports_mii = {false, false, false, false, 1579 true, true, false, false}, 1580 .supports_rmii = {false, false, false, false, 1581 true, true, false, false}, 1582 .supports_rgmii = {false, false, false, false, 1583 true, true, false, false}, 1584 .internal_phy = {true, true, true, true, 1585 false, false, true, true}, 1586 }, 1587 1588 [LAN9373] = { 1589 .chip_id = LAN9373_CHIP_ID, 1590 .dev_name = "LAN9373", 1591 .num_vlans = 4096, 1592 .num_alus = 1024, 1593 .num_statics = 256, 1594 .cpu_ports = 0x38, /* can be configured as cpu port */ 1595 .port_cnt = 5, /* total physical port count */ 1596 .port_nirqs = 6, 1597 .num_tx_queues = 8, 1598 .tc_cbs_supported = true, 1599 .tc_ets_supported = true, 1600 .ops = &lan937x_dev_ops, 1601 .mib_names = ksz9477_mib_names, 1602 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1603 .reg_mib_cnt = MIB_COUNTER_NUM, 1604 .regs = ksz9477_regs, 1605 .masks = lan937x_masks, 1606 .shifts = lan937x_shifts, 1607 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1608 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1609 .supports_mii = {false, false, false, false, 1610 true, true, false, false}, 1611 .supports_rmii = {false, false, false, false, 1612 true, true, false, false}, 1613 .supports_rgmii = {false, false, false, false, 1614 true, true, false, false}, 1615 .internal_phy = {true, true, true, false, 1616 false, false, true, true}, 1617 }, 1618 1619 [LAN9374] = { 1620 .chip_id = LAN9374_CHIP_ID, 1621 .dev_name = "LAN9374", 1622 .num_vlans = 4096, 1623 .num_alus = 1024, 1624 .num_statics = 256, 1625 .cpu_ports = 0x30, /* can be configured as cpu port */ 1626 .port_cnt = 8, /* total physical port count */ 1627 .port_nirqs = 6, 1628 .num_tx_queues = 8, 1629 .tc_cbs_supported = true, 1630 .tc_ets_supported = true, 1631 .ops = &lan937x_dev_ops, 1632 .mib_names = ksz9477_mib_names, 1633 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1634 .reg_mib_cnt = MIB_COUNTER_NUM, 1635 .regs = ksz9477_regs, 1636 .masks = lan937x_masks, 1637 .shifts = lan937x_shifts, 1638 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1639 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1640 .supports_mii = {false, false, false, false, 1641 true, true, false, false}, 1642 .supports_rmii = {false, false, false, false, 1643 true, true, false, false}, 1644 .supports_rgmii = {false, false, false, false, 1645 true, true, false, false}, 1646 .internal_phy = {true, true, true, true, 1647 false, false, true, true}, 1648 }, 1649 }; 1650 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1651 1652 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1653 { 1654 int i; 1655 1656 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1657 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1658 1659 if (chip->chip_id == prod_num) 1660 return chip; 1661 } 1662 1663 return NULL; 1664 } 1665 1666 static int ksz_check_device_id(struct ksz_device *dev) 1667 { 1668 const struct ksz_chip_data *dt_chip_data; 1669 1670 dt_chip_data = of_device_get_match_data(dev->dev); 1671 1672 /* Check for Device Tree and Chip ID */ 1673 if (dt_chip_data->chip_id != dev->chip_id) { 1674 dev_err(dev->dev, 1675 "Device tree specifies chip %s but found %s, please fix it!\n", 1676 dt_chip_data->dev_name, dev->info->dev_name); 1677 return -ENODEV; 1678 } 1679 1680 return 0; 1681 } 1682 1683 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1684 struct phylink_config *config) 1685 { 1686 struct ksz_device *dev = ds->priv; 1687 1688 if (dev->info->supports_mii[port]) 1689 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1690 1691 if (dev->info->supports_rmii[port]) 1692 __set_bit(PHY_INTERFACE_MODE_RMII, 1693 config->supported_interfaces); 1694 1695 if (dev->info->supports_rgmii[port]) 1696 phy_interface_set_rgmii(config->supported_interfaces); 1697 1698 if (dev->info->internal_phy[port]) { 1699 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1700 config->supported_interfaces); 1701 /* Compatibility for phylib's default interface type when the 1702 * phy-mode property is absent 1703 */ 1704 __set_bit(PHY_INTERFACE_MODE_GMII, 1705 config->supported_interfaces); 1706 } 1707 1708 if (dev->dev_ops->get_caps) 1709 dev->dev_ops->get_caps(dev, port, config); 1710 } 1711 1712 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 1713 { 1714 struct ethtool_pause_stats *pstats; 1715 struct rtnl_link_stats64 *stats; 1716 struct ksz_stats_raw *raw; 1717 struct ksz_port_mib *mib; 1718 1719 mib = &dev->ports[port].mib; 1720 stats = &mib->stats64; 1721 pstats = &mib->pause_stats; 1722 raw = (struct ksz_stats_raw *)mib->counters; 1723 1724 spin_lock(&mib->stats64_lock); 1725 1726 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1727 raw->rx_pause; 1728 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1729 raw->tx_pause; 1730 1731 /* HW counters are counting bytes + FCS which is not acceptable 1732 * for rtnl_link_stats64 interface 1733 */ 1734 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 1735 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 1736 1737 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1738 raw->rx_oversize; 1739 1740 stats->rx_crc_errors = raw->rx_crc_err; 1741 stats->rx_frame_errors = raw->rx_align_err; 1742 stats->rx_dropped = raw->rx_discards; 1743 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1744 stats->rx_frame_errors + stats->rx_dropped; 1745 1746 stats->tx_window_errors = raw->tx_late_col; 1747 stats->tx_fifo_errors = raw->tx_discards; 1748 stats->tx_aborted_errors = raw->tx_exc_col; 1749 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1750 stats->tx_aborted_errors; 1751 1752 stats->multicast = raw->rx_mcast; 1753 stats->collisions = raw->tx_total_col; 1754 1755 pstats->tx_pause_frames = raw->tx_pause; 1756 pstats->rx_pause_frames = raw->rx_pause; 1757 1758 spin_unlock(&mib->stats64_lock); 1759 } 1760 1761 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 1762 { 1763 struct ethtool_pause_stats *pstats; 1764 struct rtnl_link_stats64 *stats; 1765 struct ksz88xx_stats_raw *raw; 1766 struct ksz_port_mib *mib; 1767 1768 mib = &dev->ports[port].mib; 1769 stats = &mib->stats64; 1770 pstats = &mib->pause_stats; 1771 raw = (struct ksz88xx_stats_raw *)mib->counters; 1772 1773 spin_lock(&mib->stats64_lock); 1774 1775 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1776 raw->rx_pause; 1777 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1778 raw->tx_pause; 1779 1780 /* HW counters are counting bytes + FCS which is not acceptable 1781 * for rtnl_link_stats64 interface 1782 */ 1783 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 1784 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 1785 1786 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1787 raw->rx_oversize; 1788 1789 stats->rx_crc_errors = raw->rx_crc_err; 1790 stats->rx_frame_errors = raw->rx_align_err; 1791 stats->rx_dropped = raw->rx_discards; 1792 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1793 stats->rx_frame_errors + stats->rx_dropped; 1794 1795 stats->tx_window_errors = raw->tx_late_col; 1796 stats->tx_fifo_errors = raw->tx_discards; 1797 stats->tx_aborted_errors = raw->tx_exc_col; 1798 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1799 stats->tx_aborted_errors; 1800 1801 stats->multicast = raw->rx_mcast; 1802 stats->collisions = raw->tx_total_col; 1803 1804 pstats->tx_pause_frames = raw->tx_pause; 1805 pstats->rx_pause_frames = raw->rx_pause; 1806 1807 spin_unlock(&mib->stats64_lock); 1808 } 1809 1810 static void ksz_get_stats64(struct dsa_switch *ds, int port, 1811 struct rtnl_link_stats64 *s) 1812 { 1813 struct ksz_device *dev = ds->priv; 1814 struct ksz_port_mib *mib; 1815 1816 mib = &dev->ports[port].mib; 1817 1818 spin_lock(&mib->stats64_lock); 1819 memcpy(s, &mib->stats64, sizeof(*s)); 1820 spin_unlock(&mib->stats64_lock); 1821 } 1822 1823 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 1824 struct ethtool_pause_stats *pause_stats) 1825 { 1826 struct ksz_device *dev = ds->priv; 1827 struct ksz_port_mib *mib; 1828 1829 mib = &dev->ports[port].mib; 1830 1831 spin_lock(&mib->stats64_lock); 1832 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 1833 spin_unlock(&mib->stats64_lock); 1834 } 1835 1836 static void ksz_get_strings(struct dsa_switch *ds, int port, 1837 u32 stringset, uint8_t *buf) 1838 { 1839 struct ksz_device *dev = ds->priv; 1840 int i; 1841 1842 if (stringset != ETH_SS_STATS) 1843 return; 1844 1845 for (i = 0; i < dev->info->mib_cnt; i++) { 1846 memcpy(buf + i * ETH_GSTRING_LEN, 1847 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 1848 } 1849 } 1850 1851 static void ksz_update_port_member(struct ksz_device *dev, int port) 1852 { 1853 struct ksz_port *p = &dev->ports[port]; 1854 struct dsa_switch *ds = dev->ds; 1855 u8 port_member = 0, cpu_port; 1856 const struct dsa_port *dp; 1857 int i, j; 1858 1859 if (!dsa_is_user_port(ds, port)) 1860 return; 1861 1862 dp = dsa_to_port(ds, port); 1863 cpu_port = BIT(dsa_upstream_port(ds, port)); 1864 1865 for (i = 0; i < ds->num_ports; i++) { 1866 const struct dsa_port *other_dp = dsa_to_port(ds, i); 1867 struct ksz_port *other_p = &dev->ports[i]; 1868 u8 val = 0; 1869 1870 if (!dsa_is_user_port(ds, i)) 1871 continue; 1872 if (port == i) 1873 continue; 1874 if (!dsa_port_bridge_same(dp, other_dp)) 1875 continue; 1876 if (other_p->stp_state != BR_STATE_FORWARDING) 1877 continue; 1878 1879 if (p->stp_state == BR_STATE_FORWARDING) { 1880 val |= BIT(port); 1881 port_member |= BIT(i); 1882 } 1883 1884 /* Retain port [i]'s relationship to other ports than [port] */ 1885 for (j = 0; j < ds->num_ports; j++) { 1886 const struct dsa_port *third_dp; 1887 struct ksz_port *third_p; 1888 1889 if (j == i) 1890 continue; 1891 if (j == port) 1892 continue; 1893 if (!dsa_is_user_port(ds, j)) 1894 continue; 1895 third_p = &dev->ports[j]; 1896 if (third_p->stp_state != BR_STATE_FORWARDING) 1897 continue; 1898 third_dp = dsa_to_port(ds, j); 1899 if (dsa_port_bridge_same(other_dp, third_dp)) 1900 val |= BIT(j); 1901 } 1902 1903 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 1904 } 1905 1906 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 1907 } 1908 1909 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 1910 { 1911 struct ksz_device *dev = bus->priv; 1912 u16 val; 1913 int ret; 1914 1915 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 1916 if (ret < 0) 1917 return ret; 1918 1919 return val; 1920 } 1921 1922 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 1923 u16 val) 1924 { 1925 struct ksz_device *dev = bus->priv; 1926 1927 return dev->dev_ops->w_phy(dev, addr, regnum, val); 1928 } 1929 1930 static int ksz_irq_phy_setup(struct ksz_device *dev) 1931 { 1932 struct dsa_switch *ds = dev->ds; 1933 int phy; 1934 int irq; 1935 int ret; 1936 1937 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) { 1938 if (BIT(phy) & ds->phys_mii_mask) { 1939 irq = irq_find_mapping(dev->ports[phy].pirq.domain, 1940 PORT_SRC_PHY_INT); 1941 if (irq < 0) { 1942 ret = irq; 1943 goto out; 1944 } 1945 ds->slave_mii_bus->irq[phy] = irq; 1946 } 1947 } 1948 return 0; 1949 out: 1950 while (phy--) 1951 if (BIT(phy) & ds->phys_mii_mask) 1952 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]); 1953 1954 return ret; 1955 } 1956 1957 static void ksz_irq_phy_free(struct ksz_device *dev) 1958 { 1959 struct dsa_switch *ds = dev->ds; 1960 int phy; 1961 1962 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) 1963 if (BIT(phy) & ds->phys_mii_mask) 1964 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]); 1965 } 1966 1967 static int ksz_mdio_register(struct ksz_device *dev) 1968 { 1969 struct dsa_switch *ds = dev->ds; 1970 struct device_node *mdio_np; 1971 struct mii_bus *bus; 1972 int ret; 1973 1974 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 1975 if (!mdio_np) 1976 return 0; 1977 1978 bus = devm_mdiobus_alloc(ds->dev); 1979 if (!bus) { 1980 of_node_put(mdio_np); 1981 return -ENOMEM; 1982 } 1983 1984 bus->priv = dev; 1985 bus->read = ksz_sw_mdio_read; 1986 bus->write = ksz_sw_mdio_write; 1987 bus->name = "ksz slave smi"; 1988 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 1989 bus->parent = ds->dev; 1990 bus->phy_mask = ~ds->phys_mii_mask; 1991 1992 ds->slave_mii_bus = bus; 1993 1994 if (dev->irq > 0) { 1995 ret = ksz_irq_phy_setup(dev); 1996 if (ret) { 1997 of_node_put(mdio_np); 1998 return ret; 1999 } 2000 } 2001 2002 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 2003 if (ret) { 2004 dev_err(ds->dev, "unable to register MDIO bus %s\n", 2005 bus->id); 2006 if (dev->irq > 0) 2007 ksz_irq_phy_free(dev); 2008 } 2009 2010 of_node_put(mdio_np); 2011 2012 return ret; 2013 } 2014 2015 static void ksz_irq_mask(struct irq_data *d) 2016 { 2017 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2018 2019 kirq->masked |= BIT(d->hwirq); 2020 } 2021 2022 static void ksz_irq_unmask(struct irq_data *d) 2023 { 2024 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2025 2026 kirq->masked &= ~BIT(d->hwirq); 2027 } 2028 2029 static void ksz_irq_bus_lock(struct irq_data *d) 2030 { 2031 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2032 2033 mutex_lock(&kirq->dev->lock_irq); 2034 } 2035 2036 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 2037 { 2038 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2039 struct ksz_device *dev = kirq->dev; 2040 int ret; 2041 2042 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked); 2043 if (ret) 2044 dev_err(dev->dev, "failed to change IRQ mask\n"); 2045 2046 mutex_unlock(&dev->lock_irq); 2047 } 2048 2049 static const struct irq_chip ksz_irq_chip = { 2050 .name = "ksz-irq", 2051 .irq_mask = ksz_irq_mask, 2052 .irq_unmask = ksz_irq_unmask, 2053 .irq_bus_lock = ksz_irq_bus_lock, 2054 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 2055 }; 2056 2057 static int ksz_irq_domain_map(struct irq_domain *d, 2058 unsigned int irq, irq_hw_number_t hwirq) 2059 { 2060 irq_set_chip_data(irq, d->host_data); 2061 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 2062 irq_set_noprobe(irq); 2063 2064 return 0; 2065 } 2066 2067 static const struct irq_domain_ops ksz_irq_domain_ops = { 2068 .map = ksz_irq_domain_map, 2069 .xlate = irq_domain_xlate_twocell, 2070 }; 2071 2072 static void ksz_irq_free(struct ksz_irq *kirq) 2073 { 2074 int irq, virq; 2075 2076 free_irq(kirq->irq_num, kirq); 2077 2078 for (irq = 0; irq < kirq->nirqs; irq++) { 2079 virq = irq_find_mapping(kirq->domain, irq); 2080 irq_dispose_mapping(virq); 2081 } 2082 2083 irq_domain_remove(kirq->domain); 2084 } 2085 2086 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 2087 { 2088 struct ksz_irq *kirq = dev_id; 2089 unsigned int nhandled = 0; 2090 struct ksz_device *dev; 2091 unsigned int sub_irq; 2092 u8 data; 2093 int ret; 2094 u8 n; 2095 2096 dev = kirq->dev; 2097 2098 /* Read interrupt status register */ 2099 ret = ksz_read8(dev, kirq->reg_status, &data); 2100 if (ret) 2101 goto out; 2102 2103 for (n = 0; n < kirq->nirqs; ++n) { 2104 if (data & BIT(n)) { 2105 sub_irq = irq_find_mapping(kirq->domain, n); 2106 handle_nested_irq(sub_irq); 2107 ++nhandled; 2108 } 2109 } 2110 out: 2111 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2112 } 2113 2114 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 2115 { 2116 int ret, n; 2117 2118 kirq->dev = dev; 2119 kirq->masked = ~0; 2120 2121 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0, 2122 &ksz_irq_domain_ops, kirq); 2123 if (!kirq->domain) 2124 return -ENOMEM; 2125 2126 for (n = 0; n < kirq->nirqs; n++) 2127 irq_create_mapping(kirq->domain, n); 2128 2129 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2130 IRQF_ONESHOT, kirq->name, kirq); 2131 if (ret) 2132 goto out; 2133 2134 return 0; 2135 2136 out: 2137 ksz_irq_free(kirq); 2138 2139 return ret; 2140 } 2141 2142 static int ksz_girq_setup(struct ksz_device *dev) 2143 { 2144 struct ksz_irq *girq = &dev->girq; 2145 2146 girq->nirqs = dev->info->port_cnt; 2147 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2148 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2149 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2150 2151 girq->irq_num = dev->irq; 2152 2153 return ksz_irq_common_setup(dev, girq); 2154 } 2155 2156 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2157 { 2158 struct ksz_irq *pirq = &dev->ports[p].pirq; 2159 2160 pirq->nirqs = dev->info->port_nirqs; 2161 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2162 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2163 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2164 2165 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2166 if (pirq->irq_num < 0) 2167 return pirq->irq_num; 2168 2169 return ksz_irq_common_setup(dev, pirq); 2170 } 2171 2172 static int ksz_setup(struct dsa_switch *ds) 2173 { 2174 struct ksz_device *dev = ds->priv; 2175 struct dsa_port *dp; 2176 struct ksz_port *p; 2177 const u16 *regs; 2178 int ret; 2179 2180 regs = dev->info->regs; 2181 2182 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2183 dev->info->num_vlans, GFP_KERNEL); 2184 if (!dev->vlan_cache) 2185 return -ENOMEM; 2186 2187 ret = dev->dev_ops->reset(dev); 2188 if (ret) { 2189 dev_err(ds->dev, "failed to reset switch\n"); 2190 return ret; 2191 } 2192 2193 /* set broadcast storm protection 10% rate */ 2194 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2195 BROADCAST_STORM_RATE, 2196 (BROADCAST_STORM_VALUE * 2197 BROADCAST_STORM_PROT_RATE) / 100); 2198 2199 dev->dev_ops->config_cpu_port(ds); 2200 2201 dev->dev_ops->enable_stp_addr(dev); 2202 2203 ds->num_tx_queues = dev->info->num_tx_queues; 2204 2205 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 2206 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2207 2208 ksz_init_mib_timer(dev); 2209 2210 ds->configure_vlan_while_not_filtering = false; 2211 2212 if (dev->dev_ops->setup) { 2213 ret = dev->dev_ops->setup(ds); 2214 if (ret) 2215 return ret; 2216 } 2217 2218 /* Start with learning disabled on standalone user ports, and enabled 2219 * on the CPU port. In lack of other finer mechanisms, learning on the 2220 * CPU port will avoid flooding bridge local addresses on the network 2221 * in some cases. 2222 */ 2223 p = &dev->ports[dev->cpu_port]; 2224 p->learning = true; 2225 2226 if (dev->irq > 0) { 2227 ret = ksz_girq_setup(dev); 2228 if (ret) 2229 return ret; 2230 2231 dsa_switch_for_each_user_port(dp, dev->ds) { 2232 ret = ksz_pirq_setup(dev, dp->index); 2233 if (ret) 2234 goto out_girq; 2235 2236 ret = ksz_ptp_irq_setup(ds, dp->index); 2237 if (ret) 2238 goto out_pirq; 2239 } 2240 } 2241 2242 ret = ksz_ptp_clock_register(ds); 2243 if (ret) { 2244 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret); 2245 goto out_ptpirq; 2246 } 2247 2248 ret = ksz_mdio_register(dev); 2249 if (ret < 0) { 2250 dev_err(dev->dev, "failed to register the mdio"); 2251 goto out_ptp_clock_unregister; 2252 } 2253 2254 /* start switch */ 2255 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 2256 SW_START, SW_START); 2257 2258 return 0; 2259 2260 out_ptp_clock_unregister: 2261 ksz_ptp_clock_unregister(ds); 2262 out_ptpirq: 2263 if (dev->irq > 0) 2264 dsa_switch_for_each_user_port(dp, dev->ds) 2265 ksz_ptp_irq_free(ds, dp->index); 2266 out_pirq: 2267 if (dev->irq > 0) 2268 dsa_switch_for_each_user_port(dp, dev->ds) 2269 ksz_irq_free(&dev->ports[dp->index].pirq); 2270 out_girq: 2271 if (dev->irq > 0) 2272 ksz_irq_free(&dev->girq); 2273 2274 return ret; 2275 } 2276 2277 static void ksz_teardown(struct dsa_switch *ds) 2278 { 2279 struct ksz_device *dev = ds->priv; 2280 struct dsa_port *dp; 2281 2282 ksz_ptp_clock_unregister(ds); 2283 2284 if (dev->irq > 0) { 2285 dsa_switch_for_each_user_port(dp, dev->ds) { 2286 ksz_ptp_irq_free(ds, dp->index); 2287 2288 ksz_irq_free(&dev->ports[dp->index].pirq); 2289 } 2290 2291 ksz_irq_free(&dev->girq); 2292 } 2293 2294 if (dev->dev_ops->teardown) 2295 dev->dev_ops->teardown(ds); 2296 } 2297 2298 static void port_r_cnt(struct ksz_device *dev, int port) 2299 { 2300 struct ksz_port_mib *mib = &dev->ports[port].mib; 2301 u64 *dropped; 2302 2303 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2304 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2305 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2306 &mib->counters[mib->cnt_ptr]); 2307 ++mib->cnt_ptr; 2308 } 2309 2310 /* last one in storage */ 2311 dropped = &mib->counters[dev->info->mib_cnt]; 2312 2313 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2314 while (mib->cnt_ptr < dev->info->mib_cnt) { 2315 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2316 dropped, &mib->counters[mib->cnt_ptr]); 2317 ++mib->cnt_ptr; 2318 } 2319 mib->cnt_ptr = 0; 2320 } 2321 2322 static void ksz_mib_read_work(struct work_struct *work) 2323 { 2324 struct ksz_device *dev = container_of(work, struct ksz_device, 2325 mib_read.work); 2326 struct ksz_port_mib *mib; 2327 struct ksz_port *p; 2328 int i; 2329 2330 for (i = 0; i < dev->info->port_cnt; i++) { 2331 if (dsa_is_unused_port(dev->ds, i)) 2332 continue; 2333 2334 p = &dev->ports[i]; 2335 mib = &p->mib; 2336 mutex_lock(&mib->cnt_mutex); 2337 2338 /* Only read MIB counters when the port is told to do. 2339 * If not, read only dropped counters when link is not up. 2340 */ 2341 if (!p->read) { 2342 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 2343 2344 if (!netif_carrier_ok(dp->slave)) 2345 mib->cnt_ptr = dev->info->reg_mib_cnt; 2346 } 2347 port_r_cnt(dev, i); 2348 p->read = false; 2349 2350 if (dev->dev_ops->r_mib_stat64) 2351 dev->dev_ops->r_mib_stat64(dev, i); 2352 2353 mutex_unlock(&mib->cnt_mutex); 2354 } 2355 2356 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 2357 } 2358 2359 void ksz_init_mib_timer(struct ksz_device *dev) 2360 { 2361 int i; 2362 2363 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 2364 2365 for (i = 0; i < dev->info->port_cnt; i++) { 2366 struct ksz_port_mib *mib = &dev->ports[i].mib; 2367 2368 dev->dev_ops->port_init_cnt(dev, i); 2369 2370 mib->cnt_ptr = 0; 2371 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 2372 } 2373 } 2374 2375 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 2376 { 2377 struct ksz_device *dev = ds->priv; 2378 u16 val = 0xffff; 2379 int ret; 2380 2381 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 2382 if (ret) 2383 return ret; 2384 2385 return val; 2386 } 2387 2388 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 2389 { 2390 struct ksz_device *dev = ds->priv; 2391 int ret; 2392 2393 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 2394 if (ret) 2395 return ret; 2396 2397 return 0; 2398 } 2399 2400 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 2401 { 2402 struct ksz_device *dev = ds->priv; 2403 2404 switch (dev->chip_id) { 2405 case KSZ8830_CHIP_ID: 2406 /* Silicon Errata Sheet (DS80000830A): 2407 * Port 1 does not work with LinkMD Cable-Testing. 2408 * Port 1 does not respond to received PAUSE control frames. 2409 */ 2410 if (!port) 2411 return MICREL_KSZ8_P1_ERRATA; 2412 break; 2413 case KSZ9477_CHIP_ID: 2414 /* KSZ9477 Errata DS80000754C 2415 * 2416 * Module 4: Energy Efficient Ethernet (EEE) feature select must 2417 * be manually disabled 2418 * The EEE feature is enabled by default, but it is not fully 2419 * operational. It must be manually disabled through register 2420 * controls. If not disabled, the PHY ports can auto-negotiate 2421 * to enable EEE, and this feature can cause link drops when 2422 * linked to another device supporting EEE. 2423 */ 2424 return MICREL_NO_EEE; 2425 } 2426 2427 return 0; 2428 } 2429 2430 static void ksz_mac_link_down(struct dsa_switch *ds, int port, 2431 unsigned int mode, phy_interface_t interface) 2432 { 2433 struct ksz_device *dev = ds->priv; 2434 struct ksz_port *p = &dev->ports[port]; 2435 2436 /* Read all MIB counters when the link is going down. */ 2437 p->read = true; 2438 /* timer started */ 2439 if (dev->mib_read_interval) 2440 schedule_delayed_work(&dev->mib_read, 0); 2441 } 2442 2443 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 2444 { 2445 struct ksz_device *dev = ds->priv; 2446 2447 if (sset != ETH_SS_STATS) 2448 return 0; 2449 2450 return dev->info->mib_cnt; 2451 } 2452 2453 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 2454 uint64_t *buf) 2455 { 2456 const struct dsa_port *dp = dsa_to_port(ds, port); 2457 struct ksz_device *dev = ds->priv; 2458 struct ksz_port_mib *mib; 2459 2460 mib = &dev->ports[port].mib; 2461 mutex_lock(&mib->cnt_mutex); 2462 2463 /* Only read dropped counters if no link. */ 2464 if (!netif_carrier_ok(dp->slave)) 2465 mib->cnt_ptr = dev->info->reg_mib_cnt; 2466 port_r_cnt(dev, port); 2467 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 2468 mutex_unlock(&mib->cnt_mutex); 2469 } 2470 2471 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 2472 struct dsa_bridge bridge, 2473 bool *tx_fwd_offload, 2474 struct netlink_ext_ack *extack) 2475 { 2476 /* port_stp_state_set() will be called after to put the port in 2477 * appropriate state so there is no need to do anything. 2478 */ 2479 2480 return 0; 2481 } 2482 2483 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 2484 struct dsa_bridge bridge) 2485 { 2486 /* port_stp_state_set() will be called after to put the port in 2487 * forwarding state so there is no need to do anything. 2488 */ 2489 } 2490 2491 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 2492 { 2493 struct ksz_device *dev = ds->priv; 2494 2495 dev->dev_ops->flush_dyn_mac_table(dev, port); 2496 } 2497 2498 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 2499 { 2500 struct ksz_device *dev = ds->priv; 2501 2502 if (!dev->dev_ops->set_ageing_time) 2503 return -EOPNOTSUPP; 2504 2505 return dev->dev_ops->set_ageing_time(dev, msecs); 2506 } 2507 2508 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 2509 const unsigned char *addr, u16 vid, 2510 struct dsa_db db) 2511 { 2512 struct ksz_device *dev = ds->priv; 2513 2514 if (!dev->dev_ops->fdb_add) 2515 return -EOPNOTSUPP; 2516 2517 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 2518 } 2519 2520 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 2521 const unsigned char *addr, 2522 u16 vid, struct dsa_db db) 2523 { 2524 struct ksz_device *dev = ds->priv; 2525 2526 if (!dev->dev_ops->fdb_del) 2527 return -EOPNOTSUPP; 2528 2529 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 2530 } 2531 2532 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 2533 dsa_fdb_dump_cb_t *cb, void *data) 2534 { 2535 struct ksz_device *dev = ds->priv; 2536 2537 if (!dev->dev_ops->fdb_dump) 2538 return -EOPNOTSUPP; 2539 2540 return dev->dev_ops->fdb_dump(dev, port, cb, data); 2541 } 2542 2543 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 2544 const struct switchdev_obj_port_mdb *mdb, 2545 struct dsa_db db) 2546 { 2547 struct ksz_device *dev = ds->priv; 2548 2549 if (!dev->dev_ops->mdb_add) 2550 return -EOPNOTSUPP; 2551 2552 return dev->dev_ops->mdb_add(dev, port, mdb, db); 2553 } 2554 2555 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 2556 const struct switchdev_obj_port_mdb *mdb, 2557 struct dsa_db db) 2558 { 2559 struct ksz_device *dev = ds->priv; 2560 2561 if (!dev->dev_ops->mdb_del) 2562 return -EOPNOTSUPP; 2563 2564 return dev->dev_ops->mdb_del(dev, port, mdb, db); 2565 } 2566 2567 static int ksz_port_setup(struct dsa_switch *ds, int port) 2568 { 2569 struct ksz_device *dev = ds->priv; 2570 2571 if (!dsa_is_user_port(ds, port)) 2572 return 0; 2573 2574 /* setup slave port */ 2575 dev->dev_ops->port_setup(dev, port, false); 2576 2577 /* port_stp_state_set() will be called after to enable the port so 2578 * there is no need to do anything. 2579 */ 2580 2581 return 0; 2582 } 2583 2584 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 2585 { 2586 struct ksz_device *dev = ds->priv; 2587 struct ksz_port *p; 2588 const u16 *regs; 2589 u8 data; 2590 2591 regs = dev->info->regs; 2592 2593 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 2594 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2595 2596 p = &dev->ports[port]; 2597 2598 switch (state) { 2599 case BR_STATE_DISABLED: 2600 data |= PORT_LEARN_DISABLE; 2601 break; 2602 case BR_STATE_LISTENING: 2603 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2604 break; 2605 case BR_STATE_LEARNING: 2606 data |= PORT_RX_ENABLE; 2607 if (!p->learning) 2608 data |= PORT_LEARN_DISABLE; 2609 break; 2610 case BR_STATE_FORWARDING: 2611 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 2612 if (!p->learning) 2613 data |= PORT_LEARN_DISABLE; 2614 break; 2615 case BR_STATE_BLOCKING: 2616 data |= PORT_LEARN_DISABLE; 2617 break; 2618 default: 2619 dev_err(ds->dev, "invalid STP state: %d\n", state); 2620 return; 2621 } 2622 2623 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 2624 2625 p->stp_state = state; 2626 2627 ksz_update_port_member(dev, port); 2628 } 2629 2630 static void ksz_port_teardown(struct dsa_switch *ds, int port) 2631 { 2632 struct ksz_device *dev = ds->priv; 2633 2634 switch (dev->chip_id) { 2635 case KSZ8563_CHIP_ID: 2636 case KSZ9477_CHIP_ID: 2637 case KSZ9563_CHIP_ID: 2638 case KSZ9567_CHIP_ID: 2639 case KSZ9893_CHIP_ID: 2640 case KSZ9896_CHIP_ID: 2641 case KSZ9897_CHIP_ID: 2642 if (dsa_is_user_port(ds, port)) 2643 ksz9477_port_acl_free(dev, port); 2644 } 2645 } 2646 2647 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 2648 struct switchdev_brport_flags flags, 2649 struct netlink_ext_ack *extack) 2650 { 2651 if (flags.mask & ~BR_LEARNING) 2652 return -EINVAL; 2653 2654 return 0; 2655 } 2656 2657 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 2658 struct switchdev_brport_flags flags, 2659 struct netlink_ext_ack *extack) 2660 { 2661 struct ksz_device *dev = ds->priv; 2662 struct ksz_port *p = &dev->ports[port]; 2663 2664 if (flags.mask & BR_LEARNING) { 2665 p->learning = !!(flags.val & BR_LEARNING); 2666 2667 /* Make the change take effect immediately */ 2668 ksz_port_stp_state_set(ds, port, p->stp_state); 2669 } 2670 2671 return 0; 2672 } 2673 2674 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 2675 int port, 2676 enum dsa_tag_protocol mp) 2677 { 2678 struct ksz_device *dev = ds->priv; 2679 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 2680 2681 if (dev->chip_id == KSZ8795_CHIP_ID || 2682 dev->chip_id == KSZ8794_CHIP_ID || 2683 dev->chip_id == KSZ8765_CHIP_ID) 2684 proto = DSA_TAG_PROTO_KSZ8795; 2685 2686 if (dev->chip_id == KSZ8830_CHIP_ID || 2687 dev->chip_id == KSZ8563_CHIP_ID || 2688 dev->chip_id == KSZ9893_CHIP_ID || 2689 dev->chip_id == KSZ9563_CHIP_ID) 2690 proto = DSA_TAG_PROTO_KSZ9893; 2691 2692 if (dev->chip_id == KSZ9477_CHIP_ID || 2693 dev->chip_id == KSZ9896_CHIP_ID || 2694 dev->chip_id == KSZ9897_CHIP_ID || 2695 dev->chip_id == KSZ9567_CHIP_ID) 2696 proto = DSA_TAG_PROTO_KSZ9477; 2697 2698 if (is_lan937x(dev)) 2699 proto = DSA_TAG_PROTO_LAN937X_VALUE; 2700 2701 return proto; 2702 } 2703 2704 static int ksz_connect_tag_protocol(struct dsa_switch *ds, 2705 enum dsa_tag_protocol proto) 2706 { 2707 struct ksz_tagger_data *tagger_data; 2708 2709 tagger_data = ksz_tagger_data(ds); 2710 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 2711 2712 return 0; 2713 } 2714 2715 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 2716 bool flag, struct netlink_ext_ack *extack) 2717 { 2718 struct ksz_device *dev = ds->priv; 2719 2720 if (!dev->dev_ops->vlan_filtering) 2721 return -EOPNOTSUPP; 2722 2723 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 2724 } 2725 2726 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 2727 const struct switchdev_obj_port_vlan *vlan, 2728 struct netlink_ext_ack *extack) 2729 { 2730 struct ksz_device *dev = ds->priv; 2731 2732 if (!dev->dev_ops->vlan_add) 2733 return -EOPNOTSUPP; 2734 2735 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 2736 } 2737 2738 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 2739 const struct switchdev_obj_port_vlan *vlan) 2740 { 2741 struct ksz_device *dev = ds->priv; 2742 2743 if (!dev->dev_ops->vlan_del) 2744 return -EOPNOTSUPP; 2745 2746 return dev->dev_ops->vlan_del(dev, port, vlan); 2747 } 2748 2749 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 2750 struct dsa_mall_mirror_tc_entry *mirror, 2751 bool ingress, struct netlink_ext_ack *extack) 2752 { 2753 struct ksz_device *dev = ds->priv; 2754 2755 if (!dev->dev_ops->mirror_add) 2756 return -EOPNOTSUPP; 2757 2758 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 2759 } 2760 2761 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 2762 struct dsa_mall_mirror_tc_entry *mirror) 2763 { 2764 struct ksz_device *dev = ds->priv; 2765 2766 if (dev->dev_ops->mirror_del) 2767 dev->dev_ops->mirror_del(dev, port, mirror); 2768 } 2769 2770 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 2771 { 2772 struct ksz_device *dev = ds->priv; 2773 2774 if (!dev->dev_ops->change_mtu) 2775 return -EOPNOTSUPP; 2776 2777 return dev->dev_ops->change_mtu(dev, port, mtu); 2778 } 2779 2780 static int ksz_max_mtu(struct dsa_switch *ds, int port) 2781 { 2782 struct ksz_device *dev = ds->priv; 2783 2784 switch (dev->chip_id) { 2785 case KSZ8795_CHIP_ID: 2786 case KSZ8794_CHIP_ID: 2787 case KSZ8765_CHIP_ID: 2788 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2789 case KSZ8830_CHIP_ID: 2790 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2791 case KSZ8563_CHIP_ID: 2792 case KSZ9477_CHIP_ID: 2793 case KSZ9563_CHIP_ID: 2794 case KSZ9567_CHIP_ID: 2795 case KSZ9893_CHIP_ID: 2796 case KSZ9896_CHIP_ID: 2797 case KSZ9897_CHIP_ID: 2798 case LAN9370_CHIP_ID: 2799 case LAN9371_CHIP_ID: 2800 case LAN9372_CHIP_ID: 2801 case LAN9373_CHIP_ID: 2802 case LAN9374_CHIP_ID: 2803 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2804 } 2805 2806 return -EOPNOTSUPP; 2807 } 2808 2809 static int ksz_validate_eee(struct dsa_switch *ds, int port) 2810 { 2811 struct ksz_device *dev = ds->priv; 2812 2813 if (!dev->info->internal_phy[port]) 2814 return -EOPNOTSUPP; 2815 2816 switch (dev->chip_id) { 2817 case KSZ8563_CHIP_ID: 2818 case KSZ9477_CHIP_ID: 2819 case KSZ9563_CHIP_ID: 2820 case KSZ9567_CHIP_ID: 2821 case KSZ9893_CHIP_ID: 2822 case KSZ9896_CHIP_ID: 2823 case KSZ9897_CHIP_ID: 2824 return 0; 2825 } 2826 2827 return -EOPNOTSUPP; 2828 } 2829 2830 static int ksz_get_mac_eee(struct dsa_switch *ds, int port, 2831 struct ethtool_eee *e) 2832 { 2833 int ret; 2834 2835 ret = ksz_validate_eee(ds, port); 2836 if (ret) 2837 return ret; 2838 2839 /* There is no documented control of Tx LPI configuration. */ 2840 e->tx_lpi_enabled = true; 2841 2842 /* There is no documented control of Tx LPI timer. According to tests 2843 * Tx LPI timer seems to be set by default to minimal value. 2844 */ 2845 e->tx_lpi_timer = 0; 2846 2847 return 0; 2848 } 2849 2850 static int ksz_set_mac_eee(struct dsa_switch *ds, int port, 2851 struct ethtool_eee *e) 2852 { 2853 struct ksz_device *dev = ds->priv; 2854 int ret; 2855 2856 ret = ksz_validate_eee(ds, port); 2857 if (ret) 2858 return ret; 2859 2860 if (!e->tx_lpi_enabled) { 2861 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 2862 return -EINVAL; 2863 } 2864 2865 if (e->tx_lpi_timer) { 2866 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 2867 return -EINVAL; 2868 } 2869 2870 return 0; 2871 } 2872 2873 static void ksz_set_xmii(struct ksz_device *dev, int port, 2874 phy_interface_t interface) 2875 { 2876 const u8 *bitval = dev->info->xmii_ctrl1; 2877 struct ksz_port *p = &dev->ports[port]; 2878 const u16 *regs = dev->info->regs; 2879 u8 data8; 2880 2881 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2882 2883 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 2884 P_RGMII_ID_EG_ENABLE); 2885 2886 switch (interface) { 2887 case PHY_INTERFACE_MODE_MII: 2888 data8 |= bitval[P_MII_SEL]; 2889 break; 2890 case PHY_INTERFACE_MODE_RMII: 2891 data8 |= bitval[P_RMII_SEL]; 2892 break; 2893 case PHY_INTERFACE_MODE_GMII: 2894 data8 |= bitval[P_GMII_SEL]; 2895 break; 2896 case PHY_INTERFACE_MODE_RGMII: 2897 case PHY_INTERFACE_MODE_RGMII_ID: 2898 case PHY_INTERFACE_MODE_RGMII_TXID: 2899 case PHY_INTERFACE_MODE_RGMII_RXID: 2900 data8 |= bitval[P_RGMII_SEL]; 2901 /* On KSZ9893, disable RGMII in-band status support */ 2902 if (dev->chip_id == KSZ9893_CHIP_ID || 2903 dev->chip_id == KSZ8563_CHIP_ID || 2904 dev->chip_id == KSZ9563_CHIP_ID) 2905 data8 &= ~P_MII_MAC_MODE; 2906 break; 2907 default: 2908 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 2909 phy_modes(interface), port); 2910 return; 2911 } 2912 2913 if (p->rgmii_tx_val) 2914 data8 |= P_RGMII_ID_EG_ENABLE; 2915 2916 if (p->rgmii_rx_val) 2917 data8 |= P_RGMII_ID_IG_ENABLE; 2918 2919 /* Write the updated value */ 2920 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2921 } 2922 2923 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 2924 { 2925 const u8 *bitval = dev->info->xmii_ctrl1; 2926 const u16 *regs = dev->info->regs; 2927 phy_interface_t interface; 2928 u8 data8; 2929 u8 val; 2930 2931 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2932 2933 val = FIELD_GET(P_MII_SEL_M, data8); 2934 2935 if (val == bitval[P_MII_SEL]) { 2936 if (gbit) 2937 interface = PHY_INTERFACE_MODE_GMII; 2938 else 2939 interface = PHY_INTERFACE_MODE_MII; 2940 } else if (val == bitval[P_RMII_SEL]) { 2941 interface = PHY_INTERFACE_MODE_RGMII; 2942 } else { 2943 interface = PHY_INTERFACE_MODE_RGMII; 2944 if (data8 & P_RGMII_ID_EG_ENABLE) 2945 interface = PHY_INTERFACE_MODE_RGMII_TXID; 2946 if (data8 & P_RGMII_ID_IG_ENABLE) { 2947 interface = PHY_INTERFACE_MODE_RGMII_RXID; 2948 if (data8 & P_RGMII_ID_EG_ENABLE) 2949 interface = PHY_INTERFACE_MODE_RGMII_ID; 2950 } 2951 } 2952 2953 return interface; 2954 } 2955 2956 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, 2957 unsigned int mode, 2958 const struct phylink_link_state *state) 2959 { 2960 struct ksz_device *dev = ds->priv; 2961 2962 if (ksz_is_ksz88x3(dev)) 2963 return; 2964 2965 /* Internal PHYs */ 2966 if (dev->info->internal_phy[port]) 2967 return; 2968 2969 if (phylink_autoneg_inband(mode)) { 2970 dev_err(dev->dev, "In-band AN not supported!\n"); 2971 return; 2972 } 2973 2974 ksz_set_xmii(dev, port, state->interface); 2975 2976 if (dev->dev_ops->phylink_mac_config) 2977 dev->dev_ops->phylink_mac_config(dev, port, mode, state); 2978 2979 if (dev->dev_ops->setup_rgmii_delay) 2980 dev->dev_ops->setup_rgmii_delay(dev, port); 2981 } 2982 2983 bool ksz_get_gbit(struct ksz_device *dev, int port) 2984 { 2985 const u8 *bitval = dev->info->xmii_ctrl1; 2986 const u16 *regs = dev->info->regs; 2987 bool gbit = false; 2988 u8 data8; 2989 bool val; 2990 2991 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2992 2993 val = FIELD_GET(P_GMII_1GBIT_M, data8); 2994 2995 if (val == bitval[P_GMII_1GBIT]) 2996 gbit = true; 2997 2998 return gbit; 2999 } 3000 3001 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 3002 { 3003 const u8 *bitval = dev->info->xmii_ctrl1; 3004 const u16 *regs = dev->info->regs; 3005 u8 data8; 3006 3007 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3008 3009 data8 &= ~P_GMII_1GBIT_M; 3010 3011 if (gbit) 3012 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 3013 else 3014 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 3015 3016 /* Write the updated value */ 3017 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3018 } 3019 3020 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 3021 { 3022 const u8 *bitval = dev->info->xmii_ctrl0; 3023 const u16 *regs = dev->info->regs; 3024 u8 data8; 3025 3026 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 3027 3028 data8 &= ~P_MII_100MBIT_M; 3029 3030 if (speed == SPEED_100) 3031 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 3032 else 3033 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 3034 3035 /* Write the updated value */ 3036 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 3037 } 3038 3039 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 3040 { 3041 if (speed == SPEED_1000) 3042 ksz_set_gbit(dev, port, true); 3043 else 3044 ksz_set_gbit(dev, port, false); 3045 3046 if (speed == SPEED_100 || speed == SPEED_10) 3047 ksz_set_100_10mbit(dev, port, speed); 3048 } 3049 3050 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 3051 bool tx_pause, bool rx_pause) 3052 { 3053 const u8 *bitval = dev->info->xmii_ctrl0; 3054 const u32 *masks = dev->info->masks; 3055 const u16 *regs = dev->info->regs; 3056 u8 mask; 3057 u8 val; 3058 3059 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 3060 masks[P_MII_RX_FLOW_CTRL]; 3061 3062 if (duplex == DUPLEX_FULL) 3063 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 3064 else 3065 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 3066 3067 if (tx_pause) 3068 val |= masks[P_MII_TX_FLOW_CTRL]; 3069 3070 if (rx_pause) 3071 val |= masks[P_MII_RX_FLOW_CTRL]; 3072 3073 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 3074 } 3075 3076 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 3077 unsigned int mode, 3078 phy_interface_t interface, 3079 struct phy_device *phydev, int speed, 3080 int duplex, bool tx_pause, 3081 bool rx_pause) 3082 { 3083 struct ksz_port *p; 3084 3085 p = &dev->ports[port]; 3086 3087 /* Internal PHYs */ 3088 if (dev->info->internal_phy[port]) 3089 return; 3090 3091 p->phydev.speed = speed; 3092 3093 ksz_port_set_xmii_speed(dev, port, speed); 3094 3095 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 3096 } 3097 3098 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, 3099 unsigned int mode, 3100 phy_interface_t interface, 3101 struct phy_device *phydev, int speed, 3102 int duplex, bool tx_pause, bool rx_pause) 3103 { 3104 struct ksz_device *dev = ds->priv; 3105 3106 if (dev->dev_ops->phylink_mac_link_up) 3107 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface, 3108 phydev, speed, duplex, 3109 tx_pause, rx_pause); 3110 } 3111 3112 static int ksz_switch_detect(struct ksz_device *dev) 3113 { 3114 u8 id1, id2, id4; 3115 u16 id16; 3116 u32 id32; 3117 int ret; 3118 3119 /* read chip id */ 3120 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 3121 if (ret) 3122 return ret; 3123 3124 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 3125 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 3126 3127 switch (id1) { 3128 case KSZ87_FAMILY_ID: 3129 if (id2 == KSZ87_CHIP_ID_95) { 3130 u8 val; 3131 3132 dev->chip_id = KSZ8795_CHIP_ID; 3133 3134 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 3135 if (val & KSZ8_PORT_FIBER_MODE) 3136 dev->chip_id = KSZ8765_CHIP_ID; 3137 } else if (id2 == KSZ87_CHIP_ID_94) { 3138 dev->chip_id = KSZ8794_CHIP_ID; 3139 } else { 3140 return -ENODEV; 3141 } 3142 break; 3143 case KSZ88_FAMILY_ID: 3144 if (id2 == KSZ88_CHIP_ID_63) 3145 dev->chip_id = KSZ8830_CHIP_ID; 3146 else 3147 return -ENODEV; 3148 break; 3149 default: 3150 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 3151 if (ret) 3152 return ret; 3153 3154 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 3155 id32 &= ~0xFF; 3156 3157 switch (id32) { 3158 case KSZ9477_CHIP_ID: 3159 case KSZ9896_CHIP_ID: 3160 case KSZ9897_CHIP_ID: 3161 case KSZ9567_CHIP_ID: 3162 case LAN9370_CHIP_ID: 3163 case LAN9371_CHIP_ID: 3164 case LAN9372_CHIP_ID: 3165 case LAN9373_CHIP_ID: 3166 case LAN9374_CHIP_ID: 3167 dev->chip_id = id32; 3168 break; 3169 case KSZ9893_CHIP_ID: 3170 ret = ksz_read8(dev, REG_CHIP_ID4, 3171 &id4); 3172 if (ret) 3173 return ret; 3174 3175 if (id4 == SKU_ID_KSZ8563) 3176 dev->chip_id = KSZ8563_CHIP_ID; 3177 else if (id4 == SKU_ID_KSZ9563) 3178 dev->chip_id = KSZ9563_CHIP_ID; 3179 else 3180 dev->chip_id = KSZ9893_CHIP_ID; 3181 3182 break; 3183 default: 3184 dev_err(dev->dev, 3185 "unsupported switch detected %x)\n", id32); 3186 return -ENODEV; 3187 } 3188 } 3189 return 0; 3190 } 3191 3192 static int ksz_cls_flower_add(struct dsa_switch *ds, int port, 3193 struct flow_cls_offload *cls, bool ingress) 3194 { 3195 struct ksz_device *dev = ds->priv; 3196 3197 switch (dev->chip_id) { 3198 case KSZ8563_CHIP_ID: 3199 case KSZ9477_CHIP_ID: 3200 case KSZ9563_CHIP_ID: 3201 case KSZ9567_CHIP_ID: 3202 case KSZ9893_CHIP_ID: 3203 case KSZ9896_CHIP_ID: 3204 case KSZ9897_CHIP_ID: 3205 return ksz9477_cls_flower_add(ds, port, cls, ingress); 3206 } 3207 3208 return -EOPNOTSUPP; 3209 } 3210 3211 static int ksz_cls_flower_del(struct dsa_switch *ds, int port, 3212 struct flow_cls_offload *cls, bool ingress) 3213 { 3214 struct ksz_device *dev = ds->priv; 3215 3216 switch (dev->chip_id) { 3217 case KSZ8563_CHIP_ID: 3218 case KSZ9477_CHIP_ID: 3219 case KSZ9563_CHIP_ID: 3220 case KSZ9567_CHIP_ID: 3221 case KSZ9893_CHIP_ID: 3222 case KSZ9896_CHIP_ID: 3223 case KSZ9897_CHIP_ID: 3224 return ksz9477_cls_flower_del(ds, port, cls, ingress); 3225 } 3226 3227 return -EOPNOTSUPP; 3228 } 3229 3230 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 3231 * is converted to Hex-decimal using the successive multiplication method. On 3232 * every step, integer part is taken and decimal part is carry forwarded. 3233 */ 3234 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 3235 { 3236 u32 cinc = 0; 3237 u32 txrate; 3238 u32 rate; 3239 u8 temp; 3240 u8 i; 3241 3242 txrate = idle_slope - send_slope; 3243 3244 if (!txrate) 3245 return -EINVAL; 3246 3247 rate = idle_slope; 3248 3249 /* 24 bit register */ 3250 for (i = 0; i < 6; i++) { 3251 rate = rate * 16; 3252 3253 temp = rate / txrate; 3254 3255 rate %= txrate; 3256 3257 cinc = ((cinc << 4) | temp); 3258 } 3259 3260 *bw = cinc; 3261 3262 return 0; 3263 } 3264 3265 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 3266 u8 shaper) 3267 { 3268 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 3269 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 3270 FIELD_PREP(MTI_SHAPING_M, shaper)); 3271 } 3272 3273 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 3274 struct tc_cbs_qopt_offload *qopt) 3275 { 3276 struct ksz_device *dev = ds->priv; 3277 int ret; 3278 u32 bw; 3279 3280 if (!dev->info->tc_cbs_supported) 3281 return -EOPNOTSUPP; 3282 3283 if (qopt->queue > dev->info->num_tx_queues) 3284 return -EINVAL; 3285 3286 /* Queue Selection */ 3287 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 3288 if (ret) 3289 return ret; 3290 3291 if (!qopt->enable) 3292 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3293 MTI_SHAPING_OFF); 3294 3295 /* High Credit */ 3296 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 3297 qopt->hicredit); 3298 if (ret) 3299 return ret; 3300 3301 /* Low Credit */ 3302 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 3303 qopt->locredit); 3304 if (ret) 3305 return ret; 3306 3307 /* Credit Increment Register */ 3308 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 3309 if (ret) 3310 return ret; 3311 3312 if (dev->dev_ops->tc_cbs_set_cinc) { 3313 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 3314 if (ret) 3315 return ret; 3316 } 3317 3318 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3319 MTI_SHAPING_SRP); 3320 } 3321 3322 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 3323 { 3324 int queue, ret; 3325 3326 /* Configuration will not take effect until the last Port Queue X 3327 * Egress Limit Control Register is written. 3328 */ 3329 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3330 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 3331 KSZ9477_OUT_RATE_NO_LIMIT); 3332 if (ret) 3333 return ret; 3334 } 3335 3336 return 0; 3337 } 3338 3339 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 3340 int band) 3341 { 3342 /* Compared to queues, bands prioritize packets differently. In strict 3343 * priority mode, the lowest priority is assigned to Queue 0 while the 3344 * highest priority is given to Band 0. 3345 */ 3346 return p->bands - 1 - band; 3347 } 3348 3349 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 3350 { 3351 int ret; 3352 3353 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3354 if (ret) 3355 return ret; 3356 3357 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3358 MTI_SHAPING_OFF); 3359 } 3360 3361 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 3362 int weight) 3363 { 3364 int ret; 3365 3366 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3367 if (ret) 3368 return ret; 3369 3370 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3371 MTI_SHAPING_OFF); 3372 if (ret) 3373 return ret; 3374 3375 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 3376 } 3377 3378 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 3379 struct tc_ets_qopt_offload_replace_params *p) 3380 { 3381 int ret, band, tc_prio; 3382 u32 queue_map = 0; 3383 3384 /* In order to ensure proper prioritization, it is necessary to set the 3385 * rate limit for the related queue to zero. Otherwise strict priority 3386 * or WRR mode will not work. This is a hardware limitation. 3387 */ 3388 ret = ksz_disable_egress_rate_limit(dev, port); 3389 if (ret) 3390 return ret; 3391 3392 /* Configure queue scheduling mode for all bands. Currently only strict 3393 * prio mode is supported. 3394 */ 3395 for (band = 0; band < p->bands; band++) { 3396 int queue = ksz_ets_band_to_queue(p, band); 3397 3398 ret = ksz_queue_set_strict(dev, port, queue); 3399 if (ret) 3400 return ret; 3401 } 3402 3403 /* Configure the mapping between traffic classes and queues. Note: 3404 * priomap variable support 16 traffic classes, but the chip can handle 3405 * only 8 classes. 3406 */ 3407 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 3408 int queue; 3409 3410 if (tc_prio > KSZ9477_MAX_TC_PRIO) 3411 break; 3412 3413 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 3414 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3415 } 3416 3417 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3418 } 3419 3420 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 3421 { 3422 int ret, queue, tc_prio, s; 3423 u32 queue_map = 0; 3424 3425 /* To restore the default chip configuration, set all queues to use the 3426 * WRR scheduler with a weight of 1. 3427 */ 3428 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3429 ret = ksz_queue_set_wrr(dev, port, queue, 3430 KSZ9477_DEFAULT_WRR_WEIGHT); 3431 if (ret) 3432 return ret; 3433 } 3434 3435 switch (dev->info->num_tx_queues) { 3436 case 2: 3437 s = 2; 3438 break; 3439 case 4: 3440 s = 1; 3441 break; 3442 case 8: 3443 s = 0; 3444 break; 3445 default: 3446 return -EINVAL; 3447 } 3448 3449 /* Revert the queue mapping for TC-priority to its default setting on 3450 * the chip. 3451 */ 3452 for (tc_prio = 0; tc_prio <= KSZ9477_MAX_TC_PRIO; tc_prio++) { 3453 int queue; 3454 3455 queue = tc_prio >> s; 3456 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3457 } 3458 3459 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3460 } 3461 3462 static int ksz_tc_ets_validate(struct ksz_device *dev, int port, 3463 struct tc_ets_qopt_offload_replace_params *p) 3464 { 3465 int band; 3466 3467 /* Since it is not feasible to share one port among multiple qdisc, 3468 * the user must configure all available queues appropriately. 3469 */ 3470 if (p->bands != dev->info->num_tx_queues) { 3471 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 3472 dev->info->num_tx_queues); 3473 return -EOPNOTSUPP; 3474 } 3475 3476 for (band = 0; band < p->bands; ++band) { 3477 /* The KSZ switches utilize a weighted round robin configuration 3478 * where a certain number of packets can be transmitted from a 3479 * queue before the next queue is serviced. For more information 3480 * on this, refer to section 5.2.8.4 of the KSZ8565R 3481 * documentation on the Port Transmit Queue Control 1 Register. 3482 * However, the current ETS Qdisc implementation (as of February 3483 * 2023) assigns a weight to each queue based on the number of 3484 * bytes or extrapolated bandwidth in percentages. Since this 3485 * differs from the KSZ switches' method and we don't want to 3486 * fake support by converting bytes to packets, it is better to 3487 * return an error instead. 3488 */ 3489 if (p->quanta[band]) { 3490 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 3491 return -EOPNOTSUPP; 3492 } 3493 } 3494 3495 return 0; 3496 } 3497 3498 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 3499 struct tc_ets_qopt_offload *qopt) 3500 { 3501 struct ksz_device *dev = ds->priv; 3502 int ret; 3503 3504 if (!dev->info->tc_ets_supported) 3505 return -EOPNOTSUPP; 3506 3507 if (qopt->parent != TC_H_ROOT) { 3508 dev_err(dev->dev, "Parent should be \"root\"\n"); 3509 return -EOPNOTSUPP; 3510 } 3511 3512 switch (qopt->command) { 3513 case TC_ETS_REPLACE: 3514 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 3515 if (ret) 3516 return ret; 3517 3518 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 3519 case TC_ETS_DESTROY: 3520 return ksz_tc_ets_del(dev, port); 3521 case TC_ETS_STATS: 3522 case TC_ETS_GRAFT: 3523 return -EOPNOTSUPP; 3524 } 3525 3526 return -EOPNOTSUPP; 3527 } 3528 3529 static int ksz_setup_tc(struct dsa_switch *ds, int port, 3530 enum tc_setup_type type, void *type_data) 3531 { 3532 switch (type) { 3533 case TC_SETUP_QDISC_CBS: 3534 return ksz_setup_tc_cbs(ds, port, type_data); 3535 case TC_SETUP_QDISC_ETS: 3536 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 3537 default: 3538 return -EOPNOTSUPP; 3539 } 3540 } 3541 3542 static const struct dsa_switch_ops ksz_switch_ops = { 3543 .get_tag_protocol = ksz_get_tag_protocol, 3544 .connect_tag_protocol = ksz_connect_tag_protocol, 3545 .get_phy_flags = ksz_get_phy_flags, 3546 .setup = ksz_setup, 3547 .teardown = ksz_teardown, 3548 .phy_read = ksz_phy_read16, 3549 .phy_write = ksz_phy_write16, 3550 .phylink_get_caps = ksz_phylink_get_caps, 3551 .phylink_mac_config = ksz_phylink_mac_config, 3552 .phylink_mac_link_up = ksz_phylink_mac_link_up, 3553 .phylink_mac_link_down = ksz_mac_link_down, 3554 .port_setup = ksz_port_setup, 3555 .set_ageing_time = ksz_set_ageing_time, 3556 .get_strings = ksz_get_strings, 3557 .get_ethtool_stats = ksz_get_ethtool_stats, 3558 .get_sset_count = ksz_sset_count, 3559 .port_bridge_join = ksz_port_bridge_join, 3560 .port_bridge_leave = ksz_port_bridge_leave, 3561 .port_stp_state_set = ksz_port_stp_state_set, 3562 .port_teardown = ksz_port_teardown, 3563 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 3564 .port_bridge_flags = ksz_port_bridge_flags, 3565 .port_fast_age = ksz_port_fast_age, 3566 .port_vlan_filtering = ksz_port_vlan_filtering, 3567 .port_vlan_add = ksz_port_vlan_add, 3568 .port_vlan_del = ksz_port_vlan_del, 3569 .port_fdb_dump = ksz_port_fdb_dump, 3570 .port_fdb_add = ksz_port_fdb_add, 3571 .port_fdb_del = ksz_port_fdb_del, 3572 .port_mdb_add = ksz_port_mdb_add, 3573 .port_mdb_del = ksz_port_mdb_del, 3574 .port_mirror_add = ksz_port_mirror_add, 3575 .port_mirror_del = ksz_port_mirror_del, 3576 .get_stats64 = ksz_get_stats64, 3577 .get_pause_stats = ksz_get_pause_stats, 3578 .port_change_mtu = ksz_change_mtu, 3579 .port_max_mtu = ksz_max_mtu, 3580 .get_ts_info = ksz_get_ts_info, 3581 .port_hwtstamp_get = ksz_hwtstamp_get, 3582 .port_hwtstamp_set = ksz_hwtstamp_set, 3583 .port_txtstamp = ksz_port_txtstamp, 3584 .port_rxtstamp = ksz_port_rxtstamp, 3585 .cls_flower_add = ksz_cls_flower_add, 3586 .cls_flower_del = ksz_cls_flower_del, 3587 .port_setup_tc = ksz_setup_tc, 3588 .get_mac_eee = ksz_get_mac_eee, 3589 .set_mac_eee = ksz_set_mac_eee, 3590 }; 3591 3592 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 3593 { 3594 struct dsa_switch *ds; 3595 struct ksz_device *swdev; 3596 3597 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 3598 if (!ds) 3599 return NULL; 3600 3601 ds->dev = base; 3602 ds->num_ports = DSA_MAX_PORTS; 3603 ds->ops = &ksz_switch_ops; 3604 3605 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 3606 if (!swdev) 3607 return NULL; 3608 3609 ds->priv = swdev; 3610 swdev->dev = base; 3611 3612 swdev->ds = ds; 3613 swdev->priv = priv; 3614 3615 return swdev; 3616 } 3617 EXPORT_SYMBOL(ksz_switch_alloc); 3618 3619 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 3620 struct device_node *port_dn) 3621 { 3622 phy_interface_t phy_mode = dev->ports[port_num].interface; 3623 int rx_delay = -1, tx_delay = -1; 3624 3625 if (!phy_interface_mode_is_rgmii(phy_mode)) 3626 return; 3627 3628 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 3629 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 3630 3631 if (rx_delay == -1 && tx_delay == -1) { 3632 dev_warn(dev->dev, 3633 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 3634 "please update device tree to specify \"rx-internal-delay-ps\" and " 3635 "\"tx-internal-delay-ps\"", 3636 port_num); 3637 3638 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 3639 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 3640 rx_delay = 2000; 3641 3642 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 3643 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 3644 tx_delay = 2000; 3645 } 3646 3647 if (rx_delay < 0) 3648 rx_delay = 0; 3649 if (tx_delay < 0) 3650 tx_delay = 0; 3651 3652 dev->ports[port_num].rgmii_rx_val = rx_delay; 3653 dev->ports[port_num].rgmii_tx_val = tx_delay; 3654 } 3655 3656 /** 3657 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding 3658 * register value. 3659 * @array: The array of drive strength values to search. 3660 * @array_size: The size of the array. 3661 * @microamp: The drive strength value in microamp to be converted. 3662 * 3663 * This function searches the array of drive strength values for the given 3664 * microamp value and returns the corresponding register value for that drive. 3665 * 3666 * Returns: If found, the corresponding register value for that drive strength 3667 * is returned. Otherwise, -EINVAL is returned indicating an invalid value. 3668 */ 3669 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array, 3670 size_t array_size, int microamp) 3671 { 3672 int i; 3673 3674 for (i = 0; i < array_size; i++) { 3675 if (array[i].microamp == microamp) 3676 return array[i].reg_val; 3677 } 3678 3679 return -EINVAL; 3680 } 3681 3682 /** 3683 * ksz_drive_strength_error() - Report invalid drive strength value 3684 * @dev: ksz device 3685 * @array: The array of drive strength values to search. 3686 * @array_size: The size of the array. 3687 * @microamp: Invalid drive strength value in microamp 3688 * 3689 * This function logs an error message when an unsupported drive strength value 3690 * is detected. It lists out all the supported drive strength values for 3691 * reference in the error message. 3692 */ 3693 static void ksz_drive_strength_error(struct ksz_device *dev, 3694 const struct ksz_drive_strength *array, 3695 size_t array_size, int microamp) 3696 { 3697 char supported_values[100]; 3698 size_t remaining_size; 3699 int added_len; 3700 char *ptr; 3701 int i; 3702 3703 remaining_size = sizeof(supported_values); 3704 ptr = supported_values; 3705 3706 for (i = 0; i < array_size; i++) { 3707 added_len = snprintf(ptr, remaining_size, 3708 i == 0 ? "%d" : ", %d", array[i].microamp); 3709 3710 if (added_len >= remaining_size) 3711 break; 3712 3713 ptr += added_len; 3714 remaining_size -= added_len; 3715 } 3716 3717 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n", 3718 microamp, supported_values); 3719 } 3720 3721 /** 3722 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477 3723 * chip variants. 3724 * @dev: ksz device 3725 * @props: Array of drive strength properties to be applied 3726 * @num_props: Number of properties in the array 3727 * 3728 * This function configures the drive strength for various KSZ9477 chip variants 3729 * based on the provided properties. It handles chip-specific nuances and 3730 * ensures only valid drive strengths are written to the respective chip. 3731 * 3732 * Return: 0 on successful configuration, a negative error code on failure. 3733 */ 3734 static int ksz9477_drive_strength_write(struct ksz_device *dev, 3735 struct ksz_driver_strength_prop *props, 3736 int num_props) 3737 { 3738 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths); 3739 int i, ret, reg; 3740 u8 mask = 0; 3741 u8 val = 0; 3742 3743 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1) 3744 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 3745 props[KSZ_DRIVER_STRENGTH_IO].name); 3746 3747 if (dev->chip_id == KSZ8795_CHIP_ID || 3748 dev->chip_id == KSZ8794_CHIP_ID || 3749 dev->chip_id == KSZ8765_CHIP_ID) 3750 reg = KSZ8795_REG_SW_CTRL_20; 3751 else 3752 reg = KSZ9477_REG_SW_IO_STRENGTH; 3753 3754 for (i = 0; i < num_props; i++) { 3755 if (props[i].value == -1) 3756 continue; 3757 3758 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths, 3759 array_size, props[i].value); 3760 if (ret < 0) { 3761 ksz_drive_strength_error(dev, ksz9477_drive_strengths, 3762 array_size, props[i].value); 3763 return ret; 3764 } 3765 3766 mask |= SW_DRIVE_STRENGTH_M << props[i].offset; 3767 val |= ret << props[i].offset; 3768 } 3769 3770 return ksz_rmw8(dev, reg, mask, val); 3771 } 3772 3773 /** 3774 * ksz8830_drive_strength_write() - Set the drive strength configuration for 3775 * KSZ8830 compatible chip variants. 3776 * @dev: ksz device 3777 * @props: Array of drive strength properties to be set 3778 * @num_props: Number of properties in the array 3779 * 3780 * This function applies the specified drive strength settings to KSZ8830 chip 3781 * variants (KSZ8873, KSZ8863). 3782 * It ensures the configurations align with what the chip variant supports and 3783 * warns or errors out on unsupported settings. 3784 * 3785 * Return: 0 on success, error code otherwise 3786 */ 3787 static int ksz8830_drive_strength_write(struct ksz_device *dev, 3788 struct ksz_driver_strength_prop *props, 3789 int num_props) 3790 { 3791 size_t array_size = ARRAY_SIZE(ksz8830_drive_strengths); 3792 int microamp; 3793 int i, ret; 3794 3795 for (i = 0; i < num_props; i++) { 3796 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO) 3797 continue; 3798 3799 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 3800 props[i].name); 3801 } 3802 3803 microamp = props[KSZ_DRIVER_STRENGTH_IO].value; 3804 ret = ksz_drive_strength_to_reg(ksz8830_drive_strengths, array_size, 3805 microamp); 3806 if (ret < 0) { 3807 ksz_drive_strength_error(dev, ksz8830_drive_strengths, 3808 array_size, microamp); 3809 return ret; 3810 } 3811 3812 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12, 3813 KSZ8873_DRIVE_STRENGTH_16MA, ret); 3814 } 3815 3816 /** 3817 * ksz_parse_drive_strength() - Extract and apply drive strength configurations 3818 * from device tree properties. 3819 * @dev: ksz device 3820 * 3821 * This function reads the specified drive strength properties from the 3822 * device tree, validates against the supported chip variants, and sets 3823 * them accordingly. An error should be critical here, as the drive strength 3824 * settings are crucial for EMI compliance. 3825 * 3826 * Return: 0 on success, error code otherwise 3827 */ 3828 static int ksz_parse_drive_strength(struct ksz_device *dev) 3829 { 3830 struct ksz_driver_strength_prop of_props[] = { 3831 [KSZ_DRIVER_STRENGTH_HI] = { 3832 .name = "microchip,hi-drive-strength-microamp", 3833 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S, 3834 .value = -1, 3835 }, 3836 [KSZ_DRIVER_STRENGTH_LO] = { 3837 .name = "microchip,lo-drive-strength-microamp", 3838 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S, 3839 .value = -1, 3840 }, 3841 [KSZ_DRIVER_STRENGTH_IO] = { 3842 .name = "microchip,io-drive-strength-microamp", 3843 .offset = 0, /* don't care */ 3844 .value = -1, 3845 }, 3846 }; 3847 struct device_node *np = dev->dev->of_node; 3848 bool have_any_prop = false; 3849 int i, ret; 3850 3851 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 3852 ret = of_property_read_u32(np, of_props[i].name, 3853 &of_props[i].value); 3854 if (ret && ret != -EINVAL) 3855 dev_warn(dev->dev, "Failed to read %s\n", 3856 of_props[i].name); 3857 if (ret) 3858 continue; 3859 3860 have_any_prop = true; 3861 } 3862 3863 if (!have_any_prop) 3864 return 0; 3865 3866 switch (dev->chip_id) { 3867 case KSZ8830_CHIP_ID: 3868 return ksz8830_drive_strength_write(dev, of_props, 3869 ARRAY_SIZE(of_props)); 3870 case KSZ8795_CHIP_ID: 3871 case KSZ8794_CHIP_ID: 3872 case KSZ8765_CHIP_ID: 3873 case KSZ8563_CHIP_ID: 3874 case KSZ9477_CHIP_ID: 3875 case KSZ9563_CHIP_ID: 3876 case KSZ9567_CHIP_ID: 3877 case KSZ9893_CHIP_ID: 3878 case KSZ9896_CHIP_ID: 3879 case KSZ9897_CHIP_ID: 3880 return ksz9477_drive_strength_write(dev, of_props, 3881 ARRAY_SIZE(of_props)); 3882 default: 3883 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 3884 if (of_props[i].value == -1) 3885 continue; 3886 3887 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 3888 of_props[i].name); 3889 } 3890 } 3891 3892 return 0; 3893 } 3894 3895 int ksz_switch_register(struct ksz_device *dev) 3896 { 3897 const struct ksz_chip_data *info; 3898 struct device_node *port, *ports; 3899 phy_interface_t interface; 3900 unsigned int port_num; 3901 int ret; 3902 int i; 3903 3904 if (dev->pdata) 3905 dev->chip_id = dev->pdata->chip_id; 3906 3907 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 3908 GPIOD_OUT_LOW); 3909 if (IS_ERR(dev->reset_gpio)) 3910 return PTR_ERR(dev->reset_gpio); 3911 3912 if (dev->reset_gpio) { 3913 gpiod_set_value_cansleep(dev->reset_gpio, 1); 3914 usleep_range(10000, 12000); 3915 gpiod_set_value_cansleep(dev->reset_gpio, 0); 3916 msleep(100); 3917 } 3918 3919 mutex_init(&dev->dev_mutex); 3920 mutex_init(&dev->regmap_mutex); 3921 mutex_init(&dev->alu_mutex); 3922 mutex_init(&dev->vlan_mutex); 3923 3924 ret = ksz_switch_detect(dev); 3925 if (ret) 3926 return ret; 3927 3928 info = ksz_lookup_info(dev->chip_id); 3929 if (!info) 3930 return -ENODEV; 3931 3932 /* Update the compatible info with the probed one */ 3933 dev->info = info; 3934 3935 dev_info(dev->dev, "found switch: %s, rev %i\n", 3936 dev->info->dev_name, dev->chip_rev); 3937 3938 ret = ksz_check_device_id(dev); 3939 if (ret) 3940 return ret; 3941 3942 dev->dev_ops = dev->info->ops; 3943 3944 ret = dev->dev_ops->init(dev); 3945 if (ret) 3946 return ret; 3947 3948 dev->ports = devm_kzalloc(dev->dev, 3949 dev->info->port_cnt * sizeof(struct ksz_port), 3950 GFP_KERNEL); 3951 if (!dev->ports) 3952 return -ENOMEM; 3953 3954 for (i = 0; i < dev->info->port_cnt; i++) { 3955 spin_lock_init(&dev->ports[i].mib.stats64_lock); 3956 mutex_init(&dev->ports[i].mib.cnt_mutex); 3957 dev->ports[i].mib.counters = 3958 devm_kzalloc(dev->dev, 3959 sizeof(u64) * (dev->info->mib_cnt + 1), 3960 GFP_KERNEL); 3961 if (!dev->ports[i].mib.counters) 3962 return -ENOMEM; 3963 3964 dev->ports[i].ksz_dev = dev; 3965 dev->ports[i].num = i; 3966 } 3967 3968 /* set the real number of ports */ 3969 dev->ds->num_ports = dev->info->port_cnt; 3970 3971 /* Host port interface will be self detected, or specifically set in 3972 * device tree. 3973 */ 3974 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 3975 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 3976 if (dev->dev->of_node) { 3977 ret = ksz_parse_drive_strength(dev); 3978 if (ret) 3979 return ret; 3980 3981 ret = of_get_phy_mode(dev->dev->of_node, &interface); 3982 if (ret == 0) 3983 dev->compat_interface = interface; 3984 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 3985 if (!ports) 3986 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 3987 if (ports) { 3988 for_each_available_child_of_node(ports, port) { 3989 if (of_property_read_u32(port, "reg", 3990 &port_num)) 3991 continue; 3992 if (!(dev->port_mask & BIT(port_num))) { 3993 of_node_put(port); 3994 of_node_put(ports); 3995 return -EINVAL; 3996 } 3997 of_get_phy_mode(port, 3998 &dev->ports[port_num].interface); 3999 4000 ksz_parse_rgmii_delay(dev, port_num, port); 4001 } 4002 of_node_put(ports); 4003 } 4004 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 4005 "microchip,synclko-125"); 4006 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 4007 "microchip,synclko-disable"); 4008 if (dev->synclko_125 && dev->synclko_disable) { 4009 dev_err(dev->dev, "inconsistent synclko settings\n"); 4010 return -EINVAL; 4011 } 4012 } 4013 4014 ret = dsa_register_switch(dev->ds); 4015 if (ret) { 4016 dev->dev_ops->exit(dev); 4017 return ret; 4018 } 4019 4020 /* Read MIB counters every 30 seconds to avoid overflow. */ 4021 dev->mib_read_interval = msecs_to_jiffies(5000); 4022 4023 /* Start the MIB timer. */ 4024 schedule_delayed_work(&dev->mib_read, 0); 4025 4026 return ret; 4027 } 4028 EXPORT_SYMBOL(ksz_switch_register); 4029 4030 void ksz_switch_remove(struct ksz_device *dev) 4031 { 4032 /* timer started */ 4033 if (dev->mib_read_interval) { 4034 dev->mib_read_interval = 0; 4035 cancel_delayed_work_sync(&dev->mib_read); 4036 } 4037 4038 dev->dev_ops->exit(dev); 4039 dsa_unregister_switch(dev->ds); 4040 4041 if (dev->reset_gpio) 4042 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4043 4044 } 4045 EXPORT_SYMBOL(ksz_switch_remove); 4046 4047 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 4048 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 4049 MODULE_LICENSE("GPL"); 4050