1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2024 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/if_hsr.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/of.h> 23 #include <linux/of_mdio.h> 24 #include <linux/of_net.h> 25 #include <linux/micrel_phy.h> 26 #include <net/dsa.h> 27 #include <net/ieee8021q.h> 28 #include <net/pkt_cls.h> 29 #include <net/switchdev.h> 30 31 #include "ksz_common.h" 32 #include "ksz_dcb.h" 33 #include "ksz_ptp.h" 34 #include "ksz8.h" 35 #include "ksz9477.h" 36 #include "lan937x.h" 37 38 #define MIB_COUNTER_NUM 0x20 39 40 struct ksz_stats_raw { 41 u64 rx_hi; 42 u64 rx_undersize; 43 u64 rx_fragments; 44 u64 rx_oversize; 45 u64 rx_jabbers; 46 u64 rx_symbol_err; 47 u64 rx_crc_err; 48 u64 rx_align_err; 49 u64 rx_mac_ctrl; 50 u64 rx_pause; 51 u64 rx_bcast; 52 u64 rx_mcast; 53 u64 rx_ucast; 54 u64 rx_64_or_less; 55 u64 rx_65_127; 56 u64 rx_128_255; 57 u64 rx_256_511; 58 u64 rx_512_1023; 59 u64 rx_1024_1522; 60 u64 rx_1523_2000; 61 u64 rx_2001; 62 u64 tx_hi; 63 u64 tx_late_col; 64 u64 tx_pause; 65 u64 tx_bcast; 66 u64 tx_mcast; 67 u64 tx_ucast; 68 u64 tx_deferred; 69 u64 tx_total_col; 70 u64 tx_exc_col; 71 u64 tx_single_col; 72 u64 tx_mult_col; 73 u64 rx_total; 74 u64 tx_total; 75 u64 rx_discards; 76 u64 tx_discards; 77 }; 78 79 struct ksz88xx_stats_raw { 80 u64 rx; 81 u64 rx_hi; 82 u64 rx_undersize; 83 u64 rx_fragments; 84 u64 rx_oversize; 85 u64 rx_jabbers; 86 u64 rx_symbol_err; 87 u64 rx_crc_err; 88 u64 rx_align_err; 89 u64 rx_mac_ctrl; 90 u64 rx_pause; 91 u64 rx_bcast; 92 u64 rx_mcast; 93 u64 rx_ucast; 94 u64 rx_64_or_less; 95 u64 rx_65_127; 96 u64 rx_128_255; 97 u64 rx_256_511; 98 u64 rx_512_1023; 99 u64 rx_1024_1522; 100 u64 tx; 101 u64 tx_hi; 102 u64 tx_late_col; 103 u64 tx_pause; 104 u64 tx_bcast; 105 u64 tx_mcast; 106 u64 tx_ucast; 107 u64 tx_deferred; 108 u64 tx_total_col; 109 u64 tx_exc_col; 110 u64 tx_single_col; 111 u64 tx_mult_col; 112 u64 rx_discards; 113 u64 tx_discards; 114 }; 115 116 static const struct ksz_mib_names ksz88xx_mib_names[] = { 117 { 0x00, "rx" }, 118 { 0x01, "rx_hi" }, 119 { 0x02, "rx_undersize" }, 120 { 0x03, "rx_fragments" }, 121 { 0x04, "rx_oversize" }, 122 { 0x05, "rx_jabbers" }, 123 { 0x06, "rx_symbol_err" }, 124 { 0x07, "rx_crc_err" }, 125 { 0x08, "rx_align_err" }, 126 { 0x09, "rx_mac_ctrl" }, 127 { 0x0a, "rx_pause" }, 128 { 0x0b, "rx_bcast" }, 129 { 0x0c, "rx_mcast" }, 130 { 0x0d, "rx_ucast" }, 131 { 0x0e, "rx_64_or_less" }, 132 { 0x0f, "rx_65_127" }, 133 { 0x10, "rx_128_255" }, 134 { 0x11, "rx_256_511" }, 135 { 0x12, "rx_512_1023" }, 136 { 0x13, "rx_1024_1522" }, 137 { 0x14, "tx" }, 138 { 0x15, "tx_hi" }, 139 { 0x16, "tx_late_col" }, 140 { 0x17, "tx_pause" }, 141 { 0x18, "tx_bcast" }, 142 { 0x19, "tx_mcast" }, 143 { 0x1a, "tx_ucast" }, 144 { 0x1b, "tx_deferred" }, 145 { 0x1c, "tx_total_col" }, 146 { 0x1d, "tx_exc_col" }, 147 { 0x1e, "tx_single_col" }, 148 { 0x1f, "tx_mult_col" }, 149 { 0x100, "rx_discards" }, 150 { 0x101, "tx_discards" }, 151 }; 152 153 static const struct ksz_mib_names ksz9477_mib_names[] = { 154 { 0x00, "rx_hi" }, 155 { 0x01, "rx_undersize" }, 156 { 0x02, "rx_fragments" }, 157 { 0x03, "rx_oversize" }, 158 { 0x04, "rx_jabbers" }, 159 { 0x05, "rx_symbol_err" }, 160 { 0x06, "rx_crc_err" }, 161 { 0x07, "rx_align_err" }, 162 { 0x08, "rx_mac_ctrl" }, 163 { 0x09, "rx_pause" }, 164 { 0x0A, "rx_bcast" }, 165 { 0x0B, "rx_mcast" }, 166 { 0x0C, "rx_ucast" }, 167 { 0x0D, "rx_64_or_less" }, 168 { 0x0E, "rx_65_127" }, 169 { 0x0F, "rx_128_255" }, 170 { 0x10, "rx_256_511" }, 171 { 0x11, "rx_512_1023" }, 172 { 0x12, "rx_1024_1522" }, 173 { 0x13, "rx_1523_2000" }, 174 { 0x14, "rx_2001" }, 175 { 0x15, "tx_hi" }, 176 { 0x16, "tx_late_col" }, 177 { 0x17, "tx_pause" }, 178 { 0x18, "tx_bcast" }, 179 { 0x19, "tx_mcast" }, 180 { 0x1A, "tx_ucast" }, 181 { 0x1B, "tx_deferred" }, 182 { 0x1C, "tx_total_col" }, 183 { 0x1D, "tx_exc_col" }, 184 { 0x1E, "tx_single_col" }, 185 { 0x1F, "tx_mult_col" }, 186 { 0x80, "rx_total" }, 187 { 0x81, "tx_total" }, 188 { 0x82, "rx_discards" }, 189 { 0x83, "tx_discards" }, 190 }; 191 192 struct ksz_driver_strength_prop { 193 const char *name; 194 int offset; 195 int value; 196 }; 197 198 enum ksz_driver_strength_type { 199 KSZ_DRIVER_STRENGTH_HI, 200 KSZ_DRIVER_STRENGTH_LO, 201 KSZ_DRIVER_STRENGTH_IO, 202 }; 203 204 /** 205 * struct ksz_drive_strength - drive strength mapping 206 * @reg_val: register value 207 * @microamp: microamp value 208 */ 209 struct ksz_drive_strength { 210 u32 reg_val; 211 u32 microamp; 212 }; 213 214 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants 215 * 216 * This values are not documented in KSZ9477 variants but confirmed by 217 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893 218 * and KSZ8563 are using same register (drive strength) settings like KSZ8795. 219 * 220 * Documentation in KSZ8795CLX provides more information with some 221 * recommendations: 222 * - for high speed signals 223 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using 224 * 2.5V or 3.3V VDDIO. 225 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with 226 * using 1.8V VDDIO. 227 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V 228 * or 3.3V VDDIO. 229 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO. 230 * 5. In same interface, the heavy loading should use higher one of the 231 * drive current strength. 232 * - for low speed signals 233 * 1. 3.3V VDDIO, use either 4 mA or 8 mA. 234 * 2. 2.5V VDDIO, use either 8 mA or 12 mA. 235 * 3. 1.8V VDDIO, use either 12 mA or 16 mA. 236 * 4. If it is heavy loading, can use higher drive current strength. 237 */ 238 static const struct ksz_drive_strength ksz9477_drive_strengths[] = { 239 { SW_DRIVE_STRENGTH_2MA, 2000 }, 240 { SW_DRIVE_STRENGTH_4MA, 4000 }, 241 { SW_DRIVE_STRENGTH_8MA, 8000 }, 242 { SW_DRIVE_STRENGTH_12MA, 12000 }, 243 { SW_DRIVE_STRENGTH_16MA, 16000 }, 244 { SW_DRIVE_STRENGTH_20MA, 20000 }, 245 { SW_DRIVE_STRENGTH_24MA, 24000 }, 246 { SW_DRIVE_STRENGTH_28MA, 28000 }, 247 }; 248 249 /* ksz88x3_drive_strengths - Drive strength mapping for KSZ8863, KSZ8873, .. 250 * variants. 251 * This values are documented in KSZ8873 and KSZ8863 datasheets. 252 */ 253 static const struct ksz_drive_strength ksz88x3_drive_strengths[] = { 254 { 0, 8000 }, 255 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 }, 256 }; 257 258 static void ksz88x3_phylink_mac_config(struct phylink_config *config, 259 unsigned int mode, 260 const struct phylink_link_state *state); 261 static void ksz_phylink_mac_config(struct phylink_config *config, 262 unsigned int mode, 263 const struct phylink_link_state *state); 264 static void ksz_phylink_mac_link_down(struct phylink_config *config, 265 unsigned int mode, 266 phy_interface_t interface); 267 268 static const struct phylink_mac_ops ksz88x3_phylink_mac_ops = { 269 .mac_config = ksz88x3_phylink_mac_config, 270 .mac_link_down = ksz_phylink_mac_link_down, 271 .mac_link_up = ksz8_phylink_mac_link_up, 272 }; 273 274 static const struct phylink_mac_ops ksz8_phylink_mac_ops = { 275 .mac_config = ksz_phylink_mac_config, 276 .mac_link_down = ksz_phylink_mac_link_down, 277 .mac_link_up = ksz8_phylink_mac_link_up, 278 }; 279 280 static const struct ksz_dev_ops ksz88xx_dev_ops = { 281 .setup = ksz8_setup, 282 .get_port_addr = ksz8_get_port_addr, 283 .cfg_port_member = ksz8_cfg_port_member, 284 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 285 .port_setup = ksz8_port_setup, 286 .r_phy = ksz8_r_phy, 287 .w_phy = ksz8_w_phy, 288 .r_mib_cnt = ksz8_r_mib_cnt, 289 .r_mib_pkt = ksz8_r_mib_pkt, 290 .r_mib_stat64 = ksz88xx_r_mib_stats64, 291 .freeze_mib = ksz8_freeze_mib, 292 .port_init_cnt = ksz8_port_init_cnt, 293 .fdb_dump = ksz8_fdb_dump, 294 .fdb_add = ksz8_fdb_add, 295 .fdb_del = ksz8_fdb_del, 296 .mdb_add = ksz8_mdb_add, 297 .mdb_del = ksz8_mdb_del, 298 .vlan_filtering = ksz8_port_vlan_filtering, 299 .vlan_add = ksz8_port_vlan_add, 300 .vlan_del = ksz8_port_vlan_del, 301 .mirror_add = ksz8_port_mirror_add, 302 .mirror_del = ksz8_port_mirror_del, 303 .get_caps = ksz8_get_caps, 304 .config_cpu_port = ksz8_config_cpu_port, 305 .enable_stp_addr = ksz8_enable_stp_addr, 306 .reset = ksz8_reset_switch, 307 .init = ksz8_switch_init, 308 .exit = ksz8_switch_exit, 309 .change_mtu = ksz8_change_mtu, 310 .pme_write8 = ksz8_pme_write8, 311 .pme_pread8 = ksz8_pme_pread8, 312 .pme_pwrite8 = ksz8_pme_pwrite8, 313 }; 314 315 static const struct ksz_dev_ops ksz87xx_dev_ops = { 316 .setup = ksz8_setup, 317 .get_port_addr = ksz8_get_port_addr, 318 .cfg_port_member = ksz8_cfg_port_member, 319 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 320 .port_setup = ksz8_port_setup, 321 .r_phy = ksz8_r_phy, 322 .w_phy = ksz8_w_phy, 323 .r_mib_cnt = ksz8_r_mib_cnt, 324 .r_mib_pkt = ksz8_r_mib_pkt, 325 .r_mib_stat64 = ksz_r_mib_stats64, 326 .freeze_mib = ksz8_freeze_mib, 327 .port_init_cnt = ksz8_port_init_cnt, 328 .fdb_dump = ksz8_fdb_dump, 329 .fdb_add = ksz8_fdb_add, 330 .fdb_del = ksz8_fdb_del, 331 .mdb_add = ksz8_mdb_add, 332 .mdb_del = ksz8_mdb_del, 333 .vlan_filtering = ksz8_port_vlan_filtering, 334 .vlan_add = ksz8_port_vlan_add, 335 .vlan_del = ksz8_port_vlan_del, 336 .mirror_add = ksz8_port_mirror_add, 337 .mirror_del = ksz8_port_mirror_del, 338 .get_caps = ksz8_get_caps, 339 .config_cpu_port = ksz8_config_cpu_port, 340 .enable_stp_addr = ksz8_enable_stp_addr, 341 .reset = ksz8_reset_switch, 342 .init = ksz8_switch_init, 343 .exit = ksz8_switch_exit, 344 .change_mtu = ksz8_change_mtu, 345 .pme_write8 = ksz8_pme_write8, 346 .pme_pread8 = ksz8_pme_pread8, 347 .pme_pwrite8 = ksz8_pme_pwrite8, 348 }; 349 350 static void ksz9477_phylink_mac_link_up(struct phylink_config *config, 351 struct phy_device *phydev, 352 unsigned int mode, 353 phy_interface_t interface, 354 int speed, int duplex, bool tx_pause, 355 bool rx_pause); 356 357 static const struct phylink_mac_ops ksz9477_phylink_mac_ops = { 358 .mac_config = ksz_phylink_mac_config, 359 .mac_link_down = ksz_phylink_mac_link_down, 360 .mac_link_up = ksz9477_phylink_mac_link_up, 361 }; 362 363 static const struct ksz_dev_ops ksz9477_dev_ops = { 364 .setup = ksz9477_setup, 365 .get_port_addr = ksz9477_get_port_addr, 366 .cfg_port_member = ksz9477_cfg_port_member, 367 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 368 .port_setup = ksz9477_port_setup, 369 .set_ageing_time = ksz9477_set_ageing_time, 370 .r_phy = ksz9477_r_phy, 371 .w_phy = ksz9477_w_phy, 372 .r_mib_cnt = ksz9477_r_mib_cnt, 373 .r_mib_pkt = ksz9477_r_mib_pkt, 374 .r_mib_stat64 = ksz_r_mib_stats64, 375 .freeze_mib = ksz9477_freeze_mib, 376 .port_init_cnt = ksz9477_port_init_cnt, 377 .vlan_filtering = ksz9477_port_vlan_filtering, 378 .vlan_add = ksz9477_port_vlan_add, 379 .vlan_del = ksz9477_port_vlan_del, 380 .mirror_add = ksz9477_port_mirror_add, 381 .mirror_del = ksz9477_port_mirror_del, 382 .get_caps = ksz9477_get_caps, 383 .fdb_dump = ksz9477_fdb_dump, 384 .fdb_add = ksz9477_fdb_add, 385 .fdb_del = ksz9477_fdb_del, 386 .mdb_add = ksz9477_mdb_add, 387 .mdb_del = ksz9477_mdb_del, 388 .change_mtu = ksz9477_change_mtu, 389 .pme_write8 = ksz_write8, 390 .pme_pread8 = ksz_pread8, 391 .pme_pwrite8 = ksz_pwrite8, 392 .config_cpu_port = ksz9477_config_cpu_port, 393 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc, 394 .enable_stp_addr = ksz9477_enable_stp_addr, 395 .reset = ksz9477_reset_switch, 396 .init = ksz9477_switch_init, 397 .exit = ksz9477_switch_exit, 398 }; 399 400 static const struct phylink_mac_ops lan937x_phylink_mac_ops = { 401 .mac_config = ksz_phylink_mac_config, 402 .mac_link_down = ksz_phylink_mac_link_down, 403 .mac_link_up = ksz9477_phylink_mac_link_up, 404 }; 405 406 static const struct ksz_dev_ops lan937x_dev_ops = { 407 .setup = lan937x_setup, 408 .teardown = lan937x_teardown, 409 .get_port_addr = ksz9477_get_port_addr, 410 .cfg_port_member = ksz9477_cfg_port_member, 411 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 412 .port_setup = lan937x_port_setup, 413 .set_ageing_time = lan937x_set_ageing_time, 414 .r_phy = lan937x_r_phy, 415 .w_phy = lan937x_w_phy, 416 .r_mib_cnt = ksz9477_r_mib_cnt, 417 .r_mib_pkt = ksz9477_r_mib_pkt, 418 .r_mib_stat64 = ksz_r_mib_stats64, 419 .freeze_mib = ksz9477_freeze_mib, 420 .port_init_cnt = ksz9477_port_init_cnt, 421 .vlan_filtering = ksz9477_port_vlan_filtering, 422 .vlan_add = ksz9477_port_vlan_add, 423 .vlan_del = ksz9477_port_vlan_del, 424 .mirror_add = ksz9477_port_mirror_add, 425 .mirror_del = ksz9477_port_mirror_del, 426 .get_caps = lan937x_phylink_get_caps, 427 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 428 .fdb_dump = ksz9477_fdb_dump, 429 .fdb_add = ksz9477_fdb_add, 430 .fdb_del = ksz9477_fdb_del, 431 .mdb_add = ksz9477_mdb_add, 432 .mdb_del = ksz9477_mdb_del, 433 .change_mtu = lan937x_change_mtu, 434 .config_cpu_port = lan937x_config_cpu_port, 435 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 436 .enable_stp_addr = ksz9477_enable_stp_addr, 437 .reset = lan937x_reset_switch, 438 .init = lan937x_switch_init, 439 .exit = lan937x_switch_exit, 440 }; 441 442 static const u16 ksz8795_regs[] = { 443 [REG_SW_MAC_ADDR] = 0x68, 444 [REG_IND_CTRL_0] = 0x6E, 445 [REG_IND_DATA_8] = 0x70, 446 [REG_IND_DATA_CHECK] = 0x72, 447 [REG_IND_DATA_HI] = 0x71, 448 [REG_IND_DATA_LO] = 0x75, 449 [REG_IND_MIB_CHECK] = 0x74, 450 [REG_IND_BYTE] = 0xA0, 451 [P_FORCE_CTRL] = 0x0C, 452 [P_LINK_STATUS] = 0x0E, 453 [P_LOCAL_CTRL] = 0x07, 454 [P_NEG_RESTART_CTRL] = 0x0D, 455 [P_REMOTE_STATUS] = 0x08, 456 [P_SPEED_STATUS] = 0x09, 457 [S_TAIL_TAG_CTRL] = 0x0C, 458 [P_STP_CTRL] = 0x02, 459 [S_START_CTRL] = 0x01, 460 [S_BROADCAST_CTRL] = 0x06, 461 [S_MULTICAST_CTRL] = 0x04, 462 [P_XMII_CTRL_0] = 0x06, 463 [P_XMII_CTRL_1] = 0x06, 464 [REG_SW_PME_CTRL] = 0x8003, 465 [REG_PORT_PME_STATUS] = 0x8003, 466 [REG_PORT_PME_CTRL] = 0x8007, 467 }; 468 469 static const u32 ksz8795_masks[] = { 470 [PORT_802_1P_REMAPPING] = BIT(7), 471 [SW_TAIL_TAG_ENABLE] = BIT(1), 472 [MIB_COUNTER_OVERFLOW] = BIT(6), 473 [MIB_COUNTER_VALID] = BIT(5), 474 [VLAN_TABLE_FID] = GENMASK(6, 0), 475 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 476 [VLAN_TABLE_VALID] = BIT(12), 477 [STATIC_MAC_TABLE_VALID] = BIT(21), 478 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 479 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 480 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 481 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 482 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 483 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 484 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 485 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 486 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 487 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 488 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 489 [P_MII_TX_FLOW_CTRL] = BIT(5), 490 [P_MII_RX_FLOW_CTRL] = BIT(5), 491 }; 492 493 static const u8 ksz8795_xmii_ctrl0[] = { 494 [P_MII_100MBIT] = 0, 495 [P_MII_10MBIT] = 1, 496 [P_MII_FULL_DUPLEX] = 0, 497 [P_MII_HALF_DUPLEX] = 1, 498 }; 499 500 static const u8 ksz8795_xmii_ctrl1[] = { 501 [P_RGMII_SEL] = 3, 502 [P_GMII_SEL] = 2, 503 [P_RMII_SEL] = 1, 504 [P_MII_SEL] = 0, 505 [P_GMII_1GBIT] = 1, 506 [P_GMII_NOT_1GBIT] = 0, 507 }; 508 509 static const u8 ksz8795_shifts[] = { 510 [VLAN_TABLE_MEMBERSHIP_S] = 7, 511 [VLAN_TABLE] = 16, 512 [STATIC_MAC_FWD_PORTS] = 16, 513 [STATIC_MAC_FID] = 24, 514 [DYNAMIC_MAC_ENTRIES_H] = 3, 515 [DYNAMIC_MAC_ENTRIES] = 29, 516 [DYNAMIC_MAC_FID] = 16, 517 [DYNAMIC_MAC_TIMESTAMP] = 27, 518 [DYNAMIC_MAC_SRC_PORT] = 24, 519 }; 520 521 static const u16 ksz8863_regs[] = { 522 [REG_SW_MAC_ADDR] = 0x70, 523 [REG_IND_CTRL_0] = 0x79, 524 [REG_IND_DATA_8] = 0x7B, 525 [REG_IND_DATA_CHECK] = 0x7B, 526 [REG_IND_DATA_HI] = 0x7C, 527 [REG_IND_DATA_LO] = 0x80, 528 [REG_IND_MIB_CHECK] = 0x80, 529 [P_FORCE_CTRL] = 0x0C, 530 [P_LINK_STATUS] = 0x0E, 531 [P_LOCAL_CTRL] = 0x0C, 532 [P_NEG_RESTART_CTRL] = 0x0D, 533 [P_REMOTE_STATUS] = 0x0E, 534 [P_SPEED_STATUS] = 0x0F, 535 [S_TAIL_TAG_CTRL] = 0x03, 536 [P_STP_CTRL] = 0x02, 537 [S_START_CTRL] = 0x01, 538 [S_BROADCAST_CTRL] = 0x06, 539 [S_MULTICAST_CTRL] = 0x04, 540 }; 541 542 static const u32 ksz8863_masks[] = { 543 [PORT_802_1P_REMAPPING] = BIT(3), 544 [SW_TAIL_TAG_ENABLE] = BIT(6), 545 [MIB_COUNTER_OVERFLOW] = BIT(7), 546 [MIB_COUNTER_VALID] = BIT(6), 547 [VLAN_TABLE_FID] = GENMASK(15, 12), 548 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 549 [VLAN_TABLE_VALID] = BIT(19), 550 [STATIC_MAC_TABLE_VALID] = BIT(19), 551 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 552 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 553 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 554 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 555 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 556 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 557 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 558 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 559 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 560 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 561 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 562 }; 563 564 static u8 ksz8863_shifts[] = { 565 [VLAN_TABLE_MEMBERSHIP_S] = 16, 566 [STATIC_MAC_FWD_PORTS] = 16, 567 [STATIC_MAC_FID] = 22, 568 [DYNAMIC_MAC_ENTRIES_H] = 8, 569 [DYNAMIC_MAC_ENTRIES] = 24, 570 [DYNAMIC_MAC_FID] = 16, 571 [DYNAMIC_MAC_TIMESTAMP] = 22, 572 [DYNAMIC_MAC_SRC_PORT] = 20, 573 }; 574 575 static const u16 ksz8895_regs[] = { 576 [REG_SW_MAC_ADDR] = 0x68, 577 [REG_IND_CTRL_0] = 0x6E, 578 [REG_IND_DATA_8] = 0x70, 579 [REG_IND_DATA_CHECK] = 0x72, 580 [REG_IND_DATA_HI] = 0x71, 581 [REG_IND_DATA_LO] = 0x75, 582 [REG_IND_MIB_CHECK] = 0x75, 583 [P_FORCE_CTRL] = 0x0C, 584 [P_LINK_STATUS] = 0x0E, 585 [P_LOCAL_CTRL] = 0x0C, 586 [P_NEG_RESTART_CTRL] = 0x0D, 587 [P_REMOTE_STATUS] = 0x0E, 588 [P_SPEED_STATUS] = 0x09, 589 [S_TAIL_TAG_CTRL] = 0x0C, 590 [P_STP_CTRL] = 0x02, 591 [S_START_CTRL] = 0x01, 592 [S_BROADCAST_CTRL] = 0x06, 593 [S_MULTICAST_CTRL] = 0x04, 594 }; 595 596 static const u32 ksz8895_masks[] = { 597 [PORT_802_1P_REMAPPING] = BIT(7), 598 [SW_TAIL_TAG_ENABLE] = BIT(1), 599 [MIB_COUNTER_OVERFLOW] = BIT(7), 600 [MIB_COUNTER_VALID] = BIT(6), 601 [VLAN_TABLE_FID] = GENMASK(6, 0), 602 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 603 [VLAN_TABLE_VALID] = BIT(12), 604 [STATIC_MAC_TABLE_VALID] = BIT(21), 605 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 606 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 607 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 608 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 609 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 610 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 611 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 612 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 613 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 614 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 615 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 616 }; 617 618 static const u8 ksz8895_shifts[] = { 619 [VLAN_TABLE_MEMBERSHIP_S] = 7, 620 [VLAN_TABLE] = 13, 621 [STATIC_MAC_FWD_PORTS] = 16, 622 [STATIC_MAC_FID] = 24, 623 [DYNAMIC_MAC_ENTRIES_H] = 3, 624 [DYNAMIC_MAC_ENTRIES] = 29, 625 [DYNAMIC_MAC_FID] = 16, 626 [DYNAMIC_MAC_TIMESTAMP] = 27, 627 [DYNAMIC_MAC_SRC_PORT] = 24, 628 }; 629 630 static const u16 ksz9477_regs[] = { 631 [REG_SW_MAC_ADDR] = 0x0302, 632 [P_STP_CTRL] = 0x0B04, 633 [S_START_CTRL] = 0x0300, 634 [S_BROADCAST_CTRL] = 0x0332, 635 [S_MULTICAST_CTRL] = 0x0331, 636 [P_XMII_CTRL_0] = 0x0300, 637 [P_XMII_CTRL_1] = 0x0301, 638 [REG_SW_PME_CTRL] = 0x0006, 639 [REG_PORT_PME_STATUS] = 0x0013, 640 [REG_PORT_PME_CTRL] = 0x0017, 641 }; 642 643 static const u32 ksz9477_masks[] = { 644 [ALU_STAT_WRITE] = 0, 645 [ALU_STAT_READ] = 1, 646 [P_MII_TX_FLOW_CTRL] = BIT(5), 647 [P_MII_RX_FLOW_CTRL] = BIT(3), 648 }; 649 650 static const u8 ksz9477_shifts[] = { 651 [ALU_STAT_INDEX] = 16, 652 }; 653 654 static const u8 ksz9477_xmii_ctrl0[] = { 655 [P_MII_100MBIT] = 1, 656 [P_MII_10MBIT] = 0, 657 [P_MII_FULL_DUPLEX] = 1, 658 [P_MII_HALF_DUPLEX] = 0, 659 }; 660 661 static const u8 ksz9477_xmii_ctrl1[] = { 662 [P_RGMII_SEL] = 0, 663 [P_RMII_SEL] = 1, 664 [P_GMII_SEL] = 2, 665 [P_MII_SEL] = 3, 666 [P_GMII_1GBIT] = 0, 667 [P_GMII_NOT_1GBIT] = 1, 668 }; 669 670 static const u32 lan937x_masks[] = { 671 [ALU_STAT_WRITE] = 1, 672 [ALU_STAT_READ] = 2, 673 [P_MII_TX_FLOW_CTRL] = BIT(5), 674 [P_MII_RX_FLOW_CTRL] = BIT(3), 675 }; 676 677 static const u8 lan937x_shifts[] = { 678 [ALU_STAT_INDEX] = 8, 679 }; 680 681 static const struct regmap_range ksz8563_valid_regs[] = { 682 regmap_reg_range(0x0000, 0x0003), 683 regmap_reg_range(0x0006, 0x0006), 684 regmap_reg_range(0x000f, 0x001f), 685 regmap_reg_range(0x0100, 0x0100), 686 regmap_reg_range(0x0104, 0x0107), 687 regmap_reg_range(0x010d, 0x010d), 688 regmap_reg_range(0x0110, 0x0113), 689 regmap_reg_range(0x0120, 0x012b), 690 regmap_reg_range(0x0201, 0x0201), 691 regmap_reg_range(0x0210, 0x0213), 692 regmap_reg_range(0x0300, 0x0300), 693 regmap_reg_range(0x0302, 0x031b), 694 regmap_reg_range(0x0320, 0x032b), 695 regmap_reg_range(0x0330, 0x0336), 696 regmap_reg_range(0x0338, 0x033e), 697 regmap_reg_range(0x0340, 0x035f), 698 regmap_reg_range(0x0370, 0x0370), 699 regmap_reg_range(0x0378, 0x0378), 700 regmap_reg_range(0x037c, 0x037d), 701 regmap_reg_range(0x0390, 0x0393), 702 regmap_reg_range(0x0400, 0x040e), 703 regmap_reg_range(0x0410, 0x042f), 704 regmap_reg_range(0x0500, 0x0519), 705 regmap_reg_range(0x0520, 0x054b), 706 regmap_reg_range(0x0550, 0x05b3), 707 708 /* port 1 */ 709 regmap_reg_range(0x1000, 0x1001), 710 regmap_reg_range(0x1004, 0x100b), 711 regmap_reg_range(0x1013, 0x1013), 712 regmap_reg_range(0x1017, 0x1017), 713 regmap_reg_range(0x101b, 0x101b), 714 regmap_reg_range(0x101f, 0x1021), 715 regmap_reg_range(0x1030, 0x1030), 716 regmap_reg_range(0x1100, 0x1111), 717 regmap_reg_range(0x111a, 0x111d), 718 regmap_reg_range(0x1122, 0x1127), 719 regmap_reg_range(0x112a, 0x112b), 720 regmap_reg_range(0x1136, 0x1139), 721 regmap_reg_range(0x113e, 0x113f), 722 regmap_reg_range(0x1400, 0x1401), 723 regmap_reg_range(0x1403, 0x1403), 724 regmap_reg_range(0x1410, 0x1417), 725 regmap_reg_range(0x1420, 0x1423), 726 regmap_reg_range(0x1500, 0x1507), 727 regmap_reg_range(0x1600, 0x1612), 728 regmap_reg_range(0x1800, 0x180f), 729 regmap_reg_range(0x1900, 0x1907), 730 regmap_reg_range(0x1914, 0x191b), 731 regmap_reg_range(0x1a00, 0x1a03), 732 regmap_reg_range(0x1a04, 0x1a08), 733 regmap_reg_range(0x1b00, 0x1b01), 734 regmap_reg_range(0x1b04, 0x1b04), 735 regmap_reg_range(0x1c00, 0x1c05), 736 regmap_reg_range(0x1c08, 0x1c1b), 737 738 /* port 2 */ 739 regmap_reg_range(0x2000, 0x2001), 740 regmap_reg_range(0x2004, 0x200b), 741 regmap_reg_range(0x2013, 0x2013), 742 regmap_reg_range(0x2017, 0x2017), 743 regmap_reg_range(0x201b, 0x201b), 744 regmap_reg_range(0x201f, 0x2021), 745 regmap_reg_range(0x2030, 0x2030), 746 regmap_reg_range(0x2100, 0x2111), 747 regmap_reg_range(0x211a, 0x211d), 748 regmap_reg_range(0x2122, 0x2127), 749 regmap_reg_range(0x212a, 0x212b), 750 regmap_reg_range(0x2136, 0x2139), 751 regmap_reg_range(0x213e, 0x213f), 752 regmap_reg_range(0x2400, 0x2401), 753 regmap_reg_range(0x2403, 0x2403), 754 regmap_reg_range(0x2410, 0x2417), 755 regmap_reg_range(0x2420, 0x2423), 756 regmap_reg_range(0x2500, 0x2507), 757 regmap_reg_range(0x2600, 0x2612), 758 regmap_reg_range(0x2800, 0x280f), 759 regmap_reg_range(0x2900, 0x2907), 760 regmap_reg_range(0x2914, 0x291b), 761 regmap_reg_range(0x2a00, 0x2a03), 762 regmap_reg_range(0x2a04, 0x2a08), 763 regmap_reg_range(0x2b00, 0x2b01), 764 regmap_reg_range(0x2b04, 0x2b04), 765 regmap_reg_range(0x2c00, 0x2c05), 766 regmap_reg_range(0x2c08, 0x2c1b), 767 768 /* port 3 */ 769 regmap_reg_range(0x3000, 0x3001), 770 regmap_reg_range(0x3004, 0x300b), 771 regmap_reg_range(0x3013, 0x3013), 772 regmap_reg_range(0x3017, 0x3017), 773 regmap_reg_range(0x301b, 0x301b), 774 regmap_reg_range(0x301f, 0x3021), 775 regmap_reg_range(0x3030, 0x3030), 776 regmap_reg_range(0x3300, 0x3301), 777 regmap_reg_range(0x3303, 0x3303), 778 regmap_reg_range(0x3400, 0x3401), 779 regmap_reg_range(0x3403, 0x3403), 780 regmap_reg_range(0x3410, 0x3417), 781 regmap_reg_range(0x3420, 0x3423), 782 regmap_reg_range(0x3500, 0x3507), 783 regmap_reg_range(0x3600, 0x3612), 784 regmap_reg_range(0x3800, 0x380f), 785 regmap_reg_range(0x3900, 0x3907), 786 regmap_reg_range(0x3914, 0x391b), 787 regmap_reg_range(0x3a00, 0x3a03), 788 regmap_reg_range(0x3a04, 0x3a08), 789 regmap_reg_range(0x3b00, 0x3b01), 790 regmap_reg_range(0x3b04, 0x3b04), 791 regmap_reg_range(0x3c00, 0x3c05), 792 regmap_reg_range(0x3c08, 0x3c1b), 793 }; 794 795 static const struct regmap_access_table ksz8563_register_set = { 796 .yes_ranges = ksz8563_valid_regs, 797 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 798 }; 799 800 static const struct regmap_range ksz9477_valid_regs[] = { 801 regmap_reg_range(0x0000, 0x0003), 802 regmap_reg_range(0x0006, 0x0006), 803 regmap_reg_range(0x0010, 0x001f), 804 regmap_reg_range(0x0100, 0x0100), 805 regmap_reg_range(0x0103, 0x0107), 806 regmap_reg_range(0x010d, 0x010d), 807 regmap_reg_range(0x0110, 0x0113), 808 regmap_reg_range(0x0120, 0x012b), 809 regmap_reg_range(0x0201, 0x0201), 810 regmap_reg_range(0x0210, 0x0213), 811 regmap_reg_range(0x0300, 0x0300), 812 regmap_reg_range(0x0302, 0x031b), 813 regmap_reg_range(0x0320, 0x032b), 814 regmap_reg_range(0x0330, 0x0336), 815 regmap_reg_range(0x0338, 0x033b), 816 regmap_reg_range(0x033e, 0x033e), 817 regmap_reg_range(0x0340, 0x035f), 818 regmap_reg_range(0x0370, 0x0370), 819 regmap_reg_range(0x0378, 0x0378), 820 regmap_reg_range(0x037c, 0x037d), 821 regmap_reg_range(0x0390, 0x0393), 822 regmap_reg_range(0x0400, 0x040e), 823 regmap_reg_range(0x0410, 0x042f), 824 regmap_reg_range(0x0444, 0x044b), 825 regmap_reg_range(0x0450, 0x046f), 826 regmap_reg_range(0x0500, 0x0519), 827 regmap_reg_range(0x0520, 0x054b), 828 regmap_reg_range(0x0550, 0x05b3), 829 regmap_reg_range(0x0604, 0x060b), 830 regmap_reg_range(0x0610, 0x0612), 831 regmap_reg_range(0x0614, 0x062c), 832 regmap_reg_range(0x0640, 0x0645), 833 regmap_reg_range(0x0648, 0x064d), 834 835 /* port 1 */ 836 regmap_reg_range(0x1000, 0x1001), 837 regmap_reg_range(0x1013, 0x1013), 838 regmap_reg_range(0x1017, 0x1017), 839 regmap_reg_range(0x101b, 0x101b), 840 regmap_reg_range(0x101f, 0x1020), 841 regmap_reg_range(0x1030, 0x1030), 842 regmap_reg_range(0x1100, 0x1115), 843 regmap_reg_range(0x111a, 0x111f), 844 regmap_reg_range(0x1120, 0x112b), 845 regmap_reg_range(0x1134, 0x113b), 846 regmap_reg_range(0x113c, 0x113f), 847 regmap_reg_range(0x1400, 0x1401), 848 regmap_reg_range(0x1403, 0x1403), 849 regmap_reg_range(0x1410, 0x1417), 850 regmap_reg_range(0x1420, 0x1423), 851 regmap_reg_range(0x1500, 0x1507), 852 regmap_reg_range(0x1600, 0x1613), 853 regmap_reg_range(0x1800, 0x180f), 854 regmap_reg_range(0x1820, 0x1827), 855 regmap_reg_range(0x1830, 0x1837), 856 regmap_reg_range(0x1840, 0x184b), 857 regmap_reg_range(0x1900, 0x1907), 858 regmap_reg_range(0x1914, 0x191b), 859 regmap_reg_range(0x1920, 0x1920), 860 regmap_reg_range(0x1923, 0x1927), 861 regmap_reg_range(0x1a00, 0x1a03), 862 regmap_reg_range(0x1a04, 0x1a07), 863 regmap_reg_range(0x1b00, 0x1b01), 864 regmap_reg_range(0x1b04, 0x1b04), 865 regmap_reg_range(0x1c00, 0x1c05), 866 regmap_reg_range(0x1c08, 0x1c1b), 867 868 /* port 2 */ 869 regmap_reg_range(0x2000, 0x2001), 870 regmap_reg_range(0x2013, 0x2013), 871 regmap_reg_range(0x2017, 0x2017), 872 regmap_reg_range(0x201b, 0x201b), 873 regmap_reg_range(0x201f, 0x2020), 874 regmap_reg_range(0x2030, 0x2030), 875 regmap_reg_range(0x2100, 0x2115), 876 regmap_reg_range(0x211a, 0x211f), 877 regmap_reg_range(0x2120, 0x212b), 878 regmap_reg_range(0x2134, 0x213b), 879 regmap_reg_range(0x213c, 0x213f), 880 regmap_reg_range(0x2400, 0x2401), 881 regmap_reg_range(0x2403, 0x2403), 882 regmap_reg_range(0x2410, 0x2417), 883 regmap_reg_range(0x2420, 0x2423), 884 regmap_reg_range(0x2500, 0x2507), 885 regmap_reg_range(0x2600, 0x2613), 886 regmap_reg_range(0x2800, 0x280f), 887 regmap_reg_range(0x2820, 0x2827), 888 regmap_reg_range(0x2830, 0x2837), 889 regmap_reg_range(0x2840, 0x284b), 890 regmap_reg_range(0x2900, 0x2907), 891 regmap_reg_range(0x2914, 0x291b), 892 regmap_reg_range(0x2920, 0x2920), 893 regmap_reg_range(0x2923, 0x2927), 894 regmap_reg_range(0x2a00, 0x2a03), 895 regmap_reg_range(0x2a04, 0x2a07), 896 regmap_reg_range(0x2b00, 0x2b01), 897 regmap_reg_range(0x2b04, 0x2b04), 898 regmap_reg_range(0x2c00, 0x2c05), 899 regmap_reg_range(0x2c08, 0x2c1b), 900 901 /* port 3 */ 902 regmap_reg_range(0x3000, 0x3001), 903 regmap_reg_range(0x3013, 0x3013), 904 regmap_reg_range(0x3017, 0x3017), 905 regmap_reg_range(0x301b, 0x301b), 906 regmap_reg_range(0x301f, 0x3020), 907 regmap_reg_range(0x3030, 0x3030), 908 regmap_reg_range(0x3100, 0x3115), 909 regmap_reg_range(0x311a, 0x311f), 910 regmap_reg_range(0x3120, 0x312b), 911 regmap_reg_range(0x3134, 0x313b), 912 regmap_reg_range(0x313c, 0x313f), 913 regmap_reg_range(0x3400, 0x3401), 914 regmap_reg_range(0x3403, 0x3403), 915 regmap_reg_range(0x3410, 0x3417), 916 regmap_reg_range(0x3420, 0x3423), 917 regmap_reg_range(0x3500, 0x3507), 918 regmap_reg_range(0x3600, 0x3613), 919 regmap_reg_range(0x3800, 0x380f), 920 regmap_reg_range(0x3820, 0x3827), 921 regmap_reg_range(0x3830, 0x3837), 922 regmap_reg_range(0x3840, 0x384b), 923 regmap_reg_range(0x3900, 0x3907), 924 regmap_reg_range(0x3914, 0x391b), 925 regmap_reg_range(0x3920, 0x3920), 926 regmap_reg_range(0x3923, 0x3927), 927 regmap_reg_range(0x3a00, 0x3a03), 928 regmap_reg_range(0x3a04, 0x3a07), 929 regmap_reg_range(0x3b00, 0x3b01), 930 regmap_reg_range(0x3b04, 0x3b04), 931 regmap_reg_range(0x3c00, 0x3c05), 932 regmap_reg_range(0x3c08, 0x3c1b), 933 934 /* port 4 */ 935 regmap_reg_range(0x4000, 0x4001), 936 regmap_reg_range(0x4013, 0x4013), 937 regmap_reg_range(0x4017, 0x4017), 938 regmap_reg_range(0x401b, 0x401b), 939 regmap_reg_range(0x401f, 0x4020), 940 regmap_reg_range(0x4030, 0x4030), 941 regmap_reg_range(0x4100, 0x4115), 942 regmap_reg_range(0x411a, 0x411f), 943 regmap_reg_range(0x4120, 0x412b), 944 regmap_reg_range(0x4134, 0x413b), 945 regmap_reg_range(0x413c, 0x413f), 946 regmap_reg_range(0x4400, 0x4401), 947 regmap_reg_range(0x4403, 0x4403), 948 regmap_reg_range(0x4410, 0x4417), 949 regmap_reg_range(0x4420, 0x4423), 950 regmap_reg_range(0x4500, 0x4507), 951 regmap_reg_range(0x4600, 0x4613), 952 regmap_reg_range(0x4800, 0x480f), 953 regmap_reg_range(0x4820, 0x4827), 954 regmap_reg_range(0x4830, 0x4837), 955 regmap_reg_range(0x4840, 0x484b), 956 regmap_reg_range(0x4900, 0x4907), 957 regmap_reg_range(0x4914, 0x491b), 958 regmap_reg_range(0x4920, 0x4920), 959 regmap_reg_range(0x4923, 0x4927), 960 regmap_reg_range(0x4a00, 0x4a03), 961 regmap_reg_range(0x4a04, 0x4a07), 962 regmap_reg_range(0x4b00, 0x4b01), 963 regmap_reg_range(0x4b04, 0x4b04), 964 regmap_reg_range(0x4c00, 0x4c05), 965 regmap_reg_range(0x4c08, 0x4c1b), 966 967 /* port 5 */ 968 regmap_reg_range(0x5000, 0x5001), 969 regmap_reg_range(0x5013, 0x5013), 970 regmap_reg_range(0x5017, 0x5017), 971 regmap_reg_range(0x501b, 0x501b), 972 regmap_reg_range(0x501f, 0x5020), 973 regmap_reg_range(0x5030, 0x5030), 974 regmap_reg_range(0x5100, 0x5115), 975 regmap_reg_range(0x511a, 0x511f), 976 regmap_reg_range(0x5120, 0x512b), 977 regmap_reg_range(0x5134, 0x513b), 978 regmap_reg_range(0x513c, 0x513f), 979 regmap_reg_range(0x5400, 0x5401), 980 regmap_reg_range(0x5403, 0x5403), 981 regmap_reg_range(0x5410, 0x5417), 982 regmap_reg_range(0x5420, 0x5423), 983 regmap_reg_range(0x5500, 0x5507), 984 regmap_reg_range(0x5600, 0x5613), 985 regmap_reg_range(0x5800, 0x580f), 986 regmap_reg_range(0x5820, 0x5827), 987 regmap_reg_range(0x5830, 0x5837), 988 regmap_reg_range(0x5840, 0x584b), 989 regmap_reg_range(0x5900, 0x5907), 990 regmap_reg_range(0x5914, 0x591b), 991 regmap_reg_range(0x5920, 0x5920), 992 regmap_reg_range(0x5923, 0x5927), 993 regmap_reg_range(0x5a00, 0x5a03), 994 regmap_reg_range(0x5a04, 0x5a07), 995 regmap_reg_range(0x5b00, 0x5b01), 996 regmap_reg_range(0x5b04, 0x5b04), 997 regmap_reg_range(0x5c00, 0x5c05), 998 regmap_reg_range(0x5c08, 0x5c1b), 999 1000 /* port 6 */ 1001 regmap_reg_range(0x6000, 0x6001), 1002 regmap_reg_range(0x6013, 0x6013), 1003 regmap_reg_range(0x6017, 0x6017), 1004 regmap_reg_range(0x601b, 0x601b), 1005 regmap_reg_range(0x601f, 0x6020), 1006 regmap_reg_range(0x6030, 0x6030), 1007 regmap_reg_range(0x6300, 0x6301), 1008 regmap_reg_range(0x6400, 0x6401), 1009 regmap_reg_range(0x6403, 0x6403), 1010 regmap_reg_range(0x6410, 0x6417), 1011 regmap_reg_range(0x6420, 0x6423), 1012 regmap_reg_range(0x6500, 0x6507), 1013 regmap_reg_range(0x6600, 0x6613), 1014 regmap_reg_range(0x6800, 0x680f), 1015 regmap_reg_range(0x6820, 0x6827), 1016 regmap_reg_range(0x6830, 0x6837), 1017 regmap_reg_range(0x6840, 0x684b), 1018 regmap_reg_range(0x6900, 0x6907), 1019 regmap_reg_range(0x6914, 0x691b), 1020 regmap_reg_range(0x6920, 0x6920), 1021 regmap_reg_range(0x6923, 0x6927), 1022 regmap_reg_range(0x6a00, 0x6a03), 1023 regmap_reg_range(0x6a04, 0x6a07), 1024 regmap_reg_range(0x6b00, 0x6b01), 1025 regmap_reg_range(0x6b04, 0x6b04), 1026 regmap_reg_range(0x6c00, 0x6c05), 1027 regmap_reg_range(0x6c08, 0x6c1b), 1028 1029 /* port 7 */ 1030 regmap_reg_range(0x7000, 0x7001), 1031 regmap_reg_range(0x7013, 0x7013), 1032 regmap_reg_range(0x7017, 0x7017), 1033 regmap_reg_range(0x701b, 0x701b), 1034 regmap_reg_range(0x701f, 0x7020), 1035 regmap_reg_range(0x7030, 0x7030), 1036 regmap_reg_range(0x7200, 0x7203), 1037 regmap_reg_range(0x7206, 0x7207), 1038 regmap_reg_range(0x7300, 0x7301), 1039 regmap_reg_range(0x7400, 0x7401), 1040 regmap_reg_range(0x7403, 0x7403), 1041 regmap_reg_range(0x7410, 0x7417), 1042 regmap_reg_range(0x7420, 0x7423), 1043 regmap_reg_range(0x7500, 0x7507), 1044 regmap_reg_range(0x7600, 0x7613), 1045 regmap_reg_range(0x7800, 0x780f), 1046 regmap_reg_range(0x7820, 0x7827), 1047 regmap_reg_range(0x7830, 0x7837), 1048 regmap_reg_range(0x7840, 0x784b), 1049 regmap_reg_range(0x7900, 0x7907), 1050 regmap_reg_range(0x7914, 0x791b), 1051 regmap_reg_range(0x7920, 0x7920), 1052 regmap_reg_range(0x7923, 0x7927), 1053 regmap_reg_range(0x7a00, 0x7a03), 1054 regmap_reg_range(0x7a04, 0x7a07), 1055 regmap_reg_range(0x7b00, 0x7b01), 1056 regmap_reg_range(0x7b04, 0x7b04), 1057 regmap_reg_range(0x7c00, 0x7c05), 1058 regmap_reg_range(0x7c08, 0x7c1b), 1059 }; 1060 1061 static const struct regmap_access_table ksz9477_register_set = { 1062 .yes_ranges = ksz9477_valid_regs, 1063 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 1064 }; 1065 1066 static const struct regmap_range ksz9896_valid_regs[] = { 1067 regmap_reg_range(0x0000, 0x0003), 1068 regmap_reg_range(0x0006, 0x0006), 1069 regmap_reg_range(0x0010, 0x001f), 1070 regmap_reg_range(0x0100, 0x0100), 1071 regmap_reg_range(0x0103, 0x0107), 1072 regmap_reg_range(0x010d, 0x010d), 1073 regmap_reg_range(0x0110, 0x0113), 1074 regmap_reg_range(0x0120, 0x0127), 1075 regmap_reg_range(0x0201, 0x0201), 1076 regmap_reg_range(0x0210, 0x0213), 1077 regmap_reg_range(0x0300, 0x0300), 1078 regmap_reg_range(0x0302, 0x030b), 1079 regmap_reg_range(0x0310, 0x031b), 1080 regmap_reg_range(0x0320, 0x032b), 1081 regmap_reg_range(0x0330, 0x0336), 1082 regmap_reg_range(0x0338, 0x033b), 1083 regmap_reg_range(0x033e, 0x033e), 1084 regmap_reg_range(0x0340, 0x035f), 1085 regmap_reg_range(0x0370, 0x0370), 1086 regmap_reg_range(0x0378, 0x0378), 1087 regmap_reg_range(0x037c, 0x037d), 1088 regmap_reg_range(0x0390, 0x0393), 1089 regmap_reg_range(0x0400, 0x040e), 1090 regmap_reg_range(0x0410, 0x042f), 1091 1092 /* port 1 */ 1093 regmap_reg_range(0x1000, 0x1001), 1094 regmap_reg_range(0x1013, 0x1013), 1095 regmap_reg_range(0x1017, 0x1017), 1096 regmap_reg_range(0x101b, 0x101b), 1097 regmap_reg_range(0x101f, 0x1020), 1098 regmap_reg_range(0x1030, 0x1030), 1099 regmap_reg_range(0x1100, 0x1115), 1100 regmap_reg_range(0x111a, 0x111f), 1101 regmap_reg_range(0x1122, 0x1127), 1102 regmap_reg_range(0x112a, 0x112b), 1103 regmap_reg_range(0x1136, 0x1139), 1104 regmap_reg_range(0x113e, 0x113f), 1105 regmap_reg_range(0x1400, 0x1401), 1106 regmap_reg_range(0x1403, 0x1403), 1107 regmap_reg_range(0x1410, 0x1417), 1108 regmap_reg_range(0x1420, 0x1423), 1109 regmap_reg_range(0x1500, 0x1507), 1110 regmap_reg_range(0x1600, 0x1612), 1111 regmap_reg_range(0x1800, 0x180f), 1112 regmap_reg_range(0x1820, 0x1827), 1113 regmap_reg_range(0x1830, 0x1837), 1114 regmap_reg_range(0x1840, 0x184b), 1115 regmap_reg_range(0x1900, 0x1907), 1116 regmap_reg_range(0x1914, 0x1915), 1117 regmap_reg_range(0x1a00, 0x1a03), 1118 regmap_reg_range(0x1a04, 0x1a07), 1119 regmap_reg_range(0x1b00, 0x1b01), 1120 regmap_reg_range(0x1b04, 0x1b04), 1121 1122 /* port 2 */ 1123 regmap_reg_range(0x2000, 0x2001), 1124 regmap_reg_range(0x2013, 0x2013), 1125 regmap_reg_range(0x2017, 0x2017), 1126 regmap_reg_range(0x201b, 0x201b), 1127 regmap_reg_range(0x201f, 0x2020), 1128 regmap_reg_range(0x2030, 0x2030), 1129 regmap_reg_range(0x2100, 0x2115), 1130 regmap_reg_range(0x211a, 0x211f), 1131 regmap_reg_range(0x2122, 0x2127), 1132 regmap_reg_range(0x212a, 0x212b), 1133 regmap_reg_range(0x2136, 0x2139), 1134 regmap_reg_range(0x213e, 0x213f), 1135 regmap_reg_range(0x2400, 0x2401), 1136 regmap_reg_range(0x2403, 0x2403), 1137 regmap_reg_range(0x2410, 0x2417), 1138 regmap_reg_range(0x2420, 0x2423), 1139 regmap_reg_range(0x2500, 0x2507), 1140 regmap_reg_range(0x2600, 0x2612), 1141 regmap_reg_range(0x2800, 0x280f), 1142 regmap_reg_range(0x2820, 0x2827), 1143 regmap_reg_range(0x2830, 0x2837), 1144 regmap_reg_range(0x2840, 0x284b), 1145 regmap_reg_range(0x2900, 0x2907), 1146 regmap_reg_range(0x2914, 0x2915), 1147 regmap_reg_range(0x2a00, 0x2a03), 1148 regmap_reg_range(0x2a04, 0x2a07), 1149 regmap_reg_range(0x2b00, 0x2b01), 1150 regmap_reg_range(0x2b04, 0x2b04), 1151 1152 /* port 3 */ 1153 regmap_reg_range(0x3000, 0x3001), 1154 regmap_reg_range(0x3013, 0x3013), 1155 regmap_reg_range(0x3017, 0x3017), 1156 regmap_reg_range(0x301b, 0x301b), 1157 regmap_reg_range(0x301f, 0x3020), 1158 regmap_reg_range(0x3030, 0x3030), 1159 regmap_reg_range(0x3100, 0x3115), 1160 regmap_reg_range(0x311a, 0x311f), 1161 regmap_reg_range(0x3122, 0x3127), 1162 regmap_reg_range(0x312a, 0x312b), 1163 regmap_reg_range(0x3136, 0x3139), 1164 regmap_reg_range(0x313e, 0x313f), 1165 regmap_reg_range(0x3400, 0x3401), 1166 regmap_reg_range(0x3403, 0x3403), 1167 regmap_reg_range(0x3410, 0x3417), 1168 regmap_reg_range(0x3420, 0x3423), 1169 regmap_reg_range(0x3500, 0x3507), 1170 regmap_reg_range(0x3600, 0x3612), 1171 regmap_reg_range(0x3800, 0x380f), 1172 regmap_reg_range(0x3820, 0x3827), 1173 regmap_reg_range(0x3830, 0x3837), 1174 regmap_reg_range(0x3840, 0x384b), 1175 regmap_reg_range(0x3900, 0x3907), 1176 regmap_reg_range(0x3914, 0x3915), 1177 regmap_reg_range(0x3a00, 0x3a03), 1178 regmap_reg_range(0x3a04, 0x3a07), 1179 regmap_reg_range(0x3b00, 0x3b01), 1180 regmap_reg_range(0x3b04, 0x3b04), 1181 1182 /* port 4 */ 1183 regmap_reg_range(0x4000, 0x4001), 1184 regmap_reg_range(0x4013, 0x4013), 1185 regmap_reg_range(0x4017, 0x4017), 1186 regmap_reg_range(0x401b, 0x401b), 1187 regmap_reg_range(0x401f, 0x4020), 1188 regmap_reg_range(0x4030, 0x4030), 1189 regmap_reg_range(0x4100, 0x4115), 1190 regmap_reg_range(0x411a, 0x411f), 1191 regmap_reg_range(0x4122, 0x4127), 1192 regmap_reg_range(0x412a, 0x412b), 1193 regmap_reg_range(0x4136, 0x4139), 1194 regmap_reg_range(0x413e, 0x413f), 1195 regmap_reg_range(0x4400, 0x4401), 1196 regmap_reg_range(0x4403, 0x4403), 1197 regmap_reg_range(0x4410, 0x4417), 1198 regmap_reg_range(0x4420, 0x4423), 1199 regmap_reg_range(0x4500, 0x4507), 1200 regmap_reg_range(0x4600, 0x4612), 1201 regmap_reg_range(0x4800, 0x480f), 1202 regmap_reg_range(0x4820, 0x4827), 1203 regmap_reg_range(0x4830, 0x4837), 1204 regmap_reg_range(0x4840, 0x484b), 1205 regmap_reg_range(0x4900, 0x4907), 1206 regmap_reg_range(0x4914, 0x4915), 1207 regmap_reg_range(0x4a00, 0x4a03), 1208 regmap_reg_range(0x4a04, 0x4a07), 1209 regmap_reg_range(0x4b00, 0x4b01), 1210 regmap_reg_range(0x4b04, 0x4b04), 1211 1212 /* port 5 */ 1213 regmap_reg_range(0x5000, 0x5001), 1214 regmap_reg_range(0x5013, 0x5013), 1215 regmap_reg_range(0x5017, 0x5017), 1216 regmap_reg_range(0x501b, 0x501b), 1217 regmap_reg_range(0x501f, 0x5020), 1218 regmap_reg_range(0x5030, 0x5030), 1219 regmap_reg_range(0x5100, 0x5115), 1220 regmap_reg_range(0x511a, 0x511f), 1221 regmap_reg_range(0x5122, 0x5127), 1222 regmap_reg_range(0x512a, 0x512b), 1223 regmap_reg_range(0x5136, 0x5139), 1224 regmap_reg_range(0x513e, 0x513f), 1225 regmap_reg_range(0x5400, 0x5401), 1226 regmap_reg_range(0x5403, 0x5403), 1227 regmap_reg_range(0x5410, 0x5417), 1228 regmap_reg_range(0x5420, 0x5423), 1229 regmap_reg_range(0x5500, 0x5507), 1230 regmap_reg_range(0x5600, 0x5612), 1231 regmap_reg_range(0x5800, 0x580f), 1232 regmap_reg_range(0x5820, 0x5827), 1233 regmap_reg_range(0x5830, 0x5837), 1234 regmap_reg_range(0x5840, 0x584b), 1235 regmap_reg_range(0x5900, 0x5907), 1236 regmap_reg_range(0x5914, 0x5915), 1237 regmap_reg_range(0x5a00, 0x5a03), 1238 regmap_reg_range(0x5a04, 0x5a07), 1239 regmap_reg_range(0x5b00, 0x5b01), 1240 regmap_reg_range(0x5b04, 0x5b04), 1241 1242 /* port 6 */ 1243 regmap_reg_range(0x6000, 0x6001), 1244 regmap_reg_range(0x6013, 0x6013), 1245 regmap_reg_range(0x6017, 0x6017), 1246 regmap_reg_range(0x601b, 0x601b), 1247 regmap_reg_range(0x601f, 0x6020), 1248 regmap_reg_range(0x6030, 0x6030), 1249 regmap_reg_range(0x6100, 0x6115), 1250 regmap_reg_range(0x611a, 0x611f), 1251 regmap_reg_range(0x6122, 0x6127), 1252 regmap_reg_range(0x612a, 0x612b), 1253 regmap_reg_range(0x6136, 0x6139), 1254 regmap_reg_range(0x613e, 0x613f), 1255 regmap_reg_range(0x6300, 0x6301), 1256 regmap_reg_range(0x6400, 0x6401), 1257 regmap_reg_range(0x6403, 0x6403), 1258 regmap_reg_range(0x6410, 0x6417), 1259 regmap_reg_range(0x6420, 0x6423), 1260 regmap_reg_range(0x6500, 0x6507), 1261 regmap_reg_range(0x6600, 0x6612), 1262 regmap_reg_range(0x6800, 0x680f), 1263 regmap_reg_range(0x6820, 0x6827), 1264 regmap_reg_range(0x6830, 0x6837), 1265 regmap_reg_range(0x6840, 0x684b), 1266 regmap_reg_range(0x6900, 0x6907), 1267 regmap_reg_range(0x6914, 0x6915), 1268 regmap_reg_range(0x6a00, 0x6a03), 1269 regmap_reg_range(0x6a04, 0x6a07), 1270 regmap_reg_range(0x6b00, 0x6b01), 1271 regmap_reg_range(0x6b04, 0x6b04), 1272 }; 1273 1274 static const struct regmap_access_table ksz9896_register_set = { 1275 .yes_ranges = ksz9896_valid_regs, 1276 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1277 }; 1278 1279 static const struct regmap_range ksz8873_valid_regs[] = { 1280 regmap_reg_range(0x00, 0x01), 1281 /* global control register */ 1282 regmap_reg_range(0x02, 0x0f), 1283 1284 /* port registers */ 1285 regmap_reg_range(0x10, 0x1d), 1286 regmap_reg_range(0x1e, 0x1f), 1287 regmap_reg_range(0x20, 0x2d), 1288 regmap_reg_range(0x2e, 0x2f), 1289 regmap_reg_range(0x30, 0x39), 1290 regmap_reg_range(0x3f, 0x3f), 1291 1292 /* advanced control registers */ 1293 regmap_reg_range(0x60, 0x6f), 1294 regmap_reg_range(0x70, 0x75), 1295 regmap_reg_range(0x76, 0x78), 1296 regmap_reg_range(0x79, 0x7a), 1297 regmap_reg_range(0x7b, 0x83), 1298 regmap_reg_range(0x8e, 0x99), 1299 regmap_reg_range(0x9a, 0xa5), 1300 regmap_reg_range(0xa6, 0xa6), 1301 regmap_reg_range(0xa7, 0xaa), 1302 regmap_reg_range(0xab, 0xae), 1303 regmap_reg_range(0xaf, 0xba), 1304 regmap_reg_range(0xbb, 0xbc), 1305 regmap_reg_range(0xbd, 0xbd), 1306 regmap_reg_range(0xc0, 0xc0), 1307 regmap_reg_range(0xc2, 0xc2), 1308 regmap_reg_range(0xc3, 0xc3), 1309 regmap_reg_range(0xc4, 0xc4), 1310 regmap_reg_range(0xc6, 0xc6), 1311 }; 1312 1313 static const struct regmap_access_table ksz8873_register_set = { 1314 .yes_ranges = ksz8873_valid_regs, 1315 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), 1316 }; 1317 1318 const struct ksz_chip_data ksz_switch_chips[] = { 1319 [KSZ8563] = { 1320 .chip_id = KSZ8563_CHIP_ID, 1321 .dev_name = "KSZ8563", 1322 .num_vlans = 4096, 1323 .num_alus = 4096, 1324 .num_statics = 16, 1325 .cpu_ports = 0x07, /* can be configured as cpu port */ 1326 .port_cnt = 3, /* total port count */ 1327 .port_nirqs = 3, 1328 .num_tx_queues = 4, 1329 .num_ipms = 8, 1330 .tc_cbs_supported = true, 1331 .ops = &ksz9477_dev_ops, 1332 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1333 .mib_names = ksz9477_mib_names, 1334 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1335 .reg_mib_cnt = MIB_COUNTER_NUM, 1336 .regs = ksz9477_regs, 1337 .masks = ksz9477_masks, 1338 .shifts = ksz9477_shifts, 1339 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1340 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1341 .supports_mii = {false, false, true}, 1342 .supports_rmii = {false, false, true}, 1343 .supports_rgmii = {false, false, true}, 1344 .internal_phy = {true, true, false}, 1345 .gbit_capable = {false, false, true}, 1346 .wr_table = &ksz8563_register_set, 1347 .rd_table = &ksz8563_register_set, 1348 }, 1349 1350 [KSZ8795] = { 1351 .chip_id = KSZ8795_CHIP_ID, 1352 .dev_name = "KSZ8795", 1353 .num_vlans = 4096, 1354 .num_alus = 0, 1355 .num_statics = 32, 1356 .cpu_ports = 0x10, /* can be configured as cpu port */ 1357 .port_cnt = 5, /* total cpu and user ports */ 1358 .num_tx_queues = 4, 1359 .num_ipms = 4, 1360 .ops = &ksz87xx_dev_ops, 1361 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1362 .ksz87xx_eee_link_erratum = true, 1363 .mib_names = ksz9477_mib_names, 1364 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1365 .reg_mib_cnt = MIB_COUNTER_NUM, 1366 .regs = ksz8795_regs, 1367 .masks = ksz8795_masks, 1368 .shifts = ksz8795_shifts, 1369 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1370 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1371 .supports_mii = {false, false, false, false, true}, 1372 .supports_rmii = {false, false, false, false, true}, 1373 .supports_rgmii = {false, false, false, false, true}, 1374 .internal_phy = {true, true, true, true, false}, 1375 }, 1376 1377 [KSZ8794] = { 1378 /* WARNING 1379 * ======= 1380 * KSZ8794 is similar to KSZ8795, except the port map 1381 * contains a gap between external and CPU ports, the 1382 * port map is NOT continuous. The per-port register 1383 * map is shifted accordingly too, i.e. registers at 1384 * offset 0x40 are NOT used on KSZ8794 and they ARE 1385 * used on KSZ8795 for external port 3. 1386 * external cpu 1387 * KSZ8794 0,1,2 4 1388 * KSZ8795 0,1,2,3 4 1389 * KSZ8765 0,1,2,3 4 1390 * port_cnt is configured as 5, even though it is 4 1391 */ 1392 .chip_id = KSZ8794_CHIP_ID, 1393 .dev_name = "KSZ8794", 1394 .num_vlans = 4096, 1395 .num_alus = 0, 1396 .num_statics = 32, 1397 .cpu_ports = 0x10, /* can be configured as cpu port */ 1398 .port_cnt = 5, /* total cpu and user ports */ 1399 .num_tx_queues = 4, 1400 .num_ipms = 4, 1401 .ops = &ksz87xx_dev_ops, 1402 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1403 .ksz87xx_eee_link_erratum = true, 1404 .mib_names = ksz9477_mib_names, 1405 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1406 .reg_mib_cnt = MIB_COUNTER_NUM, 1407 .regs = ksz8795_regs, 1408 .masks = ksz8795_masks, 1409 .shifts = ksz8795_shifts, 1410 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1411 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1412 .supports_mii = {false, false, false, false, true}, 1413 .supports_rmii = {false, false, false, false, true}, 1414 .supports_rgmii = {false, false, false, false, true}, 1415 .internal_phy = {true, true, true, false, false}, 1416 }, 1417 1418 [KSZ8765] = { 1419 .chip_id = KSZ8765_CHIP_ID, 1420 .dev_name = "KSZ8765", 1421 .num_vlans = 4096, 1422 .num_alus = 0, 1423 .num_statics = 32, 1424 .cpu_ports = 0x10, /* can be configured as cpu port */ 1425 .port_cnt = 5, /* total cpu and user ports */ 1426 .num_tx_queues = 4, 1427 .num_ipms = 4, 1428 .ops = &ksz87xx_dev_ops, 1429 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1430 .ksz87xx_eee_link_erratum = true, 1431 .mib_names = ksz9477_mib_names, 1432 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1433 .reg_mib_cnt = MIB_COUNTER_NUM, 1434 .regs = ksz8795_regs, 1435 .masks = ksz8795_masks, 1436 .shifts = ksz8795_shifts, 1437 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1438 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1439 .supports_mii = {false, false, false, false, true}, 1440 .supports_rmii = {false, false, false, false, true}, 1441 .supports_rgmii = {false, false, false, false, true}, 1442 .internal_phy = {true, true, true, true, false}, 1443 }, 1444 1445 [KSZ88X3] = { 1446 .chip_id = KSZ88X3_CHIP_ID, 1447 .dev_name = "KSZ8863/KSZ8873", 1448 .num_vlans = 16, 1449 .num_alus = 0, 1450 .num_statics = 8, 1451 .cpu_ports = 0x4, /* can be configured as cpu port */ 1452 .port_cnt = 3, 1453 .num_tx_queues = 4, 1454 .num_ipms = 4, 1455 .ops = &ksz88xx_dev_ops, 1456 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1457 .mib_names = ksz88xx_mib_names, 1458 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1459 .reg_mib_cnt = MIB_COUNTER_NUM, 1460 .regs = ksz8863_regs, 1461 .masks = ksz8863_masks, 1462 .shifts = ksz8863_shifts, 1463 .supports_mii = {false, false, true}, 1464 .supports_rmii = {false, false, true}, 1465 .internal_phy = {true, true, false}, 1466 .wr_table = &ksz8873_register_set, 1467 .rd_table = &ksz8873_register_set, 1468 }, 1469 1470 [KSZ8864] = { 1471 /* WARNING 1472 * ======= 1473 * KSZ8864 is similar to KSZ8895, except the first port 1474 * does not exist. 1475 * external cpu 1476 * KSZ8864 1,2,3 4 1477 * KSZ8895 0,1,2,3 4 1478 * port_cnt is configured as 5, even though it is 4 1479 */ 1480 .chip_id = KSZ8864_CHIP_ID, 1481 .dev_name = "KSZ8864", 1482 .num_vlans = 4096, 1483 .num_alus = 0, 1484 .num_statics = 32, 1485 .cpu_ports = 0x10, /* can be configured as cpu port */ 1486 .port_cnt = 5, /* total cpu and user ports */ 1487 .num_tx_queues = 4, 1488 .num_ipms = 4, 1489 .ops = &ksz88xx_dev_ops, 1490 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1491 .mib_names = ksz88xx_mib_names, 1492 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1493 .reg_mib_cnt = MIB_COUNTER_NUM, 1494 .regs = ksz8895_regs, 1495 .masks = ksz8895_masks, 1496 .shifts = ksz8895_shifts, 1497 .supports_mii = {false, false, false, false, true}, 1498 .supports_rmii = {false, false, false, false, true}, 1499 .internal_phy = {false, true, true, true, false}, 1500 }, 1501 1502 [KSZ8895] = { 1503 .chip_id = KSZ8895_CHIP_ID, 1504 .dev_name = "KSZ8895", 1505 .num_vlans = 4096, 1506 .num_alus = 0, 1507 .num_statics = 32, 1508 .cpu_ports = 0x10, /* can be configured as cpu port */ 1509 .port_cnt = 5, /* total cpu and user ports */ 1510 .num_tx_queues = 4, 1511 .num_ipms = 4, 1512 .ops = &ksz88xx_dev_ops, 1513 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1514 .mib_names = ksz88xx_mib_names, 1515 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1516 .reg_mib_cnt = MIB_COUNTER_NUM, 1517 .regs = ksz8895_regs, 1518 .masks = ksz8895_masks, 1519 .shifts = ksz8895_shifts, 1520 .supports_mii = {false, false, false, false, true}, 1521 .supports_rmii = {false, false, false, false, true}, 1522 .internal_phy = {true, true, true, true, false}, 1523 }, 1524 1525 [KSZ9477] = { 1526 .chip_id = KSZ9477_CHIP_ID, 1527 .dev_name = "KSZ9477", 1528 .num_vlans = 4096, 1529 .num_alus = 4096, 1530 .num_statics = 16, 1531 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1532 .port_cnt = 7, /* total physical port count */ 1533 .port_nirqs = 4, 1534 .num_tx_queues = 4, 1535 .num_ipms = 8, 1536 .tc_cbs_supported = true, 1537 .ops = &ksz9477_dev_ops, 1538 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1539 .phy_errata_9477 = true, 1540 .mib_names = ksz9477_mib_names, 1541 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1542 .reg_mib_cnt = MIB_COUNTER_NUM, 1543 .regs = ksz9477_regs, 1544 .masks = ksz9477_masks, 1545 .shifts = ksz9477_shifts, 1546 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1547 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1548 .supports_mii = {false, false, false, false, 1549 false, true, false}, 1550 .supports_rmii = {false, false, false, false, 1551 false, true, false}, 1552 .supports_rgmii = {false, false, false, false, 1553 false, true, false}, 1554 .internal_phy = {true, true, true, true, 1555 true, false, false}, 1556 .gbit_capable = {true, true, true, true, true, true, true}, 1557 .wr_table = &ksz9477_register_set, 1558 .rd_table = &ksz9477_register_set, 1559 }, 1560 1561 [KSZ9896] = { 1562 .chip_id = KSZ9896_CHIP_ID, 1563 .dev_name = "KSZ9896", 1564 .num_vlans = 4096, 1565 .num_alus = 4096, 1566 .num_statics = 16, 1567 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1568 .port_cnt = 6, /* total physical port count */ 1569 .port_nirqs = 2, 1570 .num_tx_queues = 4, 1571 .num_ipms = 8, 1572 .ops = &ksz9477_dev_ops, 1573 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1574 .phy_errata_9477 = true, 1575 .mib_names = ksz9477_mib_names, 1576 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1577 .reg_mib_cnt = MIB_COUNTER_NUM, 1578 .regs = ksz9477_regs, 1579 .masks = ksz9477_masks, 1580 .shifts = ksz9477_shifts, 1581 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1582 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1583 .supports_mii = {false, false, false, false, 1584 false, true}, 1585 .supports_rmii = {false, false, false, false, 1586 false, true}, 1587 .supports_rgmii = {false, false, false, false, 1588 false, true}, 1589 .internal_phy = {true, true, true, true, 1590 true, false}, 1591 .gbit_capable = {true, true, true, true, true, true}, 1592 .wr_table = &ksz9896_register_set, 1593 .rd_table = &ksz9896_register_set, 1594 }, 1595 1596 [KSZ9897] = { 1597 .chip_id = KSZ9897_CHIP_ID, 1598 .dev_name = "KSZ9897", 1599 .num_vlans = 4096, 1600 .num_alus = 4096, 1601 .num_statics = 16, 1602 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1603 .port_cnt = 7, /* total physical port count */ 1604 .port_nirqs = 2, 1605 .num_tx_queues = 4, 1606 .num_ipms = 8, 1607 .ops = &ksz9477_dev_ops, 1608 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1609 .phy_errata_9477 = true, 1610 .mib_names = ksz9477_mib_names, 1611 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1612 .reg_mib_cnt = MIB_COUNTER_NUM, 1613 .regs = ksz9477_regs, 1614 .masks = ksz9477_masks, 1615 .shifts = ksz9477_shifts, 1616 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1617 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1618 .supports_mii = {false, false, false, false, 1619 false, true, true}, 1620 .supports_rmii = {false, false, false, false, 1621 false, true, true}, 1622 .supports_rgmii = {false, false, false, false, 1623 false, true, true}, 1624 .internal_phy = {true, true, true, true, 1625 true, false, false}, 1626 .gbit_capable = {true, true, true, true, true, true, true}, 1627 }, 1628 1629 [KSZ9893] = { 1630 .chip_id = KSZ9893_CHIP_ID, 1631 .dev_name = "KSZ9893", 1632 .num_vlans = 4096, 1633 .num_alus = 4096, 1634 .num_statics = 16, 1635 .cpu_ports = 0x07, /* can be configured as cpu port */ 1636 .port_cnt = 3, /* total port count */ 1637 .port_nirqs = 2, 1638 .num_tx_queues = 4, 1639 .num_ipms = 8, 1640 .ops = &ksz9477_dev_ops, 1641 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1642 .mib_names = ksz9477_mib_names, 1643 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1644 .reg_mib_cnt = MIB_COUNTER_NUM, 1645 .regs = ksz9477_regs, 1646 .masks = ksz9477_masks, 1647 .shifts = ksz9477_shifts, 1648 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1649 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1650 .supports_mii = {false, false, true}, 1651 .supports_rmii = {false, false, true}, 1652 .supports_rgmii = {false, false, true}, 1653 .internal_phy = {true, true, false}, 1654 .gbit_capable = {true, true, true}, 1655 }, 1656 1657 [KSZ9563] = { 1658 .chip_id = KSZ9563_CHIP_ID, 1659 .dev_name = "KSZ9563", 1660 .num_vlans = 4096, 1661 .num_alus = 4096, 1662 .num_statics = 16, 1663 .cpu_ports = 0x07, /* can be configured as cpu port */ 1664 .port_cnt = 3, /* total port count */ 1665 .port_nirqs = 3, 1666 .num_tx_queues = 4, 1667 .num_ipms = 8, 1668 .tc_cbs_supported = true, 1669 .ops = &ksz9477_dev_ops, 1670 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1671 .mib_names = ksz9477_mib_names, 1672 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1673 .reg_mib_cnt = MIB_COUNTER_NUM, 1674 .regs = ksz9477_regs, 1675 .masks = ksz9477_masks, 1676 .shifts = ksz9477_shifts, 1677 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1678 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1679 .supports_mii = {false, false, true}, 1680 .supports_rmii = {false, false, true}, 1681 .supports_rgmii = {false, false, true}, 1682 .internal_phy = {true, true, false}, 1683 .gbit_capable = {true, true, true}, 1684 }, 1685 1686 [KSZ8567] = { 1687 .chip_id = KSZ8567_CHIP_ID, 1688 .dev_name = "KSZ8567", 1689 .num_vlans = 4096, 1690 .num_alus = 4096, 1691 .num_statics = 16, 1692 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1693 .port_cnt = 7, /* total port count */ 1694 .port_nirqs = 3, 1695 .num_tx_queues = 4, 1696 .num_ipms = 8, 1697 .tc_cbs_supported = true, 1698 .ops = &ksz9477_dev_ops, 1699 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1700 .phy_errata_9477 = true, 1701 .mib_names = ksz9477_mib_names, 1702 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1703 .reg_mib_cnt = MIB_COUNTER_NUM, 1704 .regs = ksz9477_regs, 1705 .masks = ksz9477_masks, 1706 .shifts = ksz9477_shifts, 1707 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1708 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1709 .supports_mii = {false, false, false, false, 1710 false, true, true}, 1711 .supports_rmii = {false, false, false, false, 1712 false, true, true}, 1713 .supports_rgmii = {false, false, false, false, 1714 false, true, true}, 1715 .internal_phy = {true, true, true, true, 1716 true, false, false}, 1717 .gbit_capable = {false, false, false, false, false, 1718 true, true}, 1719 }, 1720 1721 [KSZ9567] = { 1722 .chip_id = KSZ9567_CHIP_ID, 1723 .dev_name = "KSZ9567", 1724 .num_vlans = 4096, 1725 .num_alus = 4096, 1726 .num_statics = 16, 1727 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1728 .port_cnt = 7, /* total physical port count */ 1729 .port_nirqs = 3, 1730 .num_tx_queues = 4, 1731 .num_ipms = 8, 1732 .tc_cbs_supported = true, 1733 .ops = &ksz9477_dev_ops, 1734 .mib_names = ksz9477_mib_names, 1735 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1736 .reg_mib_cnt = MIB_COUNTER_NUM, 1737 .regs = ksz9477_regs, 1738 .masks = ksz9477_masks, 1739 .shifts = ksz9477_shifts, 1740 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1741 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1742 .supports_mii = {false, false, false, false, 1743 false, true, true}, 1744 .supports_rmii = {false, false, false, false, 1745 false, true, true}, 1746 .supports_rgmii = {false, false, false, false, 1747 false, true, true}, 1748 .internal_phy = {true, true, true, true, 1749 true, false, false}, 1750 .gbit_capable = {true, true, true, true, true, true, true}, 1751 }, 1752 1753 [LAN9370] = { 1754 .chip_id = LAN9370_CHIP_ID, 1755 .dev_name = "LAN9370", 1756 .num_vlans = 4096, 1757 .num_alus = 1024, 1758 .num_statics = 256, 1759 .cpu_ports = 0x10, /* can be configured as cpu port */ 1760 .port_cnt = 5, /* total physical port count */ 1761 .port_nirqs = 6, 1762 .num_tx_queues = 8, 1763 .num_ipms = 8, 1764 .tc_cbs_supported = true, 1765 .ops = &lan937x_dev_ops, 1766 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1767 .mib_names = ksz9477_mib_names, 1768 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1769 .reg_mib_cnt = MIB_COUNTER_NUM, 1770 .regs = ksz9477_regs, 1771 .masks = lan937x_masks, 1772 .shifts = lan937x_shifts, 1773 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1774 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1775 .supports_mii = {false, false, false, false, true}, 1776 .supports_rmii = {false, false, false, false, true}, 1777 .supports_rgmii = {false, false, false, false, true}, 1778 .internal_phy = {true, true, true, true, false}, 1779 }, 1780 1781 [LAN9371] = { 1782 .chip_id = LAN9371_CHIP_ID, 1783 .dev_name = "LAN9371", 1784 .num_vlans = 4096, 1785 .num_alus = 1024, 1786 .num_statics = 256, 1787 .cpu_ports = 0x30, /* can be configured as cpu port */ 1788 .port_cnt = 6, /* total physical port count */ 1789 .port_nirqs = 6, 1790 .num_tx_queues = 8, 1791 .num_ipms = 8, 1792 .tc_cbs_supported = true, 1793 .ops = &lan937x_dev_ops, 1794 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1795 .mib_names = ksz9477_mib_names, 1796 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1797 .reg_mib_cnt = MIB_COUNTER_NUM, 1798 .regs = ksz9477_regs, 1799 .masks = lan937x_masks, 1800 .shifts = lan937x_shifts, 1801 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1802 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1803 .supports_mii = {false, false, false, false, true, true}, 1804 .supports_rmii = {false, false, false, false, true, true}, 1805 .supports_rgmii = {false, false, false, false, true, true}, 1806 .internal_phy = {true, true, true, true, false, false}, 1807 }, 1808 1809 [LAN9372] = { 1810 .chip_id = LAN9372_CHIP_ID, 1811 .dev_name = "LAN9372", 1812 .num_vlans = 4096, 1813 .num_alus = 1024, 1814 .num_statics = 256, 1815 .cpu_ports = 0x30, /* can be configured as cpu port */ 1816 .port_cnt = 8, /* total physical port count */ 1817 .port_nirqs = 6, 1818 .num_tx_queues = 8, 1819 .num_ipms = 8, 1820 .tc_cbs_supported = true, 1821 .ops = &lan937x_dev_ops, 1822 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1823 .mib_names = ksz9477_mib_names, 1824 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1825 .reg_mib_cnt = MIB_COUNTER_NUM, 1826 .regs = ksz9477_regs, 1827 .masks = lan937x_masks, 1828 .shifts = lan937x_shifts, 1829 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1830 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1831 .supports_mii = {false, false, false, false, 1832 true, true, false, false}, 1833 .supports_rmii = {false, false, false, false, 1834 true, true, false, false}, 1835 .supports_rgmii = {false, false, false, false, 1836 true, true, false, false}, 1837 .internal_phy = {true, true, true, true, 1838 false, false, true, true}, 1839 }, 1840 1841 [LAN9373] = { 1842 .chip_id = LAN9373_CHIP_ID, 1843 .dev_name = "LAN9373", 1844 .num_vlans = 4096, 1845 .num_alus = 1024, 1846 .num_statics = 256, 1847 .cpu_ports = 0x38, /* can be configured as cpu port */ 1848 .port_cnt = 5, /* total physical port count */ 1849 .port_nirqs = 6, 1850 .num_tx_queues = 8, 1851 .num_ipms = 8, 1852 .tc_cbs_supported = true, 1853 .ops = &lan937x_dev_ops, 1854 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1855 .mib_names = ksz9477_mib_names, 1856 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1857 .reg_mib_cnt = MIB_COUNTER_NUM, 1858 .regs = ksz9477_regs, 1859 .masks = lan937x_masks, 1860 .shifts = lan937x_shifts, 1861 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1862 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1863 .supports_mii = {false, false, false, false, 1864 true, true, false, false}, 1865 .supports_rmii = {false, false, false, false, 1866 true, true, false, false}, 1867 .supports_rgmii = {false, false, false, false, 1868 true, true, false, false}, 1869 .internal_phy = {true, true, true, false, 1870 false, false, true, true}, 1871 }, 1872 1873 [LAN9374] = { 1874 .chip_id = LAN9374_CHIP_ID, 1875 .dev_name = "LAN9374", 1876 .num_vlans = 4096, 1877 .num_alus = 1024, 1878 .num_statics = 256, 1879 .cpu_ports = 0x30, /* can be configured as cpu port */ 1880 .port_cnt = 8, /* total physical port count */ 1881 .port_nirqs = 6, 1882 .num_tx_queues = 8, 1883 .num_ipms = 8, 1884 .tc_cbs_supported = true, 1885 .ops = &lan937x_dev_ops, 1886 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1887 .mib_names = ksz9477_mib_names, 1888 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1889 .reg_mib_cnt = MIB_COUNTER_NUM, 1890 .regs = ksz9477_regs, 1891 .masks = lan937x_masks, 1892 .shifts = lan937x_shifts, 1893 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1894 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1895 .supports_mii = {false, false, false, false, 1896 true, true, false, false}, 1897 .supports_rmii = {false, false, false, false, 1898 true, true, false, false}, 1899 .supports_rgmii = {false, false, false, false, 1900 true, true, false, false}, 1901 .internal_phy = {true, true, true, true, 1902 false, false, true, true}, 1903 }, 1904 }; 1905 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1906 1907 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1908 { 1909 int i; 1910 1911 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1912 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1913 1914 if (chip->chip_id == prod_num) 1915 return chip; 1916 } 1917 1918 return NULL; 1919 } 1920 1921 static int ksz_check_device_id(struct ksz_device *dev) 1922 { 1923 const struct ksz_chip_data *expected_chip_data; 1924 u32 expected_chip_id; 1925 1926 if (dev->pdata) { 1927 expected_chip_id = dev->pdata->chip_id; 1928 expected_chip_data = ksz_lookup_info(expected_chip_id); 1929 if (WARN_ON(!expected_chip_data)) 1930 return -ENODEV; 1931 } else { 1932 expected_chip_data = of_device_get_match_data(dev->dev); 1933 expected_chip_id = expected_chip_data->chip_id; 1934 } 1935 1936 if (expected_chip_id != dev->chip_id) { 1937 dev_err(dev->dev, 1938 "Device tree specifies chip %s but found %s, please fix it!\n", 1939 expected_chip_data->dev_name, dev->info->dev_name); 1940 return -ENODEV; 1941 } 1942 1943 return 0; 1944 } 1945 1946 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1947 struct phylink_config *config) 1948 { 1949 struct ksz_device *dev = ds->priv; 1950 1951 if (dev->info->supports_mii[port]) 1952 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1953 1954 if (dev->info->supports_rmii[port]) 1955 __set_bit(PHY_INTERFACE_MODE_RMII, 1956 config->supported_interfaces); 1957 1958 if (dev->info->supports_rgmii[port]) 1959 phy_interface_set_rgmii(config->supported_interfaces); 1960 1961 if (dev->info->internal_phy[port]) { 1962 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1963 config->supported_interfaces); 1964 /* Compatibility for phylib's default interface type when the 1965 * phy-mode property is absent 1966 */ 1967 __set_bit(PHY_INTERFACE_MODE_GMII, 1968 config->supported_interfaces); 1969 } 1970 1971 if (dev->dev_ops->get_caps) 1972 dev->dev_ops->get_caps(dev, port, config); 1973 } 1974 1975 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 1976 { 1977 struct ethtool_pause_stats *pstats; 1978 struct rtnl_link_stats64 *stats; 1979 struct ksz_stats_raw *raw; 1980 struct ksz_port_mib *mib; 1981 int ret; 1982 1983 mib = &dev->ports[port].mib; 1984 stats = &mib->stats64; 1985 pstats = &mib->pause_stats; 1986 raw = (struct ksz_stats_raw *)mib->counters; 1987 1988 spin_lock(&mib->stats64_lock); 1989 1990 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1991 raw->rx_pause; 1992 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1993 raw->tx_pause; 1994 1995 /* HW counters are counting bytes + FCS which is not acceptable 1996 * for rtnl_link_stats64 interface 1997 */ 1998 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 1999 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 2000 2001 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2002 raw->rx_oversize; 2003 2004 stats->rx_crc_errors = raw->rx_crc_err; 2005 stats->rx_frame_errors = raw->rx_align_err; 2006 stats->rx_dropped = raw->rx_discards; 2007 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2008 stats->rx_frame_errors + stats->rx_dropped; 2009 2010 stats->tx_window_errors = raw->tx_late_col; 2011 stats->tx_fifo_errors = raw->tx_discards; 2012 stats->tx_aborted_errors = raw->tx_exc_col; 2013 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2014 stats->tx_aborted_errors; 2015 2016 stats->multicast = raw->rx_mcast; 2017 stats->collisions = raw->tx_total_col; 2018 2019 pstats->tx_pause_frames = raw->tx_pause; 2020 pstats->rx_pause_frames = raw->rx_pause; 2021 2022 spin_unlock(&mib->stats64_lock); 2023 2024 if (dev->info->phy_errata_9477) { 2025 ret = ksz9477_errata_monitor(dev, port, raw->tx_late_col); 2026 if (ret) 2027 dev_err(dev->dev, "Failed to monitor transmission halt\n"); 2028 } 2029 } 2030 2031 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 2032 { 2033 struct ethtool_pause_stats *pstats; 2034 struct rtnl_link_stats64 *stats; 2035 struct ksz88xx_stats_raw *raw; 2036 struct ksz_port_mib *mib; 2037 2038 mib = &dev->ports[port].mib; 2039 stats = &mib->stats64; 2040 pstats = &mib->pause_stats; 2041 raw = (struct ksz88xx_stats_raw *)mib->counters; 2042 2043 spin_lock(&mib->stats64_lock); 2044 2045 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 2046 raw->rx_pause; 2047 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2048 raw->tx_pause; 2049 2050 /* HW counters are counting bytes + FCS which is not acceptable 2051 * for rtnl_link_stats64 interface 2052 */ 2053 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 2054 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 2055 2056 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2057 raw->rx_oversize; 2058 2059 stats->rx_crc_errors = raw->rx_crc_err; 2060 stats->rx_frame_errors = raw->rx_align_err; 2061 stats->rx_dropped = raw->rx_discards; 2062 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2063 stats->rx_frame_errors + stats->rx_dropped; 2064 2065 stats->tx_window_errors = raw->tx_late_col; 2066 stats->tx_fifo_errors = raw->tx_discards; 2067 stats->tx_aborted_errors = raw->tx_exc_col; 2068 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2069 stats->tx_aborted_errors; 2070 2071 stats->multicast = raw->rx_mcast; 2072 stats->collisions = raw->tx_total_col; 2073 2074 pstats->tx_pause_frames = raw->tx_pause; 2075 pstats->rx_pause_frames = raw->rx_pause; 2076 2077 spin_unlock(&mib->stats64_lock); 2078 } 2079 2080 static void ksz_get_stats64(struct dsa_switch *ds, int port, 2081 struct rtnl_link_stats64 *s) 2082 { 2083 struct ksz_device *dev = ds->priv; 2084 struct ksz_port_mib *mib; 2085 2086 mib = &dev->ports[port].mib; 2087 2088 spin_lock(&mib->stats64_lock); 2089 memcpy(s, &mib->stats64, sizeof(*s)); 2090 spin_unlock(&mib->stats64_lock); 2091 } 2092 2093 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 2094 struct ethtool_pause_stats *pause_stats) 2095 { 2096 struct ksz_device *dev = ds->priv; 2097 struct ksz_port_mib *mib; 2098 2099 mib = &dev->ports[port].mib; 2100 2101 spin_lock(&mib->stats64_lock); 2102 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 2103 spin_unlock(&mib->stats64_lock); 2104 } 2105 2106 static void ksz_get_strings(struct dsa_switch *ds, int port, 2107 u32 stringset, uint8_t *buf) 2108 { 2109 struct ksz_device *dev = ds->priv; 2110 int i; 2111 2112 if (stringset != ETH_SS_STATS) 2113 return; 2114 2115 for (i = 0; i < dev->info->mib_cnt; i++) 2116 ethtool_puts(&buf, dev->info->mib_names[i].string); 2117 } 2118 2119 /** 2120 * ksz_update_port_member - Adjust port forwarding rules based on STP state and 2121 * isolation settings. 2122 * @dev: A pointer to the struct ksz_device representing the device. 2123 * @port: The port number to adjust. 2124 * 2125 * This function dynamically adjusts the port membership configuration for a 2126 * specified port and other device ports, based on Spanning Tree Protocol (STP) 2127 * states and port isolation settings. Each port, including the CPU port, has a 2128 * membership register, represented as a bitfield, where each bit corresponds 2129 * to a port number. A set bit indicates permission to forward frames to that 2130 * port. This function iterates over all ports, updating the membership register 2131 * to reflect current forwarding permissions: 2132 * 2133 * 1. Forwards frames only to ports that are part of the same bridge group and 2134 * in the BR_STATE_FORWARDING state. 2135 * 2. Takes into account the isolation status of ports; ports in the 2136 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward 2137 * frames to each other, even if they are in the same bridge group. 2138 * 3. Ensures that the CPU port is included in the membership based on its 2139 * upstream port configuration, allowing for management and control traffic 2140 * to flow as required. 2141 */ 2142 static void ksz_update_port_member(struct ksz_device *dev, int port) 2143 { 2144 struct ksz_port *p = &dev->ports[port]; 2145 struct dsa_switch *ds = dev->ds; 2146 u8 port_member = 0, cpu_port; 2147 const struct dsa_port *dp; 2148 int i, j; 2149 2150 if (!dsa_is_user_port(ds, port)) 2151 return; 2152 2153 dp = dsa_to_port(ds, port); 2154 cpu_port = BIT(dsa_upstream_port(ds, port)); 2155 2156 for (i = 0; i < ds->num_ports; i++) { 2157 const struct dsa_port *other_dp = dsa_to_port(ds, i); 2158 struct ksz_port *other_p = &dev->ports[i]; 2159 u8 val = 0; 2160 2161 if (!dsa_is_user_port(ds, i)) 2162 continue; 2163 if (port == i) 2164 continue; 2165 if (!dsa_port_bridge_same(dp, other_dp)) 2166 continue; 2167 if (other_p->stp_state != BR_STATE_FORWARDING) 2168 continue; 2169 2170 /* At this point we know that "port" and "other" port [i] are in 2171 * the same bridge group and that "other" port [i] is in 2172 * forwarding stp state. If "port" is also in forwarding stp 2173 * state, we can allow forwarding from port [port] to port [i]. 2174 * Except if both ports are isolated. 2175 */ 2176 if (p->stp_state == BR_STATE_FORWARDING && 2177 !(p->isolated && other_p->isolated)) { 2178 val |= BIT(port); 2179 port_member |= BIT(i); 2180 } 2181 2182 /* Retain port [i]'s relationship to other ports than [port] */ 2183 for (j = 0; j < ds->num_ports; j++) { 2184 const struct dsa_port *third_dp; 2185 struct ksz_port *third_p; 2186 2187 if (j == i) 2188 continue; 2189 if (j == port) 2190 continue; 2191 if (!dsa_is_user_port(ds, j)) 2192 continue; 2193 third_p = &dev->ports[j]; 2194 if (third_p->stp_state != BR_STATE_FORWARDING) 2195 continue; 2196 2197 third_dp = dsa_to_port(ds, j); 2198 2199 /* Now we updating relation of the "other" port [i] to 2200 * the "third" port [j]. We already know that "other" 2201 * port [i] is in forwarding stp state and that "third" 2202 * port [j] is in forwarding stp state too. 2203 * We need to check if "other" port [i] and "third" port 2204 * [j] are in the same bridge group and not isolated 2205 * before allowing forwarding from port [i] to port [j]. 2206 */ 2207 if (dsa_port_bridge_same(other_dp, third_dp) && 2208 !(other_p->isolated && third_p->isolated)) 2209 val |= BIT(j); 2210 } 2211 2212 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 2213 } 2214 2215 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 2216 } 2217 2218 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 2219 { 2220 struct ksz_device *dev = bus->priv; 2221 u16 val; 2222 int ret; 2223 2224 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 2225 if (ret < 0) 2226 return ret; 2227 2228 return val; 2229 } 2230 2231 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 2232 u16 val) 2233 { 2234 struct ksz_device *dev = bus->priv; 2235 2236 return dev->dev_ops->w_phy(dev, addr, regnum, val); 2237 } 2238 2239 static int ksz_irq_phy_setup(struct ksz_device *dev) 2240 { 2241 struct dsa_switch *ds = dev->ds; 2242 int phy; 2243 int irq; 2244 int ret; 2245 2246 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) { 2247 if (BIT(phy) & ds->phys_mii_mask) { 2248 irq = irq_find_mapping(dev->ports[phy].pirq.domain, 2249 PORT_SRC_PHY_INT); 2250 if (irq < 0) { 2251 ret = irq; 2252 goto out; 2253 } 2254 ds->user_mii_bus->irq[phy] = irq; 2255 } 2256 } 2257 return 0; 2258 out: 2259 while (phy--) 2260 if (BIT(phy) & ds->phys_mii_mask) 2261 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2262 2263 return ret; 2264 } 2265 2266 static void ksz_irq_phy_free(struct ksz_device *dev) 2267 { 2268 struct dsa_switch *ds = dev->ds; 2269 int phy; 2270 2271 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) 2272 if (BIT(phy) & ds->phys_mii_mask) 2273 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2274 } 2275 2276 static int ksz_mdio_register(struct ksz_device *dev) 2277 { 2278 struct dsa_switch *ds = dev->ds; 2279 struct device_node *mdio_np; 2280 struct mii_bus *bus; 2281 int ret; 2282 2283 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 2284 if (!mdio_np) 2285 return 0; 2286 2287 bus = devm_mdiobus_alloc(ds->dev); 2288 if (!bus) { 2289 of_node_put(mdio_np); 2290 return -ENOMEM; 2291 } 2292 2293 bus->priv = dev; 2294 bus->read = ksz_sw_mdio_read; 2295 bus->write = ksz_sw_mdio_write; 2296 bus->name = "ksz user smi"; 2297 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 2298 bus->parent = ds->dev; 2299 bus->phy_mask = ~ds->phys_mii_mask; 2300 2301 ds->user_mii_bus = bus; 2302 2303 if (dev->irq > 0) { 2304 ret = ksz_irq_phy_setup(dev); 2305 if (ret) { 2306 of_node_put(mdio_np); 2307 return ret; 2308 } 2309 } 2310 2311 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 2312 if (ret) { 2313 dev_err(ds->dev, "unable to register MDIO bus %s\n", 2314 bus->id); 2315 if (dev->irq > 0) 2316 ksz_irq_phy_free(dev); 2317 } 2318 2319 of_node_put(mdio_np); 2320 2321 return ret; 2322 } 2323 2324 static void ksz_irq_mask(struct irq_data *d) 2325 { 2326 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2327 2328 kirq->masked |= BIT(d->hwirq); 2329 } 2330 2331 static void ksz_irq_unmask(struct irq_data *d) 2332 { 2333 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2334 2335 kirq->masked &= ~BIT(d->hwirq); 2336 } 2337 2338 static void ksz_irq_bus_lock(struct irq_data *d) 2339 { 2340 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2341 2342 mutex_lock(&kirq->dev->lock_irq); 2343 } 2344 2345 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 2346 { 2347 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2348 struct ksz_device *dev = kirq->dev; 2349 int ret; 2350 2351 ret = ksz_write8(dev, kirq->reg_mask, kirq->masked); 2352 if (ret) 2353 dev_err(dev->dev, "failed to change IRQ mask\n"); 2354 2355 mutex_unlock(&dev->lock_irq); 2356 } 2357 2358 static const struct irq_chip ksz_irq_chip = { 2359 .name = "ksz-irq", 2360 .irq_mask = ksz_irq_mask, 2361 .irq_unmask = ksz_irq_unmask, 2362 .irq_bus_lock = ksz_irq_bus_lock, 2363 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 2364 }; 2365 2366 static int ksz_irq_domain_map(struct irq_domain *d, 2367 unsigned int irq, irq_hw_number_t hwirq) 2368 { 2369 irq_set_chip_data(irq, d->host_data); 2370 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 2371 irq_set_noprobe(irq); 2372 2373 return 0; 2374 } 2375 2376 static const struct irq_domain_ops ksz_irq_domain_ops = { 2377 .map = ksz_irq_domain_map, 2378 .xlate = irq_domain_xlate_twocell, 2379 }; 2380 2381 static void ksz_irq_free(struct ksz_irq *kirq) 2382 { 2383 int irq, virq; 2384 2385 free_irq(kirq->irq_num, kirq); 2386 2387 for (irq = 0; irq < kirq->nirqs; irq++) { 2388 virq = irq_find_mapping(kirq->domain, irq); 2389 irq_dispose_mapping(virq); 2390 } 2391 2392 irq_domain_remove(kirq->domain); 2393 } 2394 2395 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 2396 { 2397 struct ksz_irq *kirq = dev_id; 2398 unsigned int nhandled = 0; 2399 struct ksz_device *dev; 2400 unsigned int sub_irq; 2401 u8 data; 2402 int ret; 2403 u8 n; 2404 2405 dev = kirq->dev; 2406 2407 /* Read interrupt status register */ 2408 ret = ksz_read8(dev, kirq->reg_status, &data); 2409 if (ret) 2410 goto out; 2411 2412 for (n = 0; n < kirq->nirqs; ++n) { 2413 if (data & BIT(n)) { 2414 sub_irq = irq_find_mapping(kirq->domain, n); 2415 handle_nested_irq(sub_irq); 2416 ++nhandled; 2417 } 2418 } 2419 out: 2420 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2421 } 2422 2423 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 2424 { 2425 int ret, n; 2426 2427 kirq->dev = dev; 2428 kirq->masked = ~0; 2429 2430 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0, 2431 &ksz_irq_domain_ops, kirq); 2432 if (!kirq->domain) 2433 return -ENOMEM; 2434 2435 for (n = 0; n < kirq->nirqs; n++) 2436 irq_create_mapping(kirq->domain, n); 2437 2438 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2439 IRQF_ONESHOT, kirq->name, kirq); 2440 if (ret) 2441 goto out; 2442 2443 return 0; 2444 2445 out: 2446 ksz_irq_free(kirq); 2447 2448 return ret; 2449 } 2450 2451 static int ksz_girq_setup(struct ksz_device *dev) 2452 { 2453 struct ksz_irq *girq = &dev->girq; 2454 2455 girq->nirqs = dev->info->port_cnt; 2456 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2457 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2458 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2459 2460 girq->irq_num = dev->irq; 2461 2462 return ksz_irq_common_setup(dev, girq); 2463 } 2464 2465 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2466 { 2467 struct ksz_irq *pirq = &dev->ports[p].pirq; 2468 2469 pirq->nirqs = dev->info->port_nirqs; 2470 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2471 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2472 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2473 2474 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2475 if (pirq->irq_num < 0) 2476 return pirq->irq_num; 2477 2478 return ksz_irq_common_setup(dev, pirq); 2479 } 2480 2481 static int ksz_parse_drive_strength(struct ksz_device *dev); 2482 2483 static int ksz_setup(struct dsa_switch *ds) 2484 { 2485 struct ksz_device *dev = ds->priv; 2486 struct dsa_port *dp; 2487 struct ksz_port *p; 2488 const u16 *regs; 2489 int ret; 2490 2491 regs = dev->info->regs; 2492 2493 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2494 dev->info->num_vlans, GFP_KERNEL); 2495 if (!dev->vlan_cache) 2496 return -ENOMEM; 2497 2498 ret = dev->dev_ops->reset(dev); 2499 if (ret) { 2500 dev_err(ds->dev, "failed to reset switch\n"); 2501 return ret; 2502 } 2503 2504 ret = ksz_parse_drive_strength(dev); 2505 if (ret) 2506 return ret; 2507 2508 /* set broadcast storm protection 10% rate */ 2509 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2510 BROADCAST_STORM_RATE, 2511 (BROADCAST_STORM_VALUE * 2512 BROADCAST_STORM_PROT_RATE) / 100); 2513 2514 dev->dev_ops->config_cpu_port(ds); 2515 2516 dev->dev_ops->enable_stp_addr(dev); 2517 2518 ds->num_tx_queues = dev->info->num_tx_queues; 2519 2520 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 2521 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2522 2523 ksz_init_mib_timer(dev); 2524 2525 ds->configure_vlan_while_not_filtering = false; 2526 ds->dscp_prio_mapping_is_global = true; 2527 2528 if (dev->dev_ops->setup) { 2529 ret = dev->dev_ops->setup(ds); 2530 if (ret) 2531 return ret; 2532 } 2533 2534 /* Start with learning disabled on standalone user ports, and enabled 2535 * on the CPU port. In lack of other finer mechanisms, learning on the 2536 * CPU port will avoid flooding bridge local addresses on the network 2537 * in some cases. 2538 */ 2539 p = &dev->ports[dev->cpu_port]; 2540 p->learning = true; 2541 2542 if (dev->irq > 0) { 2543 ret = ksz_girq_setup(dev); 2544 if (ret) 2545 return ret; 2546 2547 dsa_switch_for_each_user_port(dp, dev->ds) { 2548 ret = ksz_pirq_setup(dev, dp->index); 2549 if (ret) 2550 goto out_girq; 2551 2552 ret = ksz_ptp_irq_setup(ds, dp->index); 2553 if (ret) 2554 goto out_pirq; 2555 } 2556 } 2557 2558 ret = ksz_ptp_clock_register(ds); 2559 if (ret) { 2560 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret); 2561 goto out_ptpirq; 2562 } 2563 2564 ret = ksz_mdio_register(dev); 2565 if (ret < 0) { 2566 dev_err(dev->dev, "failed to register the mdio"); 2567 goto out_ptp_clock_unregister; 2568 } 2569 2570 ret = ksz_dcb_init(dev); 2571 if (ret) 2572 goto out_ptp_clock_unregister; 2573 2574 /* start switch */ 2575 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 2576 SW_START, SW_START); 2577 2578 return 0; 2579 2580 out_ptp_clock_unregister: 2581 ksz_ptp_clock_unregister(ds); 2582 out_ptpirq: 2583 if (dev->irq > 0) 2584 dsa_switch_for_each_user_port(dp, dev->ds) 2585 ksz_ptp_irq_free(ds, dp->index); 2586 out_pirq: 2587 if (dev->irq > 0) 2588 dsa_switch_for_each_user_port(dp, dev->ds) 2589 ksz_irq_free(&dev->ports[dp->index].pirq); 2590 out_girq: 2591 if (dev->irq > 0) 2592 ksz_irq_free(&dev->girq); 2593 2594 return ret; 2595 } 2596 2597 static void ksz_teardown(struct dsa_switch *ds) 2598 { 2599 struct ksz_device *dev = ds->priv; 2600 struct dsa_port *dp; 2601 2602 ksz_ptp_clock_unregister(ds); 2603 2604 if (dev->irq > 0) { 2605 dsa_switch_for_each_user_port(dp, dev->ds) { 2606 ksz_ptp_irq_free(ds, dp->index); 2607 2608 ksz_irq_free(&dev->ports[dp->index].pirq); 2609 } 2610 2611 ksz_irq_free(&dev->girq); 2612 } 2613 2614 if (dev->dev_ops->teardown) 2615 dev->dev_ops->teardown(ds); 2616 } 2617 2618 static void port_r_cnt(struct ksz_device *dev, int port) 2619 { 2620 struct ksz_port_mib *mib = &dev->ports[port].mib; 2621 u64 *dropped; 2622 2623 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2624 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2625 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2626 &mib->counters[mib->cnt_ptr]); 2627 ++mib->cnt_ptr; 2628 } 2629 2630 /* last one in storage */ 2631 dropped = &mib->counters[dev->info->mib_cnt]; 2632 2633 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2634 while (mib->cnt_ptr < dev->info->mib_cnt) { 2635 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2636 dropped, &mib->counters[mib->cnt_ptr]); 2637 ++mib->cnt_ptr; 2638 } 2639 mib->cnt_ptr = 0; 2640 } 2641 2642 static void ksz_mib_read_work(struct work_struct *work) 2643 { 2644 struct ksz_device *dev = container_of(work, struct ksz_device, 2645 mib_read.work); 2646 struct ksz_port_mib *mib; 2647 struct ksz_port *p; 2648 int i; 2649 2650 for (i = 0; i < dev->info->port_cnt; i++) { 2651 if (dsa_is_unused_port(dev->ds, i)) 2652 continue; 2653 2654 p = &dev->ports[i]; 2655 mib = &p->mib; 2656 mutex_lock(&mib->cnt_mutex); 2657 2658 /* Only read MIB counters when the port is told to do. 2659 * If not, read only dropped counters when link is not up. 2660 */ 2661 if (!p->read) { 2662 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 2663 2664 if (!netif_carrier_ok(dp->user)) 2665 mib->cnt_ptr = dev->info->reg_mib_cnt; 2666 } 2667 port_r_cnt(dev, i); 2668 p->read = false; 2669 2670 if (dev->dev_ops->r_mib_stat64) 2671 dev->dev_ops->r_mib_stat64(dev, i); 2672 2673 mutex_unlock(&mib->cnt_mutex); 2674 } 2675 2676 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 2677 } 2678 2679 void ksz_init_mib_timer(struct ksz_device *dev) 2680 { 2681 int i; 2682 2683 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 2684 2685 for (i = 0; i < dev->info->port_cnt; i++) { 2686 struct ksz_port_mib *mib = &dev->ports[i].mib; 2687 2688 dev->dev_ops->port_init_cnt(dev, i); 2689 2690 mib->cnt_ptr = 0; 2691 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 2692 } 2693 } 2694 2695 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 2696 { 2697 struct ksz_device *dev = ds->priv; 2698 u16 val = 0xffff; 2699 int ret; 2700 2701 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 2702 if (ret) 2703 return ret; 2704 2705 return val; 2706 } 2707 2708 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 2709 { 2710 struct ksz_device *dev = ds->priv; 2711 int ret; 2712 2713 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 2714 if (ret) 2715 return ret; 2716 2717 return 0; 2718 } 2719 2720 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 2721 { 2722 struct ksz_device *dev = ds->priv; 2723 2724 switch (dev->chip_id) { 2725 case KSZ88X3_CHIP_ID: 2726 /* Silicon Errata Sheet (DS80000830A): 2727 * Port 1 does not work with LinkMD Cable-Testing. 2728 * Port 1 does not respond to received PAUSE control frames. 2729 */ 2730 if (!port) 2731 return MICREL_KSZ8_P1_ERRATA; 2732 break; 2733 case KSZ8567_CHIP_ID: 2734 /* KSZ8567R Errata DS80000752C Module 4 */ 2735 case KSZ8765_CHIP_ID: 2736 case KSZ8794_CHIP_ID: 2737 case KSZ8795_CHIP_ID: 2738 /* KSZ879x/KSZ877x/KSZ876x Errata DS80000687C Module 2 */ 2739 case KSZ9477_CHIP_ID: 2740 /* KSZ9477S Errata DS80000754A Module 4 */ 2741 case KSZ9567_CHIP_ID: 2742 /* KSZ9567S Errata DS80000756A Module 4 */ 2743 case KSZ9896_CHIP_ID: 2744 /* KSZ9896C Errata DS80000757A Module 3 */ 2745 case KSZ9897_CHIP_ID: 2746 /* KSZ9897R Errata DS80000758C Module 4 */ 2747 /* Energy Efficient Ethernet (EEE) feature select must be manually disabled 2748 * The EEE feature is enabled by default, but it is not fully 2749 * operational. It must be manually disabled through register 2750 * controls. If not disabled, the PHY ports can auto-negotiate 2751 * to enable EEE, and this feature can cause link drops when 2752 * linked to another device supporting EEE. 2753 * 2754 * The same item appears in the errata for all switches above. 2755 */ 2756 return MICREL_NO_EEE; 2757 } 2758 2759 return 0; 2760 } 2761 2762 static void ksz_phylink_mac_link_down(struct phylink_config *config, 2763 unsigned int mode, 2764 phy_interface_t interface) 2765 { 2766 struct dsa_port *dp = dsa_phylink_to_port(config); 2767 struct ksz_device *dev = dp->ds->priv; 2768 2769 /* Read all MIB counters when the link is going down. */ 2770 dev->ports[dp->index].read = true; 2771 /* timer started */ 2772 if (dev->mib_read_interval) 2773 schedule_delayed_work(&dev->mib_read, 0); 2774 } 2775 2776 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 2777 { 2778 struct ksz_device *dev = ds->priv; 2779 2780 if (sset != ETH_SS_STATS) 2781 return 0; 2782 2783 return dev->info->mib_cnt; 2784 } 2785 2786 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 2787 uint64_t *buf) 2788 { 2789 const struct dsa_port *dp = dsa_to_port(ds, port); 2790 struct ksz_device *dev = ds->priv; 2791 struct ksz_port_mib *mib; 2792 2793 mib = &dev->ports[port].mib; 2794 mutex_lock(&mib->cnt_mutex); 2795 2796 /* Only read dropped counters if no link. */ 2797 if (!netif_carrier_ok(dp->user)) 2798 mib->cnt_ptr = dev->info->reg_mib_cnt; 2799 port_r_cnt(dev, port); 2800 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 2801 mutex_unlock(&mib->cnt_mutex); 2802 } 2803 2804 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 2805 struct dsa_bridge bridge, 2806 bool *tx_fwd_offload, 2807 struct netlink_ext_ack *extack) 2808 { 2809 /* port_stp_state_set() will be called after to put the port in 2810 * appropriate state so there is no need to do anything. 2811 */ 2812 2813 return 0; 2814 } 2815 2816 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 2817 struct dsa_bridge bridge) 2818 { 2819 /* port_stp_state_set() will be called after to put the port in 2820 * forwarding state so there is no need to do anything. 2821 */ 2822 } 2823 2824 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 2825 { 2826 struct ksz_device *dev = ds->priv; 2827 2828 dev->dev_ops->flush_dyn_mac_table(dev, port); 2829 } 2830 2831 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 2832 { 2833 struct ksz_device *dev = ds->priv; 2834 2835 if (!dev->dev_ops->set_ageing_time) 2836 return -EOPNOTSUPP; 2837 2838 return dev->dev_ops->set_ageing_time(dev, msecs); 2839 } 2840 2841 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 2842 const unsigned char *addr, u16 vid, 2843 struct dsa_db db) 2844 { 2845 struct ksz_device *dev = ds->priv; 2846 2847 if (!dev->dev_ops->fdb_add) 2848 return -EOPNOTSUPP; 2849 2850 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 2851 } 2852 2853 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 2854 const unsigned char *addr, 2855 u16 vid, struct dsa_db db) 2856 { 2857 struct ksz_device *dev = ds->priv; 2858 2859 if (!dev->dev_ops->fdb_del) 2860 return -EOPNOTSUPP; 2861 2862 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 2863 } 2864 2865 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 2866 dsa_fdb_dump_cb_t *cb, void *data) 2867 { 2868 struct ksz_device *dev = ds->priv; 2869 2870 if (!dev->dev_ops->fdb_dump) 2871 return -EOPNOTSUPP; 2872 2873 return dev->dev_ops->fdb_dump(dev, port, cb, data); 2874 } 2875 2876 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 2877 const struct switchdev_obj_port_mdb *mdb, 2878 struct dsa_db db) 2879 { 2880 struct ksz_device *dev = ds->priv; 2881 2882 if (!dev->dev_ops->mdb_add) 2883 return -EOPNOTSUPP; 2884 2885 return dev->dev_ops->mdb_add(dev, port, mdb, db); 2886 } 2887 2888 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 2889 const struct switchdev_obj_port_mdb *mdb, 2890 struct dsa_db db) 2891 { 2892 struct ksz_device *dev = ds->priv; 2893 2894 if (!dev->dev_ops->mdb_del) 2895 return -EOPNOTSUPP; 2896 2897 return dev->dev_ops->mdb_del(dev, port, mdb, db); 2898 } 2899 2900 static int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev, 2901 int port) 2902 { 2903 u32 queue_map = 0; 2904 int ipm; 2905 2906 for (ipm = 0; ipm < dev->info->num_ipms; ipm++) { 2907 int queue; 2908 2909 /* Traffic Type (TT) is corresponding to the Internal Priority 2910 * Map (IPM) in the switch. Traffic Class (TC) is 2911 * corresponding to the queue in the switch. 2912 */ 2913 queue = ieee8021q_tt_to_tc(ipm, dev->info->num_tx_queues); 2914 if (queue < 0) 2915 return queue; 2916 2917 queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S); 2918 } 2919 2920 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 2921 } 2922 2923 static int ksz_port_setup(struct dsa_switch *ds, int port) 2924 { 2925 struct ksz_device *dev = ds->priv; 2926 int ret; 2927 2928 if (!dsa_is_user_port(ds, port)) 2929 return 0; 2930 2931 /* setup user port */ 2932 dev->dev_ops->port_setup(dev, port, false); 2933 2934 if (!is_ksz8(dev)) { 2935 ret = ksz9477_set_default_prio_queue_mapping(dev, port); 2936 if (ret) 2937 return ret; 2938 } 2939 2940 /* port_stp_state_set() will be called after to enable the port so 2941 * there is no need to do anything. 2942 */ 2943 2944 return ksz_dcb_init_port(dev, port); 2945 } 2946 2947 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 2948 { 2949 struct ksz_device *dev = ds->priv; 2950 struct ksz_port *p; 2951 const u16 *regs; 2952 u8 data; 2953 2954 regs = dev->info->regs; 2955 2956 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 2957 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2958 2959 p = &dev->ports[port]; 2960 2961 switch (state) { 2962 case BR_STATE_DISABLED: 2963 data |= PORT_LEARN_DISABLE; 2964 break; 2965 case BR_STATE_LISTENING: 2966 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2967 break; 2968 case BR_STATE_LEARNING: 2969 data |= PORT_RX_ENABLE; 2970 if (!p->learning) 2971 data |= PORT_LEARN_DISABLE; 2972 break; 2973 case BR_STATE_FORWARDING: 2974 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 2975 if (!p->learning) 2976 data |= PORT_LEARN_DISABLE; 2977 break; 2978 case BR_STATE_BLOCKING: 2979 data |= PORT_LEARN_DISABLE; 2980 break; 2981 default: 2982 dev_err(ds->dev, "invalid STP state: %d\n", state); 2983 return; 2984 } 2985 2986 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 2987 2988 p->stp_state = state; 2989 2990 ksz_update_port_member(dev, port); 2991 } 2992 2993 static void ksz_port_teardown(struct dsa_switch *ds, int port) 2994 { 2995 struct ksz_device *dev = ds->priv; 2996 2997 switch (dev->chip_id) { 2998 case KSZ8563_CHIP_ID: 2999 case KSZ8567_CHIP_ID: 3000 case KSZ9477_CHIP_ID: 3001 case KSZ9563_CHIP_ID: 3002 case KSZ9567_CHIP_ID: 3003 case KSZ9893_CHIP_ID: 3004 case KSZ9896_CHIP_ID: 3005 case KSZ9897_CHIP_ID: 3006 if (dsa_is_user_port(ds, port)) 3007 ksz9477_port_acl_free(dev, port); 3008 } 3009 } 3010 3011 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 3012 struct switchdev_brport_flags flags, 3013 struct netlink_ext_ack *extack) 3014 { 3015 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED)) 3016 return -EINVAL; 3017 3018 return 0; 3019 } 3020 3021 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 3022 struct switchdev_brport_flags flags, 3023 struct netlink_ext_ack *extack) 3024 { 3025 struct ksz_device *dev = ds->priv; 3026 struct ksz_port *p = &dev->ports[port]; 3027 3028 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) { 3029 if (flags.mask & BR_LEARNING) 3030 p->learning = !!(flags.val & BR_LEARNING); 3031 3032 if (flags.mask & BR_ISOLATED) 3033 p->isolated = !!(flags.val & BR_ISOLATED); 3034 3035 /* Make the change take effect immediately */ 3036 ksz_port_stp_state_set(ds, port, p->stp_state); 3037 } 3038 3039 return 0; 3040 } 3041 3042 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 3043 int port, 3044 enum dsa_tag_protocol mp) 3045 { 3046 struct ksz_device *dev = ds->priv; 3047 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 3048 3049 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev)) 3050 proto = DSA_TAG_PROTO_KSZ8795; 3051 3052 if (dev->chip_id == KSZ88X3_CHIP_ID || 3053 dev->chip_id == KSZ8563_CHIP_ID || 3054 dev->chip_id == KSZ9893_CHIP_ID || 3055 dev->chip_id == KSZ9563_CHIP_ID) 3056 proto = DSA_TAG_PROTO_KSZ9893; 3057 3058 if (dev->chip_id == KSZ8567_CHIP_ID || 3059 dev->chip_id == KSZ9477_CHIP_ID || 3060 dev->chip_id == KSZ9896_CHIP_ID || 3061 dev->chip_id == KSZ9897_CHIP_ID || 3062 dev->chip_id == KSZ9567_CHIP_ID) 3063 proto = DSA_TAG_PROTO_KSZ9477; 3064 3065 if (is_lan937x(dev)) 3066 proto = DSA_TAG_PROTO_LAN937X; 3067 3068 return proto; 3069 } 3070 3071 static int ksz_connect_tag_protocol(struct dsa_switch *ds, 3072 enum dsa_tag_protocol proto) 3073 { 3074 struct ksz_tagger_data *tagger_data; 3075 3076 switch (proto) { 3077 case DSA_TAG_PROTO_KSZ8795: 3078 return 0; 3079 case DSA_TAG_PROTO_KSZ9893: 3080 case DSA_TAG_PROTO_KSZ9477: 3081 case DSA_TAG_PROTO_LAN937X: 3082 tagger_data = ksz_tagger_data(ds); 3083 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 3084 return 0; 3085 default: 3086 return -EPROTONOSUPPORT; 3087 } 3088 } 3089 3090 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 3091 bool flag, struct netlink_ext_ack *extack) 3092 { 3093 struct ksz_device *dev = ds->priv; 3094 3095 if (!dev->dev_ops->vlan_filtering) 3096 return -EOPNOTSUPP; 3097 3098 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 3099 } 3100 3101 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 3102 const struct switchdev_obj_port_vlan *vlan, 3103 struct netlink_ext_ack *extack) 3104 { 3105 struct ksz_device *dev = ds->priv; 3106 3107 if (!dev->dev_ops->vlan_add) 3108 return -EOPNOTSUPP; 3109 3110 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 3111 } 3112 3113 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 3114 const struct switchdev_obj_port_vlan *vlan) 3115 { 3116 struct ksz_device *dev = ds->priv; 3117 3118 if (!dev->dev_ops->vlan_del) 3119 return -EOPNOTSUPP; 3120 3121 return dev->dev_ops->vlan_del(dev, port, vlan); 3122 } 3123 3124 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 3125 struct dsa_mall_mirror_tc_entry *mirror, 3126 bool ingress, struct netlink_ext_ack *extack) 3127 { 3128 struct ksz_device *dev = ds->priv; 3129 3130 if (!dev->dev_ops->mirror_add) 3131 return -EOPNOTSUPP; 3132 3133 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 3134 } 3135 3136 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 3137 struct dsa_mall_mirror_tc_entry *mirror) 3138 { 3139 struct ksz_device *dev = ds->priv; 3140 3141 if (dev->dev_ops->mirror_del) 3142 dev->dev_ops->mirror_del(dev, port, mirror); 3143 } 3144 3145 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 3146 { 3147 struct ksz_device *dev = ds->priv; 3148 3149 if (!dev->dev_ops->change_mtu) 3150 return -EOPNOTSUPP; 3151 3152 return dev->dev_ops->change_mtu(dev, port, mtu); 3153 } 3154 3155 static int ksz_max_mtu(struct dsa_switch *ds, int port) 3156 { 3157 struct ksz_device *dev = ds->priv; 3158 3159 switch (dev->chip_id) { 3160 case KSZ8795_CHIP_ID: 3161 case KSZ8794_CHIP_ID: 3162 case KSZ8765_CHIP_ID: 3163 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3164 case KSZ88X3_CHIP_ID: 3165 case KSZ8864_CHIP_ID: 3166 case KSZ8895_CHIP_ID: 3167 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3168 case KSZ8563_CHIP_ID: 3169 case KSZ8567_CHIP_ID: 3170 case KSZ9477_CHIP_ID: 3171 case KSZ9563_CHIP_ID: 3172 case KSZ9567_CHIP_ID: 3173 case KSZ9893_CHIP_ID: 3174 case KSZ9896_CHIP_ID: 3175 case KSZ9897_CHIP_ID: 3176 case LAN9370_CHIP_ID: 3177 case LAN9371_CHIP_ID: 3178 case LAN9372_CHIP_ID: 3179 case LAN9373_CHIP_ID: 3180 case LAN9374_CHIP_ID: 3181 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3182 } 3183 3184 return -EOPNOTSUPP; 3185 } 3186 3187 static int ksz_validate_eee(struct dsa_switch *ds, int port) 3188 { 3189 struct ksz_device *dev = ds->priv; 3190 3191 if (!dev->info->internal_phy[port]) 3192 return -EOPNOTSUPP; 3193 3194 switch (dev->chip_id) { 3195 case KSZ8563_CHIP_ID: 3196 case KSZ8567_CHIP_ID: 3197 case KSZ9477_CHIP_ID: 3198 case KSZ9563_CHIP_ID: 3199 case KSZ9567_CHIP_ID: 3200 case KSZ9893_CHIP_ID: 3201 case KSZ9896_CHIP_ID: 3202 case KSZ9897_CHIP_ID: 3203 return 0; 3204 } 3205 3206 return -EOPNOTSUPP; 3207 } 3208 3209 static int ksz_get_mac_eee(struct dsa_switch *ds, int port, 3210 struct ethtool_keee *e) 3211 { 3212 int ret; 3213 3214 ret = ksz_validate_eee(ds, port); 3215 if (ret) 3216 return ret; 3217 3218 /* There is no documented control of Tx LPI configuration. */ 3219 e->tx_lpi_enabled = true; 3220 3221 /* There is no documented control of Tx LPI timer. According to tests 3222 * Tx LPI timer seems to be set by default to minimal value. 3223 */ 3224 e->tx_lpi_timer = 0; 3225 3226 return 0; 3227 } 3228 3229 static int ksz_set_mac_eee(struct dsa_switch *ds, int port, 3230 struct ethtool_keee *e) 3231 { 3232 struct ksz_device *dev = ds->priv; 3233 int ret; 3234 3235 ret = ksz_validate_eee(ds, port); 3236 if (ret) 3237 return ret; 3238 3239 if (!e->tx_lpi_enabled) { 3240 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 3241 return -EINVAL; 3242 } 3243 3244 if (e->tx_lpi_timer) { 3245 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 3246 return -EINVAL; 3247 } 3248 3249 return 0; 3250 } 3251 3252 static void ksz_set_xmii(struct ksz_device *dev, int port, 3253 phy_interface_t interface) 3254 { 3255 const u8 *bitval = dev->info->xmii_ctrl1; 3256 struct ksz_port *p = &dev->ports[port]; 3257 const u16 *regs = dev->info->regs; 3258 u8 data8; 3259 3260 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3261 3262 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 3263 P_RGMII_ID_EG_ENABLE); 3264 3265 switch (interface) { 3266 case PHY_INTERFACE_MODE_MII: 3267 data8 |= bitval[P_MII_SEL]; 3268 break; 3269 case PHY_INTERFACE_MODE_RMII: 3270 data8 |= bitval[P_RMII_SEL]; 3271 break; 3272 case PHY_INTERFACE_MODE_GMII: 3273 data8 |= bitval[P_GMII_SEL]; 3274 break; 3275 case PHY_INTERFACE_MODE_RGMII: 3276 case PHY_INTERFACE_MODE_RGMII_ID: 3277 case PHY_INTERFACE_MODE_RGMII_TXID: 3278 case PHY_INTERFACE_MODE_RGMII_RXID: 3279 data8 |= bitval[P_RGMII_SEL]; 3280 /* On KSZ9893, disable RGMII in-band status support */ 3281 if (dev->chip_id == KSZ9893_CHIP_ID || 3282 dev->chip_id == KSZ8563_CHIP_ID || 3283 dev->chip_id == KSZ9563_CHIP_ID || 3284 is_lan937x(dev)) 3285 data8 &= ~P_MII_MAC_MODE; 3286 break; 3287 default: 3288 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 3289 phy_modes(interface), port); 3290 return; 3291 } 3292 3293 if (p->rgmii_tx_val) 3294 data8 |= P_RGMII_ID_EG_ENABLE; 3295 3296 if (p->rgmii_rx_val) 3297 data8 |= P_RGMII_ID_IG_ENABLE; 3298 3299 /* Write the updated value */ 3300 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3301 } 3302 3303 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 3304 { 3305 const u8 *bitval = dev->info->xmii_ctrl1; 3306 const u16 *regs = dev->info->regs; 3307 phy_interface_t interface; 3308 u8 data8; 3309 u8 val; 3310 3311 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3312 3313 val = FIELD_GET(P_MII_SEL_M, data8); 3314 3315 if (val == bitval[P_MII_SEL]) { 3316 if (gbit) 3317 interface = PHY_INTERFACE_MODE_GMII; 3318 else 3319 interface = PHY_INTERFACE_MODE_MII; 3320 } else if (val == bitval[P_RMII_SEL]) { 3321 interface = PHY_INTERFACE_MODE_RMII; 3322 } else { 3323 interface = PHY_INTERFACE_MODE_RGMII; 3324 if (data8 & P_RGMII_ID_EG_ENABLE) 3325 interface = PHY_INTERFACE_MODE_RGMII_TXID; 3326 if (data8 & P_RGMII_ID_IG_ENABLE) { 3327 interface = PHY_INTERFACE_MODE_RGMII_RXID; 3328 if (data8 & P_RGMII_ID_EG_ENABLE) 3329 interface = PHY_INTERFACE_MODE_RGMII_ID; 3330 } 3331 } 3332 3333 return interface; 3334 } 3335 3336 static void ksz88x3_phylink_mac_config(struct phylink_config *config, 3337 unsigned int mode, 3338 const struct phylink_link_state *state) 3339 { 3340 struct dsa_port *dp = dsa_phylink_to_port(config); 3341 struct ksz_device *dev = dp->ds->priv; 3342 3343 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN); 3344 } 3345 3346 static void ksz_phylink_mac_config(struct phylink_config *config, 3347 unsigned int mode, 3348 const struct phylink_link_state *state) 3349 { 3350 struct dsa_port *dp = dsa_phylink_to_port(config); 3351 struct ksz_device *dev = dp->ds->priv; 3352 int port = dp->index; 3353 3354 /* Internal PHYs */ 3355 if (dev->info->internal_phy[port]) 3356 return; 3357 3358 if (phylink_autoneg_inband(mode)) { 3359 dev_err(dev->dev, "In-band AN not supported!\n"); 3360 return; 3361 } 3362 3363 ksz_set_xmii(dev, port, state->interface); 3364 3365 if (dev->dev_ops->setup_rgmii_delay) 3366 dev->dev_ops->setup_rgmii_delay(dev, port); 3367 } 3368 3369 bool ksz_get_gbit(struct ksz_device *dev, int port) 3370 { 3371 const u8 *bitval = dev->info->xmii_ctrl1; 3372 const u16 *regs = dev->info->regs; 3373 bool gbit = false; 3374 u8 data8; 3375 bool val; 3376 3377 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3378 3379 val = FIELD_GET(P_GMII_1GBIT_M, data8); 3380 3381 if (val == bitval[P_GMII_1GBIT]) 3382 gbit = true; 3383 3384 return gbit; 3385 } 3386 3387 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 3388 { 3389 const u8 *bitval = dev->info->xmii_ctrl1; 3390 const u16 *regs = dev->info->regs; 3391 u8 data8; 3392 3393 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3394 3395 data8 &= ~P_GMII_1GBIT_M; 3396 3397 if (gbit) 3398 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 3399 else 3400 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 3401 3402 /* Write the updated value */ 3403 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3404 } 3405 3406 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 3407 { 3408 const u8 *bitval = dev->info->xmii_ctrl0; 3409 const u16 *regs = dev->info->regs; 3410 u8 data8; 3411 3412 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 3413 3414 data8 &= ~P_MII_100MBIT_M; 3415 3416 if (speed == SPEED_100) 3417 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 3418 else 3419 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 3420 3421 /* Write the updated value */ 3422 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 3423 } 3424 3425 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 3426 { 3427 if (speed == SPEED_1000) 3428 ksz_set_gbit(dev, port, true); 3429 else 3430 ksz_set_gbit(dev, port, false); 3431 3432 if (speed == SPEED_100 || speed == SPEED_10) 3433 ksz_set_100_10mbit(dev, port, speed); 3434 } 3435 3436 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 3437 bool tx_pause, bool rx_pause) 3438 { 3439 const u8 *bitval = dev->info->xmii_ctrl0; 3440 const u32 *masks = dev->info->masks; 3441 const u16 *regs = dev->info->regs; 3442 u8 mask; 3443 u8 val; 3444 3445 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 3446 masks[P_MII_RX_FLOW_CTRL]; 3447 3448 if (duplex == DUPLEX_FULL) 3449 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 3450 else 3451 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 3452 3453 if (tx_pause) 3454 val |= masks[P_MII_TX_FLOW_CTRL]; 3455 3456 if (rx_pause) 3457 val |= masks[P_MII_RX_FLOW_CTRL]; 3458 3459 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 3460 } 3461 3462 static void ksz9477_phylink_mac_link_up(struct phylink_config *config, 3463 struct phy_device *phydev, 3464 unsigned int mode, 3465 phy_interface_t interface, 3466 int speed, int duplex, bool tx_pause, 3467 bool rx_pause) 3468 { 3469 struct dsa_port *dp = dsa_phylink_to_port(config); 3470 struct ksz_device *dev = dp->ds->priv; 3471 int port = dp->index; 3472 struct ksz_port *p; 3473 3474 p = &dev->ports[port]; 3475 3476 /* Internal PHYs */ 3477 if (dev->info->internal_phy[port]) 3478 return; 3479 3480 p->phydev.speed = speed; 3481 3482 ksz_port_set_xmii_speed(dev, port, speed); 3483 3484 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 3485 } 3486 3487 static int ksz_switch_detect(struct ksz_device *dev) 3488 { 3489 u8 id1, id2, id4; 3490 u16 id16; 3491 u32 id32; 3492 int ret; 3493 3494 /* read chip id */ 3495 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 3496 if (ret) 3497 return ret; 3498 3499 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 3500 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 3501 3502 switch (id1) { 3503 case KSZ87_FAMILY_ID: 3504 if (id2 == KSZ87_CHIP_ID_95) { 3505 u8 val; 3506 3507 dev->chip_id = KSZ8795_CHIP_ID; 3508 3509 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 3510 if (val & KSZ8_PORT_FIBER_MODE) 3511 dev->chip_id = KSZ8765_CHIP_ID; 3512 } else if (id2 == KSZ87_CHIP_ID_94) { 3513 dev->chip_id = KSZ8794_CHIP_ID; 3514 } else { 3515 return -ENODEV; 3516 } 3517 break; 3518 case KSZ88_FAMILY_ID: 3519 if (id2 == KSZ88_CHIP_ID_63) 3520 dev->chip_id = KSZ88X3_CHIP_ID; 3521 else 3522 return -ENODEV; 3523 break; 3524 case KSZ8895_FAMILY_ID: 3525 if (id2 == KSZ8895_CHIP_ID_95 || 3526 id2 == KSZ8895_CHIP_ID_95R) 3527 dev->chip_id = KSZ8895_CHIP_ID; 3528 else 3529 return -ENODEV; 3530 ret = ksz_read8(dev, REG_KSZ8864_CHIP_ID, &id4); 3531 if (ret) 3532 return ret; 3533 if (id4 & SW_KSZ8864) 3534 dev->chip_id = KSZ8864_CHIP_ID; 3535 break; 3536 default: 3537 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 3538 if (ret) 3539 return ret; 3540 3541 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 3542 id32 &= ~0xFF; 3543 3544 switch (id32) { 3545 case KSZ9477_CHIP_ID: 3546 case KSZ9896_CHIP_ID: 3547 case KSZ9897_CHIP_ID: 3548 case KSZ9567_CHIP_ID: 3549 case KSZ8567_CHIP_ID: 3550 case LAN9370_CHIP_ID: 3551 case LAN9371_CHIP_ID: 3552 case LAN9372_CHIP_ID: 3553 case LAN9373_CHIP_ID: 3554 case LAN9374_CHIP_ID: 3555 dev->chip_id = id32; 3556 break; 3557 case KSZ9893_CHIP_ID: 3558 ret = ksz_read8(dev, REG_CHIP_ID4, 3559 &id4); 3560 if (ret) 3561 return ret; 3562 3563 if (id4 == SKU_ID_KSZ8563) 3564 dev->chip_id = KSZ8563_CHIP_ID; 3565 else if (id4 == SKU_ID_KSZ9563) 3566 dev->chip_id = KSZ9563_CHIP_ID; 3567 else 3568 dev->chip_id = KSZ9893_CHIP_ID; 3569 3570 break; 3571 default: 3572 dev_err(dev->dev, 3573 "unsupported switch detected %x)\n", id32); 3574 return -ENODEV; 3575 } 3576 } 3577 return 0; 3578 } 3579 3580 static int ksz_cls_flower_add(struct dsa_switch *ds, int port, 3581 struct flow_cls_offload *cls, bool ingress) 3582 { 3583 struct ksz_device *dev = ds->priv; 3584 3585 switch (dev->chip_id) { 3586 case KSZ8563_CHIP_ID: 3587 case KSZ8567_CHIP_ID: 3588 case KSZ9477_CHIP_ID: 3589 case KSZ9563_CHIP_ID: 3590 case KSZ9567_CHIP_ID: 3591 case KSZ9893_CHIP_ID: 3592 case KSZ9896_CHIP_ID: 3593 case KSZ9897_CHIP_ID: 3594 return ksz9477_cls_flower_add(ds, port, cls, ingress); 3595 } 3596 3597 return -EOPNOTSUPP; 3598 } 3599 3600 static int ksz_cls_flower_del(struct dsa_switch *ds, int port, 3601 struct flow_cls_offload *cls, bool ingress) 3602 { 3603 struct ksz_device *dev = ds->priv; 3604 3605 switch (dev->chip_id) { 3606 case KSZ8563_CHIP_ID: 3607 case KSZ8567_CHIP_ID: 3608 case KSZ9477_CHIP_ID: 3609 case KSZ9563_CHIP_ID: 3610 case KSZ9567_CHIP_ID: 3611 case KSZ9893_CHIP_ID: 3612 case KSZ9896_CHIP_ID: 3613 case KSZ9897_CHIP_ID: 3614 return ksz9477_cls_flower_del(ds, port, cls, ingress); 3615 } 3616 3617 return -EOPNOTSUPP; 3618 } 3619 3620 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 3621 * is converted to Hex-decimal using the successive multiplication method. On 3622 * every step, integer part is taken and decimal part is carry forwarded. 3623 */ 3624 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 3625 { 3626 u32 cinc = 0; 3627 u32 txrate; 3628 u32 rate; 3629 u8 temp; 3630 u8 i; 3631 3632 txrate = idle_slope - send_slope; 3633 3634 if (!txrate) 3635 return -EINVAL; 3636 3637 rate = idle_slope; 3638 3639 /* 24 bit register */ 3640 for (i = 0; i < 6; i++) { 3641 rate = rate * 16; 3642 3643 temp = rate / txrate; 3644 3645 rate %= txrate; 3646 3647 cinc = ((cinc << 4) | temp); 3648 } 3649 3650 *bw = cinc; 3651 3652 return 0; 3653 } 3654 3655 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 3656 u8 shaper) 3657 { 3658 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 3659 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 3660 FIELD_PREP(MTI_SHAPING_M, shaper)); 3661 } 3662 3663 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 3664 struct tc_cbs_qopt_offload *qopt) 3665 { 3666 struct ksz_device *dev = ds->priv; 3667 int ret; 3668 u32 bw; 3669 3670 if (!dev->info->tc_cbs_supported) 3671 return -EOPNOTSUPP; 3672 3673 if (qopt->queue > dev->info->num_tx_queues) 3674 return -EINVAL; 3675 3676 /* Queue Selection */ 3677 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 3678 if (ret) 3679 return ret; 3680 3681 if (!qopt->enable) 3682 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3683 MTI_SHAPING_OFF); 3684 3685 /* High Credit */ 3686 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 3687 qopt->hicredit); 3688 if (ret) 3689 return ret; 3690 3691 /* Low Credit */ 3692 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 3693 qopt->locredit); 3694 if (ret) 3695 return ret; 3696 3697 /* Credit Increment Register */ 3698 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 3699 if (ret) 3700 return ret; 3701 3702 if (dev->dev_ops->tc_cbs_set_cinc) { 3703 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 3704 if (ret) 3705 return ret; 3706 } 3707 3708 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3709 MTI_SHAPING_SRP); 3710 } 3711 3712 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 3713 { 3714 int queue, ret; 3715 3716 /* Configuration will not take effect until the last Port Queue X 3717 * Egress Limit Control Register is written. 3718 */ 3719 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3720 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 3721 KSZ9477_OUT_RATE_NO_LIMIT); 3722 if (ret) 3723 return ret; 3724 } 3725 3726 return 0; 3727 } 3728 3729 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 3730 int band) 3731 { 3732 /* Compared to queues, bands prioritize packets differently. In strict 3733 * priority mode, the lowest priority is assigned to Queue 0 while the 3734 * highest priority is given to Band 0. 3735 */ 3736 return p->bands - 1 - band; 3737 } 3738 3739 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 3740 { 3741 int ret; 3742 3743 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3744 if (ret) 3745 return ret; 3746 3747 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3748 MTI_SHAPING_OFF); 3749 } 3750 3751 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 3752 int weight) 3753 { 3754 int ret; 3755 3756 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3757 if (ret) 3758 return ret; 3759 3760 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3761 MTI_SHAPING_OFF); 3762 if (ret) 3763 return ret; 3764 3765 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 3766 } 3767 3768 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 3769 struct tc_ets_qopt_offload_replace_params *p) 3770 { 3771 int ret, band, tc_prio; 3772 u32 queue_map = 0; 3773 3774 /* In order to ensure proper prioritization, it is necessary to set the 3775 * rate limit for the related queue to zero. Otherwise strict priority 3776 * or WRR mode will not work. This is a hardware limitation. 3777 */ 3778 ret = ksz_disable_egress_rate_limit(dev, port); 3779 if (ret) 3780 return ret; 3781 3782 /* Configure queue scheduling mode for all bands. Currently only strict 3783 * prio mode is supported. 3784 */ 3785 for (band = 0; band < p->bands; band++) { 3786 int queue = ksz_ets_band_to_queue(p, band); 3787 3788 ret = ksz_queue_set_strict(dev, port, queue); 3789 if (ret) 3790 return ret; 3791 } 3792 3793 /* Configure the mapping between traffic classes and queues. Note: 3794 * priomap variable support 16 traffic classes, but the chip can handle 3795 * only 8 classes. 3796 */ 3797 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 3798 int queue; 3799 3800 if (tc_prio >= dev->info->num_ipms) 3801 break; 3802 3803 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 3804 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3805 } 3806 3807 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3808 } 3809 3810 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 3811 { 3812 int ret, queue; 3813 3814 /* To restore the default chip configuration, set all queues to use the 3815 * WRR scheduler with a weight of 1. 3816 */ 3817 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3818 ret = ksz_queue_set_wrr(dev, port, queue, 3819 KSZ9477_DEFAULT_WRR_WEIGHT); 3820 if (ret) 3821 return ret; 3822 } 3823 3824 /* Revert the queue mapping for TC-priority to its default setting on 3825 * the chip. 3826 */ 3827 return ksz9477_set_default_prio_queue_mapping(dev, port); 3828 } 3829 3830 static int ksz_tc_ets_validate(struct ksz_device *dev, int port, 3831 struct tc_ets_qopt_offload_replace_params *p) 3832 { 3833 int band; 3834 3835 /* Since it is not feasible to share one port among multiple qdisc, 3836 * the user must configure all available queues appropriately. 3837 */ 3838 if (p->bands != dev->info->num_tx_queues) { 3839 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 3840 dev->info->num_tx_queues); 3841 return -EOPNOTSUPP; 3842 } 3843 3844 for (band = 0; band < p->bands; ++band) { 3845 /* The KSZ switches utilize a weighted round robin configuration 3846 * where a certain number of packets can be transmitted from a 3847 * queue before the next queue is serviced. For more information 3848 * on this, refer to section 5.2.8.4 of the KSZ8565R 3849 * documentation on the Port Transmit Queue Control 1 Register. 3850 * However, the current ETS Qdisc implementation (as of February 3851 * 2023) assigns a weight to each queue based on the number of 3852 * bytes or extrapolated bandwidth in percentages. Since this 3853 * differs from the KSZ switches' method and we don't want to 3854 * fake support by converting bytes to packets, it is better to 3855 * return an error instead. 3856 */ 3857 if (p->quanta[band]) { 3858 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 3859 return -EOPNOTSUPP; 3860 } 3861 } 3862 3863 return 0; 3864 } 3865 3866 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 3867 struct tc_ets_qopt_offload *qopt) 3868 { 3869 struct ksz_device *dev = ds->priv; 3870 int ret; 3871 3872 if (is_ksz8(dev)) 3873 return -EOPNOTSUPP; 3874 3875 if (qopt->parent != TC_H_ROOT) { 3876 dev_err(dev->dev, "Parent should be \"root\"\n"); 3877 return -EOPNOTSUPP; 3878 } 3879 3880 switch (qopt->command) { 3881 case TC_ETS_REPLACE: 3882 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 3883 if (ret) 3884 return ret; 3885 3886 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 3887 case TC_ETS_DESTROY: 3888 return ksz_tc_ets_del(dev, port); 3889 case TC_ETS_STATS: 3890 case TC_ETS_GRAFT: 3891 return -EOPNOTSUPP; 3892 } 3893 3894 return -EOPNOTSUPP; 3895 } 3896 3897 static int ksz_setup_tc(struct dsa_switch *ds, int port, 3898 enum tc_setup_type type, void *type_data) 3899 { 3900 switch (type) { 3901 case TC_SETUP_QDISC_CBS: 3902 return ksz_setup_tc_cbs(ds, port, type_data); 3903 case TC_SETUP_QDISC_ETS: 3904 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 3905 default: 3906 return -EOPNOTSUPP; 3907 } 3908 } 3909 3910 /** 3911 * ksz_handle_wake_reason - Handle wake reason on a specified port. 3912 * @dev: The device structure. 3913 * @port: The port number. 3914 * 3915 * This function reads the PME (Power Management Event) status register of a 3916 * specified port to determine the wake reason. If there is no wake event, it 3917 * returns early. Otherwise, it logs the wake reason which could be due to a 3918 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register 3919 * is then cleared to acknowledge the handling of the wake event. 3920 * 3921 * Return: 0 on success, or an error code on failure. 3922 */ 3923 int ksz_handle_wake_reason(struct ksz_device *dev, int port) 3924 { 3925 const struct ksz_dev_ops *ops = dev->dev_ops; 3926 const u16 *regs = dev->info->regs; 3927 u8 pme_status; 3928 int ret; 3929 3930 ret = ops->pme_pread8(dev, port, regs[REG_PORT_PME_STATUS], 3931 &pme_status); 3932 if (ret) 3933 return ret; 3934 3935 if (!pme_status) 3936 return 0; 3937 3938 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port, 3939 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "", 3940 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "", 3941 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : ""); 3942 3943 return ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_STATUS], 3944 pme_status); 3945 } 3946 3947 /** 3948 * ksz_get_wol - Get Wake-on-LAN settings for a specified port. 3949 * @ds: The dsa_switch structure. 3950 * @port: The port number. 3951 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 3952 * 3953 * This function checks the device PME wakeup_source flag and chip_id. 3954 * If enabled and supported, it sets the supported and active WoL 3955 * flags. 3956 */ 3957 static void ksz_get_wol(struct dsa_switch *ds, int port, 3958 struct ethtool_wolinfo *wol) 3959 { 3960 struct ksz_device *dev = ds->priv; 3961 const u16 *regs = dev->info->regs; 3962 u8 pme_ctrl; 3963 int ret; 3964 3965 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 3966 return; 3967 3968 if (!dev->wakeup_source) 3969 return; 3970 3971 wol->supported = WAKE_PHY; 3972 3973 /* Check if the current MAC address on this port can be set 3974 * as global for WAKE_MAGIC support. The result may vary 3975 * dynamically based on other ports configurations. 3976 */ 3977 if (ksz_is_port_mac_global_usable(dev->ds, port)) 3978 wol->supported |= WAKE_MAGIC; 3979 3980 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 3981 &pme_ctrl); 3982 if (ret) 3983 return; 3984 3985 if (pme_ctrl & PME_WOL_MAGICPKT) 3986 wol->wolopts |= WAKE_MAGIC; 3987 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY)) 3988 wol->wolopts |= WAKE_PHY; 3989 } 3990 3991 /** 3992 * ksz_set_wol - Set Wake-on-LAN settings for a specified port. 3993 * @ds: The dsa_switch structure. 3994 * @port: The port number. 3995 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 3996 * 3997 * This function configures Wake-on-LAN (WoL) settings for a specified 3998 * port. It validates the provided WoL options, checks if PME is 3999 * enabled and supported, clears any previous wake reasons, and sets 4000 * the Magic Packet flag in the port's PME control register if 4001 * specified. 4002 * 4003 * Return: 0 on success, or other error codes on failure. 4004 */ 4005 static int ksz_set_wol(struct dsa_switch *ds, int port, 4006 struct ethtool_wolinfo *wol) 4007 { 4008 u8 pme_ctrl = 0, pme_ctrl_old = 0; 4009 struct ksz_device *dev = ds->priv; 4010 const u16 *regs = dev->info->regs; 4011 bool magic_switched_off; 4012 bool magic_switched_on; 4013 int ret; 4014 4015 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC)) 4016 return -EINVAL; 4017 4018 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4019 return -EOPNOTSUPP; 4020 4021 if (!dev->wakeup_source) 4022 return -EOPNOTSUPP; 4023 4024 ret = ksz_handle_wake_reason(dev, port); 4025 if (ret) 4026 return ret; 4027 4028 if (wol->wolopts & WAKE_MAGIC) 4029 pme_ctrl |= PME_WOL_MAGICPKT; 4030 if (wol->wolopts & WAKE_PHY) 4031 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY; 4032 4033 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 4034 &pme_ctrl_old); 4035 if (ret) 4036 return ret; 4037 4038 if (pme_ctrl_old == pme_ctrl) 4039 return 0; 4040 4041 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) && 4042 !(pme_ctrl & PME_WOL_MAGICPKT); 4043 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) && 4044 (pme_ctrl & PME_WOL_MAGICPKT); 4045 4046 /* To keep reference count of MAC address, we should do this 4047 * operation only on change of WOL settings. 4048 */ 4049 if (magic_switched_on) { 4050 ret = ksz_switch_macaddr_get(dev->ds, port, NULL); 4051 if (ret) 4052 return ret; 4053 } else if (magic_switched_off) { 4054 ksz_switch_macaddr_put(dev->ds); 4055 } 4056 4057 ret = dev->dev_ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 4058 pme_ctrl); 4059 if (ret) { 4060 if (magic_switched_on) 4061 ksz_switch_macaddr_put(dev->ds); 4062 return ret; 4063 } 4064 4065 return 0; 4066 } 4067 4068 /** 4069 * ksz_wol_pre_shutdown - Prepares the switch device for shutdown while 4070 * considering Wake-on-LAN (WoL) settings. 4071 * @dev: The switch device structure. 4072 * @wol_enabled: Pointer to a boolean which will be set to true if WoL is 4073 * enabled on any port. 4074 * 4075 * This function prepares the switch device for a safe shutdown while taking 4076 * into account the Wake-on-LAN (WoL) settings on the user ports. It updates 4077 * the wol_enabled flag accordingly to reflect whether WoL is active on any 4078 * port. 4079 */ 4080 static void ksz_wol_pre_shutdown(struct ksz_device *dev, bool *wol_enabled) 4081 { 4082 const struct ksz_dev_ops *ops = dev->dev_ops; 4083 const u16 *regs = dev->info->regs; 4084 u8 pme_pin_en = PME_ENABLE; 4085 struct dsa_port *dp; 4086 int ret; 4087 4088 *wol_enabled = false; 4089 4090 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4091 return; 4092 4093 if (!dev->wakeup_source) 4094 return; 4095 4096 dsa_switch_for_each_user_port(dp, dev->ds) { 4097 u8 pme_ctrl = 0; 4098 4099 ret = ops->pme_pread8(dev, dp->index, 4100 regs[REG_PORT_PME_CTRL], &pme_ctrl); 4101 if (!ret && pme_ctrl) 4102 *wol_enabled = true; 4103 4104 /* make sure there are no pending wake events which would 4105 * prevent the device from going to sleep/shutdown. 4106 */ 4107 ksz_handle_wake_reason(dev, dp->index); 4108 } 4109 4110 /* Now we are save to enable PME pin. */ 4111 if (*wol_enabled) { 4112 if (dev->pme_active_high) 4113 pme_pin_en |= PME_POLARITY; 4114 ops->pme_write8(dev, regs[REG_SW_PME_CTRL], pme_pin_en); 4115 if (ksz_is_ksz87xx(dev)) 4116 ksz_write8(dev, KSZ87XX_REG_INT_EN, KSZ87XX_INT_PME_MASK); 4117 } 4118 } 4119 4120 static int ksz_port_set_mac_address(struct dsa_switch *ds, int port, 4121 const unsigned char *addr) 4122 { 4123 struct dsa_port *dp = dsa_to_port(ds, port); 4124 struct ethtool_wolinfo wol; 4125 4126 if (dp->hsr_dev) { 4127 dev_err(ds->dev, 4128 "Cannot change MAC address on port %d with active HSR offload\n", 4129 port); 4130 return -EBUSY; 4131 } 4132 4133 /* Need to initialize variable as the code to fill in settings may 4134 * not be executed. 4135 */ 4136 wol.wolopts = 0; 4137 4138 ksz_get_wol(ds, dp->index, &wol); 4139 if (wol.wolopts & WAKE_MAGIC) { 4140 dev_err(ds->dev, 4141 "Cannot change MAC address on port %d with active Wake on Magic Packet\n", 4142 port); 4143 return -EBUSY; 4144 } 4145 4146 return 0; 4147 } 4148 4149 /** 4150 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port 4151 * can be used as a global address. 4152 * @ds: Pointer to the DSA switch structure. 4153 * @port: The port number on which the MAC address is to be checked. 4154 * 4155 * This function examines the MAC address set on the specified port and 4156 * determines if it can be used as a global address for the switch. 4157 * 4158 * Return: true if the port's MAC address can be used as a global address, false 4159 * otherwise. 4160 */ 4161 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port) 4162 { 4163 struct net_device *user = dsa_to_port(ds, port)->user; 4164 const unsigned char *addr = user->dev_addr; 4165 struct ksz_switch_macaddr *switch_macaddr; 4166 struct ksz_device *dev = ds->priv; 4167 4168 ASSERT_RTNL(); 4169 4170 switch_macaddr = dev->switch_macaddr; 4171 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr)) 4172 return false; 4173 4174 return true; 4175 } 4176 4177 /** 4178 * ksz_switch_macaddr_get - Program the switch's MAC address register. 4179 * @ds: DSA switch instance. 4180 * @port: Port number. 4181 * @extack: Netlink extended acknowledgment. 4182 * 4183 * This function programs the switch's MAC address register with the MAC address 4184 * of the requesting user port. This single address is used by the switch for 4185 * multiple features like HSR self-address filtering and WoL. Other user ports 4186 * can share ownership of this address as long as their MAC address is the same. 4187 * The MAC addresses of user ports must not change while they have ownership of 4188 * the switch MAC address. 4189 * 4190 * Return: 0 on success, or other error codes on failure. 4191 */ 4192 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 4193 struct netlink_ext_ack *extack) 4194 { 4195 struct net_device *user = dsa_to_port(ds, port)->user; 4196 const unsigned char *addr = user->dev_addr; 4197 struct ksz_switch_macaddr *switch_macaddr; 4198 struct ksz_device *dev = ds->priv; 4199 const u16 *regs = dev->info->regs; 4200 int i, ret; 4201 4202 /* Make sure concurrent MAC address changes are blocked */ 4203 ASSERT_RTNL(); 4204 4205 switch_macaddr = dev->switch_macaddr; 4206 if (switch_macaddr) { 4207 if (!ether_addr_equal(switch_macaddr->addr, addr)) { 4208 NL_SET_ERR_MSG_FMT_MOD(extack, 4209 "Switch already configured for MAC address %pM", 4210 switch_macaddr->addr); 4211 return -EBUSY; 4212 } 4213 4214 refcount_inc(&switch_macaddr->refcount); 4215 return 0; 4216 } 4217 4218 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL); 4219 if (!switch_macaddr) 4220 return -ENOMEM; 4221 4222 ether_addr_copy(switch_macaddr->addr, addr); 4223 refcount_set(&switch_macaddr->refcount, 1); 4224 dev->switch_macaddr = switch_macaddr; 4225 4226 /* Program the switch MAC address to hardware */ 4227 for (i = 0; i < ETH_ALEN; i++) { 4228 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, addr[i]); 4229 if (ret) 4230 goto macaddr_drop; 4231 } 4232 4233 return 0; 4234 4235 macaddr_drop: 4236 dev->switch_macaddr = NULL; 4237 refcount_set(&switch_macaddr->refcount, 0); 4238 kfree(switch_macaddr); 4239 4240 return ret; 4241 } 4242 4243 void ksz_switch_macaddr_put(struct dsa_switch *ds) 4244 { 4245 struct ksz_switch_macaddr *switch_macaddr; 4246 struct ksz_device *dev = ds->priv; 4247 const u16 *regs = dev->info->regs; 4248 int i; 4249 4250 /* Make sure concurrent MAC address changes are blocked */ 4251 ASSERT_RTNL(); 4252 4253 switch_macaddr = dev->switch_macaddr; 4254 if (!refcount_dec_and_test(&switch_macaddr->refcount)) 4255 return; 4256 4257 for (i = 0; i < ETH_ALEN; i++) 4258 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0); 4259 4260 dev->switch_macaddr = NULL; 4261 kfree(switch_macaddr); 4262 } 4263 4264 static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr, 4265 struct netlink_ext_ack *extack) 4266 { 4267 struct ksz_device *dev = ds->priv; 4268 enum hsr_version ver; 4269 int ret; 4270 4271 ret = hsr_get_version(hsr, &ver); 4272 if (ret) 4273 return ret; 4274 4275 if (dev->chip_id != KSZ9477_CHIP_ID) { 4276 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload"); 4277 return -EOPNOTSUPP; 4278 } 4279 4280 /* KSZ9477 can support HW offloading of only 1 HSR device */ 4281 if (dev->hsr_dev && hsr != dev->hsr_dev) { 4282 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR"); 4283 return -EOPNOTSUPP; 4284 } 4285 4286 /* KSZ9477 only supports HSR v0 and v1 */ 4287 if (!(ver == HSR_V0 || ver == HSR_V1)) { 4288 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported"); 4289 return -EOPNOTSUPP; 4290 } 4291 4292 /* KSZ9477 can only perform HSR offloading for up to two ports */ 4293 if (hweight8(dev->hsr_ports) >= 2) { 4294 NL_SET_ERR_MSG_MOD(extack, 4295 "Cannot offload more than two ports - using software HSR"); 4296 return -EOPNOTSUPP; 4297 } 4298 4299 /* Self MAC address filtering, to avoid frames traversing 4300 * the HSR ring more than once. 4301 */ 4302 ret = ksz_switch_macaddr_get(ds, port, extack); 4303 if (ret) 4304 return ret; 4305 4306 ksz9477_hsr_join(ds, port, hsr); 4307 dev->hsr_dev = hsr; 4308 dev->hsr_ports |= BIT(port); 4309 4310 return 0; 4311 } 4312 4313 static int ksz_hsr_leave(struct dsa_switch *ds, int port, 4314 struct net_device *hsr) 4315 { 4316 struct ksz_device *dev = ds->priv; 4317 4318 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID); 4319 4320 ksz9477_hsr_leave(ds, port, hsr); 4321 dev->hsr_ports &= ~BIT(port); 4322 if (!dev->hsr_ports) 4323 dev->hsr_dev = NULL; 4324 4325 ksz_switch_macaddr_put(ds); 4326 4327 return 0; 4328 } 4329 4330 static const struct dsa_switch_ops ksz_switch_ops = { 4331 .get_tag_protocol = ksz_get_tag_protocol, 4332 .connect_tag_protocol = ksz_connect_tag_protocol, 4333 .get_phy_flags = ksz_get_phy_flags, 4334 .setup = ksz_setup, 4335 .teardown = ksz_teardown, 4336 .phy_read = ksz_phy_read16, 4337 .phy_write = ksz_phy_write16, 4338 .phylink_get_caps = ksz_phylink_get_caps, 4339 .port_setup = ksz_port_setup, 4340 .set_ageing_time = ksz_set_ageing_time, 4341 .get_strings = ksz_get_strings, 4342 .get_ethtool_stats = ksz_get_ethtool_stats, 4343 .get_sset_count = ksz_sset_count, 4344 .port_bridge_join = ksz_port_bridge_join, 4345 .port_bridge_leave = ksz_port_bridge_leave, 4346 .port_hsr_join = ksz_hsr_join, 4347 .port_hsr_leave = ksz_hsr_leave, 4348 .port_set_mac_address = ksz_port_set_mac_address, 4349 .port_stp_state_set = ksz_port_stp_state_set, 4350 .port_teardown = ksz_port_teardown, 4351 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 4352 .port_bridge_flags = ksz_port_bridge_flags, 4353 .port_fast_age = ksz_port_fast_age, 4354 .port_vlan_filtering = ksz_port_vlan_filtering, 4355 .port_vlan_add = ksz_port_vlan_add, 4356 .port_vlan_del = ksz_port_vlan_del, 4357 .port_fdb_dump = ksz_port_fdb_dump, 4358 .port_fdb_add = ksz_port_fdb_add, 4359 .port_fdb_del = ksz_port_fdb_del, 4360 .port_mdb_add = ksz_port_mdb_add, 4361 .port_mdb_del = ksz_port_mdb_del, 4362 .port_mirror_add = ksz_port_mirror_add, 4363 .port_mirror_del = ksz_port_mirror_del, 4364 .get_stats64 = ksz_get_stats64, 4365 .get_pause_stats = ksz_get_pause_stats, 4366 .port_change_mtu = ksz_change_mtu, 4367 .port_max_mtu = ksz_max_mtu, 4368 .get_wol = ksz_get_wol, 4369 .set_wol = ksz_set_wol, 4370 .get_ts_info = ksz_get_ts_info, 4371 .port_hwtstamp_get = ksz_hwtstamp_get, 4372 .port_hwtstamp_set = ksz_hwtstamp_set, 4373 .port_txtstamp = ksz_port_txtstamp, 4374 .port_rxtstamp = ksz_port_rxtstamp, 4375 .cls_flower_add = ksz_cls_flower_add, 4376 .cls_flower_del = ksz_cls_flower_del, 4377 .port_setup_tc = ksz_setup_tc, 4378 .get_mac_eee = ksz_get_mac_eee, 4379 .set_mac_eee = ksz_set_mac_eee, 4380 .port_get_default_prio = ksz_port_get_default_prio, 4381 .port_set_default_prio = ksz_port_set_default_prio, 4382 .port_get_dscp_prio = ksz_port_get_dscp_prio, 4383 .port_add_dscp_prio = ksz_port_add_dscp_prio, 4384 .port_del_dscp_prio = ksz_port_del_dscp_prio, 4385 .port_get_apptrust = ksz_port_get_apptrust, 4386 .port_set_apptrust = ksz_port_set_apptrust, 4387 }; 4388 4389 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 4390 { 4391 struct dsa_switch *ds; 4392 struct ksz_device *swdev; 4393 4394 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 4395 if (!ds) 4396 return NULL; 4397 4398 ds->dev = base; 4399 ds->num_ports = DSA_MAX_PORTS; 4400 ds->ops = &ksz_switch_ops; 4401 4402 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 4403 if (!swdev) 4404 return NULL; 4405 4406 ds->priv = swdev; 4407 swdev->dev = base; 4408 4409 swdev->ds = ds; 4410 swdev->priv = priv; 4411 4412 return swdev; 4413 } 4414 EXPORT_SYMBOL(ksz_switch_alloc); 4415 4416 /** 4417 * ksz_switch_shutdown - Shutdown routine for the switch device. 4418 * @dev: The switch device structure. 4419 * 4420 * This function is responsible for initiating a shutdown sequence for the 4421 * switch device. It invokes the reset operation defined in the device 4422 * operations, if available, to reset the switch. Subsequently, it calls the 4423 * DSA framework's shutdown function to ensure a proper shutdown of the DSA 4424 * switch. 4425 */ 4426 void ksz_switch_shutdown(struct ksz_device *dev) 4427 { 4428 bool wol_enabled = false; 4429 4430 ksz_wol_pre_shutdown(dev, &wol_enabled); 4431 4432 if (dev->dev_ops->reset && !wol_enabled) 4433 dev->dev_ops->reset(dev); 4434 4435 dsa_switch_shutdown(dev->ds); 4436 } 4437 EXPORT_SYMBOL(ksz_switch_shutdown); 4438 4439 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 4440 struct device_node *port_dn) 4441 { 4442 phy_interface_t phy_mode = dev->ports[port_num].interface; 4443 int rx_delay = -1, tx_delay = -1; 4444 4445 if (!phy_interface_mode_is_rgmii(phy_mode)) 4446 return; 4447 4448 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 4449 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 4450 4451 if (rx_delay == -1 && tx_delay == -1) { 4452 dev_warn(dev->dev, 4453 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 4454 "please update device tree to specify \"rx-internal-delay-ps\" and " 4455 "\"tx-internal-delay-ps\"", 4456 port_num); 4457 4458 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 4459 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 4460 rx_delay = 2000; 4461 4462 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 4463 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 4464 tx_delay = 2000; 4465 } 4466 4467 if (rx_delay < 0) 4468 rx_delay = 0; 4469 if (tx_delay < 0) 4470 tx_delay = 0; 4471 4472 dev->ports[port_num].rgmii_rx_val = rx_delay; 4473 dev->ports[port_num].rgmii_tx_val = tx_delay; 4474 } 4475 4476 /** 4477 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding 4478 * register value. 4479 * @array: The array of drive strength values to search. 4480 * @array_size: The size of the array. 4481 * @microamp: The drive strength value in microamp to be converted. 4482 * 4483 * This function searches the array of drive strength values for the given 4484 * microamp value and returns the corresponding register value for that drive. 4485 * 4486 * Returns: If found, the corresponding register value for that drive strength 4487 * is returned. Otherwise, -EINVAL is returned indicating an invalid value. 4488 */ 4489 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array, 4490 size_t array_size, int microamp) 4491 { 4492 int i; 4493 4494 for (i = 0; i < array_size; i++) { 4495 if (array[i].microamp == microamp) 4496 return array[i].reg_val; 4497 } 4498 4499 return -EINVAL; 4500 } 4501 4502 /** 4503 * ksz_drive_strength_error() - Report invalid drive strength value 4504 * @dev: ksz device 4505 * @array: The array of drive strength values to search. 4506 * @array_size: The size of the array. 4507 * @microamp: Invalid drive strength value in microamp 4508 * 4509 * This function logs an error message when an unsupported drive strength value 4510 * is detected. It lists out all the supported drive strength values for 4511 * reference in the error message. 4512 */ 4513 static void ksz_drive_strength_error(struct ksz_device *dev, 4514 const struct ksz_drive_strength *array, 4515 size_t array_size, int microamp) 4516 { 4517 char supported_values[100]; 4518 size_t remaining_size; 4519 int added_len; 4520 char *ptr; 4521 int i; 4522 4523 remaining_size = sizeof(supported_values); 4524 ptr = supported_values; 4525 4526 for (i = 0; i < array_size; i++) { 4527 added_len = snprintf(ptr, remaining_size, 4528 i == 0 ? "%d" : ", %d", array[i].microamp); 4529 4530 if (added_len >= remaining_size) 4531 break; 4532 4533 ptr += added_len; 4534 remaining_size -= added_len; 4535 } 4536 4537 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n", 4538 microamp, supported_values); 4539 } 4540 4541 /** 4542 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477 4543 * chip variants. 4544 * @dev: ksz device 4545 * @props: Array of drive strength properties to be applied 4546 * @num_props: Number of properties in the array 4547 * 4548 * This function configures the drive strength for various KSZ9477 chip variants 4549 * based on the provided properties. It handles chip-specific nuances and 4550 * ensures only valid drive strengths are written to the respective chip. 4551 * 4552 * Return: 0 on successful configuration, a negative error code on failure. 4553 */ 4554 static int ksz9477_drive_strength_write(struct ksz_device *dev, 4555 struct ksz_driver_strength_prop *props, 4556 int num_props) 4557 { 4558 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths); 4559 int i, ret, reg; 4560 u8 mask = 0; 4561 u8 val = 0; 4562 4563 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1) 4564 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4565 props[KSZ_DRIVER_STRENGTH_IO].name); 4566 4567 if (dev->chip_id == KSZ8795_CHIP_ID || 4568 dev->chip_id == KSZ8794_CHIP_ID || 4569 dev->chip_id == KSZ8765_CHIP_ID) 4570 reg = KSZ8795_REG_SW_CTRL_20; 4571 else 4572 reg = KSZ9477_REG_SW_IO_STRENGTH; 4573 4574 for (i = 0; i < num_props; i++) { 4575 if (props[i].value == -1) 4576 continue; 4577 4578 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths, 4579 array_size, props[i].value); 4580 if (ret < 0) { 4581 ksz_drive_strength_error(dev, ksz9477_drive_strengths, 4582 array_size, props[i].value); 4583 return ret; 4584 } 4585 4586 mask |= SW_DRIVE_STRENGTH_M << props[i].offset; 4587 val |= ret << props[i].offset; 4588 } 4589 4590 return ksz_rmw8(dev, reg, mask, val); 4591 } 4592 4593 /** 4594 * ksz88x3_drive_strength_write() - Set the drive strength configuration for 4595 * KSZ8863 compatible chip variants. 4596 * @dev: ksz device 4597 * @props: Array of drive strength properties to be set 4598 * @num_props: Number of properties in the array 4599 * 4600 * This function applies the specified drive strength settings to KSZ88X3 chip 4601 * variants (KSZ8873, KSZ8863). 4602 * It ensures the configurations align with what the chip variant supports and 4603 * warns or errors out on unsupported settings. 4604 * 4605 * Return: 0 on success, error code otherwise 4606 */ 4607 static int ksz88x3_drive_strength_write(struct ksz_device *dev, 4608 struct ksz_driver_strength_prop *props, 4609 int num_props) 4610 { 4611 size_t array_size = ARRAY_SIZE(ksz88x3_drive_strengths); 4612 int microamp; 4613 int i, ret; 4614 4615 for (i = 0; i < num_props; i++) { 4616 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO) 4617 continue; 4618 4619 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4620 props[i].name); 4621 } 4622 4623 microamp = props[KSZ_DRIVER_STRENGTH_IO].value; 4624 ret = ksz_drive_strength_to_reg(ksz88x3_drive_strengths, array_size, 4625 microamp); 4626 if (ret < 0) { 4627 ksz_drive_strength_error(dev, ksz88x3_drive_strengths, 4628 array_size, microamp); 4629 return ret; 4630 } 4631 4632 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12, 4633 KSZ8873_DRIVE_STRENGTH_16MA, ret); 4634 } 4635 4636 /** 4637 * ksz_parse_drive_strength() - Extract and apply drive strength configurations 4638 * from device tree properties. 4639 * @dev: ksz device 4640 * 4641 * This function reads the specified drive strength properties from the 4642 * device tree, validates against the supported chip variants, and sets 4643 * them accordingly. An error should be critical here, as the drive strength 4644 * settings are crucial for EMI compliance. 4645 * 4646 * Return: 0 on success, error code otherwise 4647 */ 4648 static int ksz_parse_drive_strength(struct ksz_device *dev) 4649 { 4650 struct ksz_driver_strength_prop of_props[] = { 4651 [KSZ_DRIVER_STRENGTH_HI] = { 4652 .name = "microchip,hi-drive-strength-microamp", 4653 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S, 4654 .value = -1, 4655 }, 4656 [KSZ_DRIVER_STRENGTH_LO] = { 4657 .name = "microchip,lo-drive-strength-microamp", 4658 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S, 4659 .value = -1, 4660 }, 4661 [KSZ_DRIVER_STRENGTH_IO] = { 4662 .name = "microchip,io-drive-strength-microamp", 4663 .offset = 0, /* don't care */ 4664 .value = -1, 4665 }, 4666 }; 4667 struct device_node *np = dev->dev->of_node; 4668 bool have_any_prop = false; 4669 int i, ret; 4670 4671 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4672 ret = of_property_read_u32(np, of_props[i].name, 4673 &of_props[i].value); 4674 if (ret && ret != -EINVAL) 4675 dev_warn(dev->dev, "Failed to read %s\n", 4676 of_props[i].name); 4677 if (ret) 4678 continue; 4679 4680 have_any_prop = true; 4681 } 4682 4683 if (!have_any_prop) 4684 return 0; 4685 4686 switch (dev->chip_id) { 4687 case KSZ88X3_CHIP_ID: 4688 return ksz88x3_drive_strength_write(dev, of_props, 4689 ARRAY_SIZE(of_props)); 4690 case KSZ8795_CHIP_ID: 4691 case KSZ8794_CHIP_ID: 4692 case KSZ8765_CHIP_ID: 4693 case KSZ8563_CHIP_ID: 4694 case KSZ8567_CHIP_ID: 4695 case KSZ9477_CHIP_ID: 4696 case KSZ9563_CHIP_ID: 4697 case KSZ9567_CHIP_ID: 4698 case KSZ9893_CHIP_ID: 4699 case KSZ9896_CHIP_ID: 4700 case KSZ9897_CHIP_ID: 4701 return ksz9477_drive_strength_write(dev, of_props, 4702 ARRAY_SIZE(of_props)); 4703 default: 4704 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4705 if (of_props[i].value == -1) 4706 continue; 4707 4708 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4709 of_props[i].name); 4710 } 4711 } 4712 4713 return 0; 4714 } 4715 4716 int ksz_switch_register(struct ksz_device *dev) 4717 { 4718 const struct ksz_chip_data *info; 4719 struct device_node *ports; 4720 phy_interface_t interface; 4721 unsigned int port_num; 4722 int ret; 4723 int i; 4724 4725 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 4726 GPIOD_OUT_LOW); 4727 if (IS_ERR(dev->reset_gpio)) 4728 return PTR_ERR(dev->reset_gpio); 4729 4730 if (dev->reset_gpio) { 4731 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4732 usleep_range(10000, 12000); 4733 gpiod_set_value_cansleep(dev->reset_gpio, 0); 4734 msleep(100); 4735 } 4736 4737 mutex_init(&dev->dev_mutex); 4738 mutex_init(&dev->regmap_mutex); 4739 mutex_init(&dev->alu_mutex); 4740 mutex_init(&dev->vlan_mutex); 4741 4742 ret = ksz_switch_detect(dev); 4743 if (ret) 4744 return ret; 4745 4746 info = ksz_lookup_info(dev->chip_id); 4747 if (!info) 4748 return -ENODEV; 4749 4750 /* Update the compatible info with the probed one */ 4751 dev->info = info; 4752 4753 dev_info(dev->dev, "found switch: %s, rev %i\n", 4754 dev->info->dev_name, dev->chip_rev); 4755 4756 ret = ksz_check_device_id(dev); 4757 if (ret) 4758 return ret; 4759 4760 dev->dev_ops = dev->info->ops; 4761 4762 ret = dev->dev_ops->init(dev); 4763 if (ret) 4764 return ret; 4765 4766 dev->ports = devm_kzalloc(dev->dev, 4767 dev->info->port_cnt * sizeof(struct ksz_port), 4768 GFP_KERNEL); 4769 if (!dev->ports) 4770 return -ENOMEM; 4771 4772 for (i = 0; i < dev->info->port_cnt; i++) { 4773 spin_lock_init(&dev->ports[i].mib.stats64_lock); 4774 mutex_init(&dev->ports[i].mib.cnt_mutex); 4775 dev->ports[i].mib.counters = 4776 devm_kzalloc(dev->dev, 4777 sizeof(u64) * (dev->info->mib_cnt + 1), 4778 GFP_KERNEL); 4779 if (!dev->ports[i].mib.counters) 4780 return -ENOMEM; 4781 4782 dev->ports[i].ksz_dev = dev; 4783 dev->ports[i].num = i; 4784 } 4785 4786 /* set the real number of ports */ 4787 dev->ds->num_ports = dev->info->port_cnt; 4788 4789 /* set the phylink ops */ 4790 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops; 4791 4792 /* Host port interface will be self detected, or specifically set in 4793 * device tree. 4794 */ 4795 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 4796 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 4797 if (dev->dev->of_node) { 4798 ret = of_get_phy_mode(dev->dev->of_node, &interface); 4799 if (ret == 0) 4800 dev->compat_interface = interface; 4801 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 4802 if (!ports) 4803 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 4804 if (ports) { 4805 for_each_available_child_of_node_scoped(ports, port) { 4806 if (of_property_read_u32(port, "reg", 4807 &port_num)) 4808 continue; 4809 if (!(dev->port_mask & BIT(port_num))) { 4810 of_node_put(ports); 4811 return -EINVAL; 4812 } 4813 of_get_phy_mode(port, 4814 &dev->ports[port_num].interface); 4815 4816 ksz_parse_rgmii_delay(dev, port_num, port); 4817 } 4818 of_node_put(ports); 4819 } 4820 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 4821 "microchip,synclko-125"); 4822 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 4823 "microchip,synclko-disable"); 4824 if (dev->synclko_125 && dev->synclko_disable) { 4825 dev_err(dev->dev, "inconsistent synclko settings\n"); 4826 return -EINVAL; 4827 } 4828 4829 dev->wakeup_source = of_property_read_bool(dev->dev->of_node, 4830 "wakeup-source"); 4831 dev->pme_active_high = of_property_read_bool(dev->dev->of_node, 4832 "microchip,pme-active-high"); 4833 } 4834 4835 ret = dsa_register_switch(dev->ds); 4836 if (ret) { 4837 dev->dev_ops->exit(dev); 4838 return ret; 4839 } 4840 4841 /* Read MIB counters every 30 seconds to avoid overflow. */ 4842 dev->mib_read_interval = msecs_to_jiffies(5000); 4843 4844 /* Start the MIB timer. */ 4845 schedule_delayed_work(&dev->mib_read, 0); 4846 4847 return ret; 4848 } 4849 EXPORT_SYMBOL(ksz_switch_register); 4850 4851 void ksz_switch_remove(struct ksz_device *dev) 4852 { 4853 /* timer started */ 4854 if (dev->mib_read_interval) { 4855 dev->mib_read_interval = 0; 4856 cancel_delayed_work_sync(&dev->mib_read); 4857 } 4858 4859 dev->dev_ops->exit(dev); 4860 dsa_unregister_switch(dev->ds); 4861 4862 if (dev->reset_gpio) 4863 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4864 4865 } 4866 EXPORT_SYMBOL(ksz_switch_remove); 4867 4868 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 4869 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 4870 MODULE_LICENSE("GPL"); 4871