1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/if_hsr.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/of.h> 23 #include <linux/of_mdio.h> 24 #include <linux/of_net.h> 25 #include <linux/micrel_phy.h> 26 #include <net/dsa.h> 27 #include <net/pkt_cls.h> 28 #include <net/switchdev.h> 29 30 #include "ksz_common.h" 31 #include "ksz_ptp.h" 32 #include "ksz8.h" 33 #include "ksz9477.h" 34 #include "lan937x.h" 35 36 #define MIB_COUNTER_NUM 0x20 37 38 struct ksz_stats_raw { 39 u64 rx_hi; 40 u64 rx_undersize; 41 u64 rx_fragments; 42 u64 rx_oversize; 43 u64 rx_jabbers; 44 u64 rx_symbol_err; 45 u64 rx_crc_err; 46 u64 rx_align_err; 47 u64 rx_mac_ctrl; 48 u64 rx_pause; 49 u64 rx_bcast; 50 u64 rx_mcast; 51 u64 rx_ucast; 52 u64 rx_64_or_less; 53 u64 rx_65_127; 54 u64 rx_128_255; 55 u64 rx_256_511; 56 u64 rx_512_1023; 57 u64 rx_1024_1522; 58 u64 rx_1523_2000; 59 u64 rx_2001; 60 u64 tx_hi; 61 u64 tx_late_col; 62 u64 tx_pause; 63 u64 tx_bcast; 64 u64 tx_mcast; 65 u64 tx_ucast; 66 u64 tx_deferred; 67 u64 tx_total_col; 68 u64 tx_exc_col; 69 u64 tx_single_col; 70 u64 tx_mult_col; 71 u64 rx_total; 72 u64 tx_total; 73 u64 rx_discards; 74 u64 tx_discards; 75 }; 76 77 struct ksz88xx_stats_raw { 78 u64 rx; 79 u64 rx_hi; 80 u64 rx_undersize; 81 u64 rx_fragments; 82 u64 rx_oversize; 83 u64 rx_jabbers; 84 u64 rx_symbol_err; 85 u64 rx_crc_err; 86 u64 rx_align_err; 87 u64 rx_mac_ctrl; 88 u64 rx_pause; 89 u64 rx_bcast; 90 u64 rx_mcast; 91 u64 rx_ucast; 92 u64 rx_64_or_less; 93 u64 rx_65_127; 94 u64 rx_128_255; 95 u64 rx_256_511; 96 u64 rx_512_1023; 97 u64 rx_1024_1522; 98 u64 tx; 99 u64 tx_hi; 100 u64 tx_late_col; 101 u64 tx_pause; 102 u64 tx_bcast; 103 u64 tx_mcast; 104 u64 tx_ucast; 105 u64 tx_deferred; 106 u64 tx_total_col; 107 u64 tx_exc_col; 108 u64 tx_single_col; 109 u64 tx_mult_col; 110 u64 rx_discards; 111 u64 tx_discards; 112 }; 113 114 static const struct ksz_mib_names ksz88xx_mib_names[] = { 115 { 0x00, "rx" }, 116 { 0x01, "rx_hi" }, 117 { 0x02, "rx_undersize" }, 118 { 0x03, "rx_fragments" }, 119 { 0x04, "rx_oversize" }, 120 { 0x05, "rx_jabbers" }, 121 { 0x06, "rx_symbol_err" }, 122 { 0x07, "rx_crc_err" }, 123 { 0x08, "rx_align_err" }, 124 { 0x09, "rx_mac_ctrl" }, 125 { 0x0a, "rx_pause" }, 126 { 0x0b, "rx_bcast" }, 127 { 0x0c, "rx_mcast" }, 128 { 0x0d, "rx_ucast" }, 129 { 0x0e, "rx_64_or_less" }, 130 { 0x0f, "rx_65_127" }, 131 { 0x10, "rx_128_255" }, 132 { 0x11, "rx_256_511" }, 133 { 0x12, "rx_512_1023" }, 134 { 0x13, "rx_1024_1522" }, 135 { 0x14, "tx" }, 136 { 0x15, "tx_hi" }, 137 { 0x16, "tx_late_col" }, 138 { 0x17, "tx_pause" }, 139 { 0x18, "tx_bcast" }, 140 { 0x19, "tx_mcast" }, 141 { 0x1a, "tx_ucast" }, 142 { 0x1b, "tx_deferred" }, 143 { 0x1c, "tx_total_col" }, 144 { 0x1d, "tx_exc_col" }, 145 { 0x1e, "tx_single_col" }, 146 { 0x1f, "tx_mult_col" }, 147 { 0x100, "rx_discards" }, 148 { 0x101, "tx_discards" }, 149 }; 150 151 static const struct ksz_mib_names ksz9477_mib_names[] = { 152 { 0x00, "rx_hi" }, 153 { 0x01, "rx_undersize" }, 154 { 0x02, "rx_fragments" }, 155 { 0x03, "rx_oversize" }, 156 { 0x04, "rx_jabbers" }, 157 { 0x05, "rx_symbol_err" }, 158 { 0x06, "rx_crc_err" }, 159 { 0x07, "rx_align_err" }, 160 { 0x08, "rx_mac_ctrl" }, 161 { 0x09, "rx_pause" }, 162 { 0x0A, "rx_bcast" }, 163 { 0x0B, "rx_mcast" }, 164 { 0x0C, "rx_ucast" }, 165 { 0x0D, "rx_64_or_less" }, 166 { 0x0E, "rx_65_127" }, 167 { 0x0F, "rx_128_255" }, 168 { 0x10, "rx_256_511" }, 169 { 0x11, "rx_512_1023" }, 170 { 0x12, "rx_1024_1522" }, 171 { 0x13, "rx_1523_2000" }, 172 { 0x14, "rx_2001" }, 173 { 0x15, "tx_hi" }, 174 { 0x16, "tx_late_col" }, 175 { 0x17, "tx_pause" }, 176 { 0x18, "tx_bcast" }, 177 { 0x19, "tx_mcast" }, 178 { 0x1A, "tx_ucast" }, 179 { 0x1B, "tx_deferred" }, 180 { 0x1C, "tx_total_col" }, 181 { 0x1D, "tx_exc_col" }, 182 { 0x1E, "tx_single_col" }, 183 { 0x1F, "tx_mult_col" }, 184 { 0x80, "rx_total" }, 185 { 0x81, "tx_total" }, 186 { 0x82, "rx_discards" }, 187 { 0x83, "tx_discards" }, 188 }; 189 190 struct ksz_driver_strength_prop { 191 const char *name; 192 int offset; 193 int value; 194 }; 195 196 enum ksz_driver_strength_type { 197 KSZ_DRIVER_STRENGTH_HI, 198 KSZ_DRIVER_STRENGTH_LO, 199 KSZ_DRIVER_STRENGTH_IO, 200 }; 201 202 /** 203 * struct ksz_drive_strength - drive strength mapping 204 * @reg_val: register value 205 * @microamp: microamp value 206 */ 207 struct ksz_drive_strength { 208 u32 reg_val; 209 u32 microamp; 210 }; 211 212 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants 213 * 214 * This values are not documented in KSZ9477 variants but confirmed by 215 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893 216 * and KSZ8563 are using same register (drive strength) settings like KSZ8795. 217 * 218 * Documentation in KSZ8795CLX provides more information with some 219 * recommendations: 220 * - for high speed signals 221 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using 222 * 2.5V or 3.3V VDDIO. 223 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with 224 * using 1.8V VDDIO. 225 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V 226 * or 3.3V VDDIO. 227 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO. 228 * 5. In same interface, the heavy loading should use higher one of the 229 * drive current strength. 230 * - for low speed signals 231 * 1. 3.3V VDDIO, use either 4 mA or 8 mA. 232 * 2. 2.5V VDDIO, use either 8 mA or 12 mA. 233 * 3. 1.8V VDDIO, use either 12 mA or 16 mA. 234 * 4. If it is heavy loading, can use higher drive current strength. 235 */ 236 static const struct ksz_drive_strength ksz9477_drive_strengths[] = { 237 { SW_DRIVE_STRENGTH_2MA, 2000 }, 238 { SW_DRIVE_STRENGTH_4MA, 4000 }, 239 { SW_DRIVE_STRENGTH_8MA, 8000 }, 240 { SW_DRIVE_STRENGTH_12MA, 12000 }, 241 { SW_DRIVE_STRENGTH_16MA, 16000 }, 242 { SW_DRIVE_STRENGTH_20MA, 20000 }, 243 { SW_DRIVE_STRENGTH_24MA, 24000 }, 244 { SW_DRIVE_STRENGTH_28MA, 28000 }, 245 }; 246 247 /* ksz8830_drive_strengths - Drive strength mapping for KSZ8830, KSZ8873, .. 248 * variants. 249 * This values are documented in KSZ8873 and KSZ8863 datasheets. 250 */ 251 static const struct ksz_drive_strength ksz8830_drive_strengths[] = { 252 { 0, 8000 }, 253 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 }, 254 }; 255 256 static void ksz8830_phylink_mac_config(struct phylink_config *config, 257 unsigned int mode, 258 const struct phylink_link_state *state); 259 static void ksz_phylink_mac_config(struct phylink_config *config, 260 unsigned int mode, 261 const struct phylink_link_state *state); 262 static void ksz_phylink_mac_link_down(struct phylink_config *config, 263 unsigned int mode, 264 phy_interface_t interface); 265 266 static const struct phylink_mac_ops ksz8830_phylink_mac_ops = { 267 .mac_config = ksz8830_phylink_mac_config, 268 .mac_link_down = ksz_phylink_mac_link_down, 269 .mac_link_up = ksz8_phylink_mac_link_up, 270 }; 271 272 static const struct phylink_mac_ops ksz8_phylink_mac_ops = { 273 .mac_config = ksz_phylink_mac_config, 274 .mac_link_down = ksz_phylink_mac_link_down, 275 .mac_link_up = ksz8_phylink_mac_link_up, 276 }; 277 278 static const struct ksz_dev_ops ksz8_dev_ops = { 279 .setup = ksz8_setup, 280 .get_port_addr = ksz8_get_port_addr, 281 .cfg_port_member = ksz8_cfg_port_member, 282 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 283 .port_setup = ksz8_port_setup, 284 .r_phy = ksz8_r_phy, 285 .w_phy = ksz8_w_phy, 286 .r_mib_cnt = ksz8_r_mib_cnt, 287 .r_mib_pkt = ksz8_r_mib_pkt, 288 .r_mib_stat64 = ksz88xx_r_mib_stats64, 289 .freeze_mib = ksz8_freeze_mib, 290 .port_init_cnt = ksz8_port_init_cnt, 291 .fdb_dump = ksz8_fdb_dump, 292 .fdb_add = ksz8_fdb_add, 293 .fdb_del = ksz8_fdb_del, 294 .mdb_add = ksz8_mdb_add, 295 .mdb_del = ksz8_mdb_del, 296 .vlan_filtering = ksz8_port_vlan_filtering, 297 .vlan_add = ksz8_port_vlan_add, 298 .vlan_del = ksz8_port_vlan_del, 299 .mirror_add = ksz8_port_mirror_add, 300 .mirror_del = ksz8_port_mirror_del, 301 .get_caps = ksz8_get_caps, 302 .config_cpu_port = ksz8_config_cpu_port, 303 .enable_stp_addr = ksz8_enable_stp_addr, 304 .reset = ksz8_reset_switch, 305 .init = ksz8_switch_init, 306 .exit = ksz8_switch_exit, 307 .change_mtu = ksz8_change_mtu, 308 }; 309 310 static void ksz9477_phylink_mac_link_up(struct phylink_config *config, 311 struct phy_device *phydev, 312 unsigned int mode, 313 phy_interface_t interface, 314 int speed, int duplex, bool tx_pause, 315 bool rx_pause); 316 317 static const struct phylink_mac_ops ksz9477_phylink_mac_ops = { 318 .mac_config = ksz_phylink_mac_config, 319 .mac_link_down = ksz_phylink_mac_link_down, 320 .mac_link_up = ksz9477_phylink_mac_link_up, 321 }; 322 323 static const struct ksz_dev_ops ksz9477_dev_ops = { 324 .setup = ksz9477_setup, 325 .get_port_addr = ksz9477_get_port_addr, 326 .cfg_port_member = ksz9477_cfg_port_member, 327 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 328 .port_setup = ksz9477_port_setup, 329 .set_ageing_time = ksz9477_set_ageing_time, 330 .r_phy = ksz9477_r_phy, 331 .w_phy = ksz9477_w_phy, 332 .r_mib_cnt = ksz9477_r_mib_cnt, 333 .r_mib_pkt = ksz9477_r_mib_pkt, 334 .r_mib_stat64 = ksz_r_mib_stats64, 335 .freeze_mib = ksz9477_freeze_mib, 336 .port_init_cnt = ksz9477_port_init_cnt, 337 .vlan_filtering = ksz9477_port_vlan_filtering, 338 .vlan_add = ksz9477_port_vlan_add, 339 .vlan_del = ksz9477_port_vlan_del, 340 .mirror_add = ksz9477_port_mirror_add, 341 .mirror_del = ksz9477_port_mirror_del, 342 .get_caps = ksz9477_get_caps, 343 .fdb_dump = ksz9477_fdb_dump, 344 .fdb_add = ksz9477_fdb_add, 345 .fdb_del = ksz9477_fdb_del, 346 .mdb_add = ksz9477_mdb_add, 347 .mdb_del = ksz9477_mdb_del, 348 .change_mtu = ksz9477_change_mtu, 349 .get_wol = ksz9477_get_wol, 350 .set_wol = ksz9477_set_wol, 351 .wol_pre_shutdown = ksz9477_wol_pre_shutdown, 352 .config_cpu_port = ksz9477_config_cpu_port, 353 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc, 354 .enable_stp_addr = ksz9477_enable_stp_addr, 355 .reset = ksz9477_reset_switch, 356 .init = ksz9477_switch_init, 357 .exit = ksz9477_switch_exit, 358 }; 359 360 static const struct phylink_mac_ops lan937x_phylink_mac_ops = { 361 .mac_config = ksz_phylink_mac_config, 362 .mac_link_down = ksz_phylink_mac_link_down, 363 .mac_link_up = ksz9477_phylink_mac_link_up, 364 }; 365 366 static const struct ksz_dev_ops lan937x_dev_ops = { 367 .setup = lan937x_setup, 368 .teardown = lan937x_teardown, 369 .get_port_addr = ksz9477_get_port_addr, 370 .cfg_port_member = ksz9477_cfg_port_member, 371 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 372 .port_setup = lan937x_port_setup, 373 .set_ageing_time = lan937x_set_ageing_time, 374 .r_phy = lan937x_r_phy, 375 .w_phy = lan937x_w_phy, 376 .r_mib_cnt = ksz9477_r_mib_cnt, 377 .r_mib_pkt = ksz9477_r_mib_pkt, 378 .r_mib_stat64 = ksz_r_mib_stats64, 379 .freeze_mib = ksz9477_freeze_mib, 380 .port_init_cnt = ksz9477_port_init_cnt, 381 .vlan_filtering = ksz9477_port_vlan_filtering, 382 .vlan_add = ksz9477_port_vlan_add, 383 .vlan_del = ksz9477_port_vlan_del, 384 .mirror_add = ksz9477_port_mirror_add, 385 .mirror_del = ksz9477_port_mirror_del, 386 .get_caps = lan937x_phylink_get_caps, 387 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 388 .fdb_dump = ksz9477_fdb_dump, 389 .fdb_add = ksz9477_fdb_add, 390 .fdb_del = ksz9477_fdb_del, 391 .mdb_add = ksz9477_mdb_add, 392 .mdb_del = ksz9477_mdb_del, 393 .change_mtu = lan937x_change_mtu, 394 .config_cpu_port = lan937x_config_cpu_port, 395 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 396 .enable_stp_addr = ksz9477_enable_stp_addr, 397 .reset = lan937x_reset_switch, 398 .init = lan937x_switch_init, 399 .exit = lan937x_switch_exit, 400 }; 401 402 static const u16 ksz8795_regs[] = { 403 [REG_SW_MAC_ADDR] = 0x68, 404 [REG_IND_CTRL_0] = 0x6E, 405 [REG_IND_DATA_8] = 0x70, 406 [REG_IND_DATA_CHECK] = 0x72, 407 [REG_IND_DATA_HI] = 0x71, 408 [REG_IND_DATA_LO] = 0x75, 409 [REG_IND_MIB_CHECK] = 0x74, 410 [REG_IND_BYTE] = 0xA0, 411 [P_FORCE_CTRL] = 0x0C, 412 [P_LINK_STATUS] = 0x0E, 413 [P_LOCAL_CTRL] = 0x07, 414 [P_NEG_RESTART_CTRL] = 0x0D, 415 [P_REMOTE_STATUS] = 0x08, 416 [P_SPEED_STATUS] = 0x09, 417 [S_TAIL_TAG_CTRL] = 0x0C, 418 [P_STP_CTRL] = 0x02, 419 [S_START_CTRL] = 0x01, 420 [S_BROADCAST_CTRL] = 0x06, 421 [S_MULTICAST_CTRL] = 0x04, 422 [P_XMII_CTRL_0] = 0x06, 423 [P_XMII_CTRL_1] = 0x06, 424 }; 425 426 static const u32 ksz8795_masks[] = { 427 [PORT_802_1P_REMAPPING] = BIT(7), 428 [SW_TAIL_TAG_ENABLE] = BIT(1), 429 [MIB_COUNTER_OVERFLOW] = BIT(6), 430 [MIB_COUNTER_VALID] = BIT(5), 431 [VLAN_TABLE_FID] = GENMASK(6, 0), 432 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 433 [VLAN_TABLE_VALID] = BIT(12), 434 [STATIC_MAC_TABLE_VALID] = BIT(21), 435 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 436 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 437 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 438 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 439 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 440 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 441 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 442 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 443 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 444 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 445 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 446 [P_MII_TX_FLOW_CTRL] = BIT(5), 447 [P_MII_RX_FLOW_CTRL] = BIT(5), 448 }; 449 450 static const u8 ksz8795_xmii_ctrl0[] = { 451 [P_MII_100MBIT] = 0, 452 [P_MII_10MBIT] = 1, 453 [P_MII_FULL_DUPLEX] = 0, 454 [P_MII_HALF_DUPLEX] = 1, 455 }; 456 457 static const u8 ksz8795_xmii_ctrl1[] = { 458 [P_RGMII_SEL] = 3, 459 [P_GMII_SEL] = 2, 460 [P_RMII_SEL] = 1, 461 [P_MII_SEL] = 0, 462 [P_GMII_1GBIT] = 1, 463 [P_GMII_NOT_1GBIT] = 0, 464 }; 465 466 static const u8 ksz8795_shifts[] = { 467 [VLAN_TABLE_MEMBERSHIP_S] = 7, 468 [VLAN_TABLE] = 16, 469 [STATIC_MAC_FWD_PORTS] = 16, 470 [STATIC_MAC_FID] = 24, 471 [DYNAMIC_MAC_ENTRIES_H] = 3, 472 [DYNAMIC_MAC_ENTRIES] = 29, 473 [DYNAMIC_MAC_FID] = 16, 474 [DYNAMIC_MAC_TIMESTAMP] = 27, 475 [DYNAMIC_MAC_SRC_PORT] = 24, 476 }; 477 478 static const u16 ksz8863_regs[] = { 479 [REG_SW_MAC_ADDR] = 0x70, 480 [REG_IND_CTRL_0] = 0x79, 481 [REG_IND_DATA_8] = 0x7B, 482 [REG_IND_DATA_CHECK] = 0x7B, 483 [REG_IND_DATA_HI] = 0x7C, 484 [REG_IND_DATA_LO] = 0x80, 485 [REG_IND_MIB_CHECK] = 0x80, 486 [P_FORCE_CTRL] = 0x0C, 487 [P_LINK_STATUS] = 0x0E, 488 [P_LOCAL_CTRL] = 0x0C, 489 [P_NEG_RESTART_CTRL] = 0x0D, 490 [P_REMOTE_STATUS] = 0x0E, 491 [P_SPEED_STATUS] = 0x0F, 492 [S_TAIL_TAG_CTRL] = 0x03, 493 [P_STP_CTRL] = 0x02, 494 [S_START_CTRL] = 0x01, 495 [S_BROADCAST_CTRL] = 0x06, 496 [S_MULTICAST_CTRL] = 0x04, 497 }; 498 499 static const u32 ksz8863_masks[] = { 500 [PORT_802_1P_REMAPPING] = BIT(3), 501 [SW_TAIL_TAG_ENABLE] = BIT(6), 502 [MIB_COUNTER_OVERFLOW] = BIT(7), 503 [MIB_COUNTER_VALID] = BIT(6), 504 [VLAN_TABLE_FID] = GENMASK(15, 12), 505 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 506 [VLAN_TABLE_VALID] = BIT(19), 507 [STATIC_MAC_TABLE_VALID] = BIT(19), 508 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 509 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 510 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 511 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 512 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 513 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 514 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 515 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 516 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 517 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 518 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 519 }; 520 521 static u8 ksz8863_shifts[] = { 522 [VLAN_TABLE_MEMBERSHIP_S] = 16, 523 [STATIC_MAC_FWD_PORTS] = 16, 524 [STATIC_MAC_FID] = 22, 525 [DYNAMIC_MAC_ENTRIES_H] = 8, 526 [DYNAMIC_MAC_ENTRIES] = 24, 527 [DYNAMIC_MAC_FID] = 16, 528 [DYNAMIC_MAC_TIMESTAMP] = 22, 529 [DYNAMIC_MAC_SRC_PORT] = 20, 530 }; 531 532 static const u16 ksz9477_regs[] = { 533 [REG_SW_MAC_ADDR] = 0x0302, 534 [P_STP_CTRL] = 0x0B04, 535 [S_START_CTRL] = 0x0300, 536 [S_BROADCAST_CTRL] = 0x0332, 537 [S_MULTICAST_CTRL] = 0x0331, 538 [P_XMII_CTRL_0] = 0x0300, 539 [P_XMII_CTRL_1] = 0x0301, 540 }; 541 542 static const u32 ksz9477_masks[] = { 543 [ALU_STAT_WRITE] = 0, 544 [ALU_STAT_READ] = 1, 545 [P_MII_TX_FLOW_CTRL] = BIT(5), 546 [P_MII_RX_FLOW_CTRL] = BIT(3), 547 }; 548 549 static const u8 ksz9477_shifts[] = { 550 [ALU_STAT_INDEX] = 16, 551 }; 552 553 static const u8 ksz9477_xmii_ctrl0[] = { 554 [P_MII_100MBIT] = 1, 555 [P_MII_10MBIT] = 0, 556 [P_MII_FULL_DUPLEX] = 1, 557 [P_MII_HALF_DUPLEX] = 0, 558 }; 559 560 static const u8 ksz9477_xmii_ctrl1[] = { 561 [P_RGMII_SEL] = 0, 562 [P_RMII_SEL] = 1, 563 [P_GMII_SEL] = 2, 564 [P_MII_SEL] = 3, 565 [P_GMII_1GBIT] = 0, 566 [P_GMII_NOT_1GBIT] = 1, 567 }; 568 569 static const u32 lan937x_masks[] = { 570 [ALU_STAT_WRITE] = 1, 571 [ALU_STAT_READ] = 2, 572 [P_MII_TX_FLOW_CTRL] = BIT(5), 573 [P_MII_RX_FLOW_CTRL] = BIT(3), 574 }; 575 576 static const u8 lan937x_shifts[] = { 577 [ALU_STAT_INDEX] = 8, 578 }; 579 580 static const struct regmap_range ksz8563_valid_regs[] = { 581 regmap_reg_range(0x0000, 0x0003), 582 regmap_reg_range(0x0006, 0x0006), 583 regmap_reg_range(0x000f, 0x001f), 584 regmap_reg_range(0x0100, 0x0100), 585 regmap_reg_range(0x0104, 0x0107), 586 regmap_reg_range(0x010d, 0x010d), 587 regmap_reg_range(0x0110, 0x0113), 588 regmap_reg_range(0x0120, 0x012b), 589 regmap_reg_range(0x0201, 0x0201), 590 regmap_reg_range(0x0210, 0x0213), 591 regmap_reg_range(0x0300, 0x0300), 592 regmap_reg_range(0x0302, 0x031b), 593 regmap_reg_range(0x0320, 0x032b), 594 regmap_reg_range(0x0330, 0x0336), 595 regmap_reg_range(0x0338, 0x033e), 596 regmap_reg_range(0x0340, 0x035f), 597 regmap_reg_range(0x0370, 0x0370), 598 regmap_reg_range(0x0378, 0x0378), 599 regmap_reg_range(0x037c, 0x037d), 600 regmap_reg_range(0x0390, 0x0393), 601 regmap_reg_range(0x0400, 0x040e), 602 regmap_reg_range(0x0410, 0x042f), 603 regmap_reg_range(0x0500, 0x0519), 604 regmap_reg_range(0x0520, 0x054b), 605 regmap_reg_range(0x0550, 0x05b3), 606 607 /* port 1 */ 608 regmap_reg_range(0x1000, 0x1001), 609 regmap_reg_range(0x1004, 0x100b), 610 regmap_reg_range(0x1013, 0x1013), 611 regmap_reg_range(0x1017, 0x1017), 612 regmap_reg_range(0x101b, 0x101b), 613 regmap_reg_range(0x101f, 0x1021), 614 regmap_reg_range(0x1030, 0x1030), 615 regmap_reg_range(0x1100, 0x1111), 616 regmap_reg_range(0x111a, 0x111d), 617 regmap_reg_range(0x1122, 0x1127), 618 regmap_reg_range(0x112a, 0x112b), 619 regmap_reg_range(0x1136, 0x1139), 620 regmap_reg_range(0x113e, 0x113f), 621 regmap_reg_range(0x1400, 0x1401), 622 regmap_reg_range(0x1403, 0x1403), 623 regmap_reg_range(0x1410, 0x1417), 624 regmap_reg_range(0x1420, 0x1423), 625 regmap_reg_range(0x1500, 0x1507), 626 regmap_reg_range(0x1600, 0x1612), 627 regmap_reg_range(0x1800, 0x180f), 628 regmap_reg_range(0x1900, 0x1907), 629 regmap_reg_range(0x1914, 0x191b), 630 regmap_reg_range(0x1a00, 0x1a03), 631 regmap_reg_range(0x1a04, 0x1a08), 632 regmap_reg_range(0x1b00, 0x1b01), 633 regmap_reg_range(0x1b04, 0x1b04), 634 regmap_reg_range(0x1c00, 0x1c05), 635 regmap_reg_range(0x1c08, 0x1c1b), 636 637 /* port 2 */ 638 regmap_reg_range(0x2000, 0x2001), 639 regmap_reg_range(0x2004, 0x200b), 640 regmap_reg_range(0x2013, 0x2013), 641 regmap_reg_range(0x2017, 0x2017), 642 regmap_reg_range(0x201b, 0x201b), 643 regmap_reg_range(0x201f, 0x2021), 644 regmap_reg_range(0x2030, 0x2030), 645 regmap_reg_range(0x2100, 0x2111), 646 regmap_reg_range(0x211a, 0x211d), 647 regmap_reg_range(0x2122, 0x2127), 648 regmap_reg_range(0x212a, 0x212b), 649 regmap_reg_range(0x2136, 0x2139), 650 regmap_reg_range(0x213e, 0x213f), 651 regmap_reg_range(0x2400, 0x2401), 652 regmap_reg_range(0x2403, 0x2403), 653 regmap_reg_range(0x2410, 0x2417), 654 regmap_reg_range(0x2420, 0x2423), 655 regmap_reg_range(0x2500, 0x2507), 656 regmap_reg_range(0x2600, 0x2612), 657 regmap_reg_range(0x2800, 0x280f), 658 regmap_reg_range(0x2900, 0x2907), 659 regmap_reg_range(0x2914, 0x291b), 660 regmap_reg_range(0x2a00, 0x2a03), 661 regmap_reg_range(0x2a04, 0x2a08), 662 regmap_reg_range(0x2b00, 0x2b01), 663 regmap_reg_range(0x2b04, 0x2b04), 664 regmap_reg_range(0x2c00, 0x2c05), 665 regmap_reg_range(0x2c08, 0x2c1b), 666 667 /* port 3 */ 668 regmap_reg_range(0x3000, 0x3001), 669 regmap_reg_range(0x3004, 0x300b), 670 regmap_reg_range(0x3013, 0x3013), 671 regmap_reg_range(0x3017, 0x3017), 672 regmap_reg_range(0x301b, 0x301b), 673 regmap_reg_range(0x301f, 0x3021), 674 regmap_reg_range(0x3030, 0x3030), 675 regmap_reg_range(0x3300, 0x3301), 676 regmap_reg_range(0x3303, 0x3303), 677 regmap_reg_range(0x3400, 0x3401), 678 regmap_reg_range(0x3403, 0x3403), 679 regmap_reg_range(0x3410, 0x3417), 680 regmap_reg_range(0x3420, 0x3423), 681 regmap_reg_range(0x3500, 0x3507), 682 regmap_reg_range(0x3600, 0x3612), 683 regmap_reg_range(0x3800, 0x380f), 684 regmap_reg_range(0x3900, 0x3907), 685 regmap_reg_range(0x3914, 0x391b), 686 regmap_reg_range(0x3a00, 0x3a03), 687 regmap_reg_range(0x3a04, 0x3a08), 688 regmap_reg_range(0x3b00, 0x3b01), 689 regmap_reg_range(0x3b04, 0x3b04), 690 regmap_reg_range(0x3c00, 0x3c05), 691 regmap_reg_range(0x3c08, 0x3c1b), 692 }; 693 694 static const struct regmap_access_table ksz8563_register_set = { 695 .yes_ranges = ksz8563_valid_regs, 696 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 697 }; 698 699 static const struct regmap_range ksz9477_valid_regs[] = { 700 regmap_reg_range(0x0000, 0x0003), 701 regmap_reg_range(0x0006, 0x0006), 702 regmap_reg_range(0x0010, 0x001f), 703 regmap_reg_range(0x0100, 0x0100), 704 regmap_reg_range(0x0103, 0x0107), 705 regmap_reg_range(0x010d, 0x010d), 706 regmap_reg_range(0x0110, 0x0113), 707 regmap_reg_range(0x0120, 0x012b), 708 regmap_reg_range(0x0201, 0x0201), 709 regmap_reg_range(0x0210, 0x0213), 710 regmap_reg_range(0x0300, 0x0300), 711 regmap_reg_range(0x0302, 0x031b), 712 regmap_reg_range(0x0320, 0x032b), 713 regmap_reg_range(0x0330, 0x0336), 714 regmap_reg_range(0x0338, 0x033b), 715 regmap_reg_range(0x033e, 0x033e), 716 regmap_reg_range(0x0340, 0x035f), 717 regmap_reg_range(0x0370, 0x0370), 718 regmap_reg_range(0x0378, 0x0378), 719 regmap_reg_range(0x037c, 0x037d), 720 regmap_reg_range(0x0390, 0x0393), 721 regmap_reg_range(0x0400, 0x040e), 722 regmap_reg_range(0x0410, 0x042f), 723 regmap_reg_range(0x0444, 0x044b), 724 regmap_reg_range(0x0450, 0x046f), 725 regmap_reg_range(0x0500, 0x0519), 726 regmap_reg_range(0x0520, 0x054b), 727 regmap_reg_range(0x0550, 0x05b3), 728 regmap_reg_range(0x0604, 0x060b), 729 regmap_reg_range(0x0610, 0x0612), 730 regmap_reg_range(0x0614, 0x062c), 731 regmap_reg_range(0x0640, 0x0645), 732 regmap_reg_range(0x0648, 0x064d), 733 734 /* port 1 */ 735 regmap_reg_range(0x1000, 0x1001), 736 regmap_reg_range(0x1013, 0x1013), 737 regmap_reg_range(0x1017, 0x1017), 738 regmap_reg_range(0x101b, 0x101b), 739 regmap_reg_range(0x101f, 0x1020), 740 regmap_reg_range(0x1030, 0x1030), 741 regmap_reg_range(0x1100, 0x1115), 742 regmap_reg_range(0x111a, 0x111f), 743 regmap_reg_range(0x1120, 0x112b), 744 regmap_reg_range(0x1134, 0x113b), 745 regmap_reg_range(0x113c, 0x113f), 746 regmap_reg_range(0x1400, 0x1401), 747 regmap_reg_range(0x1403, 0x1403), 748 regmap_reg_range(0x1410, 0x1417), 749 regmap_reg_range(0x1420, 0x1423), 750 regmap_reg_range(0x1500, 0x1507), 751 regmap_reg_range(0x1600, 0x1613), 752 regmap_reg_range(0x1800, 0x180f), 753 regmap_reg_range(0x1820, 0x1827), 754 regmap_reg_range(0x1830, 0x1837), 755 regmap_reg_range(0x1840, 0x184b), 756 regmap_reg_range(0x1900, 0x1907), 757 regmap_reg_range(0x1914, 0x191b), 758 regmap_reg_range(0x1920, 0x1920), 759 regmap_reg_range(0x1923, 0x1927), 760 regmap_reg_range(0x1a00, 0x1a03), 761 regmap_reg_range(0x1a04, 0x1a07), 762 regmap_reg_range(0x1b00, 0x1b01), 763 regmap_reg_range(0x1b04, 0x1b04), 764 regmap_reg_range(0x1c00, 0x1c05), 765 regmap_reg_range(0x1c08, 0x1c1b), 766 767 /* port 2 */ 768 regmap_reg_range(0x2000, 0x2001), 769 regmap_reg_range(0x2013, 0x2013), 770 regmap_reg_range(0x2017, 0x2017), 771 regmap_reg_range(0x201b, 0x201b), 772 regmap_reg_range(0x201f, 0x2020), 773 regmap_reg_range(0x2030, 0x2030), 774 regmap_reg_range(0x2100, 0x2115), 775 regmap_reg_range(0x211a, 0x211f), 776 regmap_reg_range(0x2120, 0x212b), 777 regmap_reg_range(0x2134, 0x213b), 778 regmap_reg_range(0x213c, 0x213f), 779 regmap_reg_range(0x2400, 0x2401), 780 regmap_reg_range(0x2403, 0x2403), 781 regmap_reg_range(0x2410, 0x2417), 782 regmap_reg_range(0x2420, 0x2423), 783 regmap_reg_range(0x2500, 0x2507), 784 regmap_reg_range(0x2600, 0x2613), 785 regmap_reg_range(0x2800, 0x280f), 786 regmap_reg_range(0x2820, 0x2827), 787 regmap_reg_range(0x2830, 0x2837), 788 regmap_reg_range(0x2840, 0x284b), 789 regmap_reg_range(0x2900, 0x2907), 790 regmap_reg_range(0x2914, 0x291b), 791 regmap_reg_range(0x2920, 0x2920), 792 regmap_reg_range(0x2923, 0x2927), 793 regmap_reg_range(0x2a00, 0x2a03), 794 regmap_reg_range(0x2a04, 0x2a07), 795 regmap_reg_range(0x2b00, 0x2b01), 796 regmap_reg_range(0x2b04, 0x2b04), 797 regmap_reg_range(0x2c00, 0x2c05), 798 regmap_reg_range(0x2c08, 0x2c1b), 799 800 /* port 3 */ 801 regmap_reg_range(0x3000, 0x3001), 802 regmap_reg_range(0x3013, 0x3013), 803 regmap_reg_range(0x3017, 0x3017), 804 regmap_reg_range(0x301b, 0x301b), 805 regmap_reg_range(0x301f, 0x3020), 806 regmap_reg_range(0x3030, 0x3030), 807 regmap_reg_range(0x3100, 0x3115), 808 regmap_reg_range(0x311a, 0x311f), 809 regmap_reg_range(0x3120, 0x312b), 810 regmap_reg_range(0x3134, 0x313b), 811 regmap_reg_range(0x313c, 0x313f), 812 regmap_reg_range(0x3400, 0x3401), 813 regmap_reg_range(0x3403, 0x3403), 814 regmap_reg_range(0x3410, 0x3417), 815 regmap_reg_range(0x3420, 0x3423), 816 regmap_reg_range(0x3500, 0x3507), 817 regmap_reg_range(0x3600, 0x3613), 818 regmap_reg_range(0x3800, 0x380f), 819 regmap_reg_range(0x3820, 0x3827), 820 regmap_reg_range(0x3830, 0x3837), 821 regmap_reg_range(0x3840, 0x384b), 822 regmap_reg_range(0x3900, 0x3907), 823 regmap_reg_range(0x3914, 0x391b), 824 regmap_reg_range(0x3920, 0x3920), 825 regmap_reg_range(0x3923, 0x3927), 826 regmap_reg_range(0x3a00, 0x3a03), 827 regmap_reg_range(0x3a04, 0x3a07), 828 regmap_reg_range(0x3b00, 0x3b01), 829 regmap_reg_range(0x3b04, 0x3b04), 830 regmap_reg_range(0x3c00, 0x3c05), 831 regmap_reg_range(0x3c08, 0x3c1b), 832 833 /* port 4 */ 834 regmap_reg_range(0x4000, 0x4001), 835 regmap_reg_range(0x4013, 0x4013), 836 regmap_reg_range(0x4017, 0x4017), 837 regmap_reg_range(0x401b, 0x401b), 838 regmap_reg_range(0x401f, 0x4020), 839 regmap_reg_range(0x4030, 0x4030), 840 regmap_reg_range(0x4100, 0x4115), 841 regmap_reg_range(0x411a, 0x411f), 842 regmap_reg_range(0x4120, 0x412b), 843 regmap_reg_range(0x4134, 0x413b), 844 regmap_reg_range(0x413c, 0x413f), 845 regmap_reg_range(0x4400, 0x4401), 846 regmap_reg_range(0x4403, 0x4403), 847 regmap_reg_range(0x4410, 0x4417), 848 regmap_reg_range(0x4420, 0x4423), 849 regmap_reg_range(0x4500, 0x4507), 850 regmap_reg_range(0x4600, 0x4613), 851 regmap_reg_range(0x4800, 0x480f), 852 regmap_reg_range(0x4820, 0x4827), 853 regmap_reg_range(0x4830, 0x4837), 854 regmap_reg_range(0x4840, 0x484b), 855 regmap_reg_range(0x4900, 0x4907), 856 regmap_reg_range(0x4914, 0x491b), 857 regmap_reg_range(0x4920, 0x4920), 858 regmap_reg_range(0x4923, 0x4927), 859 regmap_reg_range(0x4a00, 0x4a03), 860 regmap_reg_range(0x4a04, 0x4a07), 861 regmap_reg_range(0x4b00, 0x4b01), 862 regmap_reg_range(0x4b04, 0x4b04), 863 regmap_reg_range(0x4c00, 0x4c05), 864 regmap_reg_range(0x4c08, 0x4c1b), 865 866 /* port 5 */ 867 regmap_reg_range(0x5000, 0x5001), 868 regmap_reg_range(0x5013, 0x5013), 869 regmap_reg_range(0x5017, 0x5017), 870 regmap_reg_range(0x501b, 0x501b), 871 regmap_reg_range(0x501f, 0x5020), 872 regmap_reg_range(0x5030, 0x5030), 873 regmap_reg_range(0x5100, 0x5115), 874 regmap_reg_range(0x511a, 0x511f), 875 regmap_reg_range(0x5120, 0x512b), 876 regmap_reg_range(0x5134, 0x513b), 877 regmap_reg_range(0x513c, 0x513f), 878 regmap_reg_range(0x5400, 0x5401), 879 regmap_reg_range(0x5403, 0x5403), 880 regmap_reg_range(0x5410, 0x5417), 881 regmap_reg_range(0x5420, 0x5423), 882 regmap_reg_range(0x5500, 0x5507), 883 regmap_reg_range(0x5600, 0x5613), 884 regmap_reg_range(0x5800, 0x580f), 885 regmap_reg_range(0x5820, 0x5827), 886 regmap_reg_range(0x5830, 0x5837), 887 regmap_reg_range(0x5840, 0x584b), 888 regmap_reg_range(0x5900, 0x5907), 889 regmap_reg_range(0x5914, 0x591b), 890 regmap_reg_range(0x5920, 0x5920), 891 regmap_reg_range(0x5923, 0x5927), 892 regmap_reg_range(0x5a00, 0x5a03), 893 regmap_reg_range(0x5a04, 0x5a07), 894 regmap_reg_range(0x5b00, 0x5b01), 895 regmap_reg_range(0x5b04, 0x5b04), 896 regmap_reg_range(0x5c00, 0x5c05), 897 regmap_reg_range(0x5c08, 0x5c1b), 898 899 /* port 6 */ 900 regmap_reg_range(0x6000, 0x6001), 901 regmap_reg_range(0x6013, 0x6013), 902 regmap_reg_range(0x6017, 0x6017), 903 regmap_reg_range(0x601b, 0x601b), 904 regmap_reg_range(0x601f, 0x6020), 905 regmap_reg_range(0x6030, 0x6030), 906 regmap_reg_range(0x6300, 0x6301), 907 regmap_reg_range(0x6400, 0x6401), 908 regmap_reg_range(0x6403, 0x6403), 909 regmap_reg_range(0x6410, 0x6417), 910 regmap_reg_range(0x6420, 0x6423), 911 regmap_reg_range(0x6500, 0x6507), 912 regmap_reg_range(0x6600, 0x6613), 913 regmap_reg_range(0x6800, 0x680f), 914 regmap_reg_range(0x6820, 0x6827), 915 regmap_reg_range(0x6830, 0x6837), 916 regmap_reg_range(0x6840, 0x684b), 917 regmap_reg_range(0x6900, 0x6907), 918 regmap_reg_range(0x6914, 0x691b), 919 regmap_reg_range(0x6920, 0x6920), 920 regmap_reg_range(0x6923, 0x6927), 921 regmap_reg_range(0x6a00, 0x6a03), 922 regmap_reg_range(0x6a04, 0x6a07), 923 regmap_reg_range(0x6b00, 0x6b01), 924 regmap_reg_range(0x6b04, 0x6b04), 925 regmap_reg_range(0x6c00, 0x6c05), 926 regmap_reg_range(0x6c08, 0x6c1b), 927 928 /* port 7 */ 929 regmap_reg_range(0x7000, 0x7001), 930 regmap_reg_range(0x7013, 0x7013), 931 regmap_reg_range(0x7017, 0x7017), 932 regmap_reg_range(0x701b, 0x701b), 933 regmap_reg_range(0x701f, 0x7020), 934 regmap_reg_range(0x7030, 0x7030), 935 regmap_reg_range(0x7200, 0x7203), 936 regmap_reg_range(0x7206, 0x7207), 937 regmap_reg_range(0x7300, 0x7301), 938 regmap_reg_range(0x7400, 0x7401), 939 regmap_reg_range(0x7403, 0x7403), 940 regmap_reg_range(0x7410, 0x7417), 941 regmap_reg_range(0x7420, 0x7423), 942 regmap_reg_range(0x7500, 0x7507), 943 regmap_reg_range(0x7600, 0x7613), 944 regmap_reg_range(0x7800, 0x780f), 945 regmap_reg_range(0x7820, 0x7827), 946 regmap_reg_range(0x7830, 0x7837), 947 regmap_reg_range(0x7840, 0x784b), 948 regmap_reg_range(0x7900, 0x7907), 949 regmap_reg_range(0x7914, 0x791b), 950 regmap_reg_range(0x7920, 0x7920), 951 regmap_reg_range(0x7923, 0x7927), 952 regmap_reg_range(0x7a00, 0x7a03), 953 regmap_reg_range(0x7a04, 0x7a07), 954 regmap_reg_range(0x7b00, 0x7b01), 955 regmap_reg_range(0x7b04, 0x7b04), 956 regmap_reg_range(0x7c00, 0x7c05), 957 regmap_reg_range(0x7c08, 0x7c1b), 958 }; 959 960 static const struct regmap_access_table ksz9477_register_set = { 961 .yes_ranges = ksz9477_valid_regs, 962 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 963 }; 964 965 static const struct regmap_range ksz9896_valid_regs[] = { 966 regmap_reg_range(0x0000, 0x0003), 967 regmap_reg_range(0x0006, 0x0006), 968 regmap_reg_range(0x0010, 0x001f), 969 regmap_reg_range(0x0100, 0x0100), 970 regmap_reg_range(0x0103, 0x0107), 971 regmap_reg_range(0x010d, 0x010d), 972 regmap_reg_range(0x0110, 0x0113), 973 regmap_reg_range(0x0120, 0x0127), 974 regmap_reg_range(0x0201, 0x0201), 975 regmap_reg_range(0x0210, 0x0213), 976 regmap_reg_range(0x0300, 0x0300), 977 regmap_reg_range(0x0302, 0x030b), 978 regmap_reg_range(0x0310, 0x031b), 979 regmap_reg_range(0x0320, 0x032b), 980 regmap_reg_range(0x0330, 0x0336), 981 regmap_reg_range(0x0338, 0x033b), 982 regmap_reg_range(0x033e, 0x033e), 983 regmap_reg_range(0x0340, 0x035f), 984 regmap_reg_range(0x0370, 0x0370), 985 regmap_reg_range(0x0378, 0x0378), 986 regmap_reg_range(0x037c, 0x037d), 987 regmap_reg_range(0x0390, 0x0393), 988 regmap_reg_range(0x0400, 0x040e), 989 regmap_reg_range(0x0410, 0x042f), 990 991 /* port 1 */ 992 regmap_reg_range(0x1000, 0x1001), 993 regmap_reg_range(0x1013, 0x1013), 994 regmap_reg_range(0x1017, 0x1017), 995 regmap_reg_range(0x101b, 0x101b), 996 regmap_reg_range(0x101f, 0x1020), 997 regmap_reg_range(0x1030, 0x1030), 998 regmap_reg_range(0x1100, 0x1115), 999 regmap_reg_range(0x111a, 0x111f), 1000 regmap_reg_range(0x1122, 0x1127), 1001 regmap_reg_range(0x112a, 0x112b), 1002 regmap_reg_range(0x1136, 0x1139), 1003 regmap_reg_range(0x113e, 0x113f), 1004 regmap_reg_range(0x1400, 0x1401), 1005 regmap_reg_range(0x1403, 0x1403), 1006 regmap_reg_range(0x1410, 0x1417), 1007 regmap_reg_range(0x1420, 0x1423), 1008 regmap_reg_range(0x1500, 0x1507), 1009 regmap_reg_range(0x1600, 0x1612), 1010 regmap_reg_range(0x1800, 0x180f), 1011 regmap_reg_range(0x1820, 0x1827), 1012 regmap_reg_range(0x1830, 0x1837), 1013 regmap_reg_range(0x1840, 0x184b), 1014 regmap_reg_range(0x1900, 0x1907), 1015 regmap_reg_range(0x1914, 0x1915), 1016 regmap_reg_range(0x1a00, 0x1a03), 1017 regmap_reg_range(0x1a04, 0x1a07), 1018 regmap_reg_range(0x1b00, 0x1b01), 1019 regmap_reg_range(0x1b04, 0x1b04), 1020 1021 /* port 2 */ 1022 regmap_reg_range(0x2000, 0x2001), 1023 regmap_reg_range(0x2013, 0x2013), 1024 regmap_reg_range(0x2017, 0x2017), 1025 regmap_reg_range(0x201b, 0x201b), 1026 regmap_reg_range(0x201f, 0x2020), 1027 regmap_reg_range(0x2030, 0x2030), 1028 regmap_reg_range(0x2100, 0x2115), 1029 regmap_reg_range(0x211a, 0x211f), 1030 regmap_reg_range(0x2122, 0x2127), 1031 regmap_reg_range(0x212a, 0x212b), 1032 regmap_reg_range(0x2136, 0x2139), 1033 regmap_reg_range(0x213e, 0x213f), 1034 regmap_reg_range(0x2400, 0x2401), 1035 regmap_reg_range(0x2403, 0x2403), 1036 regmap_reg_range(0x2410, 0x2417), 1037 regmap_reg_range(0x2420, 0x2423), 1038 regmap_reg_range(0x2500, 0x2507), 1039 regmap_reg_range(0x2600, 0x2612), 1040 regmap_reg_range(0x2800, 0x280f), 1041 regmap_reg_range(0x2820, 0x2827), 1042 regmap_reg_range(0x2830, 0x2837), 1043 regmap_reg_range(0x2840, 0x284b), 1044 regmap_reg_range(0x2900, 0x2907), 1045 regmap_reg_range(0x2914, 0x2915), 1046 regmap_reg_range(0x2a00, 0x2a03), 1047 regmap_reg_range(0x2a04, 0x2a07), 1048 regmap_reg_range(0x2b00, 0x2b01), 1049 regmap_reg_range(0x2b04, 0x2b04), 1050 1051 /* port 3 */ 1052 regmap_reg_range(0x3000, 0x3001), 1053 regmap_reg_range(0x3013, 0x3013), 1054 regmap_reg_range(0x3017, 0x3017), 1055 regmap_reg_range(0x301b, 0x301b), 1056 regmap_reg_range(0x301f, 0x3020), 1057 regmap_reg_range(0x3030, 0x3030), 1058 regmap_reg_range(0x3100, 0x3115), 1059 regmap_reg_range(0x311a, 0x311f), 1060 regmap_reg_range(0x3122, 0x3127), 1061 regmap_reg_range(0x312a, 0x312b), 1062 regmap_reg_range(0x3136, 0x3139), 1063 regmap_reg_range(0x313e, 0x313f), 1064 regmap_reg_range(0x3400, 0x3401), 1065 regmap_reg_range(0x3403, 0x3403), 1066 regmap_reg_range(0x3410, 0x3417), 1067 regmap_reg_range(0x3420, 0x3423), 1068 regmap_reg_range(0x3500, 0x3507), 1069 regmap_reg_range(0x3600, 0x3612), 1070 regmap_reg_range(0x3800, 0x380f), 1071 regmap_reg_range(0x3820, 0x3827), 1072 regmap_reg_range(0x3830, 0x3837), 1073 regmap_reg_range(0x3840, 0x384b), 1074 regmap_reg_range(0x3900, 0x3907), 1075 regmap_reg_range(0x3914, 0x3915), 1076 regmap_reg_range(0x3a00, 0x3a03), 1077 regmap_reg_range(0x3a04, 0x3a07), 1078 regmap_reg_range(0x3b00, 0x3b01), 1079 regmap_reg_range(0x3b04, 0x3b04), 1080 1081 /* port 4 */ 1082 regmap_reg_range(0x4000, 0x4001), 1083 regmap_reg_range(0x4013, 0x4013), 1084 regmap_reg_range(0x4017, 0x4017), 1085 regmap_reg_range(0x401b, 0x401b), 1086 regmap_reg_range(0x401f, 0x4020), 1087 regmap_reg_range(0x4030, 0x4030), 1088 regmap_reg_range(0x4100, 0x4115), 1089 regmap_reg_range(0x411a, 0x411f), 1090 regmap_reg_range(0x4122, 0x4127), 1091 regmap_reg_range(0x412a, 0x412b), 1092 regmap_reg_range(0x4136, 0x4139), 1093 regmap_reg_range(0x413e, 0x413f), 1094 regmap_reg_range(0x4400, 0x4401), 1095 regmap_reg_range(0x4403, 0x4403), 1096 regmap_reg_range(0x4410, 0x4417), 1097 regmap_reg_range(0x4420, 0x4423), 1098 regmap_reg_range(0x4500, 0x4507), 1099 regmap_reg_range(0x4600, 0x4612), 1100 regmap_reg_range(0x4800, 0x480f), 1101 regmap_reg_range(0x4820, 0x4827), 1102 regmap_reg_range(0x4830, 0x4837), 1103 regmap_reg_range(0x4840, 0x484b), 1104 regmap_reg_range(0x4900, 0x4907), 1105 regmap_reg_range(0x4914, 0x4915), 1106 regmap_reg_range(0x4a00, 0x4a03), 1107 regmap_reg_range(0x4a04, 0x4a07), 1108 regmap_reg_range(0x4b00, 0x4b01), 1109 regmap_reg_range(0x4b04, 0x4b04), 1110 1111 /* port 5 */ 1112 regmap_reg_range(0x5000, 0x5001), 1113 regmap_reg_range(0x5013, 0x5013), 1114 regmap_reg_range(0x5017, 0x5017), 1115 regmap_reg_range(0x501b, 0x501b), 1116 regmap_reg_range(0x501f, 0x5020), 1117 regmap_reg_range(0x5030, 0x5030), 1118 regmap_reg_range(0x5100, 0x5115), 1119 regmap_reg_range(0x511a, 0x511f), 1120 regmap_reg_range(0x5122, 0x5127), 1121 regmap_reg_range(0x512a, 0x512b), 1122 regmap_reg_range(0x5136, 0x5139), 1123 regmap_reg_range(0x513e, 0x513f), 1124 regmap_reg_range(0x5400, 0x5401), 1125 regmap_reg_range(0x5403, 0x5403), 1126 regmap_reg_range(0x5410, 0x5417), 1127 regmap_reg_range(0x5420, 0x5423), 1128 regmap_reg_range(0x5500, 0x5507), 1129 regmap_reg_range(0x5600, 0x5612), 1130 regmap_reg_range(0x5800, 0x580f), 1131 regmap_reg_range(0x5820, 0x5827), 1132 regmap_reg_range(0x5830, 0x5837), 1133 regmap_reg_range(0x5840, 0x584b), 1134 regmap_reg_range(0x5900, 0x5907), 1135 regmap_reg_range(0x5914, 0x5915), 1136 regmap_reg_range(0x5a00, 0x5a03), 1137 regmap_reg_range(0x5a04, 0x5a07), 1138 regmap_reg_range(0x5b00, 0x5b01), 1139 regmap_reg_range(0x5b04, 0x5b04), 1140 1141 /* port 6 */ 1142 regmap_reg_range(0x6000, 0x6001), 1143 regmap_reg_range(0x6013, 0x6013), 1144 regmap_reg_range(0x6017, 0x6017), 1145 regmap_reg_range(0x601b, 0x601b), 1146 regmap_reg_range(0x601f, 0x6020), 1147 regmap_reg_range(0x6030, 0x6030), 1148 regmap_reg_range(0x6100, 0x6115), 1149 regmap_reg_range(0x611a, 0x611f), 1150 regmap_reg_range(0x6122, 0x6127), 1151 regmap_reg_range(0x612a, 0x612b), 1152 regmap_reg_range(0x6136, 0x6139), 1153 regmap_reg_range(0x613e, 0x613f), 1154 regmap_reg_range(0x6300, 0x6301), 1155 regmap_reg_range(0x6400, 0x6401), 1156 regmap_reg_range(0x6403, 0x6403), 1157 regmap_reg_range(0x6410, 0x6417), 1158 regmap_reg_range(0x6420, 0x6423), 1159 regmap_reg_range(0x6500, 0x6507), 1160 regmap_reg_range(0x6600, 0x6612), 1161 regmap_reg_range(0x6800, 0x680f), 1162 regmap_reg_range(0x6820, 0x6827), 1163 regmap_reg_range(0x6830, 0x6837), 1164 regmap_reg_range(0x6840, 0x684b), 1165 regmap_reg_range(0x6900, 0x6907), 1166 regmap_reg_range(0x6914, 0x6915), 1167 regmap_reg_range(0x6a00, 0x6a03), 1168 regmap_reg_range(0x6a04, 0x6a07), 1169 regmap_reg_range(0x6b00, 0x6b01), 1170 regmap_reg_range(0x6b04, 0x6b04), 1171 }; 1172 1173 static const struct regmap_access_table ksz9896_register_set = { 1174 .yes_ranges = ksz9896_valid_regs, 1175 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1176 }; 1177 1178 static const struct regmap_range ksz8873_valid_regs[] = { 1179 regmap_reg_range(0x00, 0x01), 1180 /* global control register */ 1181 regmap_reg_range(0x02, 0x0f), 1182 1183 /* port registers */ 1184 regmap_reg_range(0x10, 0x1d), 1185 regmap_reg_range(0x1e, 0x1f), 1186 regmap_reg_range(0x20, 0x2d), 1187 regmap_reg_range(0x2e, 0x2f), 1188 regmap_reg_range(0x30, 0x39), 1189 regmap_reg_range(0x3f, 0x3f), 1190 1191 /* advanced control registers */ 1192 regmap_reg_range(0x60, 0x6f), 1193 regmap_reg_range(0x70, 0x75), 1194 regmap_reg_range(0x76, 0x78), 1195 regmap_reg_range(0x79, 0x7a), 1196 regmap_reg_range(0x7b, 0x83), 1197 regmap_reg_range(0x8e, 0x99), 1198 regmap_reg_range(0x9a, 0xa5), 1199 regmap_reg_range(0xa6, 0xa6), 1200 regmap_reg_range(0xa7, 0xaa), 1201 regmap_reg_range(0xab, 0xae), 1202 regmap_reg_range(0xaf, 0xba), 1203 regmap_reg_range(0xbb, 0xbc), 1204 regmap_reg_range(0xbd, 0xbd), 1205 regmap_reg_range(0xc0, 0xc0), 1206 regmap_reg_range(0xc2, 0xc2), 1207 regmap_reg_range(0xc3, 0xc3), 1208 regmap_reg_range(0xc4, 0xc4), 1209 regmap_reg_range(0xc6, 0xc6), 1210 }; 1211 1212 static const struct regmap_access_table ksz8873_register_set = { 1213 .yes_ranges = ksz8873_valid_regs, 1214 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), 1215 }; 1216 1217 const struct ksz_chip_data ksz_switch_chips[] = { 1218 [KSZ8563] = { 1219 .chip_id = KSZ8563_CHIP_ID, 1220 .dev_name = "KSZ8563", 1221 .num_vlans = 4096, 1222 .num_alus = 4096, 1223 .num_statics = 16, 1224 .cpu_ports = 0x07, /* can be configured as cpu port */ 1225 .port_cnt = 3, /* total port count */ 1226 .port_nirqs = 3, 1227 .num_tx_queues = 4, 1228 .tc_cbs_supported = true, 1229 .tc_ets_supported = true, 1230 .ops = &ksz9477_dev_ops, 1231 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1232 .mib_names = ksz9477_mib_names, 1233 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1234 .reg_mib_cnt = MIB_COUNTER_NUM, 1235 .regs = ksz9477_regs, 1236 .masks = ksz9477_masks, 1237 .shifts = ksz9477_shifts, 1238 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1239 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1240 .supports_mii = {false, false, true}, 1241 .supports_rmii = {false, false, true}, 1242 .supports_rgmii = {false, false, true}, 1243 .internal_phy = {true, true, false}, 1244 .gbit_capable = {false, false, true}, 1245 .wr_table = &ksz8563_register_set, 1246 .rd_table = &ksz8563_register_set, 1247 }, 1248 1249 [KSZ8795] = { 1250 .chip_id = KSZ8795_CHIP_ID, 1251 .dev_name = "KSZ8795", 1252 .num_vlans = 4096, 1253 .num_alus = 0, 1254 .num_statics = 8, 1255 .cpu_ports = 0x10, /* can be configured as cpu port */ 1256 .port_cnt = 5, /* total cpu and user ports */ 1257 .num_tx_queues = 4, 1258 .ops = &ksz8_dev_ops, 1259 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1260 .ksz87xx_eee_link_erratum = true, 1261 .mib_names = ksz9477_mib_names, 1262 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1263 .reg_mib_cnt = MIB_COUNTER_NUM, 1264 .regs = ksz8795_regs, 1265 .masks = ksz8795_masks, 1266 .shifts = ksz8795_shifts, 1267 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1268 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1269 .supports_mii = {false, false, false, false, true}, 1270 .supports_rmii = {false, false, false, false, true}, 1271 .supports_rgmii = {false, false, false, false, true}, 1272 .internal_phy = {true, true, true, true, false}, 1273 }, 1274 1275 [KSZ8794] = { 1276 /* WARNING 1277 * ======= 1278 * KSZ8794 is similar to KSZ8795, except the port map 1279 * contains a gap between external and CPU ports, the 1280 * port map is NOT continuous. The per-port register 1281 * map is shifted accordingly too, i.e. registers at 1282 * offset 0x40 are NOT used on KSZ8794 and they ARE 1283 * used on KSZ8795 for external port 3. 1284 * external cpu 1285 * KSZ8794 0,1,2 4 1286 * KSZ8795 0,1,2,3 4 1287 * KSZ8765 0,1,2,3 4 1288 * port_cnt is configured as 5, even though it is 4 1289 */ 1290 .chip_id = KSZ8794_CHIP_ID, 1291 .dev_name = "KSZ8794", 1292 .num_vlans = 4096, 1293 .num_alus = 0, 1294 .num_statics = 8, 1295 .cpu_ports = 0x10, /* can be configured as cpu port */ 1296 .port_cnt = 5, /* total cpu and user ports */ 1297 .num_tx_queues = 4, 1298 .ops = &ksz8_dev_ops, 1299 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1300 .ksz87xx_eee_link_erratum = true, 1301 .mib_names = ksz9477_mib_names, 1302 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1303 .reg_mib_cnt = MIB_COUNTER_NUM, 1304 .regs = ksz8795_regs, 1305 .masks = ksz8795_masks, 1306 .shifts = ksz8795_shifts, 1307 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1308 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1309 .supports_mii = {false, false, false, false, true}, 1310 .supports_rmii = {false, false, false, false, true}, 1311 .supports_rgmii = {false, false, false, false, true}, 1312 .internal_phy = {true, true, true, false, false}, 1313 }, 1314 1315 [KSZ8765] = { 1316 .chip_id = KSZ8765_CHIP_ID, 1317 .dev_name = "KSZ8765", 1318 .num_vlans = 4096, 1319 .num_alus = 0, 1320 .num_statics = 8, 1321 .cpu_ports = 0x10, /* can be configured as cpu port */ 1322 .port_cnt = 5, /* total cpu and user ports */ 1323 .num_tx_queues = 4, 1324 .ops = &ksz8_dev_ops, 1325 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1326 .ksz87xx_eee_link_erratum = true, 1327 .mib_names = ksz9477_mib_names, 1328 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1329 .reg_mib_cnt = MIB_COUNTER_NUM, 1330 .regs = ksz8795_regs, 1331 .masks = ksz8795_masks, 1332 .shifts = ksz8795_shifts, 1333 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1334 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1335 .supports_mii = {false, false, false, false, true}, 1336 .supports_rmii = {false, false, false, false, true}, 1337 .supports_rgmii = {false, false, false, false, true}, 1338 .internal_phy = {true, true, true, true, false}, 1339 }, 1340 1341 [KSZ8830] = { 1342 .chip_id = KSZ8830_CHIP_ID, 1343 .dev_name = "KSZ8863/KSZ8873", 1344 .num_vlans = 16, 1345 .num_alus = 0, 1346 .num_statics = 8, 1347 .cpu_ports = 0x4, /* can be configured as cpu port */ 1348 .port_cnt = 3, 1349 .num_tx_queues = 4, 1350 .ops = &ksz8_dev_ops, 1351 .phylink_mac_ops = &ksz8830_phylink_mac_ops, 1352 .mib_names = ksz88xx_mib_names, 1353 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1354 .reg_mib_cnt = MIB_COUNTER_NUM, 1355 .regs = ksz8863_regs, 1356 .masks = ksz8863_masks, 1357 .shifts = ksz8863_shifts, 1358 .supports_mii = {false, false, true}, 1359 .supports_rmii = {false, false, true}, 1360 .internal_phy = {true, true, false}, 1361 .wr_table = &ksz8873_register_set, 1362 .rd_table = &ksz8873_register_set, 1363 }, 1364 1365 [KSZ9477] = { 1366 .chip_id = KSZ9477_CHIP_ID, 1367 .dev_name = "KSZ9477", 1368 .num_vlans = 4096, 1369 .num_alus = 4096, 1370 .num_statics = 16, 1371 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1372 .port_cnt = 7, /* total physical port count */ 1373 .port_nirqs = 4, 1374 .num_tx_queues = 4, 1375 .tc_cbs_supported = true, 1376 .tc_ets_supported = true, 1377 .ops = &ksz9477_dev_ops, 1378 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1379 .mib_names = ksz9477_mib_names, 1380 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1381 .reg_mib_cnt = MIB_COUNTER_NUM, 1382 .regs = ksz9477_regs, 1383 .masks = ksz9477_masks, 1384 .shifts = ksz9477_shifts, 1385 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1386 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1387 .supports_mii = {false, false, false, false, 1388 false, true, false}, 1389 .supports_rmii = {false, false, false, false, 1390 false, true, false}, 1391 .supports_rgmii = {false, false, false, false, 1392 false, true, false}, 1393 .internal_phy = {true, true, true, true, 1394 true, false, false}, 1395 .gbit_capable = {true, true, true, true, true, true, true}, 1396 .wr_table = &ksz9477_register_set, 1397 .rd_table = &ksz9477_register_set, 1398 }, 1399 1400 [KSZ9896] = { 1401 .chip_id = KSZ9896_CHIP_ID, 1402 .dev_name = "KSZ9896", 1403 .num_vlans = 4096, 1404 .num_alus = 4096, 1405 .num_statics = 16, 1406 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1407 .port_cnt = 6, /* total physical port count */ 1408 .port_nirqs = 2, 1409 .num_tx_queues = 4, 1410 .ops = &ksz9477_dev_ops, 1411 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1412 .mib_names = ksz9477_mib_names, 1413 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1414 .reg_mib_cnt = MIB_COUNTER_NUM, 1415 .regs = ksz9477_regs, 1416 .masks = ksz9477_masks, 1417 .shifts = ksz9477_shifts, 1418 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1419 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1420 .supports_mii = {false, false, false, false, 1421 false, true}, 1422 .supports_rmii = {false, false, false, false, 1423 false, true}, 1424 .supports_rgmii = {false, false, false, false, 1425 false, true}, 1426 .internal_phy = {true, true, true, true, 1427 true, false}, 1428 .gbit_capable = {true, true, true, true, true, true}, 1429 .wr_table = &ksz9896_register_set, 1430 .rd_table = &ksz9896_register_set, 1431 }, 1432 1433 [KSZ9897] = { 1434 .chip_id = KSZ9897_CHIP_ID, 1435 .dev_name = "KSZ9897", 1436 .num_vlans = 4096, 1437 .num_alus = 4096, 1438 .num_statics = 16, 1439 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1440 .port_cnt = 7, /* total physical port count */ 1441 .port_nirqs = 2, 1442 .num_tx_queues = 4, 1443 .ops = &ksz9477_dev_ops, 1444 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1445 .mib_names = ksz9477_mib_names, 1446 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1447 .reg_mib_cnt = MIB_COUNTER_NUM, 1448 .regs = ksz9477_regs, 1449 .masks = ksz9477_masks, 1450 .shifts = ksz9477_shifts, 1451 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1452 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1453 .supports_mii = {false, false, false, false, 1454 false, true, true}, 1455 .supports_rmii = {false, false, false, false, 1456 false, true, true}, 1457 .supports_rgmii = {false, false, false, false, 1458 false, true, true}, 1459 .internal_phy = {true, true, true, true, 1460 true, false, false}, 1461 .gbit_capable = {true, true, true, true, true, true, true}, 1462 }, 1463 1464 [KSZ9893] = { 1465 .chip_id = KSZ9893_CHIP_ID, 1466 .dev_name = "KSZ9893", 1467 .num_vlans = 4096, 1468 .num_alus = 4096, 1469 .num_statics = 16, 1470 .cpu_ports = 0x07, /* can be configured as cpu port */ 1471 .port_cnt = 3, /* total port count */ 1472 .port_nirqs = 2, 1473 .num_tx_queues = 4, 1474 .ops = &ksz9477_dev_ops, 1475 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1476 .mib_names = ksz9477_mib_names, 1477 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1478 .reg_mib_cnt = MIB_COUNTER_NUM, 1479 .regs = ksz9477_regs, 1480 .masks = ksz9477_masks, 1481 .shifts = ksz9477_shifts, 1482 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1483 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1484 .supports_mii = {false, false, true}, 1485 .supports_rmii = {false, false, true}, 1486 .supports_rgmii = {false, false, true}, 1487 .internal_phy = {true, true, false}, 1488 .gbit_capable = {true, true, true}, 1489 }, 1490 1491 [KSZ9563] = { 1492 .chip_id = KSZ9563_CHIP_ID, 1493 .dev_name = "KSZ9563", 1494 .num_vlans = 4096, 1495 .num_alus = 4096, 1496 .num_statics = 16, 1497 .cpu_ports = 0x07, /* can be configured as cpu port */ 1498 .port_cnt = 3, /* total port count */ 1499 .port_nirqs = 3, 1500 .num_tx_queues = 4, 1501 .tc_cbs_supported = true, 1502 .tc_ets_supported = true, 1503 .ops = &ksz9477_dev_ops, 1504 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1505 .mib_names = ksz9477_mib_names, 1506 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1507 .reg_mib_cnt = MIB_COUNTER_NUM, 1508 .regs = ksz9477_regs, 1509 .masks = ksz9477_masks, 1510 .shifts = ksz9477_shifts, 1511 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1512 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1513 .supports_mii = {false, false, true}, 1514 .supports_rmii = {false, false, true}, 1515 .supports_rgmii = {false, false, true}, 1516 .internal_phy = {true, true, false}, 1517 .gbit_capable = {true, true, true}, 1518 }, 1519 1520 [KSZ8567] = { 1521 .chip_id = KSZ8567_CHIP_ID, 1522 .dev_name = "KSZ8567", 1523 .num_vlans = 4096, 1524 .num_alus = 4096, 1525 .num_statics = 16, 1526 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1527 .port_cnt = 7, /* total port count */ 1528 .port_nirqs = 3, 1529 .num_tx_queues = 4, 1530 .tc_cbs_supported = true, 1531 .tc_ets_supported = true, 1532 .ops = &ksz9477_dev_ops, 1533 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1534 .mib_names = ksz9477_mib_names, 1535 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1536 .reg_mib_cnt = MIB_COUNTER_NUM, 1537 .regs = ksz9477_regs, 1538 .masks = ksz9477_masks, 1539 .shifts = ksz9477_shifts, 1540 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1541 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1542 .supports_mii = {false, false, false, false, 1543 false, true, true}, 1544 .supports_rmii = {false, false, false, false, 1545 false, true, true}, 1546 .supports_rgmii = {false, false, false, false, 1547 false, true, true}, 1548 .internal_phy = {true, true, true, true, 1549 true, false, false}, 1550 .gbit_capable = {false, false, false, false, false, 1551 true, true}, 1552 }, 1553 1554 [KSZ9567] = { 1555 .chip_id = KSZ9567_CHIP_ID, 1556 .dev_name = "KSZ9567", 1557 .num_vlans = 4096, 1558 .num_alus = 4096, 1559 .num_statics = 16, 1560 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1561 .port_cnt = 7, /* total physical port count */ 1562 .port_nirqs = 3, 1563 .num_tx_queues = 4, 1564 .tc_cbs_supported = true, 1565 .tc_ets_supported = true, 1566 .ops = &ksz9477_dev_ops, 1567 .mib_names = ksz9477_mib_names, 1568 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1569 .reg_mib_cnt = MIB_COUNTER_NUM, 1570 .regs = ksz9477_regs, 1571 .masks = ksz9477_masks, 1572 .shifts = ksz9477_shifts, 1573 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1574 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1575 .supports_mii = {false, false, false, false, 1576 false, true, true}, 1577 .supports_rmii = {false, false, false, false, 1578 false, true, true}, 1579 .supports_rgmii = {false, false, false, false, 1580 false, true, true}, 1581 .internal_phy = {true, true, true, true, 1582 true, false, false}, 1583 .gbit_capable = {true, true, true, true, true, true, true}, 1584 }, 1585 1586 [LAN9370] = { 1587 .chip_id = LAN9370_CHIP_ID, 1588 .dev_name = "LAN9370", 1589 .num_vlans = 4096, 1590 .num_alus = 1024, 1591 .num_statics = 256, 1592 .cpu_ports = 0x10, /* can be configured as cpu port */ 1593 .port_cnt = 5, /* total physical port count */ 1594 .port_nirqs = 6, 1595 .num_tx_queues = 8, 1596 .tc_cbs_supported = true, 1597 .tc_ets_supported = true, 1598 .ops = &lan937x_dev_ops, 1599 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1600 .mib_names = ksz9477_mib_names, 1601 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1602 .reg_mib_cnt = MIB_COUNTER_NUM, 1603 .regs = ksz9477_regs, 1604 .masks = lan937x_masks, 1605 .shifts = lan937x_shifts, 1606 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1607 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1608 .supports_mii = {false, false, false, false, true}, 1609 .supports_rmii = {false, false, false, false, true}, 1610 .supports_rgmii = {false, false, false, false, true}, 1611 .internal_phy = {true, true, true, true, false}, 1612 }, 1613 1614 [LAN9371] = { 1615 .chip_id = LAN9371_CHIP_ID, 1616 .dev_name = "LAN9371", 1617 .num_vlans = 4096, 1618 .num_alus = 1024, 1619 .num_statics = 256, 1620 .cpu_ports = 0x30, /* can be configured as cpu port */ 1621 .port_cnt = 6, /* total physical port count */ 1622 .port_nirqs = 6, 1623 .num_tx_queues = 8, 1624 .tc_cbs_supported = true, 1625 .tc_ets_supported = true, 1626 .ops = &lan937x_dev_ops, 1627 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1628 .mib_names = ksz9477_mib_names, 1629 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1630 .reg_mib_cnt = MIB_COUNTER_NUM, 1631 .regs = ksz9477_regs, 1632 .masks = lan937x_masks, 1633 .shifts = lan937x_shifts, 1634 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1635 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1636 .supports_mii = {false, false, false, false, true, true}, 1637 .supports_rmii = {false, false, false, false, true, true}, 1638 .supports_rgmii = {false, false, false, false, true, true}, 1639 .internal_phy = {true, true, true, true, false, false}, 1640 }, 1641 1642 [LAN9372] = { 1643 .chip_id = LAN9372_CHIP_ID, 1644 .dev_name = "LAN9372", 1645 .num_vlans = 4096, 1646 .num_alus = 1024, 1647 .num_statics = 256, 1648 .cpu_ports = 0x30, /* can be configured as cpu port */ 1649 .port_cnt = 8, /* total physical port count */ 1650 .port_nirqs = 6, 1651 .num_tx_queues = 8, 1652 .tc_cbs_supported = true, 1653 .tc_ets_supported = true, 1654 .ops = &lan937x_dev_ops, 1655 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1656 .mib_names = ksz9477_mib_names, 1657 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1658 .reg_mib_cnt = MIB_COUNTER_NUM, 1659 .regs = ksz9477_regs, 1660 .masks = lan937x_masks, 1661 .shifts = lan937x_shifts, 1662 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1663 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1664 .supports_mii = {false, false, false, false, 1665 true, true, false, false}, 1666 .supports_rmii = {false, false, false, false, 1667 true, true, false, false}, 1668 .supports_rgmii = {false, false, false, false, 1669 true, true, false, false}, 1670 .internal_phy = {true, true, true, true, 1671 false, false, true, true}, 1672 }, 1673 1674 [LAN9373] = { 1675 .chip_id = LAN9373_CHIP_ID, 1676 .dev_name = "LAN9373", 1677 .num_vlans = 4096, 1678 .num_alus = 1024, 1679 .num_statics = 256, 1680 .cpu_ports = 0x38, /* can be configured as cpu port */ 1681 .port_cnt = 5, /* total physical port count */ 1682 .port_nirqs = 6, 1683 .num_tx_queues = 8, 1684 .tc_cbs_supported = true, 1685 .tc_ets_supported = true, 1686 .ops = &lan937x_dev_ops, 1687 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1688 .mib_names = ksz9477_mib_names, 1689 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1690 .reg_mib_cnt = MIB_COUNTER_NUM, 1691 .regs = ksz9477_regs, 1692 .masks = lan937x_masks, 1693 .shifts = lan937x_shifts, 1694 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1695 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1696 .supports_mii = {false, false, false, false, 1697 true, true, false, false}, 1698 .supports_rmii = {false, false, false, false, 1699 true, true, false, false}, 1700 .supports_rgmii = {false, false, false, false, 1701 true, true, false, false}, 1702 .internal_phy = {true, true, true, false, 1703 false, false, true, true}, 1704 }, 1705 1706 [LAN9374] = { 1707 .chip_id = LAN9374_CHIP_ID, 1708 .dev_name = "LAN9374", 1709 .num_vlans = 4096, 1710 .num_alus = 1024, 1711 .num_statics = 256, 1712 .cpu_ports = 0x30, /* can be configured as cpu port */ 1713 .port_cnt = 8, /* total physical port count */ 1714 .port_nirqs = 6, 1715 .num_tx_queues = 8, 1716 .tc_cbs_supported = true, 1717 .tc_ets_supported = true, 1718 .ops = &lan937x_dev_ops, 1719 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1720 .mib_names = ksz9477_mib_names, 1721 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1722 .reg_mib_cnt = MIB_COUNTER_NUM, 1723 .regs = ksz9477_regs, 1724 .masks = lan937x_masks, 1725 .shifts = lan937x_shifts, 1726 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1727 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1728 .supports_mii = {false, false, false, false, 1729 true, true, false, false}, 1730 .supports_rmii = {false, false, false, false, 1731 true, true, false, false}, 1732 .supports_rgmii = {false, false, false, false, 1733 true, true, false, false}, 1734 .internal_phy = {true, true, true, true, 1735 false, false, true, true}, 1736 }, 1737 }; 1738 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1739 1740 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1741 { 1742 int i; 1743 1744 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1745 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1746 1747 if (chip->chip_id == prod_num) 1748 return chip; 1749 } 1750 1751 return NULL; 1752 } 1753 1754 static int ksz_check_device_id(struct ksz_device *dev) 1755 { 1756 const struct ksz_chip_data *expected_chip_data; 1757 u32 expected_chip_id; 1758 1759 if (dev->pdata) { 1760 expected_chip_id = dev->pdata->chip_id; 1761 expected_chip_data = ksz_lookup_info(expected_chip_id); 1762 if (WARN_ON(!expected_chip_data)) 1763 return -ENODEV; 1764 } else { 1765 expected_chip_data = of_device_get_match_data(dev->dev); 1766 expected_chip_id = expected_chip_data->chip_id; 1767 } 1768 1769 if (expected_chip_id != dev->chip_id) { 1770 dev_err(dev->dev, 1771 "Device tree specifies chip %s but found %s, please fix it!\n", 1772 expected_chip_data->dev_name, dev->info->dev_name); 1773 return -ENODEV; 1774 } 1775 1776 return 0; 1777 } 1778 1779 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1780 struct phylink_config *config) 1781 { 1782 struct ksz_device *dev = ds->priv; 1783 1784 if (dev->info->supports_mii[port]) 1785 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1786 1787 if (dev->info->supports_rmii[port]) 1788 __set_bit(PHY_INTERFACE_MODE_RMII, 1789 config->supported_interfaces); 1790 1791 if (dev->info->supports_rgmii[port]) 1792 phy_interface_set_rgmii(config->supported_interfaces); 1793 1794 if (dev->info->internal_phy[port]) { 1795 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1796 config->supported_interfaces); 1797 /* Compatibility for phylib's default interface type when the 1798 * phy-mode property is absent 1799 */ 1800 __set_bit(PHY_INTERFACE_MODE_GMII, 1801 config->supported_interfaces); 1802 } 1803 1804 if (dev->dev_ops->get_caps) 1805 dev->dev_ops->get_caps(dev, port, config); 1806 } 1807 1808 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 1809 { 1810 struct ethtool_pause_stats *pstats; 1811 struct rtnl_link_stats64 *stats; 1812 struct ksz_stats_raw *raw; 1813 struct ksz_port_mib *mib; 1814 1815 mib = &dev->ports[port].mib; 1816 stats = &mib->stats64; 1817 pstats = &mib->pause_stats; 1818 raw = (struct ksz_stats_raw *)mib->counters; 1819 1820 spin_lock(&mib->stats64_lock); 1821 1822 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1823 raw->rx_pause; 1824 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1825 raw->tx_pause; 1826 1827 /* HW counters are counting bytes + FCS which is not acceptable 1828 * for rtnl_link_stats64 interface 1829 */ 1830 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 1831 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 1832 1833 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1834 raw->rx_oversize; 1835 1836 stats->rx_crc_errors = raw->rx_crc_err; 1837 stats->rx_frame_errors = raw->rx_align_err; 1838 stats->rx_dropped = raw->rx_discards; 1839 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1840 stats->rx_frame_errors + stats->rx_dropped; 1841 1842 stats->tx_window_errors = raw->tx_late_col; 1843 stats->tx_fifo_errors = raw->tx_discards; 1844 stats->tx_aborted_errors = raw->tx_exc_col; 1845 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1846 stats->tx_aborted_errors; 1847 1848 stats->multicast = raw->rx_mcast; 1849 stats->collisions = raw->tx_total_col; 1850 1851 pstats->tx_pause_frames = raw->tx_pause; 1852 pstats->rx_pause_frames = raw->rx_pause; 1853 1854 spin_unlock(&mib->stats64_lock); 1855 } 1856 1857 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 1858 { 1859 struct ethtool_pause_stats *pstats; 1860 struct rtnl_link_stats64 *stats; 1861 struct ksz88xx_stats_raw *raw; 1862 struct ksz_port_mib *mib; 1863 1864 mib = &dev->ports[port].mib; 1865 stats = &mib->stats64; 1866 pstats = &mib->pause_stats; 1867 raw = (struct ksz88xx_stats_raw *)mib->counters; 1868 1869 spin_lock(&mib->stats64_lock); 1870 1871 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1872 raw->rx_pause; 1873 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1874 raw->tx_pause; 1875 1876 /* HW counters are counting bytes + FCS which is not acceptable 1877 * for rtnl_link_stats64 interface 1878 */ 1879 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 1880 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 1881 1882 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1883 raw->rx_oversize; 1884 1885 stats->rx_crc_errors = raw->rx_crc_err; 1886 stats->rx_frame_errors = raw->rx_align_err; 1887 stats->rx_dropped = raw->rx_discards; 1888 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1889 stats->rx_frame_errors + stats->rx_dropped; 1890 1891 stats->tx_window_errors = raw->tx_late_col; 1892 stats->tx_fifo_errors = raw->tx_discards; 1893 stats->tx_aborted_errors = raw->tx_exc_col; 1894 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1895 stats->tx_aborted_errors; 1896 1897 stats->multicast = raw->rx_mcast; 1898 stats->collisions = raw->tx_total_col; 1899 1900 pstats->tx_pause_frames = raw->tx_pause; 1901 pstats->rx_pause_frames = raw->rx_pause; 1902 1903 spin_unlock(&mib->stats64_lock); 1904 } 1905 1906 static void ksz_get_stats64(struct dsa_switch *ds, int port, 1907 struct rtnl_link_stats64 *s) 1908 { 1909 struct ksz_device *dev = ds->priv; 1910 struct ksz_port_mib *mib; 1911 1912 mib = &dev->ports[port].mib; 1913 1914 spin_lock(&mib->stats64_lock); 1915 memcpy(s, &mib->stats64, sizeof(*s)); 1916 spin_unlock(&mib->stats64_lock); 1917 } 1918 1919 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 1920 struct ethtool_pause_stats *pause_stats) 1921 { 1922 struct ksz_device *dev = ds->priv; 1923 struct ksz_port_mib *mib; 1924 1925 mib = &dev->ports[port].mib; 1926 1927 spin_lock(&mib->stats64_lock); 1928 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 1929 spin_unlock(&mib->stats64_lock); 1930 } 1931 1932 static void ksz_get_strings(struct dsa_switch *ds, int port, 1933 u32 stringset, uint8_t *buf) 1934 { 1935 struct ksz_device *dev = ds->priv; 1936 int i; 1937 1938 if (stringset != ETH_SS_STATS) 1939 return; 1940 1941 for (i = 0; i < dev->info->mib_cnt; i++) { 1942 memcpy(buf + i * ETH_GSTRING_LEN, 1943 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 1944 } 1945 } 1946 1947 /** 1948 * ksz_update_port_member - Adjust port forwarding rules based on STP state and 1949 * isolation settings. 1950 * @dev: A pointer to the struct ksz_device representing the device. 1951 * @port: The port number to adjust. 1952 * 1953 * This function dynamically adjusts the port membership configuration for a 1954 * specified port and other device ports, based on Spanning Tree Protocol (STP) 1955 * states and port isolation settings. Each port, including the CPU port, has a 1956 * membership register, represented as a bitfield, where each bit corresponds 1957 * to a port number. A set bit indicates permission to forward frames to that 1958 * port. This function iterates over all ports, updating the membership register 1959 * to reflect current forwarding permissions: 1960 * 1961 * 1. Forwards frames only to ports that are part of the same bridge group and 1962 * in the BR_STATE_FORWARDING state. 1963 * 2. Takes into account the isolation status of ports; ports in the 1964 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward 1965 * frames to each other, even if they are in the same bridge group. 1966 * 3. Ensures that the CPU port is included in the membership based on its 1967 * upstream port configuration, allowing for management and control traffic 1968 * to flow as required. 1969 */ 1970 static void ksz_update_port_member(struct ksz_device *dev, int port) 1971 { 1972 struct ksz_port *p = &dev->ports[port]; 1973 struct dsa_switch *ds = dev->ds; 1974 u8 port_member = 0, cpu_port; 1975 const struct dsa_port *dp; 1976 int i, j; 1977 1978 if (!dsa_is_user_port(ds, port)) 1979 return; 1980 1981 dp = dsa_to_port(ds, port); 1982 cpu_port = BIT(dsa_upstream_port(ds, port)); 1983 1984 for (i = 0; i < ds->num_ports; i++) { 1985 const struct dsa_port *other_dp = dsa_to_port(ds, i); 1986 struct ksz_port *other_p = &dev->ports[i]; 1987 u8 val = 0; 1988 1989 if (!dsa_is_user_port(ds, i)) 1990 continue; 1991 if (port == i) 1992 continue; 1993 if (!dsa_port_bridge_same(dp, other_dp)) 1994 continue; 1995 if (other_p->stp_state != BR_STATE_FORWARDING) 1996 continue; 1997 1998 /* At this point we know that "port" and "other" port [i] are in 1999 * the same bridge group and that "other" port [i] is in 2000 * forwarding stp state. If "port" is also in forwarding stp 2001 * state, we can allow forwarding from port [port] to port [i]. 2002 * Except if both ports are isolated. 2003 */ 2004 if (p->stp_state == BR_STATE_FORWARDING && 2005 !(p->isolated && other_p->isolated)) { 2006 val |= BIT(port); 2007 port_member |= BIT(i); 2008 } 2009 2010 /* Retain port [i]'s relationship to other ports than [port] */ 2011 for (j = 0; j < ds->num_ports; j++) { 2012 const struct dsa_port *third_dp; 2013 struct ksz_port *third_p; 2014 2015 if (j == i) 2016 continue; 2017 if (j == port) 2018 continue; 2019 if (!dsa_is_user_port(ds, j)) 2020 continue; 2021 third_p = &dev->ports[j]; 2022 if (third_p->stp_state != BR_STATE_FORWARDING) 2023 continue; 2024 2025 third_dp = dsa_to_port(ds, j); 2026 2027 /* Now we updating relation of the "other" port [i] to 2028 * the "third" port [j]. We already know that "other" 2029 * port [i] is in forwarding stp state and that "third" 2030 * port [j] is in forwarding stp state too. 2031 * We need to check if "other" port [i] and "third" port 2032 * [j] are in the same bridge group and not isolated 2033 * before allowing forwarding from port [i] to port [j]. 2034 */ 2035 if (dsa_port_bridge_same(other_dp, third_dp) && 2036 !(other_p->isolated && third_p->isolated)) 2037 val |= BIT(j); 2038 } 2039 2040 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 2041 } 2042 2043 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 2044 } 2045 2046 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 2047 { 2048 struct ksz_device *dev = bus->priv; 2049 u16 val; 2050 int ret; 2051 2052 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 2053 if (ret < 0) 2054 return ret; 2055 2056 return val; 2057 } 2058 2059 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 2060 u16 val) 2061 { 2062 struct ksz_device *dev = bus->priv; 2063 2064 return dev->dev_ops->w_phy(dev, addr, regnum, val); 2065 } 2066 2067 static int ksz_irq_phy_setup(struct ksz_device *dev) 2068 { 2069 struct dsa_switch *ds = dev->ds; 2070 int phy; 2071 int irq; 2072 int ret; 2073 2074 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) { 2075 if (BIT(phy) & ds->phys_mii_mask) { 2076 irq = irq_find_mapping(dev->ports[phy].pirq.domain, 2077 PORT_SRC_PHY_INT); 2078 if (irq < 0) { 2079 ret = irq; 2080 goto out; 2081 } 2082 ds->user_mii_bus->irq[phy] = irq; 2083 } 2084 } 2085 return 0; 2086 out: 2087 while (phy--) 2088 if (BIT(phy) & ds->phys_mii_mask) 2089 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2090 2091 return ret; 2092 } 2093 2094 static void ksz_irq_phy_free(struct ksz_device *dev) 2095 { 2096 struct dsa_switch *ds = dev->ds; 2097 int phy; 2098 2099 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) 2100 if (BIT(phy) & ds->phys_mii_mask) 2101 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2102 } 2103 2104 static int ksz_mdio_register(struct ksz_device *dev) 2105 { 2106 struct dsa_switch *ds = dev->ds; 2107 struct device_node *mdio_np; 2108 struct mii_bus *bus; 2109 int ret; 2110 2111 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 2112 if (!mdio_np) 2113 return 0; 2114 2115 bus = devm_mdiobus_alloc(ds->dev); 2116 if (!bus) { 2117 of_node_put(mdio_np); 2118 return -ENOMEM; 2119 } 2120 2121 bus->priv = dev; 2122 bus->read = ksz_sw_mdio_read; 2123 bus->write = ksz_sw_mdio_write; 2124 bus->name = "ksz user smi"; 2125 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 2126 bus->parent = ds->dev; 2127 bus->phy_mask = ~ds->phys_mii_mask; 2128 2129 ds->user_mii_bus = bus; 2130 2131 if (dev->irq > 0) { 2132 ret = ksz_irq_phy_setup(dev); 2133 if (ret) { 2134 of_node_put(mdio_np); 2135 return ret; 2136 } 2137 } 2138 2139 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 2140 if (ret) { 2141 dev_err(ds->dev, "unable to register MDIO bus %s\n", 2142 bus->id); 2143 if (dev->irq > 0) 2144 ksz_irq_phy_free(dev); 2145 } 2146 2147 of_node_put(mdio_np); 2148 2149 return ret; 2150 } 2151 2152 static void ksz_irq_mask(struct irq_data *d) 2153 { 2154 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2155 2156 kirq->masked |= BIT(d->hwirq); 2157 } 2158 2159 static void ksz_irq_unmask(struct irq_data *d) 2160 { 2161 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2162 2163 kirq->masked &= ~BIT(d->hwirq); 2164 } 2165 2166 static void ksz_irq_bus_lock(struct irq_data *d) 2167 { 2168 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2169 2170 mutex_lock(&kirq->dev->lock_irq); 2171 } 2172 2173 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 2174 { 2175 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2176 struct ksz_device *dev = kirq->dev; 2177 int ret; 2178 2179 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked); 2180 if (ret) 2181 dev_err(dev->dev, "failed to change IRQ mask\n"); 2182 2183 mutex_unlock(&dev->lock_irq); 2184 } 2185 2186 static const struct irq_chip ksz_irq_chip = { 2187 .name = "ksz-irq", 2188 .irq_mask = ksz_irq_mask, 2189 .irq_unmask = ksz_irq_unmask, 2190 .irq_bus_lock = ksz_irq_bus_lock, 2191 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 2192 }; 2193 2194 static int ksz_irq_domain_map(struct irq_domain *d, 2195 unsigned int irq, irq_hw_number_t hwirq) 2196 { 2197 irq_set_chip_data(irq, d->host_data); 2198 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 2199 irq_set_noprobe(irq); 2200 2201 return 0; 2202 } 2203 2204 static const struct irq_domain_ops ksz_irq_domain_ops = { 2205 .map = ksz_irq_domain_map, 2206 .xlate = irq_domain_xlate_twocell, 2207 }; 2208 2209 static void ksz_irq_free(struct ksz_irq *kirq) 2210 { 2211 int irq, virq; 2212 2213 free_irq(kirq->irq_num, kirq); 2214 2215 for (irq = 0; irq < kirq->nirqs; irq++) { 2216 virq = irq_find_mapping(kirq->domain, irq); 2217 irq_dispose_mapping(virq); 2218 } 2219 2220 irq_domain_remove(kirq->domain); 2221 } 2222 2223 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 2224 { 2225 struct ksz_irq *kirq = dev_id; 2226 unsigned int nhandled = 0; 2227 struct ksz_device *dev; 2228 unsigned int sub_irq; 2229 u8 data; 2230 int ret; 2231 u8 n; 2232 2233 dev = kirq->dev; 2234 2235 /* Read interrupt status register */ 2236 ret = ksz_read8(dev, kirq->reg_status, &data); 2237 if (ret) 2238 goto out; 2239 2240 for (n = 0; n < kirq->nirqs; ++n) { 2241 if (data & BIT(n)) { 2242 sub_irq = irq_find_mapping(kirq->domain, n); 2243 handle_nested_irq(sub_irq); 2244 ++nhandled; 2245 } 2246 } 2247 out: 2248 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2249 } 2250 2251 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 2252 { 2253 int ret, n; 2254 2255 kirq->dev = dev; 2256 kirq->masked = ~0; 2257 2258 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0, 2259 &ksz_irq_domain_ops, kirq); 2260 if (!kirq->domain) 2261 return -ENOMEM; 2262 2263 for (n = 0; n < kirq->nirqs; n++) 2264 irq_create_mapping(kirq->domain, n); 2265 2266 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2267 IRQF_ONESHOT, kirq->name, kirq); 2268 if (ret) 2269 goto out; 2270 2271 return 0; 2272 2273 out: 2274 ksz_irq_free(kirq); 2275 2276 return ret; 2277 } 2278 2279 static int ksz_girq_setup(struct ksz_device *dev) 2280 { 2281 struct ksz_irq *girq = &dev->girq; 2282 2283 girq->nirqs = dev->info->port_cnt; 2284 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2285 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2286 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2287 2288 girq->irq_num = dev->irq; 2289 2290 return ksz_irq_common_setup(dev, girq); 2291 } 2292 2293 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2294 { 2295 struct ksz_irq *pirq = &dev->ports[p].pirq; 2296 2297 pirq->nirqs = dev->info->port_nirqs; 2298 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2299 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2300 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2301 2302 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2303 if (pirq->irq_num < 0) 2304 return pirq->irq_num; 2305 2306 return ksz_irq_common_setup(dev, pirq); 2307 } 2308 2309 static int ksz_parse_drive_strength(struct ksz_device *dev); 2310 2311 static int ksz_setup(struct dsa_switch *ds) 2312 { 2313 struct ksz_device *dev = ds->priv; 2314 struct dsa_port *dp; 2315 struct ksz_port *p; 2316 const u16 *regs; 2317 int ret; 2318 2319 regs = dev->info->regs; 2320 2321 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2322 dev->info->num_vlans, GFP_KERNEL); 2323 if (!dev->vlan_cache) 2324 return -ENOMEM; 2325 2326 ret = dev->dev_ops->reset(dev); 2327 if (ret) { 2328 dev_err(ds->dev, "failed to reset switch\n"); 2329 return ret; 2330 } 2331 2332 ret = ksz_parse_drive_strength(dev); 2333 if (ret) 2334 return ret; 2335 2336 /* set broadcast storm protection 10% rate */ 2337 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2338 BROADCAST_STORM_RATE, 2339 (BROADCAST_STORM_VALUE * 2340 BROADCAST_STORM_PROT_RATE) / 100); 2341 2342 dev->dev_ops->config_cpu_port(ds); 2343 2344 dev->dev_ops->enable_stp_addr(dev); 2345 2346 ds->num_tx_queues = dev->info->num_tx_queues; 2347 2348 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 2349 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2350 2351 ksz_init_mib_timer(dev); 2352 2353 ds->configure_vlan_while_not_filtering = false; 2354 2355 if (dev->dev_ops->setup) { 2356 ret = dev->dev_ops->setup(ds); 2357 if (ret) 2358 return ret; 2359 } 2360 2361 /* Start with learning disabled on standalone user ports, and enabled 2362 * on the CPU port. In lack of other finer mechanisms, learning on the 2363 * CPU port will avoid flooding bridge local addresses on the network 2364 * in some cases. 2365 */ 2366 p = &dev->ports[dev->cpu_port]; 2367 p->learning = true; 2368 2369 if (dev->irq > 0) { 2370 ret = ksz_girq_setup(dev); 2371 if (ret) 2372 return ret; 2373 2374 dsa_switch_for_each_user_port(dp, dev->ds) { 2375 ret = ksz_pirq_setup(dev, dp->index); 2376 if (ret) 2377 goto out_girq; 2378 2379 ret = ksz_ptp_irq_setup(ds, dp->index); 2380 if (ret) 2381 goto out_pirq; 2382 } 2383 } 2384 2385 ret = ksz_ptp_clock_register(ds); 2386 if (ret) { 2387 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret); 2388 goto out_ptpirq; 2389 } 2390 2391 ret = ksz_mdio_register(dev); 2392 if (ret < 0) { 2393 dev_err(dev->dev, "failed to register the mdio"); 2394 goto out_ptp_clock_unregister; 2395 } 2396 2397 /* start switch */ 2398 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 2399 SW_START, SW_START); 2400 2401 return 0; 2402 2403 out_ptp_clock_unregister: 2404 ksz_ptp_clock_unregister(ds); 2405 out_ptpirq: 2406 if (dev->irq > 0) 2407 dsa_switch_for_each_user_port(dp, dev->ds) 2408 ksz_ptp_irq_free(ds, dp->index); 2409 out_pirq: 2410 if (dev->irq > 0) 2411 dsa_switch_for_each_user_port(dp, dev->ds) 2412 ksz_irq_free(&dev->ports[dp->index].pirq); 2413 out_girq: 2414 if (dev->irq > 0) 2415 ksz_irq_free(&dev->girq); 2416 2417 return ret; 2418 } 2419 2420 static void ksz_teardown(struct dsa_switch *ds) 2421 { 2422 struct ksz_device *dev = ds->priv; 2423 struct dsa_port *dp; 2424 2425 ksz_ptp_clock_unregister(ds); 2426 2427 if (dev->irq > 0) { 2428 dsa_switch_for_each_user_port(dp, dev->ds) { 2429 ksz_ptp_irq_free(ds, dp->index); 2430 2431 ksz_irq_free(&dev->ports[dp->index].pirq); 2432 } 2433 2434 ksz_irq_free(&dev->girq); 2435 } 2436 2437 if (dev->dev_ops->teardown) 2438 dev->dev_ops->teardown(ds); 2439 } 2440 2441 static void port_r_cnt(struct ksz_device *dev, int port) 2442 { 2443 struct ksz_port_mib *mib = &dev->ports[port].mib; 2444 u64 *dropped; 2445 2446 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2447 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2448 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2449 &mib->counters[mib->cnt_ptr]); 2450 ++mib->cnt_ptr; 2451 } 2452 2453 /* last one in storage */ 2454 dropped = &mib->counters[dev->info->mib_cnt]; 2455 2456 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2457 while (mib->cnt_ptr < dev->info->mib_cnt) { 2458 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2459 dropped, &mib->counters[mib->cnt_ptr]); 2460 ++mib->cnt_ptr; 2461 } 2462 mib->cnt_ptr = 0; 2463 } 2464 2465 static void ksz_mib_read_work(struct work_struct *work) 2466 { 2467 struct ksz_device *dev = container_of(work, struct ksz_device, 2468 mib_read.work); 2469 struct ksz_port_mib *mib; 2470 struct ksz_port *p; 2471 int i; 2472 2473 for (i = 0; i < dev->info->port_cnt; i++) { 2474 if (dsa_is_unused_port(dev->ds, i)) 2475 continue; 2476 2477 p = &dev->ports[i]; 2478 mib = &p->mib; 2479 mutex_lock(&mib->cnt_mutex); 2480 2481 /* Only read MIB counters when the port is told to do. 2482 * If not, read only dropped counters when link is not up. 2483 */ 2484 if (!p->read) { 2485 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 2486 2487 if (!netif_carrier_ok(dp->user)) 2488 mib->cnt_ptr = dev->info->reg_mib_cnt; 2489 } 2490 port_r_cnt(dev, i); 2491 p->read = false; 2492 2493 if (dev->dev_ops->r_mib_stat64) 2494 dev->dev_ops->r_mib_stat64(dev, i); 2495 2496 mutex_unlock(&mib->cnt_mutex); 2497 } 2498 2499 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 2500 } 2501 2502 void ksz_init_mib_timer(struct ksz_device *dev) 2503 { 2504 int i; 2505 2506 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 2507 2508 for (i = 0; i < dev->info->port_cnt; i++) { 2509 struct ksz_port_mib *mib = &dev->ports[i].mib; 2510 2511 dev->dev_ops->port_init_cnt(dev, i); 2512 2513 mib->cnt_ptr = 0; 2514 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 2515 } 2516 } 2517 2518 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 2519 { 2520 struct ksz_device *dev = ds->priv; 2521 u16 val = 0xffff; 2522 int ret; 2523 2524 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 2525 if (ret) 2526 return ret; 2527 2528 return val; 2529 } 2530 2531 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 2532 { 2533 struct ksz_device *dev = ds->priv; 2534 int ret; 2535 2536 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 2537 if (ret) 2538 return ret; 2539 2540 return 0; 2541 } 2542 2543 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 2544 { 2545 struct ksz_device *dev = ds->priv; 2546 2547 switch (dev->chip_id) { 2548 case KSZ8830_CHIP_ID: 2549 /* Silicon Errata Sheet (DS80000830A): 2550 * Port 1 does not work with LinkMD Cable-Testing. 2551 * Port 1 does not respond to received PAUSE control frames. 2552 */ 2553 if (!port) 2554 return MICREL_KSZ8_P1_ERRATA; 2555 break; 2556 case KSZ9477_CHIP_ID: 2557 /* KSZ9477 Errata DS80000754C 2558 * 2559 * Module 4: Energy Efficient Ethernet (EEE) feature select must 2560 * be manually disabled 2561 * The EEE feature is enabled by default, but it is not fully 2562 * operational. It must be manually disabled through register 2563 * controls. If not disabled, the PHY ports can auto-negotiate 2564 * to enable EEE, and this feature can cause link drops when 2565 * linked to another device supporting EEE. 2566 */ 2567 return MICREL_NO_EEE; 2568 } 2569 2570 return 0; 2571 } 2572 2573 static void ksz_phylink_mac_link_down(struct phylink_config *config, 2574 unsigned int mode, 2575 phy_interface_t interface) 2576 { 2577 struct dsa_port *dp = dsa_phylink_to_port(config); 2578 struct ksz_device *dev = dp->ds->priv; 2579 2580 /* Read all MIB counters when the link is going down. */ 2581 dev->ports[dp->index].read = true; 2582 /* timer started */ 2583 if (dev->mib_read_interval) 2584 schedule_delayed_work(&dev->mib_read, 0); 2585 } 2586 2587 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 2588 { 2589 struct ksz_device *dev = ds->priv; 2590 2591 if (sset != ETH_SS_STATS) 2592 return 0; 2593 2594 return dev->info->mib_cnt; 2595 } 2596 2597 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 2598 uint64_t *buf) 2599 { 2600 const struct dsa_port *dp = dsa_to_port(ds, port); 2601 struct ksz_device *dev = ds->priv; 2602 struct ksz_port_mib *mib; 2603 2604 mib = &dev->ports[port].mib; 2605 mutex_lock(&mib->cnt_mutex); 2606 2607 /* Only read dropped counters if no link. */ 2608 if (!netif_carrier_ok(dp->user)) 2609 mib->cnt_ptr = dev->info->reg_mib_cnt; 2610 port_r_cnt(dev, port); 2611 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 2612 mutex_unlock(&mib->cnt_mutex); 2613 } 2614 2615 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 2616 struct dsa_bridge bridge, 2617 bool *tx_fwd_offload, 2618 struct netlink_ext_ack *extack) 2619 { 2620 /* port_stp_state_set() will be called after to put the port in 2621 * appropriate state so there is no need to do anything. 2622 */ 2623 2624 return 0; 2625 } 2626 2627 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 2628 struct dsa_bridge bridge) 2629 { 2630 /* port_stp_state_set() will be called after to put the port in 2631 * forwarding state so there is no need to do anything. 2632 */ 2633 } 2634 2635 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 2636 { 2637 struct ksz_device *dev = ds->priv; 2638 2639 dev->dev_ops->flush_dyn_mac_table(dev, port); 2640 } 2641 2642 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 2643 { 2644 struct ksz_device *dev = ds->priv; 2645 2646 if (!dev->dev_ops->set_ageing_time) 2647 return -EOPNOTSUPP; 2648 2649 return dev->dev_ops->set_ageing_time(dev, msecs); 2650 } 2651 2652 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 2653 const unsigned char *addr, u16 vid, 2654 struct dsa_db db) 2655 { 2656 struct ksz_device *dev = ds->priv; 2657 2658 if (!dev->dev_ops->fdb_add) 2659 return -EOPNOTSUPP; 2660 2661 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 2662 } 2663 2664 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 2665 const unsigned char *addr, 2666 u16 vid, struct dsa_db db) 2667 { 2668 struct ksz_device *dev = ds->priv; 2669 2670 if (!dev->dev_ops->fdb_del) 2671 return -EOPNOTSUPP; 2672 2673 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 2674 } 2675 2676 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 2677 dsa_fdb_dump_cb_t *cb, void *data) 2678 { 2679 struct ksz_device *dev = ds->priv; 2680 2681 if (!dev->dev_ops->fdb_dump) 2682 return -EOPNOTSUPP; 2683 2684 return dev->dev_ops->fdb_dump(dev, port, cb, data); 2685 } 2686 2687 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 2688 const struct switchdev_obj_port_mdb *mdb, 2689 struct dsa_db db) 2690 { 2691 struct ksz_device *dev = ds->priv; 2692 2693 if (!dev->dev_ops->mdb_add) 2694 return -EOPNOTSUPP; 2695 2696 return dev->dev_ops->mdb_add(dev, port, mdb, db); 2697 } 2698 2699 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 2700 const struct switchdev_obj_port_mdb *mdb, 2701 struct dsa_db db) 2702 { 2703 struct ksz_device *dev = ds->priv; 2704 2705 if (!dev->dev_ops->mdb_del) 2706 return -EOPNOTSUPP; 2707 2708 return dev->dev_ops->mdb_del(dev, port, mdb, db); 2709 } 2710 2711 static int ksz_port_setup(struct dsa_switch *ds, int port) 2712 { 2713 struct ksz_device *dev = ds->priv; 2714 2715 if (!dsa_is_user_port(ds, port)) 2716 return 0; 2717 2718 /* setup user port */ 2719 dev->dev_ops->port_setup(dev, port, false); 2720 2721 /* port_stp_state_set() will be called after to enable the port so 2722 * there is no need to do anything. 2723 */ 2724 2725 return 0; 2726 } 2727 2728 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 2729 { 2730 struct ksz_device *dev = ds->priv; 2731 struct ksz_port *p; 2732 const u16 *regs; 2733 u8 data; 2734 2735 regs = dev->info->regs; 2736 2737 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 2738 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2739 2740 p = &dev->ports[port]; 2741 2742 switch (state) { 2743 case BR_STATE_DISABLED: 2744 data |= PORT_LEARN_DISABLE; 2745 break; 2746 case BR_STATE_LISTENING: 2747 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2748 break; 2749 case BR_STATE_LEARNING: 2750 data |= PORT_RX_ENABLE; 2751 if (!p->learning) 2752 data |= PORT_LEARN_DISABLE; 2753 break; 2754 case BR_STATE_FORWARDING: 2755 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 2756 if (!p->learning) 2757 data |= PORT_LEARN_DISABLE; 2758 break; 2759 case BR_STATE_BLOCKING: 2760 data |= PORT_LEARN_DISABLE; 2761 break; 2762 default: 2763 dev_err(ds->dev, "invalid STP state: %d\n", state); 2764 return; 2765 } 2766 2767 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 2768 2769 p->stp_state = state; 2770 2771 ksz_update_port_member(dev, port); 2772 } 2773 2774 static void ksz_port_teardown(struct dsa_switch *ds, int port) 2775 { 2776 struct ksz_device *dev = ds->priv; 2777 2778 switch (dev->chip_id) { 2779 case KSZ8563_CHIP_ID: 2780 case KSZ8567_CHIP_ID: 2781 case KSZ9477_CHIP_ID: 2782 case KSZ9563_CHIP_ID: 2783 case KSZ9567_CHIP_ID: 2784 case KSZ9893_CHIP_ID: 2785 case KSZ9896_CHIP_ID: 2786 case KSZ9897_CHIP_ID: 2787 if (dsa_is_user_port(ds, port)) 2788 ksz9477_port_acl_free(dev, port); 2789 } 2790 } 2791 2792 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 2793 struct switchdev_brport_flags flags, 2794 struct netlink_ext_ack *extack) 2795 { 2796 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED)) 2797 return -EINVAL; 2798 2799 return 0; 2800 } 2801 2802 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 2803 struct switchdev_brport_flags flags, 2804 struct netlink_ext_ack *extack) 2805 { 2806 struct ksz_device *dev = ds->priv; 2807 struct ksz_port *p = &dev->ports[port]; 2808 2809 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) { 2810 if (flags.mask & BR_LEARNING) 2811 p->learning = !!(flags.val & BR_LEARNING); 2812 2813 if (flags.mask & BR_ISOLATED) 2814 p->isolated = !!(flags.val & BR_ISOLATED); 2815 2816 /* Make the change take effect immediately */ 2817 ksz_port_stp_state_set(ds, port, p->stp_state); 2818 } 2819 2820 return 0; 2821 } 2822 2823 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 2824 int port, 2825 enum dsa_tag_protocol mp) 2826 { 2827 struct ksz_device *dev = ds->priv; 2828 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 2829 2830 if (dev->chip_id == KSZ8795_CHIP_ID || 2831 dev->chip_id == KSZ8794_CHIP_ID || 2832 dev->chip_id == KSZ8765_CHIP_ID) 2833 proto = DSA_TAG_PROTO_KSZ8795; 2834 2835 if (dev->chip_id == KSZ8830_CHIP_ID || 2836 dev->chip_id == KSZ8563_CHIP_ID || 2837 dev->chip_id == KSZ9893_CHIP_ID || 2838 dev->chip_id == KSZ9563_CHIP_ID) 2839 proto = DSA_TAG_PROTO_KSZ9893; 2840 2841 if (dev->chip_id == KSZ8567_CHIP_ID || 2842 dev->chip_id == KSZ9477_CHIP_ID || 2843 dev->chip_id == KSZ9896_CHIP_ID || 2844 dev->chip_id == KSZ9897_CHIP_ID || 2845 dev->chip_id == KSZ9567_CHIP_ID) 2846 proto = DSA_TAG_PROTO_KSZ9477; 2847 2848 if (is_lan937x(dev)) 2849 proto = DSA_TAG_PROTO_LAN937X; 2850 2851 return proto; 2852 } 2853 2854 static int ksz_connect_tag_protocol(struct dsa_switch *ds, 2855 enum dsa_tag_protocol proto) 2856 { 2857 struct ksz_tagger_data *tagger_data; 2858 2859 switch (proto) { 2860 case DSA_TAG_PROTO_KSZ8795: 2861 return 0; 2862 case DSA_TAG_PROTO_KSZ9893: 2863 case DSA_TAG_PROTO_KSZ9477: 2864 case DSA_TAG_PROTO_LAN937X: 2865 tagger_data = ksz_tagger_data(ds); 2866 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 2867 return 0; 2868 default: 2869 return -EPROTONOSUPPORT; 2870 } 2871 } 2872 2873 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 2874 bool flag, struct netlink_ext_ack *extack) 2875 { 2876 struct ksz_device *dev = ds->priv; 2877 2878 if (!dev->dev_ops->vlan_filtering) 2879 return -EOPNOTSUPP; 2880 2881 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 2882 } 2883 2884 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 2885 const struct switchdev_obj_port_vlan *vlan, 2886 struct netlink_ext_ack *extack) 2887 { 2888 struct ksz_device *dev = ds->priv; 2889 2890 if (!dev->dev_ops->vlan_add) 2891 return -EOPNOTSUPP; 2892 2893 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 2894 } 2895 2896 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 2897 const struct switchdev_obj_port_vlan *vlan) 2898 { 2899 struct ksz_device *dev = ds->priv; 2900 2901 if (!dev->dev_ops->vlan_del) 2902 return -EOPNOTSUPP; 2903 2904 return dev->dev_ops->vlan_del(dev, port, vlan); 2905 } 2906 2907 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 2908 struct dsa_mall_mirror_tc_entry *mirror, 2909 bool ingress, struct netlink_ext_ack *extack) 2910 { 2911 struct ksz_device *dev = ds->priv; 2912 2913 if (!dev->dev_ops->mirror_add) 2914 return -EOPNOTSUPP; 2915 2916 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 2917 } 2918 2919 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 2920 struct dsa_mall_mirror_tc_entry *mirror) 2921 { 2922 struct ksz_device *dev = ds->priv; 2923 2924 if (dev->dev_ops->mirror_del) 2925 dev->dev_ops->mirror_del(dev, port, mirror); 2926 } 2927 2928 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 2929 { 2930 struct ksz_device *dev = ds->priv; 2931 2932 if (!dev->dev_ops->change_mtu) 2933 return -EOPNOTSUPP; 2934 2935 return dev->dev_ops->change_mtu(dev, port, mtu); 2936 } 2937 2938 static int ksz_max_mtu(struct dsa_switch *ds, int port) 2939 { 2940 struct ksz_device *dev = ds->priv; 2941 2942 switch (dev->chip_id) { 2943 case KSZ8795_CHIP_ID: 2944 case KSZ8794_CHIP_ID: 2945 case KSZ8765_CHIP_ID: 2946 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2947 case KSZ8830_CHIP_ID: 2948 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2949 case KSZ8563_CHIP_ID: 2950 case KSZ8567_CHIP_ID: 2951 case KSZ9477_CHIP_ID: 2952 case KSZ9563_CHIP_ID: 2953 case KSZ9567_CHIP_ID: 2954 case KSZ9893_CHIP_ID: 2955 case KSZ9896_CHIP_ID: 2956 case KSZ9897_CHIP_ID: 2957 case LAN9370_CHIP_ID: 2958 case LAN9371_CHIP_ID: 2959 case LAN9372_CHIP_ID: 2960 case LAN9373_CHIP_ID: 2961 case LAN9374_CHIP_ID: 2962 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2963 } 2964 2965 return -EOPNOTSUPP; 2966 } 2967 2968 static int ksz_validate_eee(struct dsa_switch *ds, int port) 2969 { 2970 struct ksz_device *dev = ds->priv; 2971 2972 if (!dev->info->internal_phy[port]) 2973 return -EOPNOTSUPP; 2974 2975 switch (dev->chip_id) { 2976 case KSZ8563_CHIP_ID: 2977 case KSZ8567_CHIP_ID: 2978 case KSZ9477_CHIP_ID: 2979 case KSZ9563_CHIP_ID: 2980 case KSZ9567_CHIP_ID: 2981 case KSZ9893_CHIP_ID: 2982 case KSZ9896_CHIP_ID: 2983 case KSZ9897_CHIP_ID: 2984 return 0; 2985 } 2986 2987 return -EOPNOTSUPP; 2988 } 2989 2990 static int ksz_get_mac_eee(struct dsa_switch *ds, int port, 2991 struct ethtool_keee *e) 2992 { 2993 int ret; 2994 2995 ret = ksz_validate_eee(ds, port); 2996 if (ret) 2997 return ret; 2998 2999 /* There is no documented control of Tx LPI configuration. */ 3000 e->tx_lpi_enabled = true; 3001 3002 /* There is no documented control of Tx LPI timer. According to tests 3003 * Tx LPI timer seems to be set by default to minimal value. 3004 */ 3005 e->tx_lpi_timer = 0; 3006 3007 return 0; 3008 } 3009 3010 static int ksz_set_mac_eee(struct dsa_switch *ds, int port, 3011 struct ethtool_keee *e) 3012 { 3013 struct ksz_device *dev = ds->priv; 3014 int ret; 3015 3016 ret = ksz_validate_eee(ds, port); 3017 if (ret) 3018 return ret; 3019 3020 if (!e->tx_lpi_enabled) { 3021 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 3022 return -EINVAL; 3023 } 3024 3025 if (e->tx_lpi_timer) { 3026 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 3027 return -EINVAL; 3028 } 3029 3030 return 0; 3031 } 3032 3033 static void ksz_set_xmii(struct ksz_device *dev, int port, 3034 phy_interface_t interface) 3035 { 3036 const u8 *bitval = dev->info->xmii_ctrl1; 3037 struct ksz_port *p = &dev->ports[port]; 3038 const u16 *regs = dev->info->regs; 3039 u8 data8; 3040 3041 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3042 3043 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 3044 P_RGMII_ID_EG_ENABLE); 3045 3046 switch (interface) { 3047 case PHY_INTERFACE_MODE_MII: 3048 data8 |= bitval[P_MII_SEL]; 3049 break; 3050 case PHY_INTERFACE_MODE_RMII: 3051 data8 |= bitval[P_RMII_SEL]; 3052 break; 3053 case PHY_INTERFACE_MODE_GMII: 3054 data8 |= bitval[P_GMII_SEL]; 3055 break; 3056 case PHY_INTERFACE_MODE_RGMII: 3057 case PHY_INTERFACE_MODE_RGMII_ID: 3058 case PHY_INTERFACE_MODE_RGMII_TXID: 3059 case PHY_INTERFACE_MODE_RGMII_RXID: 3060 data8 |= bitval[P_RGMII_SEL]; 3061 /* On KSZ9893, disable RGMII in-band status support */ 3062 if (dev->chip_id == KSZ9893_CHIP_ID || 3063 dev->chip_id == KSZ8563_CHIP_ID || 3064 dev->chip_id == KSZ9563_CHIP_ID) 3065 data8 &= ~P_MII_MAC_MODE; 3066 break; 3067 default: 3068 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 3069 phy_modes(interface), port); 3070 return; 3071 } 3072 3073 if (p->rgmii_tx_val) 3074 data8 |= P_RGMII_ID_EG_ENABLE; 3075 3076 if (p->rgmii_rx_val) 3077 data8 |= P_RGMII_ID_IG_ENABLE; 3078 3079 /* Write the updated value */ 3080 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3081 } 3082 3083 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 3084 { 3085 const u8 *bitval = dev->info->xmii_ctrl1; 3086 const u16 *regs = dev->info->regs; 3087 phy_interface_t interface; 3088 u8 data8; 3089 u8 val; 3090 3091 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3092 3093 val = FIELD_GET(P_MII_SEL_M, data8); 3094 3095 if (val == bitval[P_MII_SEL]) { 3096 if (gbit) 3097 interface = PHY_INTERFACE_MODE_GMII; 3098 else 3099 interface = PHY_INTERFACE_MODE_MII; 3100 } else if (val == bitval[P_RMII_SEL]) { 3101 interface = PHY_INTERFACE_MODE_RGMII; 3102 } else { 3103 interface = PHY_INTERFACE_MODE_RGMII; 3104 if (data8 & P_RGMII_ID_EG_ENABLE) 3105 interface = PHY_INTERFACE_MODE_RGMII_TXID; 3106 if (data8 & P_RGMII_ID_IG_ENABLE) { 3107 interface = PHY_INTERFACE_MODE_RGMII_RXID; 3108 if (data8 & P_RGMII_ID_EG_ENABLE) 3109 interface = PHY_INTERFACE_MODE_RGMII_ID; 3110 } 3111 } 3112 3113 return interface; 3114 } 3115 3116 static void ksz8830_phylink_mac_config(struct phylink_config *config, 3117 unsigned int mode, 3118 const struct phylink_link_state *state) 3119 { 3120 struct dsa_port *dp = dsa_phylink_to_port(config); 3121 struct ksz_device *dev = dp->ds->priv; 3122 3123 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN); 3124 } 3125 3126 static void ksz_phylink_mac_config(struct phylink_config *config, 3127 unsigned int mode, 3128 const struct phylink_link_state *state) 3129 { 3130 struct dsa_port *dp = dsa_phylink_to_port(config); 3131 struct ksz_device *dev = dp->ds->priv; 3132 int port = dp->index; 3133 3134 /* Internal PHYs */ 3135 if (dev->info->internal_phy[port]) 3136 return; 3137 3138 if (phylink_autoneg_inband(mode)) { 3139 dev_err(dev->dev, "In-band AN not supported!\n"); 3140 return; 3141 } 3142 3143 ksz_set_xmii(dev, port, state->interface); 3144 3145 if (dev->dev_ops->setup_rgmii_delay) 3146 dev->dev_ops->setup_rgmii_delay(dev, port); 3147 } 3148 3149 bool ksz_get_gbit(struct ksz_device *dev, int port) 3150 { 3151 const u8 *bitval = dev->info->xmii_ctrl1; 3152 const u16 *regs = dev->info->regs; 3153 bool gbit = false; 3154 u8 data8; 3155 bool val; 3156 3157 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3158 3159 val = FIELD_GET(P_GMII_1GBIT_M, data8); 3160 3161 if (val == bitval[P_GMII_1GBIT]) 3162 gbit = true; 3163 3164 return gbit; 3165 } 3166 3167 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 3168 { 3169 const u8 *bitval = dev->info->xmii_ctrl1; 3170 const u16 *regs = dev->info->regs; 3171 u8 data8; 3172 3173 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3174 3175 data8 &= ~P_GMII_1GBIT_M; 3176 3177 if (gbit) 3178 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 3179 else 3180 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 3181 3182 /* Write the updated value */ 3183 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3184 } 3185 3186 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 3187 { 3188 const u8 *bitval = dev->info->xmii_ctrl0; 3189 const u16 *regs = dev->info->regs; 3190 u8 data8; 3191 3192 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 3193 3194 data8 &= ~P_MII_100MBIT_M; 3195 3196 if (speed == SPEED_100) 3197 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 3198 else 3199 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 3200 3201 /* Write the updated value */ 3202 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 3203 } 3204 3205 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 3206 { 3207 if (speed == SPEED_1000) 3208 ksz_set_gbit(dev, port, true); 3209 else 3210 ksz_set_gbit(dev, port, false); 3211 3212 if (speed == SPEED_100 || speed == SPEED_10) 3213 ksz_set_100_10mbit(dev, port, speed); 3214 } 3215 3216 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 3217 bool tx_pause, bool rx_pause) 3218 { 3219 const u8 *bitval = dev->info->xmii_ctrl0; 3220 const u32 *masks = dev->info->masks; 3221 const u16 *regs = dev->info->regs; 3222 u8 mask; 3223 u8 val; 3224 3225 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 3226 masks[P_MII_RX_FLOW_CTRL]; 3227 3228 if (duplex == DUPLEX_FULL) 3229 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 3230 else 3231 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 3232 3233 if (tx_pause) 3234 val |= masks[P_MII_TX_FLOW_CTRL]; 3235 3236 if (rx_pause) 3237 val |= masks[P_MII_RX_FLOW_CTRL]; 3238 3239 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 3240 } 3241 3242 static void ksz9477_phylink_mac_link_up(struct phylink_config *config, 3243 struct phy_device *phydev, 3244 unsigned int mode, 3245 phy_interface_t interface, 3246 int speed, int duplex, bool tx_pause, 3247 bool rx_pause) 3248 { 3249 struct dsa_port *dp = dsa_phylink_to_port(config); 3250 struct ksz_device *dev = dp->ds->priv; 3251 int port = dp->index; 3252 struct ksz_port *p; 3253 3254 p = &dev->ports[port]; 3255 3256 /* Internal PHYs */ 3257 if (dev->info->internal_phy[port]) 3258 return; 3259 3260 p->phydev.speed = speed; 3261 3262 ksz_port_set_xmii_speed(dev, port, speed); 3263 3264 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 3265 } 3266 3267 static int ksz_switch_detect(struct ksz_device *dev) 3268 { 3269 u8 id1, id2, id4; 3270 u16 id16; 3271 u32 id32; 3272 int ret; 3273 3274 /* read chip id */ 3275 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 3276 if (ret) 3277 return ret; 3278 3279 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 3280 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 3281 3282 switch (id1) { 3283 case KSZ87_FAMILY_ID: 3284 if (id2 == KSZ87_CHIP_ID_95) { 3285 u8 val; 3286 3287 dev->chip_id = KSZ8795_CHIP_ID; 3288 3289 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 3290 if (val & KSZ8_PORT_FIBER_MODE) 3291 dev->chip_id = KSZ8765_CHIP_ID; 3292 } else if (id2 == KSZ87_CHIP_ID_94) { 3293 dev->chip_id = KSZ8794_CHIP_ID; 3294 } else { 3295 return -ENODEV; 3296 } 3297 break; 3298 case KSZ88_FAMILY_ID: 3299 if (id2 == KSZ88_CHIP_ID_63) 3300 dev->chip_id = KSZ8830_CHIP_ID; 3301 else 3302 return -ENODEV; 3303 break; 3304 default: 3305 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 3306 if (ret) 3307 return ret; 3308 3309 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 3310 id32 &= ~0xFF; 3311 3312 switch (id32) { 3313 case KSZ9477_CHIP_ID: 3314 case KSZ9896_CHIP_ID: 3315 case KSZ9897_CHIP_ID: 3316 case KSZ9567_CHIP_ID: 3317 case KSZ8567_CHIP_ID: 3318 case LAN9370_CHIP_ID: 3319 case LAN9371_CHIP_ID: 3320 case LAN9372_CHIP_ID: 3321 case LAN9373_CHIP_ID: 3322 case LAN9374_CHIP_ID: 3323 dev->chip_id = id32; 3324 break; 3325 case KSZ9893_CHIP_ID: 3326 ret = ksz_read8(dev, REG_CHIP_ID4, 3327 &id4); 3328 if (ret) 3329 return ret; 3330 3331 if (id4 == SKU_ID_KSZ8563) 3332 dev->chip_id = KSZ8563_CHIP_ID; 3333 else if (id4 == SKU_ID_KSZ9563) 3334 dev->chip_id = KSZ9563_CHIP_ID; 3335 else 3336 dev->chip_id = KSZ9893_CHIP_ID; 3337 3338 break; 3339 default: 3340 dev_err(dev->dev, 3341 "unsupported switch detected %x)\n", id32); 3342 return -ENODEV; 3343 } 3344 } 3345 return 0; 3346 } 3347 3348 static int ksz_cls_flower_add(struct dsa_switch *ds, int port, 3349 struct flow_cls_offload *cls, bool ingress) 3350 { 3351 struct ksz_device *dev = ds->priv; 3352 3353 switch (dev->chip_id) { 3354 case KSZ8563_CHIP_ID: 3355 case KSZ8567_CHIP_ID: 3356 case KSZ9477_CHIP_ID: 3357 case KSZ9563_CHIP_ID: 3358 case KSZ9567_CHIP_ID: 3359 case KSZ9893_CHIP_ID: 3360 case KSZ9896_CHIP_ID: 3361 case KSZ9897_CHIP_ID: 3362 return ksz9477_cls_flower_add(ds, port, cls, ingress); 3363 } 3364 3365 return -EOPNOTSUPP; 3366 } 3367 3368 static int ksz_cls_flower_del(struct dsa_switch *ds, int port, 3369 struct flow_cls_offload *cls, bool ingress) 3370 { 3371 struct ksz_device *dev = ds->priv; 3372 3373 switch (dev->chip_id) { 3374 case KSZ8563_CHIP_ID: 3375 case KSZ8567_CHIP_ID: 3376 case KSZ9477_CHIP_ID: 3377 case KSZ9563_CHIP_ID: 3378 case KSZ9567_CHIP_ID: 3379 case KSZ9893_CHIP_ID: 3380 case KSZ9896_CHIP_ID: 3381 case KSZ9897_CHIP_ID: 3382 return ksz9477_cls_flower_del(ds, port, cls, ingress); 3383 } 3384 3385 return -EOPNOTSUPP; 3386 } 3387 3388 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 3389 * is converted to Hex-decimal using the successive multiplication method. On 3390 * every step, integer part is taken and decimal part is carry forwarded. 3391 */ 3392 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 3393 { 3394 u32 cinc = 0; 3395 u32 txrate; 3396 u32 rate; 3397 u8 temp; 3398 u8 i; 3399 3400 txrate = idle_slope - send_slope; 3401 3402 if (!txrate) 3403 return -EINVAL; 3404 3405 rate = idle_slope; 3406 3407 /* 24 bit register */ 3408 for (i = 0; i < 6; i++) { 3409 rate = rate * 16; 3410 3411 temp = rate / txrate; 3412 3413 rate %= txrate; 3414 3415 cinc = ((cinc << 4) | temp); 3416 } 3417 3418 *bw = cinc; 3419 3420 return 0; 3421 } 3422 3423 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 3424 u8 shaper) 3425 { 3426 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 3427 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 3428 FIELD_PREP(MTI_SHAPING_M, shaper)); 3429 } 3430 3431 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 3432 struct tc_cbs_qopt_offload *qopt) 3433 { 3434 struct ksz_device *dev = ds->priv; 3435 int ret; 3436 u32 bw; 3437 3438 if (!dev->info->tc_cbs_supported) 3439 return -EOPNOTSUPP; 3440 3441 if (qopt->queue > dev->info->num_tx_queues) 3442 return -EINVAL; 3443 3444 /* Queue Selection */ 3445 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 3446 if (ret) 3447 return ret; 3448 3449 if (!qopt->enable) 3450 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3451 MTI_SHAPING_OFF); 3452 3453 /* High Credit */ 3454 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 3455 qopt->hicredit); 3456 if (ret) 3457 return ret; 3458 3459 /* Low Credit */ 3460 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 3461 qopt->locredit); 3462 if (ret) 3463 return ret; 3464 3465 /* Credit Increment Register */ 3466 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 3467 if (ret) 3468 return ret; 3469 3470 if (dev->dev_ops->tc_cbs_set_cinc) { 3471 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 3472 if (ret) 3473 return ret; 3474 } 3475 3476 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3477 MTI_SHAPING_SRP); 3478 } 3479 3480 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 3481 { 3482 int queue, ret; 3483 3484 /* Configuration will not take effect until the last Port Queue X 3485 * Egress Limit Control Register is written. 3486 */ 3487 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3488 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 3489 KSZ9477_OUT_RATE_NO_LIMIT); 3490 if (ret) 3491 return ret; 3492 } 3493 3494 return 0; 3495 } 3496 3497 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 3498 int band) 3499 { 3500 /* Compared to queues, bands prioritize packets differently. In strict 3501 * priority mode, the lowest priority is assigned to Queue 0 while the 3502 * highest priority is given to Band 0. 3503 */ 3504 return p->bands - 1 - band; 3505 } 3506 3507 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 3508 { 3509 int ret; 3510 3511 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3512 if (ret) 3513 return ret; 3514 3515 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3516 MTI_SHAPING_OFF); 3517 } 3518 3519 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 3520 int weight) 3521 { 3522 int ret; 3523 3524 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3525 if (ret) 3526 return ret; 3527 3528 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3529 MTI_SHAPING_OFF); 3530 if (ret) 3531 return ret; 3532 3533 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 3534 } 3535 3536 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 3537 struct tc_ets_qopt_offload_replace_params *p) 3538 { 3539 int ret, band, tc_prio; 3540 u32 queue_map = 0; 3541 3542 /* In order to ensure proper prioritization, it is necessary to set the 3543 * rate limit for the related queue to zero. Otherwise strict priority 3544 * or WRR mode will not work. This is a hardware limitation. 3545 */ 3546 ret = ksz_disable_egress_rate_limit(dev, port); 3547 if (ret) 3548 return ret; 3549 3550 /* Configure queue scheduling mode for all bands. Currently only strict 3551 * prio mode is supported. 3552 */ 3553 for (band = 0; band < p->bands; band++) { 3554 int queue = ksz_ets_band_to_queue(p, band); 3555 3556 ret = ksz_queue_set_strict(dev, port, queue); 3557 if (ret) 3558 return ret; 3559 } 3560 3561 /* Configure the mapping between traffic classes and queues. Note: 3562 * priomap variable support 16 traffic classes, but the chip can handle 3563 * only 8 classes. 3564 */ 3565 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 3566 int queue; 3567 3568 if (tc_prio > KSZ9477_MAX_TC_PRIO) 3569 break; 3570 3571 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 3572 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3573 } 3574 3575 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3576 } 3577 3578 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 3579 { 3580 int ret, queue, tc_prio, s; 3581 u32 queue_map = 0; 3582 3583 /* To restore the default chip configuration, set all queues to use the 3584 * WRR scheduler with a weight of 1. 3585 */ 3586 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3587 ret = ksz_queue_set_wrr(dev, port, queue, 3588 KSZ9477_DEFAULT_WRR_WEIGHT); 3589 if (ret) 3590 return ret; 3591 } 3592 3593 switch (dev->info->num_tx_queues) { 3594 case 2: 3595 s = 2; 3596 break; 3597 case 4: 3598 s = 1; 3599 break; 3600 case 8: 3601 s = 0; 3602 break; 3603 default: 3604 return -EINVAL; 3605 } 3606 3607 /* Revert the queue mapping for TC-priority to its default setting on 3608 * the chip. 3609 */ 3610 for (tc_prio = 0; tc_prio <= KSZ9477_MAX_TC_PRIO; tc_prio++) { 3611 int queue; 3612 3613 queue = tc_prio >> s; 3614 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3615 } 3616 3617 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3618 } 3619 3620 static int ksz_tc_ets_validate(struct ksz_device *dev, int port, 3621 struct tc_ets_qopt_offload_replace_params *p) 3622 { 3623 int band; 3624 3625 /* Since it is not feasible to share one port among multiple qdisc, 3626 * the user must configure all available queues appropriately. 3627 */ 3628 if (p->bands != dev->info->num_tx_queues) { 3629 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 3630 dev->info->num_tx_queues); 3631 return -EOPNOTSUPP; 3632 } 3633 3634 for (band = 0; band < p->bands; ++band) { 3635 /* The KSZ switches utilize a weighted round robin configuration 3636 * where a certain number of packets can be transmitted from a 3637 * queue before the next queue is serviced. For more information 3638 * on this, refer to section 5.2.8.4 of the KSZ8565R 3639 * documentation on the Port Transmit Queue Control 1 Register. 3640 * However, the current ETS Qdisc implementation (as of February 3641 * 2023) assigns a weight to each queue based on the number of 3642 * bytes or extrapolated bandwidth in percentages. Since this 3643 * differs from the KSZ switches' method and we don't want to 3644 * fake support by converting bytes to packets, it is better to 3645 * return an error instead. 3646 */ 3647 if (p->quanta[band]) { 3648 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 3649 return -EOPNOTSUPP; 3650 } 3651 } 3652 3653 return 0; 3654 } 3655 3656 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 3657 struct tc_ets_qopt_offload *qopt) 3658 { 3659 struct ksz_device *dev = ds->priv; 3660 int ret; 3661 3662 if (!dev->info->tc_ets_supported) 3663 return -EOPNOTSUPP; 3664 3665 if (qopt->parent != TC_H_ROOT) { 3666 dev_err(dev->dev, "Parent should be \"root\"\n"); 3667 return -EOPNOTSUPP; 3668 } 3669 3670 switch (qopt->command) { 3671 case TC_ETS_REPLACE: 3672 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 3673 if (ret) 3674 return ret; 3675 3676 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 3677 case TC_ETS_DESTROY: 3678 return ksz_tc_ets_del(dev, port); 3679 case TC_ETS_STATS: 3680 case TC_ETS_GRAFT: 3681 return -EOPNOTSUPP; 3682 } 3683 3684 return -EOPNOTSUPP; 3685 } 3686 3687 static int ksz_setup_tc(struct dsa_switch *ds, int port, 3688 enum tc_setup_type type, void *type_data) 3689 { 3690 switch (type) { 3691 case TC_SETUP_QDISC_CBS: 3692 return ksz_setup_tc_cbs(ds, port, type_data); 3693 case TC_SETUP_QDISC_ETS: 3694 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 3695 default: 3696 return -EOPNOTSUPP; 3697 } 3698 } 3699 3700 static void ksz_get_wol(struct dsa_switch *ds, int port, 3701 struct ethtool_wolinfo *wol) 3702 { 3703 struct ksz_device *dev = ds->priv; 3704 3705 if (dev->dev_ops->get_wol) 3706 dev->dev_ops->get_wol(dev, port, wol); 3707 } 3708 3709 static int ksz_set_wol(struct dsa_switch *ds, int port, 3710 struct ethtool_wolinfo *wol) 3711 { 3712 struct ksz_device *dev = ds->priv; 3713 3714 if (dev->dev_ops->set_wol) 3715 return dev->dev_ops->set_wol(dev, port, wol); 3716 3717 return -EOPNOTSUPP; 3718 } 3719 3720 static int ksz_port_set_mac_address(struct dsa_switch *ds, int port, 3721 const unsigned char *addr) 3722 { 3723 struct dsa_port *dp = dsa_to_port(ds, port); 3724 struct ethtool_wolinfo wol; 3725 3726 if (dp->hsr_dev) { 3727 dev_err(ds->dev, 3728 "Cannot change MAC address on port %d with active HSR offload\n", 3729 port); 3730 return -EBUSY; 3731 } 3732 3733 ksz_get_wol(ds, dp->index, &wol); 3734 if (wol.wolopts & WAKE_MAGIC) { 3735 dev_err(ds->dev, 3736 "Cannot change MAC address on port %d with active Wake on Magic Packet\n", 3737 port); 3738 return -EBUSY; 3739 } 3740 3741 return 0; 3742 } 3743 3744 /** 3745 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port 3746 * can be used as a global address. 3747 * @ds: Pointer to the DSA switch structure. 3748 * @port: The port number on which the MAC address is to be checked. 3749 * 3750 * This function examines the MAC address set on the specified port and 3751 * determines if it can be used as a global address for the switch. 3752 * 3753 * Return: true if the port's MAC address can be used as a global address, false 3754 * otherwise. 3755 */ 3756 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port) 3757 { 3758 struct net_device *user = dsa_to_port(ds, port)->user; 3759 const unsigned char *addr = user->dev_addr; 3760 struct ksz_switch_macaddr *switch_macaddr; 3761 struct ksz_device *dev = ds->priv; 3762 3763 ASSERT_RTNL(); 3764 3765 switch_macaddr = dev->switch_macaddr; 3766 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr)) 3767 return false; 3768 3769 return true; 3770 } 3771 3772 /** 3773 * ksz_switch_macaddr_get - Program the switch's MAC address register. 3774 * @ds: DSA switch instance. 3775 * @port: Port number. 3776 * @extack: Netlink extended acknowledgment. 3777 * 3778 * This function programs the switch's MAC address register with the MAC address 3779 * of the requesting user port. This single address is used by the switch for 3780 * multiple features like HSR self-address filtering and WoL. Other user ports 3781 * can share ownership of this address as long as their MAC address is the same. 3782 * The MAC addresses of user ports must not change while they have ownership of 3783 * the switch MAC address. 3784 * 3785 * Return: 0 on success, or other error codes on failure. 3786 */ 3787 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 3788 struct netlink_ext_ack *extack) 3789 { 3790 struct net_device *user = dsa_to_port(ds, port)->user; 3791 const unsigned char *addr = user->dev_addr; 3792 struct ksz_switch_macaddr *switch_macaddr; 3793 struct ksz_device *dev = ds->priv; 3794 const u16 *regs = dev->info->regs; 3795 int i, ret; 3796 3797 /* Make sure concurrent MAC address changes are blocked */ 3798 ASSERT_RTNL(); 3799 3800 switch_macaddr = dev->switch_macaddr; 3801 if (switch_macaddr) { 3802 if (!ether_addr_equal(switch_macaddr->addr, addr)) { 3803 NL_SET_ERR_MSG_FMT_MOD(extack, 3804 "Switch already configured for MAC address %pM", 3805 switch_macaddr->addr); 3806 return -EBUSY; 3807 } 3808 3809 refcount_inc(&switch_macaddr->refcount); 3810 return 0; 3811 } 3812 3813 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL); 3814 if (!switch_macaddr) 3815 return -ENOMEM; 3816 3817 ether_addr_copy(switch_macaddr->addr, addr); 3818 refcount_set(&switch_macaddr->refcount, 1); 3819 dev->switch_macaddr = switch_macaddr; 3820 3821 /* Program the switch MAC address to hardware */ 3822 for (i = 0; i < ETH_ALEN; i++) { 3823 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, addr[i]); 3824 if (ret) 3825 goto macaddr_drop; 3826 } 3827 3828 return 0; 3829 3830 macaddr_drop: 3831 dev->switch_macaddr = NULL; 3832 refcount_set(&switch_macaddr->refcount, 0); 3833 kfree(switch_macaddr); 3834 3835 return ret; 3836 } 3837 3838 void ksz_switch_macaddr_put(struct dsa_switch *ds) 3839 { 3840 struct ksz_switch_macaddr *switch_macaddr; 3841 struct ksz_device *dev = ds->priv; 3842 const u16 *regs = dev->info->regs; 3843 int i; 3844 3845 /* Make sure concurrent MAC address changes are blocked */ 3846 ASSERT_RTNL(); 3847 3848 switch_macaddr = dev->switch_macaddr; 3849 if (!refcount_dec_and_test(&switch_macaddr->refcount)) 3850 return; 3851 3852 for (i = 0; i < ETH_ALEN; i++) 3853 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0); 3854 3855 dev->switch_macaddr = NULL; 3856 kfree(switch_macaddr); 3857 } 3858 3859 static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr, 3860 struct netlink_ext_ack *extack) 3861 { 3862 struct ksz_device *dev = ds->priv; 3863 enum hsr_version ver; 3864 int ret; 3865 3866 ret = hsr_get_version(hsr, &ver); 3867 if (ret) 3868 return ret; 3869 3870 if (dev->chip_id != KSZ9477_CHIP_ID) { 3871 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload"); 3872 return -EOPNOTSUPP; 3873 } 3874 3875 /* KSZ9477 can support HW offloading of only 1 HSR device */ 3876 if (dev->hsr_dev && hsr != dev->hsr_dev) { 3877 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR"); 3878 return -EOPNOTSUPP; 3879 } 3880 3881 /* KSZ9477 only supports HSR v0 and v1 */ 3882 if (!(ver == HSR_V0 || ver == HSR_V1)) { 3883 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported"); 3884 return -EOPNOTSUPP; 3885 } 3886 3887 /* Self MAC address filtering, to avoid frames traversing 3888 * the HSR ring more than once. 3889 */ 3890 ret = ksz_switch_macaddr_get(ds, port, extack); 3891 if (ret) 3892 return ret; 3893 3894 ksz9477_hsr_join(ds, port, hsr); 3895 dev->hsr_dev = hsr; 3896 dev->hsr_ports |= BIT(port); 3897 3898 return 0; 3899 } 3900 3901 static int ksz_hsr_leave(struct dsa_switch *ds, int port, 3902 struct net_device *hsr) 3903 { 3904 struct ksz_device *dev = ds->priv; 3905 3906 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID); 3907 3908 ksz9477_hsr_leave(ds, port, hsr); 3909 dev->hsr_ports &= ~BIT(port); 3910 if (!dev->hsr_ports) 3911 dev->hsr_dev = NULL; 3912 3913 ksz_switch_macaddr_put(ds); 3914 3915 return 0; 3916 } 3917 3918 static const struct dsa_switch_ops ksz_switch_ops = { 3919 .get_tag_protocol = ksz_get_tag_protocol, 3920 .connect_tag_protocol = ksz_connect_tag_protocol, 3921 .get_phy_flags = ksz_get_phy_flags, 3922 .setup = ksz_setup, 3923 .teardown = ksz_teardown, 3924 .phy_read = ksz_phy_read16, 3925 .phy_write = ksz_phy_write16, 3926 .phylink_get_caps = ksz_phylink_get_caps, 3927 .port_setup = ksz_port_setup, 3928 .set_ageing_time = ksz_set_ageing_time, 3929 .get_strings = ksz_get_strings, 3930 .get_ethtool_stats = ksz_get_ethtool_stats, 3931 .get_sset_count = ksz_sset_count, 3932 .port_bridge_join = ksz_port_bridge_join, 3933 .port_bridge_leave = ksz_port_bridge_leave, 3934 .port_hsr_join = ksz_hsr_join, 3935 .port_hsr_leave = ksz_hsr_leave, 3936 .port_set_mac_address = ksz_port_set_mac_address, 3937 .port_stp_state_set = ksz_port_stp_state_set, 3938 .port_teardown = ksz_port_teardown, 3939 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 3940 .port_bridge_flags = ksz_port_bridge_flags, 3941 .port_fast_age = ksz_port_fast_age, 3942 .port_vlan_filtering = ksz_port_vlan_filtering, 3943 .port_vlan_add = ksz_port_vlan_add, 3944 .port_vlan_del = ksz_port_vlan_del, 3945 .port_fdb_dump = ksz_port_fdb_dump, 3946 .port_fdb_add = ksz_port_fdb_add, 3947 .port_fdb_del = ksz_port_fdb_del, 3948 .port_mdb_add = ksz_port_mdb_add, 3949 .port_mdb_del = ksz_port_mdb_del, 3950 .port_mirror_add = ksz_port_mirror_add, 3951 .port_mirror_del = ksz_port_mirror_del, 3952 .get_stats64 = ksz_get_stats64, 3953 .get_pause_stats = ksz_get_pause_stats, 3954 .port_change_mtu = ksz_change_mtu, 3955 .port_max_mtu = ksz_max_mtu, 3956 .get_wol = ksz_get_wol, 3957 .set_wol = ksz_set_wol, 3958 .get_ts_info = ksz_get_ts_info, 3959 .port_hwtstamp_get = ksz_hwtstamp_get, 3960 .port_hwtstamp_set = ksz_hwtstamp_set, 3961 .port_txtstamp = ksz_port_txtstamp, 3962 .port_rxtstamp = ksz_port_rxtstamp, 3963 .cls_flower_add = ksz_cls_flower_add, 3964 .cls_flower_del = ksz_cls_flower_del, 3965 .port_setup_tc = ksz_setup_tc, 3966 .get_mac_eee = ksz_get_mac_eee, 3967 .set_mac_eee = ksz_set_mac_eee, 3968 }; 3969 3970 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 3971 { 3972 struct dsa_switch *ds; 3973 struct ksz_device *swdev; 3974 3975 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 3976 if (!ds) 3977 return NULL; 3978 3979 ds->dev = base; 3980 ds->num_ports = DSA_MAX_PORTS; 3981 ds->ops = &ksz_switch_ops; 3982 3983 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 3984 if (!swdev) 3985 return NULL; 3986 3987 ds->priv = swdev; 3988 swdev->dev = base; 3989 3990 swdev->ds = ds; 3991 swdev->priv = priv; 3992 3993 return swdev; 3994 } 3995 EXPORT_SYMBOL(ksz_switch_alloc); 3996 3997 /** 3998 * ksz_switch_shutdown - Shutdown routine for the switch device. 3999 * @dev: The switch device structure. 4000 * 4001 * This function is responsible for initiating a shutdown sequence for the 4002 * switch device. It invokes the reset operation defined in the device 4003 * operations, if available, to reset the switch. Subsequently, it calls the 4004 * DSA framework's shutdown function to ensure a proper shutdown of the DSA 4005 * switch. 4006 */ 4007 void ksz_switch_shutdown(struct ksz_device *dev) 4008 { 4009 bool wol_enabled = false; 4010 4011 if (dev->dev_ops->wol_pre_shutdown) 4012 dev->dev_ops->wol_pre_shutdown(dev, &wol_enabled); 4013 4014 if (dev->dev_ops->reset && !wol_enabled) 4015 dev->dev_ops->reset(dev); 4016 4017 dsa_switch_shutdown(dev->ds); 4018 } 4019 EXPORT_SYMBOL(ksz_switch_shutdown); 4020 4021 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 4022 struct device_node *port_dn) 4023 { 4024 phy_interface_t phy_mode = dev->ports[port_num].interface; 4025 int rx_delay = -1, tx_delay = -1; 4026 4027 if (!phy_interface_mode_is_rgmii(phy_mode)) 4028 return; 4029 4030 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 4031 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 4032 4033 if (rx_delay == -1 && tx_delay == -1) { 4034 dev_warn(dev->dev, 4035 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 4036 "please update device tree to specify \"rx-internal-delay-ps\" and " 4037 "\"tx-internal-delay-ps\"", 4038 port_num); 4039 4040 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 4041 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 4042 rx_delay = 2000; 4043 4044 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 4045 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 4046 tx_delay = 2000; 4047 } 4048 4049 if (rx_delay < 0) 4050 rx_delay = 0; 4051 if (tx_delay < 0) 4052 tx_delay = 0; 4053 4054 dev->ports[port_num].rgmii_rx_val = rx_delay; 4055 dev->ports[port_num].rgmii_tx_val = tx_delay; 4056 } 4057 4058 /** 4059 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding 4060 * register value. 4061 * @array: The array of drive strength values to search. 4062 * @array_size: The size of the array. 4063 * @microamp: The drive strength value in microamp to be converted. 4064 * 4065 * This function searches the array of drive strength values for the given 4066 * microamp value and returns the corresponding register value for that drive. 4067 * 4068 * Returns: If found, the corresponding register value for that drive strength 4069 * is returned. Otherwise, -EINVAL is returned indicating an invalid value. 4070 */ 4071 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array, 4072 size_t array_size, int microamp) 4073 { 4074 int i; 4075 4076 for (i = 0; i < array_size; i++) { 4077 if (array[i].microamp == microamp) 4078 return array[i].reg_val; 4079 } 4080 4081 return -EINVAL; 4082 } 4083 4084 /** 4085 * ksz_drive_strength_error() - Report invalid drive strength value 4086 * @dev: ksz device 4087 * @array: The array of drive strength values to search. 4088 * @array_size: The size of the array. 4089 * @microamp: Invalid drive strength value in microamp 4090 * 4091 * This function logs an error message when an unsupported drive strength value 4092 * is detected. It lists out all the supported drive strength values for 4093 * reference in the error message. 4094 */ 4095 static void ksz_drive_strength_error(struct ksz_device *dev, 4096 const struct ksz_drive_strength *array, 4097 size_t array_size, int microamp) 4098 { 4099 char supported_values[100]; 4100 size_t remaining_size; 4101 int added_len; 4102 char *ptr; 4103 int i; 4104 4105 remaining_size = sizeof(supported_values); 4106 ptr = supported_values; 4107 4108 for (i = 0; i < array_size; i++) { 4109 added_len = snprintf(ptr, remaining_size, 4110 i == 0 ? "%d" : ", %d", array[i].microamp); 4111 4112 if (added_len >= remaining_size) 4113 break; 4114 4115 ptr += added_len; 4116 remaining_size -= added_len; 4117 } 4118 4119 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n", 4120 microamp, supported_values); 4121 } 4122 4123 /** 4124 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477 4125 * chip variants. 4126 * @dev: ksz device 4127 * @props: Array of drive strength properties to be applied 4128 * @num_props: Number of properties in the array 4129 * 4130 * This function configures the drive strength for various KSZ9477 chip variants 4131 * based on the provided properties. It handles chip-specific nuances and 4132 * ensures only valid drive strengths are written to the respective chip. 4133 * 4134 * Return: 0 on successful configuration, a negative error code on failure. 4135 */ 4136 static int ksz9477_drive_strength_write(struct ksz_device *dev, 4137 struct ksz_driver_strength_prop *props, 4138 int num_props) 4139 { 4140 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths); 4141 int i, ret, reg; 4142 u8 mask = 0; 4143 u8 val = 0; 4144 4145 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1) 4146 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4147 props[KSZ_DRIVER_STRENGTH_IO].name); 4148 4149 if (dev->chip_id == KSZ8795_CHIP_ID || 4150 dev->chip_id == KSZ8794_CHIP_ID || 4151 dev->chip_id == KSZ8765_CHIP_ID) 4152 reg = KSZ8795_REG_SW_CTRL_20; 4153 else 4154 reg = KSZ9477_REG_SW_IO_STRENGTH; 4155 4156 for (i = 0; i < num_props; i++) { 4157 if (props[i].value == -1) 4158 continue; 4159 4160 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths, 4161 array_size, props[i].value); 4162 if (ret < 0) { 4163 ksz_drive_strength_error(dev, ksz9477_drive_strengths, 4164 array_size, props[i].value); 4165 return ret; 4166 } 4167 4168 mask |= SW_DRIVE_STRENGTH_M << props[i].offset; 4169 val |= ret << props[i].offset; 4170 } 4171 4172 return ksz_rmw8(dev, reg, mask, val); 4173 } 4174 4175 /** 4176 * ksz8830_drive_strength_write() - Set the drive strength configuration for 4177 * KSZ8830 compatible chip variants. 4178 * @dev: ksz device 4179 * @props: Array of drive strength properties to be set 4180 * @num_props: Number of properties in the array 4181 * 4182 * This function applies the specified drive strength settings to KSZ8830 chip 4183 * variants (KSZ8873, KSZ8863). 4184 * It ensures the configurations align with what the chip variant supports and 4185 * warns or errors out on unsupported settings. 4186 * 4187 * Return: 0 on success, error code otherwise 4188 */ 4189 static int ksz8830_drive_strength_write(struct ksz_device *dev, 4190 struct ksz_driver_strength_prop *props, 4191 int num_props) 4192 { 4193 size_t array_size = ARRAY_SIZE(ksz8830_drive_strengths); 4194 int microamp; 4195 int i, ret; 4196 4197 for (i = 0; i < num_props; i++) { 4198 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO) 4199 continue; 4200 4201 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4202 props[i].name); 4203 } 4204 4205 microamp = props[KSZ_DRIVER_STRENGTH_IO].value; 4206 ret = ksz_drive_strength_to_reg(ksz8830_drive_strengths, array_size, 4207 microamp); 4208 if (ret < 0) { 4209 ksz_drive_strength_error(dev, ksz8830_drive_strengths, 4210 array_size, microamp); 4211 return ret; 4212 } 4213 4214 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12, 4215 KSZ8873_DRIVE_STRENGTH_16MA, ret); 4216 } 4217 4218 /** 4219 * ksz_parse_drive_strength() - Extract and apply drive strength configurations 4220 * from device tree properties. 4221 * @dev: ksz device 4222 * 4223 * This function reads the specified drive strength properties from the 4224 * device tree, validates against the supported chip variants, and sets 4225 * them accordingly. An error should be critical here, as the drive strength 4226 * settings are crucial for EMI compliance. 4227 * 4228 * Return: 0 on success, error code otherwise 4229 */ 4230 static int ksz_parse_drive_strength(struct ksz_device *dev) 4231 { 4232 struct ksz_driver_strength_prop of_props[] = { 4233 [KSZ_DRIVER_STRENGTH_HI] = { 4234 .name = "microchip,hi-drive-strength-microamp", 4235 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S, 4236 .value = -1, 4237 }, 4238 [KSZ_DRIVER_STRENGTH_LO] = { 4239 .name = "microchip,lo-drive-strength-microamp", 4240 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S, 4241 .value = -1, 4242 }, 4243 [KSZ_DRIVER_STRENGTH_IO] = { 4244 .name = "microchip,io-drive-strength-microamp", 4245 .offset = 0, /* don't care */ 4246 .value = -1, 4247 }, 4248 }; 4249 struct device_node *np = dev->dev->of_node; 4250 bool have_any_prop = false; 4251 int i, ret; 4252 4253 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4254 ret = of_property_read_u32(np, of_props[i].name, 4255 &of_props[i].value); 4256 if (ret && ret != -EINVAL) 4257 dev_warn(dev->dev, "Failed to read %s\n", 4258 of_props[i].name); 4259 if (ret) 4260 continue; 4261 4262 have_any_prop = true; 4263 } 4264 4265 if (!have_any_prop) 4266 return 0; 4267 4268 switch (dev->chip_id) { 4269 case KSZ8830_CHIP_ID: 4270 return ksz8830_drive_strength_write(dev, of_props, 4271 ARRAY_SIZE(of_props)); 4272 case KSZ8795_CHIP_ID: 4273 case KSZ8794_CHIP_ID: 4274 case KSZ8765_CHIP_ID: 4275 case KSZ8563_CHIP_ID: 4276 case KSZ8567_CHIP_ID: 4277 case KSZ9477_CHIP_ID: 4278 case KSZ9563_CHIP_ID: 4279 case KSZ9567_CHIP_ID: 4280 case KSZ9893_CHIP_ID: 4281 case KSZ9896_CHIP_ID: 4282 case KSZ9897_CHIP_ID: 4283 return ksz9477_drive_strength_write(dev, of_props, 4284 ARRAY_SIZE(of_props)); 4285 default: 4286 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4287 if (of_props[i].value == -1) 4288 continue; 4289 4290 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4291 of_props[i].name); 4292 } 4293 } 4294 4295 return 0; 4296 } 4297 4298 int ksz_switch_register(struct ksz_device *dev) 4299 { 4300 const struct ksz_chip_data *info; 4301 struct device_node *port, *ports; 4302 phy_interface_t interface; 4303 unsigned int port_num; 4304 int ret; 4305 int i; 4306 4307 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 4308 GPIOD_OUT_LOW); 4309 if (IS_ERR(dev->reset_gpio)) 4310 return PTR_ERR(dev->reset_gpio); 4311 4312 if (dev->reset_gpio) { 4313 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4314 usleep_range(10000, 12000); 4315 gpiod_set_value_cansleep(dev->reset_gpio, 0); 4316 msleep(100); 4317 } 4318 4319 mutex_init(&dev->dev_mutex); 4320 mutex_init(&dev->regmap_mutex); 4321 mutex_init(&dev->alu_mutex); 4322 mutex_init(&dev->vlan_mutex); 4323 4324 ret = ksz_switch_detect(dev); 4325 if (ret) 4326 return ret; 4327 4328 info = ksz_lookup_info(dev->chip_id); 4329 if (!info) 4330 return -ENODEV; 4331 4332 /* Update the compatible info with the probed one */ 4333 dev->info = info; 4334 4335 dev_info(dev->dev, "found switch: %s, rev %i\n", 4336 dev->info->dev_name, dev->chip_rev); 4337 4338 ret = ksz_check_device_id(dev); 4339 if (ret) 4340 return ret; 4341 4342 dev->dev_ops = dev->info->ops; 4343 4344 ret = dev->dev_ops->init(dev); 4345 if (ret) 4346 return ret; 4347 4348 dev->ports = devm_kzalloc(dev->dev, 4349 dev->info->port_cnt * sizeof(struct ksz_port), 4350 GFP_KERNEL); 4351 if (!dev->ports) 4352 return -ENOMEM; 4353 4354 for (i = 0; i < dev->info->port_cnt; i++) { 4355 spin_lock_init(&dev->ports[i].mib.stats64_lock); 4356 mutex_init(&dev->ports[i].mib.cnt_mutex); 4357 dev->ports[i].mib.counters = 4358 devm_kzalloc(dev->dev, 4359 sizeof(u64) * (dev->info->mib_cnt + 1), 4360 GFP_KERNEL); 4361 if (!dev->ports[i].mib.counters) 4362 return -ENOMEM; 4363 4364 dev->ports[i].ksz_dev = dev; 4365 dev->ports[i].num = i; 4366 } 4367 4368 /* set the real number of ports */ 4369 dev->ds->num_ports = dev->info->port_cnt; 4370 4371 /* set the phylink ops */ 4372 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops; 4373 4374 /* Host port interface will be self detected, or specifically set in 4375 * device tree. 4376 */ 4377 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 4378 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 4379 if (dev->dev->of_node) { 4380 ret = of_get_phy_mode(dev->dev->of_node, &interface); 4381 if (ret == 0) 4382 dev->compat_interface = interface; 4383 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 4384 if (!ports) 4385 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 4386 if (ports) { 4387 for_each_available_child_of_node(ports, port) { 4388 if (of_property_read_u32(port, "reg", 4389 &port_num)) 4390 continue; 4391 if (!(dev->port_mask & BIT(port_num))) { 4392 of_node_put(port); 4393 of_node_put(ports); 4394 return -EINVAL; 4395 } 4396 of_get_phy_mode(port, 4397 &dev->ports[port_num].interface); 4398 4399 ksz_parse_rgmii_delay(dev, port_num, port); 4400 } 4401 of_node_put(ports); 4402 } 4403 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 4404 "microchip,synclko-125"); 4405 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 4406 "microchip,synclko-disable"); 4407 if (dev->synclko_125 && dev->synclko_disable) { 4408 dev_err(dev->dev, "inconsistent synclko settings\n"); 4409 return -EINVAL; 4410 } 4411 4412 dev->wakeup_source = of_property_read_bool(dev->dev->of_node, 4413 "wakeup-source"); 4414 } 4415 4416 ret = dsa_register_switch(dev->ds); 4417 if (ret) { 4418 dev->dev_ops->exit(dev); 4419 return ret; 4420 } 4421 4422 /* Read MIB counters every 30 seconds to avoid overflow. */ 4423 dev->mib_read_interval = msecs_to_jiffies(5000); 4424 4425 /* Start the MIB timer. */ 4426 schedule_delayed_work(&dev->mib_read, 0); 4427 4428 return ret; 4429 } 4430 EXPORT_SYMBOL(ksz_switch_register); 4431 4432 void ksz_switch_remove(struct ksz_device *dev) 4433 { 4434 /* timer started */ 4435 if (dev->mib_read_interval) { 4436 dev->mib_read_interval = 0; 4437 cancel_delayed_work_sync(&dev->mib_read); 4438 } 4439 4440 dev->dev_ops->exit(dev); 4441 dsa_unregister_switch(dev->ds); 4442 4443 if (dev->reset_gpio) 4444 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4445 4446 } 4447 EXPORT_SYMBOL(ksz_switch_remove); 4448 4449 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 4450 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 4451 MODULE_LICENSE("GPL"); 4452