1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/if_hsr.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/of.h> 23 #include <linux/of_mdio.h> 24 #include <linux/of_net.h> 25 #include <linux/micrel_phy.h> 26 #include <net/dsa.h> 27 #include <net/pkt_cls.h> 28 #include <net/switchdev.h> 29 30 #include "ksz_common.h" 31 #include "ksz_ptp.h" 32 #include "ksz8.h" 33 #include "ksz9477.h" 34 #include "lan937x.h" 35 36 #define MIB_COUNTER_NUM 0x20 37 38 struct ksz_stats_raw { 39 u64 rx_hi; 40 u64 rx_undersize; 41 u64 rx_fragments; 42 u64 rx_oversize; 43 u64 rx_jabbers; 44 u64 rx_symbol_err; 45 u64 rx_crc_err; 46 u64 rx_align_err; 47 u64 rx_mac_ctrl; 48 u64 rx_pause; 49 u64 rx_bcast; 50 u64 rx_mcast; 51 u64 rx_ucast; 52 u64 rx_64_or_less; 53 u64 rx_65_127; 54 u64 rx_128_255; 55 u64 rx_256_511; 56 u64 rx_512_1023; 57 u64 rx_1024_1522; 58 u64 rx_1523_2000; 59 u64 rx_2001; 60 u64 tx_hi; 61 u64 tx_late_col; 62 u64 tx_pause; 63 u64 tx_bcast; 64 u64 tx_mcast; 65 u64 tx_ucast; 66 u64 tx_deferred; 67 u64 tx_total_col; 68 u64 tx_exc_col; 69 u64 tx_single_col; 70 u64 tx_mult_col; 71 u64 rx_total; 72 u64 tx_total; 73 u64 rx_discards; 74 u64 tx_discards; 75 }; 76 77 struct ksz88xx_stats_raw { 78 u64 rx; 79 u64 rx_hi; 80 u64 rx_undersize; 81 u64 rx_fragments; 82 u64 rx_oversize; 83 u64 rx_jabbers; 84 u64 rx_symbol_err; 85 u64 rx_crc_err; 86 u64 rx_align_err; 87 u64 rx_mac_ctrl; 88 u64 rx_pause; 89 u64 rx_bcast; 90 u64 rx_mcast; 91 u64 rx_ucast; 92 u64 rx_64_or_less; 93 u64 rx_65_127; 94 u64 rx_128_255; 95 u64 rx_256_511; 96 u64 rx_512_1023; 97 u64 rx_1024_1522; 98 u64 tx; 99 u64 tx_hi; 100 u64 tx_late_col; 101 u64 tx_pause; 102 u64 tx_bcast; 103 u64 tx_mcast; 104 u64 tx_ucast; 105 u64 tx_deferred; 106 u64 tx_total_col; 107 u64 tx_exc_col; 108 u64 tx_single_col; 109 u64 tx_mult_col; 110 u64 rx_discards; 111 u64 tx_discards; 112 }; 113 114 static const struct ksz_mib_names ksz88xx_mib_names[] = { 115 { 0x00, "rx" }, 116 { 0x01, "rx_hi" }, 117 { 0x02, "rx_undersize" }, 118 { 0x03, "rx_fragments" }, 119 { 0x04, "rx_oversize" }, 120 { 0x05, "rx_jabbers" }, 121 { 0x06, "rx_symbol_err" }, 122 { 0x07, "rx_crc_err" }, 123 { 0x08, "rx_align_err" }, 124 { 0x09, "rx_mac_ctrl" }, 125 { 0x0a, "rx_pause" }, 126 { 0x0b, "rx_bcast" }, 127 { 0x0c, "rx_mcast" }, 128 { 0x0d, "rx_ucast" }, 129 { 0x0e, "rx_64_or_less" }, 130 { 0x0f, "rx_65_127" }, 131 { 0x10, "rx_128_255" }, 132 { 0x11, "rx_256_511" }, 133 { 0x12, "rx_512_1023" }, 134 { 0x13, "rx_1024_1522" }, 135 { 0x14, "tx" }, 136 { 0x15, "tx_hi" }, 137 { 0x16, "tx_late_col" }, 138 { 0x17, "tx_pause" }, 139 { 0x18, "tx_bcast" }, 140 { 0x19, "tx_mcast" }, 141 { 0x1a, "tx_ucast" }, 142 { 0x1b, "tx_deferred" }, 143 { 0x1c, "tx_total_col" }, 144 { 0x1d, "tx_exc_col" }, 145 { 0x1e, "tx_single_col" }, 146 { 0x1f, "tx_mult_col" }, 147 { 0x100, "rx_discards" }, 148 { 0x101, "tx_discards" }, 149 }; 150 151 static const struct ksz_mib_names ksz9477_mib_names[] = { 152 { 0x00, "rx_hi" }, 153 { 0x01, "rx_undersize" }, 154 { 0x02, "rx_fragments" }, 155 { 0x03, "rx_oversize" }, 156 { 0x04, "rx_jabbers" }, 157 { 0x05, "rx_symbol_err" }, 158 { 0x06, "rx_crc_err" }, 159 { 0x07, "rx_align_err" }, 160 { 0x08, "rx_mac_ctrl" }, 161 { 0x09, "rx_pause" }, 162 { 0x0A, "rx_bcast" }, 163 { 0x0B, "rx_mcast" }, 164 { 0x0C, "rx_ucast" }, 165 { 0x0D, "rx_64_or_less" }, 166 { 0x0E, "rx_65_127" }, 167 { 0x0F, "rx_128_255" }, 168 { 0x10, "rx_256_511" }, 169 { 0x11, "rx_512_1023" }, 170 { 0x12, "rx_1024_1522" }, 171 { 0x13, "rx_1523_2000" }, 172 { 0x14, "rx_2001" }, 173 { 0x15, "tx_hi" }, 174 { 0x16, "tx_late_col" }, 175 { 0x17, "tx_pause" }, 176 { 0x18, "tx_bcast" }, 177 { 0x19, "tx_mcast" }, 178 { 0x1A, "tx_ucast" }, 179 { 0x1B, "tx_deferred" }, 180 { 0x1C, "tx_total_col" }, 181 { 0x1D, "tx_exc_col" }, 182 { 0x1E, "tx_single_col" }, 183 { 0x1F, "tx_mult_col" }, 184 { 0x80, "rx_total" }, 185 { 0x81, "tx_total" }, 186 { 0x82, "rx_discards" }, 187 { 0x83, "tx_discards" }, 188 }; 189 190 struct ksz_driver_strength_prop { 191 const char *name; 192 int offset; 193 int value; 194 }; 195 196 enum ksz_driver_strength_type { 197 KSZ_DRIVER_STRENGTH_HI, 198 KSZ_DRIVER_STRENGTH_LO, 199 KSZ_DRIVER_STRENGTH_IO, 200 }; 201 202 /** 203 * struct ksz_drive_strength - drive strength mapping 204 * @reg_val: register value 205 * @microamp: microamp value 206 */ 207 struct ksz_drive_strength { 208 u32 reg_val; 209 u32 microamp; 210 }; 211 212 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants 213 * 214 * This values are not documented in KSZ9477 variants but confirmed by 215 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893 216 * and KSZ8563 are using same register (drive strength) settings like KSZ8795. 217 * 218 * Documentation in KSZ8795CLX provides more information with some 219 * recommendations: 220 * - for high speed signals 221 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using 222 * 2.5V or 3.3V VDDIO. 223 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with 224 * using 1.8V VDDIO. 225 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V 226 * or 3.3V VDDIO. 227 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO. 228 * 5. In same interface, the heavy loading should use higher one of the 229 * drive current strength. 230 * - for low speed signals 231 * 1. 3.3V VDDIO, use either 4 mA or 8 mA. 232 * 2. 2.5V VDDIO, use either 8 mA or 12 mA. 233 * 3. 1.8V VDDIO, use either 12 mA or 16 mA. 234 * 4. If it is heavy loading, can use higher drive current strength. 235 */ 236 static const struct ksz_drive_strength ksz9477_drive_strengths[] = { 237 { SW_DRIVE_STRENGTH_2MA, 2000 }, 238 { SW_DRIVE_STRENGTH_4MA, 4000 }, 239 { SW_DRIVE_STRENGTH_8MA, 8000 }, 240 { SW_DRIVE_STRENGTH_12MA, 12000 }, 241 { SW_DRIVE_STRENGTH_16MA, 16000 }, 242 { SW_DRIVE_STRENGTH_20MA, 20000 }, 243 { SW_DRIVE_STRENGTH_24MA, 24000 }, 244 { SW_DRIVE_STRENGTH_28MA, 28000 }, 245 }; 246 247 /* ksz8830_drive_strengths - Drive strength mapping for KSZ8830, KSZ8873, .. 248 * variants. 249 * This values are documented in KSZ8873 and KSZ8863 datasheets. 250 */ 251 static const struct ksz_drive_strength ksz8830_drive_strengths[] = { 252 { 0, 8000 }, 253 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 }, 254 }; 255 256 static const struct ksz_dev_ops ksz8_dev_ops = { 257 .setup = ksz8_setup, 258 .get_port_addr = ksz8_get_port_addr, 259 .cfg_port_member = ksz8_cfg_port_member, 260 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 261 .port_setup = ksz8_port_setup, 262 .r_phy = ksz8_r_phy, 263 .w_phy = ksz8_w_phy, 264 .r_mib_cnt = ksz8_r_mib_cnt, 265 .r_mib_pkt = ksz8_r_mib_pkt, 266 .r_mib_stat64 = ksz88xx_r_mib_stats64, 267 .freeze_mib = ksz8_freeze_mib, 268 .port_init_cnt = ksz8_port_init_cnt, 269 .fdb_dump = ksz8_fdb_dump, 270 .fdb_add = ksz8_fdb_add, 271 .fdb_del = ksz8_fdb_del, 272 .mdb_add = ksz8_mdb_add, 273 .mdb_del = ksz8_mdb_del, 274 .vlan_filtering = ksz8_port_vlan_filtering, 275 .vlan_add = ksz8_port_vlan_add, 276 .vlan_del = ksz8_port_vlan_del, 277 .mirror_add = ksz8_port_mirror_add, 278 .mirror_del = ksz8_port_mirror_del, 279 .get_caps = ksz8_get_caps, 280 .phylink_mac_link_up = ksz8_phylink_mac_link_up, 281 .config_cpu_port = ksz8_config_cpu_port, 282 .enable_stp_addr = ksz8_enable_stp_addr, 283 .reset = ksz8_reset_switch, 284 .init = ksz8_switch_init, 285 .exit = ksz8_switch_exit, 286 .change_mtu = ksz8_change_mtu, 287 }; 288 289 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 290 unsigned int mode, 291 phy_interface_t interface, 292 struct phy_device *phydev, int speed, 293 int duplex, bool tx_pause, 294 bool rx_pause); 295 296 static const struct ksz_dev_ops ksz9477_dev_ops = { 297 .setup = ksz9477_setup, 298 .get_port_addr = ksz9477_get_port_addr, 299 .cfg_port_member = ksz9477_cfg_port_member, 300 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 301 .port_setup = ksz9477_port_setup, 302 .set_ageing_time = ksz9477_set_ageing_time, 303 .r_phy = ksz9477_r_phy, 304 .w_phy = ksz9477_w_phy, 305 .r_mib_cnt = ksz9477_r_mib_cnt, 306 .r_mib_pkt = ksz9477_r_mib_pkt, 307 .r_mib_stat64 = ksz_r_mib_stats64, 308 .freeze_mib = ksz9477_freeze_mib, 309 .port_init_cnt = ksz9477_port_init_cnt, 310 .vlan_filtering = ksz9477_port_vlan_filtering, 311 .vlan_add = ksz9477_port_vlan_add, 312 .vlan_del = ksz9477_port_vlan_del, 313 .mirror_add = ksz9477_port_mirror_add, 314 .mirror_del = ksz9477_port_mirror_del, 315 .get_caps = ksz9477_get_caps, 316 .fdb_dump = ksz9477_fdb_dump, 317 .fdb_add = ksz9477_fdb_add, 318 .fdb_del = ksz9477_fdb_del, 319 .mdb_add = ksz9477_mdb_add, 320 .mdb_del = ksz9477_mdb_del, 321 .change_mtu = ksz9477_change_mtu, 322 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 323 .get_wol = ksz9477_get_wol, 324 .set_wol = ksz9477_set_wol, 325 .wol_pre_shutdown = ksz9477_wol_pre_shutdown, 326 .config_cpu_port = ksz9477_config_cpu_port, 327 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc, 328 .enable_stp_addr = ksz9477_enable_stp_addr, 329 .reset = ksz9477_reset_switch, 330 .init = ksz9477_switch_init, 331 .exit = ksz9477_switch_exit, 332 }; 333 334 static const struct ksz_dev_ops lan937x_dev_ops = { 335 .setup = lan937x_setup, 336 .teardown = lan937x_teardown, 337 .get_port_addr = ksz9477_get_port_addr, 338 .cfg_port_member = ksz9477_cfg_port_member, 339 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 340 .port_setup = lan937x_port_setup, 341 .set_ageing_time = lan937x_set_ageing_time, 342 .r_phy = lan937x_r_phy, 343 .w_phy = lan937x_w_phy, 344 .r_mib_cnt = ksz9477_r_mib_cnt, 345 .r_mib_pkt = ksz9477_r_mib_pkt, 346 .r_mib_stat64 = ksz_r_mib_stats64, 347 .freeze_mib = ksz9477_freeze_mib, 348 .port_init_cnt = ksz9477_port_init_cnt, 349 .vlan_filtering = ksz9477_port_vlan_filtering, 350 .vlan_add = ksz9477_port_vlan_add, 351 .vlan_del = ksz9477_port_vlan_del, 352 .mirror_add = ksz9477_port_mirror_add, 353 .mirror_del = ksz9477_port_mirror_del, 354 .get_caps = lan937x_phylink_get_caps, 355 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 356 .fdb_dump = ksz9477_fdb_dump, 357 .fdb_add = ksz9477_fdb_add, 358 .fdb_del = ksz9477_fdb_del, 359 .mdb_add = ksz9477_mdb_add, 360 .mdb_del = ksz9477_mdb_del, 361 .change_mtu = lan937x_change_mtu, 362 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 363 .config_cpu_port = lan937x_config_cpu_port, 364 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 365 .enable_stp_addr = ksz9477_enable_stp_addr, 366 .reset = lan937x_reset_switch, 367 .init = lan937x_switch_init, 368 .exit = lan937x_switch_exit, 369 }; 370 371 static const u16 ksz8795_regs[] = { 372 [REG_SW_MAC_ADDR] = 0x68, 373 [REG_IND_CTRL_0] = 0x6E, 374 [REG_IND_DATA_8] = 0x70, 375 [REG_IND_DATA_CHECK] = 0x72, 376 [REG_IND_DATA_HI] = 0x71, 377 [REG_IND_DATA_LO] = 0x75, 378 [REG_IND_MIB_CHECK] = 0x74, 379 [REG_IND_BYTE] = 0xA0, 380 [P_FORCE_CTRL] = 0x0C, 381 [P_LINK_STATUS] = 0x0E, 382 [P_LOCAL_CTRL] = 0x07, 383 [P_NEG_RESTART_CTRL] = 0x0D, 384 [P_REMOTE_STATUS] = 0x08, 385 [P_SPEED_STATUS] = 0x09, 386 [S_TAIL_TAG_CTRL] = 0x0C, 387 [P_STP_CTRL] = 0x02, 388 [S_START_CTRL] = 0x01, 389 [S_BROADCAST_CTRL] = 0x06, 390 [S_MULTICAST_CTRL] = 0x04, 391 [P_XMII_CTRL_0] = 0x06, 392 [P_XMII_CTRL_1] = 0x06, 393 }; 394 395 static const u32 ksz8795_masks[] = { 396 [PORT_802_1P_REMAPPING] = BIT(7), 397 [SW_TAIL_TAG_ENABLE] = BIT(1), 398 [MIB_COUNTER_OVERFLOW] = BIT(6), 399 [MIB_COUNTER_VALID] = BIT(5), 400 [VLAN_TABLE_FID] = GENMASK(6, 0), 401 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 402 [VLAN_TABLE_VALID] = BIT(12), 403 [STATIC_MAC_TABLE_VALID] = BIT(21), 404 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 405 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 406 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 407 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 408 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 409 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 410 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 411 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 412 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 413 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 414 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 415 [P_MII_TX_FLOW_CTRL] = BIT(5), 416 [P_MII_RX_FLOW_CTRL] = BIT(5), 417 }; 418 419 static const u8 ksz8795_xmii_ctrl0[] = { 420 [P_MII_100MBIT] = 0, 421 [P_MII_10MBIT] = 1, 422 [P_MII_FULL_DUPLEX] = 0, 423 [P_MII_HALF_DUPLEX] = 1, 424 }; 425 426 static const u8 ksz8795_xmii_ctrl1[] = { 427 [P_RGMII_SEL] = 3, 428 [P_GMII_SEL] = 2, 429 [P_RMII_SEL] = 1, 430 [P_MII_SEL] = 0, 431 [P_GMII_1GBIT] = 1, 432 [P_GMII_NOT_1GBIT] = 0, 433 }; 434 435 static const u8 ksz8795_shifts[] = { 436 [VLAN_TABLE_MEMBERSHIP_S] = 7, 437 [VLAN_TABLE] = 16, 438 [STATIC_MAC_FWD_PORTS] = 16, 439 [STATIC_MAC_FID] = 24, 440 [DYNAMIC_MAC_ENTRIES_H] = 3, 441 [DYNAMIC_MAC_ENTRIES] = 29, 442 [DYNAMIC_MAC_FID] = 16, 443 [DYNAMIC_MAC_TIMESTAMP] = 27, 444 [DYNAMIC_MAC_SRC_PORT] = 24, 445 }; 446 447 static const u16 ksz8863_regs[] = { 448 [REG_SW_MAC_ADDR] = 0x70, 449 [REG_IND_CTRL_0] = 0x79, 450 [REG_IND_DATA_8] = 0x7B, 451 [REG_IND_DATA_CHECK] = 0x7B, 452 [REG_IND_DATA_HI] = 0x7C, 453 [REG_IND_DATA_LO] = 0x80, 454 [REG_IND_MIB_CHECK] = 0x80, 455 [P_FORCE_CTRL] = 0x0C, 456 [P_LINK_STATUS] = 0x0E, 457 [P_LOCAL_CTRL] = 0x0C, 458 [P_NEG_RESTART_CTRL] = 0x0D, 459 [P_REMOTE_STATUS] = 0x0E, 460 [P_SPEED_STATUS] = 0x0F, 461 [S_TAIL_TAG_CTRL] = 0x03, 462 [P_STP_CTRL] = 0x02, 463 [S_START_CTRL] = 0x01, 464 [S_BROADCAST_CTRL] = 0x06, 465 [S_MULTICAST_CTRL] = 0x04, 466 }; 467 468 static const u32 ksz8863_masks[] = { 469 [PORT_802_1P_REMAPPING] = BIT(3), 470 [SW_TAIL_TAG_ENABLE] = BIT(6), 471 [MIB_COUNTER_OVERFLOW] = BIT(7), 472 [MIB_COUNTER_VALID] = BIT(6), 473 [VLAN_TABLE_FID] = GENMASK(15, 12), 474 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 475 [VLAN_TABLE_VALID] = BIT(19), 476 [STATIC_MAC_TABLE_VALID] = BIT(19), 477 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 478 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 479 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 480 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 481 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 482 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 483 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 484 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 485 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 486 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 487 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 488 }; 489 490 static u8 ksz8863_shifts[] = { 491 [VLAN_TABLE_MEMBERSHIP_S] = 16, 492 [STATIC_MAC_FWD_PORTS] = 16, 493 [STATIC_MAC_FID] = 22, 494 [DYNAMIC_MAC_ENTRIES_H] = 8, 495 [DYNAMIC_MAC_ENTRIES] = 24, 496 [DYNAMIC_MAC_FID] = 16, 497 [DYNAMIC_MAC_TIMESTAMP] = 22, 498 [DYNAMIC_MAC_SRC_PORT] = 20, 499 }; 500 501 static const u16 ksz9477_regs[] = { 502 [REG_SW_MAC_ADDR] = 0x0302, 503 [P_STP_CTRL] = 0x0B04, 504 [S_START_CTRL] = 0x0300, 505 [S_BROADCAST_CTRL] = 0x0332, 506 [S_MULTICAST_CTRL] = 0x0331, 507 [P_XMII_CTRL_0] = 0x0300, 508 [P_XMII_CTRL_1] = 0x0301, 509 }; 510 511 static const u32 ksz9477_masks[] = { 512 [ALU_STAT_WRITE] = 0, 513 [ALU_STAT_READ] = 1, 514 [P_MII_TX_FLOW_CTRL] = BIT(5), 515 [P_MII_RX_FLOW_CTRL] = BIT(3), 516 }; 517 518 static const u8 ksz9477_shifts[] = { 519 [ALU_STAT_INDEX] = 16, 520 }; 521 522 static const u8 ksz9477_xmii_ctrl0[] = { 523 [P_MII_100MBIT] = 1, 524 [P_MII_10MBIT] = 0, 525 [P_MII_FULL_DUPLEX] = 1, 526 [P_MII_HALF_DUPLEX] = 0, 527 }; 528 529 static const u8 ksz9477_xmii_ctrl1[] = { 530 [P_RGMII_SEL] = 0, 531 [P_RMII_SEL] = 1, 532 [P_GMII_SEL] = 2, 533 [P_MII_SEL] = 3, 534 [P_GMII_1GBIT] = 0, 535 [P_GMII_NOT_1GBIT] = 1, 536 }; 537 538 static const u32 lan937x_masks[] = { 539 [ALU_STAT_WRITE] = 1, 540 [ALU_STAT_READ] = 2, 541 [P_MII_TX_FLOW_CTRL] = BIT(5), 542 [P_MII_RX_FLOW_CTRL] = BIT(3), 543 }; 544 545 static const u8 lan937x_shifts[] = { 546 [ALU_STAT_INDEX] = 8, 547 }; 548 549 static const struct regmap_range ksz8563_valid_regs[] = { 550 regmap_reg_range(0x0000, 0x0003), 551 regmap_reg_range(0x0006, 0x0006), 552 regmap_reg_range(0x000f, 0x001f), 553 regmap_reg_range(0x0100, 0x0100), 554 regmap_reg_range(0x0104, 0x0107), 555 regmap_reg_range(0x010d, 0x010d), 556 regmap_reg_range(0x0110, 0x0113), 557 regmap_reg_range(0x0120, 0x012b), 558 regmap_reg_range(0x0201, 0x0201), 559 regmap_reg_range(0x0210, 0x0213), 560 regmap_reg_range(0x0300, 0x0300), 561 regmap_reg_range(0x0302, 0x031b), 562 regmap_reg_range(0x0320, 0x032b), 563 regmap_reg_range(0x0330, 0x0336), 564 regmap_reg_range(0x0338, 0x033e), 565 regmap_reg_range(0x0340, 0x035f), 566 regmap_reg_range(0x0370, 0x0370), 567 regmap_reg_range(0x0378, 0x0378), 568 regmap_reg_range(0x037c, 0x037d), 569 regmap_reg_range(0x0390, 0x0393), 570 regmap_reg_range(0x0400, 0x040e), 571 regmap_reg_range(0x0410, 0x042f), 572 regmap_reg_range(0x0500, 0x0519), 573 regmap_reg_range(0x0520, 0x054b), 574 regmap_reg_range(0x0550, 0x05b3), 575 576 /* port 1 */ 577 regmap_reg_range(0x1000, 0x1001), 578 regmap_reg_range(0x1004, 0x100b), 579 regmap_reg_range(0x1013, 0x1013), 580 regmap_reg_range(0x1017, 0x1017), 581 regmap_reg_range(0x101b, 0x101b), 582 regmap_reg_range(0x101f, 0x1021), 583 regmap_reg_range(0x1030, 0x1030), 584 regmap_reg_range(0x1100, 0x1111), 585 regmap_reg_range(0x111a, 0x111d), 586 regmap_reg_range(0x1122, 0x1127), 587 regmap_reg_range(0x112a, 0x112b), 588 regmap_reg_range(0x1136, 0x1139), 589 regmap_reg_range(0x113e, 0x113f), 590 regmap_reg_range(0x1400, 0x1401), 591 regmap_reg_range(0x1403, 0x1403), 592 regmap_reg_range(0x1410, 0x1417), 593 regmap_reg_range(0x1420, 0x1423), 594 regmap_reg_range(0x1500, 0x1507), 595 regmap_reg_range(0x1600, 0x1612), 596 regmap_reg_range(0x1800, 0x180f), 597 regmap_reg_range(0x1900, 0x1907), 598 regmap_reg_range(0x1914, 0x191b), 599 regmap_reg_range(0x1a00, 0x1a03), 600 regmap_reg_range(0x1a04, 0x1a08), 601 regmap_reg_range(0x1b00, 0x1b01), 602 regmap_reg_range(0x1b04, 0x1b04), 603 regmap_reg_range(0x1c00, 0x1c05), 604 regmap_reg_range(0x1c08, 0x1c1b), 605 606 /* port 2 */ 607 regmap_reg_range(0x2000, 0x2001), 608 regmap_reg_range(0x2004, 0x200b), 609 regmap_reg_range(0x2013, 0x2013), 610 regmap_reg_range(0x2017, 0x2017), 611 regmap_reg_range(0x201b, 0x201b), 612 regmap_reg_range(0x201f, 0x2021), 613 regmap_reg_range(0x2030, 0x2030), 614 regmap_reg_range(0x2100, 0x2111), 615 regmap_reg_range(0x211a, 0x211d), 616 regmap_reg_range(0x2122, 0x2127), 617 regmap_reg_range(0x212a, 0x212b), 618 regmap_reg_range(0x2136, 0x2139), 619 regmap_reg_range(0x213e, 0x213f), 620 regmap_reg_range(0x2400, 0x2401), 621 regmap_reg_range(0x2403, 0x2403), 622 regmap_reg_range(0x2410, 0x2417), 623 regmap_reg_range(0x2420, 0x2423), 624 regmap_reg_range(0x2500, 0x2507), 625 regmap_reg_range(0x2600, 0x2612), 626 regmap_reg_range(0x2800, 0x280f), 627 regmap_reg_range(0x2900, 0x2907), 628 regmap_reg_range(0x2914, 0x291b), 629 regmap_reg_range(0x2a00, 0x2a03), 630 regmap_reg_range(0x2a04, 0x2a08), 631 regmap_reg_range(0x2b00, 0x2b01), 632 regmap_reg_range(0x2b04, 0x2b04), 633 regmap_reg_range(0x2c00, 0x2c05), 634 regmap_reg_range(0x2c08, 0x2c1b), 635 636 /* port 3 */ 637 regmap_reg_range(0x3000, 0x3001), 638 regmap_reg_range(0x3004, 0x300b), 639 regmap_reg_range(0x3013, 0x3013), 640 regmap_reg_range(0x3017, 0x3017), 641 regmap_reg_range(0x301b, 0x301b), 642 regmap_reg_range(0x301f, 0x3021), 643 regmap_reg_range(0x3030, 0x3030), 644 regmap_reg_range(0x3300, 0x3301), 645 regmap_reg_range(0x3303, 0x3303), 646 regmap_reg_range(0x3400, 0x3401), 647 regmap_reg_range(0x3403, 0x3403), 648 regmap_reg_range(0x3410, 0x3417), 649 regmap_reg_range(0x3420, 0x3423), 650 regmap_reg_range(0x3500, 0x3507), 651 regmap_reg_range(0x3600, 0x3612), 652 regmap_reg_range(0x3800, 0x380f), 653 regmap_reg_range(0x3900, 0x3907), 654 regmap_reg_range(0x3914, 0x391b), 655 regmap_reg_range(0x3a00, 0x3a03), 656 regmap_reg_range(0x3a04, 0x3a08), 657 regmap_reg_range(0x3b00, 0x3b01), 658 regmap_reg_range(0x3b04, 0x3b04), 659 regmap_reg_range(0x3c00, 0x3c05), 660 regmap_reg_range(0x3c08, 0x3c1b), 661 }; 662 663 static const struct regmap_access_table ksz8563_register_set = { 664 .yes_ranges = ksz8563_valid_regs, 665 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 666 }; 667 668 static const struct regmap_range ksz9477_valid_regs[] = { 669 regmap_reg_range(0x0000, 0x0003), 670 regmap_reg_range(0x0006, 0x0006), 671 regmap_reg_range(0x0010, 0x001f), 672 regmap_reg_range(0x0100, 0x0100), 673 regmap_reg_range(0x0103, 0x0107), 674 regmap_reg_range(0x010d, 0x010d), 675 regmap_reg_range(0x0110, 0x0113), 676 regmap_reg_range(0x0120, 0x012b), 677 regmap_reg_range(0x0201, 0x0201), 678 regmap_reg_range(0x0210, 0x0213), 679 regmap_reg_range(0x0300, 0x0300), 680 regmap_reg_range(0x0302, 0x031b), 681 regmap_reg_range(0x0320, 0x032b), 682 regmap_reg_range(0x0330, 0x0336), 683 regmap_reg_range(0x0338, 0x033b), 684 regmap_reg_range(0x033e, 0x033e), 685 regmap_reg_range(0x0340, 0x035f), 686 regmap_reg_range(0x0370, 0x0370), 687 regmap_reg_range(0x0378, 0x0378), 688 regmap_reg_range(0x037c, 0x037d), 689 regmap_reg_range(0x0390, 0x0393), 690 regmap_reg_range(0x0400, 0x040e), 691 regmap_reg_range(0x0410, 0x042f), 692 regmap_reg_range(0x0444, 0x044b), 693 regmap_reg_range(0x0450, 0x046f), 694 regmap_reg_range(0x0500, 0x0519), 695 regmap_reg_range(0x0520, 0x054b), 696 regmap_reg_range(0x0550, 0x05b3), 697 regmap_reg_range(0x0604, 0x060b), 698 regmap_reg_range(0x0610, 0x0612), 699 regmap_reg_range(0x0614, 0x062c), 700 regmap_reg_range(0x0640, 0x0645), 701 regmap_reg_range(0x0648, 0x064d), 702 703 /* port 1 */ 704 regmap_reg_range(0x1000, 0x1001), 705 regmap_reg_range(0x1013, 0x1013), 706 regmap_reg_range(0x1017, 0x1017), 707 regmap_reg_range(0x101b, 0x101b), 708 regmap_reg_range(0x101f, 0x1020), 709 regmap_reg_range(0x1030, 0x1030), 710 regmap_reg_range(0x1100, 0x1115), 711 regmap_reg_range(0x111a, 0x111f), 712 regmap_reg_range(0x1120, 0x112b), 713 regmap_reg_range(0x1134, 0x113b), 714 regmap_reg_range(0x113c, 0x113f), 715 regmap_reg_range(0x1400, 0x1401), 716 regmap_reg_range(0x1403, 0x1403), 717 regmap_reg_range(0x1410, 0x1417), 718 regmap_reg_range(0x1420, 0x1423), 719 regmap_reg_range(0x1500, 0x1507), 720 regmap_reg_range(0x1600, 0x1613), 721 regmap_reg_range(0x1800, 0x180f), 722 regmap_reg_range(0x1820, 0x1827), 723 regmap_reg_range(0x1830, 0x1837), 724 regmap_reg_range(0x1840, 0x184b), 725 regmap_reg_range(0x1900, 0x1907), 726 regmap_reg_range(0x1914, 0x191b), 727 regmap_reg_range(0x1920, 0x1920), 728 regmap_reg_range(0x1923, 0x1927), 729 regmap_reg_range(0x1a00, 0x1a03), 730 regmap_reg_range(0x1a04, 0x1a07), 731 regmap_reg_range(0x1b00, 0x1b01), 732 regmap_reg_range(0x1b04, 0x1b04), 733 regmap_reg_range(0x1c00, 0x1c05), 734 regmap_reg_range(0x1c08, 0x1c1b), 735 736 /* port 2 */ 737 regmap_reg_range(0x2000, 0x2001), 738 regmap_reg_range(0x2013, 0x2013), 739 regmap_reg_range(0x2017, 0x2017), 740 regmap_reg_range(0x201b, 0x201b), 741 regmap_reg_range(0x201f, 0x2020), 742 regmap_reg_range(0x2030, 0x2030), 743 regmap_reg_range(0x2100, 0x2115), 744 regmap_reg_range(0x211a, 0x211f), 745 regmap_reg_range(0x2120, 0x212b), 746 regmap_reg_range(0x2134, 0x213b), 747 regmap_reg_range(0x213c, 0x213f), 748 regmap_reg_range(0x2400, 0x2401), 749 regmap_reg_range(0x2403, 0x2403), 750 regmap_reg_range(0x2410, 0x2417), 751 regmap_reg_range(0x2420, 0x2423), 752 regmap_reg_range(0x2500, 0x2507), 753 regmap_reg_range(0x2600, 0x2613), 754 regmap_reg_range(0x2800, 0x280f), 755 regmap_reg_range(0x2820, 0x2827), 756 regmap_reg_range(0x2830, 0x2837), 757 regmap_reg_range(0x2840, 0x284b), 758 regmap_reg_range(0x2900, 0x2907), 759 regmap_reg_range(0x2914, 0x291b), 760 regmap_reg_range(0x2920, 0x2920), 761 regmap_reg_range(0x2923, 0x2927), 762 regmap_reg_range(0x2a00, 0x2a03), 763 regmap_reg_range(0x2a04, 0x2a07), 764 regmap_reg_range(0x2b00, 0x2b01), 765 regmap_reg_range(0x2b04, 0x2b04), 766 regmap_reg_range(0x2c00, 0x2c05), 767 regmap_reg_range(0x2c08, 0x2c1b), 768 769 /* port 3 */ 770 regmap_reg_range(0x3000, 0x3001), 771 regmap_reg_range(0x3013, 0x3013), 772 regmap_reg_range(0x3017, 0x3017), 773 regmap_reg_range(0x301b, 0x301b), 774 regmap_reg_range(0x301f, 0x3020), 775 regmap_reg_range(0x3030, 0x3030), 776 regmap_reg_range(0x3100, 0x3115), 777 regmap_reg_range(0x311a, 0x311f), 778 regmap_reg_range(0x3120, 0x312b), 779 regmap_reg_range(0x3134, 0x313b), 780 regmap_reg_range(0x313c, 0x313f), 781 regmap_reg_range(0x3400, 0x3401), 782 regmap_reg_range(0x3403, 0x3403), 783 regmap_reg_range(0x3410, 0x3417), 784 regmap_reg_range(0x3420, 0x3423), 785 regmap_reg_range(0x3500, 0x3507), 786 regmap_reg_range(0x3600, 0x3613), 787 regmap_reg_range(0x3800, 0x380f), 788 regmap_reg_range(0x3820, 0x3827), 789 regmap_reg_range(0x3830, 0x3837), 790 regmap_reg_range(0x3840, 0x384b), 791 regmap_reg_range(0x3900, 0x3907), 792 regmap_reg_range(0x3914, 0x391b), 793 regmap_reg_range(0x3920, 0x3920), 794 regmap_reg_range(0x3923, 0x3927), 795 regmap_reg_range(0x3a00, 0x3a03), 796 regmap_reg_range(0x3a04, 0x3a07), 797 regmap_reg_range(0x3b00, 0x3b01), 798 regmap_reg_range(0x3b04, 0x3b04), 799 regmap_reg_range(0x3c00, 0x3c05), 800 regmap_reg_range(0x3c08, 0x3c1b), 801 802 /* port 4 */ 803 regmap_reg_range(0x4000, 0x4001), 804 regmap_reg_range(0x4013, 0x4013), 805 regmap_reg_range(0x4017, 0x4017), 806 regmap_reg_range(0x401b, 0x401b), 807 regmap_reg_range(0x401f, 0x4020), 808 regmap_reg_range(0x4030, 0x4030), 809 regmap_reg_range(0x4100, 0x4115), 810 regmap_reg_range(0x411a, 0x411f), 811 regmap_reg_range(0x4120, 0x412b), 812 regmap_reg_range(0x4134, 0x413b), 813 regmap_reg_range(0x413c, 0x413f), 814 regmap_reg_range(0x4400, 0x4401), 815 regmap_reg_range(0x4403, 0x4403), 816 regmap_reg_range(0x4410, 0x4417), 817 regmap_reg_range(0x4420, 0x4423), 818 regmap_reg_range(0x4500, 0x4507), 819 regmap_reg_range(0x4600, 0x4613), 820 regmap_reg_range(0x4800, 0x480f), 821 regmap_reg_range(0x4820, 0x4827), 822 regmap_reg_range(0x4830, 0x4837), 823 regmap_reg_range(0x4840, 0x484b), 824 regmap_reg_range(0x4900, 0x4907), 825 regmap_reg_range(0x4914, 0x491b), 826 regmap_reg_range(0x4920, 0x4920), 827 regmap_reg_range(0x4923, 0x4927), 828 regmap_reg_range(0x4a00, 0x4a03), 829 regmap_reg_range(0x4a04, 0x4a07), 830 regmap_reg_range(0x4b00, 0x4b01), 831 regmap_reg_range(0x4b04, 0x4b04), 832 regmap_reg_range(0x4c00, 0x4c05), 833 regmap_reg_range(0x4c08, 0x4c1b), 834 835 /* port 5 */ 836 regmap_reg_range(0x5000, 0x5001), 837 regmap_reg_range(0x5013, 0x5013), 838 regmap_reg_range(0x5017, 0x5017), 839 regmap_reg_range(0x501b, 0x501b), 840 regmap_reg_range(0x501f, 0x5020), 841 regmap_reg_range(0x5030, 0x5030), 842 regmap_reg_range(0x5100, 0x5115), 843 regmap_reg_range(0x511a, 0x511f), 844 regmap_reg_range(0x5120, 0x512b), 845 regmap_reg_range(0x5134, 0x513b), 846 regmap_reg_range(0x513c, 0x513f), 847 regmap_reg_range(0x5400, 0x5401), 848 regmap_reg_range(0x5403, 0x5403), 849 regmap_reg_range(0x5410, 0x5417), 850 regmap_reg_range(0x5420, 0x5423), 851 regmap_reg_range(0x5500, 0x5507), 852 regmap_reg_range(0x5600, 0x5613), 853 regmap_reg_range(0x5800, 0x580f), 854 regmap_reg_range(0x5820, 0x5827), 855 regmap_reg_range(0x5830, 0x5837), 856 regmap_reg_range(0x5840, 0x584b), 857 regmap_reg_range(0x5900, 0x5907), 858 regmap_reg_range(0x5914, 0x591b), 859 regmap_reg_range(0x5920, 0x5920), 860 regmap_reg_range(0x5923, 0x5927), 861 regmap_reg_range(0x5a00, 0x5a03), 862 regmap_reg_range(0x5a04, 0x5a07), 863 regmap_reg_range(0x5b00, 0x5b01), 864 regmap_reg_range(0x5b04, 0x5b04), 865 regmap_reg_range(0x5c00, 0x5c05), 866 regmap_reg_range(0x5c08, 0x5c1b), 867 868 /* port 6 */ 869 regmap_reg_range(0x6000, 0x6001), 870 regmap_reg_range(0x6013, 0x6013), 871 regmap_reg_range(0x6017, 0x6017), 872 regmap_reg_range(0x601b, 0x601b), 873 regmap_reg_range(0x601f, 0x6020), 874 regmap_reg_range(0x6030, 0x6030), 875 regmap_reg_range(0x6300, 0x6301), 876 regmap_reg_range(0x6400, 0x6401), 877 regmap_reg_range(0x6403, 0x6403), 878 regmap_reg_range(0x6410, 0x6417), 879 regmap_reg_range(0x6420, 0x6423), 880 regmap_reg_range(0x6500, 0x6507), 881 regmap_reg_range(0x6600, 0x6613), 882 regmap_reg_range(0x6800, 0x680f), 883 regmap_reg_range(0x6820, 0x6827), 884 regmap_reg_range(0x6830, 0x6837), 885 regmap_reg_range(0x6840, 0x684b), 886 regmap_reg_range(0x6900, 0x6907), 887 regmap_reg_range(0x6914, 0x691b), 888 regmap_reg_range(0x6920, 0x6920), 889 regmap_reg_range(0x6923, 0x6927), 890 regmap_reg_range(0x6a00, 0x6a03), 891 regmap_reg_range(0x6a04, 0x6a07), 892 regmap_reg_range(0x6b00, 0x6b01), 893 regmap_reg_range(0x6b04, 0x6b04), 894 regmap_reg_range(0x6c00, 0x6c05), 895 regmap_reg_range(0x6c08, 0x6c1b), 896 897 /* port 7 */ 898 regmap_reg_range(0x7000, 0x7001), 899 regmap_reg_range(0x7013, 0x7013), 900 regmap_reg_range(0x7017, 0x7017), 901 regmap_reg_range(0x701b, 0x701b), 902 regmap_reg_range(0x701f, 0x7020), 903 regmap_reg_range(0x7030, 0x7030), 904 regmap_reg_range(0x7200, 0x7203), 905 regmap_reg_range(0x7206, 0x7207), 906 regmap_reg_range(0x7300, 0x7301), 907 regmap_reg_range(0x7400, 0x7401), 908 regmap_reg_range(0x7403, 0x7403), 909 regmap_reg_range(0x7410, 0x7417), 910 regmap_reg_range(0x7420, 0x7423), 911 regmap_reg_range(0x7500, 0x7507), 912 regmap_reg_range(0x7600, 0x7613), 913 regmap_reg_range(0x7800, 0x780f), 914 regmap_reg_range(0x7820, 0x7827), 915 regmap_reg_range(0x7830, 0x7837), 916 regmap_reg_range(0x7840, 0x784b), 917 regmap_reg_range(0x7900, 0x7907), 918 regmap_reg_range(0x7914, 0x791b), 919 regmap_reg_range(0x7920, 0x7920), 920 regmap_reg_range(0x7923, 0x7927), 921 regmap_reg_range(0x7a00, 0x7a03), 922 regmap_reg_range(0x7a04, 0x7a07), 923 regmap_reg_range(0x7b00, 0x7b01), 924 regmap_reg_range(0x7b04, 0x7b04), 925 regmap_reg_range(0x7c00, 0x7c05), 926 regmap_reg_range(0x7c08, 0x7c1b), 927 }; 928 929 static const struct regmap_access_table ksz9477_register_set = { 930 .yes_ranges = ksz9477_valid_regs, 931 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 932 }; 933 934 static const struct regmap_range ksz9896_valid_regs[] = { 935 regmap_reg_range(0x0000, 0x0003), 936 regmap_reg_range(0x0006, 0x0006), 937 regmap_reg_range(0x0010, 0x001f), 938 regmap_reg_range(0x0100, 0x0100), 939 regmap_reg_range(0x0103, 0x0107), 940 regmap_reg_range(0x010d, 0x010d), 941 regmap_reg_range(0x0110, 0x0113), 942 regmap_reg_range(0x0120, 0x0127), 943 regmap_reg_range(0x0201, 0x0201), 944 regmap_reg_range(0x0210, 0x0213), 945 regmap_reg_range(0x0300, 0x0300), 946 regmap_reg_range(0x0302, 0x030b), 947 regmap_reg_range(0x0310, 0x031b), 948 regmap_reg_range(0x0320, 0x032b), 949 regmap_reg_range(0x0330, 0x0336), 950 regmap_reg_range(0x0338, 0x033b), 951 regmap_reg_range(0x033e, 0x033e), 952 regmap_reg_range(0x0340, 0x035f), 953 regmap_reg_range(0x0370, 0x0370), 954 regmap_reg_range(0x0378, 0x0378), 955 regmap_reg_range(0x037c, 0x037d), 956 regmap_reg_range(0x0390, 0x0393), 957 regmap_reg_range(0x0400, 0x040e), 958 regmap_reg_range(0x0410, 0x042f), 959 960 /* port 1 */ 961 regmap_reg_range(0x1000, 0x1001), 962 regmap_reg_range(0x1013, 0x1013), 963 regmap_reg_range(0x1017, 0x1017), 964 regmap_reg_range(0x101b, 0x101b), 965 regmap_reg_range(0x101f, 0x1020), 966 regmap_reg_range(0x1030, 0x1030), 967 regmap_reg_range(0x1100, 0x1115), 968 regmap_reg_range(0x111a, 0x111f), 969 regmap_reg_range(0x1122, 0x1127), 970 regmap_reg_range(0x112a, 0x112b), 971 regmap_reg_range(0x1136, 0x1139), 972 regmap_reg_range(0x113e, 0x113f), 973 regmap_reg_range(0x1400, 0x1401), 974 regmap_reg_range(0x1403, 0x1403), 975 regmap_reg_range(0x1410, 0x1417), 976 regmap_reg_range(0x1420, 0x1423), 977 regmap_reg_range(0x1500, 0x1507), 978 regmap_reg_range(0x1600, 0x1612), 979 regmap_reg_range(0x1800, 0x180f), 980 regmap_reg_range(0x1820, 0x1827), 981 regmap_reg_range(0x1830, 0x1837), 982 regmap_reg_range(0x1840, 0x184b), 983 regmap_reg_range(0x1900, 0x1907), 984 regmap_reg_range(0x1914, 0x1915), 985 regmap_reg_range(0x1a00, 0x1a03), 986 regmap_reg_range(0x1a04, 0x1a07), 987 regmap_reg_range(0x1b00, 0x1b01), 988 regmap_reg_range(0x1b04, 0x1b04), 989 990 /* port 2 */ 991 regmap_reg_range(0x2000, 0x2001), 992 regmap_reg_range(0x2013, 0x2013), 993 regmap_reg_range(0x2017, 0x2017), 994 regmap_reg_range(0x201b, 0x201b), 995 regmap_reg_range(0x201f, 0x2020), 996 regmap_reg_range(0x2030, 0x2030), 997 regmap_reg_range(0x2100, 0x2115), 998 regmap_reg_range(0x211a, 0x211f), 999 regmap_reg_range(0x2122, 0x2127), 1000 regmap_reg_range(0x212a, 0x212b), 1001 regmap_reg_range(0x2136, 0x2139), 1002 regmap_reg_range(0x213e, 0x213f), 1003 regmap_reg_range(0x2400, 0x2401), 1004 regmap_reg_range(0x2403, 0x2403), 1005 regmap_reg_range(0x2410, 0x2417), 1006 regmap_reg_range(0x2420, 0x2423), 1007 regmap_reg_range(0x2500, 0x2507), 1008 regmap_reg_range(0x2600, 0x2612), 1009 regmap_reg_range(0x2800, 0x280f), 1010 regmap_reg_range(0x2820, 0x2827), 1011 regmap_reg_range(0x2830, 0x2837), 1012 regmap_reg_range(0x2840, 0x284b), 1013 regmap_reg_range(0x2900, 0x2907), 1014 regmap_reg_range(0x2914, 0x2915), 1015 regmap_reg_range(0x2a00, 0x2a03), 1016 regmap_reg_range(0x2a04, 0x2a07), 1017 regmap_reg_range(0x2b00, 0x2b01), 1018 regmap_reg_range(0x2b04, 0x2b04), 1019 1020 /* port 3 */ 1021 regmap_reg_range(0x3000, 0x3001), 1022 regmap_reg_range(0x3013, 0x3013), 1023 regmap_reg_range(0x3017, 0x3017), 1024 regmap_reg_range(0x301b, 0x301b), 1025 regmap_reg_range(0x301f, 0x3020), 1026 regmap_reg_range(0x3030, 0x3030), 1027 regmap_reg_range(0x3100, 0x3115), 1028 regmap_reg_range(0x311a, 0x311f), 1029 regmap_reg_range(0x3122, 0x3127), 1030 regmap_reg_range(0x312a, 0x312b), 1031 regmap_reg_range(0x3136, 0x3139), 1032 regmap_reg_range(0x313e, 0x313f), 1033 regmap_reg_range(0x3400, 0x3401), 1034 regmap_reg_range(0x3403, 0x3403), 1035 regmap_reg_range(0x3410, 0x3417), 1036 regmap_reg_range(0x3420, 0x3423), 1037 regmap_reg_range(0x3500, 0x3507), 1038 regmap_reg_range(0x3600, 0x3612), 1039 regmap_reg_range(0x3800, 0x380f), 1040 regmap_reg_range(0x3820, 0x3827), 1041 regmap_reg_range(0x3830, 0x3837), 1042 regmap_reg_range(0x3840, 0x384b), 1043 regmap_reg_range(0x3900, 0x3907), 1044 regmap_reg_range(0x3914, 0x3915), 1045 regmap_reg_range(0x3a00, 0x3a03), 1046 regmap_reg_range(0x3a04, 0x3a07), 1047 regmap_reg_range(0x3b00, 0x3b01), 1048 regmap_reg_range(0x3b04, 0x3b04), 1049 1050 /* port 4 */ 1051 regmap_reg_range(0x4000, 0x4001), 1052 regmap_reg_range(0x4013, 0x4013), 1053 regmap_reg_range(0x4017, 0x4017), 1054 regmap_reg_range(0x401b, 0x401b), 1055 regmap_reg_range(0x401f, 0x4020), 1056 regmap_reg_range(0x4030, 0x4030), 1057 regmap_reg_range(0x4100, 0x4115), 1058 regmap_reg_range(0x411a, 0x411f), 1059 regmap_reg_range(0x4122, 0x4127), 1060 regmap_reg_range(0x412a, 0x412b), 1061 regmap_reg_range(0x4136, 0x4139), 1062 regmap_reg_range(0x413e, 0x413f), 1063 regmap_reg_range(0x4400, 0x4401), 1064 regmap_reg_range(0x4403, 0x4403), 1065 regmap_reg_range(0x4410, 0x4417), 1066 regmap_reg_range(0x4420, 0x4423), 1067 regmap_reg_range(0x4500, 0x4507), 1068 regmap_reg_range(0x4600, 0x4612), 1069 regmap_reg_range(0x4800, 0x480f), 1070 regmap_reg_range(0x4820, 0x4827), 1071 regmap_reg_range(0x4830, 0x4837), 1072 regmap_reg_range(0x4840, 0x484b), 1073 regmap_reg_range(0x4900, 0x4907), 1074 regmap_reg_range(0x4914, 0x4915), 1075 regmap_reg_range(0x4a00, 0x4a03), 1076 regmap_reg_range(0x4a04, 0x4a07), 1077 regmap_reg_range(0x4b00, 0x4b01), 1078 regmap_reg_range(0x4b04, 0x4b04), 1079 1080 /* port 5 */ 1081 regmap_reg_range(0x5000, 0x5001), 1082 regmap_reg_range(0x5013, 0x5013), 1083 regmap_reg_range(0x5017, 0x5017), 1084 regmap_reg_range(0x501b, 0x501b), 1085 regmap_reg_range(0x501f, 0x5020), 1086 regmap_reg_range(0x5030, 0x5030), 1087 regmap_reg_range(0x5100, 0x5115), 1088 regmap_reg_range(0x511a, 0x511f), 1089 regmap_reg_range(0x5122, 0x5127), 1090 regmap_reg_range(0x512a, 0x512b), 1091 regmap_reg_range(0x5136, 0x5139), 1092 regmap_reg_range(0x513e, 0x513f), 1093 regmap_reg_range(0x5400, 0x5401), 1094 regmap_reg_range(0x5403, 0x5403), 1095 regmap_reg_range(0x5410, 0x5417), 1096 regmap_reg_range(0x5420, 0x5423), 1097 regmap_reg_range(0x5500, 0x5507), 1098 regmap_reg_range(0x5600, 0x5612), 1099 regmap_reg_range(0x5800, 0x580f), 1100 regmap_reg_range(0x5820, 0x5827), 1101 regmap_reg_range(0x5830, 0x5837), 1102 regmap_reg_range(0x5840, 0x584b), 1103 regmap_reg_range(0x5900, 0x5907), 1104 regmap_reg_range(0x5914, 0x5915), 1105 regmap_reg_range(0x5a00, 0x5a03), 1106 regmap_reg_range(0x5a04, 0x5a07), 1107 regmap_reg_range(0x5b00, 0x5b01), 1108 regmap_reg_range(0x5b04, 0x5b04), 1109 1110 /* port 6 */ 1111 regmap_reg_range(0x6000, 0x6001), 1112 regmap_reg_range(0x6013, 0x6013), 1113 regmap_reg_range(0x6017, 0x6017), 1114 regmap_reg_range(0x601b, 0x601b), 1115 regmap_reg_range(0x601f, 0x6020), 1116 regmap_reg_range(0x6030, 0x6030), 1117 regmap_reg_range(0x6100, 0x6115), 1118 regmap_reg_range(0x611a, 0x611f), 1119 regmap_reg_range(0x6122, 0x6127), 1120 regmap_reg_range(0x612a, 0x612b), 1121 regmap_reg_range(0x6136, 0x6139), 1122 regmap_reg_range(0x613e, 0x613f), 1123 regmap_reg_range(0x6300, 0x6301), 1124 regmap_reg_range(0x6400, 0x6401), 1125 regmap_reg_range(0x6403, 0x6403), 1126 regmap_reg_range(0x6410, 0x6417), 1127 regmap_reg_range(0x6420, 0x6423), 1128 regmap_reg_range(0x6500, 0x6507), 1129 regmap_reg_range(0x6600, 0x6612), 1130 regmap_reg_range(0x6800, 0x680f), 1131 regmap_reg_range(0x6820, 0x6827), 1132 regmap_reg_range(0x6830, 0x6837), 1133 regmap_reg_range(0x6840, 0x684b), 1134 regmap_reg_range(0x6900, 0x6907), 1135 regmap_reg_range(0x6914, 0x6915), 1136 regmap_reg_range(0x6a00, 0x6a03), 1137 regmap_reg_range(0x6a04, 0x6a07), 1138 regmap_reg_range(0x6b00, 0x6b01), 1139 regmap_reg_range(0x6b04, 0x6b04), 1140 }; 1141 1142 static const struct regmap_access_table ksz9896_register_set = { 1143 .yes_ranges = ksz9896_valid_regs, 1144 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1145 }; 1146 1147 static const struct regmap_range ksz8873_valid_regs[] = { 1148 regmap_reg_range(0x00, 0x01), 1149 /* global control register */ 1150 regmap_reg_range(0x02, 0x0f), 1151 1152 /* port registers */ 1153 regmap_reg_range(0x10, 0x1d), 1154 regmap_reg_range(0x1e, 0x1f), 1155 regmap_reg_range(0x20, 0x2d), 1156 regmap_reg_range(0x2e, 0x2f), 1157 regmap_reg_range(0x30, 0x39), 1158 regmap_reg_range(0x3f, 0x3f), 1159 1160 /* advanced control registers */ 1161 regmap_reg_range(0x60, 0x6f), 1162 regmap_reg_range(0x70, 0x75), 1163 regmap_reg_range(0x76, 0x78), 1164 regmap_reg_range(0x79, 0x7a), 1165 regmap_reg_range(0x7b, 0x83), 1166 regmap_reg_range(0x8e, 0x99), 1167 regmap_reg_range(0x9a, 0xa5), 1168 regmap_reg_range(0xa6, 0xa6), 1169 regmap_reg_range(0xa7, 0xaa), 1170 regmap_reg_range(0xab, 0xae), 1171 regmap_reg_range(0xaf, 0xba), 1172 regmap_reg_range(0xbb, 0xbc), 1173 regmap_reg_range(0xbd, 0xbd), 1174 regmap_reg_range(0xc0, 0xc0), 1175 regmap_reg_range(0xc2, 0xc2), 1176 regmap_reg_range(0xc3, 0xc3), 1177 regmap_reg_range(0xc4, 0xc4), 1178 regmap_reg_range(0xc6, 0xc6), 1179 }; 1180 1181 static const struct regmap_access_table ksz8873_register_set = { 1182 .yes_ranges = ksz8873_valid_regs, 1183 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), 1184 }; 1185 1186 const struct ksz_chip_data ksz_switch_chips[] = { 1187 [KSZ8563] = { 1188 .chip_id = KSZ8563_CHIP_ID, 1189 .dev_name = "KSZ8563", 1190 .num_vlans = 4096, 1191 .num_alus = 4096, 1192 .num_statics = 16, 1193 .cpu_ports = 0x07, /* can be configured as cpu port */ 1194 .port_cnt = 3, /* total port count */ 1195 .port_nirqs = 3, 1196 .num_tx_queues = 4, 1197 .tc_cbs_supported = true, 1198 .tc_ets_supported = true, 1199 .ops = &ksz9477_dev_ops, 1200 .mib_names = ksz9477_mib_names, 1201 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1202 .reg_mib_cnt = MIB_COUNTER_NUM, 1203 .regs = ksz9477_regs, 1204 .masks = ksz9477_masks, 1205 .shifts = ksz9477_shifts, 1206 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1207 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1208 .supports_mii = {false, false, true}, 1209 .supports_rmii = {false, false, true}, 1210 .supports_rgmii = {false, false, true}, 1211 .internal_phy = {true, true, false}, 1212 .gbit_capable = {false, false, true}, 1213 .wr_table = &ksz8563_register_set, 1214 .rd_table = &ksz8563_register_set, 1215 }, 1216 1217 [KSZ8795] = { 1218 .chip_id = KSZ8795_CHIP_ID, 1219 .dev_name = "KSZ8795", 1220 .num_vlans = 4096, 1221 .num_alus = 0, 1222 .num_statics = 8, 1223 .cpu_ports = 0x10, /* can be configured as cpu port */ 1224 .port_cnt = 5, /* total cpu and user ports */ 1225 .num_tx_queues = 4, 1226 .ops = &ksz8_dev_ops, 1227 .ksz87xx_eee_link_erratum = true, 1228 .mib_names = ksz9477_mib_names, 1229 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1230 .reg_mib_cnt = MIB_COUNTER_NUM, 1231 .regs = ksz8795_regs, 1232 .masks = ksz8795_masks, 1233 .shifts = ksz8795_shifts, 1234 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1235 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1236 .supports_mii = {false, false, false, false, true}, 1237 .supports_rmii = {false, false, false, false, true}, 1238 .supports_rgmii = {false, false, false, false, true}, 1239 .internal_phy = {true, true, true, true, false}, 1240 }, 1241 1242 [KSZ8794] = { 1243 /* WARNING 1244 * ======= 1245 * KSZ8794 is similar to KSZ8795, except the port map 1246 * contains a gap between external and CPU ports, the 1247 * port map is NOT continuous. The per-port register 1248 * map is shifted accordingly too, i.e. registers at 1249 * offset 0x40 are NOT used on KSZ8794 and they ARE 1250 * used on KSZ8795 for external port 3. 1251 * external cpu 1252 * KSZ8794 0,1,2 4 1253 * KSZ8795 0,1,2,3 4 1254 * KSZ8765 0,1,2,3 4 1255 * port_cnt is configured as 5, even though it is 4 1256 */ 1257 .chip_id = KSZ8794_CHIP_ID, 1258 .dev_name = "KSZ8794", 1259 .num_vlans = 4096, 1260 .num_alus = 0, 1261 .num_statics = 8, 1262 .cpu_ports = 0x10, /* can be configured as cpu port */ 1263 .port_cnt = 5, /* total cpu and user ports */ 1264 .num_tx_queues = 4, 1265 .ops = &ksz8_dev_ops, 1266 .ksz87xx_eee_link_erratum = true, 1267 .mib_names = ksz9477_mib_names, 1268 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1269 .reg_mib_cnt = MIB_COUNTER_NUM, 1270 .regs = ksz8795_regs, 1271 .masks = ksz8795_masks, 1272 .shifts = ksz8795_shifts, 1273 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1274 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1275 .supports_mii = {false, false, false, false, true}, 1276 .supports_rmii = {false, false, false, false, true}, 1277 .supports_rgmii = {false, false, false, false, true}, 1278 .internal_phy = {true, true, true, false, false}, 1279 }, 1280 1281 [KSZ8765] = { 1282 .chip_id = KSZ8765_CHIP_ID, 1283 .dev_name = "KSZ8765", 1284 .num_vlans = 4096, 1285 .num_alus = 0, 1286 .num_statics = 8, 1287 .cpu_ports = 0x10, /* can be configured as cpu port */ 1288 .port_cnt = 5, /* total cpu and user ports */ 1289 .num_tx_queues = 4, 1290 .ops = &ksz8_dev_ops, 1291 .ksz87xx_eee_link_erratum = true, 1292 .mib_names = ksz9477_mib_names, 1293 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1294 .reg_mib_cnt = MIB_COUNTER_NUM, 1295 .regs = ksz8795_regs, 1296 .masks = ksz8795_masks, 1297 .shifts = ksz8795_shifts, 1298 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1299 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1300 .supports_mii = {false, false, false, false, true}, 1301 .supports_rmii = {false, false, false, false, true}, 1302 .supports_rgmii = {false, false, false, false, true}, 1303 .internal_phy = {true, true, true, true, false}, 1304 }, 1305 1306 [KSZ8830] = { 1307 .chip_id = KSZ8830_CHIP_ID, 1308 .dev_name = "KSZ8863/KSZ8873", 1309 .num_vlans = 16, 1310 .num_alus = 0, 1311 .num_statics = 8, 1312 .cpu_ports = 0x4, /* can be configured as cpu port */ 1313 .port_cnt = 3, 1314 .num_tx_queues = 4, 1315 .ops = &ksz8_dev_ops, 1316 .mib_names = ksz88xx_mib_names, 1317 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1318 .reg_mib_cnt = MIB_COUNTER_NUM, 1319 .regs = ksz8863_regs, 1320 .masks = ksz8863_masks, 1321 .shifts = ksz8863_shifts, 1322 .supports_mii = {false, false, true}, 1323 .supports_rmii = {false, false, true}, 1324 .internal_phy = {true, true, false}, 1325 .wr_table = &ksz8873_register_set, 1326 .rd_table = &ksz8873_register_set, 1327 }, 1328 1329 [KSZ9477] = { 1330 .chip_id = KSZ9477_CHIP_ID, 1331 .dev_name = "KSZ9477", 1332 .num_vlans = 4096, 1333 .num_alus = 4096, 1334 .num_statics = 16, 1335 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1336 .port_cnt = 7, /* total physical port count */ 1337 .port_nirqs = 4, 1338 .num_tx_queues = 4, 1339 .tc_cbs_supported = true, 1340 .tc_ets_supported = true, 1341 .ops = &ksz9477_dev_ops, 1342 .mib_names = ksz9477_mib_names, 1343 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1344 .reg_mib_cnt = MIB_COUNTER_NUM, 1345 .regs = ksz9477_regs, 1346 .masks = ksz9477_masks, 1347 .shifts = ksz9477_shifts, 1348 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1349 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1350 .supports_mii = {false, false, false, false, 1351 false, true, false}, 1352 .supports_rmii = {false, false, false, false, 1353 false, true, false}, 1354 .supports_rgmii = {false, false, false, false, 1355 false, true, false}, 1356 .internal_phy = {true, true, true, true, 1357 true, false, false}, 1358 .gbit_capable = {true, true, true, true, true, true, true}, 1359 .wr_table = &ksz9477_register_set, 1360 .rd_table = &ksz9477_register_set, 1361 }, 1362 1363 [KSZ9896] = { 1364 .chip_id = KSZ9896_CHIP_ID, 1365 .dev_name = "KSZ9896", 1366 .num_vlans = 4096, 1367 .num_alus = 4096, 1368 .num_statics = 16, 1369 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1370 .port_cnt = 6, /* total physical port count */ 1371 .port_nirqs = 2, 1372 .num_tx_queues = 4, 1373 .ops = &ksz9477_dev_ops, 1374 .mib_names = ksz9477_mib_names, 1375 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1376 .reg_mib_cnt = MIB_COUNTER_NUM, 1377 .regs = ksz9477_regs, 1378 .masks = ksz9477_masks, 1379 .shifts = ksz9477_shifts, 1380 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1381 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1382 .supports_mii = {false, false, false, false, 1383 false, true}, 1384 .supports_rmii = {false, false, false, false, 1385 false, true}, 1386 .supports_rgmii = {false, false, false, false, 1387 false, true}, 1388 .internal_phy = {true, true, true, true, 1389 true, false}, 1390 .gbit_capable = {true, true, true, true, true, true}, 1391 .wr_table = &ksz9896_register_set, 1392 .rd_table = &ksz9896_register_set, 1393 }, 1394 1395 [KSZ9897] = { 1396 .chip_id = KSZ9897_CHIP_ID, 1397 .dev_name = "KSZ9897", 1398 .num_vlans = 4096, 1399 .num_alus = 4096, 1400 .num_statics = 16, 1401 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1402 .port_cnt = 7, /* total physical port count */ 1403 .port_nirqs = 2, 1404 .num_tx_queues = 4, 1405 .ops = &ksz9477_dev_ops, 1406 .mib_names = ksz9477_mib_names, 1407 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1408 .reg_mib_cnt = MIB_COUNTER_NUM, 1409 .regs = ksz9477_regs, 1410 .masks = ksz9477_masks, 1411 .shifts = ksz9477_shifts, 1412 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1413 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1414 .supports_mii = {false, false, false, false, 1415 false, true, true}, 1416 .supports_rmii = {false, false, false, false, 1417 false, true, true}, 1418 .supports_rgmii = {false, false, false, false, 1419 false, true, true}, 1420 .internal_phy = {true, true, true, true, 1421 true, false, false}, 1422 .gbit_capable = {true, true, true, true, true, true, true}, 1423 }, 1424 1425 [KSZ9893] = { 1426 .chip_id = KSZ9893_CHIP_ID, 1427 .dev_name = "KSZ9893", 1428 .num_vlans = 4096, 1429 .num_alus = 4096, 1430 .num_statics = 16, 1431 .cpu_ports = 0x07, /* can be configured as cpu port */ 1432 .port_cnt = 3, /* total port count */ 1433 .port_nirqs = 2, 1434 .num_tx_queues = 4, 1435 .ops = &ksz9477_dev_ops, 1436 .mib_names = ksz9477_mib_names, 1437 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1438 .reg_mib_cnt = MIB_COUNTER_NUM, 1439 .regs = ksz9477_regs, 1440 .masks = ksz9477_masks, 1441 .shifts = ksz9477_shifts, 1442 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1443 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1444 .supports_mii = {false, false, true}, 1445 .supports_rmii = {false, false, true}, 1446 .supports_rgmii = {false, false, true}, 1447 .internal_phy = {true, true, false}, 1448 .gbit_capable = {true, true, true}, 1449 }, 1450 1451 [KSZ9563] = { 1452 .chip_id = KSZ9563_CHIP_ID, 1453 .dev_name = "KSZ9563", 1454 .num_vlans = 4096, 1455 .num_alus = 4096, 1456 .num_statics = 16, 1457 .cpu_ports = 0x07, /* can be configured as cpu port */ 1458 .port_cnt = 3, /* total port count */ 1459 .port_nirqs = 3, 1460 .num_tx_queues = 4, 1461 .tc_cbs_supported = true, 1462 .tc_ets_supported = true, 1463 .ops = &ksz9477_dev_ops, 1464 .mib_names = ksz9477_mib_names, 1465 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1466 .reg_mib_cnt = MIB_COUNTER_NUM, 1467 .regs = ksz9477_regs, 1468 .masks = ksz9477_masks, 1469 .shifts = ksz9477_shifts, 1470 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1471 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1472 .supports_mii = {false, false, true}, 1473 .supports_rmii = {false, false, true}, 1474 .supports_rgmii = {false, false, true}, 1475 .internal_phy = {true, true, false}, 1476 .gbit_capable = {true, true, true}, 1477 }, 1478 1479 [KSZ8567] = { 1480 .chip_id = KSZ8567_CHIP_ID, 1481 .dev_name = "KSZ8567", 1482 .num_vlans = 4096, 1483 .num_alus = 4096, 1484 .num_statics = 16, 1485 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1486 .port_cnt = 7, /* total port count */ 1487 .port_nirqs = 3, 1488 .num_tx_queues = 4, 1489 .tc_cbs_supported = true, 1490 .tc_ets_supported = true, 1491 .ops = &ksz9477_dev_ops, 1492 .mib_names = ksz9477_mib_names, 1493 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1494 .reg_mib_cnt = MIB_COUNTER_NUM, 1495 .regs = ksz9477_regs, 1496 .masks = ksz9477_masks, 1497 .shifts = ksz9477_shifts, 1498 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1499 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1500 .supports_mii = {false, false, false, false, 1501 false, true, true}, 1502 .supports_rmii = {false, false, false, false, 1503 false, true, true}, 1504 .supports_rgmii = {false, false, false, false, 1505 false, true, true}, 1506 .internal_phy = {true, true, true, true, 1507 true, false, false}, 1508 .gbit_capable = {false, false, false, false, false, 1509 true, true}, 1510 }, 1511 1512 [KSZ9567] = { 1513 .chip_id = KSZ9567_CHIP_ID, 1514 .dev_name = "KSZ9567", 1515 .num_vlans = 4096, 1516 .num_alus = 4096, 1517 .num_statics = 16, 1518 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1519 .port_cnt = 7, /* total physical port count */ 1520 .port_nirqs = 3, 1521 .num_tx_queues = 4, 1522 .tc_cbs_supported = true, 1523 .tc_ets_supported = true, 1524 .ops = &ksz9477_dev_ops, 1525 .mib_names = ksz9477_mib_names, 1526 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1527 .reg_mib_cnt = MIB_COUNTER_NUM, 1528 .regs = ksz9477_regs, 1529 .masks = ksz9477_masks, 1530 .shifts = ksz9477_shifts, 1531 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1532 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1533 .supports_mii = {false, false, false, false, 1534 false, true, true}, 1535 .supports_rmii = {false, false, false, false, 1536 false, true, true}, 1537 .supports_rgmii = {false, false, false, false, 1538 false, true, true}, 1539 .internal_phy = {true, true, true, true, 1540 true, false, false}, 1541 .gbit_capable = {true, true, true, true, true, true, true}, 1542 }, 1543 1544 [LAN9370] = { 1545 .chip_id = LAN9370_CHIP_ID, 1546 .dev_name = "LAN9370", 1547 .num_vlans = 4096, 1548 .num_alus = 1024, 1549 .num_statics = 256, 1550 .cpu_ports = 0x10, /* can be configured as cpu port */ 1551 .port_cnt = 5, /* total physical port count */ 1552 .port_nirqs = 6, 1553 .num_tx_queues = 8, 1554 .tc_cbs_supported = true, 1555 .tc_ets_supported = true, 1556 .ops = &lan937x_dev_ops, 1557 .mib_names = ksz9477_mib_names, 1558 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1559 .reg_mib_cnt = MIB_COUNTER_NUM, 1560 .regs = ksz9477_regs, 1561 .masks = lan937x_masks, 1562 .shifts = lan937x_shifts, 1563 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1564 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1565 .supports_mii = {false, false, false, false, true}, 1566 .supports_rmii = {false, false, false, false, true}, 1567 .supports_rgmii = {false, false, false, false, true}, 1568 .internal_phy = {true, true, true, true, false}, 1569 }, 1570 1571 [LAN9371] = { 1572 .chip_id = LAN9371_CHIP_ID, 1573 .dev_name = "LAN9371", 1574 .num_vlans = 4096, 1575 .num_alus = 1024, 1576 .num_statics = 256, 1577 .cpu_ports = 0x30, /* can be configured as cpu port */ 1578 .port_cnt = 6, /* total physical port count */ 1579 .port_nirqs = 6, 1580 .num_tx_queues = 8, 1581 .tc_cbs_supported = true, 1582 .tc_ets_supported = true, 1583 .ops = &lan937x_dev_ops, 1584 .mib_names = ksz9477_mib_names, 1585 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1586 .reg_mib_cnt = MIB_COUNTER_NUM, 1587 .regs = ksz9477_regs, 1588 .masks = lan937x_masks, 1589 .shifts = lan937x_shifts, 1590 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1591 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1592 .supports_mii = {false, false, false, false, true, true}, 1593 .supports_rmii = {false, false, false, false, true, true}, 1594 .supports_rgmii = {false, false, false, false, true, true}, 1595 .internal_phy = {true, true, true, true, false, false}, 1596 }, 1597 1598 [LAN9372] = { 1599 .chip_id = LAN9372_CHIP_ID, 1600 .dev_name = "LAN9372", 1601 .num_vlans = 4096, 1602 .num_alus = 1024, 1603 .num_statics = 256, 1604 .cpu_ports = 0x30, /* can be configured as cpu port */ 1605 .port_cnt = 8, /* total physical port count */ 1606 .port_nirqs = 6, 1607 .num_tx_queues = 8, 1608 .tc_cbs_supported = true, 1609 .tc_ets_supported = true, 1610 .ops = &lan937x_dev_ops, 1611 .mib_names = ksz9477_mib_names, 1612 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1613 .reg_mib_cnt = MIB_COUNTER_NUM, 1614 .regs = ksz9477_regs, 1615 .masks = lan937x_masks, 1616 .shifts = lan937x_shifts, 1617 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1618 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1619 .supports_mii = {false, false, false, false, 1620 true, true, false, false}, 1621 .supports_rmii = {false, false, false, false, 1622 true, true, false, false}, 1623 .supports_rgmii = {false, false, false, false, 1624 true, true, false, false}, 1625 .internal_phy = {true, true, true, true, 1626 false, false, true, true}, 1627 }, 1628 1629 [LAN9373] = { 1630 .chip_id = LAN9373_CHIP_ID, 1631 .dev_name = "LAN9373", 1632 .num_vlans = 4096, 1633 .num_alus = 1024, 1634 .num_statics = 256, 1635 .cpu_ports = 0x38, /* can be configured as cpu port */ 1636 .port_cnt = 5, /* total physical port count */ 1637 .port_nirqs = 6, 1638 .num_tx_queues = 8, 1639 .tc_cbs_supported = true, 1640 .tc_ets_supported = true, 1641 .ops = &lan937x_dev_ops, 1642 .mib_names = ksz9477_mib_names, 1643 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1644 .reg_mib_cnt = MIB_COUNTER_NUM, 1645 .regs = ksz9477_regs, 1646 .masks = lan937x_masks, 1647 .shifts = lan937x_shifts, 1648 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1649 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1650 .supports_mii = {false, false, false, false, 1651 true, true, false, false}, 1652 .supports_rmii = {false, false, false, false, 1653 true, true, false, false}, 1654 .supports_rgmii = {false, false, false, false, 1655 true, true, false, false}, 1656 .internal_phy = {true, true, true, false, 1657 false, false, true, true}, 1658 }, 1659 1660 [LAN9374] = { 1661 .chip_id = LAN9374_CHIP_ID, 1662 .dev_name = "LAN9374", 1663 .num_vlans = 4096, 1664 .num_alus = 1024, 1665 .num_statics = 256, 1666 .cpu_ports = 0x30, /* can be configured as cpu port */ 1667 .port_cnt = 8, /* total physical port count */ 1668 .port_nirqs = 6, 1669 .num_tx_queues = 8, 1670 .tc_cbs_supported = true, 1671 .tc_ets_supported = true, 1672 .ops = &lan937x_dev_ops, 1673 .mib_names = ksz9477_mib_names, 1674 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1675 .reg_mib_cnt = MIB_COUNTER_NUM, 1676 .regs = ksz9477_regs, 1677 .masks = lan937x_masks, 1678 .shifts = lan937x_shifts, 1679 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1680 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1681 .supports_mii = {false, false, false, false, 1682 true, true, false, false}, 1683 .supports_rmii = {false, false, false, false, 1684 true, true, false, false}, 1685 .supports_rgmii = {false, false, false, false, 1686 true, true, false, false}, 1687 .internal_phy = {true, true, true, true, 1688 false, false, true, true}, 1689 }, 1690 }; 1691 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1692 1693 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1694 { 1695 int i; 1696 1697 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1698 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1699 1700 if (chip->chip_id == prod_num) 1701 return chip; 1702 } 1703 1704 return NULL; 1705 } 1706 1707 static int ksz_check_device_id(struct ksz_device *dev) 1708 { 1709 const struct ksz_chip_data *expected_chip_data; 1710 u32 expected_chip_id; 1711 1712 if (dev->pdata) { 1713 expected_chip_id = dev->pdata->chip_id; 1714 expected_chip_data = ksz_lookup_info(expected_chip_id); 1715 if (WARN_ON(!expected_chip_data)) 1716 return -ENODEV; 1717 } else { 1718 expected_chip_data = of_device_get_match_data(dev->dev); 1719 expected_chip_id = expected_chip_data->chip_id; 1720 } 1721 1722 if (expected_chip_id != dev->chip_id) { 1723 dev_err(dev->dev, 1724 "Device tree specifies chip %s but found %s, please fix it!\n", 1725 expected_chip_data->dev_name, dev->info->dev_name); 1726 return -ENODEV; 1727 } 1728 1729 return 0; 1730 } 1731 1732 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1733 struct phylink_config *config) 1734 { 1735 struct ksz_device *dev = ds->priv; 1736 1737 if (dev->info->supports_mii[port]) 1738 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1739 1740 if (dev->info->supports_rmii[port]) 1741 __set_bit(PHY_INTERFACE_MODE_RMII, 1742 config->supported_interfaces); 1743 1744 if (dev->info->supports_rgmii[port]) 1745 phy_interface_set_rgmii(config->supported_interfaces); 1746 1747 if (dev->info->internal_phy[port]) { 1748 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1749 config->supported_interfaces); 1750 /* Compatibility for phylib's default interface type when the 1751 * phy-mode property is absent 1752 */ 1753 __set_bit(PHY_INTERFACE_MODE_GMII, 1754 config->supported_interfaces); 1755 } 1756 1757 if (dev->dev_ops->get_caps) 1758 dev->dev_ops->get_caps(dev, port, config); 1759 } 1760 1761 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 1762 { 1763 struct ethtool_pause_stats *pstats; 1764 struct rtnl_link_stats64 *stats; 1765 struct ksz_stats_raw *raw; 1766 struct ksz_port_mib *mib; 1767 1768 mib = &dev->ports[port].mib; 1769 stats = &mib->stats64; 1770 pstats = &mib->pause_stats; 1771 raw = (struct ksz_stats_raw *)mib->counters; 1772 1773 spin_lock(&mib->stats64_lock); 1774 1775 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1776 raw->rx_pause; 1777 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1778 raw->tx_pause; 1779 1780 /* HW counters are counting bytes + FCS which is not acceptable 1781 * for rtnl_link_stats64 interface 1782 */ 1783 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 1784 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 1785 1786 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1787 raw->rx_oversize; 1788 1789 stats->rx_crc_errors = raw->rx_crc_err; 1790 stats->rx_frame_errors = raw->rx_align_err; 1791 stats->rx_dropped = raw->rx_discards; 1792 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1793 stats->rx_frame_errors + stats->rx_dropped; 1794 1795 stats->tx_window_errors = raw->tx_late_col; 1796 stats->tx_fifo_errors = raw->tx_discards; 1797 stats->tx_aborted_errors = raw->tx_exc_col; 1798 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1799 stats->tx_aborted_errors; 1800 1801 stats->multicast = raw->rx_mcast; 1802 stats->collisions = raw->tx_total_col; 1803 1804 pstats->tx_pause_frames = raw->tx_pause; 1805 pstats->rx_pause_frames = raw->rx_pause; 1806 1807 spin_unlock(&mib->stats64_lock); 1808 } 1809 1810 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 1811 { 1812 struct ethtool_pause_stats *pstats; 1813 struct rtnl_link_stats64 *stats; 1814 struct ksz88xx_stats_raw *raw; 1815 struct ksz_port_mib *mib; 1816 1817 mib = &dev->ports[port].mib; 1818 stats = &mib->stats64; 1819 pstats = &mib->pause_stats; 1820 raw = (struct ksz88xx_stats_raw *)mib->counters; 1821 1822 spin_lock(&mib->stats64_lock); 1823 1824 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1825 raw->rx_pause; 1826 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1827 raw->tx_pause; 1828 1829 /* HW counters are counting bytes + FCS which is not acceptable 1830 * for rtnl_link_stats64 interface 1831 */ 1832 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 1833 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 1834 1835 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1836 raw->rx_oversize; 1837 1838 stats->rx_crc_errors = raw->rx_crc_err; 1839 stats->rx_frame_errors = raw->rx_align_err; 1840 stats->rx_dropped = raw->rx_discards; 1841 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1842 stats->rx_frame_errors + stats->rx_dropped; 1843 1844 stats->tx_window_errors = raw->tx_late_col; 1845 stats->tx_fifo_errors = raw->tx_discards; 1846 stats->tx_aborted_errors = raw->tx_exc_col; 1847 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1848 stats->tx_aborted_errors; 1849 1850 stats->multicast = raw->rx_mcast; 1851 stats->collisions = raw->tx_total_col; 1852 1853 pstats->tx_pause_frames = raw->tx_pause; 1854 pstats->rx_pause_frames = raw->rx_pause; 1855 1856 spin_unlock(&mib->stats64_lock); 1857 } 1858 1859 static void ksz_get_stats64(struct dsa_switch *ds, int port, 1860 struct rtnl_link_stats64 *s) 1861 { 1862 struct ksz_device *dev = ds->priv; 1863 struct ksz_port_mib *mib; 1864 1865 mib = &dev->ports[port].mib; 1866 1867 spin_lock(&mib->stats64_lock); 1868 memcpy(s, &mib->stats64, sizeof(*s)); 1869 spin_unlock(&mib->stats64_lock); 1870 } 1871 1872 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 1873 struct ethtool_pause_stats *pause_stats) 1874 { 1875 struct ksz_device *dev = ds->priv; 1876 struct ksz_port_mib *mib; 1877 1878 mib = &dev->ports[port].mib; 1879 1880 spin_lock(&mib->stats64_lock); 1881 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 1882 spin_unlock(&mib->stats64_lock); 1883 } 1884 1885 static void ksz_get_strings(struct dsa_switch *ds, int port, 1886 u32 stringset, uint8_t *buf) 1887 { 1888 struct ksz_device *dev = ds->priv; 1889 int i; 1890 1891 if (stringset != ETH_SS_STATS) 1892 return; 1893 1894 for (i = 0; i < dev->info->mib_cnt; i++) { 1895 memcpy(buf + i * ETH_GSTRING_LEN, 1896 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 1897 } 1898 } 1899 1900 static void ksz_update_port_member(struct ksz_device *dev, int port) 1901 { 1902 struct ksz_port *p = &dev->ports[port]; 1903 struct dsa_switch *ds = dev->ds; 1904 u8 port_member = 0, cpu_port; 1905 const struct dsa_port *dp; 1906 int i, j; 1907 1908 if (!dsa_is_user_port(ds, port)) 1909 return; 1910 1911 dp = dsa_to_port(ds, port); 1912 cpu_port = BIT(dsa_upstream_port(ds, port)); 1913 1914 for (i = 0; i < ds->num_ports; i++) { 1915 const struct dsa_port *other_dp = dsa_to_port(ds, i); 1916 struct ksz_port *other_p = &dev->ports[i]; 1917 u8 val = 0; 1918 1919 if (!dsa_is_user_port(ds, i)) 1920 continue; 1921 if (port == i) 1922 continue; 1923 if (!dsa_port_bridge_same(dp, other_dp)) 1924 continue; 1925 if (other_p->stp_state != BR_STATE_FORWARDING) 1926 continue; 1927 1928 if (p->stp_state == BR_STATE_FORWARDING) { 1929 val |= BIT(port); 1930 port_member |= BIT(i); 1931 } 1932 1933 /* Retain port [i]'s relationship to other ports than [port] */ 1934 for (j = 0; j < ds->num_ports; j++) { 1935 const struct dsa_port *third_dp; 1936 struct ksz_port *third_p; 1937 1938 if (j == i) 1939 continue; 1940 if (j == port) 1941 continue; 1942 if (!dsa_is_user_port(ds, j)) 1943 continue; 1944 third_p = &dev->ports[j]; 1945 if (third_p->stp_state != BR_STATE_FORWARDING) 1946 continue; 1947 third_dp = dsa_to_port(ds, j); 1948 if (dsa_port_bridge_same(other_dp, third_dp)) 1949 val |= BIT(j); 1950 } 1951 1952 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 1953 } 1954 1955 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 1956 } 1957 1958 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 1959 { 1960 struct ksz_device *dev = bus->priv; 1961 u16 val; 1962 int ret; 1963 1964 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 1965 if (ret < 0) 1966 return ret; 1967 1968 return val; 1969 } 1970 1971 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 1972 u16 val) 1973 { 1974 struct ksz_device *dev = bus->priv; 1975 1976 return dev->dev_ops->w_phy(dev, addr, regnum, val); 1977 } 1978 1979 static int ksz_irq_phy_setup(struct ksz_device *dev) 1980 { 1981 struct dsa_switch *ds = dev->ds; 1982 int phy; 1983 int irq; 1984 int ret; 1985 1986 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) { 1987 if (BIT(phy) & ds->phys_mii_mask) { 1988 irq = irq_find_mapping(dev->ports[phy].pirq.domain, 1989 PORT_SRC_PHY_INT); 1990 if (irq < 0) { 1991 ret = irq; 1992 goto out; 1993 } 1994 ds->user_mii_bus->irq[phy] = irq; 1995 } 1996 } 1997 return 0; 1998 out: 1999 while (phy--) 2000 if (BIT(phy) & ds->phys_mii_mask) 2001 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2002 2003 return ret; 2004 } 2005 2006 static void ksz_irq_phy_free(struct ksz_device *dev) 2007 { 2008 struct dsa_switch *ds = dev->ds; 2009 int phy; 2010 2011 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) 2012 if (BIT(phy) & ds->phys_mii_mask) 2013 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2014 } 2015 2016 static int ksz_mdio_register(struct ksz_device *dev) 2017 { 2018 struct dsa_switch *ds = dev->ds; 2019 struct device_node *mdio_np; 2020 struct mii_bus *bus; 2021 int ret; 2022 2023 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 2024 if (!mdio_np) 2025 return 0; 2026 2027 bus = devm_mdiobus_alloc(ds->dev); 2028 if (!bus) { 2029 of_node_put(mdio_np); 2030 return -ENOMEM; 2031 } 2032 2033 bus->priv = dev; 2034 bus->read = ksz_sw_mdio_read; 2035 bus->write = ksz_sw_mdio_write; 2036 bus->name = "ksz user smi"; 2037 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 2038 bus->parent = ds->dev; 2039 bus->phy_mask = ~ds->phys_mii_mask; 2040 2041 ds->user_mii_bus = bus; 2042 2043 if (dev->irq > 0) { 2044 ret = ksz_irq_phy_setup(dev); 2045 if (ret) { 2046 of_node_put(mdio_np); 2047 return ret; 2048 } 2049 } 2050 2051 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 2052 if (ret) { 2053 dev_err(ds->dev, "unable to register MDIO bus %s\n", 2054 bus->id); 2055 if (dev->irq > 0) 2056 ksz_irq_phy_free(dev); 2057 } 2058 2059 of_node_put(mdio_np); 2060 2061 return ret; 2062 } 2063 2064 static void ksz_irq_mask(struct irq_data *d) 2065 { 2066 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2067 2068 kirq->masked |= BIT(d->hwirq); 2069 } 2070 2071 static void ksz_irq_unmask(struct irq_data *d) 2072 { 2073 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2074 2075 kirq->masked &= ~BIT(d->hwirq); 2076 } 2077 2078 static void ksz_irq_bus_lock(struct irq_data *d) 2079 { 2080 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2081 2082 mutex_lock(&kirq->dev->lock_irq); 2083 } 2084 2085 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 2086 { 2087 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2088 struct ksz_device *dev = kirq->dev; 2089 int ret; 2090 2091 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked); 2092 if (ret) 2093 dev_err(dev->dev, "failed to change IRQ mask\n"); 2094 2095 mutex_unlock(&dev->lock_irq); 2096 } 2097 2098 static const struct irq_chip ksz_irq_chip = { 2099 .name = "ksz-irq", 2100 .irq_mask = ksz_irq_mask, 2101 .irq_unmask = ksz_irq_unmask, 2102 .irq_bus_lock = ksz_irq_bus_lock, 2103 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 2104 }; 2105 2106 static int ksz_irq_domain_map(struct irq_domain *d, 2107 unsigned int irq, irq_hw_number_t hwirq) 2108 { 2109 irq_set_chip_data(irq, d->host_data); 2110 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 2111 irq_set_noprobe(irq); 2112 2113 return 0; 2114 } 2115 2116 static const struct irq_domain_ops ksz_irq_domain_ops = { 2117 .map = ksz_irq_domain_map, 2118 .xlate = irq_domain_xlate_twocell, 2119 }; 2120 2121 static void ksz_irq_free(struct ksz_irq *kirq) 2122 { 2123 int irq, virq; 2124 2125 free_irq(kirq->irq_num, kirq); 2126 2127 for (irq = 0; irq < kirq->nirqs; irq++) { 2128 virq = irq_find_mapping(kirq->domain, irq); 2129 irq_dispose_mapping(virq); 2130 } 2131 2132 irq_domain_remove(kirq->domain); 2133 } 2134 2135 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 2136 { 2137 struct ksz_irq *kirq = dev_id; 2138 unsigned int nhandled = 0; 2139 struct ksz_device *dev; 2140 unsigned int sub_irq; 2141 u8 data; 2142 int ret; 2143 u8 n; 2144 2145 dev = kirq->dev; 2146 2147 /* Read interrupt status register */ 2148 ret = ksz_read8(dev, kirq->reg_status, &data); 2149 if (ret) 2150 goto out; 2151 2152 for (n = 0; n < kirq->nirqs; ++n) { 2153 if (data & BIT(n)) { 2154 sub_irq = irq_find_mapping(kirq->domain, n); 2155 handle_nested_irq(sub_irq); 2156 ++nhandled; 2157 } 2158 } 2159 out: 2160 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2161 } 2162 2163 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 2164 { 2165 int ret, n; 2166 2167 kirq->dev = dev; 2168 kirq->masked = ~0; 2169 2170 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0, 2171 &ksz_irq_domain_ops, kirq); 2172 if (!kirq->domain) 2173 return -ENOMEM; 2174 2175 for (n = 0; n < kirq->nirqs; n++) 2176 irq_create_mapping(kirq->domain, n); 2177 2178 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2179 IRQF_ONESHOT, kirq->name, kirq); 2180 if (ret) 2181 goto out; 2182 2183 return 0; 2184 2185 out: 2186 ksz_irq_free(kirq); 2187 2188 return ret; 2189 } 2190 2191 static int ksz_girq_setup(struct ksz_device *dev) 2192 { 2193 struct ksz_irq *girq = &dev->girq; 2194 2195 girq->nirqs = dev->info->port_cnt; 2196 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2197 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2198 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2199 2200 girq->irq_num = dev->irq; 2201 2202 return ksz_irq_common_setup(dev, girq); 2203 } 2204 2205 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2206 { 2207 struct ksz_irq *pirq = &dev->ports[p].pirq; 2208 2209 pirq->nirqs = dev->info->port_nirqs; 2210 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2211 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2212 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2213 2214 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2215 if (pirq->irq_num < 0) 2216 return pirq->irq_num; 2217 2218 return ksz_irq_common_setup(dev, pirq); 2219 } 2220 2221 static int ksz_setup(struct dsa_switch *ds) 2222 { 2223 struct ksz_device *dev = ds->priv; 2224 struct dsa_port *dp; 2225 struct ksz_port *p; 2226 const u16 *regs; 2227 int ret; 2228 2229 regs = dev->info->regs; 2230 2231 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2232 dev->info->num_vlans, GFP_KERNEL); 2233 if (!dev->vlan_cache) 2234 return -ENOMEM; 2235 2236 ret = dev->dev_ops->reset(dev); 2237 if (ret) { 2238 dev_err(ds->dev, "failed to reset switch\n"); 2239 return ret; 2240 } 2241 2242 /* set broadcast storm protection 10% rate */ 2243 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2244 BROADCAST_STORM_RATE, 2245 (BROADCAST_STORM_VALUE * 2246 BROADCAST_STORM_PROT_RATE) / 100); 2247 2248 dev->dev_ops->config_cpu_port(ds); 2249 2250 dev->dev_ops->enable_stp_addr(dev); 2251 2252 ds->num_tx_queues = dev->info->num_tx_queues; 2253 2254 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 2255 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2256 2257 ksz_init_mib_timer(dev); 2258 2259 ds->configure_vlan_while_not_filtering = false; 2260 2261 if (dev->dev_ops->setup) { 2262 ret = dev->dev_ops->setup(ds); 2263 if (ret) 2264 return ret; 2265 } 2266 2267 /* Start with learning disabled on standalone user ports, and enabled 2268 * on the CPU port. In lack of other finer mechanisms, learning on the 2269 * CPU port will avoid flooding bridge local addresses on the network 2270 * in some cases. 2271 */ 2272 p = &dev->ports[dev->cpu_port]; 2273 p->learning = true; 2274 2275 if (dev->irq > 0) { 2276 ret = ksz_girq_setup(dev); 2277 if (ret) 2278 return ret; 2279 2280 dsa_switch_for_each_user_port(dp, dev->ds) { 2281 ret = ksz_pirq_setup(dev, dp->index); 2282 if (ret) 2283 goto out_girq; 2284 2285 ret = ksz_ptp_irq_setup(ds, dp->index); 2286 if (ret) 2287 goto out_pirq; 2288 } 2289 } 2290 2291 ret = ksz_ptp_clock_register(ds); 2292 if (ret) { 2293 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret); 2294 goto out_ptpirq; 2295 } 2296 2297 ret = ksz_mdio_register(dev); 2298 if (ret < 0) { 2299 dev_err(dev->dev, "failed to register the mdio"); 2300 goto out_ptp_clock_unregister; 2301 } 2302 2303 /* start switch */ 2304 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 2305 SW_START, SW_START); 2306 2307 return 0; 2308 2309 out_ptp_clock_unregister: 2310 ksz_ptp_clock_unregister(ds); 2311 out_ptpirq: 2312 if (dev->irq > 0) 2313 dsa_switch_for_each_user_port(dp, dev->ds) 2314 ksz_ptp_irq_free(ds, dp->index); 2315 out_pirq: 2316 if (dev->irq > 0) 2317 dsa_switch_for_each_user_port(dp, dev->ds) 2318 ksz_irq_free(&dev->ports[dp->index].pirq); 2319 out_girq: 2320 if (dev->irq > 0) 2321 ksz_irq_free(&dev->girq); 2322 2323 return ret; 2324 } 2325 2326 static void ksz_teardown(struct dsa_switch *ds) 2327 { 2328 struct ksz_device *dev = ds->priv; 2329 struct dsa_port *dp; 2330 2331 ksz_ptp_clock_unregister(ds); 2332 2333 if (dev->irq > 0) { 2334 dsa_switch_for_each_user_port(dp, dev->ds) { 2335 ksz_ptp_irq_free(ds, dp->index); 2336 2337 ksz_irq_free(&dev->ports[dp->index].pirq); 2338 } 2339 2340 ksz_irq_free(&dev->girq); 2341 } 2342 2343 if (dev->dev_ops->teardown) 2344 dev->dev_ops->teardown(ds); 2345 } 2346 2347 static void port_r_cnt(struct ksz_device *dev, int port) 2348 { 2349 struct ksz_port_mib *mib = &dev->ports[port].mib; 2350 u64 *dropped; 2351 2352 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2353 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2354 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2355 &mib->counters[mib->cnt_ptr]); 2356 ++mib->cnt_ptr; 2357 } 2358 2359 /* last one in storage */ 2360 dropped = &mib->counters[dev->info->mib_cnt]; 2361 2362 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2363 while (mib->cnt_ptr < dev->info->mib_cnt) { 2364 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2365 dropped, &mib->counters[mib->cnt_ptr]); 2366 ++mib->cnt_ptr; 2367 } 2368 mib->cnt_ptr = 0; 2369 } 2370 2371 static void ksz_mib_read_work(struct work_struct *work) 2372 { 2373 struct ksz_device *dev = container_of(work, struct ksz_device, 2374 mib_read.work); 2375 struct ksz_port_mib *mib; 2376 struct ksz_port *p; 2377 int i; 2378 2379 for (i = 0; i < dev->info->port_cnt; i++) { 2380 if (dsa_is_unused_port(dev->ds, i)) 2381 continue; 2382 2383 p = &dev->ports[i]; 2384 mib = &p->mib; 2385 mutex_lock(&mib->cnt_mutex); 2386 2387 /* Only read MIB counters when the port is told to do. 2388 * If not, read only dropped counters when link is not up. 2389 */ 2390 if (!p->read) { 2391 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 2392 2393 if (!netif_carrier_ok(dp->user)) 2394 mib->cnt_ptr = dev->info->reg_mib_cnt; 2395 } 2396 port_r_cnt(dev, i); 2397 p->read = false; 2398 2399 if (dev->dev_ops->r_mib_stat64) 2400 dev->dev_ops->r_mib_stat64(dev, i); 2401 2402 mutex_unlock(&mib->cnt_mutex); 2403 } 2404 2405 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 2406 } 2407 2408 void ksz_init_mib_timer(struct ksz_device *dev) 2409 { 2410 int i; 2411 2412 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 2413 2414 for (i = 0; i < dev->info->port_cnt; i++) { 2415 struct ksz_port_mib *mib = &dev->ports[i].mib; 2416 2417 dev->dev_ops->port_init_cnt(dev, i); 2418 2419 mib->cnt_ptr = 0; 2420 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 2421 } 2422 } 2423 2424 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 2425 { 2426 struct ksz_device *dev = ds->priv; 2427 u16 val = 0xffff; 2428 int ret; 2429 2430 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 2431 if (ret) 2432 return ret; 2433 2434 return val; 2435 } 2436 2437 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 2438 { 2439 struct ksz_device *dev = ds->priv; 2440 int ret; 2441 2442 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 2443 if (ret) 2444 return ret; 2445 2446 return 0; 2447 } 2448 2449 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 2450 { 2451 struct ksz_device *dev = ds->priv; 2452 2453 switch (dev->chip_id) { 2454 case KSZ8830_CHIP_ID: 2455 /* Silicon Errata Sheet (DS80000830A): 2456 * Port 1 does not work with LinkMD Cable-Testing. 2457 * Port 1 does not respond to received PAUSE control frames. 2458 */ 2459 if (!port) 2460 return MICREL_KSZ8_P1_ERRATA; 2461 break; 2462 case KSZ9477_CHIP_ID: 2463 /* KSZ9477 Errata DS80000754C 2464 * 2465 * Module 4: Energy Efficient Ethernet (EEE) feature select must 2466 * be manually disabled 2467 * The EEE feature is enabled by default, but it is not fully 2468 * operational. It must be manually disabled through register 2469 * controls. If not disabled, the PHY ports can auto-negotiate 2470 * to enable EEE, and this feature can cause link drops when 2471 * linked to another device supporting EEE. 2472 */ 2473 return MICREL_NO_EEE; 2474 } 2475 2476 return 0; 2477 } 2478 2479 static void ksz_mac_link_down(struct dsa_switch *ds, int port, 2480 unsigned int mode, phy_interface_t interface) 2481 { 2482 struct ksz_device *dev = ds->priv; 2483 struct ksz_port *p = &dev->ports[port]; 2484 2485 /* Read all MIB counters when the link is going down. */ 2486 p->read = true; 2487 /* timer started */ 2488 if (dev->mib_read_interval) 2489 schedule_delayed_work(&dev->mib_read, 0); 2490 } 2491 2492 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 2493 { 2494 struct ksz_device *dev = ds->priv; 2495 2496 if (sset != ETH_SS_STATS) 2497 return 0; 2498 2499 return dev->info->mib_cnt; 2500 } 2501 2502 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 2503 uint64_t *buf) 2504 { 2505 const struct dsa_port *dp = dsa_to_port(ds, port); 2506 struct ksz_device *dev = ds->priv; 2507 struct ksz_port_mib *mib; 2508 2509 mib = &dev->ports[port].mib; 2510 mutex_lock(&mib->cnt_mutex); 2511 2512 /* Only read dropped counters if no link. */ 2513 if (!netif_carrier_ok(dp->user)) 2514 mib->cnt_ptr = dev->info->reg_mib_cnt; 2515 port_r_cnt(dev, port); 2516 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 2517 mutex_unlock(&mib->cnt_mutex); 2518 } 2519 2520 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 2521 struct dsa_bridge bridge, 2522 bool *tx_fwd_offload, 2523 struct netlink_ext_ack *extack) 2524 { 2525 /* port_stp_state_set() will be called after to put the port in 2526 * appropriate state so there is no need to do anything. 2527 */ 2528 2529 return 0; 2530 } 2531 2532 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 2533 struct dsa_bridge bridge) 2534 { 2535 /* port_stp_state_set() will be called after to put the port in 2536 * forwarding state so there is no need to do anything. 2537 */ 2538 } 2539 2540 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 2541 { 2542 struct ksz_device *dev = ds->priv; 2543 2544 dev->dev_ops->flush_dyn_mac_table(dev, port); 2545 } 2546 2547 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 2548 { 2549 struct ksz_device *dev = ds->priv; 2550 2551 if (!dev->dev_ops->set_ageing_time) 2552 return -EOPNOTSUPP; 2553 2554 return dev->dev_ops->set_ageing_time(dev, msecs); 2555 } 2556 2557 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 2558 const unsigned char *addr, u16 vid, 2559 struct dsa_db db) 2560 { 2561 struct ksz_device *dev = ds->priv; 2562 2563 if (!dev->dev_ops->fdb_add) 2564 return -EOPNOTSUPP; 2565 2566 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 2567 } 2568 2569 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 2570 const unsigned char *addr, 2571 u16 vid, struct dsa_db db) 2572 { 2573 struct ksz_device *dev = ds->priv; 2574 2575 if (!dev->dev_ops->fdb_del) 2576 return -EOPNOTSUPP; 2577 2578 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 2579 } 2580 2581 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 2582 dsa_fdb_dump_cb_t *cb, void *data) 2583 { 2584 struct ksz_device *dev = ds->priv; 2585 2586 if (!dev->dev_ops->fdb_dump) 2587 return -EOPNOTSUPP; 2588 2589 return dev->dev_ops->fdb_dump(dev, port, cb, data); 2590 } 2591 2592 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 2593 const struct switchdev_obj_port_mdb *mdb, 2594 struct dsa_db db) 2595 { 2596 struct ksz_device *dev = ds->priv; 2597 2598 if (!dev->dev_ops->mdb_add) 2599 return -EOPNOTSUPP; 2600 2601 return dev->dev_ops->mdb_add(dev, port, mdb, db); 2602 } 2603 2604 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 2605 const struct switchdev_obj_port_mdb *mdb, 2606 struct dsa_db db) 2607 { 2608 struct ksz_device *dev = ds->priv; 2609 2610 if (!dev->dev_ops->mdb_del) 2611 return -EOPNOTSUPP; 2612 2613 return dev->dev_ops->mdb_del(dev, port, mdb, db); 2614 } 2615 2616 static int ksz_port_setup(struct dsa_switch *ds, int port) 2617 { 2618 struct ksz_device *dev = ds->priv; 2619 2620 if (!dsa_is_user_port(ds, port)) 2621 return 0; 2622 2623 /* setup user port */ 2624 dev->dev_ops->port_setup(dev, port, false); 2625 2626 /* port_stp_state_set() will be called after to enable the port so 2627 * there is no need to do anything. 2628 */ 2629 2630 return 0; 2631 } 2632 2633 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 2634 { 2635 struct ksz_device *dev = ds->priv; 2636 struct ksz_port *p; 2637 const u16 *regs; 2638 u8 data; 2639 2640 regs = dev->info->regs; 2641 2642 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 2643 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2644 2645 p = &dev->ports[port]; 2646 2647 switch (state) { 2648 case BR_STATE_DISABLED: 2649 data |= PORT_LEARN_DISABLE; 2650 break; 2651 case BR_STATE_LISTENING: 2652 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2653 break; 2654 case BR_STATE_LEARNING: 2655 data |= PORT_RX_ENABLE; 2656 if (!p->learning) 2657 data |= PORT_LEARN_DISABLE; 2658 break; 2659 case BR_STATE_FORWARDING: 2660 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 2661 if (!p->learning) 2662 data |= PORT_LEARN_DISABLE; 2663 break; 2664 case BR_STATE_BLOCKING: 2665 data |= PORT_LEARN_DISABLE; 2666 break; 2667 default: 2668 dev_err(ds->dev, "invalid STP state: %d\n", state); 2669 return; 2670 } 2671 2672 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 2673 2674 p->stp_state = state; 2675 2676 ksz_update_port_member(dev, port); 2677 } 2678 2679 static void ksz_port_teardown(struct dsa_switch *ds, int port) 2680 { 2681 struct ksz_device *dev = ds->priv; 2682 2683 switch (dev->chip_id) { 2684 case KSZ8563_CHIP_ID: 2685 case KSZ8567_CHIP_ID: 2686 case KSZ9477_CHIP_ID: 2687 case KSZ9563_CHIP_ID: 2688 case KSZ9567_CHIP_ID: 2689 case KSZ9893_CHIP_ID: 2690 case KSZ9896_CHIP_ID: 2691 case KSZ9897_CHIP_ID: 2692 if (dsa_is_user_port(ds, port)) 2693 ksz9477_port_acl_free(dev, port); 2694 } 2695 } 2696 2697 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 2698 struct switchdev_brport_flags flags, 2699 struct netlink_ext_ack *extack) 2700 { 2701 if (flags.mask & ~BR_LEARNING) 2702 return -EINVAL; 2703 2704 return 0; 2705 } 2706 2707 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 2708 struct switchdev_brport_flags flags, 2709 struct netlink_ext_ack *extack) 2710 { 2711 struct ksz_device *dev = ds->priv; 2712 struct ksz_port *p = &dev->ports[port]; 2713 2714 if (flags.mask & BR_LEARNING) { 2715 p->learning = !!(flags.val & BR_LEARNING); 2716 2717 /* Make the change take effect immediately */ 2718 ksz_port_stp_state_set(ds, port, p->stp_state); 2719 } 2720 2721 return 0; 2722 } 2723 2724 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 2725 int port, 2726 enum dsa_tag_protocol mp) 2727 { 2728 struct ksz_device *dev = ds->priv; 2729 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 2730 2731 if (dev->chip_id == KSZ8795_CHIP_ID || 2732 dev->chip_id == KSZ8794_CHIP_ID || 2733 dev->chip_id == KSZ8765_CHIP_ID) 2734 proto = DSA_TAG_PROTO_KSZ8795; 2735 2736 if (dev->chip_id == KSZ8830_CHIP_ID || 2737 dev->chip_id == KSZ8563_CHIP_ID || 2738 dev->chip_id == KSZ9893_CHIP_ID || 2739 dev->chip_id == KSZ9563_CHIP_ID) 2740 proto = DSA_TAG_PROTO_KSZ9893; 2741 2742 if (dev->chip_id == KSZ8567_CHIP_ID || 2743 dev->chip_id == KSZ9477_CHIP_ID || 2744 dev->chip_id == KSZ9896_CHIP_ID || 2745 dev->chip_id == KSZ9897_CHIP_ID || 2746 dev->chip_id == KSZ9567_CHIP_ID) 2747 proto = DSA_TAG_PROTO_KSZ9477; 2748 2749 if (is_lan937x(dev)) 2750 proto = DSA_TAG_PROTO_LAN937X; 2751 2752 return proto; 2753 } 2754 2755 static int ksz_connect_tag_protocol(struct dsa_switch *ds, 2756 enum dsa_tag_protocol proto) 2757 { 2758 struct ksz_tagger_data *tagger_data; 2759 2760 switch (proto) { 2761 case DSA_TAG_PROTO_KSZ8795: 2762 return 0; 2763 case DSA_TAG_PROTO_KSZ9893: 2764 case DSA_TAG_PROTO_KSZ9477: 2765 case DSA_TAG_PROTO_LAN937X: 2766 tagger_data = ksz_tagger_data(ds); 2767 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 2768 return 0; 2769 default: 2770 return -EPROTONOSUPPORT; 2771 } 2772 } 2773 2774 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 2775 bool flag, struct netlink_ext_ack *extack) 2776 { 2777 struct ksz_device *dev = ds->priv; 2778 2779 if (!dev->dev_ops->vlan_filtering) 2780 return -EOPNOTSUPP; 2781 2782 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 2783 } 2784 2785 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 2786 const struct switchdev_obj_port_vlan *vlan, 2787 struct netlink_ext_ack *extack) 2788 { 2789 struct ksz_device *dev = ds->priv; 2790 2791 if (!dev->dev_ops->vlan_add) 2792 return -EOPNOTSUPP; 2793 2794 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 2795 } 2796 2797 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 2798 const struct switchdev_obj_port_vlan *vlan) 2799 { 2800 struct ksz_device *dev = ds->priv; 2801 2802 if (!dev->dev_ops->vlan_del) 2803 return -EOPNOTSUPP; 2804 2805 return dev->dev_ops->vlan_del(dev, port, vlan); 2806 } 2807 2808 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 2809 struct dsa_mall_mirror_tc_entry *mirror, 2810 bool ingress, struct netlink_ext_ack *extack) 2811 { 2812 struct ksz_device *dev = ds->priv; 2813 2814 if (!dev->dev_ops->mirror_add) 2815 return -EOPNOTSUPP; 2816 2817 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 2818 } 2819 2820 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 2821 struct dsa_mall_mirror_tc_entry *mirror) 2822 { 2823 struct ksz_device *dev = ds->priv; 2824 2825 if (dev->dev_ops->mirror_del) 2826 dev->dev_ops->mirror_del(dev, port, mirror); 2827 } 2828 2829 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 2830 { 2831 struct ksz_device *dev = ds->priv; 2832 2833 if (!dev->dev_ops->change_mtu) 2834 return -EOPNOTSUPP; 2835 2836 return dev->dev_ops->change_mtu(dev, port, mtu); 2837 } 2838 2839 static int ksz_max_mtu(struct dsa_switch *ds, int port) 2840 { 2841 struct ksz_device *dev = ds->priv; 2842 2843 switch (dev->chip_id) { 2844 case KSZ8795_CHIP_ID: 2845 case KSZ8794_CHIP_ID: 2846 case KSZ8765_CHIP_ID: 2847 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2848 case KSZ8830_CHIP_ID: 2849 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2850 case KSZ8563_CHIP_ID: 2851 case KSZ8567_CHIP_ID: 2852 case KSZ9477_CHIP_ID: 2853 case KSZ9563_CHIP_ID: 2854 case KSZ9567_CHIP_ID: 2855 case KSZ9893_CHIP_ID: 2856 case KSZ9896_CHIP_ID: 2857 case KSZ9897_CHIP_ID: 2858 case LAN9370_CHIP_ID: 2859 case LAN9371_CHIP_ID: 2860 case LAN9372_CHIP_ID: 2861 case LAN9373_CHIP_ID: 2862 case LAN9374_CHIP_ID: 2863 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2864 } 2865 2866 return -EOPNOTSUPP; 2867 } 2868 2869 static int ksz_validate_eee(struct dsa_switch *ds, int port) 2870 { 2871 struct ksz_device *dev = ds->priv; 2872 2873 if (!dev->info->internal_phy[port]) 2874 return -EOPNOTSUPP; 2875 2876 switch (dev->chip_id) { 2877 case KSZ8563_CHIP_ID: 2878 case KSZ8567_CHIP_ID: 2879 case KSZ9477_CHIP_ID: 2880 case KSZ9563_CHIP_ID: 2881 case KSZ9567_CHIP_ID: 2882 case KSZ9893_CHIP_ID: 2883 case KSZ9896_CHIP_ID: 2884 case KSZ9897_CHIP_ID: 2885 return 0; 2886 } 2887 2888 return -EOPNOTSUPP; 2889 } 2890 2891 static int ksz_get_mac_eee(struct dsa_switch *ds, int port, 2892 struct ethtool_keee *e) 2893 { 2894 int ret; 2895 2896 ret = ksz_validate_eee(ds, port); 2897 if (ret) 2898 return ret; 2899 2900 /* There is no documented control of Tx LPI configuration. */ 2901 e->tx_lpi_enabled = true; 2902 2903 /* There is no documented control of Tx LPI timer. According to tests 2904 * Tx LPI timer seems to be set by default to minimal value. 2905 */ 2906 e->tx_lpi_timer = 0; 2907 2908 return 0; 2909 } 2910 2911 static int ksz_set_mac_eee(struct dsa_switch *ds, int port, 2912 struct ethtool_keee *e) 2913 { 2914 struct ksz_device *dev = ds->priv; 2915 int ret; 2916 2917 ret = ksz_validate_eee(ds, port); 2918 if (ret) 2919 return ret; 2920 2921 if (!e->tx_lpi_enabled) { 2922 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 2923 return -EINVAL; 2924 } 2925 2926 if (e->tx_lpi_timer) { 2927 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 2928 return -EINVAL; 2929 } 2930 2931 return 0; 2932 } 2933 2934 static void ksz_set_xmii(struct ksz_device *dev, int port, 2935 phy_interface_t interface) 2936 { 2937 const u8 *bitval = dev->info->xmii_ctrl1; 2938 struct ksz_port *p = &dev->ports[port]; 2939 const u16 *regs = dev->info->regs; 2940 u8 data8; 2941 2942 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2943 2944 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 2945 P_RGMII_ID_EG_ENABLE); 2946 2947 switch (interface) { 2948 case PHY_INTERFACE_MODE_MII: 2949 data8 |= bitval[P_MII_SEL]; 2950 break; 2951 case PHY_INTERFACE_MODE_RMII: 2952 data8 |= bitval[P_RMII_SEL]; 2953 break; 2954 case PHY_INTERFACE_MODE_GMII: 2955 data8 |= bitval[P_GMII_SEL]; 2956 break; 2957 case PHY_INTERFACE_MODE_RGMII: 2958 case PHY_INTERFACE_MODE_RGMII_ID: 2959 case PHY_INTERFACE_MODE_RGMII_TXID: 2960 case PHY_INTERFACE_MODE_RGMII_RXID: 2961 data8 |= bitval[P_RGMII_SEL]; 2962 /* On KSZ9893, disable RGMII in-band status support */ 2963 if (dev->chip_id == KSZ9893_CHIP_ID || 2964 dev->chip_id == KSZ8563_CHIP_ID || 2965 dev->chip_id == KSZ9563_CHIP_ID) 2966 data8 &= ~P_MII_MAC_MODE; 2967 break; 2968 default: 2969 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 2970 phy_modes(interface), port); 2971 return; 2972 } 2973 2974 if (p->rgmii_tx_val) 2975 data8 |= P_RGMII_ID_EG_ENABLE; 2976 2977 if (p->rgmii_rx_val) 2978 data8 |= P_RGMII_ID_IG_ENABLE; 2979 2980 /* Write the updated value */ 2981 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2982 } 2983 2984 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 2985 { 2986 const u8 *bitval = dev->info->xmii_ctrl1; 2987 const u16 *regs = dev->info->regs; 2988 phy_interface_t interface; 2989 u8 data8; 2990 u8 val; 2991 2992 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2993 2994 val = FIELD_GET(P_MII_SEL_M, data8); 2995 2996 if (val == bitval[P_MII_SEL]) { 2997 if (gbit) 2998 interface = PHY_INTERFACE_MODE_GMII; 2999 else 3000 interface = PHY_INTERFACE_MODE_MII; 3001 } else if (val == bitval[P_RMII_SEL]) { 3002 interface = PHY_INTERFACE_MODE_RGMII; 3003 } else { 3004 interface = PHY_INTERFACE_MODE_RGMII; 3005 if (data8 & P_RGMII_ID_EG_ENABLE) 3006 interface = PHY_INTERFACE_MODE_RGMII_TXID; 3007 if (data8 & P_RGMII_ID_IG_ENABLE) { 3008 interface = PHY_INTERFACE_MODE_RGMII_RXID; 3009 if (data8 & P_RGMII_ID_EG_ENABLE) 3010 interface = PHY_INTERFACE_MODE_RGMII_ID; 3011 } 3012 } 3013 3014 return interface; 3015 } 3016 3017 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, 3018 unsigned int mode, 3019 const struct phylink_link_state *state) 3020 { 3021 struct ksz_device *dev = ds->priv; 3022 3023 if (ksz_is_ksz88x3(dev)) { 3024 dev->ports[port].manual_flow = !(state->pause & MLO_PAUSE_AN); 3025 return; 3026 } 3027 3028 /* Internal PHYs */ 3029 if (dev->info->internal_phy[port]) 3030 return; 3031 3032 if (phylink_autoneg_inband(mode)) { 3033 dev_err(dev->dev, "In-band AN not supported!\n"); 3034 return; 3035 } 3036 3037 ksz_set_xmii(dev, port, state->interface); 3038 3039 if (dev->dev_ops->phylink_mac_config) 3040 dev->dev_ops->phylink_mac_config(dev, port, mode, state); 3041 3042 if (dev->dev_ops->setup_rgmii_delay) 3043 dev->dev_ops->setup_rgmii_delay(dev, port); 3044 } 3045 3046 bool ksz_get_gbit(struct ksz_device *dev, int port) 3047 { 3048 const u8 *bitval = dev->info->xmii_ctrl1; 3049 const u16 *regs = dev->info->regs; 3050 bool gbit = false; 3051 u8 data8; 3052 bool val; 3053 3054 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3055 3056 val = FIELD_GET(P_GMII_1GBIT_M, data8); 3057 3058 if (val == bitval[P_GMII_1GBIT]) 3059 gbit = true; 3060 3061 return gbit; 3062 } 3063 3064 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 3065 { 3066 const u8 *bitval = dev->info->xmii_ctrl1; 3067 const u16 *regs = dev->info->regs; 3068 u8 data8; 3069 3070 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3071 3072 data8 &= ~P_GMII_1GBIT_M; 3073 3074 if (gbit) 3075 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 3076 else 3077 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 3078 3079 /* Write the updated value */ 3080 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3081 } 3082 3083 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 3084 { 3085 const u8 *bitval = dev->info->xmii_ctrl0; 3086 const u16 *regs = dev->info->regs; 3087 u8 data8; 3088 3089 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 3090 3091 data8 &= ~P_MII_100MBIT_M; 3092 3093 if (speed == SPEED_100) 3094 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 3095 else 3096 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 3097 3098 /* Write the updated value */ 3099 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 3100 } 3101 3102 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 3103 { 3104 if (speed == SPEED_1000) 3105 ksz_set_gbit(dev, port, true); 3106 else 3107 ksz_set_gbit(dev, port, false); 3108 3109 if (speed == SPEED_100 || speed == SPEED_10) 3110 ksz_set_100_10mbit(dev, port, speed); 3111 } 3112 3113 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 3114 bool tx_pause, bool rx_pause) 3115 { 3116 const u8 *bitval = dev->info->xmii_ctrl0; 3117 const u32 *masks = dev->info->masks; 3118 const u16 *regs = dev->info->regs; 3119 u8 mask; 3120 u8 val; 3121 3122 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 3123 masks[P_MII_RX_FLOW_CTRL]; 3124 3125 if (duplex == DUPLEX_FULL) 3126 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 3127 else 3128 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 3129 3130 if (tx_pause) 3131 val |= masks[P_MII_TX_FLOW_CTRL]; 3132 3133 if (rx_pause) 3134 val |= masks[P_MII_RX_FLOW_CTRL]; 3135 3136 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 3137 } 3138 3139 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 3140 unsigned int mode, 3141 phy_interface_t interface, 3142 struct phy_device *phydev, int speed, 3143 int duplex, bool tx_pause, 3144 bool rx_pause) 3145 { 3146 struct ksz_port *p; 3147 3148 p = &dev->ports[port]; 3149 3150 /* Internal PHYs */ 3151 if (dev->info->internal_phy[port]) 3152 return; 3153 3154 p->phydev.speed = speed; 3155 3156 ksz_port_set_xmii_speed(dev, port, speed); 3157 3158 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 3159 } 3160 3161 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, 3162 unsigned int mode, 3163 phy_interface_t interface, 3164 struct phy_device *phydev, int speed, 3165 int duplex, bool tx_pause, bool rx_pause) 3166 { 3167 struct ksz_device *dev = ds->priv; 3168 3169 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface, phydev, 3170 speed, duplex, tx_pause, rx_pause); 3171 } 3172 3173 static int ksz_switch_detect(struct ksz_device *dev) 3174 { 3175 u8 id1, id2, id4; 3176 u16 id16; 3177 u32 id32; 3178 int ret; 3179 3180 /* read chip id */ 3181 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 3182 if (ret) 3183 return ret; 3184 3185 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 3186 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 3187 3188 switch (id1) { 3189 case KSZ87_FAMILY_ID: 3190 if (id2 == KSZ87_CHIP_ID_95) { 3191 u8 val; 3192 3193 dev->chip_id = KSZ8795_CHIP_ID; 3194 3195 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 3196 if (val & KSZ8_PORT_FIBER_MODE) 3197 dev->chip_id = KSZ8765_CHIP_ID; 3198 } else if (id2 == KSZ87_CHIP_ID_94) { 3199 dev->chip_id = KSZ8794_CHIP_ID; 3200 } else { 3201 return -ENODEV; 3202 } 3203 break; 3204 case KSZ88_FAMILY_ID: 3205 if (id2 == KSZ88_CHIP_ID_63) 3206 dev->chip_id = KSZ8830_CHIP_ID; 3207 else 3208 return -ENODEV; 3209 break; 3210 default: 3211 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 3212 if (ret) 3213 return ret; 3214 3215 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 3216 id32 &= ~0xFF; 3217 3218 switch (id32) { 3219 case KSZ9477_CHIP_ID: 3220 case KSZ9896_CHIP_ID: 3221 case KSZ9897_CHIP_ID: 3222 case KSZ9567_CHIP_ID: 3223 case KSZ8567_CHIP_ID: 3224 case LAN9370_CHIP_ID: 3225 case LAN9371_CHIP_ID: 3226 case LAN9372_CHIP_ID: 3227 case LAN9373_CHIP_ID: 3228 case LAN9374_CHIP_ID: 3229 dev->chip_id = id32; 3230 break; 3231 case KSZ9893_CHIP_ID: 3232 ret = ksz_read8(dev, REG_CHIP_ID4, 3233 &id4); 3234 if (ret) 3235 return ret; 3236 3237 if (id4 == SKU_ID_KSZ8563) 3238 dev->chip_id = KSZ8563_CHIP_ID; 3239 else if (id4 == SKU_ID_KSZ9563) 3240 dev->chip_id = KSZ9563_CHIP_ID; 3241 else 3242 dev->chip_id = KSZ9893_CHIP_ID; 3243 3244 break; 3245 default: 3246 dev_err(dev->dev, 3247 "unsupported switch detected %x)\n", id32); 3248 return -ENODEV; 3249 } 3250 } 3251 return 0; 3252 } 3253 3254 static int ksz_cls_flower_add(struct dsa_switch *ds, int port, 3255 struct flow_cls_offload *cls, bool ingress) 3256 { 3257 struct ksz_device *dev = ds->priv; 3258 3259 switch (dev->chip_id) { 3260 case KSZ8563_CHIP_ID: 3261 case KSZ8567_CHIP_ID: 3262 case KSZ9477_CHIP_ID: 3263 case KSZ9563_CHIP_ID: 3264 case KSZ9567_CHIP_ID: 3265 case KSZ9893_CHIP_ID: 3266 case KSZ9896_CHIP_ID: 3267 case KSZ9897_CHIP_ID: 3268 return ksz9477_cls_flower_add(ds, port, cls, ingress); 3269 } 3270 3271 return -EOPNOTSUPP; 3272 } 3273 3274 static int ksz_cls_flower_del(struct dsa_switch *ds, int port, 3275 struct flow_cls_offload *cls, bool ingress) 3276 { 3277 struct ksz_device *dev = ds->priv; 3278 3279 switch (dev->chip_id) { 3280 case KSZ8563_CHIP_ID: 3281 case KSZ8567_CHIP_ID: 3282 case KSZ9477_CHIP_ID: 3283 case KSZ9563_CHIP_ID: 3284 case KSZ9567_CHIP_ID: 3285 case KSZ9893_CHIP_ID: 3286 case KSZ9896_CHIP_ID: 3287 case KSZ9897_CHIP_ID: 3288 return ksz9477_cls_flower_del(ds, port, cls, ingress); 3289 } 3290 3291 return -EOPNOTSUPP; 3292 } 3293 3294 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 3295 * is converted to Hex-decimal using the successive multiplication method. On 3296 * every step, integer part is taken and decimal part is carry forwarded. 3297 */ 3298 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 3299 { 3300 u32 cinc = 0; 3301 u32 txrate; 3302 u32 rate; 3303 u8 temp; 3304 u8 i; 3305 3306 txrate = idle_slope - send_slope; 3307 3308 if (!txrate) 3309 return -EINVAL; 3310 3311 rate = idle_slope; 3312 3313 /* 24 bit register */ 3314 for (i = 0; i < 6; i++) { 3315 rate = rate * 16; 3316 3317 temp = rate / txrate; 3318 3319 rate %= txrate; 3320 3321 cinc = ((cinc << 4) | temp); 3322 } 3323 3324 *bw = cinc; 3325 3326 return 0; 3327 } 3328 3329 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 3330 u8 shaper) 3331 { 3332 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 3333 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 3334 FIELD_PREP(MTI_SHAPING_M, shaper)); 3335 } 3336 3337 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 3338 struct tc_cbs_qopt_offload *qopt) 3339 { 3340 struct ksz_device *dev = ds->priv; 3341 int ret; 3342 u32 bw; 3343 3344 if (!dev->info->tc_cbs_supported) 3345 return -EOPNOTSUPP; 3346 3347 if (qopt->queue > dev->info->num_tx_queues) 3348 return -EINVAL; 3349 3350 /* Queue Selection */ 3351 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 3352 if (ret) 3353 return ret; 3354 3355 if (!qopt->enable) 3356 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3357 MTI_SHAPING_OFF); 3358 3359 /* High Credit */ 3360 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 3361 qopt->hicredit); 3362 if (ret) 3363 return ret; 3364 3365 /* Low Credit */ 3366 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 3367 qopt->locredit); 3368 if (ret) 3369 return ret; 3370 3371 /* Credit Increment Register */ 3372 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 3373 if (ret) 3374 return ret; 3375 3376 if (dev->dev_ops->tc_cbs_set_cinc) { 3377 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 3378 if (ret) 3379 return ret; 3380 } 3381 3382 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3383 MTI_SHAPING_SRP); 3384 } 3385 3386 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 3387 { 3388 int queue, ret; 3389 3390 /* Configuration will not take effect until the last Port Queue X 3391 * Egress Limit Control Register is written. 3392 */ 3393 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3394 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 3395 KSZ9477_OUT_RATE_NO_LIMIT); 3396 if (ret) 3397 return ret; 3398 } 3399 3400 return 0; 3401 } 3402 3403 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 3404 int band) 3405 { 3406 /* Compared to queues, bands prioritize packets differently. In strict 3407 * priority mode, the lowest priority is assigned to Queue 0 while the 3408 * highest priority is given to Band 0. 3409 */ 3410 return p->bands - 1 - band; 3411 } 3412 3413 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 3414 { 3415 int ret; 3416 3417 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3418 if (ret) 3419 return ret; 3420 3421 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3422 MTI_SHAPING_OFF); 3423 } 3424 3425 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 3426 int weight) 3427 { 3428 int ret; 3429 3430 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3431 if (ret) 3432 return ret; 3433 3434 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3435 MTI_SHAPING_OFF); 3436 if (ret) 3437 return ret; 3438 3439 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 3440 } 3441 3442 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 3443 struct tc_ets_qopt_offload_replace_params *p) 3444 { 3445 int ret, band, tc_prio; 3446 u32 queue_map = 0; 3447 3448 /* In order to ensure proper prioritization, it is necessary to set the 3449 * rate limit for the related queue to zero. Otherwise strict priority 3450 * or WRR mode will not work. This is a hardware limitation. 3451 */ 3452 ret = ksz_disable_egress_rate_limit(dev, port); 3453 if (ret) 3454 return ret; 3455 3456 /* Configure queue scheduling mode for all bands. Currently only strict 3457 * prio mode is supported. 3458 */ 3459 for (band = 0; band < p->bands; band++) { 3460 int queue = ksz_ets_band_to_queue(p, band); 3461 3462 ret = ksz_queue_set_strict(dev, port, queue); 3463 if (ret) 3464 return ret; 3465 } 3466 3467 /* Configure the mapping between traffic classes and queues. Note: 3468 * priomap variable support 16 traffic classes, but the chip can handle 3469 * only 8 classes. 3470 */ 3471 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 3472 int queue; 3473 3474 if (tc_prio > KSZ9477_MAX_TC_PRIO) 3475 break; 3476 3477 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 3478 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3479 } 3480 3481 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3482 } 3483 3484 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 3485 { 3486 int ret, queue, tc_prio, s; 3487 u32 queue_map = 0; 3488 3489 /* To restore the default chip configuration, set all queues to use the 3490 * WRR scheduler with a weight of 1. 3491 */ 3492 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3493 ret = ksz_queue_set_wrr(dev, port, queue, 3494 KSZ9477_DEFAULT_WRR_WEIGHT); 3495 if (ret) 3496 return ret; 3497 } 3498 3499 switch (dev->info->num_tx_queues) { 3500 case 2: 3501 s = 2; 3502 break; 3503 case 4: 3504 s = 1; 3505 break; 3506 case 8: 3507 s = 0; 3508 break; 3509 default: 3510 return -EINVAL; 3511 } 3512 3513 /* Revert the queue mapping for TC-priority to its default setting on 3514 * the chip. 3515 */ 3516 for (tc_prio = 0; tc_prio <= KSZ9477_MAX_TC_PRIO; tc_prio++) { 3517 int queue; 3518 3519 queue = tc_prio >> s; 3520 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3521 } 3522 3523 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3524 } 3525 3526 static int ksz_tc_ets_validate(struct ksz_device *dev, int port, 3527 struct tc_ets_qopt_offload_replace_params *p) 3528 { 3529 int band; 3530 3531 /* Since it is not feasible to share one port among multiple qdisc, 3532 * the user must configure all available queues appropriately. 3533 */ 3534 if (p->bands != dev->info->num_tx_queues) { 3535 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 3536 dev->info->num_tx_queues); 3537 return -EOPNOTSUPP; 3538 } 3539 3540 for (band = 0; band < p->bands; ++band) { 3541 /* The KSZ switches utilize a weighted round robin configuration 3542 * where a certain number of packets can be transmitted from a 3543 * queue before the next queue is serviced. For more information 3544 * on this, refer to section 5.2.8.4 of the KSZ8565R 3545 * documentation on the Port Transmit Queue Control 1 Register. 3546 * However, the current ETS Qdisc implementation (as of February 3547 * 2023) assigns a weight to each queue based on the number of 3548 * bytes or extrapolated bandwidth in percentages. Since this 3549 * differs from the KSZ switches' method and we don't want to 3550 * fake support by converting bytes to packets, it is better to 3551 * return an error instead. 3552 */ 3553 if (p->quanta[band]) { 3554 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 3555 return -EOPNOTSUPP; 3556 } 3557 } 3558 3559 return 0; 3560 } 3561 3562 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 3563 struct tc_ets_qopt_offload *qopt) 3564 { 3565 struct ksz_device *dev = ds->priv; 3566 int ret; 3567 3568 if (!dev->info->tc_ets_supported) 3569 return -EOPNOTSUPP; 3570 3571 if (qopt->parent != TC_H_ROOT) { 3572 dev_err(dev->dev, "Parent should be \"root\"\n"); 3573 return -EOPNOTSUPP; 3574 } 3575 3576 switch (qopt->command) { 3577 case TC_ETS_REPLACE: 3578 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 3579 if (ret) 3580 return ret; 3581 3582 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 3583 case TC_ETS_DESTROY: 3584 return ksz_tc_ets_del(dev, port); 3585 case TC_ETS_STATS: 3586 case TC_ETS_GRAFT: 3587 return -EOPNOTSUPP; 3588 } 3589 3590 return -EOPNOTSUPP; 3591 } 3592 3593 static int ksz_setup_tc(struct dsa_switch *ds, int port, 3594 enum tc_setup_type type, void *type_data) 3595 { 3596 switch (type) { 3597 case TC_SETUP_QDISC_CBS: 3598 return ksz_setup_tc_cbs(ds, port, type_data); 3599 case TC_SETUP_QDISC_ETS: 3600 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 3601 default: 3602 return -EOPNOTSUPP; 3603 } 3604 } 3605 3606 static void ksz_get_wol(struct dsa_switch *ds, int port, 3607 struct ethtool_wolinfo *wol) 3608 { 3609 struct ksz_device *dev = ds->priv; 3610 3611 if (dev->dev_ops->get_wol) 3612 dev->dev_ops->get_wol(dev, port, wol); 3613 } 3614 3615 static int ksz_set_wol(struct dsa_switch *ds, int port, 3616 struct ethtool_wolinfo *wol) 3617 { 3618 struct ksz_device *dev = ds->priv; 3619 3620 if (dev->dev_ops->set_wol) 3621 return dev->dev_ops->set_wol(dev, port, wol); 3622 3623 return -EOPNOTSUPP; 3624 } 3625 3626 static int ksz_port_set_mac_address(struct dsa_switch *ds, int port, 3627 const unsigned char *addr) 3628 { 3629 struct dsa_port *dp = dsa_to_port(ds, port); 3630 struct ethtool_wolinfo wol; 3631 3632 if (dp->hsr_dev) { 3633 dev_err(ds->dev, 3634 "Cannot change MAC address on port %d with active HSR offload\n", 3635 port); 3636 return -EBUSY; 3637 } 3638 3639 ksz_get_wol(ds, dp->index, &wol); 3640 if (wol.wolopts & WAKE_MAGIC) { 3641 dev_err(ds->dev, 3642 "Cannot change MAC address on port %d with active Wake on Magic Packet\n", 3643 port); 3644 return -EBUSY; 3645 } 3646 3647 return 0; 3648 } 3649 3650 /** 3651 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port 3652 * can be used as a global address. 3653 * @ds: Pointer to the DSA switch structure. 3654 * @port: The port number on which the MAC address is to be checked. 3655 * 3656 * This function examines the MAC address set on the specified port and 3657 * determines if it can be used as a global address for the switch. 3658 * 3659 * Return: true if the port's MAC address can be used as a global address, false 3660 * otherwise. 3661 */ 3662 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port) 3663 { 3664 struct net_device *user = dsa_to_port(ds, port)->user; 3665 const unsigned char *addr = user->dev_addr; 3666 struct ksz_switch_macaddr *switch_macaddr; 3667 struct ksz_device *dev = ds->priv; 3668 3669 ASSERT_RTNL(); 3670 3671 switch_macaddr = dev->switch_macaddr; 3672 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr)) 3673 return false; 3674 3675 return true; 3676 } 3677 3678 /** 3679 * ksz_switch_macaddr_get - Program the switch's MAC address register. 3680 * @ds: DSA switch instance. 3681 * @port: Port number. 3682 * @extack: Netlink extended acknowledgment. 3683 * 3684 * This function programs the switch's MAC address register with the MAC address 3685 * of the requesting user port. This single address is used by the switch for 3686 * multiple features like HSR self-address filtering and WoL. Other user ports 3687 * can share ownership of this address as long as their MAC address is the same. 3688 * The MAC addresses of user ports must not change while they have ownership of 3689 * the switch MAC address. 3690 * 3691 * Return: 0 on success, or other error codes on failure. 3692 */ 3693 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 3694 struct netlink_ext_ack *extack) 3695 { 3696 struct net_device *user = dsa_to_port(ds, port)->user; 3697 const unsigned char *addr = user->dev_addr; 3698 struct ksz_switch_macaddr *switch_macaddr; 3699 struct ksz_device *dev = ds->priv; 3700 const u16 *regs = dev->info->regs; 3701 int i, ret; 3702 3703 /* Make sure concurrent MAC address changes are blocked */ 3704 ASSERT_RTNL(); 3705 3706 switch_macaddr = dev->switch_macaddr; 3707 if (switch_macaddr) { 3708 if (!ether_addr_equal(switch_macaddr->addr, addr)) { 3709 NL_SET_ERR_MSG_FMT_MOD(extack, 3710 "Switch already configured for MAC address %pM", 3711 switch_macaddr->addr); 3712 return -EBUSY; 3713 } 3714 3715 refcount_inc(&switch_macaddr->refcount); 3716 return 0; 3717 } 3718 3719 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL); 3720 if (!switch_macaddr) 3721 return -ENOMEM; 3722 3723 ether_addr_copy(switch_macaddr->addr, addr); 3724 refcount_set(&switch_macaddr->refcount, 1); 3725 dev->switch_macaddr = switch_macaddr; 3726 3727 /* Program the switch MAC address to hardware */ 3728 for (i = 0; i < ETH_ALEN; i++) { 3729 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, addr[i]); 3730 if (ret) 3731 goto macaddr_drop; 3732 } 3733 3734 return 0; 3735 3736 macaddr_drop: 3737 dev->switch_macaddr = NULL; 3738 refcount_set(&switch_macaddr->refcount, 0); 3739 kfree(switch_macaddr); 3740 3741 return ret; 3742 } 3743 3744 void ksz_switch_macaddr_put(struct dsa_switch *ds) 3745 { 3746 struct ksz_switch_macaddr *switch_macaddr; 3747 struct ksz_device *dev = ds->priv; 3748 const u16 *regs = dev->info->regs; 3749 int i; 3750 3751 /* Make sure concurrent MAC address changes are blocked */ 3752 ASSERT_RTNL(); 3753 3754 switch_macaddr = dev->switch_macaddr; 3755 if (!refcount_dec_and_test(&switch_macaddr->refcount)) 3756 return; 3757 3758 for (i = 0; i < ETH_ALEN; i++) 3759 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0); 3760 3761 dev->switch_macaddr = NULL; 3762 kfree(switch_macaddr); 3763 } 3764 3765 static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr, 3766 struct netlink_ext_ack *extack) 3767 { 3768 struct ksz_device *dev = ds->priv; 3769 enum hsr_version ver; 3770 int ret; 3771 3772 ret = hsr_get_version(hsr, &ver); 3773 if (ret) 3774 return ret; 3775 3776 if (dev->chip_id != KSZ9477_CHIP_ID) { 3777 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload"); 3778 return -EOPNOTSUPP; 3779 } 3780 3781 /* KSZ9477 can support HW offloading of only 1 HSR device */ 3782 if (dev->hsr_dev && hsr != dev->hsr_dev) { 3783 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR"); 3784 return -EOPNOTSUPP; 3785 } 3786 3787 /* KSZ9477 only supports HSR v0 and v1 */ 3788 if (!(ver == HSR_V0 || ver == HSR_V1)) { 3789 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported"); 3790 return -EOPNOTSUPP; 3791 } 3792 3793 /* Self MAC address filtering, to avoid frames traversing 3794 * the HSR ring more than once. 3795 */ 3796 ret = ksz_switch_macaddr_get(ds, port, extack); 3797 if (ret) 3798 return ret; 3799 3800 ksz9477_hsr_join(ds, port, hsr); 3801 dev->hsr_dev = hsr; 3802 dev->hsr_ports |= BIT(port); 3803 3804 return 0; 3805 } 3806 3807 static int ksz_hsr_leave(struct dsa_switch *ds, int port, 3808 struct net_device *hsr) 3809 { 3810 struct ksz_device *dev = ds->priv; 3811 3812 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID); 3813 3814 ksz9477_hsr_leave(ds, port, hsr); 3815 dev->hsr_ports &= ~BIT(port); 3816 if (!dev->hsr_ports) 3817 dev->hsr_dev = NULL; 3818 3819 ksz_switch_macaddr_put(ds); 3820 3821 return 0; 3822 } 3823 3824 static const struct dsa_switch_ops ksz_switch_ops = { 3825 .get_tag_protocol = ksz_get_tag_protocol, 3826 .connect_tag_protocol = ksz_connect_tag_protocol, 3827 .get_phy_flags = ksz_get_phy_flags, 3828 .setup = ksz_setup, 3829 .teardown = ksz_teardown, 3830 .phy_read = ksz_phy_read16, 3831 .phy_write = ksz_phy_write16, 3832 .phylink_get_caps = ksz_phylink_get_caps, 3833 .phylink_mac_config = ksz_phylink_mac_config, 3834 .phylink_mac_link_up = ksz_phylink_mac_link_up, 3835 .phylink_mac_link_down = ksz_mac_link_down, 3836 .port_setup = ksz_port_setup, 3837 .set_ageing_time = ksz_set_ageing_time, 3838 .get_strings = ksz_get_strings, 3839 .get_ethtool_stats = ksz_get_ethtool_stats, 3840 .get_sset_count = ksz_sset_count, 3841 .port_bridge_join = ksz_port_bridge_join, 3842 .port_bridge_leave = ksz_port_bridge_leave, 3843 .port_hsr_join = ksz_hsr_join, 3844 .port_hsr_leave = ksz_hsr_leave, 3845 .port_set_mac_address = ksz_port_set_mac_address, 3846 .port_stp_state_set = ksz_port_stp_state_set, 3847 .port_teardown = ksz_port_teardown, 3848 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 3849 .port_bridge_flags = ksz_port_bridge_flags, 3850 .port_fast_age = ksz_port_fast_age, 3851 .port_vlan_filtering = ksz_port_vlan_filtering, 3852 .port_vlan_add = ksz_port_vlan_add, 3853 .port_vlan_del = ksz_port_vlan_del, 3854 .port_fdb_dump = ksz_port_fdb_dump, 3855 .port_fdb_add = ksz_port_fdb_add, 3856 .port_fdb_del = ksz_port_fdb_del, 3857 .port_mdb_add = ksz_port_mdb_add, 3858 .port_mdb_del = ksz_port_mdb_del, 3859 .port_mirror_add = ksz_port_mirror_add, 3860 .port_mirror_del = ksz_port_mirror_del, 3861 .get_stats64 = ksz_get_stats64, 3862 .get_pause_stats = ksz_get_pause_stats, 3863 .port_change_mtu = ksz_change_mtu, 3864 .port_max_mtu = ksz_max_mtu, 3865 .get_wol = ksz_get_wol, 3866 .set_wol = ksz_set_wol, 3867 .get_ts_info = ksz_get_ts_info, 3868 .port_hwtstamp_get = ksz_hwtstamp_get, 3869 .port_hwtstamp_set = ksz_hwtstamp_set, 3870 .port_txtstamp = ksz_port_txtstamp, 3871 .port_rxtstamp = ksz_port_rxtstamp, 3872 .cls_flower_add = ksz_cls_flower_add, 3873 .cls_flower_del = ksz_cls_flower_del, 3874 .port_setup_tc = ksz_setup_tc, 3875 .get_mac_eee = ksz_get_mac_eee, 3876 .set_mac_eee = ksz_set_mac_eee, 3877 }; 3878 3879 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 3880 { 3881 struct dsa_switch *ds; 3882 struct ksz_device *swdev; 3883 3884 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 3885 if (!ds) 3886 return NULL; 3887 3888 ds->dev = base; 3889 ds->num_ports = DSA_MAX_PORTS; 3890 ds->ops = &ksz_switch_ops; 3891 3892 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 3893 if (!swdev) 3894 return NULL; 3895 3896 ds->priv = swdev; 3897 swdev->dev = base; 3898 3899 swdev->ds = ds; 3900 swdev->priv = priv; 3901 3902 return swdev; 3903 } 3904 EXPORT_SYMBOL(ksz_switch_alloc); 3905 3906 /** 3907 * ksz_switch_shutdown - Shutdown routine for the switch device. 3908 * @dev: The switch device structure. 3909 * 3910 * This function is responsible for initiating a shutdown sequence for the 3911 * switch device. It invokes the reset operation defined in the device 3912 * operations, if available, to reset the switch. Subsequently, it calls the 3913 * DSA framework's shutdown function to ensure a proper shutdown of the DSA 3914 * switch. 3915 */ 3916 void ksz_switch_shutdown(struct ksz_device *dev) 3917 { 3918 bool wol_enabled = false; 3919 3920 if (dev->dev_ops->wol_pre_shutdown) 3921 dev->dev_ops->wol_pre_shutdown(dev, &wol_enabled); 3922 3923 if (dev->dev_ops->reset && !wol_enabled) 3924 dev->dev_ops->reset(dev); 3925 3926 dsa_switch_shutdown(dev->ds); 3927 } 3928 EXPORT_SYMBOL(ksz_switch_shutdown); 3929 3930 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 3931 struct device_node *port_dn) 3932 { 3933 phy_interface_t phy_mode = dev->ports[port_num].interface; 3934 int rx_delay = -1, tx_delay = -1; 3935 3936 if (!phy_interface_mode_is_rgmii(phy_mode)) 3937 return; 3938 3939 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 3940 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 3941 3942 if (rx_delay == -1 && tx_delay == -1) { 3943 dev_warn(dev->dev, 3944 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 3945 "please update device tree to specify \"rx-internal-delay-ps\" and " 3946 "\"tx-internal-delay-ps\"", 3947 port_num); 3948 3949 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 3950 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 3951 rx_delay = 2000; 3952 3953 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 3954 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 3955 tx_delay = 2000; 3956 } 3957 3958 if (rx_delay < 0) 3959 rx_delay = 0; 3960 if (tx_delay < 0) 3961 tx_delay = 0; 3962 3963 dev->ports[port_num].rgmii_rx_val = rx_delay; 3964 dev->ports[port_num].rgmii_tx_val = tx_delay; 3965 } 3966 3967 /** 3968 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding 3969 * register value. 3970 * @array: The array of drive strength values to search. 3971 * @array_size: The size of the array. 3972 * @microamp: The drive strength value in microamp to be converted. 3973 * 3974 * This function searches the array of drive strength values for the given 3975 * microamp value and returns the corresponding register value for that drive. 3976 * 3977 * Returns: If found, the corresponding register value for that drive strength 3978 * is returned. Otherwise, -EINVAL is returned indicating an invalid value. 3979 */ 3980 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array, 3981 size_t array_size, int microamp) 3982 { 3983 int i; 3984 3985 for (i = 0; i < array_size; i++) { 3986 if (array[i].microamp == microamp) 3987 return array[i].reg_val; 3988 } 3989 3990 return -EINVAL; 3991 } 3992 3993 /** 3994 * ksz_drive_strength_error() - Report invalid drive strength value 3995 * @dev: ksz device 3996 * @array: The array of drive strength values to search. 3997 * @array_size: The size of the array. 3998 * @microamp: Invalid drive strength value in microamp 3999 * 4000 * This function logs an error message when an unsupported drive strength value 4001 * is detected. It lists out all the supported drive strength values for 4002 * reference in the error message. 4003 */ 4004 static void ksz_drive_strength_error(struct ksz_device *dev, 4005 const struct ksz_drive_strength *array, 4006 size_t array_size, int microamp) 4007 { 4008 char supported_values[100]; 4009 size_t remaining_size; 4010 int added_len; 4011 char *ptr; 4012 int i; 4013 4014 remaining_size = sizeof(supported_values); 4015 ptr = supported_values; 4016 4017 for (i = 0; i < array_size; i++) { 4018 added_len = snprintf(ptr, remaining_size, 4019 i == 0 ? "%d" : ", %d", array[i].microamp); 4020 4021 if (added_len >= remaining_size) 4022 break; 4023 4024 ptr += added_len; 4025 remaining_size -= added_len; 4026 } 4027 4028 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n", 4029 microamp, supported_values); 4030 } 4031 4032 /** 4033 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477 4034 * chip variants. 4035 * @dev: ksz device 4036 * @props: Array of drive strength properties to be applied 4037 * @num_props: Number of properties in the array 4038 * 4039 * This function configures the drive strength for various KSZ9477 chip variants 4040 * based on the provided properties. It handles chip-specific nuances and 4041 * ensures only valid drive strengths are written to the respective chip. 4042 * 4043 * Return: 0 on successful configuration, a negative error code on failure. 4044 */ 4045 static int ksz9477_drive_strength_write(struct ksz_device *dev, 4046 struct ksz_driver_strength_prop *props, 4047 int num_props) 4048 { 4049 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths); 4050 int i, ret, reg; 4051 u8 mask = 0; 4052 u8 val = 0; 4053 4054 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1) 4055 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4056 props[KSZ_DRIVER_STRENGTH_IO].name); 4057 4058 if (dev->chip_id == KSZ8795_CHIP_ID || 4059 dev->chip_id == KSZ8794_CHIP_ID || 4060 dev->chip_id == KSZ8765_CHIP_ID) 4061 reg = KSZ8795_REG_SW_CTRL_20; 4062 else 4063 reg = KSZ9477_REG_SW_IO_STRENGTH; 4064 4065 for (i = 0; i < num_props; i++) { 4066 if (props[i].value == -1) 4067 continue; 4068 4069 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths, 4070 array_size, props[i].value); 4071 if (ret < 0) { 4072 ksz_drive_strength_error(dev, ksz9477_drive_strengths, 4073 array_size, props[i].value); 4074 return ret; 4075 } 4076 4077 mask |= SW_DRIVE_STRENGTH_M << props[i].offset; 4078 val |= ret << props[i].offset; 4079 } 4080 4081 return ksz_rmw8(dev, reg, mask, val); 4082 } 4083 4084 /** 4085 * ksz8830_drive_strength_write() - Set the drive strength configuration for 4086 * KSZ8830 compatible chip variants. 4087 * @dev: ksz device 4088 * @props: Array of drive strength properties to be set 4089 * @num_props: Number of properties in the array 4090 * 4091 * This function applies the specified drive strength settings to KSZ8830 chip 4092 * variants (KSZ8873, KSZ8863). 4093 * It ensures the configurations align with what the chip variant supports and 4094 * warns or errors out on unsupported settings. 4095 * 4096 * Return: 0 on success, error code otherwise 4097 */ 4098 static int ksz8830_drive_strength_write(struct ksz_device *dev, 4099 struct ksz_driver_strength_prop *props, 4100 int num_props) 4101 { 4102 size_t array_size = ARRAY_SIZE(ksz8830_drive_strengths); 4103 int microamp; 4104 int i, ret; 4105 4106 for (i = 0; i < num_props; i++) { 4107 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO) 4108 continue; 4109 4110 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4111 props[i].name); 4112 } 4113 4114 microamp = props[KSZ_DRIVER_STRENGTH_IO].value; 4115 ret = ksz_drive_strength_to_reg(ksz8830_drive_strengths, array_size, 4116 microamp); 4117 if (ret < 0) { 4118 ksz_drive_strength_error(dev, ksz8830_drive_strengths, 4119 array_size, microamp); 4120 return ret; 4121 } 4122 4123 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12, 4124 KSZ8873_DRIVE_STRENGTH_16MA, ret); 4125 } 4126 4127 /** 4128 * ksz_parse_drive_strength() - Extract and apply drive strength configurations 4129 * from device tree properties. 4130 * @dev: ksz device 4131 * 4132 * This function reads the specified drive strength properties from the 4133 * device tree, validates against the supported chip variants, and sets 4134 * them accordingly. An error should be critical here, as the drive strength 4135 * settings are crucial for EMI compliance. 4136 * 4137 * Return: 0 on success, error code otherwise 4138 */ 4139 static int ksz_parse_drive_strength(struct ksz_device *dev) 4140 { 4141 struct ksz_driver_strength_prop of_props[] = { 4142 [KSZ_DRIVER_STRENGTH_HI] = { 4143 .name = "microchip,hi-drive-strength-microamp", 4144 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S, 4145 .value = -1, 4146 }, 4147 [KSZ_DRIVER_STRENGTH_LO] = { 4148 .name = "microchip,lo-drive-strength-microamp", 4149 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S, 4150 .value = -1, 4151 }, 4152 [KSZ_DRIVER_STRENGTH_IO] = { 4153 .name = "microchip,io-drive-strength-microamp", 4154 .offset = 0, /* don't care */ 4155 .value = -1, 4156 }, 4157 }; 4158 struct device_node *np = dev->dev->of_node; 4159 bool have_any_prop = false; 4160 int i, ret; 4161 4162 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4163 ret = of_property_read_u32(np, of_props[i].name, 4164 &of_props[i].value); 4165 if (ret && ret != -EINVAL) 4166 dev_warn(dev->dev, "Failed to read %s\n", 4167 of_props[i].name); 4168 if (ret) 4169 continue; 4170 4171 have_any_prop = true; 4172 } 4173 4174 if (!have_any_prop) 4175 return 0; 4176 4177 switch (dev->chip_id) { 4178 case KSZ8830_CHIP_ID: 4179 return ksz8830_drive_strength_write(dev, of_props, 4180 ARRAY_SIZE(of_props)); 4181 case KSZ8795_CHIP_ID: 4182 case KSZ8794_CHIP_ID: 4183 case KSZ8765_CHIP_ID: 4184 case KSZ8563_CHIP_ID: 4185 case KSZ8567_CHIP_ID: 4186 case KSZ9477_CHIP_ID: 4187 case KSZ9563_CHIP_ID: 4188 case KSZ9567_CHIP_ID: 4189 case KSZ9893_CHIP_ID: 4190 case KSZ9896_CHIP_ID: 4191 case KSZ9897_CHIP_ID: 4192 return ksz9477_drive_strength_write(dev, of_props, 4193 ARRAY_SIZE(of_props)); 4194 default: 4195 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4196 if (of_props[i].value == -1) 4197 continue; 4198 4199 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4200 of_props[i].name); 4201 } 4202 } 4203 4204 return 0; 4205 } 4206 4207 int ksz_switch_register(struct ksz_device *dev) 4208 { 4209 const struct ksz_chip_data *info; 4210 struct device_node *port, *ports; 4211 phy_interface_t interface; 4212 unsigned int port_num; 4213 int ret; 4214 int i; 4215 4216 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 4217 GPIOD_OUT_LOW); 4218 if (IS_ERR(dev->reset_gpio)) 4219 return PTR_ERR(dev->reset_gpio); 4220 4221 if (dev->reset_gpio) { 4222 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4223 usleep_range(10000, 12000); 4224 gpiod_set_value_cansleep(dev->reset_gpio, 0); 4225 msleep(100); 4226 } 4227 4228 mutex_init(&dev->dev_mutex); 4229 mutex_init(&dev->regmap_mutex); 4230 mutex_init(&dev->alu_mutex); 4231 mutex_init(&dev->vlan_mutex); 4232 4233 ret = ksz_switch_detect(dev); 4234 if (ret) 4235 return ret; 4236 4237 info = ksz_lookup_info(dev->chip_id); 4238 if (!info) 4239 return -ENODEV; 4240 4241 /* Update the compatible info with the probed one */ 4242 dev->info = info; 4243 4244 dev_info(dev->dev, "found switch: %s, rev %i\n", 4245 dev->info->dev_name, dev->chip_rev); 4246 4247 ret = ksz_check_device_id(dev); 4248 if (ret) 4249 return ret; 4250 4251 dev->dev_ops = dev->info->ops; 4252 4253 ret = dev->dev_ops->init(dev); 4254 if (ret) 4255 return ret; 4256 4257 dev->ports = devm_kzalloc(dev->dev, 4258 dev->info->port_cnt * sizeof(struct ksz_port), 4259 GFP_KERNEL); 4260 if (!dev->ports) 4261 return -ENOMEM; 4262 4263 for (i = 0; i < dev->info->port_cnt; i++) { 4264 spin_lock_init(&dev->ports[i].mib.stats64_lock); 4265 mutex_init(&dev->ports[i].mib.cnt_mutex); 4266 dev->ports[i].mib.counters = 4267 devm_kzalloc(dev->dev, 4268 sizeof(u64) * (dev->info->mib_cnt + 1), 4269 GFP_KERNEL); 4270 if (!dev->ports[i].mib.counters) 4271 return -ENOMEM; 4272 4273 dev->ports[i].ksz_dev = dev; 4274 dev->ports[i].num = i; 4275 } 4276 4277 /* set the real number of ports */ 4278 dev->ds->num_ports = dev->info->port_cnt; 4279 4280 /* Host port interface will be self detected, or specifically set in 4281 * device tree. 4282 */ 4283 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 4284 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 4285 if (dev->dev->of_node) { 4286 ret = ksz_parse_drive_strength(dev); 4287 if (ret) 4288 return ret; 4289 4290 ret = of_get_phy_mode(dev->dev->of_node, &interface); 4291 if (ret == 0) 4292 dev->compat_interface = interface; 4293 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 4294 if (!ports) 4295 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 4296 if (ports) { 4297 for_each_available_child_of_node(ports, port) { 4298 if (of_property_read_u32(port, "reg", 4299 &port_num)) 4300 continue; 4301 if (!(dev->port_mask & BIT(port_num))) { 4302 of_node_put(port); 4303 of_node_put(ports); 4304 return -EINVAL; 4305 } 4306 of_get_phy_mode(port, 4307 &dev->ports[port_num].interface); 4308 4309 ksz_parse_rgmii_delay(dev, port_num, port); 4310 } 4311 of_node_put(ports); 4312 } 4313 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 4314 "microchip,synclko-125"); 4315 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 4316 "microchip,synclko-disable"); 4317 if (dev->synclko_125 && dev->synclko_disable) { 4318 dev_err(dev->dev, "inconsistent synclko settings\n"); 4319 return -EINVAL; 4320 } 4321 4322 dev->wakeup_source = of_property_read_bool(dev->dev->of_node, 4323 "wakeup-source"); 4324 } 4325 4326 ret = dsa_register_switch(dev->ds); 4327 if (ret) { 4328 dev->dev_ops->exit(dev); 4329 return ret; 4330 } 4331 4332 /* Read MIB counters every 30 seconds to avoid overflow. */ 4333 dev->mib_read_interval = msecs_to_jiffies(5000); 4334 4335 /* Start the MIB timer. */ 4336 schedule_delayed_work(&dev->mib_read, 0); 4337 4338 return ret; 4339 } 4340 EXPORT_SYMBOL(ksz_switch_register); 4341 4342 void ksz_switch_remove(struct ksz_device *dev) 4343 { 4344 /* timer started */ 4345 if (dev->mib_read_interval) { 4346 dev->mib_read_interval = 0; 4347 cancel_delayed_work_sync(&dev->mib_read); 4348 } 4349 4350 dev->dev_ops->exit(dev); 4351 dsa_unregister_switch(dev->ds); 4352 4353 if (dev->reset_gpio) 4354 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4355 4356 } 4357 EXPORT_SYMBOL(ksz_switch_remove); 4358 4359 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 4360 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 4361 MODULE_LICENSE("GPL"); 4362