1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2024 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/if_hsr.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/of.h> 23 #include <linux/of_mdio.h> 24 #include <linux/of_net.h> 25 #include <linux/micrel_phy.h> 26 #include <net/dsa.h> 27 #include <net/ieee8021q.h> 28 #include <net/pkt_cls.h> 29 #include <net/switchdev.h> 30 31 #include "ksz_common.h" 32 #include "ksz_dcb.h" 33 #include "ksz_ptp.h" 34 #include "ksz8.h" 35 #include "ksz9477.h" 36 #include "lan937x.h" 37 38 #define MIB_COUNTER_NUM 0x20 39 40 struct ksz_stats_raw { 41 u64 rx_hi; 42 u64 rx_undersize; 43 u64 rx_fragments; 44 u64 rx_oversize; 45 u64 rx_jabbers; 46 u64 rx_symbol_err; 47 u64 rx_crc_err; 48 u64 rx_align_err; 49 u64 rx_mac_ctrl; 50 u64 rx_pause; 51 u64 rx_bcast; 52 u64 rx_mcast; 53 u64 rx_ucast; 54 u64 rx_64_or_less; 55 u64 rx_65_127; 56 u64 rx_128_255; 57 u64 rx_256_511; 58 u64 rx_512_1023; 59 u64 rx_1024_1522; 60 u64 rx_1523_2000; 61 u64 rx_2001; 62 u64 tx_hi; 63 u64 tx_late_col; 64 u64 tx_pause; 65 u64 tx_bcast; 66 u64 tx_mcast; 67 u64 tx_ucast; 68 u64 tx_deferred; 69 u64 tx_total_col; 70 u64 tx_exc_col; 71 u64 tx_single_col; 72 u64 tx_mult_col; 73 u64 rx_total; 74 u64 tx_total; 75 u64 rx_discards; 76 u64 tx_discards; 77 }; 78 79 struct ksz88xx_stats_raw { 80 u64 rx; 81 u64 rx_hi; 82 u64 rx_undersize; 83 u64 rx_fragments; 84 u64 rx_oversize; 85 u64 rx_jabbers; 86 u64 rx_symbol_err; 87 u64 rx_crc_err; 88 u64 rx_align_err; 89 u64 rx_mac_ctrl; 90 u64 rx_pause; 91 u64 rx_bcast; 92 u64 rx_mcast; 93 u64 rx_ucast; 94 u64 rx_64_or_less; 95 u64 rx_65_127; 96 u64 rx_128_255; 97 u64 rx_256_511; 98 u64 rx_512_1023; 99 u64 rx_1024_1522; 100 u64 tx; 101 u64 tx_hi; 102 u64 tx_late_col; 103 u64 tx_pause; 104 u64 tx_bcast; 105 u64 tx_mcast; 106 u64 tx_ucast; 107 u64 tx_deferred; 108 u64 tx_total_col; 109 u64 tx_exc_col; 110 u64 tx_single_col; 111 u64 tx_mult_col; 112 u64 rx_discards; 113 u64 tx_discards; 114 }; 115 116 static const struct ksz_mib_names ksz88xx_mib_names[] = { 117 { 0x00, "rx" }, 118 { 0x01, "rx_hi" }, 119 { 0x02, "rx_undersize" }, 120 { 0x03, "rx_fragments" }, 121 { 0x04, "rx_oversize" }, 122 { 0x05, "rx_jabbers" }, 123 { 0x06, "rx_symbol_err" }, 124 { 0x07, "rx_crc_err" }, 125 { 0x08, "rx_align_err" }, 126 { 0x09, "rx_mac_ctrl" }, 127 { 0x0a, "rx_pause" }, 128 { 0x0b, "rx_bcast" }, 129 { 0x0c, "rx_mcast" }, 130 { 0x0d, "rx_ucast" }, 131 { 0x0e, "rx_64_or_less" }, 132 { 0x0f, "rx_65_127" }, 133 { 0x10, "rx_128_255" }, 134 { 0x11, "rx_256_511" }, 135 { 0x12, "rx_512_1023" }, 136 { 0x13, "rx_1024_1522" }, 137 { 0x14, "tx" }, 138 { 0x15, "tx_hi" }, 139 { 0x16, "tx_late_col" }, 140 { 0x17, "tx_pause" }, 141 { 0x18, "tx_bcast" }, 142 { 0x19, "tx_mcast" }, 143 { 0x1a, "tx_ucast" }, 144 { 0x1b, "tx_deferred" }, 145 { 0x1c, "tx_total_col" }, 146 { 0x1d, "tx_exc_col" }, 147 { 0x1e, "tx_single_col" }, 148 { 0x1f, "tx_mult_col" }, 149 { 0x100, "rx_discards" }, 150 { 0x101, "tx_discards" }, 151 }; 152 153 static const struct ksz_mib_names ksz9477_mib_names[] = { 154 { 0x00, "rx_hi" }, 155 { 0x01, "rx_undersize" }, 156 { 0x02, "rx_fragments" }, 157 { 0x03, "rx_oversize" }, 158 { 0x04, "rx_jabbers" }, 159 { 0x05, "rx_symbol_err" }, 160 { 0x06, "rx_crc_err" }, 161 { 0x07, "rx_align_err" }, 162 { 0x08, "rx_mac_ctrl" }, 163 { 0x09, "rx_pause" }, 164 { 0x0A, "rx_bcast" }, 165 { 0x0B, "rx_mcast" }, 166 { 0x0C, "rx_ucast" }, 167 { 0x0D, "rx_64_or_less" }, 168 { 0x0E, "rx_65_127" }, 169 { 0x0F, "rx_128_255" }, 170 { 0x10, "rx_256_511" }, 171 { 0x11, "rx_512_1023" }, 172 { 0x12, "rx_1024_1522" }, 173 { 0x13, "rx_1523_2000" }, 174 { 0x14, "rx_2001" }, 175 { 0x15, "tx_hi" }, 176 { 0x16, "tx_late_col" }, 177 { 0x17, "tx_pause" }, 178 { 0x18, "tx_bcast" }, 179 { 0x19, "tx_mcast" }, 180 { 0x1A, "tx_ucast" }, 181 { 0x1B, "tx_deferred" }, 182 { 0x1C, "tx_total_col" }, 183 { 0x1D, "tx_exc_col" }, 184 { 0x1E, "tx_single_col" }, 185 { 0x1F, "tx_mult_col" }, 186 { 0x80, "rx_total" }, 187 { 0x81, "tx_total" }, 188 { 0x82, "rx_discards" }, 189 { 0x83, "tx_discards" }, 190 }; 191 192 struct ksz_driver_strength_prop { 193 const char *name; 194 int offset; 195 int value; 196 }; 197 198 enum ksz_driver_strength_type { 199 KSZ_DRIVER_STRENGTH_HI, 200 KSZ_DRIVER_STRENGTH_LO, 201 KSZ_DRIVER_STRENGTH_IO, 202 }; 203 204 /** 205 * struct ksz_drive_strength - drive strength mapping 206 * @reg_val: register value 207 * @microamp: microamp value 208 */ 209 struct ksz_drive_strength { 210 u32 reg_val; 211 u32 microamp; 212 }; 213 214 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants 215 * 216 * This values are not documented in KSZ9477 variants but confirmed by 217 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893 218 * and KSZ8563 are using same register (drive strength) settings like KSZ8795. 219 * 220 * Documentation in KSZ8795CLX provides more information with some 221 * recommendations: 222 * - for high speed signals 223 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using 224 * 2.5V or 3.3V VDDIO. 225 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with 226 * using 1.8V VDDIO. 227 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V 228 * or 3.3V VDDIO. 229 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO. 230 * 5. In same interface, the heavy loading should use higher one of the 231 * drive current strength. 232 * - for low speed signals 233 * 1. 3.3V VDDIO, use either 4 mA or 8 mA. 234 * 2. 2.5V VDDIO, use either 8 mA or 12 mA. 235 * 3. 1.8V VDDIO, use either 12 mA or 16 mA. 236 * 4. If it is heavy loading, can use higher drive current strength. 237 */ 238 static const struct ksz_drive_strength ksz9477_drive_strengths[] = { 239 { SW_DRIVE_STRENGTH_2MA, 2000 }, 240 { SW_DRIVE_STRENGTH_4MA, 4000 }, 241 { SW_DRIVE_STRENGTH_8MA, 8000 }, 242 { SW_DRIVE_STRENGTH_12MA, 12000 }, 243 { SW_DRIVE_STRENGTH_16MA, 16000 }, 244 { SW_DRIVE_STRENGTH_20MA, 20000 }, 245 { SW_DRIVE_STRENGTH_24MA, 24000 }, 246 { SW_DRIVE_STRENGTH_28MA, 28000 }, 247 }; 248 249 /* ksz88x3_drive_strengths - Drive strength mapping for KSZ8863, KSZ8873, .. 250 * variants. 251 * This values are documented in KSZ8873 and KSZ8863 datasheets. 252 */ 253 static const struct ksz_drive_strength ksz88x3_drive_strengths[] = { 254 { 0, 8000 }, 255 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 }, 256 }; 257 258 static void ksz88x3_phylink_mac_config(struct phylink_config *config, 259 unsigned int mode, 260 const struct phylink_link_state *state); 261 static void ksz_phylink_mac_config(struct phylink_config *config, 262 unsigned int mode, 263 const struct phylink_link_state *state); 264 static void ksz_phylink_mac_link_down(struct phylink_config *config, 265 unsigned int mode, 266 phy_interface_t interface); 267 268 static const struct phylink_mac_ops ksz88x3_phylink_mac_ops = { 269 .mac_config = ksz88x3_phylink_mac_config, 270 .mac_link_down = ksz_phylink_mac_link_down, 271 .mac_link_up = ksz8_phylink_mac_link_up, 272 }; 273 274 static const struct phylink_mac_ops ksz8_phylink_mac_ops = { 275 .mac_config = ksz_phylink_mac_config, 276 .mac_link_down = ksz_phylink_mac_link_down, 277 .mac_link_up = ksz8_phylink_mac_link_up, 278 }; 279 280 static const struct ksz_dev_ops ksz88xx_dev_ops = { 281 .setup = ksz8_setup, 282 .get_port_addr = ksz8_get_port_addr, 283 .cfg_port_member = ksz8_cfg_port_member, 284 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 285 .port_setup = ksz8_port_setup, 286 .r_phy = ksz8_r_phy, 287 .w_phy = ksz8_w_phy, 288 .r_mib_cnt = ksz8_r_mib_cnt, 289 .r_mib_pkt = ksz8_r_mib_pkt, 290 .r_mib_stat64 = ksz88xx_r_mib_stats64, 291 .freeze_mib = ksz8_freeze_mib, 292 .port_init_cnt = ksz8_port_init_cnt, 293 .fdb_dump = ksz8_fdb_dump, 294 .fdb_add = ksz8_fdb_add, 295 .fdb_del = ksz8_fdb_del, 296 .mdb_add = ksz8_mdb_add, 297 .mdb_del = ksz8_mdb_del, 298 .vlan_filtering = ksz8_port_vlan_filtering, 299 .vlan_add = ksz8_port_vlan_add, 300 .vlan_del = ksz8_port_vlan_del, 301 .mirror_add = ksz8_port_mirror_add, 302 .mirror_del = ksz8_port_mirror_del, 303 .get_caps = ksz8_get_caps, 304 .config_cpu_port = ksz8_config_cpu_port, 305 .enable_stp_addr = ksz8_enable_stp_addr, 306 .reset = ksz8_reset_switch, 307 .init = ksz8_switch_init, 308 .exit = ksz8_switch_exit, 309 .change_mtu = ksz8_change_mtu, 310 .pme_write8 = ksz8_pme_write8, 311 .pme_pread8 = ksz8_pme_pread8, 312 .pme_pwrite8 = ksz8_pme_pwrite8, 313 }; 314 315 static const struct ksz_dev_ops ksz87xx_dev_ops = { 316 .setup = ksz8_setup, 317 .get_port_addr = ksz8_get_port_addr, 318 .cfg_port_member = ksz8_cfg_port_member, 319 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 320 .port_setup = ksz8_port_setup, 321 .r_phy = ksz8_r_phy, 322 .w_phy = ksz8_w_phy, 323 .r_mib_cnt = ksz8_r_mib_cnt, 324 .r_mib_pkt = ksz8_r_mib_pkt, 325 .r_mib_stat64 = ksz_r_mib_stats64, 326 .freeze_mib = ksz8_freeze_mib, 327 .port_init_cnt = ksz8_port_init_cnt, 328 .fdb_dump = ksz8_fdb_dump, 329 .fdb_add = ksz8_fdb_add, 330 .fdb_del = ksz8_fdb_del, 331 .mdb_add = ksz8_mdb_add, 332 .mdb_del = ksz8_mdb_del, 333 .vlan_filtering = ksz8_port_vlan_filtering, 334 .vlan_add = ksz8_port_vlan_add, 335 .vlan_del = ksz8_port_vlan_del, 336 .mirror_add = ksz8_port_mirror_add, 337 .mirror_del = ksz8_port_mirror_del, 338 .get_caps = ksz8_get_caps, 339 .config_cpu_port = ksz8_config_cpu_port, 340 .enable_stp_addr = ksz8_enable_stp_addr, 341 .reset = ksz8_reset_switch, 342 .init = ksz8_switch_init, 343 .exit = ksz8_switch_exit, 344 .change_mtu = ksz8_change_mtu, 345 .pme_write8 = ksz8_pme_write8, 346 .pme_pread8 = ksz8_pme_pread8, 347 .pme_pwrite8 = ksz8_pme_pwrite8, 348 }; 349 350 static void ksz9477_phylink_mac_link_up(struct phylink_config *config, 351 struct phy_device *phydev, 352 unsigned int mode, 353 phy_interface_t interface, 354 int speed, int duplex, bool tx_pause, 355 bool rx_pause); 356 357 static const struct phylink_mac_ops ksz9477_phylink_mac_ops = { 358 .mac_config = ksz_phylink_mac_config, 359 .mac_link_down = ksz_phylink_mac_link_down, 360 .mac_link_up = ksz9477_phylink_mac_link_up, 361 }; 362 363 static const struct ksz_dev_ops ksz9477_dev_ops = { 364 .setup = ksz9477_setup, 365 .get_port_addr = ksz9477_get_port_addr, 366 .cfg_port_member = ksz9477_cfg_port_member, 367 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 368 .port_setup = ksz9477_port_setup, 369 .set_ageing_time = ksz9477_set_ageing_time, 370 .r_phy = ksz9477_r_phy, 371 .w_phy = ksz9477_w_phy, 372 .r_mib_cnt = ksz9477_r_mib_cnt, 373 .r_mib_pkt = ksz9477_r_mib_pkt, 374 .r_mib_stat64 = ksz_r_mib_stats64, 375 .freeze_mib = ksz9477_freeze_mib, 376 .port_init_cnt = ksz9477_port_init_cnt, 377 .vlan_filtering = ksz9477_port_vlan_filtering, 378 .vlan_add = ksz9477_port_vlan_add, 379 .vlan_del = ksz9477_port_vlan_del, 380 .mirror_add = ksz9477_port_mirror_add, 381 .mirror_del = ksz9477_port_mirror_del, 382 .get_caps = ksz9477_get_caps, 383 .fdb_dump = ksz9477_fdb_dump, 384 .fdb_add = ksz9477_fdb_add, 385 .fdb_del = ksz9477_fdb_del, 386 .mdb_add = ksz9477_mdb_add, 387 .mdb_del = ksz9477_mdb_del, 388 .change_mtu = ksz9477_change_mtu, 389 .pme_write8 = ksz_write8, 390 .pme_pread8 = ksz_pread8, 391 .pme_pwrite8 = ksz_pwrite8, 392 .config_cpu_port = ksz9477_config_cpu_port, 393 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc, 394 .enable_stp_addr = ksz9477_enable_stp_addr, 395 .reset = ksz9477_reset_switch, 396 .init = ksz9477_switch_init, 397 .exit = ksz9477_switch_exit, 398 }; 399 400 static const struct phylink_mac_ops lan937x_phylink_mac_ops = { 401 .mac_config = ksz_phylink_mac_config, 402 .mac_link_down = ksz_phylink_mac_link_down, 403 .mac_link_up = ksz9477_phylink_mac_link_up, 404 }; 405 406 static const struct ksz_dev_ops lan937x_dev_ops = { 407 .setup = lan937x_setup, 408 .teardown = lan937x_teardown, 409 .get_port_addr = ksz9477_get_port_addr, 410 .cfg_port_member = ksz9477_cfg_port_member, 411 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 412 .port_setup = lan937x_port_setup, 413 .set_ageing_time = lan937x_set_ageing_time, 414 .mdio_bus_preinit = lan937x_mdio_bus_preinit, 415 .create_phy_addr_map = lan937x_create_phy_addr_map, 416 .r_phy = lan937x_r_phy, 417 .w_phy = lan937x_w_phy, 418 .r_mib_cnt = ksz9477_r_mib_cnt, 419 .r_mib_pkt = ksz9477_r_mib_pkt, 420 .r_mib_stat64 = ksz_r_mib_stats64, 421 .freeze_mib = ksz9477_freeze_mib, 422 .port_init_cnt = ksz9477_port_init_cnt, 423 .vlan_filtering = ksz9477_port_vlan_filtering, 424 .vlan_add = ksz9477_port_vlan_add, 425 .vlan_del = ksz9477_port_vlan_del, 426 .mirror_add = ksz9477_port_mirror_add, 427 .mirror_del = ksz9477_port_mirror_del, 428 .get_caps = lan937x_phylink_get_caps, 429 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 430 .fdb_dump = ksz9477_fdb_dump, 431 .fdb_add = ksz9477_fdb_add, 432 .fdb_del = ksz9477_fdb_del, 433 .mdb_add = ksz9477_mdb_add, 434 .mdb_del = ksz9477_mdb_del, 435 .change_mtu = lan937x_change_mtu, 436 .config_cpu_port = lan937x_config_cpu_port, 437 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 438 .enable_stp_addr = ksz9477_enable_stp_addr, 439 .reset = lan937x_reset_switch, 440 .init = lan937x_switch_init, 441 .exit = lan937x_switch_exit, 442 }; 443 444 static const u16 ksz8795_regs[] = { 445 [REG_SW_MAC_ADDR] = 0x68, 446 [REG_IND_CTRL_0] = 0x6E, 447 [REG_IND_DATA_8] = 0x70, 448 [REG_IND_DATA_CHECK] = 0x72, 449 [REG_IND_DATA_HI] = 0x71, 450 [REG_IND_DATA_LO] = 0x75, 451 [REG_IND_MIB_CHECK] = 0x74, 452 [REG_IND_BYTE] = 0xA0, 453 [P_FORCE_CTRL] = 0x0C, 454 [P_LINK_STATUS] = 0x0E, 455 [P_LOCAL_CTRL] = 0x07, 456 [P_NEG_RESTART_CTRL] = 0x0D, 457 [P_REMOTE_STATUS] = 0x08, 458 [P_SPEED_STATUS] = 0x09, 459 [S_TAIL_TAG_CTRL] = 0x0C, 460 [P_STP_CTRL] = 0x02, 461 [S_START_CTRL] = 0x01, 462 [S_BROADCAST_CTRL] = 0x06, 463 [S_MULTICAST_CTRL] = 0x04, 464 [P_XMII_CTRL_0] = 0x06, 465 [P_XMII_CTRL_1] = 0x06, 466 [REG_SW_PME_CTRL] = 0x8003, 467 [REG_PORT_PME_STATUS] = 0x8003, 468 [REG_PORT_PME_CTRL] = 0x8007, 469 }; 470 471 static const u32 ksz8795_masks[] = { 472 [PORT_802_1P_REMAPPING] = BIT(7), 473 [SW_TAIL_TAG_ENABLE] = BIT(1), 474 [MIB_COUNTER_OVERFLOW] = BIT(6), 475 [MIB_COUNTER_VALID] = BIT(5), 476 [VLAN_TABLE_FID] = GENMASK(6, 0), 477 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 478 [VLAN_TABLE_VALID] = BIT(12), 479 [STATIC_MAC_TABLE_VALID] = BIT(21), 480 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 481 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 482 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 483 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 484 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 485 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 486 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 487 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 488 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 489 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 490 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 491 [P_MII_TX_FLOW_CTRL] = BIT(5), 492 [P_MII_RX_FLOW_CTRL] = BIT(5), 493 }; 494 495 static const u8 ksz8795_xmii_ctrl0[] = { 496 [P_MII_100MBIT] = 0, 497 [P_MII_10MBIT] = 1, 498 [P_MII_FULL_DUPLEX] = 0, 499 [P_MII_HALF_DUPLEX] = 1, 500 }; 501 502 static const u8 ksz8795_xmii_ctrl1[] = { 503 [P_RGMII_SEL] = 3, 504 [P_GMII_SEL] = 2, 505 [P_RMII_SEL] = 1, 506 [P_MII_SEL] = 0, 507 [P_GMII_1GBIT] = 1, 508 [P_GMII_NOT_1GBIT] = 0, 509 }; 510 511 static const u8 ksz8795_shifts[] = { 512 [VLAN_TABLE_MEMBERSHIP_S] = 7, 513 [VLAN_TABLE] = 16, 514 [STATIC_MAC_FWD_PORTS] = 16, 515 [STATIC_MAC_FID] = 24, 516 [DYNAMIC_MAC_ENTRIES_H] = 3, 517 [DYNAMIC_MAC_ENTRIES] = 29, 518 [DYNAMIC_MAC_FID] = 16, 519 [DYNAMIC_MAC_TIMESTAMP] = 27, 520 [DYNAMIC_MAC_SRC_PORT] = 24, 521 }; 522 523 static const u16 ksz8863_regs[] = { 524 [REG_SW_MAC_ADDR] = 0x70, 525 [REG_IND_CTRL_0] = 0x79, 526 [REG_IND_DATA_8] = 0x7B, 527 [REG_IND_DATA_CHECK] = 0x7B, 528 [REG_IND_DATA_HI] = 0x7C, 529 [REG_IND_DATA_LO] = 0x80, 530 [REG_IND_MIB_CHECK] = 0x80, 531 [P_FORCE_CTRL] = 0x0C, 532 [P_LINK_STATUS] = 0x0E, 533 [P_LOCAL_CTRL] = 0x0C, 534 [P_NEG_RESTART_CTRL] = 0x0D, 535 [P_REMOTE_STATUS] = 0x0E, 536 [P_SPEED_STATUS] = 0x0F, 537 [S_TAIL_TAG_CTRL] = 0x03, 538 [P_STP_CTRL] = 0x02, 539 [S_START_CTRL] = 0x01, 540 [S_BROADCAST_CTRL] = 0x06, 541 [S_MULTICAST_CTRL] = 0x04, 542 }; 543 544 static const u32 ksz8863_masks[] = { 545 [PORT_802_1P_REMAPPING] = BIT(3), 546 [SW_TAIL_TAG_ENABLE] = BIT(6), 547 [MIB_COUNTER_OVERFLOW] = BIT(7), 548 [MIB_COUNTER_VALID] = BIT(6), 549 [VLAN_TABLE_FID] = GENMASK(15, 12), 550 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 551 [VLAN_TABLE_VALID] = BIT(19), 552 [STATIC_MAC_TABLE_VALID] = BIT(19), 553 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 554 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 555 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 556 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 557 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 558 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 559 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 560 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 561 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 562 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 563 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 564 }; 565 566 static u8 ksz8863_shifts[] = { 567 [VLAN_TABLE_MEMBERSHIP_S] = 16, 568 [STATIC_MAC_FWD_PORTS] = 16, 569 [STATIC_MAC_FID] = 22, 570 [DYNAMIC_MAC_ENTRIES_H] = 8, 571 [DYNAMIC_MAC_ENTRIES] = 24, 572 [DYNAMIC_MAC_FID] = 16, 573 [DYNAMIC_MAC_TIMESTAMP] = 22, 574 [DYNAMIC_MAC_SRC_PORT] = 20, 575 }; 576 577 static const u16 ksz8895_regs[] = { 578 [REG_SW_MAC_ADDR] = 0x68, 579 [REG_IND_CTRL_0] = 0x6E, 580 [REG_IND_DATA_8] = 0x70, 581 [REG_IND_DATA_CHECK] = 0x72, 582 [REG_IND_DATA_HI] = 0x71, 583 [REG_IND_DATA_LO] = 0x75, 584 [REG_IND_MIB_CHECK] = 0x75, 585 [P_FORCE_CTRL] = 0x0C, 586 [P_LINK_STATUS] = 0x0E, 587 [P_LOCAL_CTRL] = 0x0C, 588 [P_NEG_RESTART_CTRL] = 0x0D, 589 [P_REMOTE_STATUS] = 0x0E, 590 [P_SPEED_STATUS] = 0x09, 591 [S_TAIL_TAG_CTRL] = 0x0C, 592 [P_STP_CTRL] = 0x02, 593 [S_START_CTRL] = 0x01, 594 [S_BROADCAST_CTRL] = 0x06, 595 [S_MULTICAST_CTRL] = 0x04, 596 }; 597 598 static const u32 ksz8895_masks[] = { 599 [PORT_802_1P_REMAPPING] = BIT(7), 600 [SW_TAIL_TAG_ENABLE] = BIT(1), 601 [MIB_COUNTER_OVERFLOW] = BIT(7), 602 [MIB_COUNTER_VALID] = BIT(6), 603 [VLAN_TABLE_FID] = GENMASK(6, 0), 604 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 605 [VLAN_TABLE_VALID] = BIT(12), 606 [STATIC_MAC_TABLE_VALID] = BIT(21), 607 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 608 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 609 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 610 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 611 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 612 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 613 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 614 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 615 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 616 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 617 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 618 }; 619 620 static const u8 ksz8895_shifts[] = { 621 [VLAN_TABLE_MEMBERSHIP_S] = 7, 622 [VLAN_TABLE] = 13, 623 [STATIC_MAC_FWD_PORTS] = 16, 624 [STATIC_MAC_FID] = 24, 625 [DYNAMIC_MAC_ENTRIES_H] = 3, 626 [DYNAMIC_MAC_ENTRIES] = 29, 627 [DYNAMIC_MAC_FID] = 16, 628 [DYNAMIC_MAC_TIMESTAMP] = 27, 629 [DYNAMIC_MAC_SRC_PORT] = 24, 630 }; 631 632 static const u16 ksz9477_regs[] = { 633 [REG_SW_MAC_ADDR] = 0x0302, 634 [P_STP_CTRL] = 0x0B04, 635 [S_START_CTRL] = 0x0300, 636 [S_BROADCAST_CTRL] = 0x0332, 637 [S_MULTICAST_CTRL] = 0x0331, 638 [P_XMII_CTRL_0] = 0x0300, 639 [P_XMII_CTRL_1] = 0x0301, 640 [REG_SW_PME_CTRL] = 0x0006, 641 [REG_PORT_PME_STATUS] = 0x0013, 642 [REG_PORT_PME_CTRL] = 0x0017, 643 }; 644 645 static const u32 ksz9477_masks[] = { 646 [ALU_STAT_WRITE] = 0, 647 [ALU_STAT_READ] = 1, 648 [P_MII_TX_FLOW_CTRL] = BIT(5), 649 [P_MII_RX_FLOW_CTRL] = BIT(3), 650 }; 651 652 static const u8 ksz9477_shifts[] = { 653 [ALU_STAT_INDEX] = 16, 654 }; 655 656 static const u8 ksz9477_xmii_ctrl0[] = { 657 [P_MII_100MBIT] = 1, 658 [P_MII_10MBIT] = 0, 659 [P_MII_FULL_DUPLEX] = 1, 660 [P_MII_HALF_DUPLEX] = 0, 661 }; 662 663 static const u8 ksz9477_xmii_ctrl1[] = { 664 [P_RGMII_SEL] = 0, 665 [P_RMII_SEL] = 1, 666 [P_GMII_SEL] = 2, 667 [P_MII_SEL] = 3, 668 [P_GMII_1GBIT] = 0, 669 [P_GMII_NOT_1GBIT] = 1, 670 }; 671 672 static const u32 lan937x_masks[] = { 673 [ALU_STAT_WRITE] = 1, 674 [ALU_STAT_READ] = 2, 675 [P_MII_TX_FLOW_CTRL] = BIT(5), 676 [P_MII_RX_FLOW_CTRL] = BIT(3), 677 }; 678 679 static const u8 lan937x_shifts[] = { 680 [ALU_STAT_INDEX] = 8, 681 }; 682 683 static const struct regmap_range ksz8563_valid_regs[] = { 684 regmap_reg_range(0x0000, 0x0003), 685 regmap_reg_range(0x0006, 0x0006), 686 regmap_reg_range(0x000f, 0x001f), 687 regmap_reg_range(0x0100, 0x0100), 688 regmap_reg_range(0x0104, 0x0107), 689 regmap_reg_range(0x010d, 0x010d), 690 regmap_reg_range(0x0110, 0x0113), 691 regmap_reg_range(0x0120, 0x012b), 692 regmap_reg_range(0x0201, 0x0201), 693 regmap_reg_range(0x0210, 0x0213), 694 regmap_reg_range(0x0300, 0x0300), 695 regmap_reg_range(0x0302, 0x031b), 696 regmap_reg_range(0x0320, 0x032b), 697 regmap_reg_range(0x0330, 0x0336), 698 regmap_reg_range(0x0338, 0x033e), 699 regmap_reg_range(0x0340, 0x035f), 700 regmap_reg_range(0x0370, 0x0370), 701 regmap_reg_range(0x0378, 0x0378), 702 regmap_reg_range(0x037c, 0x037d), 703 regmap_reg_range(0x0390, 0x0393), 704 regmap_reg_range(0x0400, 0x040e), 705 regmap_reg_range(0x0410, 0x042f), 706 regmap_reg_range(0x0500, 0x0519), 707 regmap_reg_range(0x0520, 0x054b), 708 regmap_reg_range(0x0550, 0x05b3), 709 710 /* port 1 */ 711 regmap_reg_range(0x1000, 0x1001), 712 regmap_reg_range(0x1004, 0x100b), 713 regmap_reg_range(0x1013, 0x1013), 714 regmap_reg_range(0x1017, 0x1017), 715 regmap_reg_range(0x101b, 0x101b), 716 regmap_reg_range(0x101f, 0x1021), 717 regmap_reg_range(0x1030, 0x1030), 718 regmap_reg_range(0x1100, 0x1111), 719 regmap_reg_range(0x111a, 0x111d), 720 regmap_reg_range(0x1122, 0x1127), 721 regmap_reg_range(0x112a, 0x112b), 722 regmap_reg_range(0x1136, 0x1139), 723 regmap_reg_range(0x113e, 0x113f), 724 regmap_reg_range(0x1400, 0x1401), 725 regmap_reg_range(0x1403, 0x1403), 726 regmap_reg_range(0x1410, 0x1417), 727 regmap_reg_range(0x1420, 0x1423), 728 regmap_reg_range(0x1500, 0x1507), 729 regmap_reg_range(0x1600, 0x1612), 730 regmap_reg_range(0x1800, 0x180f), 731 regmap_reg_range(0x1900, 0x1907), 732 regmap_reg_range(0x1914, 0x191b), 733 regmap_reg_range(0x1a00, 0x1a03), 734 regmap_reg_range(0x1a04, 0x1a08), 735 regmap_reg_range(0x1b00, 0x1b01), 736 regmap_reg_range(0x1b04, 0x1b04), 737 regmap_reg_range(0x1c00, 0x1c05), 738 regmap_reg_range(0x1c08, 0x1c1b), 739 740 /* port 2 */ 741 regmap_reg_range(0x2000, 0x2001), 742 regmap_reg_range(0x2004, 0x200b), 743 regmap_reg_range(0x2013, 0x2013), 744 regmap_reg_range(0x2017, 0x2017), 745 regmap_reg_range(0x201b, 0x201b), 746 regmap_reg_range(0x201f, 0x2021), 747 regmap_reg_range(0x2030, 0x2030), 748 regmap_reg_range(0x2100, 0x2111), 749 regmap_reg_range(0x211a, 0x211d), 750 regmap_reg_range(0x2122, 0x2127), 751 regmap_reg_range(0x212a, 0x212b), 752 regmap_reg_range(0x2136, 0x2139), 753 regmap_reg_range(0x213e, 0x213f), 754 regmap_reg_range(0x2400, 0x2401), 755 regmap_reg_range(0x2403, 0x2403), 756 regmap_reg_range(0x2410, 0x2417), 757 regmap_reg_range(0x2420, 0x2423), 758 regmap_reg_range(0x2500, 0x2507), 759 regmap_reg_range(0x2600, 0x2612), 760 regmap_reg_range(0x2800, 0x280f), 761 regmap_reg_range(0x2900, 0x2907), 762 regmap_reg_range(0x2914, 0x291b), 763 regmap_reg_range(0x2a00, 0x2a03), 764 regmap_reg_range(0x2a04, 0x2a08), 765 regmap_reg_range(0x2b00, 0x2b01), 766 regmap_reg_range(0x2b04, 0x2b04), 767 regmap_reg_range(0x2c00, 0x2c05), 768 regmap_reg_range(0x2c08, 0x2c1b), 769 770 /* port 3 */ 771 regmap_reg_range(0x3000, 0x3001), 772 regmap_reg_range(0x3004, 0x300b), 773 regmap_reg_range(0x3013, 0x3013), 774 regmap_reg_range(0x3017, 0x3017), 775 regmap_reg_range(0x301b, 0x301b), 776 regmap_reg_range(0x301f, 0x3021), 777 regmap_reg_range(0x3030, 0x3030), 778 regmap_reg_range(0x3300, 0x3301), 779 regmap_reg_range(0x3303, 0x3303), 780 regmap_reg_range(0x3400, 0x3401), 781 regmap_reg_range(0x3403, 0x3403), 782 regmap_reg_range(0x3410, 0x3417), 783 regmap_reg_range(0x3420, 0x3423), 784 regmap_reg_range(0x3500, 0x3507), 785 regmap_reg_range(0x3600, 0x3612), 786 regmap_reg_range(0x3800, 0x380f), 787 regmap_reg_range(0x3900, 0x3907), 788 regmap_reg_range(0x3914, 0x391b), 789 regmap_reg_range(0x3a00, 0x3a03), 790 regmap_reg_range(0x3a04, 0x3a08), 791 regmap_reg_range(0x3b00, 0x3b01), 792 regmap_reg_range(0x3b04, 0x3b04), 793 regmap_reg_range(0x3c00, 0x3c05), 794 regmap_reg_range(0x3c08, 0x3c1b), 795 }; 796 797 static const struct regmap_access_table ksz8563_register_set = { 798 .yes_ranges = ksz8563_valid_regs, 799 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 800 }; 801 802 static const struct regmap_range ksz9477_valid_regs[] = { 803 regmap_reg_range(0x0000, 0x0003), 804 regmap_reg_range(0x0006, 0x0006), 805 regmap_reg_range(0x0010, 0x001f), 806 regmap_reg_range(0x0100, 0x0100), 807 regmap_reg_range(0x0103, 0x0107), 808 regmap_reg_range(0x010d, 0x010d), 809 regmap_reg_range(0x0110, 0x0113), 810 regmap_reg_range(0x0120, 0x012b), 811 regmap_reg_range(0x0201, 0x0201), 812 regmap_reg_range(0x0210, 0x0213), 813 regmap_reg_range(0x0300, 0x0300), 814 regmap_reg_range(0x0302, 0x031b), 815 regmap_reg_range(0x0320, 0x032b), 816 regmap_reg_range(0x0330, 0x0336), 817 regmap_reg_range(0x0338, 0x033b), 818 regmap_reg_range(0x033e, 0x033e), 819 regmap_reg_range(0x0340, 0x035f), 820 regmap_reg_range(0x0370, 0x0370), 821 regmap_reg_range(0x0378, 0x0378), 822 regmap_reg_range(0x037c, 0x037d), 823 regmap_reg_range(0x0390, 0x0393), 824 regmap_reg_range(0x0400, 0x040e), 825 regmap_reg_range(0x0410, 0x042f), 826 regmap_reg_range(0x0444, 0x044b), 827 regmap_reg_range(0x0450, 0x046f), 828 regmap_reg_range(0x0500, 0x0519), 829 regmap_reg_range(0x0520, 0x054b), 830 regmap_reg_range(0x0550, 0x05b3), 831 regmap_reg_range(0x0604, 0x060b), 832 regmap_reg_range(0x0610, 0x0612), 833 regmap_reg_range(0x0614, 0x062c), 834 regmap_reg_range(0x0640, 0x0645), 835 regmap_reg_range(0x0648, 0x064d), 836 837 /* port 1 */ 838 regmap_reg_range(0x1000, 0x1001), 839 regmap_reg_range(0x1013, 0x1013), 840 regmap_reg_range(0x1017, 0x1017), 841 regmap_reg_range(0x101b, 0x101b), 842 regmap_reg_range(0x101f, 0x1020), 843 regmap_reg_range(0x1030, 0x1030), 844 regmap_reg_range(0x1100, 0x1115), 845 regmap_reg_range(0x111a, 0x111f), 846 regmap_reg_range(0x1120, 0x112b), 847 regmap_reg_range(0x1134, 0x113b), 848 regmap_reg_range(0x113c, 0x113f), 849 regmap_reg_range(0x1400, 0x1401), 850 regmap_reg_range(0x1403, 0x1403), 851 regmap_reg_range(0x1410, 0x1417), 852 regmap_reg_range(0x1420, 0x1423), 853 regmap_reg_range(0x1500, 0x1507), 854 regmap_reg_range(0x1600, 0x1613), 855 regmap_reg_range(0x1800, 0x180f), 856 regmap_reg_range(0x1820, 0x1827), 857 regmap_reg_range(0x1830, 0x1837), 858 regmap_reg_range(0x1840, 0x184b), 859 regmap_reg_range(0x1900, 0x1907), 860 regmap_reg_range(0x1914, 0x191b), 861 regmap_reg_range(0x1920, 0x1920), 862 regmap_reg_range(0x1923, 0x1927), 863 regmap_reg_range(0x1a00, 0x1a03), 864 regmap_reg_range(0x1a04, 0x1a07), 865 regmap_reg_range(0x1b00, 0x1b01), 866 regmap_reg_range(0x1b04, 0x1b04), 867 regmap_reg_range(0x1c00, 0x1c05), 868 regmap_reg_range(0x1c08, 0x1c1b), 869 870 /* port 2 */ 871 regmap_reg_range(0x2000, 0x2001), 872 regmap_reg_range(0x2013, 0x2013), 873 regmap_reg_range(0x2017, 0x2017), 874 regmap_reg_range(0x201b, 0x201b), 875 regmap_reg_range(0x201f, 0x2020), 876 regmap_reg_range(0x2030, 0x2030), 877 regmap_reg_range(0x2100, 0x2115), 878 regmap_reg_range(0x211a, 0x211f), 879 regmap_reg_range(0x2120, 0x212b), 880 regmap_reg_range(0x2134, 0x213b), 881 regmap_reg_range(0x213c, 0x213f), 882 regmap_reg_range(0x2400, 0x2401), 883 regmap_reg_range(0x2403, 0x2403), 884 regmap_reg_range(0x2410, 0x2417), 885 regmap_reg_range(0x2420, 0x2423), 886 regmap_reg_range(0x2500, 0x2507), 887 regmap_reg_range(0x2600, 0x2613), 888 regmap_reg_range(0x2800, 0x280f), 889 regmap_reg_range(0x2820, 0x2827), 890 regmap_reg_range(0x2830, 0x2837), 891 regmap_reg_range(0x2840, 0x284b), 892 regmap_reg_range(0x2900, 0x2907), 893 regmap_reg_range(0x2914, 0x291b), 894 regmap_reg_range(0x2920, 0x2920), 895 regmap_reg_range(0x2923, 0x2927), 896 regmap_reg_range(0x2a00, 0x2a03), 897 regmap_reg_range(0x2a04, 0x2a07), 898 regmap_reg_range(0x2b00, 0x2b01), 899 regmap_reg_range(0x2b04, 0x2b04), 900 regmap_reg_range(0x2c00, 0x2c05), 901 regmap_reg_range(0x2c08, 0x2c1b), 902 903 /* port 3 */ 904 regmap_reg_range(0x3000, 0x3001), 905 regmap_reg_range(0x3013, 0x3013), 906 regmap_reg_range(0x3017, 0x3017), 907 regmap_reg_range(0x301b, 0x301b), 908 regmap_reg_range(0x301f, 0x3020), 909 regmap_reg_range(0x3030, 0x3030), 910 regmap_reg_range(0x3100, 0x3115), 911 regmap_reg_range(0x311a, 0x311f), 912 regmap_reg_range(0x3120, 0x312b), 913 regmap_reg_range(0x3134, 0x313b), 914 regmap_reg_range(0x313c, 0x313f), 915 regmap_reg_range(0x3400, 0x3401), 916 regmap_reg_range(0x3403, 0x3403), 917 regmap_reg_range(0x3410, 0x3417), 918 regmap_reg_range(0x3420, 0x3423), 919 regmap_reg_range(0x3500, 0x3507), 920 regmap_reg_range(0x3600, 0x3613), 921 regmap_reg_range(0x3800, 0x380f), 922 regmap_reg_range(0x3820, 0x3827), 923 regmap_reg_range(0x3830, 0x3837), 924 regmap_reg_range(0x3840, 0x384b), 925 regmap_reg_range(0x3900, 0x3907), 926 regmap_reg_range(0x3914, 0x391b), 927 regmap_reg_range(0x3920, 0x3920), 928 regmap_reg_range(0x3923, 0x3927), 929 regmap_reg_range(0x3a00, 0x3a03), 930 regmap_reg_range(0x3a04, 0x3a07), 931 regmap_reg_range(0x3b00, 0x3b01), 932 regmap_reg_range(0x3b04, 0x3b04), 933 regmap_reg_range(0x3c00, 0x3c05), 934 regmap_reg_range(0x3c08, 0x3c1b), 935 936 /* port 4 */ 937 regmap_reg_range(0x4000, 0x4001), 938 regmap_reg_range(0x4013, 0x4013), 939 regmap_reg_range(0x4017, 0x4017), 940 regmap_reg_range(0x401b, 0x401b), 941 regmap_reg_range(0x401f, 0x4020), 942 regmap_reg_range(0x4030, 0x4030), 943 regmap_reg_range(0x4100, 0x4115), 944 regmap_reg_range(0x411a, 0x411f), 945 regmap_reg_range(0x4120, 0x412b), 946 regmap_reg_range(0x4134, 0x413b), 947 regmap_reg_range(0x413c, 0x413f), 948 regmap_reg_range(0x4400, 0x4401), 949 regmap_reg_range(0x4403, 0x4403), 950 regmap_reg_range(0x4410, 0x4417), 951 regmap_reg_range(0x4420, 0x4423), 952 regmap_reg_range(0x4500, 0x4507), 953 regmap_reg_range(0x4600, 0x4613), 954 regmap_reg_range(0x4800, 0x480f), 955 regmap_reg_range(0x4820, 0x4827), 956 regmap_reg_range(0x4830, 0x4837), 957 regmap_reg_range(0x4840, 0x484b), 958 regmap_reg_range(0x4900, 0x4907), 959 regmap_reg_range(0x4914, 0x491b), 960 regmap_reg_range(0x4920, 0x4920), 961 regmap_reg_range(0x4923, 0x4927), 962 regmap_reg_range(0x4a00, 0x4a03), 963 regmap_reg_range(0x4a04, 0x4a07), 964 regmap_reg_range(0x4b00, 0x4b01), 965 regmap_reg_range(0x4b04, 0x4b04), 966 regmap_reg_range(0x4c00, 0x4c05), 967 regmap_reg_range(0x4c08, 0x4c1b), 968 969 /* port 5 */ 970 regmap_reg_range(0x5000, 0x5001), 971 regmap_reg_range(0x5013, 0x5013), 972 regmap_reg_range(0x5017, 0x5017), 973 regmap_reg_range(0x501b, 0x501b), 974 regmap_reg_range(0x501f, 0x5020), 975 regmap_reg_range(0x5030, 0x5030), 976 regmap_reg_range(0x5100, 0x5115), 977 regmap_reg_range(0x511a, 0x511f), 978 regmap_reg_range(0x5120, 0x512b), 979 regmap_reg_range(0x5134, 0x513b), 980 regmap_reg_range(0x513c, 0x513f), 981 regmap_reg_range(0x5400, 0x5401), 982 regmap_reg_range(0x5403, 0x5403), 983 regmap_reg_range(0x5410, 0x5417), 984 regmap_reg_range(0x5420, 0x5423), 985 regmap_reg_range(0x5500, 0x5507), 986 regmap_reg_range(0x5600, 0x5613), 987 regmap_reg_range(0x5800, 0x580f), 988 regmap_reg_range(0x5820, 0x5827), 989 regmap_reg_range(0x5830, 0x5837), 990 regmap_reg_range(0x5840, 0x584b), 991 regmap_reg_range(0x5900, 0x5907), 992 regmap_reg_range(0x5914, 0x591b), 993 regmap_reg_range(0x5920, 0x5920), 994 regmap_reg_range(0x5923, 0x5927), 995 regmap_reg_range(0x5a00, 0x5a03), 996 regmap_reg_range(0x5a04, 0x5a07), 997 regmap_reg_range(0x5b00, 0x5b01), 998 regmap_reg_range(0x5b04, 0x5b04), 999 regmap_reg_range(0x5c00, 0x5c05), 1000 regmap_reg_range(0x5c08, 0x5c1b), 1001 1002 /* port 6 */ 1003 regmap_reg_range(0x6000, 0x6001), 1004 regmap_reg_range(0x6013, 0x6013), 1005 regmap_reg_range(0x6017, 0x6017), 1006 regmap_reg_range(0x601b, 0x601b), 1007 regmap_reg_range(0x601f, 0x6020), 1008 regmap_reg_range(0x6030, 0x6030), 1009 regmap_reg_range(0x6300, 0x6301), 1010 regmap_reg_range(0x6400, 0x6401), 1011 regmap_reg_range(0x6403, 0x6403), 1012 regmap_reg_range(0x6410, 0x6417), 1013 regmap_reg_range(0x6420, 0x6423), 1014 regmap_reg_range(0x6500, 0x6507), 1015 regmap_reg_range(0x6600, 0x6613), 1016 regmap_reg_range(0x6800, 0x680f), 1017 regmap_reg_range(0x6820, 0x6827), 1018 regmap_reg_range(0x6830, 0x6837), 1019 regmap_reg_range(0x6840, 0x684b), 1020 regmap_reg_range(0x6900, 0x6907), 1021 regmap_reg_range(0x6914, 0x691b), 1022 regmap_reg_range(0x6920, 0x6920), 1023 regmap_reg_range(0x6923, 0x6927), 1024 regmap_reg_range(0x6a00, 0x6a03), 1025 regmap_reg_range(0x6a04, 0x6a07), 1026 regmap_reg_range(0x6b00, 0x6b01), 1027 regmap_reg_range(0x6b04, 0x6b04), 1028 regmap_reg_range(0x6c00, 0x6c05), 1029 regmap_reg_range(0x6c08, 0x6c1b), 1030 1031 /* port 7 */ 1032 regmap_reg_range(0x7000, 0x7001), 1033 regmap_reg_range(0x7013, 0x7013), 1034 regmap_reg_range(0x7017, 0x7017), 1035 regmap_reg_range(0x701b, 0x701b), 1036 regmap_reg_range(0x701f, 0x7020), 1037 regmap_reg_range(0x7030, 0x7030), 1038 regmap_reg_range(0x7200, 0x7203), 1039 regmap_reg_range(0x7206, 0x7207), 1040 regmap_reg_range(0x7300, 0x7301), 1041 regmap_reg_range(0x7400, 0x7401), 1042 regmap_reg_range(0x7403, 0x7403), 1043 regmap_reg_range(0x7410, 0x7417), 1044 regmap_reg_range(0x7420, 0x7423), 1045 regmap_reg_range(0x7500, 0x7507), 1046 regmap_reg_range(0x7600, 0x7613), 1047 regmap_reg_range(0x7800, 0x780f), 1048 regmap_reg_range(0x7820, 0x7827), 1049 regmap_reg_range(0x7830, 0x7837), 1050 regmap_reg_range(0x7840, 0x784b), 1051 regmap_reg_range(0x7900, 0x7907), 1052 regmap_reg_range(0x7914, 0x791b), 1053 regmap_reg_range(0x7920, 0x7920), 1054 regmap_reg_range(0x7923, 0x7927), 1055 regmap_reg_range(0x7a00, 0x7a03), 1056 regmap_reg_range(0x7a04, 0x7a07), 1057 regmap_reg_range(0x7b00, 0x7b01), 1058 regmap_reg_range(0x7b04, 0x7b04), 1059 regmap_reg_range(0x7c00, 0x7c05), 1060 regmap_reg_range(0x7c08, 0x7c1b), 1061 }; 1062 1063 static const struct regmap_access_table ksz9477_register_set = { 1064 .yes_ranges = ksz9477_valid_regs, 1065 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 1066 }; 1067 1068 static const struct regmap_range ksz9896_valid_regs[] = { 1069 regmap_reg_range(0x0000, 0x0003), 1070 regmap_reg_range(0x0006, 0x0006), 1071 regmap_reg_range(0x0010, 0x001f), 1072 regmap_reg_range(0x0100, 0x0100), 1073 regmap_reg_range(0x0103, 0x0107), 1074 regmap_reg_range(0x010d, 0x010d), 1075 regmap_reg_range(0x0110, 0x0113), 1076 regmap_reg_range(0x0120, 0x0127), 1077 regmap_reg_range(0x0201, 0x0201), 1078 regmap_reg_range(0x0210, 0x0213), 1079 regmap_reg_range(0x0300, 0x0300), 1080 regmap_reg_range(0x0302, 0x030b), 1081 regmap_reg_range(0x0310, 0x031b), 1082 regmap_reg_range(0x0320, 0x032b), 1083 regmap_reg_range(0x0330, 0x0336), 1084 regmap_reg_range(0x0338, 0x033b), 1085 regmap_reg_range(0x033e, 0x033e), 1086 regmap_reg_range(0x0340, 0x035f), 1087 regmap_reg_range(0x0370, 0x0370), 1088 regmap_reg_range(0x0378, 0x0378), 1089 regmap_reg_range(0x037c, 0x037d), 1090 regmap_reg_range(0x0390, 0x0393), 1091 regmap_reg_range(0x0400, 0x040e), 1092 regmap_reg_range(0x0410, 0x042f), 1093 1094 /* port 1 */ 1095 regmap_reg_range(0x1000, 0x1001), 1096 regmap_reg_range(0x1013, 0x1013), 1097 regmap_reg_range(0x1017, 0x1017), 1098 regmap_reg_range(0x101b, 0x101b), 1099 regmap_reg_range(0x101f, 0x1020), 1100 regmap_reg_range(0x1030, 0x1030), 1101 regmap_reg_range(0x1100, 0x1115), 1102 regmap_reg_range(0x111a, 0x111f), 1103 regmap_reg_range(0x1120, 0x112b), 1104 regmap_reg_range(0x1134, 0x113b), 1105 regmap_reg_range(0x113c, 0x113f), 1106 regmap_reg_range(0x1400, 0x1401), 1107 regmap_reg_range(0x1403, 0x1403), 1108 regmap_reg_range(0x1410, 0x1417), 1109 regmap_reg_range(0x1420, 0x1423), 1110 regmap_reg_range(0x1500, 0x1507), 1111 regmap_reg_range(0x1600, 0x1612), 1112 regmap_reg_range(0x1800, 0x180f), 1113 regmap_reg_range(0x1820, 0x1827), 1114 regmap_reg_range(0x1830, 0x1837), 1115 regmap_reg_range(0x1840, 0x184b), 1116 regmap_reg_range(0x1900, 0x1907), 1117 regmap_reg_range(0x1914, 0x1915), 1118 regmap_reg_range(0x1a00, 0x1a03), 1119 regmap_reg_range(0x1a04, 0x1a07), 1120 regmap_reg_range(0x1b00, 0x1b01), 1121 regmap_reg_range(0x1b04, 0x1b04), 1122 1123 /* port 2 */ 1124 regmap_reg_range(0x2000, 0x2001), 1125 regmap_reg_range(0x2013, 0x2013), 1126 regmap_reg_range(0x2017, 0x2017), 1127 regmap_reg_range(0x201b, 0x201b), 1128 regmap_reg_range(0x201f, 0x2020), 1129 regmap_reg_range(0x2030, 0x2030), 1130 regmap_reg_range(0x2100, 0x2115), 1131 regmap_reg_range(0x211a, 0x211f), 1132 regmap_reg_range(0x2120, 0x212b), 1133 regmap_reg_range(0x2134, 0x213b), 1134 regmap_reg_range(0x213c, 0x213f), 1135 regmap_reg_range(0x2400, 0x2401), 1136 regmap_reg_range(0x2403, 0x2403), 1137 regmap_reg_range(0x2410, 0x2417), 1138 regmap_reg_range(0x2420, 0x2423), 1139 regmap_reg_range(0x2500, 0x2507), 1140 regmap_reg_range(0x2600, 0x2612), 1141 regmap_reg_range(0x2800, 0x280f), 1142 regmap_reg_range(0x2820, 0x2827), 1143 regmap_reg_range(0x2830, 0x2837), 1144 regmap_reg_range(0x2840, 0x284b), 1145 regmap_reg_range(0x2900, 0x2907), 1146 regmap_reg_range(0x2914, 0x2915), 1147 regmap_reg_range(0x2a00, 0x2a03), 1148 regmap_reg_range(0x2a04, 0x2a07), 1149 regmap_reg_range(0x2b00, 0x2b01), 1150 regmap_reg_range(0x2b04, 0x2b04), 1151 1152 /* port 3 */ 1153 regmap_reg_range(0x3000, 0x3001), 1154 regmap_reg_range(0x3013, 0x3013), 1155 regmap_reg_range(0x3017, 0x3017), 1156 regmap_reg_range(0x301b, 0x301b), 1157 regmap_reg_range(0x301f, 0x3020), 1158 regmap_reg_range(0x3030, 0x3030), 1159 regmap_reg_range(0x3100, 0x3115), 1160 regmap_reg_range(0x311a, 0x311f), 1161 regmap_reg_range(0x3120, 0x312b), 1162 regmap_reg_range(0x3134, 0x313b), 1163 regmap_reg_range(0x313c, 0x313f), 1164 regmap_reg_range(0x3400, 0x3401), 1165 regmap_reg_range(0x3403, 0x3403), 1166 regmap_reg_range(0x3410, 0x3417), 1167 regmap_reg_range(0x3420, 0x3423), 1168 regmap_reg_range(0x3500, 0x3507), 1169 regmap_reg_range(0x3600, 0x3612), 1170 regmap_reg_range(0x3800, 0x380f), 1171 regmap_reg_range(0x3820, 0x3827), 1172 regmap_reg_range(0x3830, 0x3837), 1173 regmap_reg_range(0x3840, 0x384b), 1174 regmap_reg_range(0x3900, 0x3907), 1175 regmap_reg_range(0x3914, 0x3915), 1176 regmap_reg_range(0x3a00, 0x3a03), 1177 regmap_reg_range(0x3a04, 0x3a07), 1178 regmap_reg_range(0x3b00, 0x3b01), 1179 regmap_reg_range(0x3b04, 0x3b04), 1180 1181 /* port 4 */ 1182 regmap_reg_range(0x4000, 0x4001), 1183 regmap_reg_range(0x4013, 0x4013), 1184 regmap_reg_range(0x4017, 0x4017), 1185 regmap_reg_range(0x401b, 0x401b), 1186 regmap_reg_range(0x401f, 0x4020), 1187 regmap_reg_range(0x4030, 0x4030), 1188 regmap_reg_range(0x4100, 0x4115), 1189 regmap_reg_range(0x411a, 0x411f), 1190 regmap_reg_range(0x4120, 0x412b), 1191 regmap_reg_range(0x4134, 0x413b), 1192 regmap_reg_range(0x413c, 0x413f), 1193 regmap_reg_range(0x4400, 0x4401), 1194 regmap_reg_range(0x4403, 0x4403), 1195 regmap_reg_range(0x4410, 0x4417), 1196 regmap_reg_range(0x4420, 0x4423), 1197 regmap_reg_range(0x4500, 0x4507), 1198 regmap_reg_range(0x4600, 0x4612), 1199 regmap_reg_range(0x4800, 0x480f), 1200 regmap_reg_range(0x4820, 0x4827), 1201 regmap_reg_range(0x4830, 0x4837), 1202 regmap_reg_range(0x4840, 0x484b), 1203 regmap_reg_range(0x4900, 0x4907), 1204 regmap_reg_range(0x4914, 0x4915), 1205 regmap_reg_range(0x4a00, 0x4a03), 1206 regmap_reg_range(0x4a04, 0x4a07), 1207 regmap_reg_range(0x4b00, 0x4b01), 1208 regmap_reg_range(0x4b04, 0x4b04), 1209 1210 /* port 5 */ 1211 regmap_reg_range(0x5000, 0x5001), 1212 regmap_reg_range(0x5013, 0x5013), 1213 regmap_reg_range(0x5017, 0x5017), 1214 regmap_reg_range(0x501b, 0x501b), 1215 regmap_reg_range(0x501f, 0x5020), 1216 regmap_reg_range(0x5030, 0x5030), 1217 regmap_reg_range(0x5100, 0x5115), 1218 regmap_reg_range(0x511a, 0x511f), 1219 regmap_reg_range(0x5120, 0x512b), 1220 regmap_reg_range(0x5134, 0x513b), 1221 regmap_reg_range(0x513c, 0x513f), 1222 regmap_reg_range(0x5400, 0x5401), 1223 regmap_reg_range(0x5403, 0x5403), 1224 regmap_reg_range(0x5410, 0x5417), 1225 regmap_reg_range(0x5420, 0x5423), 1226 regmap_reg_range(0x5500, 0x5507), 1227 regmap_reg_range(0x5600, 0x5612), 1228 regmap_reg_range(0x5800, 0x580f), 1229 regmap_reg_range(0x5820, 0x5827), 1230 regmap_reg_range(0x5830, 0x5837), 1231 regmap_reg_range(0x5840, 0x584b), 1232 regmap_reg_range(0x5900, 0x5907), 1233 regmap_reg_range(0x5914, 0x5915), 1234 regmap_reg_range(0x5a00, 0x5a03), 1235 regmap_reg_range(0x5a04, 0x5a07), 1236 regmap_reg_range(0x5b00, 0x5b01), 1237 regmap_reg_range(0x5b04, 0x5b04), 1238 1239 /* port 6 */ 1240 regmap_reg_range(0x6000, 0x6001), 1241 regmap_reg_range(0x6013, 0x6013), 1242 regmap_reg_range(0x6017, 0x6017), 1243 regmap_reg_range(0x601b, 0x601b), 1244 regmap_reg_range(0x601f, 0x6020), 1245 regmap_reg_range(0x6030, 0x6030), 1246 regmap_reg_range(0x6100, 0x6115), 1247 regmap_reg_range(0x611a, 0x611f), 1248 regmap_reg_range(0x6120, 0x612b), 1249 regmap_reg_range(0x6134, 0x613b), 1250 regmap_reg_range(0x613c, 0x613f), 1251 regmap_reg_range(0x6300, 0x6301), 1252 regmap_reg_range(0x6400, 0x6401), 1253 regmap_reg_range(0x6403, 0x6403), 1254 regmap_reg_range(0x6410, 0x6417), 1255 regmap_reg_range(0x6420, 0x6423), 1256 regmap_reg_range(0x6500, 0x6507), 1257 regmap_reg_range(0x6600, 0x6612), 1258 regmap_reg_range(0x6800, 0x680f), 1259 regmap_reg_range(0x6820, 0x6827), 1260 regmap_reg_range(0x6830, 0x6837), 1261 regmap_reg_range(0x6840, 0x684b), 1262 regmap_reg_range(0x6900, 0x6907), 1263 regmap_reg_range(0x6914, 0x6915), 1264 regmap_reg_range(0x6a00, 0x6a03), 1265 regmap_reg_range(0x6a04, 0x6a07), 1266 regmap_reg_range(0x6b00, 0x6b01), 1267 regmap_reg_range(0x6b04, 0x6b04), 1268 }; 1269 1270 static const struct regmap_access_table ksz9896_register_set = { 1271 .yes_ranges = ksz9896_valid_regs, 1272 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1273 }; 1274 1275 static const struct regmap_range ksz8873_valid_regs[] = { 1276 regmap_reg_range(0x00, 0x01), 1277 /* global control register */ 1278 regmap_reg_range(0x02, 0x0f), 1279 1280 /* port registers */ 1281 regmap_reg_range(0x10, 0x1d), 1282 regmap_reg_range(0x1e, 0x1f), 1283 regmap_reg_range(0x20, 0x2d), 1284 regmap_reg_range(0x2e, 0x2f), 1285 regmap_reg_range(0x30, 0x39), 1286 regmap_reg_range(0x3f, 0x3f), 1287 1288 /* advanced control registers */ 1289 regmap_reg_range(0x60, 0x6f), 1290 regmap_reg_range(0x70, 0x75), 1291 regmap_reg_range(0x76, 0x78), 1292 regmap_reg_range(0x79, 0x7a), 1293 regmap_reg_range(0x7b, 0x83), 1294 regmap_reg_range(0x8e, 0x99), 1295 regmap_reg_range(0x9a, 0xa5), 1296 regmap_reg_range(0xa6, 0xa6), 1297 regmap_reg_range(0xa7, 0xaa), 1298 regmap_reg_range(0xab, 0xae), 1299 regmap_reg_range(0xaf, 0xba), 1300 regmap_reg_range(0xbb, 0xbc), 1301 regmap_reg_range(0xbd, 0xbd), 1302 regmap_reg_range(0xc0, 0xc0), 1303 regmap_reg_range(0xc2, 0xc2), 1304 regmap_reg_range(0xc3, 0xc3), 1305 regmap_reg_range(0xc4, 0xc4), 1306 regmap_reg_range(0xc6, 0xc6), 1307 }; 1308 1309 static const struct regmap_access_table ksz8873_register_set = { 1310 .yes_ranges = ksz8873_valid_regs, 1311 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), 1312 }; 1313 1314 const struct ksz_chip_data ksz_switch_chips[] = { 1315 [KSZ8563] = { 1316 .chip_id = KSZ8563_CHIP_ID, 1317 .dev_name = "KSZ8563", 1318 .num_vlans = 4096, 1319 .num_alus = 4096, 1320 .num_statics = 16, 1321 .cpu_ports = 0x07, /* can be configured as cpu port */ 1322 .port_cnt = 3, /* total port count */ 1323 .port_nirqs = 3, 1324 .num_tx_queues = 4, 1325 .num_ipms = 8, 1326 .tc_cbs_supported = true, 1327 .ops = &ksz9477_dev_ops, 1328 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1329 .mib_names = ksz9477_mib_names, 1330 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1331 .reg_mib_cnt = MIB_COUNTER_NUM, 1332 .regs = ksz9477_regs, 1333 .masks = ksz9477_masks, 1334 .shifts = ksz9477_shifts, 1335 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1336 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1337 .supports_mii = {false, false, true}, 1338 .supports_rmii = {false, false, true}, 1339 .supports_rgmii = {false, false, true}, 1340 .internal_phy = {true, true, false}, 1341 .gbit_capable = {false, false, true}, 1342 .wr_table = &ksz8563_register_set, 1343 .rd_table = &ksz8563_register_set, 1344 }, 1345 1346 [KSZ8795] = { 1347 .chip_id = KSZ8795_CHIP_ID, 1348 .dev_name = "KSZ8795", 1349 .num_vlans = 4096, 1350 .num_alus = 0, 1351 .num_statics = 32, 1352 .cpu_ports = 0x10, /* can be configured as cpu port */ 1353 .port_cnt = 5, /* total cpu and user ports */ 1354 .num_tx_queues = 4, 1355 .num_ipms = 4, 1356 .ops = &ksz87xx_dev_ops, 1357 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1358 .ksz87xx_eee_link_erratum = true, 1359 .mib_names = ksz9477_mib_names, 1360 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1361 .reg_mib_cnt = MIB_COUNTER_NUM, 1362 .regs = ksz8795_regs, 1363 .masks = ksz8795_masks, 1364 .shifts = ksz8795_shifts, 1365 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1366 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1367 .supports_mii = {false, false, false, false, true}, 1368 .supports_rmii = {false, false, false, false, true}, 1369 .supports_rgmii = {false, false, false, false, true}, 1370 .internal_phy = {true, true, true, true, false}, 1371 }, 1372 1373 [KSZ8794] = { 1374 /* WARNING 1375 * ======= 1376 * KSZ8794 is similar to KSZ8795, except the port map 1377 * contains a gap between external and CPU ports, the 1378 * port map is NOT continuous. The per-port register 1379 * map is shifted accordingly too, i.e. registers at 1380 * offset 0x40 are NOT used on KSZ8794 and they ARE 1381 * used on KSZ8795 for external port 3. 1382 * external cpu 1383 * KSZ8794 0,1,2 4 1384 * KSZ8795 0,1,2,3 4 1385 * KSZ8765 0,1,2,3 4 1386 * port_cnt is configured as 5, even though it is 4 1387 */ 1388 .chip_id = KSZ8794_CHIP_ID, 1389 .dev_name = "KSZ8794", 1390 .num_vlans = 4096, 1391 .num_alus = 0, 1392 .num_statics = 32, 1393 .cpu_ports = 0x10, /* can be configured as cpu port */ 1394 .port_cnt = 5, /* total cpu and user ports */ 1395 .num_tx_queues = 4, 1396 .num_ipms = 4, 1397 .ops = &ksz87xx_dev_ops, 1398 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1399 .ksz87xx_eee_link_erratum = true, 1400 .mib_names = ksz9477_mib_names, 1401 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1402 .reg_mib_cnt = MIB_COUNTER_NUM, 1403 .regs = ksz8795_regs, 1404 .masks = ksz8795_masks, 1405 .shifts = ksz8795_shifts, 1406 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1407 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1408 .supports_mii = {false, false, false, false, true}, 1409 .supports_rmii = {false, false, false, false, true}, 1410 .supports_rgmii = {false, false, false, false, true}, 1411 .internal_phy = {true, true, true, false, false}, 1412 }, 1413 1414 [KSZ8765] = { 1415 .chip_id = KSZ8765_CHIP_ID, 1416 .dev_name = "KSZ8765", 1417 .num_vlans = 4096, 1418 .num_alus = 0, 1419 .num_statics = 32, 1420 .cpu_ports = 0x10, /* can be configured as cpu port */ 1421 .port_cnt = 5, /* total cpu and user ports */ 1422 .num_tx_queues = 4, 1423 .num_ipms = 4, 1424 .ops = &ksz87xx_dev_ops, 1425 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1426 .ksz87xx_eee_link_erratum = true, 1427 .mib_names = ksz9477_mib_names, 1428 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1429 .reg_mib_cnt = MIB_COUNTER_NUM, 1430 .regs = ksz8795_regs, 1431 .masks = ksz8795_masks, 1432 .shifts = ksz8795_shifts, 1433 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1434 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1435 .supports_mii = {false, false, false, false, true}, 1436 .supports_rmii = {false, false, false, false, true}, 1437 .supports_rgmii = {false, false, false, false, true}, 1438 .internal_phy = {true, true, true, true, false}, 1439 }, 1440 1441 [KSZ88X3] = { 1442 .chip_id = KSZ88X3_CHIP_ID, 1443 .dev_name = "KSZ8863/KSZ8873", 1444 .num_vlans = 16, 1445 .num_alus = 0, 1446 .num_statics = 8, 1447 .cpu_ports = 0x4, /* can be configured as cpu port */ 1448 .port_cnt = 3, 1449 .num_tx_queues = 4, 1450 .num_ipms = 4, 1451 .ops = &ksz88xx_dev_ops, 1452 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1453 .mib_names = ksz88xx_mib_names, 1454 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1455 .reg_mib_cnt = MIB_COUNTER_NUM, 1456 .regs = ksz8863_regs, 1457 .masks = ksz8863_masks, 1458 .shifts = ksz8863_shifts, 1459 .supports_mii = {false, false, true}, 1460 .supports_rmii = {false, false, true}, 1461 .internal_phy = {true, true, false}, 1462 .wr_table = &ksz8873_register_set, 1463 .rd_table = &ksz8873_register_set, 1464 }, 1465 1466 [KSZ8864] = { 1467 /* WARNING 1468 * ======= 1469 * KSZ8864 is similar to KSZ8895, except the first port 1470 * does not exist. 1471 * external cpu 1472 * KSZ8864 1,2,3 4 1473 * KSZ8895 0,1,2,3 4 1474 * port_cnt is configured as 5, even though it is 4 1475 */ 1476 .chip_id = KSZ8864_CHIP_ID, 1477 .dev_name = "KSZ8864", 1478 .num_vlans = 4096, 1479 .num_alus = 0, 1480 .num_statics = 32, 1481 .cpu_ports = 0x10, /* can be configured as cpu port */ 1482 .port_cnt = 5, /* total cpu and user ports */ 1483 .num_tx_queues = 4, 1484 .num_ipms = 4, 1485 .ops = &ksz88xx_dev_ops, 1486 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1487 .mib_names = ksz88xx_mib_names, 1488 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1489 .reg_mib_cnt = MIB_COUNTER_NUM, 1490 .regs = ksz8895_regs, 1491 .masks = ksz8895_masks, 1492 .shifts = ksz8895_shifts, 1493 .supports_mii = {false, false, false, false, true}, 1494 .supports_rmii = {false, false, false, false, true}, 1495 .internal_phy = {false, true, true, true, false}, 1496 }, 1497 1498 [KSZ8895] = { 1499 .chip_id = KSZ8895_CHIP_ID, 1500 .dev_name = "KSZ8895", 1501 .num_vlans = 4096, 1502 .num_alus = 0, 1503 .num_statics = 32, 1504 .cpu_ports = 0x10, /* can be configured as cpu port */ 1505 .port_cnt = 5, /* total cpu and user ports */ 1506 .num_tx_queues = 4, 1507 .num_ipms = 4, 1508 .ops = &ksz88xx_dev_ops, 1509 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1510 .mib_names = ksz88xx_mib_names, 1511 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1512 .reg_mib_cnt = MIB_COUNTER_NUM, 1513 .regs = ksz8895_regs, 1514 .masks = ksz8895_masks, 1515 .shifts = ksz8895_shifts, 1516 .supports_mii = {false, false, false, false, true}, 1517 .supports_rmii = {false, false, false, false, true}, 1518 .internal_phy = {true, true, true, true, false}, 1519 }, 1520 1521 [KSZ9477] = { 1522 .chip_id = KSZ9477_CHIP_ID, 1523 .dev_name = "KSZ9477", 1524 .num_vlans = 4096, 1525 .num_alus = 4096, 1526 .num_statics = 16, 1527 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1528 .port_cnt = 7, /* total physical port count */ 1529 .port_nirqs = 4, 1530 .num_tx_queues = 4, 1531 .num_ipms = 8, 1532 .tc_cbs_supported = true, 1533 .ops = &ksz9477_dev_ops, 1534 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1535 .phy_errata_9477 = true, 1536 .mib_names = ksz9477_mib_names, 1537 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1538 .reg_mib_cnt = MIB_COUNTER_NUM, 1539 .regs = ksz9477_regs, 1540 .masks = ksz9477_masks, 1541 .shifts = ksz9477_shifts, 1542 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1543 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1544 .supports_mii = {false, false, false, false, 1545 false, true, false}, 1546 .supports_rmii = {false, false, false, false, 1547 false, true, false}, 1548 .supports_rgmii = {false, false, false, false, 1549 false, true, false}, 1550 .internal_phy = {true, true, true, true, 1551 true, false, false}, 1552 .gbit_capable = {true, true, true, true, true, true, true}, 1553 .wr_table = &ksz9477_register_set, 1554 .rd_table = &ksz9477_register_set, 1555 }, 1556 1557 [KSZ9896] = { 1558 .chip_id = KSZ9896_CHIP_ID, 1559 .dev_name = "KSZ9896", 1560 .num_vlans = 4096, 1561 .num_alus = 4096, 1562 .num_statics = 16, 1563 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1564 .port_cnt = 6, /* total physical port count */ 1565 .port_nirqs = 2, 1566 .num_tx_queues = 4, 1567 .num_ipms = 8, 1568 .ops = &ksz9477_dev_ops, 1569 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1570 .phy_errata_9477 = true, 1571 .mib_names = ksz9477_mib_names, 1572 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1573 .reg_mib_cnt = MIB_COUNTER_NUM, 1574 .regs = ksz9477_regs, 1575 .masks = ksz9477_masks, 1576 .shifts = ksz9477_shifts, 1577 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1578 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1579 .supports_mii = {false, false, false, false, 1580 false, true}, 1581 .supports_rmii = {false, false, false, false, 1582 false, true}, 1583 .supports_rgmii = {false, false, false, false, 1584 false, true}, 1585 .internal_phy = {true, true, true, true, 1586 true, false}, 1587 .gbit_capable = {true, true, true, true, true, true}, 1588 .wr_table = &ksz9896_register_set, 1589 .rd_table = &ksz9896_register_set, 1590 }, 1591 1592 [KSZ9897] = { 1593 .chip_id = KSZ9897_CHIP_ID, 1594 .dev_name = "KSZ9897", 1595 .num_vlans = 4096, 1596 .num_alus = 4096, 1597 .num_statics = 16, 1598 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1599 .port_cnt = 7, /* total physical port count */ 1600 .port_nirqs = 2, 1601 .num_tx_queues = 4, 1602 .num_ipms = 8, 1603 .ops = &ksz9477_dev_ops, 1604 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1605 .phy_errata_9477 = true, 1606 .mib_names = ksz9477_mib_names, 1607 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1608 .reg_mib_cnt = MIB_COUNTER_NUM, 1609 .regs = ksz9477_regs, 1610 .masks = ksz9477_masks, 1611 .shifts = ksz9477_shifts, 1612 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1613 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1614 .supports_mii = {false, false, false, false, 1615 false, true, true}, 1616 .supports_rmii = {false, false, false, false, 1617 false, true, true}, 1618 .supports_rgmii = {false, false, false, false, 1619 false, true, true}, 1620 .internal_phy = {true, true, true, true, 1621 true, false, false}, 1622 .gbit_capable = {true, true, true, true, true, true, true}, 1623 }, 1624 1625 [KSZ9893] = { 1626 .chip_id = KSZ9893_CHIP_ID, 1627 .dev_name = "KSZ9893", 1628 .num_vlans = 4096, 1629 .num_alus = 4096, 1630 .num_statics = 16, 1631 .cpu_ports = 0x07, /* can be configured as cpu port */ 1632 .port_cnt = 3, /* total port count */ 1633 .port_nirqs = 2, 1634 .num_tx_queues = 4, 1635 .num_ipms = 8, 1636 .ops = &ksz9477_dev_ops, 1637 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1638 .mib_names = ksz9477_mib_names, 1639 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1640 .reg_mib_cnt = MIB_COUNTER_NUM, 1641 .regs = ksz9477_regs, 1642 .masks = ksz9477_masks, 1643 .shifts = ksz9477_shifts, 1644 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1645 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1646 .supports_mii = {false, false, true}, 1647 .supports_rmii = {false, false, true}, 1648 .supports_rgmii = {false, false, true}, 1649 .internal_phy = {true, true, false}, 1650 .gbit_capable = {true, true, true}, 1651 }, 1652 1653 [KSZ9563] = { 1654 .chip_id = KSZ9563_CHIP_ID, 1655 .dev_name = "KSZ9563", 1656 .num_vlans = 4096, 1657 .num_alus = 4096, 1658 .num_statics = 16, 1659 .cpu_ports = 0x07, /* can be configured as cpu port */ 1660 .port_cnt = 3, /* total port count */ 1661 .port_nirqs = 3, 1662 .num_tx_queues = 4, 1663 .num_ipms = 8, 1664 .tc_cbs_supported = true, 1665 .ops = &ksz9477_dev_ops, 1666 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1667 .mib_names = ksz9477_mib_names, 1668 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1669 .reg_mib_cnt = MIB_COUNTER_NUM, 1670 .regs = ksz9477_regs, 1671 .masks = ksz9477_masks, 1672 .shifts = ksz9477_shifts, 1673 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1674 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1675 .supports_mii = {false, false, true}, 1676 .supports_rmii = {false, false, true}, 1677 .supports_rgmii = {false, false, true}, 1678 .internal_phy = {true, true, false}, 1679 .gbit_capable = {true, true, true}, 1680 }, 1681 1682 [KSZ8567] = { 1683 .chip_id = KSZ8567_CHIP_ID, 1684 .dev_name = "KSZ8567", 1685 .num_vlans = 4096, 1686 .num_alus = 4096, 1687 .num_statics = 16, 1688 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1689 .port_cnt = 7, /* total port count */ 1690 .port_nirqs = 3, 1691 .num_tx_queues = 4, 1692 .num_ipms = 8, 1693 .tc_cbs_supported = true, 1694 .ops = &ksz9477_dev_ops, 1695 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1696 .phy_errata_9477 = true, 1697 .mib_names = ksz9477_mib_names, 1698 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1699 .reg_mib_cnt = MIB_COUNTER_NUM, 1700 .regs = ksz9477_regs, 1701 .masks = ksz9477_masks, 1702 .shifts = ksz9477_shifts, 1703 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1704 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1705 .supports_mii = {false, false, false, false, 1706 false, true, true}, 1707 .supports_rmii = {false, false, false, false, 1708 false, true, true}, 1709 .supports_rgmii = {false, false, false, false, 1710 false, true, true}, 1711 .internal_phy = {true, true, true, true, 1712 true, false, false}, 1713 .gbit_capable = {false, false, false, false, false, 1714 true, true}, 1715 }, 1716 1717 [KSZ9567] = { 1718 .chip_id = KSZ9567_CHIP_ID, 1719 .dev_name = "KSZ9567", 1720 .num_vlans = 4096, 1721 .num_alus = 4096, 1722 .num_statics = 16, 1723 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1724 .port_cnt = 7, /* total physical port count */ 1725 .port_nirqs = 3, 1726 .num_tx_queues = 4, 1727 .num_ipms = 8, 1728 .tc_cbs_supported = true, 1729 .ops = &ksz9477_dev_ops, 1730 .mib_names = ksz9477_mib_names, 1731 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1732 .reg_mib_cnt = MIB_COUNTER_NUM, 1733 .regs = ksz9477_regs, 1734 .masks = ksz9477_masks, 1735 .shifts = ksz9477_shifts, 1736 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1737 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1738 .supports_mii = {false, false, false, false, 1739 false, true, true}, 1740 .supports_rmii = {false, false, false, false, 1741 false, true, true}, 1742 .supports_rgmii = {false, false, false, false, 1743 false, true, true}, 1744 .internal_phy = {true, true, true, true, 1745 true, false, false}, 1746 .gbit_capable = {true, true, true, true, true, true, true}, 1747 }, 1748 1749 [LAN9370] = { 1750 .chip_id = LAN9370_CHIP_ID, 1751 .dev_name = "LAN9370", 1752 .num_vlans = 4096, 1753 .num_alus = 1024, 1754 .num_statics = 256, 1755 .cpu_ports = 0x10, /* can be configured as cpu port */ 1756 .port_cnt = 5, /* total physical port count */ 1757 .port_nirqs = 6, 1758 .num_tx_queues = 8, 1759 .num_ipms = 8, 1760 .tc_cbs_supported = true, 1761 .phy_side_mdio_supported = true, 1762 .ops = &lan937x_dev_ops, 1763 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1764 .mib_names = ksz9477_mib_names, 1765 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1766 .reg_mib_cnt = MIB_COUNTER_NUM, 1767 .regs = ksz9477_regs, 1768 .masks = lan937x_masks, 1769 .shifts = lan937x_shifts, 1770 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1771 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1772 .supports_mii = {false, false, false, false, true}, 1773 .supports_rmii = {false, false, false, false, true}, 1774 .supports_rgmii = {false, false, false, false, true}, 1775 .internal_phy = {true, true, true, true, false}, 1776 }, 1777 1778 [LAN9371] = { 1779 .chip_id = LAN9371_CHIP_ID, 1780 .dev_name = "LAN9371", 1781 .num_vlans = 4096, 1782 .num_alus = 1024, 1783 .num_statics = 256, 1784 .cpu_ports = 0x30, /* can be configured as cpu port */ 1785 .port_cnt = 6, /* total physical port count */ 1786 .port_nirqs = 6, 1787 .num_tx_queues = 8, 1788 .num_ipms = 8, 1789 .tc_cbs_supported = true, 1790 .phy_side_mdio_supported = true, 1791 .ops = &lan937x_dev_ops, 1792 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1793 .mib_names = ksz9477_mib_names, 1794 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1795 .reg_mib_cnt = MIB_COUNTER_NUM, 1796 .regs = ksz9477_regs, 1797 .masks = lan937x_masks, 1798 .shifts = lan937x_shifts, 1799 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1800 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1801 .supports_mii = {false, false, false, false, true, true}, 1802 .supports_rmii = {false, false, false, false, true, true}, 1803 .supports_rgmii = {false, false, false, false, true, true}, 1804 .internal_phy = {true, true, true, true, false, false}, 1805 }, 1806 1807 [LAN9372] = { 1808 .chip_id = LAN9372_CHIP_ID, 1809 .dev_name = "LAN9372", 1810 .num_vlans = 4096, 1811 .num_alus = 1024, 1812 .num_statics = 256, 1813 .cpu_ports = 0x30, /* can be configured as cpu port */ 1814 .port_cnt = 8, /* total physical port count */ 1815 .port_nirqs = 6, 1816 .num_tx_queues = 8, 1817 .num_ipms = 8, 1818 .tc_cbs_supported = true, 1819 .phy_side_mdio_supported = true, 1820 .ops = &lan937x_dev_ops, 1821 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1822 .mib_names = ksz9477_mib_names, 1823 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1824 .reg_mib_cnt = MIB_COUNTER_NUM, 1825 .regs = ksz9477_regs, 1826 .masks = lan937x_masks, 1827 .shifts = lan937x_shifts, 1828 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1829 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1830 .supports_mii = {false, false, false, false, 1831 true, true, false, false}, 1832 .supports_rmii = {false, false, false, false, 1833 true, true, false, false}, 1834 .supports_rgmii = {false, false, false, false, 1835 true, true, false, false}, 1836 .internal_phy = {true, true, true, true, 1837 false, false, true, true}, 1838 }, 1839 1840 [LAN9373] = { 1841 .chip_id = LAN9373_CHIP_ID, 1842 .dev_name = "LAN9373", 1843 .num_vlans = 4096, 1844 .num_alus = 1024, 1845 .num_statics = 256, 1846 .cpu_ports = 0x38, /* can be configured as cpu port */ 1847 .port_cnt = 5, /* total physical port count */ 1848 .port_nirqs = 6, 1849 .num_tx_queues = 8, 1850 .num_ipms = 8, 1851 .tc_cbs_supported = true, 1852 .phy_side_mdio_supported = true, 1853 .ops = &lan937x_dev_ops, 1854 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1855 .mib_names = ksz9477_mib_names, 1856 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1857 .reg_mib_cnt = MIB_COUNTER_NUM, 1858 .regs = ksz9477_regs, 1859 .masks = lan937x_masks, 1860 .shifts = lan937x_shifts, 1861 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1862 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1863 .supports_mii = {false, false, false, false, 1864 true, true, false, false}, 1865 .supports_rmii = {false, false, false, false, 1866 true, true, false, false}, 1867 .supports_rgmii = {false, false, false, false, 1868 true, true, false, false}, 1869 .internal_phy = {true, true, true, false, 1870 false, false, true, true}, 1871 }, 1872 1873 [LAN9374] = { 1874 .chip_id = LAN9374_CHIP_ID, 1875 .dev_name = "LAN9374", 1876 .num_vlans = 4096, 1877 .num_alus = 1024, 1878 .num_statics = 256, 1879 .cpu_ports = 0x30, /* can be configured as cpu port */ 1880 .port_cnt = 8, /* total physical port count */ 1881 .port_nirqs = 6, 1882 .num_tx_queues = 8, 1883 .num_ipms = 8, 1884 .tc_cbs_supported = true, 1885 .phy_side_mdio_supported = true, 1886 .ops = &lan937x_dev_ops, 1887 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1888 .mib_names = ksz9477_mib_names, 1889 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1890 .reg_mib_cnt = MIB_COUNTER_NUM, 1891 .regs = ksz9477_regs, 1892 .masks = lan937x_masks, 1893 .shifts = lan937x_shifts, 1894 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1895 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1896 .supports_mii = {false, false, false, false, 1897 true, true, false, false}, 1898 .supports_rmii = {false, false, false, false, 1899 true, true, false, false}, 1900 .supports_rgmii = {false, false, false, false, 1901 true, true, false, false}, 1902 .internal_phy = {true, true, true, true, 1903 false, false, true, true}, 1904 }, 1905 1906 [LAN9646] = { 1907 .chip_id = LAN9646_CHIP_ID, 1908 .dev_name = "LAN9646", 1909 .num_vlans = 4096, 1910 .num_alus = 4096, 1911 .num_statics = 16, 1912 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1913 .port_cnt = 7, /* total physical port count */ 1914 .port_nirqs = 4, 1915 .num_tx_queues = 4, 1916 .num_ipms = 8, 1917 .ops = &ksz9477_dev_ops, 1918 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1919 .phy_errata_9477 = true, 1920 .mib_names = ksz9477_mib_names, 1921 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1922 .reg_mib_cnt = MIB_COUNTER_NUM, 1923 .regs = ksz9477_regs, 1924 .masks = ksz9477_masks, 1925 .shifts = ksz9477_shifts, 1926 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1927 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1928 .supports_mii = {false, false, false, false, 1929 false, true, true}, 1930 .supports_rmii = {false, false, false, false, 1931 false, true, true}, 1932 .supports_rgmii = {false, false, false, false, 1933 false, true, true}, 1934 .internal_phy = {true, true, true, true, 1935 true, false, false}, 1936 .gbit_capable = {true, true, true, true, true, true, true}, 1937 .wr_table = &ksz9477_register_set, 1938 .rd_table = &ksz9477_register_set, 1939 }, 1940 }; 1941 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1942 1943 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1944 { 1945 int i; 1946 1947 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1948 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1949 1950 if (chip->chip_id == prod_num) 1951 return chip; 1952 } 1953 1954 return NULL; 1955 } 1956 1957 static int ksz_check_device_id(struct ksz_device *dev) 1958 { 1959 const struct ksz_chip_data *expected_chip_data; 1960 u32 expected_chip_id; 1961 1962 if (dev->pdata) { 1963 expected_chip_id = dev->pdata->chip_id; 1964 expected_chip_data = ksz_lookup_info(expected_chip_id); 1965 if (WARN_ON(!expected_chip_data)) 1966 return -ENODEV; 1967 } else { 1968 expected_chip_data = of_device_get_match_data(dev->dev); 1969 expected_chip_id = expected_chip_data->chip_id; 1970 } 1971 1972 if (expected_chip_id != dev->chip_id) { 1973 dev_err(dev->dev, 1974 "Device tree specifies chip %s but found %s, please fix it!\n", 1975 expected_chip_data->dev_name, dev->info->dev_name); 1976 return -ENODEV; 1977 } 1978 1979 return 0; 1980 } 1981 1982 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1983 struct phylink_config *config) 1984 { 1985 struct ksz_device *dev = ds->priv; 1986 1987 if (dev->info->supports_mii[port]) 1988 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1989 1990 if (dev->info->supports_rmii[port]) 1991 __set_bit(PHY_INTERFACE_MODE_RMII, 1992 config->supported_interfaces); 1993 1994 if (dev->info->supports_rgmii[port]) 1995 phy_interface_set_rgmii(config->supported_interfaces); 1996 1997 if (dev->info->internal_phy[port]) { 1998 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1999 config->supported_interfaces); 2000 /* Compatibility for phylib's default interface type when the 2001 * phy-mode property is absent 2002 */ 2003 __set_bit(PHY_INTERFACE_MODE_GMII, 2004 config->supported_interfaces); 2005 } 2006 2007 if (dev->dev_ops->get_caps) 2008 dev->dev_ops->get_caps(dev, port, config); 2009 } 2010 2011 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 2012 { 2013 struct ethtool_pause_stats *pstats; 2014 struct rtnl_link_stats64 *stats; 2015 struct ksz_stats_raw *raw; 2016 struct ksz_port_mib *mib; 2017 int ret; 2018 2019 mib = &dev->ports[port].mib; 2020 stats = &mib->stats64; 2021 pstats = &mib->pause_stats; 2022 raw = (struct ksz_stats_raw *)mib->counters; 2023 2024 spin_lock(&mib->stats64_lock); 2025 2026 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 2027 raw->rx_pause; 2028 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2029 raw->tx_pause; 2030 2031 /* HW counters are counting bytes + FCS which is not acceptable 2032 * for rtnl_link_stats64 interface 2033 */ 2034 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 2035 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 2036 2037 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2038 raw->rx_oversize; 2039 2040 stats->rx_crc_errors = raw->rx_crc_err; 2041 stats->rx_frame_errors = raw->rx_align_err; 2042 stats->rx_dropped = raw->rx_discards; 2043 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2044 stats->rx_frame_errors + stats->rx_dropped; 2045 2046 stats->tx_window_errors = raw->tx_late_col; 2047 stats->tx_fifo_errors = raw->tx_discards; 2048 stats->tx_aborted_errors = raw->tx_exc_col; 2049 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2050 stats->tx_aborted_errors; 2051 2052 stats->multicast = raw->rx_mcast; 2053 stats->collisions = raw->tx_total_col; 2054 2055 pstats->tx_pause_frames = raw->tx_pause; 2056 pstats->rx_pause_frames = raw->rx_pause; 2057 2058 spin_unlock(&mib->stats64_lock); 2059 2060 if (dev->info->phy_errata_9477) { 2061 ret = ksz9477_errata_monitor(dev, port, raw->tx_late_col); 2062 if (ret) 2063 dev_err(dev->dev, "Failed to monitor transmission halt\n"); 2064 } 2065 } 2066 2067 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 2068 { 2069 struct ethtool_pause_stats *pstats; 2070 struct rtnl_link_stats64 *stats; 2071 struct ksz88xx_stats_raw *raw; 2072 struct ksz_port_mib *mib; 2073 2074 mib = &dev->ports[port].mib; 2075 stats = &mib->stats64; 2076 pstats = &mib->pause_stats; 2077 raw = (struct ksz88xx_stats_raw *)mib->counters; 2078 2079 spin_lock(&mib->stats64_lock); 2080 2081 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 2082 raw->rx_pause; 2083 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2084 raw->tx_pause; 2085 2086 /* HW counters are counting bytes + FCS which is not acceptable 2087 * for rtnl_link_stats64 interface 2088 */ 2089 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 2090 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 2091 2092 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2093 raw->rx_oversize; 2094 2095 stats->rx_crc_errors = raw->rx_crc_err; 2096 stats->rx_frame_errors = raw->rx_align_err; 2097 stats->rx_dropped = raw->rx_discards; 2098 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2099 stats->rx_frame_errors + stats->rx_dropped; 2100 2101 stats->tx_window_errors = raw->tx_late_col; 2102 stats->tx_fifo_errors = raw->tx_discards; 2103 stats->tx_aborted_errors = raw->tx_exc_col; 2104 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2105 stats->tx_aborted_errors; 2106 2107 stats->multicast = raw->rx_mcast; 2108 stats->collisions = raw->tx_total_col; 2109 2110 pstats->tx_pause_frames = raw->tx_pause; 2111 pstats->rx_pause_frames = raw->rx_pause; 2112 2113 spin_unlock(&mib->stats64_lock); 2114 } 2115 2116 static void ksz_get_stats64(struct dsa_switch *ds, int port, 2117 struct rtnl_link_stats64 *s) 2118 { 2119 struct ksz_device *dev = ds->priv; 2120 struct ksz_port_mib *mib; 2121 2122 mib = &dev->ports[port].mib; 2123 2124 spin_lock(&mib->stats64_lock); 2125 memcpy(s, &mib->stats64, sizeof(*s)); 2126 spin_unlock(&mib->stats64_lock); 2127 } 2128 2129 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 2130 struct ethtool_pause_stats *pause_stats) 2131 { 2132 struct ksz_device *dev = ds->priv; 2133 struct ksz_port_mib *mib; 2134 2135 mib = &dev->ports[port].mib; 2136 2137 spin_lock(&mib->stats64_lock); 2138 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 2139 spin_unlock(&mib->stats64_lock); 2140 } 2141 2142 static void ksz_get_strings(struct dsa_switch *ds, int port, 2143 u32 stringset, uint8_t *buf) 2144 { 2145 struct ksz_device *dev = ds->priv; 2146 int i; 2147 2148 if (stringset != ETH_SS_STATS) 2149 return; 2150 2151 for (i = 0; i < dev->info->mib_cnt; i++) 2152 ethtool_puts(&buf, dev->info->mib_names[i].string); 2153 } 2154 2155 /** 2156 * ksz_update_port_member - Adjust port forwarding rules based on STP state and 2157 * isolation settings. 2158 * @dev: A pointer to the struct ksz_device representing the device. 2159 * @port: The port number to adjust. 2160 * 2161 * This function dynamically adjusts the port membership configuration for a 2162 * specified port and other device ports, based on Spanning Tree Protocol (STP) 2163 * states and port isolation settings. Each port, including the CPU port, has a 2164 * membership register, represented as a bitfield, where each bit corresponds 2165 * to a port number. A set bit indicates permission to forward frames to that 2166 * port. This function iterates over all ports, updating the membership register 2167 * to reflect current forwarding permissions: 2168 * 2169 * 1. Forwards frames only to ports that are part of the same bridge group and 2170 * in the BR_STATE_FORWARDING state. 2171 * 2. Takes into account the isolation status of ports; ports in the 2172 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward 2173 * frames to each other, even if they are in the same bridge group. 2174 * 3. Ensures that the CPU port is included in the membership based on its 2175 * upstream port configuration, allowing for management and control traffic 2176 * to flow as required. 2177 */ 2178 static void ksz_update_port_member(struct ksz_device *dev, int port) 2179 { 2180 struct ksz_port *p = &dev->ports[port]; 2181 struct dsa_switch *ds = dev->ds; 2182 u8 port_member = 0, cpu_port; 2183 const struct dsa_port *dp; 2184 int i, j; 2185 2186 if (!dsa_is_user_port(ds, port)) 2187 return; 2188 2189 dp = dsa_to_port(ds, port); 2190 cpu_port = BIT(dsa_upstream_port(ds, port)); 2191 2192 for (i = 0; i < ds->num_ports; i++) { 2193 const struct dsa_port *other_dp = dsa_to_port(ds, i); 2194 struct ksz_port *other_p = &dev->ports[i]; 2195 u8 val = 0; 2196 2197 if (!dsa_is_user_port(ds, i)) 2198 continue; 2199 if (port == i) 2200 continue; 2201 if (!dsa_port_bridge_same(dp, other_dp)) 2202 continue; 2203 if (other_p->stp_state != BR_STATE_FORWARDING) 2204 continue; 2205 2206 /* At this point we know that "port" and "other" port [i] are in 2207 * the same bridge group and that "other" port [i] is in 2208 * forwarding stp state. If "port" is also in forwarding stp 2209 * state, we can allow forwarding from port [port] to port [i]. 2210 * Except if both ports are isolated. 2211 */ 2212 if (p->stp_state == BR_STATE_FORWARDING && 2213 !(p->isolated && other_p->isolated)) { 2214 val |= BIT(port); 2215 port_member |= BIT(i); 2216 } 2217 2218 /* Retain port [i]'s relationship to other ports than [port] */ 2219 for (j = 0; j < ds->num_ports; j++) { 2220 const struct dsa_port *third_dp; 2221 struct ksz_port *third_p; 2222 2223 if (j == i) 2224 continue; 2225 if (j == port) 2226 continue; 2227 if (!dsa_is_user_port(ds, j)) 2228 continue; 2229 third_p = &dev->ports[j]; 2230 if (third_p->stp_state != BR_STATE_FORWARDING) 2231 continue; 2232 2233 third_dp = dsa_to_port(ds, j); 2234 2235 /* Now we updating relation of the "other" port [i] to 2236 * the "third" port [j]. We already know that "other" 2237 * port [i] is in forwarding stp state and that "third" 2238 * port [j] is in forwarding stp state too. 2239 * We need to check if "other" port [i] and "third" port 2240 * [j] are in the same bridge group and not isolated 2241 * before allowing forwarding from port [i] to port [j]. 2242 */ 2243 if (dsa_port_bridge_same(other_dp, third_dp) && 2244 !(other_p->isolated && third_p->isolated)) 2245 val |= BIT(j); 2246 } 2247 2248 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 2249 } 2250 2251 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 2252 } 2253 2254 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 2255 { 2256 struct ksz_device *dev = bus->priv; 2257 u16 val; 2258 int ret; 2259 2260 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 2261 if (ret < 0) 2262 return ret; 2263 2264 return val; 2265 } 2266 2267 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 2268 u16 val) 2269 { 2270 struct ksz_device *dev = bus->priv; 2271 2272 return dev->dev_ops->w_phy(dev, addr, regnum, val); 2273 } 2274 2275 /** 2276 * ksz_parent_mdio_read - Read data from a PHY register on the parent MDIO bus. 2277 * @bus: MDIO bus structure. 2278 * @addr: PHY address on the parent MDIO bus. 2279 * @regnum: Register number to read. 2280 * 2281 * This function provides a direct read operation on the parent MDIO bus for 2282 * accessing PHY registers. By bypassing SPI or I2C, it uses the parent MDIO bus 2283 * to retrieve data from the PHY registers at the specified address and register 2284 * number. 2285 * 2286 * Return: Value of the PHY register, or a negative error code on failure. 2287 */ 2288 static int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum) 2289 { 2290 struct ksz_device *dev = bus->priv; 2291 2292 return mdiobus_read_nested(dev->parent_mdio_bus, addr, regnum); 2293 } 2294 2295 /** 2296 * ksz_parent_mdio_write - Write data to a PHY register on the parent MDIO bus. 2297 * @bus: MDIO bus structure. 2298 * @addr: PHY address on the parent MDIO bus. 2299 * @regnum: Register number to write to. 2300 * @val: Value to write to the PHY register. 2301 * 2302 * This function provides a direct write operation on the parent MDIO bus for 2303 * accessing PHY registers. Bypassing SPI or I2C, it uses the parent MDIO bus 2304 * to modify the PHY register values at the specified address. 2305 * 2306 * Return: 0 on success, or a negative error code on failure. 2307 */ 2308 static int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum, 2309 u16 val) 2310 { 2311 struct ksz_device *dev = bus->priv; 2312 2313 return mdiobus_write_nested(dev->parent_mdio_bus, addr, regnum, val); 2314 } 2315 2316 /** 2317 * ksz_phy_addr_to_port - Map a PHY address to the corresponding switch port. 2318 * @dev: Pointer to device structure. 2319 * @addr: PHY address to map to a port. 2320 * 2321 * This function finds the corresponding switch port for a given PHY address by 2322 * iterating over all user ports on the device. It checks if a port's PHY 2323 * address in `phy_addr_map` matches the specified address and if the port 2324 * contains an internal PHY. If a match is found, the index of the port is 2325 * returned. 2326 * 2327 * Return: Port index on success, or -EINVAL if no matching port is found. 2328 */ 2329 static int ksz_phy_addr_to_port(struct ksz_device *dev, int addr) 2330 { 2331 struct dsa_switch *ds = dev->ds; 2332 struct dsa_port *dp; 2333 2334 dsa_switch_for_each_user_port(dp, ds) { 2335 if (dev->info->internal_phy[dp->index] && 2336 dev->phy_addr_map[dp->index] == addr) 2337 return dp->index; 2338 } 2339 2340 return -EINVAL; 2341 } 2342 2343 /** 2344 * ksz_irq_phy_setup - Configure IRQs for PHYs in the KSZ device. 2345 * @dev: Pointer to the KSZ device structure. 2346 * 2347 * Sets up IRQs for each active PHY connected to the KSZ switch by mapping the 2348 * appropriate IRQs for each PHY and assigning them to the `user_mii_bus` in 2349 * the DSA switch structure. Each IRQ is mapped based on the port's IRQ domain. 2350 * 2351 * Return: 0 on success, or a negative error code on failure. 2352 */ 2353 static int ksz_irq_phy_setup(struct ksz_device *dev) 2354 { 2355 struct dsa_switch *ds = dev->ds; 2356 int phy, port; 2357 int irq; 2358 int ret; 2359 2360 for (phy = 0; phy < PHY_MAX_ADDR; phy++) { 2361 if (BIT(phy) & ds->phys_mii_mask) { 2362 port = ksz_phy_addr_to_port(dev, phy); 2363 if (port < 0) { 2364 ret = port; 2365 goto out; 2366 } 2367 2368 irq = irq_find_mapping(dev->ports[port].pirq.domain, 2369 PORT_SRC_PHY_INT); 2370 if (irq < 0) { 2371 ret = irq; 2372 goto out; 2373 } 2374 ds->user_mii_bus->irq[phy] = irq; 2375 } 2376 } 2377 return 0; 2378 out: 2379 while (phy--) 2380 if (BIT(phy) & ds->phys_mii_mask) 2381 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2382 2383 return ret; 2384 } 2385 2386 /** 2387 * ksz_irq_phy_free - Release IRQ mappings for PHYs in the KSZ device. 2388 * @dev: Pointer to the KSZ device structure. 2389 * 2390 * Releases any IRQ mappings previously assigned to active PHYs in the KSZ 2391 * switch by disposing of each mapped IRQ in the `user_mii_bus` structure. 2392 */ 2393 static void ksz_irq_phy_free(struct ksz_device *dev) 2394 { 2395 struct dsa_switch *ds = dev->ds; 2396 int phy; 2397 2398 for (phy = 0; phy < PHY_MAX_ADDR; phy++) 2399 if (BIT(phy) & ds->phys_mii_mask) 2400 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2401 } 2402 2403 /** 2404 * ksz_parse_dt_phy_config - Parse and validate PHY configuration from DT 2405 * @dev: pointer to the KSZ device structure 2406 * @bus: pointer to the MII bus structure 2407 * @mdio_np: pointer to the MDIO node in the device tree 2408 * 2409 * This function parses and validates PHY configurations for each user port 2410 * defined in the device tree for a KSZ switch device. It verifies that the 2411 * `phy-handle` properties are correctly set and that the internal PHYs match 2412 * expected addresses and parent nodes. Sets up the PHY mask in the MII bus if 2413 * all validations pass. Logs error messages for any mismatches or missing data. 2414 * 2415 * Return: 0 on success, or a negative error code on failure. 2416 */ 2417 static int ksz_parse_dt_phy_config(struct ksz_device *dev, struct mii_bus *bus, 2418 struct device_node *mdio_np) 2419 { 2420 struct device_node *phy_node, *phy_parent_node; 2421 bool phys_are_valid = true; 2422 struct dsa_port *dp; 2423 u32 phy_addr; 2424 int ret; 2425 2426 dsa_switch_for_each_user_port(dp, dev->ds) { 2427 if (!dev->info->internal_phy[dp->index]) 2428 continue; 2429 2430 phy_node = of_parse_phandle(dp->dn, "phy-handle", 0); 2431 if (!phy_node) { 2432 dev_err(dev->dev, "failed to parse phy-handle for port %d.\n", 2433 dp->index); 2434 phys_are_valid = false; 2435 continue; 2436 } 2437 2438 phy_parent_node = of_get_parent(phy_node); 2439 if (!phy_parent_node) { 2440 dev_err(dev->dev, "failed to get PHY-parent node for port %d\n", 2441 dp->index); 2442 phys_are_valid = false; 2443 } else if (phy_parent_node != mdio_np) { 2444 dev_err(dev->dev, "PHY-parent node mismatch for port %d, expected %pOF, got %pOF\n", 2445 dp->index, mdio_np, phy_parent_node); 2446 phys_are_valid = false; 2447 } else { 2448 ret = of_property_read_u32(phy_node, "reg", &phy_addr); 2449 if (ret < 0) { 2450 dev_err(dev->dev, "failed to read PHY address for port %d. Error %d\n", 2451 dp->index, ret); 2452 phys_are_valid = false; 2453 } else if (phy_addr != dev->phy_addr_map[dp->index]) { 2454 dev_err(dev->dev, "PHY address mismatch for port %d, expected 0x%x, got 0x%x\n", 2455 dp->index, dev->phy_addr_map[dp->index], 2456 phy_addr); 2457 phys_are_valid = false; 2458 } else { 2459 bus->phy_mask |= BIT(phy_addr); 2460 } 2461 } 2462 2463 of_node_put(phy_node); 2464 of_node_put(phy_parent_node); 2465 } 2466 2467 if (!phys_are_valid) 2468 return -EINVAL; 2469 2470 return 0; 2471 } 2472 2473 /** 2474 * ksz_mdio_register - Register and configure the MDIO bus for the KSZ device. 2475 * @dev: Pointer to the KSZ device structure. 2476 * 2477 * This function sets up and registers an MDIO bus for the KSZ switch device, 2478 * allowing access to its internal PHYs. If the device supports side MDIO, 2479 * the function will configure the external MDIO controller specified by the 2480 * "mdio-parent-bus" device tree property to directly manage internal PHYs. 2481 * Otherwise, SPI or I2C access is set up for PHY access. 2482 * 2483 * Return: 0 on success, or a negative error code on failure. 2484 */ 2485 static int ksz_mdio_register(struct ksz_device *dev) 2486 { 2487 struct device_node *parent_bus_node; 2488 struct mii_bus *parent_bus = NULL; 2489 struct dsa_switch *ds = dev->ds; 2490 struct device_node *mdio_np; 2491 struct mii_bus *bus; 2492 int ret, i; 2493 2494 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 2495 if (!mdio_np) 2496 return 0; 2497 2498 parent_bus_node = of_parse_phandle(mdio_np, "mdio-parent-bus", 0); 2499 if (parent_bus_node && !dev->info->phy_side_mdio_supported) { 2500 dev_err(dev->dev, "Side MDIO bus is not supported for this HW, ignoring 'mdio-parent-bus' property.\n"); 2501 ret = -EINVAL; 2502 2503 goto put_mdio_node; 2504 } else if (parent_bus_node) { 2505 parent_bus = of_mdio_find_bus(parent_bus_node); 2506 if (!parent_bus) { 2507 ret = -EPROBE_DEFER; 2508 2509 goto put_mdio_node; 2510 } 2511 2512 dev->parent_mdio_bus = parent_bus; 2513 } 2514 2515 bus = devm_mdiobus_alloc(ds->dev); 2516 if (!bus) { 2517 ret = -ENOMEM; 2518 goto put_mdio_node; 2519 } 2520 2521 if (dev->dev_ops->mdio_bus_preinit) { 2522 ret = dev->dev_ops->mdio_bus_preinit(dev, !!parent_bus); 2523 if (ret) 2524 goto put_mdio_node; 2525 } 2526 2527 if (dev->dev_ops->create_phy_addr_map) { 2528 ret = dev->dev_ops->create_phy_addr_map(dev, !!parent_bus); 2529 if (ret) 2530 goto put_mdio_node; 2531 } else { 2532 for (i = 0; i < dev->info->port_cnt; i++) 2533 dev->phy_addr_map[i] = i; 2534 } 2535 2536 bus->priv = dev; 2537 if (parent_bus) { 2538 bus->read = ksz_parent_mdio_read; 2539 bus->write = ksz_parent_mdio_write; 2540 bus->name = "KSZ side MDIO"; 2541 snprintf(bus->id, MII_BUS_ID_SIZE, "ksz-side-mdio-%d", 2542 ds->index); 2543 } else { 2544 bus->read = ksz_sw_mdio_read; 2545 bus->write = ksz_sw_mdio_write; 2546 bus->name = "ksz user smi"; 2547 if (ds->dst->index != 0) { 2548 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d-%d", ds->dst->index, ds->index); 2549 } else { 2550 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 2551 } 2552 } 2553 2554 ret = ksz_parse_dt_phy_config(dev, bus, mdio_np); 2555 if (ret) 2556 goto put_mdio_node; 2557 2558 ds->phys_mii_mask = bus->phy_mask; 2559 bus->parent = ds->dev; 2560 2561 ds->user_mii_bus = bus; 2562 2563 if (dev->irq > 0) { 2564 ret = ksz_irq_phy_setup(dev); 2565 if (ret) 2566 goto put_mdio_node; 2567 } 2568 2569 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 2570 if (ret) { 2571 dev_err(ds->dev, "unable to register MDIO bus %s\n", 2572 bus->id); 2573 if (dev->irq > 0) 2574 ksz_irq_phy_free(dev); 2575 } 2576 2577 put_mdio_node: 2578 of_node_put(mdio_np); 2579 of_node_put(parent_bus_node); 2580 2581 return ret; 2582 } 2583 2584 static void ksz_irq_mask(struct irq_data *d) 2585 { 2586 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2587 2588 kirq->masked |= BIT(d->hwirq); 2589 } 2590 2591 static void ksz_irq_unmask(struct irq_data *d) 2592 { 2593 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2594 2595 kirq->masked &= ~BIT(d->hwirq); 2596 } 2597 2598 static void ksz_irq_bus_lock(struct irq_data *d) 2599 { 2600 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2601 2602 mutex_lock(&kirq->dev->lock_irq); 2603 } 2604 2605 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 2606 { 2607 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2608 struct ksz_device *dev = kirq->dev; 2609 int ret; 2610 2611 ret = ksz_write8(dev, kirq->reg_mask, kirq->masked); 2612 if (ret) 2613 dev_err(dev->dev, "failed to change IRQ mask\n"); 2614 2615 mutex_unlock(&dev->lock_irq); 2616 } 2617 2618 static const struct irq_chip ksz_irq_chip = { 2619 .name = "ksz-irq", 2620 .irq_mask = ksz_irq_mask, 2621 .irq_unmask = ksz_irq_unmask, 2622 .irq_bus_lock = ksz_irq_bus_lock, 2623 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 2624 }; 2625 2626 static int ksz_irq_domain_map(struct irq_domain *d, 2627 unsigned int irq, irq_hw_number_t hwirq) 2628 { 2629 irq_set_chip_data(irq, d->host_data); 2630 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 2631 irq_set_noprobe(irq); 2632 2633 return 0; 2634 } 2635 2636 static const struct irq_domain_ops ksz_irq_domain_ops = { 2637 .map = ksz_irq_domain_map, 2638 .xlate = irq_domain_xlate_twocell, 2639 }; 2640 2641 static void ksz_irq_free(struct ksz_irq *kirq) 2642 { 2643 int irq, virq; 2644 2645 free_irq(kirq->irq_num, kirq); 2646 2647 for (irq = 0; irq < kirq->nirqs; irq++) { 2648 virq = irq_find_mapping(kirq->domain, irq); 2649 irq_dispose_mapping(virq); 2650 } 2651 2652 irq_domain_remove(kirq->domain); 2653 } 2654 2655 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 2656 { 2657 struct ksz_irq *kirq = dev_id; 2658 unsigned int nhandled = 0; 2659 struct ksz_device *dev; 2660 unsigned int sub_irq; 2661 u8 data; 2662 int ret; 2663 u8 n; 2664 2665 dev = kirq->dev; 2666 2667 /* Read interrupt status register */ 2668 ret = ksz_read8(dev, kirq->reg_status, &data); 2669 if (ret) 2670 goto out; 2671 2672 for (n = 0; n < kirq->nirqs; ++n) { 2673 if (data & BIT(n)) { 2674 sub_irq = irq_find_mapping(kirq->domain, n); 2675 handle_nested_irq(sub_irq); 2676 ++nhandled; 2677 } 2678 } 2679 out: 2680 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2681 } 2682 2683 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 2684 { 2685 int ret, n; 2686 2687 kirq->dev = dev; 2688 kirq->masked = ~0; 2689 2690 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0, 2691 &ksz_irq_domain_ops, kirq); 2692 if (!kirq->domain) 2693 return -ENOMEM; 2694 2695 for (n = 0; n < kirq->nirqs; n++) 2696 irq_create_mapping(kirq->domain, n); 2697 2698 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2699 IRQF_ONESHOT, kirq->name, kirq); 2700 if (ret) 2701 goto out; 2702 2703 return 0; 2704 2705 out: 2706 ksz_irq_free(kirq); 2707 2708 return ret; 2709 } 2710 2711 static int ksz_girq_setup(struct ksz_device *dev) 2712 { 2713 struct ksz_irq *girq = &dev->girq; 2714 2715 girq->nirqs = dev->info->port_cnt; 2716 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2717 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2718 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2719 2720 girq->irq_num = dev->irq; 2721 2722 return ksz_irq_common_setup(dev, girq); 2723 } 2724 2725 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2726 { 2727 struct ksz_irq *pirq = &dev->ports[p].pirq; 2728 2729 pirq->nirqs = dev->info->port_nirqs; 2730 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2731 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2732 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2733 2734 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2735 if (pirq->irq_num < 0) 2736 return pirq->irq_num; 2737 2738 return ksz_irq_common_setup(dev, pirq); 2739 } 2740 2741 static int ksz_parse_drive_strength(struct ksz_device *dev); 2742 2743 static int ksz_setup(struct dsa_switch *ds) 2744 { 2745 struct ksz_device *dev = ds->priv; 2746 struct dsa_port *dp; 2747 struct ksz_port *p; 2748 const u16 *regs; 2749 int ret; 2750 2751 regs = dev->info->regs; 2752 2753 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2754 dev->info->num_vlans, GFP_KERNEL); 2755 if (!dev->vlan_cache) 2756 return -ENOMEM; 2757 2758 ret = dev->dev_ops->reset(dev); 2759 if (ret) { 2760 dev_err(ds->dev, "failed to reset switch\n"); 2761 return ret; 2762 } 2763 2764 ret = ksz_parse_drive_strength(dev); 2765 if (ret) 2766 return ret; 2767 2768 /* set broadcast storm protection 10% rate */ 2769 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2770 BROADCAST_STORM_RATE, 2771 (BROADCAST_STORM_VALUE * 2772 BROADCAST_STORM_PROT_RATE) / 100); 2773 2774 dev->dev_ops->config_cpu_port(ds); 2775 2776 dev->dev_ops->enable_stp_addr(dev); 2777 2778 ds->num_tx_queues = dev->info->num_tx_queues; 2779 2780 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 2781 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2782 2783 ksz_init_mib_timer(dev); 2784 2785 ds->configure_vlan_while_not_filtering = false; 2786 ds->dscp_prio_mapping_is_global = true; 2787 2788 if (dev->dev_ops->setup) { 2789 ret = dev->dev_ops->setup(ds); 2790 if (ret) 2791 return ret; 2792 } 2793 2794 /* Start with learning disabled on standalone user ports, and enabled 2795 * on the CPU port. In lack of other finer mechanisms, learning on the 2796 * CPU port will avoid flooding bridge local addresses on the network 2797 * in some cases. 2798 */ 2799 p = &dev->ports[dev->cpu_port]; 2800 p->learning = true; 2801 2802 if (dev->irq > 0) { 2803 ret = ksz_girq_setup(dev); 2804 if (ret) 2805 return ret; 2806 2807 dsa_switch_for_each_user_port(dp, dev->ds) { 2808 ret = ksz_pirq_setup(dev, dp->index); 2809 if (ret) 2810 goto out_girq; 2811 2812 ret = ksz_ptp_irq_setup(ds, dp->index); 2813 if (ret) 2814 goto out_pirq; 2815 } 2816 } 2817 2818 ret = ksz_ptp_clock_register(ds); 2819 if (ret) { 2820 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret); 2821 goto out_ptpirq; 2822 } 2823 2824 ret = ksz_mdio_register(dev); 2825 if (ret < 0) { 2826 dev_err(dev->dev, "failed to register the mdio"); 2827 goto out_ptp_clock_unregister; 2828 } 2829 2830 ret = ksz_dcb_init(dev); 2831 if (ret) 2832 goto out_ptp_clock_unregister; 2833 2834 /* start switch */ 2835 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 2836 SW_START, SW_START); 2837 2838 return 0; 2839 2840 out_ptp_clock_unregister: 2841 ksz_ptp_clock_unregister(ds); 2842 out_ptpirq: 2843 if (dev->irq > 0) 2844 dsa_switch_for_each_user_port(dp, dev->ds) 2845 ksz_ptp_irq_free(ds, dp->index); 2846 out_pirq: 2847 if (dev->irq > 0) 2848 dsa_switch_for_each_user_port(dp, dev->ds) 2849 ksz_irq_free(&dev->ports[dp->index].pirq); 2850 out_girq: 2851 if (dev->irq > 0) 2852 ksz_irq_free(&dev->girq); 2853 2854 return ret; 2855 } 2856 2857 static void ksz_teardown(struct dsa_switch *ds) 2858 { 2859 struct ksz_device *dev = ds->priv; 2860 struct dsa_port *dp; 2861 2862 ksz_ptp_clock_unregister(ds); 2863 2864 if (dev->irq > 0) { 2865 dsa_switch_for_each_user_port(dp, dev->ds) { 2866 ksz_ptp_irq_free(ds, dp->index); 2867 2868 ksz_irq_free(&dev->ports[dp->index].pirq); 2869 } 2870 2871 ksz_irq_free(&dev->girq); 2872 } 2873 2874 if (dev->dev_ops->teardown) 2875 dev->dev_ops->teardown(ds); 2876 } 2877 2878 static void port_r_cnt(struct ksz_device *dev, int port) 2879 { 2880 struct ksz_port_mib *mib = &dev->ports[port].mib; 2881 u64 *dropped; 2882 2883 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2884 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2885 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2886 &mib->counters[mib->cnt_ptr]); 2887 ++mib->cnt_ptr; 2888 } 2889 2890 /* last one in storage */ 2891 dropped = &mib->counters[dev->info->mib_cnt]; 2892 2893 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2894 while (mib->cnt_ptr < dev->info->mib_cnt) { 2895 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2896 dropped, &mib->counters[mib->cnt_ptr]); 2897 ++mib->cnt_ptr; 2898 } 2899 mib->cnt_ptr = 0; 2900 } 2901 2902 static void ksz_mib_read_work(struct work_struct *work) 2903 { 2904 struct ksz_device *dev = container_of(work, struct ksz_device, 2905 mib_read.work); 2906 struct ksz_port_mib *mib; 2907 struct ksz_port *p; 2908 int i; 2909 2910 for (i = 0; i < dev->info->port_cnt; i++) { 2911 if (dsa_is_unused_port(dev->ds, i)) 2912 continue; 2913 2914 p = &dev->ports[i]; 2915 mib = &p->mib; 2916 mutex_lock(&mib->cnt_mutex); 2917 2918 /* Only read MIB counters when the port is told to do. 2919 * If not, read only dropped counters when link is not up. 2920 */ 2921 if (!p->read) { 2922 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 2923 2924 if (!netif_carrier_ok(dp->user)) 2925 mib->cnt_ptr = dev->info->reg_mib_cnt; 2926 } 2927 port_r_cnt(dev, i); 2928 p->read = false; 2929 2930 if (dev->dev_ops->r_mib_stat64) 2931 dev->dev_ops->r_mib_stat64(dev, i); 2932 2933 mutex_unlock(&mib->cnt_mutex); 2934 } 2935 2936 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 2937 } 2938 2939 void ksz_init_mib_timer(struct ksz_device *dev) 2940 { 2941 int i; 2942 2943 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 2944 2945 for (i = 0; i < dev->info->port_cnt; i++) { 2946 struct ksz_port_mib *mib = &dev->ports[i].mib; 2947 2948 dev->dev_ops->port_init_cnt(dev, i); 2949 2950 mib->cnt_ptr = 0; 2951 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 2952 } 2953 } 2954 2955 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 2956 { 2957 struct ksz_device *dev = ds->priv; 2958 u16 val = 0xffff; 2959 int ret; 2960 2961 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 2962 if (ret) 2963 return ret; 2964 2965 return val; 2966 } 2967 2968 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 2969 { 2970 struct ksz_device *dev = ds->priv; 2971 int ret; 2972 2973 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 2974 if (ret) 2975 return ret; 2976 2977 return 0; 2978 } 2979 2980 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 2981 { 2982 struct ksz_device *dev = ds->priv; 2983 2984 switch (dev->chip_id) { 2985 case KSZ88X3_CHIP_ID: 2986 /* Silicon Errata Sheet (DS80000830A): 2987 * Port 1 does not work with LinkMD Cable-Testing. 2988 * Port 1 does not respond to received PAUSE control frames. 2989 */ 2990 if (!port) 2991 return MICREL_KSZ8_P1_ERRATA; 2992 break; 2993 case KSZ8567_CHIP_ID: 2994 /* KSZ8567R Errata DS80000752C Module 4 */ 2995 case KSZ8765_CHIP_ID: 2996 case KSZ8794_CHIP_ID: 2997 case KSZ8795_CHIP_ID: 2998 /* KSZ879x/KSZ877x/KSZ876x Errata DS80000687C Module 2 */ 2999 case KSZ9477_CHIP_ID: 3000 /* KSZ9477S Errata DS80000754A Module 4 */ 3001 case KSZ9567_CHIP_ID: 3002 /* KSZ9567S Errata DS80000756A Module 4 */ 3003 case KSZ9896_CHIP_ID: 3004 /* KSZ9896C Errata DS80000757A Module 3 */ 3005 case KSZ9897_CHIP_ID: 3006 case LAN9646_CHIP_ID: 3007 /* KSZ9897R Errata DS80000758C Module 4 */ 3008 /* Energy Efficient Ethernet (EEE) feature select must be manually disabled 3009 * The EEE feature is enabled by default, but it is not fully 3010 * operational. It must be manually disabled through register 3011 * controls. If not disabled, the PHY ports can auto-negotiate 3012 * to enable EEE, and this feature can cause link drops when 3013 * linked to another device supporting EEE. 3014 * 3015 * The same item appears in the errata for all switches above. 3016 */ 3017 return MICREL_NO_EEE; 3018 } 3019 3020 return 0; 3021 } 3022 3023 static void ksz_phylink_mac_link_down(struct phylink_config *config, 3024 unsigned int mode, 3025 phy_interface_t interface) 3026 { 3027 struct dsa_port *dp = dsa_phylink_to_port(config); 3028 struct ksz_device *dev = dp->ds->priv; 3029 3030 /* Read all MIB counters when the link is going down. */ 3031 dev->ports[dp->index].read = true; 3032 /* timer started */ 3033 if (dev->mib_read_interval) 3034 schedule_delayed_work(&dev->mib_read, 0); 3035 } 3036 3037 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 3038 { 3039 struct ksz_device *dev = ds->priv; 3040 3041 if (sset != ETH_SS_STATS) 3042 return 0; 3043 3044 return dev->info->mib_cnt; 3045 } 3046 3047 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 3048 uint64_t *buf) 3049 { 3050 const struct dsa_port *dp = dsa_to_port(ds, port); 3051 struct ksz_device *dev = ds->priv; 3052 struct ksz_port_mib *mib; 3053 3054 mib = &dev->ports[port].mib; 3055 mutex_lock(&mib->cnt_mutex); 3056 3057 /* Only read dropped counters if no link. */ 3058 if (!netif_carrier_ok(dp->user)) 3059 mib->cnt_ptr = dev->info->reg_mib_cnt; 3060 port_r_cnt(dev, port); 3061 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 3062 mutex_unlock(&mib->cnt_mutex); 3063 } 3064 3065 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 3066 struct dsa_bridge bridge, 3067 bool *tx_fwd_offload, 3068 struct netlink_ext_ack *extack) 3069 { 3070 /* port_stp_state_set() will be called after to put the port in 3071 * appropriate state so there is no need to do anything. 3072 */ 3073 3074 return 0; 3075 } 3076 3077 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 3078 struct dsa_bridge bridge) 3079 { 3080 /* port_stp_state_set() will be called after to put the port in 3081 * forwarding state so there is no need to do anything. 3082 */ 3083 } 3084 3085 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 3086 { 3087 struct ksz_device *dev = ds->priv; 3088 3089 dev->dev_ops->flush_dyn_mac_table(dev, port); 3090 } 3091 3092 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 3093 { 3094 struct ksz_device *dev = ds->priv; 3095 3096 if (!dev->dev_ops->set_ageing_time) 3097 return -EOPNOTSUPP; 3098 3099 return dev->dev_ops->set_ageing_time(dev, msecs); 3100 } 3101 3102 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 3103 const unsigned char *addr, u16 vid, 3104 struct dsa_db db) 3105 { 3106 struct ksz_device *dev = ds->priv; 3107 3108 if (!dev->dev_ops->fdb_add) 3109 return -EOPNOTSUPP; 3110 3111 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 3112 } 3113 3114 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 3115 const unsigned char *addr, 3116 u16 vid, struct dsa_db db) 3117 { 3118 struct ksz_device *dev = ds->priv; 3119 3120 if (!dev->dev_ops->fdb_del) 3121 return -EOPNOTSUPP; 3122 3123 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 3124 } 3125 3126 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 3127 dsa_fdb_dump_cb_t *cb, void *data) 3128 { 3129 struct ksz_device *dev = ds->priv; 3130 3131 if (!dev->dev_ops->fdb_dump) 3132 return -EOPNOTSUPP; 3133 3134 return dev->dev_ops->fdb_dump(dev, port, cb, data); 3135 } 3136 3137 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 3138 const struct switchdev_obj_port_mdb *mdb, 3139 struct dsa_db db) 3140 { 3141 struct ksz_device *dev = ds->priv; 3142 3143 if (!dev->dev_ops->mdb_add) 3144 return -EOPNOTSUPP; 3145 3146 return dev->dev_ops->mdb_add(dev, port, mdb, db); 3147 } 3148 3149 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 3150 const struct switchdev_obj_port_mdb *mdb, 3151 struct dsa_db db) 3152 { 3153 struct ksz_device *dev = ds->priv; 3154 3155 if (!dev->dev_ops->mdb_del) 3156 return -EOPNOTSUPP; 3157 3158 return dev->dev_ops->mdb_del(dev, port, mdb, db); 3159 } 3160 3161 static int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev, 3162 int port) 3163 { 3164 u32 queue_map = 0; 3165 int ipm; 3166 3167 for (ipm = 0; ipm < dev->info->num_ipms; ipm++) { 3168 int queue; 3169 3170 /* Traffic Type (TT) is corresponding to the Internal Priority 3171 * Map (IPM) in the switch. Traffic Class (TC) is 3172 * corresponding to the queue in the switch. 3173 */ 3174 queue = ieee8021q_tt_to_tc(ipm, dev->info->num_tx_queues); 3175 if (queue < 0) 3176 return queue; 3177 3178 queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S); 3179 } 3180 3181 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3182 } 3183 3184 static int ksz_port_setup(struct dsa_switch *ds, int port) 3185 { 3186 struct ksz_device *dev = ds->priv; 3187 int ret; 3188 3189 if (!dsa_is_user_port(ds, port)) 3190 return 0; 3191 3192 /* setup user port */ 3193 dev->dev_ops->port_setup(dev, port, false); 3194 3195 if (!is_ksz8(dev)) { 3196 ret = ksz9477_set_default_prio_queue_mapping(dev, port); 3197 if (ret) 3198 return ret; 3199 } 3200 3201 /* port_stp_state_set() will be called after to enable the port so 3202 * there is no need to do anything. 3203 */ 3204 3205 return ksz_dcb_init_port(dev, port); 3206 } 3207 3208 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 3209 { 3210 struct ksz_device *dev = ds->priv; 3211 struct ksz_port *p; 3212 const u16 *regs; 3213 u8 data; 3214 3215 regs = dev->info->regs; 3216 3217 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 3218 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 3219 3220 p = &dev->ports[port]; 3221 3222 switch (state) { 3223 case BR_STATE_DISABLED: 3224 data |= PORT_LEARN_DISABLE; 3225 break; 3226 case BR_STATE_LISTENING: 3227 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 3228 break; 3229 case BR_STATE_LEARNING: 3230 data |= PORT_RX_ENABLE; 3231 if (!p->learning) 3232 data |= PORT_LEARN_DISABLE; 3233 break; 3234 case BR_STATE_FORWARDING: 3235 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 3236 if (!p->learning) 3237 data |= PORT_LEARN_DISABLE; 3238 break; 3239 case BR_STATE_BLOCKING: 3240 data |= PORT_LEARN_DISABLE; 3241 break; 3242 default: 3243 dev_err(ds->dev, "invalid STP state: %d\n", state); 3244 return; 3245 } 3246 3247 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 3248 3249 p->stp_state = state; 3250 3251 ksz_update_port_member(dev, port); 3252 } 3253 3254 static void ksz_port_teardown(struct dsa_switch *ds, int port) 3255 { 3256 struct ksz_device *dev = ds->priv; 3257 3258 switch (dev->chip_id) { 3259 case KSZ8563_CHIP_ID: 3260 case KSZ8567_CHIP_ID: 3261 case KSZ9477_CHIP_ID: 3262 case KSZ9563_CHIP_ID: 3263 case KSZ9567_CHIP_ID: 3264 case KSZ9893_CHIP_ID: 3265 case KSZ9896_CHIP_ID: 3266 case KSZ9897_CHIP_ID: 3267 case LAN9646_CHIP_ID: 3268 if (dsa_is_user_port(ds, port)) 3269 ksz9477_port_acl_free(dev, port); 3270 } 3271 } 3272 3273 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 3274 struct switchdev_brport_flags flags, 3275 struct netlink_ext_ack *extack) 3276 { 3277 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED)) 3278 return -EINVAL; 3279 3280 return 0; 3281 } 3282 3283 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 3284 struct switchdev_brport_flags flags, 3285 struct netlink_ext_ack *extack) 3286 { 3287 struct ksz_device *dev = ds->priv; 3288 struct ksz_port *p = &dev->ports[port]; 3289 3290 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) { 3291 if (flags.mask & BR_LEARNING) 3292 p->learning = !!(flags.val & BR_LEARNING); 3293 3294 if (flags.mask & BR_ISOLATED) 3295 p->isolated = !!(flags.val & BR_ISOLATED); 3296 3297 /* Make the change take effect immediately */ 3298 ksz_port_stp_state_set(ds, port, p->stp_state); 3299 } 3300 3301 return 0; 3302 } 3303 3304 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 3305 int port, 3306 enum dsa_tag_protocol mp) 3307 { 3308 struct ksz_device *dev = ds->priv; 3309 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 3310 3311 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev)) 3312 proto = DSA_TAG_PROTO_KSZ8795; 3313 3314 if (dev->chip_id == KSZ88X3_CHIP_ID || 3315 dev->chip_id == KSZ8563_CHIP_ID || 3316 dev->chip_id == KSZ9893_CHIP_ID || 3317 dev->chip_id == KSZ9563_CHIP_ID) 3318 proto = DSA_TAG_PROTO_KSZ9893; 3319 3320 if (dev->chip_id == KSZ8567_CHIP_ID || 3321 dev->chip_id == KSZ9477_CHIP_ID || 3322 dev->chip_id == KSZ9896_CHIP_ID || 3323 dev->chip_id == KSZ9897_CHIP_ID || 3324 dev->chip_id == KSZ9567_CHIP_ID || 3325 dev->chip_id == LAN9646_CHIP_ID) 3326 proto = DSA_TAG_PROTO_KSZ9477; 3327 3328 if (is_lan937x(dev)) 3329 proto = DSA_TAG_PROTO_LAN937X; 3330 3331 return proto; 3332 } 3333 3334 static int ksz_connect_tag_protocol(struct dsa_switch *ds, 3335 enum dsa_tag_protocol proto) 3336 { 3337 struct ksz_tagger_data *tagger_data; 3338 3339 switch (proto) { 3340 case DSA_TAG_PROTO_KSZ8795: 3341 return 0; 3342 case DSA_TAG_PROTO_KSZ9893: 3343 case DSA_TAG_PROTO_KSZ9477: 3344 case DSA_TAG_PROTO_LAN937X: 3345 tagger_data = ksz_tagger_data(ds); 3346 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 3347 return 0; 3348 default: 3349 return -EPROTONOSUPPORT; 3350 } 3351 } 3352 3353 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 3354 bool flag, struct netlink_ext_ack *extack) 3355 { 3356 struct ksz_device *dev = ds->priv; 3357 3358 if (!dev->dev_ops->vlan_filtering) 3359 return -EOPNOTSUPP; 3360 3361 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 3362 } 3363 3364 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 3365 const struct switchdev_obj_port_vlan *vlan, 3366 struct netlink_ext_ack *extack) 3367 { 3368 struct ksz_device *dev = ds->priv; 3369 3370 if (!dev->dev_ops->vlan_add) 3371 return -EOPNOTSUPP; 3372 3373 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 3374 } 3375 3376 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 3377 const struct switchdev_obj_port_vlan *vlan) 3378 { 3379 struct ksz_device *dev = ds->priv; 3380 3381 if (!dev->dev_ops->vlan_del) 3382 return -EOPNOTSUPP; 3383 3384 return dev->dev_ops->vlan_del(dev, port, vlan); 3385 } 3386 3387 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 3388 struct dsa_mall_mirror_tc_entry *mirror, 3389 bool ingress, struct netlink_ext_ack *extack) 3390 { 3391 struct ksz_device *dev = ds->priv; 3392 3393 if (!dev->dev_ops->mirror_add) 3394 return -EOPNOTSUPP; 3395 3396 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 3397 } 3398 3399 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 3400 struct dsa_mall_mirror_tc_entry *mirror) 3401 { 3402 struct ksz_device *dev = ds->priv; 3403 3404 if (dev->dev_ops->mirror_del) 3405 dev->dev_ops->mirror_del(dev, port, mirror); 3406 } 3407 3408 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 3409 { 3410 struct ksz_device *dev = ds->priv; 3411 3412 if (!dev->dev_ops->change_mtu) 3413 return -EOPNOTSUPP; 3414 3415 return dev->dev_ops->change_mtu(dev, port, mtu); 3416 } 3417 3418 static int ksz_max_mtu(struct dsa_switch *ds, int port) 3419 { 3420 struct ksz_device *dev = ds->priv; 3421 3422 switch (dev->chip_id) { 3423 case KSZ8795_CHIP_ID: 3424 case KSZ8794_CHIP_ID: 3425 case KSZ8765_CHIP_ID: 3426 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3427 case KSZ88X3_CHIP_ID: 3428 case KSZ8864_CHIP_ID: 3429 case KSZ8895_CHIP_ID: 3430 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3431 case KSZ8563_CHIP_ID: 3432 case KSZ8567_CHIP_ID: 3433 case KSZ9477_CHIP_ID: 3434 case KSZ9563_CHIP_ID: 3435 case KSZ9567_CHIP_ID: 3436 case KSZ9893_CHIP_ID: 3437 case KSZ9896_CHIP_ID: 3438 case KSZ9897_CHIP_ID: 3439 case LAN9370_CHIP_ID: 3440 case LAN9371_CHIP_ID: 3441 case LAN9372_CHIP_ID: 3442 case LAN9373_CHIP_ID: 3443 case LAN9374_CHIP_ID: 3444 case LAN9646_CHIP_ID: 3445 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3446 } 3447 3448 return -EOPNOTSUPP; 3449 } 3450 3451 static bool ksz_support_eee(struct dsa_switch *ds, int port) 3452 { 3453 struct ksz_device *dev = ds->priv; 3454 3455 if (!dev->info->internal_phy[port]) 3456 return false; 3457 3458 switch (dev->chip_id) { 3459 case KSZ8563_CHIP_ID: 3460 case KSZ8567_CHIP_ID: 3461 case KSZ9477_CHIP_ID: 3462 case KSZ9563_CHIP_ID: 3463 case KSZ9567_CHIP_ID: 3464 case KSZ9893_CHIP_ID: 3465 case KSZ9896_CHIP_ID: 3466 case KSZ9897_CHIP_ID: 3467 case LAN9646_CHIP_ID: 3468 return true; 3469 } 3470 3471 return false; 3472 } 3473 3474 static int ksz_get_mac_eee(struct dsa_switch *ds, int port, 3475 struct ethtool_keee *e) 3476 { 3477 /* There is no documented control of Tx LPI configuration. */ 3478 e->tx_lpi_enabled = true; 3479 3480 /* There is no documented control of Tx LPI timer. According to tests 3481 * Tx LPI timer seems to be set by default to minimal value. 3482 */ 3483 e->tx_lpi_timer = 0; 3484 3485 return 0; 3486 } 3487 3488 static int ksz_set_mac_eee(struct dsa_switch *ds, int port, 3489 struct ethtool_keee *e) 3490 { 3491 struct ksz_device *dev = ds->priv; 3492 3493 if (!e->tx_lpi_enabled) { 3494 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 3495 return -EINVAL; 3496 } 3497 3498 if (e->tx_lpi_timer) { 3499 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 3500 return -EINVAL; 3501 } 3502 3503 return 0; 3504 } 3505 3506 static void ksz_set_xmii(struct ksz_device *dev, int port, 3507 phy_interface_t interface) 3508 { 3509 const u8 *bitval = dev->info->xmii_ctrl1; 3510 struct ksz_port *p = &dev->ports[port]; 3511 const u16 *regs = dev->info->regs; 3512 u8 data8; 3513 3514 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3515 3516 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 3517 P_RGMII_ID_EG_ENABLE); 3518 3519 switch (interface) { 3520 case PHY_INTERFACE_MODE_MII: 3521 data8 |= bitval[P_MII_SEL]; 3522 break; 3523 case PHY_INTERFACE_MODE_RMII: 3524 data8 |= bitval[P_RMII_SEL]; 3525 break; 3526 case PHY_INTERFACE_MODE_GMII: 3527 data8 |= bitval[P_GMII_SEL]; 3528 break; 3529 case PHY_INTERFACE_MODE_RGMII: 3530 case PHY_INTERFACE_MODE_RGMII_ID: 3531 case PHY_INTERFACE_MODE_RGMII_TXID: 3532 case PHY_INTERFACE_MODE_RGMII_RXID: 3533 data8 |= bitval[P_RGMII_SEL]; 3534 /* On KSZ9893, disable RGMII in-band status support */ 3535 if (dev->chip_id == KSZ9893_CHIP_ID || 3536 dev->chip_id == KSZ8563_CHIP_ID || 3537 dev->chip_id == KSZ9563_CHIP_ID || 3538 is_lan937x(dev)) 3539 data8 &= ~P_MII_MAC_MODE; 3540 break; 3541 default: 3542 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 3543 phy_modes(interface), port); 3544 return; 3545 } 3546 3547 if (p->rgmii_tx_val) 3548 data8 |= P_RGMII_ID_EG_ENABLE; 3549 3550 if (p->rgmii_rx_val) 3551 data8 |= P_RGMII_ID_IG_ENABLE; 3552 3553 /* Write the updated value */ 3554 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3555 } 3556 3557 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 3558 { 3559 const u8 *bitval = dev->info->xmii_ctrl1; 3560 const u16 *regs = dev->info->regs; 3561 phy_interface_t interface; 3562 u8 data8; 3563 u8 val; 3564 3565 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3566 3567 val = FIELD_GET(P_MII_SEL_M, data8); 3568 3569 if (val == bitval[P_MII_SEL]) { 3570 if (gbit) 3571 interface = PHY_INTERFACE_MODE_GMII; 3572 else 3573 interface = PHY_INTERFACE_MODE_MII; 3574 } else if (val == bitval[P_RMII_SEL]) { 3575 interface = PHY_INTERFACE_MODE_RMII; 3576 } else { 3577 interface = PHY_INTERFACE_MODE_RGMII; 3578 if (data8 & P_RGMII_ID_EG_ENABLE) 3579 interface = PHY_INTERFACE_MODE_RGMII_TXID; 3580 if (data8 & P_RGMII_ID_IG_ENABLE) { 3581 interface = PHY_INTERFACE_MODE_RGMII_RXID; 3582 if (data8 & P_RGMII_ID_EG_ENABLE) 3583 interface = PHY_INTERFACE_MODE_RGMII_ID; 3584 } 3585 } 3586 3587 return interface; 3588 } 3589 3590 static void ksz88x3_phylink_mac_config(struct phylink_config *config, 3591 unsigned int mode, 3592 const struct phylink_link_state *state) 3593 { 3594 struct dsa_port *dp = dsa_phylink_to_port(config); 3595 struct ksz_device *dev = dp->ds->priv; 3596 3597 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN); 3598 } 3599 3600 static void ksz_phylink_mac_config(struct phylink_config *config, 3601 unsigned int mode, 3602 const struct phylink_link_state *state) 3603 { 3604 struct dsa_port *dp = dsa_phylink_to_port(config); 3605 struct ksz_device *dev = dp->ds->priv; 3606 int port = dp->index; 3607 3608 /* Internal PHYs */ 3609 if (dev->info->internal_phy[port]) 3610 return; 3611 3612 if (phylink_autoneg_inband(mode)) { 3613 dev_err(dev->dev, "In-band AN not supported!\n"); 3614 return; 3615 } 3616 3617 ksz_set_xmii(dev, port, state->interface); 3618 3619 if (dev->dev_ops->setup_rgmii_delay) 3620 dev->dev_ops->setup_rgmii_delay(dev, port); 3621 } 3622 3623 bool ksz_get_gbit(struct ksz_device *dev, int port) 3624 { 3625 const u8 *bitval = dev->info->xmii_ctrl1; 3626 const u16 *regs = dev->info->regs; 3627 bool gbit = false; 3628 u8 data8; 3629 bool val; 3630 3631 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3632 3633 val = FIELD_GET(P_GMII_1GBIT_M, data8); 3634 3635 if (val == bitval[P_GMII_1GBIT]) 3636 gbit = true; 3637 3638 return gbit; 3639 } 3640 3641 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 3642 { 3643 const u8 *bitval = dev->info->xmii_ctrl1; 3644 const u16 *regs = dev->info->regs; 3645 u8 data8; 3646 3647 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3648 3649 data8 &= ~P_GMII_1GBIT_M; 3650 3651 if (gbit) 3652 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 3653 else 3654 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 3655 3656 /* Write the updated value */ 3657 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3658 } 3659 3660 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 3661 { 3662 const u8 *bitval = dev->info->xmii_ctrl0; 3663 const u16 *regs = dev->info->regs; 3664 u8 data8; 3665 3666 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 3667 3668 data8 &= ~P_MII_100MBIT_M; 3669 3670 if (speed == SPEED_100) 3671 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 3672 else 3673 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 3674 3675 /* Write the updated value */ 3676 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 3677 } 3678 3679 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 3680 { 3681 if (speed == SPEED_1000) 3682 ksz_set_gbit(dev, port, true); 3683 else 3684 ksz_set_gbit(dev, port, false); 3685 3686 if (speed == SPEED_100 || speed == SPEED_10) 3687 ksz_set_100_10mbit(dev, port, speed); 3688 } 3689 3690 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 3691 bool tx_pause, bool rx_pause) 3692 { 3693 const u8 *bitval = dev->info->xmii_ctrl0; 3694 const u32 *masks = dev->info->masks; 3695 const u16 *regs = dev->info->regs; 3696 u8 mask; 3697 u8 val; 3698 3699 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 3700 masks[P_MII_RX_FLOW_CTRL]; 3701 3702 if (duplex == DUPLEX_FULL) 3703 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 3704 else 3705 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 3706 3707 if (tx_pause) 3708 val |= masks[P_MII_TX_FLOW_CTRL]; 3709 3710 if (rx_pause) 3711 val |= masks[P_MII_RX_FLOW_CTRL]; 3712 3713 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 3714 } 3715 3716 static void ksz9477_phylink_mac_link_up(struct phylink_config *config, 3717 struct phy_device *phydev, 3718 unsigned int mode, 3719 phy_interface_t interface, 3720 int speed, int duplex, bool tx_pause, 3721 bool rx_pause) 3722 { 3723 struct dsa_port *dp = dsa_phylink_to_port(config); 3724 struct ksz_device *dev = dp->ds->priv; 3725 int port = dp->index; 3726 struct ksz_port *p; 3727 3728 p = &dev->ports[port]; 3729 3730 /* Internal PHYs */ 3731 if (dev->info->internal_phy[port]) 3732 return; 3733 3734 p->phydev.speed = speed; 3735 3736 ksz_port_set_xmii_speed(dev, port, speed); 3737 3738 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 3739 } 3740 3741 static int ksz_switch_detect(struct ksz_device *dev) 3742 { 3743 u8 id1, id2, id4; 3744 u16 id16; 3745 u32 id32; 3746 int ret; 3747 3748 /* read chip id */ 3749 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 3750 if (ret) 3751 return ret; 3752 3753 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 3754 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 3755 3756 switch (id1) { 3757 case KSZ87_FAMILY_ID: 3758 if (id2 == KSZ87_CHIP_ID_95) { 3759 u8 val; 3760 3761 dev->chip_id = KSZ8795_CHIP_ID; 3762 3763 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 3764 if (val & KSZ8_PORT_FIBER_MODE) 3765 dev->chip_id = KSZ8765_CHIP_ID; 3766 } else if (id2 == KSZ87_CHIP_ID_94) { 3767 dev->chip_id = KSZ8794_CHIP_ID; 3768 } else { 3769 return -ENODEV; 3770 } 3771 break; 3772 case KSZ88_FAMILY_ID: 3773 if (id2 == KSZ88_CHIP_ID_63) 3774 dev->chip_id = KSZ88X3_CHIP_ID; 3775 else 3776 return -ENODEV; 3777 break; 3778 case KSZ8895_FAMILY_ID: 3779 if (id2 == KSZ8895_CHIP_ID_95 || 3780 id2 == KSZ8895_CHIP_ID_95R) 3781 dev->chip_id = KSZ8895_CHIP_ID; 3782 else 3783 return -ENODEV; 3784 ret = ksz_read8(dev, REG_KSZ8864_CHIP_ID, &id4); 3785 if (ret) 3786 return ret; 3787 if (id4 & SW_KSZ8864) 3788 dev->chip_id = KSZ8864_CHIP_ID; 3789 break; 3790 default: 3791 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 3792 if (ret) 3793 return ret; 3794 3795 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 3796 id32 &= ~0xFF; 3797 3798 switch (id32) { 3799 case KSZ9477_CHIP_ID: 3800 case KSZ9896_CHIP_ID: 3801 case KSZ9897_CHIP_ID: 3802 case KSZ9567_CHIP_ID: 3803 case KSZ8567_CHIP_ID: 3804 case LAN9370_CHIP_ID: 3805 case LAN9371_CHIP_ID: 3806 case LAN9372_CHIP_ID: 3807 case LAN9373_CHIP_ID: 3808 case LAN9374_CHIP_ID: 3809 3810 /* LAN9646 does not have its own chip id. */ 3811 if (dev->chip_id != LAN9646_CHIP_ID) 3812 dev->chip_id = id32; 3813 break; 3814 case KSZ9893_CHIP_ID: 3815 ret = ksz_read8(dev, REG_CHIP_ID4, 3816 &id4); 3817 if (ret) 3818 return ret; 3819 3820 if (id4 == SKU_ID_KSZ8563) 3821 dev->chip_id = KSZ8563_CHIP_ID; 3822 else if (id4 == SKU_ID_KSZ9563) 3823 dev->chip_id = KSZ9563_CHIP_ID; 3824 else 3825 dev->chip_id = KSZ9893_CHIP_ID; 3826 3827 break; 3828 default: 3829 dev_err(dev->dev, 3830 "unsupported switch detected %x)\n", id32); 3831 return -ENODEV; 3832 } 3833 } 3834 return 0; 3835 } 3836 3837 static int ksz_cls_flower_add(struct dsa_switch *ds, int port, 3838 struct flow_cls_offload *cls, bool ingress) 3839 { 3840 struct ksz_device *dev = ds->priv; 3841 3842 switch (dev->chip_id) { 3843 case KSZ8563_CHIP_ID: 3844 case KSZ8567_CHIP_ID: 3845 case KSZ9477_CHIP_ID: 3846 case KSZ9563_CHIP_ID: 3847 case KSZ9567_CHIP_ID: 3848 case KSZ9893_CHIP_ID: 3849 case KSZ9896_CHIP_ID: 3850 case KSZ9897_CHIP_ID: 3851 case LAN9646_CHIP_ID: 3852 return ksz9477_cls_flower_add(ds, port, cls, ingress); 3853 } 3854 3855 return -EOPNOTSUPP; 3856 } 3857 3858 static int ksz_cls_flower_del(struct dsa_switch *ds, int port, 3859 struct flow_cls_offload *cls, bool ingress) 3860 { 3861 struct ksz_device *dev = ds->priv; 3862 3863 switch (dev->chip_id) { 3864 case KSZ8563_CHIP_ID: 3865 case KSZ8567_CHIP_ID: 3866 case KSZ9477_CHIP_ID: 3867 case KSZ9563_CHIP_ID: 3868 case KSZ9567_CHIP_ID: 3869 case KSZ9893_CHIP_ID: 3870 case KSZ9896_CHIP_ID: 3871 case KSZ9897_CHIP_ID: 3872 case LAN9646_CHIP_ID: 3873 return ksz9477_cls_flower_del(ds, port, cls, ingress); 3874 } 3875 3876 return -EOPNOTSUPP; 3877 } 3878 3879 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 3880 * is converted to Hex-decimal using the successive multiplication method. On 3881 * every step, integer part is taken and decimal part is carry forwarded. 3882 */ 3883 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 3884 { 3885 u32 cinc = 0; 3886 u32 txrate; 3887 u32 rate; 3888 u8 temp; 3889 u8 i; 3890 3891 txrate = idle_slope - send_slope; 3892 3893 if (!txrate) 3894 return -EINVAL; 3895 3896 rate = idle_slope; 3897 3898 /* 24 bit register */ 3899 for (i = 0; i < 6; i++) { 3900 rate = rate * 16; 3901 3902 temp = rate / txrate; 3903 3904 rate %= txrate; 3905 3906 cinc = ((cinc << 4) | temp); 3907 } 3908 3909 *bw = cinc; 3910 3911 return 0; 3912 } 3913 3914 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 3915 u8 shaper) 3916 { 3917 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 3918 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 3919 FIELD_PREP(MTI_SHAPING_M, shaper)); 3920 } 3921 3922 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 3923 struct tc_cbs_qopt_offload *qopt) 3924 { 3925 struct ksz_device *dev = ds->priv; 3926 int ret; 3927 u32 bw; 3928 3929 if (!dev->info->tc_cbs_supported) 3930 return -EOPNOTSUPP; 3931 3932 if (qopt->queue > dev->info->num_tx_queues) 3933 return -EINVAL; 3934 3935 /* Queue Selection */ 3936 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 3937 if (ret) 3938 return ret; 3939 3940 if (!qopt->enable) 3941 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3942 MTI_SHAPING_OFF); 3943 3944 /* High Credit */ 3945 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 3946 qopt->hicredit); 3947 if (ret) 3948 return ret; 3949 3950 /* Low Credit */ 3951 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 3952 qopt->locredit); 3953 if (ret) 3954 return ret; 3955 3956 /* Credit Increment Register */ 3957 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 3958 if (ret) 3959 return ret; 3960 3961 if (dev->dev_ops->tc_cbs_set_cinc) { 3962 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 3963 if (ret) 3964 return ret; 3965 } 3966 3967 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3968 MTI_SHAPING_SRP); 3969 } 3970 3971 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 3972 { 3973 int queue, ret; 3974 3975 /* Configuration will not take effect until the last Port Queue X 3976 * Egress Limit Control Register is written. 3977 */ 3978 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3979 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 3980 KSZ9477_OUT_RATE_NO_LIMIT); 3981 if (ret) 3982 return ret; 3983 } 3984 3985 return 0; 3986 } 3987 3988 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 3989 int band) 3990 { 3991 /* Compared to queues, bands prioritize packets differently. In strict 3992 * priority mode, the lowest priority is assigned to Queue 0 while the 3993 * highest priority is given to Band 0. 3994 */ 3995 return p->bands - 1 - band; 3996 } 3997 3998 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 3999 { 4000 int ret; 4001 4002 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 4003 if (ret) 4004 return ret; 4005 4006 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 4007 MTI_SHAPING_OFF); 4008 } 4009 4010 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 4011 int weight) 4012 { 4013 int ret; 4014 4015 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 4016 if (ret) 4017 return ret; 4018 4019 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 4020 MTI_SHAPING_OFF); 4021 if (ret) 4022 return ret; 4023 4024 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 4025 } 4026 4027 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 4028 struct tc_ets_qopt_offload_replace_params *p) 4029 { 4030 int ret, band, tc_prio; 4031 u32 queue_map = 0; 4032 4033 /* In order to ensure proper prioritization, it is necessary to set the 4034 * rate limit for the related queue to zero. Otherwise strict priority 4035 * or WRR mode will not work. This is a hardware limitation. 4036 */ 4037 ret = ksz_disable_egress_rate_limit(dev, port); 4038 if (ret) 4039 return ret; 4040 4041 /* Configure queue scheduling mode for all bands. Currently only strict 4042 * prio mode is supported. 4043 */ 4044 for (band = 0; band < p->bands; band++) { 4045 int queue = ksz_ets_band_to_queue(p, band); 4046 4047 ret = ksz_queue_set_strict(dev, port, queue); 4048 if (ret) 4049 return ret; 4050 } 4051 4052 /* Configure the mapping between traffic classes and queues. Note: 4053 * priomap variable support 16 traffic classes, but the chip can handle 4054 * only 8 classes. 4055 */ 4056 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 4057 int queue; 4058 4059 if (tc_prio >= dev->info->num_ipms) 4060 break; 4061 4062 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 4063 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 4064 } 4065 4066 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 4067 } 4068 4069 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 4070 { 4071 int ret, queue; 4072 4073 /* To restore the default chip configuration, set all queues to use the 4074 * WRR scheduler with a weight of 1. 4075 */ 4076 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 4077 ret = ksz_queue_set_wrr(dev, port, queue, 4078 KSZ9477_DEFAULT_WRR_WEIGHT); 4079 if (ret) 4080 return ret; 4081 } 4082 4083 /* Revert the queue mapping for TC-priority to its default setting on 4084 * the chip. 4085 */ 4086 return ksz9477_set_default_prio_queue_mapping(dev, port); 4087 } 4088 4089 static int ksz_tc_ets_validate(struct ksz_device *dev, int port, 4090 struct tc_ets_qopt_offload_replace_params *p) 4091 { 4092 int band; 4093 4094 /* Since it is not feasible to share one port among multiple qdisc, 4095 * the user must configure all available queues appropriately. 4096 */ 4097 if (p->bands != dev->info->num_tx_queues) { 4098 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 4099 dev->info->num_tx_queues); 4100 return -EOPNOTSUPP; 4101 } 4102 4103 for (band = 0; band < p->bands; ++band) { 4104 /* The KSZ switches utilize a weighted round robin configuration 4105 * where a certain number of packets can be transmitted from a 4106 * queue before the next queue is serviced. For more information 4107 * on this, refer to section 5.2.8.4 of the KSZ8565R 4108 * documentation on the Port Transmit Queue Control 1 Register. 4109 * However, the current ETS Qdisc implementation (as of February 4110 * 2023) assigns a weight to each queue based on the number of 4111 * bytes or extrapolated bandwidth in percentages. Since this 4112 * differs from the KSZ switches' method and we don't want to 4113 * fake support by converting bytes to packets, it is better to 4114 * return an error instead. 4115 */ 4116 if (p->quanta[band]) { 4117 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 4118 return -EOPNOTSUPP; 4119 } 4120 } 4121 4122 return 0; 4123 } 4124 4125 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 4126 struct tc_ets_qopt_offload *qopt) 4127 { 4128 struct ksz_device *dev = ds->priv; 4129 int ret; 4130 4131 if (is_ksz8(dev)) 4132 return -EOPNOTSUPP; 4133 4134 if (qopt->parent != TC_H_ROOT) { 4135 dev_err(dev->dev, "Parent should be \"root\"\n"); 4136 return -EOPNOTSUPP; 4137 } 4138 4139 switch (qopt->command) { 4140 case TC_ETS_REPLACE: 4141 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 4142 if (ret) 4143 return ret; 4144 4145 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 4146 case TC_ETS_DESTROY: 4147 return ksz_tc_ets_del(dev, port); 4148 case TC_ETS_STATS: 4149 case TC_ETS_GRAFT: 4150 return -EOPNOTSUPP; 4151 } 4152 4153 return -EOPNOTSUPP; 4154 } 4155 4156 static int ksz_setup_tc(struct dsa_switch *ds, int port, 4157 enum tc_setup_type type, void *type_data) 4158 { 4159 switch (type) { 4160 case TC_SETUP_QDISC_CBS: 4161 return ksz_setup_tc_cbs(ds, port, type_data); 4162 case TC_SETUP_QDISC_ETS: 4163 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 4164 default: 4165 return -EOPNOTSUPP; 4166 } 4167 } 4168 4169 /** 4170 * ksz_handle_wake_reason - Handle wake reason on a specified port. 4171 * @dev: The device structure. 4172 * @port: The port number. 4173 * 4174 * This function reads the PME (Power Management Event) status register of a 4175 * specified port to determine the wake reason. If there is no wake event, it 4176 * returns early. Otherwise, it logs the wake reason which could be due to a 4177 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register 4178 * is then cleared to acknowledge the handling of the wake event. 4179 * 4180 * Return: 0 on success, or an error code on failure. 4181 */ 4182 int ksz_handle_wake_reason(struct ksz_device *dev, int port) 4183 { 4184 const struct ksz_dev_ops *ops = dev->dev_ops; 4185 const u16 *regs = dev->info->regs; 4186 u8 pme_status; 4187 int ret; 4188 4189 ret = ops->pme_pread8(dev, port, regs[REG_PORT_PME_STATUS], 4190 &pme_status); 4191 if (ret) 4192 return ret; 4193 4194 if (!pme_status) 4195 return 0; 4196 4197 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port, 4198 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "", 4199 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "", 4200 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : ""); 4201 4202 return ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_STATUS], 4203 pme_status); 4204 } 4205 4206 /** 4207 * ksz_get_wol - Get Wake-on-LAN settings for a specified port. 4208 * @ds: The dsa_switch structure. 4209 * @port: The port number. 4210 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 4211 * 4212 * This function checks the device PME wakeup_source flag and chip_id. 4213 * If enabled and supported, it sets the supported and active WoL 4214 * flags. 4215 */ 4216 static void ksz_get_wol(struct dsa_switch *ds, int port, 4217 struct ethtool_wolinfo *wol) 4218 { 4219 struct ksz_device *dev = ds->priv; 4220 const u16 *regs = dev->info->regs; 4221 u8 pme_ctrl; 4222 int ret; 4223 4224 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4225 return; 4226 4227 if (!dev->wakeup_source) 4228 return; 4229 4230 wol->supported = WAKE_PHY; 4231 4232 /* Check if the current MAC address on this port can be set 4233 * as global for WAKE_MAGIC support. The result may vary 4234 * dynamically based on other ports configurations. 4235 */ 4236 if (ksz_is_port_mac_global_usable(dev->ds, port)) 4237 wol->supported |= WAKE_MAGIC; 4238 4239 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 4240 &pme_ctrl); 4241 if (ret) 4242 return; 4243 4244 if (pme_ctrl & PME_WOL_MAGICPKT) 4245 wol->wolopts |= WAKE_MAGIC; 4246 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY)) 4247 wol->wolopts |= WAKE_PHY; 4248 } 4249 4250 /** 4251 * ksz_set_wol - Set Wake-on-LAN settings for a specified port. 4252 * @ds: The dsa_switch structure. 4253 * @port: The port number. 4254 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 4255 * 4256 * This function configures Wake-on-LAN (WoL) settings for a specified 4257 * port. It validates the provided WoL options, checks if PME is 4258 * enabled and supported, clears any previous wake reasons, and sets 4259 * the Magic Packet flag in the port's PME control register if 4260 * specified. 4261 * 4262 * Return: 0 on success, or other error codes on failure. 4263 */ 4264 static int ksz_set_wol(struct dsa_switch *ds, int port, 4265 struct ethtool_wolinfo *wol) 4266 { 4267 u8 pme_ctrl = 0, pme_ctrl_old = 0; 4268 struct ksz_device *dev = ds->priv; 4269 const u16 *regs = dev->info->regs; 4270 bool magic_switched_off; 4271 bool magic_switched_on; 4272 int ret; 4273 4274 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC)) 4275 return -EINVAL; 4276 4277 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4278 return -EOPNOTSUPP; 4279 4280 if (!dev->wakeup_source) 4281 return -EOPNOTSUPP; 4282 4283 ret = ksz_handle_wake_reason(dev, port); 4284 if (ret) 4285 return ret; 4286 4287 if (wol->wolopts & WAKE_MAGIC) 4288 pme_ctrl |= PME_WOL_MAGICPKT; 4289 if (wol->wolopts & WAKE_PHY) 4290 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY; 4291 4292 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 4293 &pme_ctrl_old); 4294 if (ret) 4295 return ret; 4296 4297 if (pme_ctrl_old == pme_ctrl) 4298 return 0; 4299 4300 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) && 4301 !(pme_ctrl & PME_WOL_MAGICPKT); 4302 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) && 4303 (pme_ctrl & PME_WOL_MAGICPKT); 4304 4305 /* To keep reference count of MAC address, we should do this 4306 * operation only on change of WOL settings. 4307 */ 4308 if (magic_switched_on) { 4309 ret = ksz_switch_macaddr_get(dev->ds, port, NULL); 4310 if (ret) 4311 return ret; 4312 } else if (magic_switched_off) { 4313 ksz_switch_macaddr_put(dev->ds); 4314 } 4315 4316 ret = dev->dev_ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 4317 pme_ctrl); 4318 if (ret) { 4319 if (magic_switched_on) 4320 ksz_switch_macaddr_put(dev->ds); 4321 return ret; 4322 } 4323 4324 return 0; 4325 } 4326 4327 /** 4328 * ksz_wol_pre_shutdown - Prepares the switch device for shutdown while 4329 * considering Wake-on-LAN (WoL) settings. 4330 * @dev: The switch device structure. 4331 * @wol_enabled: Pointer to a boolean which will be set to true if WoL is 4332 * enabled on any port. 4333 * 4334 * This function prepares the switch device for a safe shutdown while taking 4335 * into account the Wake-on-LAN (WoL) settings on the user ports. It updates 4336 * the wol_enabled flag accordingly to reflect whether WoL is active on any 4337 * port. 4338 */ 4339 static void ksz_wol_pre_shutdown(struct ksz_device *dev, bool *wol_enabled) 4340 { 4341 const struct ksz_dev_ops *ops = dev->dev_ops; 4342 const u16 *regs = dev->info->regs; 4343 u8 pme_pin_en = PME_ENABLE; 4344 struct dsa_port *dp; 4345 int ret; 4346 4347 *wol_enabled = false; 4348 4349 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4350 return; 4351 4352 if (!dev->wakeup_source) 4353 return; 4354 4355 dsa_switch_for_each_user_port(dp, dev->ds) { 4356 u8 pme_ctrl = 0; 4357 4358 ret = ops->pme_pread8(dev, dp->index, 4359 regs[REG_PORT_PME_CTRL], &pme_ctrl); 4360 if (!ret && pme_ctrl) 4361 *wol_enabled = true; 4362 4363 /* make sure there are no pending wake events which would 4364 * prevent the device from going to sleep/shutdown. 4365 */ 4366 ksz_handle_wake_reason(dev, dp->index); 4367 } 4368 4369 /* Now we are save to enable PME pin. */ 4370 if (*wol_enabled) { 4371 if (dev->pme_active_high) 4372 pme_pin_en |= PME_POLARITY; 4373 ops->pme_write8(dev, regs[REG_SW_PME_CTRL], pme_pin_en); 4374 if (ksz_is_ksz87xx(dev)) 4375 ksz_write8(dev, KSZ87XX_REG_INT_EN, KSZ87XX_INT_PME_MASK); 4376 } 4377 } 4378 4379 static int ksz_port_set_mac_address(struct dsa_switch *ds, int port, 4380 const unsigned char *addr) 4381 { 4382 struct dsa_port *dp = dsa_to_port(ds, port); 4383 struct ethtool_wolinfo wol; 4384 4385 if (dp->hsr_dev) { 4386 dev_err(ds->dev, 4387 "Cannot change MAC address on port %d with active HSR offload\n", 4388 port); 4389 return -EBUSY; 4390 } 4391 4392 /* Need to initialize variable as the code to fill in settings may 4393 * not be executed. 4394 */ 4395 wol.wolopts = 0; 4396 4397 ksz_get_wol(ds, dp->index, &wol); 4398 if (wol.wolopts & WAKE_MAGIC) { 4399 dev_err(ds->dev, 4400 "Cannot change MAC address on port %d with active Wake on Magic Packet\n", 4401 port); 4402 return -EBUSY; 4403 } 4404 4405 return 0; 4406 } 4407 4408 /** 4409 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port 4410 * can be used as a global address. 4411 * @ds: Pointer to the DSA switch structure. 4412 * @port: The port number on which the MAC address is to be checked. 4413 * 4414 * This function examines the MAC address set on the specified port and 4415 * determines if it can be used as a global address for the switch. 4416 * 4417 * Return: true if the port's MAC address can be used as a global address, false 4418 * otherwise. 4419 */ 4420 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port) 4421 { 4422 struct net_device *user = dsa_to_port(ds, port)->user; 4423 const unsigned char *addr = user->dev_addr; 4424 struct ksz_switch_macaddr *switch_macaddr; 4425 struct ksz_device *dev = ds->priv; 4426 4427 ASSERT_RTNL(); 4428 4429 switch_macaddr = dev->switch_macaddr; 4430 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr)) 4431 return false; 4432 4433 return true; 4434 } 4435 4436 /** 4437 * ksz_switch_macaddr_get - Program the switch's MAC address register. 4438 * @ds: DSA switch instance. 4439 * @port: Port number. 4440 * @extack: Netlink extended acknowledgment. 4441 * 4442 * This function programs the switch's MAC address register with the MAC address 4443 * of the requesting user port. This single address is used by the switch for 4444 * multiple features like HSR self-address filtering and WoL. Other user ports 4445 * can share ownership of this address as long as their MAC address is the same. 4446 * The MAC addresses of user ports must not change while they have ownership of 4447 * the switch MAC address. 4448 * 4449 * Return: 0 on success, or other error codes on failure. 4450 */ 4451 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 4452 struct netlink_ext_ack *extack) 4453 { 4454 struct net_device *user = dsa_to_port(ds, port)->user; 4455 const unsigned char *addr = user->dev_addr; 4456 struct ksz_switch_macaddr *switch_macaddr; 4457 struct ksz_device *dev = ds->priv; 4458 const u16 *regs = dev->info->regs; 4459 int i, ret; 4460 4461 /* Make sure concurrent MAC address changes are blocked */ 4462 ASSERT_RTNL(); 4463 4464 switch_macaddr = dev->switch_macaddr; 4465 if (switch_macaddr) { 4466 if (!ether_addr_equal(switch_macaddr->addr, addr)) { 4467 NL_SET_ERR_MSG_FMT_MOD(extack, 4468 "Switch already configured for MAC address %pM", 4469 switch_macaddr->addr); 4470 return -EBUSY; 4471 } 4472 4473 refcount_inc(&switch_macaddr->refcount); 4474 return 0; 4475 } 4476 4477 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL); 4478 if (!switch_macaddr) 4479 return -ENOMEM; 4480 4481 ether_addr_copy(switch_macaddr->addr, addr); 4482 refcount_set(&switch_macaddr->refcount, 1); 4483 dev->switch_macaddr = switch_macaddr; 4484 4485 /* Program the switch MAC address to hardware */ 4486 for (i = 0; i < ETH_ALEN; i++) { 4487 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, addr[i]); 4488 if (ret) 4489 goto macaddr_drop; 4490 } 4491 4492 return 0; 4493 4494 macaddr_drop: 4495 dev->switch_macaddr = NULL; 4496 refcount_set(&switch_macaddr->refcount, 0); 4497 kfree(switch_macaddr); 4498 4499 return ret; 4500 } 4501 4502 void ksz_switch_macaddr_put(struct dsa_switch *ds) 4503 { 4504 struct ksz_switch_macaddr *switch_macaddr; 4505 struct ksz_device *dev = ds->priv; 4506 const u16 *regs = dev->info->regs; 4507 int i; 4508 4509 /* Make sure concurrent MAC address changes are blocked */ 4510 ASSERT_RTNL(); 4511 4512 switch_macaddr = dev->switch_macaddr; 4513 if (!refcount_dec_and_test(&switch_macaddr->refcount)) 4514 return; 4515 4516 for (i = 0; i < ETH_ALEN; i++) 4517 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0); 4518 4519 dev->switch_macaddr = NULL; 4520 kfree(switch_macaddr); 4521 } 4522 4523 static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr, 4524 struct netlink_ext_ack *extack) 4525 { 4526 struct ksz_device *dev = ds->priv; 4527 enum hsr_version ver; 4528 int ret; 4529 4530 ret = hsr_get_version(hsr, &ver); 4531 if (ret) 4532 return ret; 4533 4534 if (dev->chip_id != KSZ9477_CHIP_ID) { 4535 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload"); 4536 return -EOPNOTSUPP; 4537 } 4538 4539 /* KSZ9477 can support HW offloading of only 1 HSR device */ 4540 if (dev->hsr_dev && hsr != dev->hsr_dev) { 4541 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR"); 4542 return -EOPNOTSUPP; 4543 } 4544 4545 /* KSZ9477 only supports HSR v0 and v1 */ 4546 if (!(ver == HSR_V0 || ver == HSR_V1)) { 4547 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported"); 4548 return -EOPNOTSUPP; 4549 } 4550 4551 /* KSZ9477 can only perform HSR offloading for up to two ports */ 4552 if (hweight8(dev->hsr_ports) >= 2) { 4553 NL_SET_ERR_MSG_MOD(extack, 4554 "Cannot offload more than two ports - using software HSR"); 4555 return -EOPNOTSUPP; 4556 } 4557 4558 /* Self MAC address filtering, to avoid frames traversing 4559 * the HSR ring more than once. 4560 */ 4561 ret = ksz_switch_macaddr_get(ds, port, extack); 4562 if (ret) 4563 return ret; 4564 4565 ksz9477_hsr_join(ds, port, hsr); 4566 dev->hsr_dev = hsr; 4567 dev->hsr_ports |= BIT(port); 4568 4569 return 0; 4570 } 4571 4572 static int ksz_hsr_leave(struct dsa_switch *ds, int port, 4573 struct net_device *hsr) 4574 { 4575 struct ksz_device *dev = ds->priv; 4576 4577 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID); 4578 4579 ksz9477_hsr_leave(ds, port, hsr); 4580 dev->hsr_ports &= ~BIT(port); 4581 if (!dev->hsr_ports) 4582 dev->hsr_dev = NULL; 4583 4584 ksz_switch_macaddr_put(ds); 4585 4586 return 0; 4587 } 4588 4589 static const struct dsa_switch_ops ksz_switch_ops = { 4590 .get_tag_protocol = ksz_get_tag_protocol, 4591 .connect_tag_protocol = ksz_connect_tag_protocol, 4592 .get_phy_flags = ksz_get_phy_flags, 4593 .setup = ksz_setup, 4594 .teardown = ksz_teardown, 4595 .phy_read = ksz_phy_read16, 4596 .phy_write = ksz_phy_write16, 4597 .phylink_get_caps = ksz_phylink_get_caps, 4598 .port_setup = ksz_port_setup, 4599 .set_ageing_time = ksz_set_ageing_time, 4600 .get_strings = ksz_get_strings, 4601 .get_ethtool_stats = ksz_get_ethtool_stats, 4602 .get_sset_count = ksz_sset_count, 4603 .port_bridge_join = ksz_port_bridge_join, 4604 .port_bridge_leave = ksz_port_bridge_leave, 4605 .port_hsr_join = ksz_hsr_join, 4606 .port_hsr_leave = ksz_hsr_leave, 4607 .port_set_mac_address = ksz_port_set_mac_address, 4608 .port_stp_state_set = ksz_port_stp_state_set, 4609 .port_teardown = ksz_port_teardown, 4610 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 4611 .port_bridge_flags = ksz_port_bridge_flags, 4612 .port_fast_age = ksz_port_fast_age, 4613 .port_vlan_filtering = ksz_port_vlan_filtering, 4614 .port_vlan_add = ksz_port_vlan_add, 4615 .port_vlan_del = ksz_port_vlan_del, 4616 .port_fdb_dump = ksz_port_fdb_dump, 4617 .port_fdb_add = ksz_port_fdb_add, 4618 .port_fdb_del = ksz_port_fdb_del, 4619 .port_mdb_add = ksz_port_mdb_add, 4620 .port_mdb_del = ksz_port_mdb_del, 4621 .port_mirror_add = ksz_port_mirror_add, 4622 .port_mirror_del = ksz_port_mirror_del, 4623 .get_stats64 = ksz_get_stats64, 4624 .get_pause_stats = ksz_get_pause_stats, 4625 .port_change_mtu = ksz_change_mtu, 4626 .port_max_mtu = ksz_max_mtu, 4627 .get_wol = ksz_get_wol, 4628 .set_wol = ksz_set_wol, 4629 .get_ts_info = ksz_get_ts_info, 4630 .port_hwtstamp_get = ksz_hwtstamp_get, 4631 .port_hwtstamp_set = ksz_hwtstamp_set, 4632 .port_txtstamp = ksz_port_txtstamp, 4633 .port_rxtstamp = ksz_port_rxtstamp, 4634 .cls_flower_add = ksz_cls_flower_add, 4635 .cls_flower_del = ksz_cls_flower_del, 4636 .port_setup_tc = ksz_setup_tc, 4637 .support_eee = ksz_support_eee, 4638 .get_mac_eee = ksz_get_mac_eee, 4639 .set_mac_eee = ksz_set_mac_eee, 4640 .port_get_default_prio = ksz_port_get_default_prio, 4641 .port_set_default_prio = ksz_port_set_default_prio, 4642 .port_get_dscp_prio = ksz_port_get_dscp_prio, 4643 .port_add_dscp_prio = ksz_port_add_dscp_prio, 4644 .port_del_dscp_prio = ksz_port_del_dscp_prio, 4645 .port_get_apptrust = ksz_port_get_apptrust, 4646 .port_set_apptrust = ksz_port_set_apptrust, 4647 }; 4648 4649 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 4650 { 4651 struct dsa_switch *ds; 4652 struct ksz_device *swdev; 4653 4654 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 4655 if (!ds) 4656 return NULL; 4657 4658 ds->dev = base; 4659 ds->num_ports = DSA_MAX_PORTS; 4660 ds->ops = &ksz_switch_ops; 4661 4662 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 4663 if (!swdev) 4664 return NULL; 4665 4666 ds->priv = swdev; 4667 swdev->dev = base; 4668 4669 swdev->ds = ds; 4670 swdev->priv = priv; 4671 4672 return swdev; 4673 } 4674 EXPORT_SYMBOL(ksz_switch_alloc); 4675 4676 /** 4677 * ksz_switch_shutdown - Shutdown routine for the switch device. 4678 * @dev: The switch device structure. 4679 * 4680 * This function is responsible for initiating a shutdown sequence for the 4681 * switch device. It invokes the reset operation defined in the device 4682 * operations, if available, to reset the switch. Subsequently, it calls the 4683 * DSA framework's shutdown function to ensure a proper shutdown of the DSA 4684 * switch. 4685 */ 4686 void ksz_switch_shutdown(struct ksz_device *dev) 4687 { 4688 bool wol_enabled = false; 4689 4690 ksz_wol_pre_shutdown(dev, &wol_enabled); 4691 4692 if (dev->dev_ops->reset && !wol_enabled) 4693 dev->dev_ops->reset(dev); 4694 4695 dsa_switch_shutdown(dev->ds); 4696 } 4697 EXPORT_SYMBOL(ksz_switch_shutdown); 4698 4699 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 4700 struct device_node *port_dn) 4701 { 4702 phy_interface_t phy_mode = dev->ports[port_num].interface; 4703 int rx_delay = -1, tx_delay = -1; 4704 4705 if (!phy_interface_mode_is_rgmii(phy_mode)) 4706 return; 4707 4708 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 4709 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 4710 4711 if (rx_delay == -1 && tx_delay == -1) { 4712 dev_warn(dev->dev, 4713 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 4714 "please update device tree to specify \"rx-internal-delay-ps\" and " 4715 "\"tx-internal-delay-ps\"", 4716 port_num); 4717 4718 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 4719 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 4720 rx_delay = 2000; 4721 4722 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 4723 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 4724 tx_delay = 2000; 4725 } 4726 4727 if (rx_delay < 0) 4728 rx_delay = 0; 4729 if (tx_delay < 0) 4730 tx_delay = 0; 4731 4732 dev->ports[port_num].rgmii_rx_val = rx_delay; 4733 dev->ports[port_num].rgmii_tx_val = tx_delay; 4734 } 4735 4736 /** 4737 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding 4738 * register value. 4739 * @array: The array of drive strength values to search. 4740 * @array_size: The size of the array. 4741 * @microamp: The drive strength value in microamp to be converted. 4742 * 4743 * This function searches the array of drive strength values for the given 4744 * microamp value and returns the corresponding register value for that drive. 4745 * 4746 * Returns: If found, the corresponding register value for that drive strength 4747 * is returned. Otherwise, -EINVAL is returned indicating an invalid value. 4748 */ 4749 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array, 4750 size_t array_size, int microamp) 4751 { 4752 int i; 4753 4754 for (i = 0; i < array_size; i++) { 4755 if (array[i].microamp == microamp) 4756 return array[i].reg_val; 4757 } 4758 4759 return -EINVAL; 4760 } 4761 4762 /** 4763 * ksz_drive_strength_error() - Report invalid drive strength value 4764 * @dev: ksz device 4765 * @array: The array of drive strength values to search. 4766 * @array_size: The size of the array. 4767 * @microamp: Invalid drive strength value in microamp 4768 * 4769 * This function logs an error message when an unsupported drive strength value 4770 * is detected. It lists out all the supported drive strength values for 4771 * reference in the error message. 4772 */ 4773 static void ksz_drive_strength_error(struct ksz_device *dev, 4774 const struct ksz_drive_strength *array, 4775 size_t array_size, int microamp) 4776 { 4777 char supported_values[100]; 4778 size_t remaining_size; 4779 int added_len; 4780 char *ptr; 4781 int i; 4782 4783 remaining_size = sizeof(supported_values); 4784 ptr = supported_values; 4785 4786 for (i = 0; i < array_size; i++) { 4787 added_len = snprintf(ptr, remaining_size, 4788 i == 0 ? "%d" : ", %d", array[i].microamp); 4789 4790 if (added_len >= remaining_size) 4791 break; 4792 4793 ptr += added_len; 4794 remaining_size -= added_len; 4795 } 4796 4797 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n", 4798 microamp, supported_values); 4799 } 4800 4801 /** 4802 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477 4803 * chip variants. 4804 * @dev: ksz device 4805 * @props: Array of drive strength properties to be applied 4806 * @num_props: Number of properties in the array 4807 * 4808 * This function configures the drive strength for various KSZ9477 chip variants 4809 * based on the provided properties. It handles chip-specific nuances and 4810 * ensures only valid drive strengths are written to the respective chip. 4811 * 4812 * Return: 0 on successful configuration, a negative error code on failure. 4813 */ 4814 static int ksz9477_drive_strength_write(struct ksz_device *dev, 4815 struct ksz_driver_strength_prop *props, 4816 int num_props) 4817 { 4818 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths); 4819 int i, ret, reg; 4820 u8 mask = 0; 4821 u8 val = 0; 4822 4823 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1) 4824 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4825 props[KSZ_DRIVER_STRENGTH_IO].name); 4826 4827 if (dev->chip_id == KSZ8795_CHIP_ID || 4828 dev->chip_id == KSZ8794_CHIP_ID || 4829 dev->chip_id == KSZ8765_CHIP_ID) 4830 reg = KSZ8795_REG_SW_CTRL_20; 4831 else 4832 reg = KSZ9477_REG_SW_IO_STRENGTH; 4833 4834 for (i = 0; i < num_props; i++) { 4835 if (props[i].value == -1) 4836 continue; 4837 4838 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths, 4839 array_size, props[i].value); 4840 if (ret < 0) { 4841 ksz_drive_strength_error(dev, ksz9477_drive_strengths, 4842 array_size, props[i].value); 4843 return ret; 4844 } 4845 4846 mask |= SW_DRIVE_STRENGTH_M << props[i].offset; 4847 val |= ret << props[i].offset; 4848 } 4849 4850 return ksz_rmw8(dev, reg, mask, val); 4851 } 4852 4853 /** 4854 * ksz88x3_drive_strength_write() - Set the drive strength configuration for 4855 * KSZ8863 compatible chip variants. 4856 * @dev: ksz device 4857 * @props: Array of drive strength properties to be set 4858 * @num_props: Number of properties in the array 4859 * 4860 * This function applies the specified drive strength settings to KSZ88X3 chip 4861 * variants (KSZ8873, KSZ8863). 4862 * It ensures the configurations align with what the chip variant supports and 4863 * warns or errors out on unsupported settings. 4864 * 4865 * Return: 0 on success, error code otherwise 4866 */ 4867 static int ksz88x3_drive_strength_write(struct ksz_device *dev, 4868 struct ksz_driver_strength_prop *props, 4869 int num_props) 4870 { 4871 size_t array_size = ARRAY_SIZE(ksz88x3_drive_strengths); 4872 int microamp; 4873 int i, ret; 4874 4875 for (i = 0; i < num_props; i++) { 4876 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO) 4877 continue; 4878 4879 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4880 props[i].name); 4881 } 4882 4883 microamp = props[KSZ_DRIVER_STRENGTH_IO].value; 4884 ret = ksz_drive_strength_to_reg(ksz88x3_drive_strengths, array_size, 4885 microamp); 4886 if (ret < 0) { 4887 ksz_drive_strength_error(dev, ksz88x3_drive_strengths, 4888 array_size, microamp); 4889 return ret; 4890 } 4891 4892 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12, 4893 KSZ8873_DRIVE_STRENGTH_16MA, ret); 4894 } 4895 4896 /** 4897 * ksz_parse_drive_strength() - Extract and apply drive strength configurations 4898 * from device tree properties. 4899 * @dev: ksz device 4900 * 4901 * This function reads the specified drive strength properties from the 4902 * device tree, validates against the supported chip variants, and sets 4903 * them accordingly. An error should be critical here, as the drive strength 4904 * settings are crucial for EMI compliance. 4905 * 4906 * Return: 0 on success, error code otherwise 4907 */ 4908 static int ksz_parse_drive_strength(struct ksz_device *dev) 4909 { 4910 struct ksz_driver_strength_prop of_props[] = { 4911 [KSZ_DRIVER_STRENGTH_HI] = { 4912 .name = "microchip,hi-drive-strength-microamp", 4913 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S, 4914 .value = -1, 4915 }, 4916 [KSZ_DRIVER_STRENGTH_LO] = { 4917 .name = "microchip,lo-drive-strength-microamp", 4918 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S, 4919 .value = -1, 4920 }, 4921 [KSZ_DRIVER_STRENGTH_IO] = { 4922 .name = "microchip,io-drive-strength-microamp", 4923 .offset = 0, /* don't care */ 4924 .value = -1, 4925 }, 4926 }; 4927 struct device_node *np = dev->dev->of_node; 4928 bool have_any_prop = false; 4929 int i, ret; 4930 4931 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4932 ret = of_property_read_u32(np, of_props[i].name, 4933 &of_props[i].value); 4934 if (ret && ret != -EINVAL) 4935 dev_warn(dev->dev, "Failed to read %s\n", 4936 of_props[i].name); 4937 if (ret) 4938 continue; 4939 4940 have_any_prop = true; 4941 } 4942 4943 if (!have_any_prop) 4944 return 0; 4945 4946 switch (dev->chip_id) { 4947 case KSZ88X3_CHIP_ID: 4948 return ksz88x3_drive_strength_write(dev, of_props, 4949 ARRAY_SIZE(of_props)); 4950 case KSZ8795_CHIP_ID: 4951 case KSZ8794_CHIP_ID: 4952 case KSZ8765_CHIP_ID: 4953 case KSZ8563_CHIP_ID: 4954 case KSZ8567_CHIP_ID: 4955 case KSZ9477_CHIP_ID: 4956 case KSZ9563_CHIP_ID: 4957 case KSZ9567_CHIP_ID: 4958 case KSZ9893_CHIP_ID: 4959 case KSZ9896_CHIP_ID: 4960 case KSZ9897_CHIP_ID: 4961 case LAN9646_CHIP_ID: 4962 return ksz9477_drive_strength_write(dev, of_props, 4963 ARRAY_SIZE(of_props)); 4964 default: 4965 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4966 if (of_props[i].value == -1) 4967 continue; 4968 4969 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4970 of_props[i].name); 4971 } 4972 } 4973 4974 return 0; 4975 } 4976 4977 int ksz_switch_register(struct ksz_device *dev) 4978 { 4979 const struct ksz_chip_data *info; 4980 struct device_node *ports; 4981 phy_interface_t interface; 4982 unsigned int port_num; 4983 int ret; 4984 int i; 4985 4986 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 4987 GPIOD_OUT_LOW); 4988 if (IS_ERR(dev->reset_gpio)) 4989 return PTR_ERR(dev->reset_gpio); 4990 4991 if (dev->reset_gpio) { 4992 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4993 usleep_range(10000, 12000); 4994 gpiod_set_value_cansleep(dev->reset_gpio, 0); 4995 msleep(100); 4996 } 4997 4998 mutex_init(&dev->dev_mutex); 4999 mutex_init(&dev->regmap_mutex); 5000 mutex_init(&dev->alu_mutex); 5001 mutex_init(&dev->vlan_mutex); 5002 5003 ret = ksz_switch_detect(dev); 5004 if (ret) 5005 return ret; 5006 5007 info = ksz_lookup_info(dev->chip_id); 5008 if (!info) 5009 return -ENODEV; 5010 5011 /* Update the compatible info with the probed one */ 5012 dev->info = info; 5013 5014 dev_info(dev->dev, "found switch: %s, rev %i\n", 5015 dev->info->dev_name, dev->chip_rev); 5016 5017 ret = ksz_check_device_id(dev); 5018 if (ret) 5019 return ret; 5020 5021 dev->dev_ops = dev->info->ops; 5022 5023 ret = dev->dev_ops->init(dev); 5024 if (ret) 5025 return ret; 5026 5027 dev->ports = devm_kzalloc(dev->dev, 5028 dev->info->port_cnt * sizeof(struct ksz_port), 5029 GFP_KERNEL); 5030 if (!dev->ports) 5031 return -ENOMEM; 5032 5033 for (i = 0; i < dev->info->port_cnt; i++) { 5034 spin_lock_init(&dev->ports[i].mib.stats64_lock); 5035 mutex_init(&dev->ports[i].mib.cnt_mutex); 5036 dev->ports[i].mib.counters = 5037 devm_kzalloc(dev->dev, 5038 sizeof(u64) * (dev->info->mib_cnt + 1), 5039 GFP_KERNEL); 5040 if (!dev->ports[i].mib.counters) 5041 return -ENOMEM; 5042 5043 dev->ports[i].ksz_dev = dev; 5044 dev->ports[i].num = i; 5045 } 5046 5047 /* set the real number of ports */ 5048 dev->ds->num_ports = dev->info->port_cnt; 5049 5050 /* set the phylink ops */ 5051 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops; 5052 5053 /* Host port interface will be self detected, or specifically set in 5054 * device tree. 5055 */ 5056 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 5057 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 5058 if (dev->dev->of_node) { 5059 ret = of_get_phy_mode(dev->dev->of_node, &interface); 5060 if (ret == 0) 5061 dev->compat_interface = interface; 5062 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 5063 if (!ports) 5064 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 5065 if (ports) { 5066 for_each_available_child_of_node_scoped(ports, port) { 5067 if (of_property_read_u32(port, "reg", 5068 &port_num)) 5069 continue; 5070 if (!(dev->port_mask & BIT(port_num))) { 5071 of_node_put(ports); 5072 return -EINVAL; 5073 } 5074 of_get_phy_mode(port, 5075 &dev->ports[port_num].interface); 5076 5077 ksz_parse_rgmii_delay(dev, port_num, port); 5078 } 5079 of_node_put(ports); 5080 } 5081 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 5082 "microchip,synclko-125"); 5083 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 5084 "microchip,synclko-disable"); 5085 if (dev->synclko_125 && dev->synclko_disable) { 5086 dev_err(dev->dev, "inconsistent synclko settings\n"); 5087 return -EINVAL; 5088 } 5089 5090 dev->wakeup_source = of_property_read_bool(dev->dev->of_node, 5091 "wakeup-source"); 5092 dev->pme_active_high = of_property_read_bool(dev->dev->of_node, 5093 "microchip,pme-active-high"); 5094 } 5095 5096 ret = dsa_register_switch(dev->ds); 5097 if (ret) { 5098 dev->dev_ops->exit(dev); 5099 return ret; 5100 } 5101 5102 /* Read MIB counters every 30 seconds to avoid overflow. */ 5103 dev->mib_read_interval = msecs_to_jiffies(5000); 5104 5105 /* Start the MIB timer. */ 5106 schedule_delayed_work(&dev->mib_read, 0); 5107 5108 return ret; 5109 } 5110 EXPORT_SYMBOL(ksz_switch_register); 5111 5112 void ksz_switch_remove(struct ksz_device *dev) 5113 { 5114 /* timer started */ 5115 if (dev->mib_read_interval) { 5116 dev->mib_read_interval = 0; 5117 cancel_delayed_work_sync(&dev->mib_read); 5118 } 5119 5120 dev->dev_ops->exit(dev); 5121 dsa_unregister_switch(dev->ds); 5122 5123 if (dev->reset_gpio) 5124 gpiod_set_value_cansleep(dev->reset_gpio, 1); 5125 5126 } 5127 EXPORT_SYMBOL(ksz_switch_remove); 5128 5129 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 5130 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 5131 MODULE_LICENSE("GPL"); 5132