1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/if_hsr.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/of.h> 23 #include <linux/of_mdio.h> 24 #include <linux/of_net.h> 25 #include <linux/micrel_phy.h> 26 #include <net/dsa.h> 27 #include <net/pkt_cls.h> 28 #include <net/switchdev.h> 29 30 #include "ksz_common.h" 31 #include "ksz_ptp.h" 32 #include "ksz8.h" 33 #include "ksz9477.h" 34 #include "lan937x.h" 35 36 #define MIB_COUNTER_NUM 0x20 37 38 struct ksz_stats_raw { 39 u64 rx_hi; 40 u64 rx_undersize; 41 u64 rx_fragments; 42 u64 rx_oversize; 43 u64 rx_jabbers; 44 u64 rx_symbol_err; 45 u64 rx_crc_err; 46 u64 rx_align_err; 47 u64 rx_mac_ctrl; 48 u64 rx_pause; 49 u64 rx_bcast; 50 u64 rx_mcast; 51 u64 rx_ucast; 52 u64 rx_64_or_less; 53 u64 rx_65_127; 54 u64 rx_128_255; 55 u64 rx_256_511; 56 u64 rx_512_1023; 57 u64 rx_1024_1522; 58 u64 rx_1523_2000; 59 u64 rx_2001; 60 u64 tx_hi; 61 u64 tx_late_col; 62 u64 tx_pause; 63 u64 tx_bcast; 64 u64 tx_mcast; 65 u64 tx_ucast; 66 u64 tx_deferred; 67 u64 tx_total_col; 68 u64 tx_exc_col; 69 u64 tx_single_col; 70 u64 tx_mult_col; 71 u64 rx_total; 72 u64 tx_total; 73 u64 rx_discards; 74 u64 tx_discards; 75 }; 76 77 struct ksz88xx_stats_raw { 78 u64 rx; 79 u64 rx_hi; 80 u64 rx_undersize; 81 u64 rx_fragments; 82 u64 rx_oversize; 83 u64 rx_jabbers; 84 u64 rx_symbol_err; 85 u64 rx_crc_err; 86 u64 rx_align_err; 87 u64 rx_mac_ctrl; 88 u64 rx_pause; 89 u64 rx_bcast; 90 u64 rx_mcast; 91 u64 rx_ucast; 92 u64 rx_64_or_less; 93 u64 rx_65_127; 94 u64 rx_128_255; 95 u64 rx_256_511; 96 u64 rx_512_1023; 97 u64 rx_1024_1522; 98 u64 tx; 99 u64 tx_hi; 100 u64 tx_late_col; 101 u64 tx_pause; 102 u64 tx_bcast; 103 u64 tx_mcast; 104 u64 tx_ucast; 105 u64 tx_deferred; 106 u64 tx_total_col; 107 u64 tx_exc_col; 108 u64 tx_single_col; 109 u64 tx_mult_col; 110 u64 rx_discards; 111 u64 tx_discards; 112 }; 113 114 static const struct ksz_mib_names ksz88xx_mib_names[] = { 115 { 0x00, "rx" }, 116 { 0x01, "rx_hi" }, 117 { 0x02, "rx_undersize" }, 118 { 0x03, "rx_fragments" }, 119 { 0x04, "rx_oversize" }, 120 { 0x05, "rx_jabbers" }, 121 { 0x06, "rx_symbol_err" }, 122 { 0x07, "rx_crc_err" }, 123 { 0x08, "rx_align_err" }, 124 { 0x09, "rx_mac_ctrl" }, 125 { 0x0a, "rx_pause" }, 126 { 0x0b, "rx_bcast" }, 127 { 0x0c, "rx_mcast" }, 128 { 0x0d, "rx_ucast" }, 129 { 0x0e, "rx_64_or_less" }, 130 { 0x0f, "rx_65_127" }, 131 { 0x10, "rx_128_255" }, 132 { 0x11, "rx_256_511" }, 133 { 0x12, "rx_512_1023" }, 134 { 0x13, "rx_1024_1522" }, 135 { 0x14, "tx" }, 136 { 0x15, "tx_hi" }, 137 { 0x16, "tx_late_col" }, 138 { 0x17, "tx_pause" }, 139 { 0x18, "tx_bcast" }, 140 { 0x19, "tx_mcast" }, 141 { 0x1a, "tx_ucast" }, 142 { 0x1b, "tx_deferred" }, 143 { 0x1c, "tx_total_col" }, 144 { 0x1d, "tx_exc_col" }, 145 { 0x1e, "tx_single_col" }, 146 { 0x1f, "tx_mult_col" }, 147 { 0x100, "rx_discards" }, 148 { 0x101, "tx_discards" }, 149 }; 150 151 static const struct ksz_mib_names ksz9477_mib_names[] = { 152 { 0x00, "rx_hi" }, 153 { 0x01, "rx_undersize" }, 154 { 0x02, "rx_fragments" }, 155 { 0x03, "rx_oversize" }, 156 { 0x04, "rx_jabbers" }, 157 { 0x05, "rx_symbol_err" }, 158 { 0x06, "rx_crc_err" }, 159 { 0x07, "rx_align_err" }, 160 { 0x08, "rx_mac_ctrl" }, 161 { 0x09, "rx_pause" }, 162 { 0x0A, "rx_bcast" }, 163 { 0x0B, "rx_mcast" }, 164 { 0x0C, "rx_ucast" }, 165 { 0x0D, "rx_64_or_less" }, 166 { 0x0E, "rx_65_127" }, 167 { 0x0F, "rx_128_255" }, 168 { 0x10, "rx_256_511" }, 169 { 0x11, "rx_512_1023" }, 170 { 0x12, "rx_1024_1522" }, 171 { 0x13, "rx_1523_2000" }, 172 { 0x14, "rx_2001" }, 173 { 0x15, "tx_hi" }, 174 { 0x16, "tx_late_col" }, 175 { 0x17, "tx_pause" }, 176 { 0x18, "tx_bcast" }, 177 { 0x19, "tx_mcast" }, 178 { 0x1A, "tx_ucast" }, 179 { 0x1B, "tx_deferred" }, 180 { 0x1C, "tx_total_col" }, 181 { 0x1D, "tx_exc_col" }, 182 { 0x1E, "tx_single_col" }, 183 { 0x1F, "tx_mult_col" }, 184 { 0x80, "rx_total" }, 185 { 0x81, "tx_total" }, 186 { 0x82, "rx_discards" }, 187 { 0x83, "tx_discards" }, 188 }; 189 190 struct ksz_driver_strength_prop { 191 const char *name; 192 int offset; 193 int value; 194 }; 195 196 enum ksz_driver_strength_type { 197 KSZ_DRIVER_STRENGTH_HI, 198 KSZ_DRIVER_STRENGTH_LO, 199 KSZ_DRIVER_STRENGTH_IO, 200 }; 201 202 /** 203 * struct ksz_drive_strength - drive strength mapping 204 * @reg_val: register value 205 * @microamp: microamp value 206 */ 207 struct ksz_drive_strength { 208 u32 reg_val; 209 u32 microamp; 210 }; 211 212 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants 213 * 214 * This values are not documented in KSZ9477 variants but confirmed by 215 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893 216 * and KSZ8563 are using same register (drive strength) settings like KSZ8795. 217 * 218 * Documentation in KSZ8795CLX provides more information with some 219 * recommendations: 220 * - for high speed signals 221 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using 222 * 2.5V or 3.3V VDDIO. 223 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with 224 * using 1.8V VDDIO. 225 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V 226 * or 3.3V VDDIO. 227 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO. 228 * 5. In same interface, the heavy loading should use higher one of the 229 * drive current strength. 230 * - for low speed signals 231 * 1. 3.3V VDDIO, use either 4 mA or 8 mA. 232 * 2. 2.5V VDDIO, use either 8 mA or 12 mA. 233 * 3. 1.8V VDDIO, use either 12 mA or 16 mA. 234 * 4. If it is heavy loading, can use higher drive current strength. 235 */ 236 static const struct ksz_drive_strength ksz9477_drive_strengths[] = { 237 { SW_DRIVE_STRENGTH_2MA, 2000 }, 238 { SW_DRIVE_STRENGTH_4MA, 4000 }, 239 { SW_DRIVE_STRENGTH_8MA, 8000 }, 240 { SW_DRIVE_STRENGTH_12MA, 12000 }, 241 { SW_DRIVE_STRENGTH_16MA, 16000 }, 242 { SW_DRIVE_STRENGTH_20MA, 20000 }, 243 { SW_DRIVE_STRENGTH_24MA, 24000 }, 244 { SW_DRIVE_STRENGTH_28MA, 28000 }, 245 }; 246 247 /* ksz8830_drive_strengths - Drive strength mapping for KSZ8830, KSZ8873, .. 248 * variants. 249 * This values are documented in KSZ8873 and KSZ8863 datasheets. 250 */ 251 static const struct ksz_drive_strength ksz8830_drive_strengths[] = { 252 { 0, 8000 }, 253 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 }, 254 }; 255 256 static const struct ksz_dev_ops ksz8_dev_ops = { 257 .setup = ksz8_setup, 258 .get_port_addr = ksz8_get_port_addr, 259 .cfg_port_member = ksz8_cfg_port_member, 260 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 261 .port_setup = ksz8_port_setup, 262 .r_phy = ksz8_r_phy, 263 .w_phy = ksz8_w_phy, 264 .r_mib_cnt = ksz8_r_mib_cnt, 265 .r_mib_pkt = ksz8_r_mib_pkt, 266 .r_mib_stat64 = ksz88xx_r_mib_stats64, 267 .freeze_mib = ksz8_freeze_mib, 268 .port_init_cnt = ksz8_port_init_cnt, 269 .fdb_dump = ksz8_fdb_dump, 270 .fdb_add = ksz8_fdb_add, 271 .fdb_del = ksz8_fdb_del, 272 .mdb_add = ksz8_mdb_add, 273 .mdb_del = ksz8_mdb_del, 274 .vlan_filtering = ksz8_port_vlan_filtering, 275 .vlan_add = ksz8_port_vlan_add, 276 .vlan_del = ksz8_port_vlan_del, 277 .mirror_add = ksz8_port_mirror_add, 278 .mirror_del = ksz8_port_mirror_del, 279 .get_caps = ksz8_get_caps, 280 .phylink_mac_link_up = ksz8_phylink_mac_link_up, 281 .config_cpu_port = ksz8_config_cpu_port, 282 .enable_stp_addr = ksz8_enable_stp_addr, 283 .reset = ksz8_reset_switch, 284 .init = ksz8_switch_init, 285 .exit = ksz8_switch_exit, 286 .change_mtu = ksz8_change_mtu, 287 }; 288 289 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 290 unsigned int mode, 291 phy_interface_t interface, 292 struct phy_device *phydev, int speed, 293 int duplex, bool tx_pause, 294 bool rx_pause); 295 296 static const struct ksz_dev_ops ksz9477_dev_ops = { 297 .setup = ksz9477_setup, 298 .get_port_addr = ksz9477_get_port_addr, 299 .cfg_port_member = ksz9477_cfg_port_member, 300 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 301 .port_setup = ksz9477_port_setup, 302 .set_ageing_time = ksz9477_set_ageing_time, 303 .r_phy = ksz9477_r_phy, 304 .w_phy = ksz9477_w_phy, 305 .r_mib_cnt = ksz9477_r_mib_cnt, 306 .r_mib_pkt = ksz9477_r_mib_pkt, 307 .r_mib_stat64 = ksz_r_mib_stats64, 308 .freeze_mib = ksz9477_freeze_mib, 309 .port_init_cnt = ksz9477_port_init_cnt, 310 .vlan_filtering = ksz9477_port_vlan_filtering, 311 .vlan_add = ksz9477_port_vlan_add, 312 .vlan_del = ksz9477_port_vlan_del, 313 .mirror_add = ksz9477_port_mirror_add, 314 .mirror_del = ksz9477_port_mirror_del, 315 .get_caps = ksz9477_get_caps, 316 .fdb_dump = ksz9477_fdb_dump, 317 .fdb_add = ksz9477_fdb_add, 318 .fdb_del = ksz9477_fdb_del, 319 .mdb_add = ksz9477_mdb_add, 320 .mdb_del = ksz9477_mdb_del, 321 .change_mtu = ksz9477_change_mtu, 322 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 323 .get_wol = ksz9477_get_wol, 324 .set_wol = ksz9477_set_wol, 325 .wol_pre_shutdown = ksz9477_wol_pre_shutdown, 326 .config_cpu_port = ksz9477_config_cpu_port, 327 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc, 328 .enable_stp_addr = ksz9477_enable_stp_addr, 329 .reset = ksz9477_reset_switch, 330 .init = ksz9477_switch_init, 331 .exit = ksz9477_switch_exit, 332 }; 333 334 static const struct ksz_dev_ops lan937x_dev_ops = { 335 .setup = lan937x_setup, 336 .teardown = lan937x_teardown, 337 .get_port_addr = ksz9477_get_port_addr, 338 .cfg_port_member = ksz9477_cfg_port_member, 339 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 340 .port_setup = lan937x_port_setup, 341 .set_ageing_time = lan937x_set_ageing_time, 342 .r_phy = lan937x_r_phy, 343 .w_phy = lan937x_w_phy, 344 .r_mib_cnt = ksz9477_r_mib_cnt, 345 .r_mib_pkt = ksz9477_r_mib_pkt, 346 .r_mib_stat64 = ksz_r_mib_stats64, 347 .freeze_mib = ksz9477_freeze_mib, 348 .port_init_cnt = ksz9477_port_init_cnt, 349 .vlan_filtering = ksz9477_port_vlan_filtering, 350 .vlan_add = ksz9477_port_vlan_add, 351 .vlan_del = ksz9477_port_vlan_del, 352 .mirror_add = ksz9477_port_mirror_add, 353 .mirror_del = ksz9477_port_mirror_del, 354 .get_caps = lan937x_phylink_get_caps, 355 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 356 .fdb_dump = ksz9477_fdb_dump, 357 .fdb_add = ksz9477_fdb_add, 358 .fdb_del = ksz9477_fdb_del, 359 .mdb_add = ksz9477_mdb_add, 360 .mdb_del = ksz9477_mdb_del, 361 .change_mtu = lan937x_change_mtu, 362 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 363 .config_cpu_port = lan937x_config_cpu_port, 364 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 365 .enable_stp_addr = ksz9477_enable_stp_addr, 366 .reset = lan937x_reset_switch, 367 .init = lan937x_switch_init, 368 .exit = lan937x_switch_exit, 369 }; 370 371 static const u16 ksz8795_regs[] = { 372 [REG_SW_MAC_ADDR] = 0x68, 373 [REG_IND_CTRL_0] = 0x6E, 374 [REG_IND_DATA_8] = 0x70, 375 [REG_IND_DATA_CHECK] = 0x72, 376 [REG_IND_DATA_HI] = 0x71, 377 [REG_IND_DATA_LO] = 0x75, 378 [REG_IND_MIB_CHECK] = 0x74, 379 [REG_IND_BYTE] = 0xA0, 380 [P_FORCE_CTRL] = 0x0C, 381 [P_LINK_STATUS] = 0x0E, 382 [P_LOCAL_CTRL] = 0x07, 383 [P_NEG_RESTART_CTRL] = 0x0D, 384 [P_REMOTE_STATUS] = 0x08, 385 [P_SPEED_STATUS] = 0x09, 386 [S_TAIL_TAG_CTRL] = 0x0C, 387 [P_STP_CTRL] = 0x02, 388 [S_START_CTRL] = 0x01, 389 [S_BROADCAST_CTRL] = 0x06, 390 [S_MULTICAST_CTRL] = 0x04, 391 [P_XMII_CTRL_0] = 0x06, 392 [P_XMII_CTRL_1] = 0x06, 393 }; 394 395 static const u32 ksz8795_masks[] = { 396 [PORT_802_1P_REMAPPING] = BIT(7), 397 [SW_TAIL_TAG_ENABLE] = BIT(1), 398 [MIB_COUNTER_OVERFLOW] = BIT(6), 399 [MIB_COUNTER_VALID] = BIT(5), 400 [VLAN_TABLE_FID] = GENMASK(6, 0), 401 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 402 [VLAN_TABLE_VALID] = BIT(12), 403 [STATIC_MAC_TABLE_VALID] = BIT(21), 404 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 405 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 406 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 407 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 408 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 409 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 410 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 411 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 412 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 413 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 414 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 415 [P_MII_TX_FLOW_CTRL] = BIT(5), 416 [P_MII_RX_FLOW_CTRL] = BIT(5), 417 }; 418 419 static const u8 ksz8795_xmii_ctrl0[] = { 420 [P_MII_100MBIT] = 0, 421 [P_MII_10MBIT] = 1, 422 [P_MII_FULL_DUPLEX] = 0, 423 [P_MII_HALF_DUPLEX] = 1, 424 }; 425 426 static const u8 ksz8795_xmii_ctrl1[] = { 427 [P_RGMII_SEL] = 3, 428 [P_GMII_SEL] = 2, 429 [P_RMII_SEL] = 1, 430 [P_MII_SEL] = 0, 431 [P_GMII_1GBIT] = 1, 432 [P_GMII_NOT_1GBIT] = 0, 433 }; 434 435 static const u8 ksz8795_shifts[] = { 436 [VLAN_TABLE_MEMBERSHIP_S] = 7, 437 [VLAN_TABLE] = 16, 438 [STATIC_MAC_FWD_PORTS] = 16, 439 [STATIC_MAC_FID] = 24, 440 [DYNAMIC_MAC_ENTRIES_H] = 3, 441 [DYNAMIC_MAC_ENTRIES] = 29, 442 [DYNAMIC_MAC_FID] = 16, 443 [DYNAMIC_MAC_TIMESTAMP] = 27, 444 [DYNAMIC_MAC_SRC_PORT] = 24, 445 }; 446 447 static const u16 ksz8863_regs[] = { 448 [REG_SW_MAC_ADDR] = 0x70, 449 [REG_IND_CTRL_0] = 0x79, 450 [REG_IND_DATA_8] = 0x7B, 451 [REG_IND_DATA_CHECK] = 0x7B, 452 [REG_IND_DATA_HI] = 0x7C, 453 [REG_IND_DATA_LO] = 0x80, 454 [REG_IND_MIB_CHECK] = 0x80, 455 [P_FORCE_CTRL] = 0x0C, 456 [P_LINK_STATUS] = 0x0E, 457 [P_LOCAL_CTRL] = 0x0C, 458 [P_NEG_RESTART_CTRL] = 0x0D, 459 [P_REMOTE_STATUS] = 0x0E, 460 [P_SPEED_STATUS] = 0x0F, 461 [S_TAIL_TAG_CTRL] = 0x03, 462 [P_STP_CTRL] = 0x02, 463 [S_START_CTRL] = 0x01, 464 [S_BROADCAST_CTRL] = 0x06, 465 [S_MULTICAST_CTRL] = 0x04, 466 }; 467 468 static const u32 ksz8863_masks[] = { 469 [PORT_802_1P_REMAPPING] = BIT(3), 470 [SW_TAIL_TAG_ENABLE] = BIT(6), 471 [MIB_COUNTER_OVERFLOW] = BIT(7), 472 [MIB_COUNTER_VALID] = BIT(6), 473 [VLAN_TABLE_FID] = GENMASK(15, 12), 474 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 475 [VLAN_TABLE_VALID] = BIT(19), 476 [STATIC_MAC_TABLE_VALID] = BIT(19), 477 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 478 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 479 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 480 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 481 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 482 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 483 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 484 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 485 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 486 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 487 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 488 }; 489 490 static u8 ksz8863_shifts[] = { 491 [VLAN_TABLE_MEMBERSHIP_S] = 16, 492 [STATIC_MAC_FWD_PORTS] = 16, 493 [STATIC_MAC_FID] = 22, 494 [DYNAMIC_MAC_ENTRIES_H] = 8, 495 [DYNAMIC_MAC_ENTRIES] = 24, 496 [DYNAMIC_MAC_FID] = 16, 497 [DYNAMIC_MAC_TIMESTAMP] = 22, 498 [DYNAMIC_MAC_SRC_PORT] = 20, 499 }; 500 501 static const u16 ksz9477_regs[] = { 502 [REG_SW_MAC_ADDR] = 0x0302, 503 [P_STP_CTRL] = 0x0B04, 504 [S_START_CTRL] = 0x0300, 505 [S_BROADCAST_CTRL] = 0x0332, 506 [S_MULTICAST_CTRL] = 0x0331, 507 [P_XMII_CTRL_0] = 0x0300, 508 [P_XMII_CTRL_1] = 0x0301, 509 }; 510 511 static const u32 ksz9477_masks[] = { 512 [ALU_STAT_WRITE] = 0, 513 [ALU_STAT_READ] = 1, 514 [P_MII_TX_FLOW_CTRL] = BIT(5), 515 [P_MII_RX_FLOW_CTRL] = BIT(3), 516 }; 517 518 static const u8 ksz9477_shifts[] = { 519 [ALU_STAT_INDEX] = 16, 520 }; 521 522 static const u8 ksz9477_xmii_ctrl0[] = { 523 [P_MII_100MBIT] = 1, 524 [P_MII_10MBIT] = 0, 525 [P_MII_FULL_DUPLEX] = 1, 526 [P_MII_HALF_DUPLEX] = 0, 527 }; 528 529 static const u8 ksz9477_xmii_ctrl1[] = { 530 [P_RGMII_SEL] = 0, 531 [P_RMII_SEL] = 1, 532 [P_GMII_SEL] = 2, 533 [P_MII_SEL] = 3, 534 [P_GMII_1GBIT] = 0, 535 [P_GMII_NOT_1GBIT] = 1, 536 }; 537 538 static const u32 lan937x_masks[] = { 539 [ALU_STAT_WRITE] = 1, 540 [ALU_STAT_READ] = 2, 541 [P_MII_TX_FLOW_CTRL] = BIT(5), 542 [P_MII_RX_FLOW_CTRL] = BIT(3), 543 }; 544 545 static const u8 lan937x_shifts[] = { 546 [ALU_STAT_INDEX] = 8, 547 }; 548 549 static const struct regmap_range ksz8563_valid_regs[] = { 550 regmap_reg_range(0x0000, 0x0003), 551 regmap_reg_range(0x0006, 0x0006), 552 regmap_reg_range(0x000f, 0x001f), 553 regmap_reg_range(0x0100, 0x0100), 554 regmap_reg_range(0x0104, 0x0107), 555 regmap_reg_range(0x010d, 0x010d), 556 regmap_reg_range(0x0110, 0x0113), 557 regmap_reg_range(0x0120, 0x012b), 558 regmap_reg_range(0x0201, 0x0201), 559 regmap_reg_range(0x0210, 0x0213), 560 regmap_reg_range(0x0300, 0x0300), 561 regmap_reg_range(0x0302, 0x031b), 562 regmap_reg_range(0x0320, 0x032b), 563 regmap_reg_range(0x0330, 0x0336), 564 regmap_reg_range(0x0338, 0x033e), 565 regmap_reg_range(0x0340, 0x035f), 566 regmap_reg_range(0x0370, 0x0370), 567 regmap_reg_range(0x0378, 0x0378), 568 regmap_reg_range(0x037c, 0x037d), 569 regmap_reg_range(0x0390, 0x0393), 570 regmap_reg_range(0x0400, 0x040e), 571 regmap_reg_range(0x0410, 0x042f), 572 regmap_reg_range(0x0500, 0x0519), 573 regmap_reg_range(0x0520, 0x054b), 574 regmap_reg_range(0x0550, 0x05b3), 575 576 /* port 1 */ 577 regmap_reg_range(0x1000, 0x1001), 578 regmap_reg_range(0x1004, 0x100b), 579 regmap_reg_range(0x1013, 0x1013), 580 regmap_reg_range(0x1017, 0x1017), 581 regmap_reg_range(0x101b, 0x101b), 582 regmap_reg_range(0x101f, 0x1021), 583 regmap_reg_range(0x1030, 0x1030), 584 regmap_reg_range(0x1100, 0x1111), 585 regmap_reg_range(0x111a, 0x111d), 586 regmap_reg_range(0x1122, 0x1127), 587 regmap_reg_range(0x112a, 0x112b), 588 regmap_reg_range(0x1136, 0x1139), 589 regmap_reg_range(0x113e, 0x113f), 590 regmap_reg_range(0x1400, 0x1401), 591 regmap_reg_range(0x1403, 0x1403), 592 regmap_reg_range(0x1410, 0x1417), 593 regmap_reg_range(0x1420, 0x1423), 594 regmap_reg_range(0x1500, 0x1507), 595 regmap_reg_range(0x1600, 0x1612), 596 regmap_reg_range(0x1800, 0x180f), 597 regmap_reg_range(0x1900, 0x1907), 598 regmap_reg_range(0x1914, 0x191b), 599 regmap_reg_range(0x1a00, 0x1a03), 600 regmap_reg_range(0x1a04, 0x1a08), 601 regmap_reg_range(0x1b00, 0x1b01), 602 regmap_reg_range(0x1b04, 0x1b04), 603 regmap_reg_range(0x1c00, 0x1c05), 604 regmap_reg_range(0x1c08, 0x1c1b), 605 606 /* port 2 */ 607 regmap_reg_range(0x2000, 0x2001), 608 regmap_reg_range(0x2004, 0x200b), 609 regmap_reg_range(0x2013, 0x2013), 610 regmap_reg_range(0x2017, 0x2017), 611 regmap_reg_range(0x201b, 0x201b), 612 regmap_reg_range(0x201f, 0x2021), 613 regmap_reg_range(0x2030, 0x2030), 614 regmap_reg_range(0x2100, 0x2111), 615 regmap_reg_range(0x211a, 0x211d), 616 regmap_reg_range(0x2122, 0x2127), 617 regmap_reg_range(0x212a, 0x212b), 618 regmap_reg_range(0x2136, 0x2139), 619 regmap_reg_range(0x213e, 0x213f), 620 regmap_reg_range(0x2400, 0x2401), 621 regmap_reg_range(0x2403, 0x2403), 622 regmap_reg_range(0x2410, 0x2417), 623 regmap_reg_range(0x2420, 0x2423), 624 regmap_reg_range(0x2500, 0x2507), 625 regmap_reg_range(0x2600, 0x2612), 626 regmap_reg_range(0x2800, 0x280f), 627 regmap_reg_range(0x2900, 0x2907), 628 regmap_reg_range(0x2914, 0x291b), 629 regmap_reg_range(0x2a00, 0x2a03), 630 regmap_reg_range(0x2a04, 0x2a08), 631 regmap_reg_range(0x2b00, 0x2b01), 632 regmap_reg_range(0x2b04, 0x2b04), 633 regmap_reg_range(0x2c00, 0x2c05), 634 regmap_reg_range(0x2c08, 0x2c1b), 635 636 /* port 3 */ 637 regmap_reg_range(0x3000, 0x3001), 638 regmap_reg_range(0x3004, 0x300b), 639 regmap_reg_range(0x3013, 0x3013), 640 regmap_reg_range(0x3017, 0x3017), 641 regmap_reg_range(0x301b, 0x301b), 642 regmap_reg_range(0x301f, 0x3021), 643 regmap_reg_range(0x3030, 0x3030), 644 regmap_reg_range(0x3300, 0x3301), 645 regmap_reg_range(0x3303, 0x3303), 646 regmap_reg_range(0x3400, 0x3401), 647 regmap_reg_range(0x3403, 0x3403), 648 regmap_reg_range(0x3410, 0x3417), 649 regmap_reg_range(0x3420, 0x3423), 650 regmap_reg_range(0x3500, 0x3507), 651 regmap_reg_range(0x3600, 0x3612), 652 regmap_reg_range(0x3800, 0x380f), 653 regmap_reg_range(0x3900, 0x3907), 654 regmap_reg_range(0x3914, 0x391b), 655 regmap_reg_range(0x3a00, 0x3a03), 656 regmap_reg_range(0x3a04, 0x3a08), 657 regmap_reg_range(0x3b00, 0x3b01), 658 regmap_reg_range(0x3b04, 0x3b04), 659 regmap_reg_range(0x3c00, 0x3c05), 660 regmap_reg_range(0x3c08, 0x3c1b), 661 }; 662 663 static const struct regmap_access_table ksz8563_register_set = { 664 .yes_ranges = ksz8563_valid_regs, 665 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 666 }; 667 668 static const struct regmap_range ksz9477_valid_regs[] = { 669 regmap_reg_range(0x0000, 0x0003), 670 regmap_reg_range(0x0006, 0x0006), 671 regmap_reg_range(0x0010, 0x001f), 672 regmap_reg_range(0x0100, 0x0100), 673 regmap_reg_range(0x0103, 0x0107), 674 regmap_reg_range(0x010d, 0x010d), 675 regmap_reg_range(0x0110, 0x0113), 676 regmap_reg_range(0x0120, 0x012b), 677 regmap_reg_range(0x0201, 0x0201), 678 regmap_reg_range(0x0210, 0x0213), 679 regmap_reg_range(0x0300, 0x0300), 680 regmap_reg_range(0x0302, 0x031b), 681 regmap_reg_range(0x0320, 0x032b), 682 regmap_reg_range(0x0330, 0x0336), 683 regmap_reg_range(0x0338, 0x033b), 684 regmap_reg_range(0x033e, 0x033e), 685 regmap_reg_range(0x0340, 0x035f), 686 regmap_reg_range(0x0370, 0x0370), 687 regmap_reg_range(0x0378, 0x0378), 688 regmap_reg_range(0x037c, 0x037d), 689 regmap_reg_range(0x0390, 0x0393), 690 regmap_reg_range(0x0400, 0x040e), 691 regmap_reg_range(0x0410, 0x042f), 692 regmap_reg_range(0x0444, 0x044b), 693 regmap_reg_range(0x0450, 0x046f), 694 regmap_reg_range(0x0500, 0x0519), 695 regmap_reg_range(0x0520, 0x054b), 696 regmap_reg_range(0x0550, 0x05b3), 697 regmap_reg_range(0x0604, 0x060b), 698 regmap_reg_range(0x0610, 0x0612), 699 regmap_reg_range(0x0614, 0x062c), 700 regmap_reg_range(0x0640, 0x0645), 701 regmap_reg_range(0x0648, 0x064d), 702 703 /* port 1 */ 704 regmap_reg_range(0x1000, 0x1001), 705 regmap_reg_range(0x1013, 0x1013), 706 regmap_reg_range(0x1017, 0x1017), 707 regmap_reg_range(0x101b, 0x101b), 708 regmap_reg_range(0x101f, 0x1020), 709 regmap_reg_range(0x1030, 0x1030), 710 regmap_reg_range(0x1100, 0x1115), 711 regmap_reg_range(0x111a, 0x111f), 712 regmap_reg_range(0x1120, 0x112b), 713 regmap_reg_range(0x1134, 0x113b), 714 regmap_reg_range(0x113c, 0x113f), 715 regmap_reg_range(0x1400, 0x1401), 716 regmap_reg_range(0x1403, 0x1403), 717 regmap_reg_range(0x1410, 0x1417), 718 regmap_reg_range(0x1420, 0x1423), 719 regmap_reg_range(0x1500, 0x1507), 720 regmap_reg_range(0x1600, 0x1613), 721 regmap_reg_range(0x1800, 0x180f), 722 regmap_reg_range(0x1820, 0x1827), 723 regmap_reg_range(0x1830, 0x1837), 724 regmap_reg_range(0x1840, 0x184b), 725 regmap_reg_range(0x1900, 0x1907), 726 regmap_reg_range(0x1914, 0x191b), 727 regmap_reg_range(0x1920, 0x1920), 728 regmap_reg_range(0x1923, 0x1927), 729 regmap_reg_range(0x1a00, 0x1a03), 730 regmap_reg_range(0x1a04, 0x1a07), 731 regmap_reg_range(0x1b00, 0x1b01), 732 regmap_reg_range(0x1b04, 0x1b04), 733 regmap_reg_range(0x1c00, 0x1c05), 734 regmap_reg_range(0x1c08, 0x1c1b), 735 736 /* port 2 */ 737 regmap_reg_range(0x2000, 0x2001), 738 regmap_reg_range(0x2013, 0x2013), 739 regmap_reg_range(0x2017, 0x2017), 740 regmap_reg_range(0x201b, 0x201b), 741 regmap_reg_range(0x201f, 0x2020), 742 regmap_reg_range(0x2030, 0x2030), 743 regmap_reg_range(0x2100, 0x2115), 744 regmap_reg_range(0x211a, 0x211f), 745 regmap_reg_range(0x2120, 0x212b), 746 regmap_reg_range(0x2134, 0x213b), 747 regmap_reg_range(0x213c, 0x213f), 748 regmap_reg_range(0x2400, 0x2401), 749 regmap_reg_range(0x2403, 0x2403), 750 regmap_reg_range(0x2410, 0x2417), 751 regmap_reg_range(0x2420, 0x2423), 752 regmap_reg_range(0x2500, 0x2507), 753 regmap_reg_range(0x2600, 0x2613), 754 regmap_reg_range(0x2800, 0x280f), 755 regmap_reg_range(0x2820, 0x2827), 756 regmap_reg_range(0x2830, 0x2837), 757 regmap_reg_range(0x2840, 0x284b), 758 regmap_reg_range(0x2900, 0x2907), 759 regmap_reg_range(0x2914, 0x291b), 760 regmap_reg_range(0x2920, 0x2920), 761 regmap_reg_range(0x2923, 0x2927), 762 regmap_reg_range(0x2a00, 0x2a03), 763 regmap_reg_range(0x2a04, 0x2a07), 764 regmap_reg_range(0x2b00, 0x2b01), 765 regmap_reg_range(0x2b04, 0x2b04), 766 regmap_reg_range(0x2c00, 0x2c05), 767 regmap_reg_range(0x2c08, 0x2c1b), 768 769 /* port 3 */ 770 regmap_reg_range(0x3000, 0x3001), 771 regmap_reg_range(0x3013, 0x3013), 772 regmap_reg_range(0x3017, 0x3017), 773 regmap_reg_range(0x301b, 0x301b), 774 regmap_reg_range(0x301f, 0x3020), 775 regmap_reg_range(0x3030, 0x3030), 776 regmap_reg_range(0x3100, 0x3115), 777 regmap_reg_range(0x311a, 0x311f), 778 regmap_reg_range(0x3120, 0x312b), 779 regmap_reg_range(0x3134, 0x313b), 780 regmap_reg_range(0x313c, 0x313f), 781 regmap_reg_range(0x3400, 0x3401), 782 regmap_reg_range(0x3403, 0x3403), 783 regmap_reg_range(0x3410, 0x3417), 784 regmap_reg_range(0x3420, 0x3423), 785 regmap_reg_range(0x3500, 0x3507), 786 regmap_reg_range(0x3600, 0x3613), 787 regmap_reg_range(0x3800, 0x380f), 788 regmap_reg_range(0x3820, 0x3827), 789 regmap_reg_range(0x3830, 0x3837), 790 regmap_reg_range(0x3840, 0x384b), 791 regmap_reg_range(0x3900, 0x3907), 792 regmap_reg_range(0x3914, 0x391b), 793 regmap_reg_range(0x3920, 0x3920), 794 regmap_reg_range(0x3923, 0x3927), 795 regmap_reg_range(0x3a00, 0x3a03), 796 regmap_reg_range(0x3a04, 0x3a07), 797 regmap_reg_range(0x3b00, 0x3b01), 798 regmap_reg_range(0x3b04, 0x3b04), 799 regmap_reg_range(0x3c00, 0x3c05), 800 regmap_reg_range(0x3c08, 0x3c1b), 801 802 /* port 4 */ 803 regmap_reg_range(0x4000, 0x4001), 804 regmap_reg_range(0x4013, 0x4013), 805 regmap_reg_range(0x4017, 0x4017), 806 regmap_reg_range(0x401b, 0x401b), 807 regmap_reg_range(0x401f, 0x4020), 808 regmap_reg_range(0x4030, 0x4030), 809 regmap_reg_range(0x4100, 0x4115), 810 regmap_reg_range(0x411a, 0x411f), 811 regmap_reg_range(0x4120, 0x412b), 812 regmap_reg_range(0x4134, 0x413b), 813 regmap_reg_range(0x413c, 0x413f), 814 regmap_reg_range(0x4400, 0x4401), 815 regmap_reg_range(0x4403, 0x4403), 816 regmap_reg_range(0x4410, 0x4417), 817 regmap_reg_range(0x4420, 0x4423), 818 regmap_reg_range(0x4500, 0x4507), 819 regmap_reg_range(0x4600, 0x4613), 820 regmap_reg_range(0x4800, 0x480f), 821 regmap_reg_range(0x4820, 0x4827), 822 regmap_reg_range(0x4830, 0x4837), 823 regmap_reg_range(0x4840, 0x484b), 824 regmap_reg_range(0x4900, 0x4907), 825 regmap_reg_range(0x4914, 0x491b), 826 regmap_reg_range(0x4920, 0x4920), 827 regmap_reg_range(0x4923, 0x4927), 828 regmap_reg_range(0x4a00, 0x4a03), 829 regmap_reg_range(0x4a04, 0x4a07), 830 regmap_reg_range(0x4b00, 0x4b01), 831 regmap_reg_range(0x4b04, 0x4b04), 832 regmap_reg_range(0x4c00, 0x4c05), 833 regmap_reg_range(0x4c08, 0x4c1b), 834 835 /* port 5 */ 836 regmap_reg_range(0x5000, 0x5001), 837 regmap_reg_range(0x5013, 0x5013), 838 regmap_reg_range(0x5017, 0x5017), 839 regmap_reg_range(0x501b, 0x501b), 840 regmap_reg_range(0x501f, 0x5020), 841 regmap_reg_range(0x5030, 0x5030), 842 regmap_reg_range(0x5100, 0x5115), 843 regmap_reg_range(0x511a, 0x511f), 844 regmap_reg_range(0x5120, 0x512b), 845 regmap_reg_range(0x5134, 0x513b), 846 regmap_reg_range(0x513c, 0x513f), 847 regmap_reg_range(0x5400, 0x5401), 848 regmap_reg_range(0x5403, 0x5403), 849 regmap_reg_range(0x5410, 0x5417), 850 regmap_reg_range(0x5420, 0x5423), 851 regmap_reg_range(0x5500, 0x5507), 852 regmap_reg_range(0x5600, 0x5613), 853 regmap_reg_range(0x5800, 0x580f), 854 regmap_reg_range(0x5820, 0x5827), 855 regmap_reg_range(0x5830, 0x5837), 856 regmap_reg_range(0x5840, 0x584b), 857 regmap_reg_range(0x5900, 0x5907), 858 regmap_reg_range(0x5914, 0x591b), 859 regmap_reg_range(0x5920, 0x5920), 860 regmap_reg_range(0x5923, 0x5927), 861 regmap_reg_range(0x5a00, 0x5a03), 862 regmap_reg_range(0x5a04, 0x5a07), 863 regmap_reg_range(0x5b00, 0x5b01), 864 regmap_reg_range(0x5b04, 0x5b04), 865 regmap_reg_range(0x5c00, 0x5c05), 866 regmap_reg_range(0x5c08, 0x5c1b), 867 868 /* port 6 */ 869 regmap_reg_range(0x6000, 0x6001), 870 regmap_reg_range(0x6013, 0x6013), 871 regmap_reg_range(0x6017, 0x6017), 872 regmap_reg_range(0x601b, 0x601b), 873 regmap_reg_range(0x601f, 0x6020), 874 regmap_reg_range(0x6030, 0x6030), 875 regmap_reg_range(0x6300, 0x6301), 876 regmap_reg_range(0x6400, 0x6401), 877 regmap_reg_range(0x6403, 0x6403), 878 regmap_reg_range(0x6410, 0x6417), 879 regmap_reg_range(0x6420, 0x6423), 880 regmap_reg_range(0x6500, 0x6507), 881 regmap_reg_range(0x6600, 0x6613), 882 regmap_reg_range(0x6800, 0x680f), 883 regmap_reg_range(0x6820, 0x6827), 884 regmap_reg_range(0x6830, 0x6837), 885 regmap_reg_range(0x6840, 0x684b), 886 regmap_reg_range(0x6900, 0x6907), 887 regmap_reg_range(0x6914, 0x691b), 888 regmap_reg_range(0x6920, 0x6920), 889 regmap_reg_range(0x6923, 0x6927), 890 regmap_reg_range(0x6a00, 0x6a03), 891 regmap_reg_range(0x6a04, 0x6a07), 892 regmap_reg_range(0x6b00, 0x6b01), 893 regmap_reg_range(0x6b04, 0x6b04), 894 regmap_reg_range(0x6c00, 0x6c05), 895 regmap_reg_range(0x6c08, 0x6c1b), 896 897 /* port 7 */ 898 regmap_reg_range(0x7000, 0x7001), 899 regmap_reg_range(0x7013, 0x7013), 900 regmap_reg_range(0x7017, 0x7017), 901 regmap_reg_range(0x701b, 0x701b), 902 regmap_reg_range(0x701f, 0x7020), 903 regmap_reg_range(0x7030, 0x7030), 904 regmap_reg_range(0x7200, 0x7203), 905 regmap_reg_range(0x7206, 0x7207), 906 regmap_reg_range(0x7300, 0x7301), 907 regmap_reg_range(0x7400, 0x7401), 908 regmap_reg_range(0x7403, 0x7403), 909 regmap_reg_range(0x7410, 0x7417), 910 regmap_reg_range(0x7420, 0x7423), 911 regmap_reg_range(0x7500, 0x7507), 912 regmap_reg_range(0x7600, 0x7613), 913 regmap_reg_range(0x7800, 0x780f), 914 regmap_reg_range(0x7820, 0x7827), 915 regmap_reg_range(0x7830, 0x7837), 916 regmap_reg_range(0x7840, 0x784b), 917 regmap_reg_range(0x7900, 0x7907), 918 regmap_reg_range(0x7914, 0x791b), 919 regmap_reg_range(0x7920, 0x7920), 920 regmap_reg_range(0x7923, 0x7927), 921 regmap_reg_range(0x7a00, 0x7a03), 922 regmap_reg_range(0x7a04, 0x7a07), 923 regmap_reg_range(0x7b00, 0x7b01), 924 regmap_reg_range(0x7b04, 0x7b04), 925 regmap_reg_range(0x7c00, 0x7c05), 926 regmap_reg_range(0x7c08, 0x7c1b), 927 }; 928 929 static const struct regmap_access_table ksz9477_register_set = { 930 .yes_ranges = ksz9477_valid_regs, 931 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 932 }; 933 934 static const struct regmap_range ksz9896_valid_regs[] = { 935 regmap_reg_range(0x0000, 0x0003), 936 regmap_reg_range(0x0006, 0x0006), 937 regmap_reg_range(0x0010, 0x001f), 938 regmap_reg_range(0x0100, 0x0100), 939 regmap_reg_range(0x0103, 0x0107), 940 regmap_reg_range(0x010d, 0x010d), 941 regmap_reg_range(0x0110, 0x0113), 942 regmap_reg_range(0x0120, 0x0127), 943 regmap_reg_range(0x0201, 0x0201), 944 regmap_reg_range(0x0210, 0x0213), 945 regmap_reg_range(0x0300, 0x0300), 946 regmap_reg_range(0x0302, 0x030b), 947 regmap_reg_range(0x0310, 0x031b), 948 regmap_reg_range(0x0320, 0x032b), 949 regmap_reg_range(0x0330, 0x0336), 950 regmap_reg_range(0x0338, 0x033b), 951 regmap_reg_range(0x033e, 0x033e), 952 regmap_reg_range(0x0340, 0x035f), 953 regmap_reg_range(0x0370, 0x0370), 954 regmap_reg_range(0x0378, 0x0378), 955 regmap_reg_range(0x037c, 0x037d), 956 regmap_reg_range(0x0390, 0x0393), 957 regmap_reg_range(0x0400, 0x040e), 958 regmap_reg_range(0x0410, 0x042f), 959 960 /* port 1 */ 961 regmap_reg_range(0x1000, 0x1001), 962 regmap_reg_range(0x1013, 0x1013), 963 regmap_reg_range(0x1017, 0x1017), 964 regmap_reg_range(0x101b, 0x101b), 965 regmap_reg_range(0x101f, 0x1020), 966 regmap_reg_range(0x1030, 0x1030), 967 regmap_reg_range(0x1100, 0x1115), 968 regmap_reg_range(0x111a, 0x111f), 969 regmap_reg_range(0x1122, 0x1127), 970 regmap_reg_range(0x112a, 0x112b), 971 regmap_reg_range(0x1136, 0x1139), 972 regmap_reg_range(0x113e, 0x113f), 973 regmap_reg_range(0x1400, 0x1401), 974 regmap_reg_range(0x1403, 0x1403), 975 regmap_reg_range(0x1410, 0x1417), 976 regmap_reg_range(0x1420, 0x1423), 977 regmap_reg_range(0x1500, 0x1507), 978 regmap_reg_range(0x1600, 0x1612), 979 regmap_reg_range(0x1800, 0x180f), 980 regmap_reg_range(0x1820, 0x1827), 981 regmap_reg_range(0x1830, 0x1837), 982 regmap_reg_range(0x1840, 0x184b), 983 regmap_reg_range(0x1900, 0x1907), 984 regmap_reg_range(0x1914, 0x1915), 985 regmap_reg_range(0x1a00, 0x1a03), 986 regmap_reg_range(0x1a04, 0x1a07), 987 regmap_reg_range(0x1b00, 0x1b01), 988 regmap_reg_range(0x1b04, 0x1b04), 989 990 /* port 2 */ 991 regmap_reg_range(0x2000, 0x2001), 992 regmap_reg_range(0x2013, 0x2013), 993 regmap_reg_range(0x2017, 0x2017), 994 regmap_reg_range(0x201b, 0x201b), 995 regmap_reg_range(0x201f, 0x2020), 996 regmap_reg_range(0x2030, 0x2030), 997 regmap_reg_range(0x2100, 0x2115), 998 regmap_reg_range(0x211a, 0x211f), 999 regmap_reg_range(0x2122, 0x2127), 1000 regmap_reg_range(0x212a, 0x212b), 1001 regmap_reg_range(0x2136, 0x2139), 1002 regmap_reg_range(0x213e, 0x213f), 1003 regmap_reg_range(0x2400, 0x2401), 1004 regmap_reg_range(0x2403, 0x2403), 1005 regmap_reg_range(0x2410, 0x2417), 1006 regmap_reg_range(0x2420, 0x2423), 1007 regmap_reg_range(0x2500, 0x2507), 1008 regmap_reg_range(0x2600, 0x2612), 1009 regmap_reg_range(0x2800, 0x280f), 1010 regmap_reg_range(0x2820, 0x2827), 1011 regmap_reg_range(0x2830, 0x2837), 1012 regmap_reg_range(0x2840, 0x284b), 1013 regmap_reg_range(0x2900, 0x2907), 1014 regmap_reg_range(0x2914, 0x2915), 1015 regmap_reg_range(0x2a00, 0x2a03), 1016 regmap_reg_range(0x2a04, 0x2a07), 1017 regmap_reg_range(0x2b00, 0x2b01), 1018 regmap_reg_range(0x2b04, 0x2b04), 1019 1020 /* port 3 */ 1021 regmap_reg_range(0x3000, 0x3001), 1022 regmap_reg_range(0x3013, 0x3013), 1023 regmap_reg_range(0x3017, 0x3017), 1024 regmap_reg_range(0x301b, 0x301b), 1025 regmap_reg_range(0x301f, 0x3020), 1026 regmap_reg_range(0x3030, 0x3030), 1027 regmap_reg_range(0x3100, 0x3115), 1028 regmap_reg_range(0x311a, 0x311f), 1029 regmap_reg_range(0x3122, 0x3127), 1030 regmap_reg_range(0x312a, 0x312b), 1031 regmap_reg_range(0x3136, 0x3139), 1032 regmap_reg_range(0x313e, 0x313f), 1033 regmap_reg_range(0x3400, 0x3401), 1034 regmap_reg_range(0x3403, 0x3403), 1035 regmap_reg_range(0x3410, 0x3417), 1036 regmap_reg_range(0x3420, 0x3423), 1037 regmap_reg_range(0x3500, 0x3507), 1038 regmap_reg_range(0x3600, 0x3612), 1039 regmap_reg_range(0x3800, 0x380f), 1040 regmap_reg_range(0x3820, 0x3827), 1041 regmap_reg_range(0x3830, 0x3837), 1042 regmap_reg_range(0x3840, 0x384b), 1043 regmap_reg_range(0x3900, 0x3907), 1044 regmap_reg_range(0x3914, 0x3915), 1045 regmap_reg_range(0x3a00, 0x3a03), 1046 regmap_reg_range(0x3a04, 0x3a07), 1047 regmap_reg_range(0x3b00, 0x3b01), 1048 regmap_reg_range(0x3b04, 0x3b04), 1049 1050 /* port 4 */ 1051 regmap_reg_range(0x4000, 0x4001), 1052 regmap_reg_range(0x4013, 0x4013), 1053 regmap_reg_range(0x4017, 0x4017), 1054 regmap_reg_range(0x401b, 0x401b), 1055 regmap_reg_range(0x401f, 0x4020), 1056 regmap_reg_range(0x4030, 0x4030), 1057 regmap_reg_range(0x4100, 0x4115), 1058 regmap_reg_range(0x411a, 0x411f), 1059 regmap_reg_range(0x4122, 0x4127), 1060 regmap_reg_range(0x412a, 0x412b), 1061 regmap_reg_range(0x4136, 0x4139), 1062 regmap_reg_range(0x413e, 0x413f), 1063 regmap_reg_range(0x4400, 0x4401), 1064 regmap_reg_range(0x4403, 0x4403), 1065 regmap_reg_range(0x4410, 0x4417), 1066 regmap_reg_range(0x4420, 0x4423), 1067 regmap_reg_range(0x4500, 0x4507), 1068 regmap_reg_range(0x4600, 0x4612), 1069 regmap_reg_range(0x4800, 0x480f), 1070 regmap_reg_range(0x4820, 0x4827), 1071 regmap_reg_range(0x4830, 0x4837), 1072 regmap_reg_range(0x4840, 0x484b), 1073 regmap_reg_range(0x4900, 0x4907), 1074 regmap_reg_range(0x4914, 0x4915), 1075 regmap_reg_range(0x4a00, 0x4a03), 1076 regmap_reg_range(0x4a04, 0x4a07), 1077 regmap_reg_range(0x4b00, 0x4b01), 1078 regmap_reg_range(0x4b04, 0x4b04), 1079 1080 /* port 5 */ 1081 regmap_reg_range(0x5000, 0x5001), 1082 regmap_reg_range(0x5013, 0x5013), 1083 regmap_reg_range(0x5017, 0x5017), 1084 regmap_reg_range(0x501b, 0x501b), 1085 regmap_reg_range(0x501f, 0x5020), 1086 regmap_reg_range(0x5030, 0x5030), 1087 regmap_reg_range(0x5100, 0x5115), 1088 regmap_reg_range(0x511a, 0x511f), 1089 regmap_reg_range(0x5122, 0x5127), 1090 regmap_reg_range(0x512a, 0x512b), 1091 regmap_reg_range(0x5136, 0x5139), 1092 regmap_reg_range(0x513e, 0x513f), 1093 regmap_reg_range(0x5400, 0x5401), 1094 regmap_reg_range(0x5403, 0x5403), 1095 regmap_reg_range(0x5410, 0x5417), 1096 regmap_reg_range(0x5420, 0x5423), 1097 regmap_reg_range(0x5500, 0x5507), 1098 regmap_reg_range(0x5600, 0x5612), 1099 regmap_reg_range(0x5800, 0x580f), 1100 regmap_reg_range(0x5820, 0x5827), 1101 regmap_reg_range(0x5830, 0x5837), 1102 regmap_reg_range(0x5840, 0x584b), 1103 regmap_reg_range(0x5900, 0x5907), 1104 regmap_reg_range(0x5914, 0x5915), 1105 regmap_reg_range(0x5a00, 0x5a03), 1106 regmap_reg_range(0x5a04, 0x5a07), 1107 regmap_reg_range(0x5b00, 0x5b01), 1108 regmap_reg_range(0x5b04, 0x5b04), 1109 1110 /* port 6 */ 1111 regmap_reg_range(0x6000, 0x6001), 1112 regmap_reg_range(0x6013, 0x6013), 1113 regmap_reg_range(0x6017, 0x6017), 1114 regmap_reg_range(0x601b, 0x601b), 1115 regmap_reg_range(0x601f, 0x6020), 1116 regmap_reg_range(0x6030, 0x6030), 1117 regmap_reg_range(0x6100, 0x6115), 1118 regmap_reg_range(0x611a, 0x611f), 1119 regmap_reg_range(0x6122, 0x6127), 1120 regmap_reg_range(0x612a, 0x612b), 1121 regmap_reg_range(0x6136, 0x6139), 1122 regmap_reg_range(0x613e, 0x613f), 1123 regmap_reg_range(0x6300, 0x6301), 1124 regmap_reg_range(0x6400, 0x6401), 1125 regmap_reg_range(0x6403, 0x6403), 1126 regmap_reg_range(0x6410, 0x6417), 1127 regmap_reg_range(0x6420, 0x6423), 1128 regmap_reg_range(0x6500, 0x6507), 1129 regmap_reg_range(0x6600, 0x6612), 1130 regmap_reg_range(0x6800, 0x680f), 1131 regmap_reg_range(0x6820, 0x6827), 1132 regmap_reg_range(0x6830, 0x6837), 1133 regmap_reg_range(0x6840, 0x684b), 1134 regmap_reg_range(0x6900, 0x6907), 1135 regmap_reg_range(0x6914, 0x6915), 1136 regmap_reg_range(0x6a00, 0x6a03), 1137 regmap_reg_range(0x6a04, 0x6a07), 1138 regmap_reg_range(0x6b00, 0x6b01), 1139 regmap_reg_range(0x6b04, 0x6b04), 1140 }; 1141 1142 static const struct regmap_access_table ksz9896_register_set = { 1143 .yes_ranges = ksz9896_valid_regs, 1144 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1145 }; 1146 1147 static const struct regmap_range ksz8873_valid_regs[] = { 1148 regmap_reg_range(0x00, 0x01), 1149 /* global control register */ 1150 regmap_reg_range(0x02, 0x0f), 1151 1152 /* port registers */ 1153 regmap_reg_range(0x10, 0x1d), 1154 regmap_reg_range(0x1e, 0x1f), 1155 regmap_reg_range(0x20, 0x2d), 1156 regmap_reg_range(0x2e, 0x2f), 1157 regmap_reg_range(0x30, 0x39), 1158 regmap_reg_range(0x3f, 0x3f), 1159 1160 /* advanced control registers */ 1161 regmap_reg_range(0x60, 0x6f), 1162 regmap_reg_range(0x70, 0x75), 1163 regmap_reg_range(0x76, 0x78), 1164 regmap_reg_range(0x79, 0x7a), 1165 regmap_reg_range(0x7b, 0x83), 1166 regmap_reg_range(0x8e, 0x99), 1167 regmap_reg_range(0x9a, 0xa5), 1168 regmap_reg_range(0xa6, 0xa6), 1169 regmap_reg_range(0xa7, 0xaa), 1170 regmap_reg_range(0xab, 0xae), 1171 regmap_reg_range(0xaf, 0xba), 1172 regmap_reg_range(0xbb, 0xbc), 1173 regmap_reg_range(0xbd, 0xbd), 1174 regmap_reg_range(0xc0, 0xc0), 1175 regmap_reg_range(0xc2, 0xc2), 1176 regmap_reg_range(0xc3, 0xc3), 1177 regmap_reg_range(0xc4, 0xc4), 1178 regmap_reg_range(0xc6, 0xc6), 1179 }; 1180 1181 static const struct regmap_access_table ksz8873_register_set = { 1182 .yes_ranges = ksz8873_valid_regs, 1183 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), 1184 }; 1185 1186 const struct ksz_chip_data ksz_switch_chips[] = { 1187 [KSZ8563] = { 1188 .chip_id = KSZ8563_CHIP_ID, 1189 .dev_name = "KSZ8563", 1190 .num_vlans = 4096, 1191 .num_alus = 4096, 1192 .num_statics = 16, 1193 .cpu_ports = 0x07, /* can be configured as cpu port */ 1194 .port_cnt = 3, /* total port count */ 1195 .port_nirqs = 3, 1196 .num_tx_queues = 4, 1197 .tc_cbs_supported = true, 1198 .tc_ets_supported = true, 1199 .ops = &ksz9477_dev_ops, 1200 .mib_names = ksz9477_mib_names, 1201 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1202 .reg_mib_cnt = MIB_COUNTER_NUM, 1203 .regs = ksz9477_regs, 1204 .masks = ksz9477_masks, 1205 .shifts = ksz9477_shifts, 1206 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1207 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1208 .supports_mii = {false, false, true}, 1209 .supports_rmii = {false, false, true}, 1210 .supports_rgmii = {false, false, true}, 1211 .internal_phy = {true, true, false}, 1212 .gbit_capable = {false, false, true}, 1213 .wr_table = &ksz8563_register_set, 1214 .rd_table = &ksz8563_register_set, 1215 }, 1216 1217 [KSZ8795] = { 1218 .chip_id = KSZ8795_CHIP_ID, 1219 .dev_name = "KSZ8795", 1220 .num_vlans = 4096, 1221 .num_alus = 0, 1222 .num_statics = 8, 1223 .cpu_ports = 0x10, /* can be configured as cpu port */ 1224 .port_cnt = 5, /* total cpu and user ports */ 1225 .num_tx_queues = 4, 1226 .ops = &ksz8_dev_ops, 1227 .ksz87xx_eee_link_erratum = true, 1228 .mib_names = ksz9477_mib_names, 1229 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1230 .reg_mib_cnt = MIB_COUNTER_NUM, 1231 .regs = ksz8795_regs, 1232 .masks = ksz8795_masks, 1233 .shifts = ksz8795_shifts, 1234 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1235 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1236 .supports_mii = {false, false, false, false, true}, 1237 .supports_rmii = {false, false, false, false, true}, 1238 .supports_rgmii = {false, false, false, false, true}, 1239 .internal_phy = {true, true, true, true, false}, 1240 }, 1241 1242 [KSZ8794] = { 1243 /* WARNING 1244 * ======= 1245 * KSZ8794 is similar to KSZ8795, except the port map 1246 * contains a gap between external and CPU ports, the 1247 * port map is NOT continuous. The per-port register 1248 * map is shifted accordingly too, i.e. registers at 1249 * offset 0x40 are NOT used on KSZ8794 and they ARE 1250 * used on KSZ8795 for external port 3. 1251 * external cpu 1252 * KSZ8794 0,1,2 4 1253 * KSZ8795 0,1,2,3 4 1254 * KSZ8765 0,1,2,3 4 1255 * port_cnt is configured as 5, even though it is 4 1256 */ 1257 .chip_id = KSZ8794_CHIP_ID, 1258 .dev_name = "KSZ8794", 1259 .num_vlans = 4096, 1260 .num_alus = 0, 1261 .num_statics = 8, 1262 .cpu_ports = 0x10, /* can be configured as cpu port */ 1263 .port_cnt = 5, /* total cpu and user ports */ 1264 .num_tx_queues = 4, 1265 .ops = &ksz8_dev_ops, 1266 .ksz87xx_eee_link_erratum = true, 1267 .mib_names = ksz9477_mib_names, 1268 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1269 .reg_mib_cnt = MIB_COUNTER_NUM, 1270 .regs = ksz8795_regs, 1271 .masks = ksz8795_masks, 1272 .shifts = ksz8795_shifts, 1273 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1274 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1275 .supports_mii = {false, false, false, false, true}, 1276 .supports_rmii = {false, false, false, false, true}, 1277 .supports_rgmii = {false, false, false, false, true}, 1278 .internal_phy = {true, true, true, false, false}, 1279 }, 1280 1281 [KSZ8765] = { 1282 .chip_id = KSZ8765_CHIP_ID, 1283 .dev_name = "KSZ8765", 1284 .num_vlans = 4096, 1285 .num_alus = 0, 1286 .num_statics = 8, 1287 .cpu_ports = 0x10, /* can be configured as cpu port */ 1288 .port_cnt = 5, /* total cpu and user ports */ 1289 .num_tx_queues = 4, 1290 .ops = &ksz8_dev_ops, 1291 .ksz87xx_eee_link_erratum = true, 1292 .mib_names = ksz9477_mib_names, 1293 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1294 .reg_mib_cnt = MIB_COUNTER_NUM, 1295 .regs = ksz8795_regs, 1296 .masks = ksz8795_masks, 1297 .shifts = ksz8795_shifts, 1298 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1299 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1300 .supports_mii = {false, false, false, false, true}, 1301 .supports_rmii = {false, false, false, false, true}, 1302 .supports_rgmii = {false, false, false, false, true}, 1303 .internal_phy = {true, true, true, true, false}, 1304 }, 1305 1306 [KSZ8830] = { 1307 .chip_id = KSZ8830_CHIP_ID, 1308 .dev_name = "KSZ8863/KSZ8873", 1309 .num_vlans = 16, 1310 .num_alus = 0, 1311 .num_statics = 8, 1312 .cpu_ports = 0x4, /* can be configured as cpu port */ 1313 .port_cnt = 3, 1314 .num_tx_queues = 4, 1315 .ops = &ksz8_dev_ops, 1316 .mib_names = ksz88xx_mib_names, 1317 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1318 .reg_mib_cnt = MIB_COUNTER_NUM, 1319 .regs = ksz8863_regs, 1320 .masks = ksz8863_masks, 1321 .shifts = ksz8863_shifts, 1322 .supports_mii = {false, false, true}, 1323 .supports_rmii = {false, false, true}, 1324 .internal_phy = {true, true, false}, 1325 .wr_table = &ksz8873_register_set, 1326 .rd_table = &ksz8873_register_set, 1327 }, 1328 1329 [KSZ9477] = { 1330 .chip_id = KSZ9477_CHIP_ID, 1331 .dev_name = "KSZ9477", 1332 .num_vlans = 4096, 1333 .num_alus = 4096, 1334 .num_statics = 16, 1335 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1336 .port_cnt = 7, /* total physical port count */ 1337 .port_nirqs = 4, 1338 .num_tx_queues = 4, 1339 .tc_cbs_supported = true, 1340 .tc_ets_supported = true, 1341 .ops = &ksz9477_dev_ops, 1342 .mib_names = ksz9477_mib_names, 1343 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1344 .reg_mib_cnt = MIB_COUNTER_NUM, 1345 .regs = ksz9477_regs, 1346 .masks = ksz9477_masks, 1347 .shifts = ksz9477_shifts, 1348 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1349 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1350 .supports_mii = {false, false, false, false, 1351 false, true, false}, 1352 .supports_rmii = {false, false, false, false, 1353 false, true, false}, 1354 .supports_rgmii = {false, false, false, false, 1355 false, true, false}, 1356 .internal_phy = {true, true, true, true, 1357 true, false, false}, 1358 .gbit_capable = {true, true, true, true, true, true, true}, 1359 .wr_table = &ksz9477_register_set, 1360 .rd_table = &ksz9477_register_set, 1361 }, 1362 1363 [KSZ9896] = { 1364 .chip_id = KSZ9896_CHIP_ID, 1365 .dev_name = "KSZ9896", 1366 .num_vlans = 4096, 1367 .num_alus = 4096, 1368 .num_statics = 16, 1369 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1370 .port_cnt = 6, /* total physical port count */ 1371 .port_nirqs = 2, 1372 .num_tx_queues = 4, 1373 .ops = &ksz9477_dev_ops, 1374 .mib_names = ksz9477_mib_names, 1375 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1376 .reg_mib_cnt = MIB_COUNTER_NUM, 1377 .regs = ksz9477_regs, 1378 .masks = ksz9477_masks, 1379 .shifts = ksz9477_shifts, 1380 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1381 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1382 .supports_mii = {false, false, false, false, 1383 false, true}, 1384 .supports_rmii = {false, false, false, false, 1385 false, true}, 1386 .supports_rgmii = {false, false, false, false, 1387 false, true}, 1388 .internal_phy = {true, true, true, true, 1389 true, false}, 1390 .gbit_capable = {true, true, true, true, true, true}, 1391 .wr_table = &ksz9896_register_set, 1392 .rd_table = &ksz9896_register_set, 1393 }, 1394 1395 [KSZ9897] = { 1396 .chip_id = KSZ9897_CHIP_ID, 1397 .dev_name = "KSZ9897", 1398 .num_vlans = 4096, 1399 .num_alus = 4096, 1400 .num_statics = 16, 1401 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1402 .port_cnt = 7, /* total physical port count */ 1403 .port_nirqs = 2, 1404 .num_tx_queues = 4, 1405 .ops = &ksz9477_dev_ops, 1406 .mib_names = ksz9477_mib_names, 1407 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1408 .reg_mib_cnt = MIB_COUNTER_NUM, 1409 .regs = ksz9477_regs, 1410 .masks = ksz9477_masks, 1411 .shifts = ksz9477_shifts, 1412 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1413 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1414 .supports_mii = {false, false, false, false, 1415 false, true, true}, 1416 .supports_rmii = {false, false, false, false, 1417 false, true, true}, 1418 .supports_rgmii = {false, false, false, false, 1419 false, true, true}, 1420 .internal_phy = {true, true, true, true, 1421 true, false, false}, 1422 .gbit_capable = {true, true, true, true, true, true, true}, 1423 }, 1424 1425 [KSZ9893] = { 1426 .chip_id = KSZ9893_CHIP_ID, 1427 .dev_name = "KSZ9893", 1428 .num_vlans = 4096, 1429 .num_alus = 4096, 1430 .num_statics = 16, 1431 .cpu_ports = 0x07, /* can be configured as cpu port */ 1432 .port_cnt = 3, /* total port count */ 1433 .port_nirqs = 2, 1434 .num_tx_queues = 4, 1435 .ops = &ksz9477_dev_ops, 1436 .mib_names = ksz9477_mib_names, 1437 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1438 .reg_mib_cnt = MIB_COUNTER_NUM, 1439 .regs = ksz9477_regs, 1440 .masks = ksz9477_masks, 1441 .shifts = ksz9477_shifts, 1442 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1443 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1444 .supports_mii = {false, false, true}, 1445 .supports_rmii = {false, false, true}, 1446 .supports_rgmii = {false, false, true}, 1447 .internal_phy = {true, true, false}, 1448 .gbit_capable = {true, true, true}, 1449 }, 1450 1451 [KSZ9563] = { 1452 .chip_id = KSZ9563_CHIP_ID, 1453 .dev_name = "KSZ9563", 1454 .num_vlans = 4096, 1455 .num_alus = 4096, 1456 .num_statics = 16, 1457 .cpu_ports = 0x07, /* can be configured as cpu port */ 1458 .port_cnt = 3, /* total port count */ 1459 .port_nirqs = 3, 1460 .num_tx_queues = 4, 1461 .tc_cbs_supported = true, 1462 .tc_ets_supported = true, 1463 .ops = &ksz9477_dev_ops, 1464 .mib_names = ksz9477_mib_names, 1465 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1466 .reg_mib_cnt = MIB_COUNTER_NUM, 1467 .regs = ksz9477_regs, 1468 .masks = ksz9477_masks, 1469 .shifts = ksz9477_shifts, 1470 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1471 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1472 .supports_mii = {false, false, true}, 1473 .supports_rmii = {false, false, true}, 1474 .supports_rgmii = {false, false, true}, 1475 .internal_phy = {true, true, false}, 1476 .gbit_capable = {true, true, true}, 1477 }, 1478 1479 [KSZ9567] = { 1480 .chip_id = KSZ9567_CHIP_ID, 1481 .dev_name = "KSZ9567", 1482 .num_vlans = 4096, 1483 .num_alus = 4096, 1484 .num_statics = 16, 1485 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1486 .port_cnt = 7, /* total physical port count */ 1487 .port_nirqs = 3, 1488 .num_tx_queues = 4, 1489 .tc_cbs_supported = true, 1490 .tc_ets_supported = true, 1491 .ops = &ksz9477_dev_ops, 1492 .mib_names = ksz9477_mib_names, 1493 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1494 .reg_mib_cnt = MIB_COUNTER_NUM, 1495 .regs = ksz9477_regs, 1496 .masks = ksz9477_masks, 1497 .shifts = ksz9477_shifts, 1498 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1499 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1500 .supports_mii = {false, false, false, false, 1501 false, true, true}, 1502 .supports_rmii = {false, false, false, false, 1503 false, true, true}, 1504 .supports_rgmii = {false, false, false, false, 1505 false, true, true}, 1506 .internal_phy = {true, true, true, true, 1507 true, false, false}, 1508 .gbit_capable = {true, true, true, true, true, true, true}, 1509 }, 1510 1511 [LAN9370] = { 1512 .chip_id = LAN9370_CHIP_ID, 1513 .dev_name = "LAN9370", 1514 .num_vlans = 4096, 1515 .num_alus = 1024, 1516 .num_statics = 256, 1517 .cpu_ports = 0x10, /* can be configured as cpu port */ 1518 .port_cnt = 5, /* total physical port count */ 1519 .port_nirqs = 6, 1520 .num_tx_queues = 8, 1521 .tc_cbs_supported = true, 1522 .tc_ets_supported = true, 1523 .ops = &lan937x_dev_ops, 1524 .mib_names = ksz9477_mib_names, 1525 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1526 .reg_mib_cnt = MIB_COUNTER_NUM, 1527 .regs = ksz9477_regs, 1528 .masks = lan937x_masks, 1529 .shifts = lan937x_shifts, 1530 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1531 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1532 .supports_mii = {false, false, false, false, true}, 1533 .supports_rmii = {false, false, false, false, true}, 1534 .supports_rgmii = {false, false, false, false, true}, 1535 .internal_phy = {true, true, true, true, false}, 1536 }, 1537 1538 [LAN9371] = { 1539 .chip_id = LAN9371_CHIP_ID, 1540 .dev_name = "LAN9371", 1541 .num_vlans = 4096, 1542 .num_alus = 1024, 1543 .num_statics = 256, 1544 .cpu_ports = 0x30, /* can be configured as cpu port */ 1545 .port_cnt = 6, /* total physical port count */ 1546 .port_nirqs = 6, 1547 .num_tx_queues = 8, 1548 .tc_cbs_supported = true, 1549 .tc_ets_supported = true, 1550 .ops = &lan937x_dev_ops, 1551 .mib_names = ksz9477_mib_names, 1552 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1553 .reg_mib_cnt = MIB_COUNTER_NUM, 1554 .regs = ksz9477_regs, 1555 .masks = lan937x_masks, 1556 .shifts = lan937x_shifts, 1557 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1558 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1559 .supports_mii = {false, false, false, false, true, true}, 1560 .supports_rmii = {false, false, false, false, true, true}, 1561 .supports_rgmii = {false, false, false, false, true, true}, 1562 .internal_phy = {true, true, true, true, false, false}, 1563 }, 1564 1565 [LAN9372] = { 1566 .chip_id = LAN9372_CHIP_ID, 1567 .dev_name = "LAN9372", 1568 .num_vlans = 4096, 1569 .num_alus = 1024, 1570 .num_statics = 256, 1571 .cpu_ports = 0x30, /* can be configured as cpu port */ 1572 .port_cnt = 8, /* total physical port count */ 1573 .port_nirqs = 6, 1574 .num_tx_queues = 8, 1575 .tc_cbs_supported = true, 1576 .tc_ets_supported = true, 1577 .ops = &lan937x_dev_ops, 1578 .mib_names = ksz9477_mib_names, 1579 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1580 .reg_mib_cnt = MIB_COUNTER_NUM, 1581 .regs = ksz9477_regs, 1582 .masks = lan937x_masks, 1583 .shifts = lan937x_shifts, 1584 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1585 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1586 .supports_mii = {false, false, false, false, 1587 true, true, false, false}, 1588 .supports_rmii = {false, false, false, false, 1589 true, true, false, false}, 1590 .supports_rgmii = {false, false, false, false, 1591 true, true, false, false}, 1592 .internal_phy = {true, true, true, true, 1593 false, false, true, true}, 1594 }, 1595 1596 [LAN9373] = { 1597 .chip_id = LAN9373_CHIP_ID, 1598 .dev_name = "LAN9373", 1599 .num_vlans = 4096, 1600 .num_alus = 1024, 1601 .num_statics = 256, 1602 .cpu_ports = 0x38, /* can be configured as cpu port */ 1603 .port_cnt = 5, /* total physical port count */ 1604 .port_nirqs = 6, 1605 .num_tx_queues = 8, 1606 .tc_cbs_supported = true, 1607 .tc_ets_supported = true, 1608 .ops = &lan937x_dev_ops, 1609 .mib_names = ksz9477_mib_names, 1610 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1611 .reg_mib_cnt = MIB_COUNTER_NUM, 1612 .regs = ksz9477_regs, 1613 .masks = lan937x_masks, 1614 .shifts = lan937x_shifts, 1615 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1616 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1617 .supports_mii = {false, false, false, false, 1618 true, true, false, false}, 1619 .supports_rmii = {false, false, false, false, 1620 true, true, false, false}, 1621 .supports_rgmii = {false, false, false, false, 1622 true, true, false, false}, 1623 .internal_phy = {true, true, true, false, 1624 false, false, true, true}, 1625 }, 1626 1627 [LAN9374] = { 1628 .chip_id = LAN9374_CHIP_ID, 1629 .dev_name = "LAN9374", 1630 .num_vlans = 4096, 1631 .num_alus = 1024, 1632 .num_statics = 256, 1633 .cpu_ports = 0x30, /* can be configured as cpu port */ 1634 .port_cnt = 8, /* total physical port count */ 1635 .port_nirqs = 6, 1636 .num_tx_queues = 8, 1637 .tc_cbs_supported = true, 1638 .tc_ets_supported = true, 1639 .ops = &lan937x_dev_ops, 1640 .mib_names = ksz9477_mib_names, 1641 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1642 .reg_mib_cnt = MIB_COUNTER_NUM, 1643 .regs = ksz9477_regs, 1644 .masks = lan937x_masks, 1645 .shifts = lan937x_shifts, 1646 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1647 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1648 .supports_mii = {false, false, false, false, 1649 true, true, false, false}, 1650 .supports_rmii = {false, false, false, false, 1651 true, true, false, false}, 1652 .supports_rgmii = {false, false, false, false, 1653 true, true, false, false}, 1654 .internal_phy = {true, true, true, true, 1655 false, false, true, true}, 1656 }, 1657 }; 1658 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1659 1660 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1661 { 1662 int i; 1663 1664 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1665 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1666 1667 if (chip->chip_id == prod_num) 1668 return chip; 1669 } 1670 1671 return NULL; 1672 } 1673 1674 static int ksz_check_device_id(struct ksz_device *dev) 1675 { 1676 const struct ksz_chip_data *expected_chip_data; 1677 u32 expected_chip_id; 1678 1679 if (dev->pdata) { 1680 expected_chip_id = dev->pdata->chip_id; 1681 expected_chip_data = ksz_lookup_info(expected_chip_id); 1682 if (WARN_ON(!expected_chip_data)) 1683 return -ENODEV; 1684 } else { 1685 expected_chip_data = of_device_get_match_data(dev->dev); 1686 expected_chip_id = expected_chip_data->chip_id; 1687 } 1688 1689 if (expected_chip_id != dev->chip_id) { 1690 dev_err(dev->dev, 1691 "Device tree specifies chip %s but found %s, please fix it!\n", 1692 expected_chip_data->dev_name, dev->info->dev_name); 1693 return -ENODEV; 1694 } 1695 1696 return 0; 1697 } 1698 1699 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1700 struct phylink_config *config) 1701 { 1702 struct ksz_device *dev = ds->priv; 1703 1704 if (dev->info->supports_mii[port]) 1705 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1706 1707 if (dev->info->supports_rmii[port]) 1708 __set_bit(PHY_INTERFACE_MODE_RMII, 1709 config->supported_interfaces); 1710 1711 if (dev->info->supports_rgmii[port]) 1712 phy_interface_set_rgmii(config->supported_interfaces); 1713 1714 if (dev->info->internal_phy[port]) { 1715 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1716 config->supported_interfaces); 1717 /* Compatibility for phylib's default interface type when the 1718 * phy-mode property is absent 1719 */ 1720 __set_bit(PHY_INTERFACE_MODE_GMII, 1721 config->supported_interfaces); 1722 } 1723 1724 if (dev->dev_ops->get_caps) 1725 dev->dev_ops->get_caps(dev, port, config); 1726 } 1727 1728 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 1729 { 1730 struct ethtool_pause_stats *pstats; 1731 struct rtnl_link_stats64 *stats; 1732 struct ksz_stats_raw *raw; 1733 struct ksz_port_mib *mib; 1734 1735 mib = &dev->ports[port].mib; 1736 stats = &mib->stats64; 1737 pstats = &mib->pause_stats; 1738 raw = (struct ksz_stats_raw *)mib->counters; 1739 1740 spin_lock(&mib->stats64_lock); 1741 1742 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1743 raw->rx_pause; 1744 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1745 raw->tx_pause; 1746 1747 /* HW counters are counting bytes + FCS which is not acceptable 1748 * for rtnl_link_stats64 interface 1749 */ 1750 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 1751 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 1752 1753 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1754 raw->rx_oversize; 1755 1756 stats->rx_crc_errors = raw->rx_crc_err; 1757 stats->rx_frame_errors = raw->rx_align_err; 1758 stats->rx_dropped = raw->rx_discards; 1759 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1760 stats->rx_frame_errors + stats->rx_dropped; 1761 1762 stats->tx_window_errors = raw->tx_late_col; 1763 stats->tx_fifo_errors = raw->tx_discards; 1764 stats->tx_aborted_errors = raw->tx_exc_col; 1765 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1766 stats->tx_aborted_errors; 1767 1768 stats->multicast = raw->rx_mcast; 1769 stats->collisions = raw->tx_total_col; 1770 1771 pstats->tx_pause_frames = raw->tx_pause; 1772 pstats->rx_pause_frames = raw->rx_pause; 1773 1774 spin_unlock(&mib->stats64_lock); 1775 } 1776 1777 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 1778 { 1779 struct ethtool_pause_stats *pstats; 1780 struct rtnl_link_stats64 *stats; 1781 struct ksz88xx_stats_raw *raw; 1782 struct ksz_port_mib *mib; 1783 1784 mib = &dev->ports[port].mib; 1785 stats = &mib->stats64; 1786 pstats = &mib->pause_stats; 1787 raw = (struct ksz88xx_stats_raw *)mib->counters; 1788 1789 spin_lock(&mib->stats64_lock); 1790 1791 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1792 raw->rx_pause; 1793 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1794 raw->tx_pause; 1795 1796 /* HW counters are counting bytes + FCS which is not acceptable 1797 * for rtnl_link_stats64 interface 1798 */ 1799 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 1800 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 1801 1802 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1803 raw->rx_oversize; 1804 1805 stats->rx_crc_errors = raw->rx_crc_err; 1806 stats->rx_frame_errors = raw->rx_align_err; 1807 stats->rx_dropped = raw->rx_discards; 1808 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1809 stats->rx_frame_errors + stats->rx_dropped; 1810 1811 stats->tx_window_errors = raw->tx_late_col; 1812 stats->tx_fifo_errors = raw->tx_discards; 1813 stats->tx_aborted_errors = raw->tx_exc_col; 1814 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1815 stats->tx_aborted_errors; 1816 1817 stats->multicast = raw->rx_mcast; 1818 stats->collisions = raw->tx_total_col; 1819 1820 pstats->tx_pause_frames = raw->tx_pause; 1821 pstats->rx_pause_frames = raw->rx_pause; 1822 1823 spin_unlock(&mib->stats64_lock); 1824 } 1825 1826 static void ksz_get_stats64(struct dsa_switch *ds, int port, 1827 struct rtnl_link_stats64 *s) 1828 { 1829 struct ksz_device *dev = ds->priv; 1830 struct ksz_port_mib *mib; 1831 1832 mib = &dev->ports[port].mib; 1833 1834 spin_lock(&mib->stats64_lock); 1835 memcpy(s, &mib->stats64, sizeof(*s)); 1836 spin_unlock(&mib->stats64_lock); 1837 } 1838 1839 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 1840 struct ethtool_pause_stats *pause_stats) 1841 { 1842 struct ksz_device *dev = ds->priv; 1843 struct ksz_port_mib *mib; 1844 1845 mib = &dev->ports[port].mib; 1846 1847 spin_lock(&mib->stats64_lock); 1848 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 1849 spin_unlock(&mib->stats64_lock); 1850 } 1851 1852 static void ksz_get_strings(struct dsa_switch *ds, int port, 1853 u32 stringset, uint8_t *buf) 1854 { 1855 struct ksz_device *dev = ds->priv; 1856 int i; 1857 1858 if (stringset != ETH_SS_STATS) 1859 return; 1860 1861 for (i = 0; i < dev->info->mib_cnt; i++) { 1862 memcpy(buf + i * ETH_GSTRING_LEN, 1863 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 1864 } 1865 } 1866 1867 static void ksz_update_port_member(struct ksz_device *dev, int port) 1868 { 1869 struct ksz_port *p = &dev->ports[port]; 1870 struct dsa_switch *ds = dev->ds; 1871 u8 port_member = 0, cpu_port; 1872 const struct dsa_port *dp; 1873 int i, j; 1874 1875 if (!dsa_is_user_port(ds, port)) 1876 return; 1877 1878 dp = dsa_to_port(ds, port); 1879 cpu_port = BIT(dsa_upstream_port(ds, port)); 1880 1881 for (i = 0; i < ds->num_ports; i++) { 1882 const struct dsa_port *other_dp = dsa_to_port(ds, i); 1883 struct ksz_port *other_p = &dev->ports[i]; 1884 u8 val = 0; 1885 1886 if (!dsa_is_user_port(ds, i)) 1887 continue; 1888 if (port == i) 1889 continue; 1890 if (!dsa_port_bridge_same(dp, other_dp)) 1891 continue; 1892 if (other_p->stp_state != BR_STATE_FORWARDING) 1893 continue; 1894 1895 if (p->stp_state == BR_STATE_FORWARDING) { 1896 val |= BIT(port); 1897 port_member |= BIT(i); 1898 } 1899 1900 /* Retain port [i]'s relationship to other ports than [port] */ 1901 for (j = 0; j < ds->num_ports; j++) { 1902 const struct dsa_port *third_dp; 1903 struct ksz_port *third_p; 1904 1905 if (j == i) 1906 continue; 1907 if (j == port) 1908 continue; 1909 if (!dsa_is_user_port(ds, j)) 1910 continue; 1911 third_p = &dev->ports[j]; 1912 if (third_p->stp_state != BR_STATE_FORWARDING) 1913 continue; 1914 third_dp = dsa_to_port(ds, j); 1915 if (dsa_port_bridge_same(other_dp, third_dp)) 1916 val |= BIT(j); 1917 } 1918 1919 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 1920 } 1921 1922 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 1923 } 1924 1925 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 1926 { 1927 struct ksz_device *dev = bus->priv; 1928 u16 val; 1929 int ret; 1930 1931 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 1932 if (ret < 0) 1933 return ret; 1934 1935 return val; 1936 } 1937 1938 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 1939 u16 val) 1940 { 1941 struct ksz_device *dev = bus->priv; 1942 1943 return dev->dev_ops->w_phy(dev, addr, regnum, val); 1944 } 1945 1946 static int ksz_irq_phy_setup(struct ksz_device *dev) 1947 { 1948 struct dsa_switch *ds = dev->ds; 1949 int phy; 1950 int irq; 1951 int ret; 1952 1953 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) { 1954 if (BIT(phy) & ds->phys_mii_mask) { 1955 irq = irq_find_mapping(dev->ports[phy].pirq.domain, 1956 PORT_SRC_PHY_INT); 1957 if (irq < 0) { 1958 ret = irq; 1959 goto out; 1960 } 1961 ds->user_mii_bus->irq[phy] = irq; 1962 } 1963 } 1964 return 0; 1965 out: 1966 while (phy--) 1967 if (BIT(phy) & ds->phys_mii_mask) 1968 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 1969 1970 return ret; 1971 } 1972 1973 static void ksz_irq_phy_free(struct ksz_device *dev) 1974 { 1975 struct dsa_switch *ds = dev->ds; 1976 int phy; 1977 1978 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) 1979 if (BIT(phy) & ds->phys_mii_mask) 1980 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 1981 } 1982 1983 static int ksz_mdio_register(struct ksz_device *dev) 1984 { 1985 struct dsa_switch *ds = dev->ds; 1986 struct device_node *mdio_np; 1987 struct mii_bus *bus; 1988 int ret; 1989 1990 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 1991 if (!mdio_np) 1992 return 0; 1993 1994 bus = devm_mdiobus_alloc(ds->dev); 1995 if (!bus) { 1996 of_node_put(mdio_np); 1997 return -ENOMEM; 1998 } 1999 2000 bus->priv = dev; 2001 bus->read = ksz_sw_mdio_read; 2002 bus->write = ksz_sw_mdio_write; 2003 bus->name = "ksz user smi"; 2004 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 2005 bus->parent = ds->dev; 2006 bus->phy_mask = ~ds->phys_mii_mask; 2007 2008 ds->user_mii_bus = bus; 2009 2010 if (dev->irq > 0) { 2011 ret = ksz_irq_phy_setup(dev); 2012 if (ret) { 2013 of_node_put(mdio_np); 2014 return ret; 2015 } 2016 } 2017 2018 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 2019 if (ret) { 2020 dev_err(ds->dev, "unable to register MDIO bus %s\n", 2021 bus->id); 2022 if (dev->irq > 0) 2023 ksz_irq_phy_free(dev); 2024 } 2025 2026 of_node_put(mdio_np); 2027 2028 return ret; 2029 } 2030 2031 static void ksz_irq_mask(struct irq_data *d) 2032 { 2033 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2034 2035 kirq->masked |= BIT(d->hwirq); 2036 } 2037 2038 static void ksz_irq_unmask(struct irq_data *d) 2039 { 2040 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2041 2042 kirq->masked &= ~BIT(d->hwirq); 2043 } 2044 2045 static void ksz_irq_bus_lock(struct irq_data *d) 2046 { 2047 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2048 2049 mutex_lock(&kirq->dev->lock_irq); 2050 } 2051 2052 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 2053 { 2054 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2055 struct ksz_device *dev = kirq->dev; 2056 int ret; 2057 2058 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked); 2059 if (ret) 2060 dev_err(dev->dev, "failed to change IRQ mask\n"); 2061 2062 mutex_unlock(&dev->lock_irq); 2063 } 2064 2065 static const struct irq_chip ksz_irq_chip = { 2066 .name = "ksz-irq", 2067 .irq_mask = ksz_irq_mask, 2068 .irq_unmask = ksz_irq_unmask, 2069 .irq_bus_lock = ksz_irq_bus_lock, 2070 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 2071 }; 2072 2073 static int ksz_irq_domain_map(struct irq_domain *d, 2074 unsigned int irq, irq_hw_number_t hwirq) 2075 { 2076 irq_set_chip_data(irq, d->host_data); 2077 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 2078 irq_set_noprobe(irq); 2079 2080 return 0; 2081 } 2082 2083 static const struct irq_domain_ops ksz_irq_domain_ops = { 2084 .map = ksz_irq_domain_map, 2085 .xlate = irq_domain_xlate_twocell, 2086 }; 2087 2088 static void ksz_irq_free(struct ksz_irq *kirq) 2089 { 2090 int irq, virq; 2091 2092 free_irq(kirq->irq_num, kirq); 2093 2094 for (irq = 0; irq < kirq->nirqs; irq++) { 2095 virq = irq_find_mapping(kirq->domain, irq); 2096 irq_dispose_mapping(virq); 2097 } 2098 2099 irq_domain_remove(kirq->domain); 2100 } 2101 2102 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 2103 { 2104 struct ksz_irq *kirq = dev_id; 2105 unsigned int nhandled = 0; 2106 struct ksz_device *dev; 2107 unsigned int sub_irq; 2108 u8 data; 2109 int ret; 2110 u8 n; 2111 2112 dev = kirq->dev; 2113 2114 /* Read interrupt status register */ 2115 ret = ksz_read8(dev, kirq->reg_status, &data); 2116 if (ret) 2117 goto out; 2118 2119 for (n = 0; n < kirq->nirqs; ++n) { 2120 if (data & BIT(n)) { 2121 sub_irq = irq_find_mapping(kirq->domain, n); 2122 handle_nested_irq(sub_irq); 2123 ++nhandled; 2124 } 2125 } 2126 out: 2127 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2128 } 2129 2130 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 2131 { 2132 int ret, n; 2133 2134 kirq->dev = dev; 2135 kirq->masked = ~0; 2136 2137 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0, 2138 &ksz_irq_domain_ops, kirq); 2139 if (!kirq->domain) 2140 return -ENOMEM; 2141 2142 for (n = 0; n < kirq->nirqs; n++) 2143 irq_create_mapping(kirq->domain, n); 2144 2145 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2146 IRQF_ONESHOT, kirq->name, kirq); 2147 if (ret) 2148 goto out; 2149 2150 return 0; 2151 2152 out: 2153 ksz_irq_free(kirq); 2154 2155 return ret; 2156 } 2157 2158 static int ksz_girq_setup(struct ksz_device *dev) 2159 { 2160 struct ksz_irq *girq = &dev->girq; 2161 2162 girq->nirqs = dev->info->port_cnt; 2163 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2164 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2165 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2166 2167 girq->irq_num = dev->irq; 2168 2169 return ksz_irq_common_setup(dev, girq); 2170 } 2171 2172 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2173 { 2174 struct ksz_irq *pirq = &dev->ports[p].pirq; 2175 2176 pirq->nirqs = dev->info->port_nirqs; 2177 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2178 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2179 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2180 2181 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2182 if (pirq->irq_num < 0) 2183 return pirq->irq_num; 2184 2185 return ksz_irq_common_setup(dev, pirq); 2186 } 2187 2188 static int ksz_setup(struct dsa_switch *ds) 2189 { 2190 struct ksz_device *dev = ds->priv; 2191 struct dsa_port *dp; 2192 struct ksz_port *p; 2193 const u16 *regs; 2194 int ret; 2195 2196 regs = dev->info->regs; 2197 2198 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2199 dev->info->num_vlans, GFP_KERNEL); 2200 if (!dev->vlan_cache) 2201 return -ENOMEM; 2202 2203 ret = dev->dev_ops->reset(dev); 2204 if (ret) { 2205 dev_err(ds->dev, "failed to reset switch\n"); 2206 return ret; 2207 } 2208 2209 /* set broadcast storm protection 10% rate */ 2210 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2211 BROADCAST_STORM_RATE, 2212 (BROADCAST_STORM_VALUE * 2213 BROADCAST_STORM_PROT_RATE) / 100); 2214 2215 dev->dev_ops->config_cpu_port(ds); 2216 2217 dev->dev_ops->enable_stp_addr(dev); 2218 2219 ds->num_tx_queues = dev->info->num_tx_queues; 2220 2221 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 2222 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2223 2224 ksz_init_mib_timer(dev); 2225 2226 ds->configure_vlan_while_not_filtering = false; 2227 2228 if (dev->dev_ops->setup) { 2229 ret = dev->dev_ops->setup(ds); 2230 if (ret) 2231 return ret; 2232 } 2233 2234 /* Start with learning disabled on standalone user ports, and enabled 2235 * on the CPU port. In lack of other finer mechanisms, learning on the 2236 * CPU port will avoid flooding bridge local addresses on the network 2237 * in some cases. 2238 */ 2239 p = &dev->ports[dev->cpu_port]; 2240 p->learning = true; 2241 2242 if (dev->irq > 0) { 2243 ret = ksz_girq_setup(dev); 2244 if (ret) 2245 return ret; 2246 2247 dsa_switch_for_each_user_port(dp, dev->ds) { 2248 ret = ksz_pirq_setup(dev, dp->index); 2249 if (ret) 2250 goto out_girq; 2251 2252 ret = ksz_ptp_irq_setup(ds, dp->index); 2253 if (ret) 2254 goto out_pirq; 2255 } 2256 } 2257 2258 ret = ksz_ptp_clock_register(ds); 2259 if (ret) { 2260 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret); 2261 goto out_ptpirq; 2262 } 2263 2264 ret = ksz_mdio_register(dev); 2265 if (ret < 0) { 2266 dev_err(dev->dev, "failed to register the mdio"); 2267 goto out_ptp_clock_unregister; 2268 } 2269 2270 /* start switch */ 2271 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 2272 SW_START, SW_START); 2273 2274 return 0; 2275 2276 out_ptp_clock_unregister: 2277 ksz_ptp_clock_unregister(ds); 2278 out_ptpirq: 2279 if (dev->irq > 0) 2280 dsa_switch_for_each_user_port(dp, dev->ds) 2281 ksz_ptp_irq_free(ds, dp->index); 2282 out_pirq: 2283 if (dev->irq > 0) 2284 dsa_switch_for_each_user_port(dp, dev->ds) 2285 ksz_irq_free(&dev->ports[dp->index].pirq); 2286 out_girq: 2287 if (dev->irq > 0) 2288 ksz_irq_free(&dev->girq); 2289 2290 return ret; 2291 } 2292 2293 static void ksz_teardown(struct dsa_switch *ds) 2294 { 2295 struct ksz_device *dev = ds->priv; 2296 struct dsa_port *dp; 2297 2298 ksz_ptp_clock_unregister(ds); 2299 2300 if (dev->irq > 0) { 2301 dsa_switch_for_each_user_port(dp, dev->ds) { 2302 ksz_ptp_irq_free(ds, dp->index); 2303 2304 ksz_irq_free(&dev->ports[dp->index].pirq); 2305 } 2306 2307 ksz_irq_free(&dev->girq); 2308 } 2309 2310 if (dev->dev_ops->teardown) 2311 dev->dev_ops->teardown(ds); 2312 } 2313 2314 static void port_r_cnt(struct ksz_device *dev, int port) 2315 { 2316 struct ksz_port_mib *mib = &dev->ports[port].mib; 2317 u64 *dropped; 2318 2319 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2320 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2321 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2322 &mib->counters[mib->cnt_ptr]); 2323 ++mib->cnt_ptr; 2324 } 2325 2326 /* last one in storage */ 2327 dropped = &mib->counters[dev->info->mib_cnt]; 2328 2329 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2330 while (mib->cnt_ptr < dev->info->mib_cnt) { 2331 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2332 dropped, &mib->counters[mib->cnt_ptr]); 2333 ++mib->cnt_ptr; 2334 } 2335 mib->cnt_ptr = 0; 2336 } 2337 2338 static void ksz_mib_read_work(struct work_struct *work) 2339 { 2340 struct ksz_device *dev = container_of(work, struct ksz_device, 2341 mib_read.work); 2342 struct ksz_port_mib *mib; 2343 struct ksz_port *p; 2344 int i; 2345 2346 for (i = 0; i < dev->info->port_cnt; i++) { 2347 if (dsa_is_unused_port(dev->ds, i)) 2348 continue; 2349 2350 p = &dev->ports[i]; 2351 mib = &p->mib; 2352 mutex_lock(&mib->cnt_mutex); 2353 2354 /* Only read MIB counters when the port is told to do. 2355 * If not, read only dropped counters when link is not up. 2356 */ 2357 if (!p->read) { 2358 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 2359 2360 if (!netif_carrier_ok(dp->user)) 2361 mib->cnt_ptr = dev->info->reg_mib_cnt; 2362 } 2363 port_r_cnt(dev, i); 2364 p->read = false; 2365 2366 if (dev->dev_ops->r_mib_stat64) 2367 dev->dev_ops->r_mib_stat64(dev, i); 2368 2369 mutex_unlock(&mib->cnt_mutex); 2370 } 2371 2372 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 2373 } 2374 2375 void ksz_init_mib_timer(struct ksz_device *dev) 2376 { 2377 int i; 2378 2379 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 2380 2381 for (i = 0; i < dev->info->port_cnt; i++) { 2382 struct ksz_port_mib *mib = &dev->ports[i].mib; 2383 2384 dev->dev_ops->port_init_cnt(dev, i); 2385 2386 mib->cnt_ptr = 0; 2387 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 2388 } 2389 } 2390 2391 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 2392 { 2393 struct ksz_device *dev = ds->priv; 2394 u16 val = 0xffff; 2395 int ret; 2396 2397 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 2398 if (ret) 2399 return ret; 2400 2401 return val; 2402 } 2403 2404 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 2405 { 2406 struct ksz_device *dev = ds->priv; 2407 int ret; 2408 2409 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 2410 if (ret) 2411 return ret; 2412 2413 return 0; 2414 } 2415 2416 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 2417 { 2418 struct ksz_device *dev = ds->priv; 2419 2420 switch (dev->chip_id) { 2421 case KSZ8830_CHIP_ID: 2422 /* Silicon Errata Sheet (DS80000830A): 2423 * Port 1 does not work with LinkMD Cable-Testing. 2424 * Port 1 does not respond to received PAUSE control frames. 2425 */ 2426 if (!port) 2427 return MICREL_KSZ8_P1_ERRATA; 2428 break; 2429 case KSZ9477_CHIP_ID: 2430 /* KSZ9477 Errata DS80000754C 2431 * 2432 * Module 4: Energy Efficient Ethernet (EEE) feature select must 2433 * be manually disabled 2434 * The EEE feature is enabled by default, but it is not fully 2435 * operational. It must be manually disabled through register 2436 * controls. If not disabled, the PHY ports can auto-negotiate 2437 * to enable EEE, and this feature can cause link drops when 2438 * linked to another device supporting EEE. 2439 */ 2440 return MICREL_NO_EEE; 2441 } 2442 2443 return 0; 2444 } 2445 2446 static void ksz_mac_link_down(struct dsa_switch *ds, int port, 2447 unsigned int mode, phy_interface_t interface) 2448 { 2449 struct ksz_device *dev = ds->priv; 2450 struct ksz_port *p = &dev->ports[port]; 2451 2452 /* Read all MIB counters when the link is going down. */ 2453 p->read = true; 2454 /* timer started */ 2455 if (dev->mib_read_interval) 2456 schedule_delayed_work(&dev->mib_read, 0); 2457 } 2458 2459 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 2460 { 2461 struct ksz_device *dev = ds->priv; 2462 2463 if (sset != ETH_SS_STATS) 2464 return 0; 2465 2466 return dev->info->mib_cnt; 2467 } 2468 2469 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 2470 uint64_t *buf) 2471 { 2472 const struct dsa_port *dp = dsa_to_port(ds, port); 2473 struct ksz_device *dev = ds->priv; 2474 struct ksz_port_mib *mib; 2475 2476 mib = &dev->ports[port].mib; 2477 mutex_lock(&mib->cnt_mutex); 2478 2479 /* Only read dropped counters if no link. */ 2480 if (!netif_carrier_ok(dp->user)) 2481 mib->cnt_ptr = dev->info->reg_mib_cnt; 2482 port_r_cnt(dev, port); 2483 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 2484 mutex_unlock(&mib->cnt_mutex); 2485 } 2486 2487 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 2488 struct dsa_bridge bridge, 2489 bool *tx_fwd_offload, 2490 struct netlink_ext_ack *extack) 2491 { 2492 /* port_stp_state_set() will be called after to put the port in 2493 * appropriate state so there is no need to do anything. 2494 */ 2495 2496 return 0; 2497 } 2498 2499 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 2500 struct dsa_bridge bridge) 2501 { 2502 /* port_stp_state_set() will be called after to put the port in 2503 * forwarding state so there is no need to do anything. 2504 */ 2505 } 2506 2507 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 2508 { 2509 struct ksz_device *dev = ds->priv; 2510 2511 dev->dev_ops->flush_dyn_mac_table(dev, port); 2512 } 2513 2514 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 2515 { 2516 struct ksz_device *dev = ds->priv; 2517 2518 if (!dev->dev_ops->set_ageing_time) 2519 return -EOPNOTSUPP; 2520 2521 return dev->dev_ops->set_ageing_time(dev, msecs); 2522 } 2523 2524 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 2525 const unsigned char *addr, u16 vid, 2526 struct dsa_db db) 2527 { 2528 struct ksz_device *dev = ds->priv; 2529 2530 if (!dev->dev_ops->fdb_add) 2531 return -EOPNOTSUPP; 2532 2533 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 2534 } 2535 2536 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 2537 const unsigned char *addr, 2538 u16 vid, struct dsa_db db) 2539 { 2540 struct ksz_device *dev = ds->priv; 2541 2542 if (!dev->dev_ops->fdb_del) 2543 return -EOPNOTSUPP; 2544 2545 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 2546 } 2547 2548 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 2549 dsa_fdb_dump_cb_t *cb, void *data) 2550 { 2551 struct ksz_device *dev = ds->priv; 2552 2553 if (!dev->dev_ops->fdb_dump) 2554 return -EOPNOTSUPP; 2555 2556 return dev->dev_ops->fdb_dump(dev, port, cb, data); 2557 } 2558 2559 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 2560 const struct switchdev_obj_port_mdb *mdb, 2561 struct dsa_db db) 2562 { 2563 struct ksz_device *dev = ds->priv; 2564 2565 if (!dev->dev_ops->mdb_add) 2566 return -EOPNOTSUPP; 2567 2568 return dev->dev_ops->mdb_add(dev, port, mdb, db); 2569 } 2570 2571 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 2572 const struct switchdev_obj_port_mdb *mdb, 2573 struct dsa_db db) 2574 { 2575 struct ksz_device *dev = ds->priv; 2576 2577 if (!dev->dev_ops->mdb_del) 2578 return -EOPNOTSUPP; 2579 2580 return dev->dev_ops->mdb_del(dev, port, mdb, db); 2581 } 2582 2583 static int ksz_port_setup(struct dsa_switch *ds, int port) 2584 { 2585 struct ksz_device *dev = ds->priv; 2586 2587 if (!dsa_is_user_port(ds, port)) 2588 return 0; 2589 2590 /* setup user port */ 2591 dev->dev_ops->port_setup(dev, port, false); 2592 2593 /* port_stp_state_set() will be called after to enable the port so 2594 * there is no need to do anything. 2595 */ 2596 2597 return 0; 2598 } 2599 2600 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 2601 { 2602 struct ksz_device *dev = ds->priv; 2603 struct ksz_port *p; 2604 const u16 *regs; 2605 u8 data; 2606 2607 regs = dev->info->regs; 2608 2609 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 2610 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2611 2612 p = &dev->ports[port]; 2613 2614 switch (state) { 2615 case BR_STATE_DISABLED: 2616 data |= PORT_LEARN_DISABLE; 2617 break; 2618 case BR_STATE_LISTENING: 2619 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2620 break; 2621 case BR_STATE_LEARNING: 2622 data |= PORT_RX_ENABLE; 2623 if (!p->learning) 2624 data |= PORT_LEARN_DISABLE; 2625 break; 2626 case BR_STATE_FORWARDING: 2627 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 2628 if (!p->learning) 2629 data |= PORT_LEARN_DISABLE; 2630 break; 2631 case BR_STATE_BLOCKING: 2632 data |= PORT_LEARN_DISABLE; 2633 break; 2634 default: 2635 dev_err(ds->dev, "invalid STP state: %d\n", state); 2636 return; 2637 } 2638 2639 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 2640 2641 p->stp_state = state; 2642 2643 ksz_update_port_member(dev, port); 2644 } 2645 2646 static void ksz_port_teardown(struct dsa_switch *ds, int port) 2647 { 2648 struct ksz_device *dev = ds->priv; 2649 2650 switch (dev->chip_id) { 2651 case KSZ8563_CHIP_ID: 2652 case KSZ9477_CHIP_ID: 2653 case KSZ9563_CHIP_ID: 2654 case KSZ9567_CHIP_ID: 2655 case KSZ9893_CHIP_ID: 2656 case KSZ9896_CHIP_ID: 2657 case KSZ9897_CHIP_ID: 2658 if (dsa_is_user_port(ds, port)) 2659 ksz9477_port_acl_free(dev, port); 2660 } 2661 } 2662 2663 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 2664 struct switchdev_brport_flags flags, 2665 struct netlink_ext_ack *extack) 2666 { 2667 if (flags.mask & ~BR_LEARNING) 2668 return -EINVAL; 2669 2670 return 0; 2671 } 2672 2673 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 2674 struct switchdev_brport_flags flags, 2675 struct netlink_ext_ack *extack) 2676 { 2677 struct ksz_device *dev = ds->priv; 2678 struct ksz_port *p = &dev->ports[port]; 2679 2680 if (flags.mask & BR_LEARNING) { 2681 p->learning = !!(flags.val & BR_LEARNING); 2682 2683 /* Make the change take effect immediately */ 2684 ksz_port_stp_state_set(ds, port, p->stp_state); 2685 } 2686 2687 return 0; 2688 } 2689 2690 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 2691 int port, 2692 enum dsa_tag_protocol mp) 2693 { 2694 struct ksz_device *dev = ds->priv; 2695 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 2696 2697 if (dev->chip_id == KSZ8795_CHIP_ID || 2698 dev->chip_id == KSZ8794_CHIP_ID || 2699 dev->chip_id == KSZ8765_CHIP_ID) 2700 proto = DSA_TAG_PROTO_KSZ8795; 2701 2702 if (dev->chip_id == KSZ8830_CHIP_ID || 2703 dev->chip_id == KSZ8563_CHIP_ID || 2704 dev->chip_id == KSZ9893_CHIP_ID || 2705 dev->chip_id == KSZ9563_CHIP_ID) 2706 proto = DSA_TAG_PROTO_KSZ9893; 2707 2708 if (dev->chip_id == KSZ9477_CHIP_ID || 2709 dev->chip_id == KSZ9896_CHIP_ID || 2710 dev->chip_id == KSZ9897_CHIP_ID || 2711 dev->chip_id == KSZ9567_CHIP_ID) 2712 proto = DSA_TAG_PROTO_KSZ9477; 2713 2714 if (is_lan937x(dev)) 2715 proto = DSA_TAG_PROTO_LAN937X; 2716 2717 return proto; 2718 } 2719 2720 static int ksz_connect_tag_protocol(struct dsa_switch *ds, 2721 enum dsa_tag_protocol proto) 2722 { 2723 struct ksz_tagger_data *tagger_data; 2724 2725 switch (proto) { 2726 case DSA_TAG_PROTO_KSZ8795: 2727 return 0; 2728 case DSA_TAG_PROTO_KSZ9893: 2729 case DSA_TAG_PROTO_KSZ9477: 2730 case DSA_TAG_PROTO_LAN937X: 2731 tagger_data = ksz_tagger_data(ds); 2732 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 2733 return 0; 2734 default: 2735 return -EPROTONOSUPPORT; 2736 } 2737 } 2738 2739 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 2740 bool flag, struct netlink_ext_ack *extack) 2741 { 2742 struct ksz_device *dev = ds->priv; 2743 2744 if (!dev->dev_ops->vlan_filtering) 2745 return -EOPNOTSUPP; 2746 2747 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 2748 } 2749 2750 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 2751 const struct switchdev_obj_port_vlan *vlan, 2752 struct netlink_ext_ack *extack) 2753 { 2754 struct ksz_device *dev = ds->priv; 2755 2756 if (!dev->dev_ops->vlan_add) 2757 return -EOPNOTSUPP; 2758 2759 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 2760 } 2761 2762 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 2763 const struct switchdev_obj_port_vlan *vlan) 2764 { 2765 struct ksz_device *dev = ds->priv; 2766 2767 if (!dev->dev_ops->vlan_del) 2768 return -EOPNOTSUPP; 2769 2770 return dev->dev_ops->vlan_del(dev, port, vlan); 2771 } 2772 2773 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 2774 struct dsa_mall_mirror_tc_entry *mirror, 2775 bool ingress, struct netlink_ext_ack *extack) 2776 { 2777 struct ksz_device *dev = ds->priv; 2778 2779 if (!dev->dev_ops->mirror_add) 2780 return -EOPNOTSUPP; 2781 2782 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 2783 } 2784 2785 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 2786 struct dsa_mall_mirror_tc_entry *mirror) 2787 { 2788 struct ksz_device *dev = ds->priv; 2789 2790 if (dev->dev_ops->mirror_del) 2791 dev->dev_ops->mirror_del(dev, port, mirror); 2792 } 2793 2794 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 2795 { 2796 struct ksz_device *dev = ds->priv; 2797 2798 if (!dev->dev_ops->change_mtu) 2799 return -EOPNOTSUPP; 2800 2801 return dev->dev_ops->change_mtu(dev, port, mtu); 2802 } 2803 2804 static int ksz_max_mtu(struct dsa_switch *ds, int port) 2805 { 2806 struct ksz_device *dev = ds->priv; 2807 2808 switch (dev->chip_id) { 2809 case KSZ8795_CHIP_ID: 2810 case KSZ8794_CHIP_ID: 2811 case KSZ8765_CHIP_ID: 2812 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2813 case KSZ8830_CHIP_ID: 2814 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2815 case KSZ8563_CHIP_ID: 2816 case KSZ9477_CHIP_ID: 2817 case KSZ9563_CHIP_ID: 2818 case KSZ9567_CHIP_ID: 2819 case KSZ9893_CHIP_ID: 2820 case KSZ9896_CHIP_ID: 2821 case KSZ9897_CHIP_ID: 2822 case LAN9370_CHIP_ID: 2823 case LAN9371_CHIP_ID: 2824 case LAN9372_CHIP_ID: 2825 case LAN9373_CHIP_ID: 2826 case LAN9374_CHIP_ID: 2827 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2828 } 2829 2830 return -EOPNOTSUPP; 2831 } 2832 2833 static int ksz_validate_eee(struct dsa_switch *ds, int port) 2834 { 2835 struct ksz_device *dev = ds->priv; 2836 2837 if (!dev->info->internal_phy[port]) 2838 return -EOPNOTSUPP; 2839 2840 switch (dev->chip_id) { 2841 case KSZ8563_CHIP_ID: 2842 case KSZ9477_CHIP_ID: 2843 case KSZ9563_CHIP_ID: 2844 case KSZ9567_CHIP_ID: 2845 case KSZ9893_CHIP_ID: 2846 case KSZ9896_CHIP_ID: 2847 case KSZ9897_CHIP_ID: 2848 return 0; 2849 } 2850 2851 return -EOPNOTSUPP; 2852 } 2853 2854 static int ksz_get_mac_eee(struct dsa_switch *ds, int port, 2855 struct ethtool_eee *e) 2856 { 2857 int ret; 2858 2859 ret = ksz_validate_eee(ds, port); 2860 if (ret) 2861 return ret; 2862 2863 /* There is no documented control of Tx LPI configuration. */ 2864 e->tx_lpi_enabled = true; 2865 2866 /* There is no documented control of Tx LPI timer. According to tests 2867 * Tx LPI timer seems to be set by default to minimal value. 2868 */ 2869 e->tx_lpi_timer = 0; 2870 2871 return 0; 2872 } 2873 2874 static int ksz_set_mac_eee(struct dsa_switch *ds, int port, 2875 struct ethtool_eee *e) 2876 { 2877 struct ksz_device *dev = ds->priv; 2878 int ret; 2879 2880 ret = ksz_validate_eee(ds, port); 2881 if (ret) 2882 return ret; 2883 2884 if (!e->tx_lpi_enabled) { 2885 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 2886 return -EINVAL; 2887 } 2888 2889 if (e->tx_lpi_timer) { 2890 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 2891 return -EINVAL; 2892 } 2893 2894 return 0; 2895 } 2896 2897 static void ksz_set_xmii(struct ksz_device *dev, int port, 2898 phy_interface_t interface) 2899 { 2900 const u8 *bitval = dev->info->xmii_ctrl1; 2901 struct ksz_port *p = &dev->ports[port]; 2902 const u16 *regs = dev->info->regs; 2903 u8 data8; 2904 2905 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2906 2907 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 2908 P_RGMII_ID_EG_ENABLE); 2909 2910 switch (interface) { 2911 case PHY_INTERFACE_MODE_MII: 2912 data8 |= bitval[P_MII_SEL]; 2913 break; 2914 case PHY_INTERFACE_MODE_RMII: 2915 data8 |= bitval[P_RMII_SEL]; 2916 break; 2917 case PHY_INTERFACE_MODE_GMII: 2918 data8 |= bitval[P_GMII_SEL]; 2919 break; 2920 case PHY_INTERFACE_MODE_RGMII: 2921 case PHY_INTERFACE_MODE_RGMII_ID: 2922 case PHY_INTERFACE_MODE_RGMII_TXID: 2923 case PHY_INTERFACE_MODE_RGMII_RXID: 2924 data8 |= bitval[P_RGMII_SEL]; 2925 /* On KSZ9893, disable RGMII in-band status support */ 2926 if (dev->chip_id == KSZ9893_CHIP_ID || 2927 dev->chip_id == KSZ8563_CHIP_ID || 2928 dev->chip_id == KSZ9563_CHIP_ID) 2929 data8 &= ~P_MII_MAC_MODE; 2930 break; 2931 default: 2932 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 2933 phy_modes(interface), port); 2934 return; 2935 } 2936 2937 if (p->rgmii_tx_val) 2938 data8 |= P_RGMII_ID_EG_ENABLE; 2939 2940 if (p->rgmii_rx_val) 2941 data8 |= P_RGMII_ID_IG_ENABLE; 2942 2943 /* Write the updated value */ 2944 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2945 } 2946 2947 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 2948 { 2949 const u8 *bitval = dev->info->xmii_ctrl1; 2950 const u16 *regs = dev->info->regs; 2951 phy_interface_t interface; 2952 u8 data8; 2953 u8 val; 2954 2955 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2956 2957 val = FIELD_GET(P_MII_SEL_M, data8); 2958 2959 if (val == bitval[P_MII_SEL]) { 2960 if (gbit) 2961 interface = PHY_INTERFACE_MODE_GMII; 2962 else 2963 interface = PHY_INTERFACE_MODE_MII; 2964 } else if (val == bitval[P_RMII_SEL]) { 2965 interface = PHY_INTERFACE_MODE_RGMII; 2966 } else { 2967 interface = PHY_INTERFACE_MODE_RGMII; 2968 if (data8 & P_RGMII_ID_EG_ENABLE) 2969 interface = PHY_INTERFACE_MODE_RGMII_TXID; 2970 if (data8 & P_RGMII_ID_IG_ENABLE) { 2971 interface = PHY_INTERFACE_MODE_RGMII_RXID; 2972 if (data8 & P_RGMII_ID_EG_ENABLE) 2973 interface = PHY_INTERFACE_MODE_RGMII_ID; 2974 } 2975 } 2976 2977 return interface; 2978 } 2979 2980 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, 2981 unsigned int mode, 2982 const struct phylink_link_state *state) 2983 { 2984 struct ksz_device *dev = ds->priv; 2985 2986 if (ksz_is_ksz88x3(dev)) { 2987 dev->ports[port].manual_flow = !(state->pause & MLO_PAUSE_AN); 2988 return; 2989 } 2990 2991 /* Internal PHYs */ 2992 if (dev->info->internal_phy[port]) 2993 return; 2994 2995 if (phylink_autoneg_inband(mode)) { 2996 dev_err(dev->dev, "In-band AN not supported!\n"); 2997 return; 2998 } 2999 3000 ksz_set_xmii(dev, port, state->interface); 3001 3002 if (dev->dev_ops->phylink_mac_config) 3003 dev->dev_ops->phylink_mac_config(dev, port, mode, state); 3004 3005 if (dev->dev_ops->setup_rgmii_delay) 3006 dev->dev_ops->setup_rgmii_delay(dev, port); 3007 } 3008 3009 bool ksz_get_gbit(struct ksz_device *dev, int port) 3010 { 3011 const u8 *bitval = dev->info->xmii_ctrl1; 3012 const u16 *regs = dev->info->regs; 3013 bool gbit = false; 3014 u8 data8; 3015 bool val; 3016 3017 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3018 3019 val = FIELD_GET(P_GMII_1GBIT_M, data8); 3020 3021 if (val == bitval[P_GMII_1GBIT]) 3022 gbit = true; 3023 3024 return gbit; 3025 } 3026 3027 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 3028 { 3029 const u8 *bitval = dev->info->xmii_ctrl1; 3030 const u16 *regs = dev->info->regs; 3031 u8 data8; 3032 3033 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3034 3035 data8 &= ~P_GMII_1GBIT_M; 3036 3037 if (gbit) 3038 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 3039 else 3040 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 3041 3042 /* Write the updated value */ 3043 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3044 } 3045 3046 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 3047 { 3048 const u8 *bitval = dev->info->xmii_ctrl0; 3049 const u16 *regs = dev->info->regs; 3050 u8 data8; 3051 3052 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 3053 3054 data8 &= ~P_MII_100MBIT_M; 3055 3056 if (speed == SPEED_100) 3057 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 3058 else 3059 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 3060 3061 /* Write the updated value */ 3062 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 3063 } 3064 3065 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 3066 { 3067 if (speed == SPEED_1000) 3068 ksz_set_gbit(dev, port, true); 3069 else 3070 ksz_set_gbit(dev, port, false); 3071 3072 if (speed == SPEED_100 || speed == SPEED_10) 3073 ksz_set_100_10mbit(dev, port, speed); 3074 } 3075 3076 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 3077 bool tx_pause, bool rx_pause) 3078 { 3079 const u8 *bitval = dev->info->xmii_ctrl0; 3080 const u32 *masks = dev->info->masks; 3081 const u16 *regs = dev->info->regs; 3082 u8 mask; 3083 u8 val; 3084 3085 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 3086 masks[P_MII_RX_FLOW_CTRL]; 3087 3088 if (duplex == DUPLEX_FULL) 3089 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 3090 else 3091 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 3092 3093 if (tx_pause) 3094 val |= masks[P_MII_TX_FLOW_CTRL]; 3095 3096 if (rx_pause) 3097 val |= masks[P_MII_RX_FLOW_CTRL]; 3098 3099 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 3100 } 3101 3102 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 3103 unsigned int mode, 3104 phy_interface_t interface, 3105 struct phy_device *phydev, int speed, 3106 int duplex, bool tx_pause, 3107 bool rx_pause) 3108 { 3109 struct ksz_port *p; 3110 3111 p = &dev->ports[port]; 3112 3113 /* Internal PHYs */ 3114 if (dev->info->internal_phy[port]) 3115 return; 3116 3117 p->phydev.speed = speed; 3118 3119 ksz_port_set_xmii_speed(dev, port, speed); 3120 3121 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 3122 } 3123 3124 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, 3125 unsigned int mode, 3126 phy_interface_t interface, 3127 struct phy_device *phydev, int speed, 3128 int duplex, bool tx_pause, bool rx_pause) 3129 { 3130 struct ksz_device *dev = ds->priv; 3131 3132 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface, phydev, 3133 speed, duplex, tx_pause, rx_pause); 3134 } 3135 3136 static int ksz_switch_detect(struct ksz_device *dev) 3137 { 3138 u8 id1, id2, id4; 3139 u16 id16; 3140 u32 id32; 3141 int ret; 3142 3143 /* read chip id */ 3144 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 3145 if (ret) 3146 return ret; 3147 3148 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 3149 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 3150 3151 switch (id1) { 3152 case KSZ87_FAMILY_ID: 3153 if (id2 == KSZ87_CHIP_ID_95) { 3154 u8 val; 3155 3156 dev->chip_id = KSZ8795_CHIP_ID; 3157 3158 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 3159 if (val & KSZ8_PORT_FIBER_MODE) 3160 dev->chip_id = KSZ8765_CHIP_ID; 3161 } else if (id2 == KSZ87_CHIP_ID_94) { 3162 dev->chip_id = KSZ8794_CHIP_ID; 3163 } else { 3164 return -ENODEV; 3165 } 3166 break; 3167 case KSZ88_FAMILY_ID: 3168 if (id2 == KSZ88_CHIP_ID_63) 3169 dev->chip_id = KSZ8830_CHIP_ID; 3170 else 3171 return -ENODEV; 3172 break; 3173 default: 3174 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 3175 if (ret) 3176 return ret; 3177 3178 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 3179 id32 &= ~0xFF; 3180 3181 switch (id32) { 3182 case KSZ9477_CHIP_ID: 3183 case KSZ9896_CHIP_ID: 3184 case KSZ9897_CHIP_ID: 3185 case KSZ9567_CHIP_ID: 3186 case LAN9370_CHIP_ID: 3187 case LAN9371_CHIP_ID: 3188 case LAN9372_CHIP_ID: 3189 case LAN9373_CHIP_ID: 3190 case LAN9374_CHIP_ID: 3191 dev->chip_id = id32; 3192 break; 3193 case KSZ9893_CHIP_ID: 3194 ret = ksz_read8(dev, REG_CHIP_ID4, 3195 &id4); 3196 if (ret) 3197 return ret; 3198 3199 if (id4 == SKU_ID_KSZ8563) 3200 dev->chip_id = KSZ8563_CHIP_ID; 3201 else if (id4 == SKU_ID_KSZ9563) 3202 dev->chip_id = KSZ9563_CHIP_ID; 3203 else 3204 dev->chip_id = KSZ9893_CHIP_ID; 3205 3206 break; 3207 default: 3208 dev_err(dev->dev, 3209 "unsupported switch detected %x)\n", id32); 3210 return -ENODEV; 3211 } 3212 } 3213 return 0; 3214 } 3215 3216 static int ksz_cls_flower_add(struct dsa_switch *ds, int port, 3217 struct flow_cls_offload *cls, bool ingress) 3218 { 3219 struct ksz_device *dev = ds->priv; 3220 3221 switch (dev->chip_id) { 3222 case KSZ8563_CHIP_ID: 3223 case KSZ9477_CHIP_ID: 3224 case KSZ9563_CHIP_ID: 3225 case KSZ9567_CHIP_ID: 3226 case KSZ9893_CHIP_ID: 3227 case KSZ9896_CHIP_ID: 3228 case KSZ9897_CHIP_ID: 3229 return ksz9477_cls_flower_add(ds, port, cls, ingress); 3230 } 3231 3232 return -EOPNOTSUPP; 3233 } 3234 3235 static int ksz_cls_flower_del(struct dsa_switch *ds, int port, 3236 struct flow_cls_offload *cls, bool ingress) 3237 { 3238 struct ksz_device *dev = ds->priv; 3239 3240 switch (dev->chip_id) { 3241 case KSZ8563_CHIP_ID: 3242 case KSZ9477_CHIP_ID: 3243 case KSZ9563_CHIP_ID: 3244 case KSZ9567_CHIP_ID: 3245 case KSZ9893_CHIP_ID: 3246 case KSZ9896_CHIP_ID: 3247 case KSZ9897_CHIP_ID: 3248 return ksz9477_cls_flower_del(ds, port, cls, ingress); 3249 } 3250 3251 return -EOPNOTSUPP; 3252 } 3253 3254 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 3255 * is converted to Hex-decimal using the successive multiplication method. On 3256 * every step, integer part is taken and decimal part is carry forwarded. 3257 */ 3258 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 3259 { 3260 u32 cinc = 0; 3261 u32 txrate; 3262 u32 rate; 3263 u8 temp; 3264 u8 i; 3265 3266 txrate = idle_slope - send_slope; 3267 3268 if (!txrate) 3269 return -EINVAL; 3270 3271 rate = idle_slope; 3272 3273 /* 24 bit register */ 3274 for (i = 0; i < 6; i++) { 3275 rate = rate * 16; 3276 3277 temp = rate / txrate; 3278 3279 rate %= txrate; 3280 3281 cinc = ((cinc << 4) | temp); 3282 } 3283 3284 *bw = cinc; 3285 3286 return 0; 3287 } 3288 3289 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 3290 u8 shaper) 3291 { 3292 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 3293 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 3294 FIELD_PREP(MTI_SHAPING_M, shaper)); 3295 } 3296 3297 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 3298 struct tc_cbs_qopt_offload *qopt) 3299 { 3300 struct ksz_device *dev = ds->priv; 3301 int ret; 3302 u32 bw; 3303 3304 if (!dev->info->tc_cbs_supported) 3305 return -EOPNOTSUPP; 3306 3307 if (qopt->queue > dev->info->num_tx_queues) 3308 return -EINVAL; 3309 3310 /* Queue Selection */ 3311 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 3312 if (ret) 3313 return ret; 3314 3315 if (!qopt->enable) 3316 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3317 MTI_SHAPING_OFF); 3318 3319 /* High Credit */ 3320 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 3321 qopt->hicredit); 3322 if (ret) 3323 return ret; 3324 3325 /* Low Credit */ 3326 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 3327 qopt->locredit); 3328 if (ret) 3329 return ret; 3330 3331 /* Credit Increment Register */ 3332 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 3333 if (ret) 3334 return ret; 3335 3336 if (dev->dev_ops->tc_cbs_set_cinc) { 3337 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 3338 if (ret) 3339 return ret; 3340 } 3341 3342 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3343 MTI_SHAPING_SRP); 3344 } 3345 3346 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 3347 { 3348 int queue, ret; 3349 3350 /* Configuration will not take effect until the last Port Queue X 3351 * Egress Limit Control Register is written. 3352 */ 3353 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3354 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 3355 KSZ9477_OUT_RATE_NO_LIMIT); 3356 if (ret) 3357 return ret; 3358 } 3359 3360 return 0; 3361 } 3362 3363 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 3364 int band) 3365 { 3366 /* Compared to queues, bands prioritize packets differently. In strict 3367 * priority mode, the lowest priority is assigned to Queue 0 while the 3368 * highest priority is given to Band 0. 3369 */ 3370 return p->bands - 1 - band; 3371 } 3372 3373 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 3374 { 3375 int ret; 3376 3377 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3378 if (ret) 3379 return ret; 3380 3381 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3382 MTI_SHAPING_OFF); 3383 } 3384 3385 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 3386 int weight) 3387 { 3388 int ret; 3389 3390 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3391 if (ret) 3392 return ret; 3393 3394 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3395 MTI_SHAPING_OFF); 3396 if (ret) 3397 return ret; 3398 3399 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 3400 } 3401 3402 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 3403 struct tc_ets_qopt_offload_replace_params *p) 3404 { 3405 int ret, band, tc_prio; 3406 u32 queue_map = 0; 3407 3408 /* In order to ensure proper prioritization, it is necessary to set the 3409 * rate limit for the related queue to zero. Otherwise strict priority 3410 * or WRR mode will not work. This is a hardware limitation. 3411 */ 3412 ret = ksz_disable_egress_rate_limit(dev, port); 3413 if (ret) 3414 return ret; 3415 3416 /* Configure queue scheduling mode for all bands. Currently only strict 3417 * prio mode is supported. 3418 */ 3419 for (band = 0; band < p->bands; band++) { 3420 int queue = ksz_ets_band_to_queue(p, band); 3421 3422 ret = ksz_queue_set_strict(dev, port, queue); 3423 if (ret) 3424 return ret; 3425 } 3426 3427 /* Configure the mapping between traffic classes and queues. Note: 3428 * priomap variable support 16 traffic classes, but the chip can handle 3429 * only 8 classes. 3430 */ 3431 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 3432 int queue; 3433 3434 if (tc_prio > KSZ9477_MAX_TC_PRIO) 3435 break; 3436 3437 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 3438 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3439 } 3440 3441 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3442 } 3443 3444 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 3445 { 3446 int ret, queue, tc_prio, s; 3447 u32 queue_map = 0; 3448 3449 /* To restore the default chip configuration, set all queues to use the 3450 * WRR scheduler with a weight of 1. 3451 */ 3452 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3453 ret = ksz_queue_set_wrr(dev, port, queue, 3454 KSZ9477_DEFAULT_WRR_WEIGHT); 3455 if (ret) 3456 return ret; 3457 } 3458 3459 switch (dev->info->num_tx_queues) { 3460 case 2: 3461 s = 2; 3462 break; 3463 case 4: 3464 s = 1; 3465 break; 3466 case 8: 3467 s = 0; 3468 break; 3469 default: 3470 return -EINVAL; 3471 } 3472 3473 /* Revert the queue mapping for TC-priority to its default setting on 3474 * the chip. 3475 */ 3476 for (tc_prio = 0; tc_prio <= KSZ9477_MAX_TC_PRIO; tc_prio++) { 3477 int queue; 3478 3479 queue = tc_prio >> s; 3480 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3481 } 3482 3483 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3484 } 3485 3486 static int ksz_tc_ets_validate(struct ksz_device *dev, int port, 3487 struct tc_ets_qopt_offload_replace_params *p) 3488 { 3489 int band; 3490 3491 /* Since it is not feasible to share one port among multiple qdisc, 3492 * the user must configure all available queues appropriately. 3493 */ 3494 if (p->bands != dev->info->num_tx_queues) { 3495 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 3496 dev->info->num_tx_queues); 3497 return -EOPNOTSUPP; 3498 } 3499 3500 for (band = 0; band < p->bands; ++band) { 3501 /* The KSZ switches utilize a weighted round robin configuration 3502 * where a certain number of packets can be transmitted from a 3503 * queue before the next queue is serviced. For more information 3504 * on this, refer to section 5.2.8.4 of the KSZ8565R 3505 * documentation on the Port Transmit Queue Control 1 Register. 3506 * However, the current ETS Qdisc implementation (as of February 3507 * 2023) assigns a weight to each queue based on the number of 3508 * bytes or extrapolated bandwidth in percentages. Since this 3509 * differs from the KSZ switches' method and we don't want to 3510 * fake support by converting bytes to packets, it is better to 3511 * return an error instead. 3512 */ 3513 if (p->quanta[band]) { 3514 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 3515 return -EOPNOTSUPP; 3516 } 3517 } 3518 3519 return 0; 3520 } 3521 3522 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 3523 struct tc_ets_qopt_offload *qopt) 3524 { 3525 struct ksz_device *dev = ds->priv; 3526 int ret; 3527 3528 if (!dev->info->tc_ets_supported) 3529 return -EOPNOTSUPP; 3530 3531 if (qopt->parent != TC_H_ROOT) { 3532 dev_err(dev->dev, "Parent should be \"root\"\n"); 3533 return -EOPNOTSUPP; 3534 } 3535 3536 switch (qopt->command) { 3537 case TC_ETS_REPLACE: 3538 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 3539 if (ret) 3540 return ret; 3541 3542 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 3543 case TC_ETS_DESTROY: 3544 return ksz_tc_ets_del(dev, port); 3545 case TC_ETS_STATS: 3546 case TC_ETS_GRAFT: 3547 return -EOPNOTSUPP; 3548 } 3549 3550 return -EOPNOTSUPP; 3551 } 3552 3553 static int ksz_setup_tc(struct dsa_switch *ds, int port, 3554 enum tc_setup_type type, void *type_data) 3555 { 3556 switch (type) { 3557 case TC_SETUP_QDISC_CBS: 3558 return ksz_setup_tc_cbs(ds, port, type_data); 3559 case TC_SETUP_QDISC_ETS: 3560 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 3561 default: 3562 return -EOPNOTSUPP; 3563 } 3564 } 3565 3566 static void ksz_get_wol(struct dsa_switch *ds, int port, 3567 struct ethtool_wolinfo *wol) 3568 { 3569 struct ksz_device *dev = ds->priv; 3570 3571 if (dev->dev_ops->get_wol) 3572 dev->dev_ops->get_wol(dev, port, wol); 3573 } 3574 3575 static int ksz_set_wol(struct dsa_switch *ds, int port, 3576 struct ethtool_wolinfo *wol) 3577 { 3578 struct ksz_device *dev = ds->priv; 3579 3580 if (dev->dev_ops->set_wol) 3581 return dev->dev_ops->set_wol(dev, port, wol); 3582 3583 return -EOPNOTSUPP; 3584 } 3585 3586 static int ksz_port_set_mac_address(struct dsa_switch *ds, int port, 3587 const unsigned char *addr) 3588 { 3589 struct dsa_port *dp = dsa_to_port(ds, port); 3590 struct ethtool_wolinfo wol; 3591 3592 if (dp->hsr_dev) { 3593 dev_err(ds->dev, 3594 "Cannot change MAC address on port %d with active HSR offload\n", 3595 port); 3596 return -EBUSY; 3597 } 3598 3599 ksz_get_wol(ds, dp->index, &wol); 3600 if (wol.wolopts & WAKE_MAGIC) { 3601 dev_err(ds->dev, 3602 "Cannot change MAC address on port %d with active Wake on Magic Packet\n", 3603 port); 3604 return -EBUSY; 3605 } 3606 3607 return 0; 3608 } 3609 3610 /** 3611 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port 3612 * can be used as a global address. 3613 * @ds: Pointer to the DSA switch structure. 3614 * @port: The port number on which the MAC address is to be checked. 3615 * 3616 * This function examines the MAC address set on the specified port and 3617 * determines if it can be used as a global address for the switch. 3618 * 3619 * Return: true if the port's MAC address can be used as a global address, false 3620 * otherwise. 3621 */ 3622 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port) 3623 { 3624 struct net_device *user = dsa_to_port(ds, port)->user; 3625 const unsigned char *addr = user->dev_addr; 3626 struct ksz_switch_macaddr *switch_macaddr; 3627 struct ksz_device *dev = ds->priv; 3628 3629 ASSERT_RTNL(); 3630 3631 switch_macaddr = dev->switch_macaddr; 3632 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr)) 3633 return false; 3634 3635 return true; 3636 } 3637 3638 /** 3639 * ksz_switch_macaddr_get - Program the switch's MAC address register. 3640 * @ds: DSA switch instance. 3641 * @port: Port number. 3642 * @extack: Netlink extended acknowledgment. 3643 * 3644 * This function programs the switch's MAC address register with the MAC address 3645 * of the requesting user port. This single address is used by the switch for 3646 * multiple features like HSR self-address filtering and WoL. Other user ports 3647 * can share ownership of this address as long as their MAC address is the same. 3648 * The MAC addresses of user ports must not change while they have ownership of 3649 * the switch MAC address. 3650 * 3651 * Return: 0 on success, or other error codes on failure. 3652 */ 3653 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 3654 struct netlink_ext_ack *extack) 3655 { 3656 struct net_device *user = dsa_to_port(ds, port)->user; 3657 const unsigned char *addr = user->dev_addr; 3658 struct ksz_switch_macaddr *switch_macaddr; 3659 struct ksz_device *dev = ds->priv; 3660 const u16 *regs = dev->info->regs; 3661 int i, ret; 3662 3663 /* Make sure concurrent MAC address changes are blocked */ 3664 ASSERT_RTNL(); 3665 3666 switch_macaddr = dev->switch_macaddr; 3667 if (switch_macaddr) { 3668 if (!ether_addr_equal(switch_macaddr->addr, addr)) { 3669 NL_SET_ERR_MSG_FMT_MOD(extack, 3670 "Switch already configured for MAC address %pM", 3671 switch_macaddr->addr); 3672 return -EBUSY; 3673 } 3674 3675 refcount_inc(&switch_macaddr->refcount); 3676 return 0; 3677 } 3678 3679 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL); 3680 if (!switch_macaddr) 3681 return -ENOMEM; 3682 3683 ether_addr_copy(switch_macaddr->addr, addr); 3684 refcount_set(&switch_macaddr->refcount, 1); 3685 dev->switch_macaddr = switch_macaddr; 3686 3687 /* Program the switch MAC address to hardware */ 3688 for (i = 0; i < ETH_ALEN; i++) { 3689 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, addr[i]); 3690 if (ret) 3691 goto macaddr_drop; 3692 } 3693 3694 return 0; 3695 3696 macaddr_drop: 3697 dev->switch_macaddr = NULL; 3698 refcount_set(&switch_macaddr->refcount, 0); 3699 kfree(switch_macaddr); 3700 3701 return ret; 3702 } 3703 3704 void ksz_switch_macaddr_put(struct dsa_switch *ds) 3705 { 3706 struct ksz_switch_macaddr *switch_macaddr; 3707 struct ksz_device *dev = ds->priv; 3708 const u16 *regs = dev->info->regs; 3709 int i; 3710 3711 /* Make sure concurrent MAC address changes are blocked */ 3712 ASSERT_RTNL(); 3713 3714 switch_macaddr = dev->switch_macaddr; 3715 if (!refcount_dec_and_test(&switch_macaddr->refcount)) 3716 return; 3717 3718 for (i = 0; i < ETH_ALEN; i++) 3719 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0); 3720 3721 dev->switch_macaddr = NULL; 3722 kfree(switch_macaddr); 3723 } 3724 3725 static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr, 3726 struct netlink_ext_ack *extack) 3727 { 3728 struct ksz_device *dev = ds->priv; 3729 enum hsr_version ver; 3730 int ret; 3731 3732 ret = hsr_get_version(hsr, &ver); 3733 if (ret) 3734 return ret; 3735 3736 if (dev->chip_id != KSZ9477_CHIP_ID) { 3737 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload"); 3738 return -EOPNOTSUPP; 3739 } 3740 3741 /* KSZ9477 can support HW offloading of only 1 HSR device */ 3742 if (dev->hsr_dev && hsr != dev->hsr_dev) { 3743 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR"); 3744 return -EOPNOTSUPP; 3745 } 3746 3747 /* KSZ9477 only supports HSR v0 and v1 */ 3748 if (!(ver == HSR_V0 || ver == HSR_V1)) { 3749 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported"); 3750 return -EOPNOTSUPP; 3751 } 3752 3753 /* Self MAC address filtering, to avoid frames traversing 3754 * the HSR ring more than once. 3755 */ 3756 ret = ksz_switch_macaddr_get(ds, port, extack); 3757 if (ret) 3758 return ret; 3759 3760 ksz9477_hsr_join(ds, port, hsr); 3761 dev->hsr_dev = hsr; 3762 dev->hsr_ports |= BIT(port); 3763 3764 return 0; 3765 } 3766 3767 static int ksz_hsr_leave(struct dsa_switch *ds, int port, 3768 struct net_device *hsr) 3769 { 3770 struct ksz_device *dev = ds->priv; 3771 3772 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID); 3773 3774 ksz9477_hsr_leave(ds, port, hsr); 3775 dev->hsr_ports &= ~BIT(port); 3776 if (!dev->hsr_ports) 3777 dev->hsr_dev = NULL; 3778 3779 ksz_switch_macaddr_put(ds); 3780 3781 return 0; 3782 } 3783 3784 static const struct dsa_switch_ops ksz_switch_ops = { 3785 .get_tag_protocol = ksz_get_tag_protocol, 3786 .connect_tag_protocol = ksz_connect_tag_protocol, 3787 .get_phy_flags = ksz_get_phy_flags, 3788 .setup = ksz_setup, 3789 .teardown = ksz_teardown, 3790 .phy_read = ksz_phy_read16, 3791 .phy_write = ksz_phy_write16, 3792 .phylink_get_caps = ksz_phylink_get_caps, 3793 .phylink_mac_config = ksz_phylink_mac_config, 3794 .phylink_mac_link_up = ksz_phylink_mac_link_up, 3795 .phylink_mac_link_down = ksz_mac_link_down, 3796 .port_setup = ksz_port_setup, 3797 .set_ageing_time = ksz_set_ageing_time, 3798 .get_strings = ksz_get_strings, 3799 .get_ethtool_stats = ksz_get_ethtool_stats, 3800 .get_sset_count = ksz_sset_count, 3801 .port_bridge_join = ksz_port_bridge_join, 3802 .port_bridge_leave = ksz_port_bridge_leave, 3803 .port_hsr_join = ksz_hsr_join, 3804 .port_hsr_leave = ksz_hsr_leave, 3805 .port_set_mac_address = ksz_port_set_mac_address, 3806 .port_stp_state_set = ksz_port_stp_state_set, 3807 .port_teardown = ksz_port_teardown, 3808 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 3809 .port_bridge_flags = ksz_port_bridge_flags, 3810 .port_fast_age = ksz_port_fast_age, 3811 .port_vlan_filtering = ksz_port_vlan_filtering, 3812 .port_vlan_add = ksz_port_vlan_add, 3813 .port_vlan_del = ksz_port_vlan_del, 3814 .port_fdb_dump = ksz_port_fdb_dump, 3815 .port_fdb_add = ksz_port_fdb_add, 3816 .port_fdb_del = ksz_port_fdb_del, 3817 .port_mdb_add = ksz_port_mdb_add, 3818 .port_mdb_del = ksz_port_mdb_del, 3819 .port_mirror_add = ksz_port_mirror_add, 3820 .port_mirror_del = ksz_port_mirror_del, 3821 .get_stats64 = ksz_get_stats64, 3822 .get_pause_stats = ksz_get_pause_stats, 3823 .port_change_mtu = ksz_change_mtu, 3824 .port_max_mtu = ksz_max_mtu, 3825 .get_wol = ksz_get_wol, 3826 .set_wol = ksz_set_wol, 3827 .get_ts_info = ksz_get_ts_info, 3828 .port_hwtstamp_get = ksz_hwtstamp_get, 3829 .port_hwtstamp_set = ksz_hwtstamp_set, 3830 .port_txtstamp = ksz_port_txtstamp, 3831 .port_rxtstamp = ksz_port_rxtstamp, 3832 .cls_flower_add = ksz_cls_flower_add, 3833 .cls_flower_del = ksz_cls_flower_del, 3834 .port_setup_tc = ksz_setup_tc, 3835 .get_mac_eee = ksz_get_mac_eee, 3836 .set_mac_eee = ksz_set_mac_eee, 3837 }; 3838 3839 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 3840 { 3841 struct dsa_switch *ds; 3842 struct ksz_device *swdev; 3843 3844 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 3845 if (!ds) 3846 return NULL; 3847 3848 ds->dev = base; 3849 ds->num_ports = DSA_MAX_PORTS; 3850 ds->ops = &ksz_switch_ops; 3851 3852 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 3853 if (!swdev) 3854 return NULL; 3855 3856 ds->priv = swdev; 3857 swdev->dev = base; 3858 3859 swdev->ds = ds; 3860 swdev->priv = priv; 3861 3862 return swdev; 3863 } 3864 EXPORT_SYMBOL(ksz_switch_alloc); 3865 3866 /** 3867 * ksz_switch_shutdown - Shutdown routine for the switch device. 3868 * @dev: The switch device structure. 3869 * 3870 * This function is responsible for initiating a shutdown sequence for the 3871 * switch device. It invokes the reset operation defined in the device 3872 * operations, if available, to reset the switch. Subsequently, it calls the 3873 * DSA framework's shutdown function to ensure a proper shutdown of the DSA 3874 * switch. 3875 */ 3876 void ksz_switch_shutdown(struct ksz_device *dev) 3877 { 3878 bool wol_enabled = false; 3879 3880 if (dev->dev_ops->wol_pre_shutdown) 3881 dev->dev_ops->wol_pre_shutdown(dev, &wol_enabled); 3882 3883 if (dev->dev_ops->reset && !wol_enabled) 3884 dev->dev_ops->reset(dev); 3885 3886 dsa_switch_shutdown(dev->ds); 3887 } 3888 EXPORT_SYMBOL(ksz_switch_shutdown); 3889 3890 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 3891 struct device_node *port_dn) 3892 { 3893 phy_interface_t phy_mode = dev->ports[port_num].interface; 3894 int rx_delay = -1, tx_delay = -1; 3895 3896 if (!phy_interface_mode_is_rgmii(phy_mode)) 3897 return; 3898 3899 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 3900 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 3901 3902 if (rx_delay == -1 && tx_delay == -1) { 3903 dev_warn(dev->dev, 3904 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 3905 "please update device tree to specify \"rx-internal-delay-ps\" and " 3906 "\"tx-internal-delay-ps\"", 3907 port_num); 3908 3909 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 3910 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 3911 rx_delay = 2000; 3912 3913 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 3914 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 3915 tx_delay = 2000; 3916 } 3917 3918 if (rx_delay < 0) 3919 rx_delay = 0; 3920 if (tx_delay < 0) 3921 tx_delay = 0; 3922 3923 dev->ports[port_num].rgmii_rx_val = rx_delay; 3924 dev->ports[port_num].rgmii_tx_val = tx_delay; 3925 } 3926 3927 /** 3928 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding 3929 * register value. 3930 * @array: The array of drive strength values to search. 3931 * @array_size: The size of the array. 3932 * @microamp: The drive strength value in microamp to be converted. 3933 * 3934 * This function searches the array of drive strength values for the given 3935 * microamp value and returns the corresponding register value for that drive. 3936 * 3937 * Returns: If found, the corresponding register value for that drive strength 3938 * is returned. Otherwise, -EINVAL is returned indicating an invalid value. 3939 */ 3940 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array, 3941 size_t array_size, int microamp) 3942 { 3943 int i; 3944 3945 for (i = 0; i < array_size; i++) { 3946 if (array[i].microamp == microamp) 3947 return array[i].reg_val; 3948 } 3949 3950 return -EINVAL; 3951 } 3952 3953 /** 3954 * ksz_drive_strength_error() - Report invalid drive strength value 3955 * @dev: ksz device 3956 * @array: The array of drive strength values to search. 3957 * @array_size: The size of the array. 3958 * @microamp: Invalid drive strength value in microamp 3959 * 3960 * This function logs an error message when an unsupported drive strength value 3961 * is detected. It lists out all the supported drive strength values for 3962 * reference in the error message. 3963 */ 3964 static void ksz_drive_strength_error(struct ksz_device *dev, 3965 const struct ksz_drive_strength *array, 3966 size_t array_size, int microamp) 3967 { 3968 char supported_values[100]; 3969 size_t remaining_size; 3970 int added_len; 3971 char *ptr; 3972 int i; 3973 3974 remaining_size = sizeof(supported_values); 3975 ptr = supported_values; 3976 3977 for (i = 0; i < array_size; i++) { 3978 added_len = snprintf(ptr, remaining_size, 3979 i == 0 ? "%d" : ", %d", array[i].microamp); 3980 3981 if (added_len >= remaining_size) 3982 break; 3983 3984 ptr += added_len; 3985 remaining_size -= added_len; 3986 } 3987 3988 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n", 3989 microamp, supported_values); 3990 } 3991 3992 /** 3993 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477 3994 * chip variants. 3995 * @dev: ksz device 3996 * @props: Array of drive strength properties to be applied 3997 * @num_props: Number of properties in the array 3998 * 3999 * This function configures the drive strength for various KSZ9477 chip variants 4000 * based on the provided properties. It handles chip-specific nuances and 4001 * ensures only valid drive strengths are written to the respective chip. 4002 * 4003 * Return: 0 on successful configuration, a negative error code on failure. 4004 */ 4005 static int ksz9477_drive_strength_write(struct ksz_device *dev, 4006 struct ksz_driver_strength_prop *props, 4007 int num_props) 4008 { 4009 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths); 4010 int i, ret, reg; 4011 u8 mask = 0; 4012 u8 val = 0; 4013 4014 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1) 4015 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4016 props[KSZ_DRIVER_STRENGTH_IO].name); 4017 4018 if (dev->chip_id == KSZ8795_CHIP_ID || 4019 dev->chip_id == KSZ8794_CHIP_ID || 4020 dev->chip_id == KSZ8765_CHIP_ID) 4021 reg = KSZ8795_REG_SW_CTRL_20; 4022 else 4023 reg = KSZ9477_REG_SW_IO_STRENGTH; 4024 4025 for (i = 0; i < num_props; i++) { 4026 if (props[i].value == -1) 4027 continue; 4028 4029 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths, 4030 array_size, props[i].value); 4031 if (ret < 0) { 4032 ksz_drive_strength_error(dev, ksz9477_drive_strengths, 4033 array_size, props[i].value); 4034 return ret; 4035 } 4036 4037 mask |= SW_DRIVE_STRENGTH_M << props[i].offset; 4038 val |= ret << props[i].offset; 4039 } 4040 4041 return ksz_rmw8(dev, reg, mask, val); 4042 } 4043 4044 /** 4045 * ksz8830_drive_strength_write() - Set the drive strength configuration for 4046 * KSZ8830 compatible chip variants. 4047 * @dev: ksz device 4048 * @props: Array of drive strength properties to be set 4049 * @num_props: Number of properties in the array 4050 * 4051 * This function applies the specified drive strength settings to KSZ8830 chip 4052 * variants (KSZ8873, KSZ8863). 4053 * It ensures the configurations align with what the chip variant supports and 4054 * warns or errors out on unsupported settings. 4055 * 4056 * Return: 0 on success, error code otherwise 4057 */ 4058 static int ksz8830_drive_strength_write(struct ksz_device *dev, 4059 struct ksz_driver_strength_prop *props, 4060 int num_props) 4061 { 4062 size_t array_size = ARRAY_SIZE(ksz8830_drive_strengths); 4063 int microamp; 4064 int i, ret; 4065 4066 for (i = 0; i < num_props; i++) { 4067 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO) 4068 continue; 4069 4070 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4071 props[i].name); 4072 } 4073 4074 microamp = props[KSZ_DRIVER_STRENGTH_IO].value; 4075 ret = ksz_drive_strength_to_reg(ksz8830_drive_strengths, array_size, 4076 microamp); 4077 if (ret < 0) { 4078 ksz_drive_strength_error(dev, ksz8830_drive_strengths, 4079 array_size, microamp); 4080 return ret; 4081 } 4082 4083 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12, 4084 KSZ8873_DRIVE_STRENGTH_16MA, ret); 4085 } 4086 4087 /** 4088 * ksz_parse_drive_strength() - Extract and apply drive strength configurations 4089 * from device tree properties. 4090 * @dev: ksz device 4091 * 4092 * This function reads the specified drive strength properties from the 4093 * device tree, validates against the supported chip variants, and sets 4094 * them accordingly. An error should be critical here, as the drive strength 4095 * settings are crucial for EMI compliance. 4096 * 4097 * Return: 0 on success, error code otherwise 4098 */ 4099 static int ksz_parse_drive_strength(struct ksz_device *dev) 4100 { 4101 struct ksz_driver_strength_prop of_props[] = { 4102 [KSZ_DRIVER_STRENGTH_HI] = { 4103 .name = "microchip,hi-drive-strength-microamp", 4104 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S, 4105 .value = -1, 4106 }, 4107 [KSZ_DRIVER_STRENGTH_LO] = { 4108 .name = "microchip,lo-drive-strength-microamp", 4109 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S, 4110 .value = -1, 4111 }, 4112 [KSZ_DRIVER_STRENGTH_IO] = { 4113 .name = "microchip,io-drive-strength-microamp", 4114 .offset = 0, /* don't care */ 4115 .value = -1, 4116 }, 4117 }; 4118 struct device_node *np = dev->dev->of_node; 4119 bool have_any_prop = false; 4120 int i, ret; 4121 4122 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4123 ret = of_property_read_u32(np, of_props[i].name, 4124 &of_props[i].value); 4125 if (ret && ret != -EINVAL) 4126 dev_warn(dev->dev, "Failed to read %s\n", 4127 of_props[i].name); 4128 if (ret) 4129 continue; 4130 4131 have_any_prop = true; 4132 } 4133 4134 if (!have_any_prop) 4135 return 0; 4136 4137 switch (dev->chip_id) { 4138 case KSZ8830_CHIP_ID: 4139 return ksz8830_drive_strength_write(dev, of_props, 4140 ARRAY_SIZE(of_props)); 4141 case KSZ8795_CHIP_ID: 4142 case KSZ8794_CHIP_ID: 4143 case KSZ8765_CHIP_ID: 4144 case KSZ8563_CHIP_ID: 4145 case KSZ9477_CHIP_ID: 4146 case KSZ9563_CHIP_ID: 4147 case KSZ9567_CHIP_ID: 4148 case KSZ9893_CHIP_ID: 4149 case KSZ9896_CHIP_ID: 4150 case KSZ9897_CHIP_ID: 4151 return ksz9477_drive_strength_write(dev, of_props, 4152 ARRAY_SIZE(of_props)); 4153 default: 4154 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4155 if (of_props[i].value == -1) 4156 continue; 4157 4158 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4159 of_props[i].name); 4160 } 4161 } 4162 4163 return 0; 4164 } 4165 4166 int ksz_switch_register(struct ksz_device *dev) 4167 { 4168 const struct ksz_chip_data *info; 4169 struct device_node *port, *ports; 4170 phy_interface_t interface; 4171 unsigned int port_num; 4172 int ret; 4173 int i; 4174 4175 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 4176 GPIOD_OUT_LOW); 4177 if (IS_ERR(dev->reset_gpio)) 4178 return PTR_ERR(dev->reset_gpio); 4179 4180 if (dev->reset_gpio) { 4181 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4182 usleep_range(10000, 12000); 4183 gpiod_set_value_cansleep(dev->reset_gpio, 0); 4184 msleep(100); 4185 } 4186 4187 mutex_init(&dev->dev_mutex); 4188 mutex_init(&dev->regmap_mutex); 4189 mutex_init(&dev->alu_mutex); 4190 mutex_init(&dev->vlan_mutex); 4191 4192 ret = ksz_switch_detect(dev); 4193 if (ret) 4194 return ret; 4195 4196 info = ksz_lookup_info(dev->chip_id); 4197 if (!info) 4198 return -ENODEV; 4199 4200 /* Update the compatible info with the probed one */ 4201 dev->info = info; 4202 4203 dev_info(dev->dev, "found switch: %s, rev %i\n", 4204 dev->info->dev_name, dev->chip_rev); 4205 4206 ret = ksz_check_device_id(dev); 4207 if (ret) 4208 return ret; 4209 4210 dev->dev_ops = dev->info->ops; 4211 4212 ret = dev->dev_ops->init(dev); 4213 if (ret) 4214 return ret; 4215 4216 dev->ports = devm_kzalloc(dev->dev, 4217 dev->info->port_cnt * sizeof(struct ksz_port), 4218 GFP_KERNEL); 4219 if (!dev->ports) 4220 return -ENOMEM; 4221 4222 for (i = 0; i < dev->info->port_cnt; i++) { 4223 spin_lock_init(&dev->ports[i].mib.stats64_lock); 4224 mutex_init(&dev->ports[i].mib.cnt_mutex); 4225 dev->ports[i].mib.counters = 4226 devm_kzalloc(dev->dev, 4227 sizeof(u64) * (dev->info->mib_cnt + 1), 4228 GFP_KERNEL); 4229 if (!dev->ports[i].mib.counters) 4230 return -ENOMEM; 4231 4232 dev->ports[i].ksz_dev = dev; 4233 dev->ports[i].num = i; 4234 } 4235 4236 /* set the real number of ports */ 4237 dev->ds->num_ports = dev->info->port_cnt; 4238 4239 /* Host port interface will be self detected, or specifically set in 4240 * device tree. 4241 */ 4242 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 4243 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 4244 if (dev->dev->of_node) { 4245 ret = ksz_parse_drive_strength(dev); 4246 if (ret) 4247 return ret; 4248 4249 ret = of_get_phy_mode(dev->dev->of_node, &interface); 4250 if (ret == 0) 4251 dev->compat_interface = interface; 4252 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 4253 if (!ports) 4254 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 4255 if (ports) { 4256 for_each_available_child_of_node(ports, port) { 4257 if (of_property_read_u32(port, "reg", 4258 &port_num)) 4259 continue; 4260 if (!(dev->port_mask & BIT(port_num))) { 4261 of_node_put(port); 4262 of_node_put(ports); 4263 return -EINVAL; 4264 } 4265 of_get_phy_mode(port, 4266 &dev->ports[port_num].interface); 4267 4268 ksz_parse_rgmii_delay(dev, port_num, port); 4269 } 4270 of_node_put(ports); 4271 } 4272 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 4273 "microchip,synclko-125"); 4274 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 4275 "microchip,synclko-disable"); 4276 if (dev->synclko_125 && dev->synclko_disable) { 4277 dev_err(dev->dev, "inconsistent synclko settings\n"); 4278 return -EINVAL; 4279 } 4280 4281 dev->wakeup_source = of_property_read_bool(dev->dev->of_node, 4282 "wakeup-source"); 4283 } 4284 4285 ret = dsa_register_switch(dev->ds); 4286 if (ret) { 4287 dev->dev_ops->exit(dev); 4288 return ret; 4289 } 4290 4291 /* Read MIB counters every 30 seconds to avoid overflow. */ 4292 dev->mib_read_interval = msecs_to_jiffies(5000); 4293 4294 /* Start the MIB timer. */ 4295 schedule_delayed_work(&dev->mib_read, 0); 4296 4297 return ret; 4298 } 4299 EXPORT_SYMBOL(ksz_switch_register); 4300 4301 void ksz_switch_remove(struct ksz_device *dev) 4302 { 4303 /* timer started */ 4304 if (dev->mib_read_interval) { 4305 dev->mib_read_interval = 0; 4306 cancel_delayed_work_sync(&dev->mib_read); 4307 } 4308 4309 dev->dev_ops->exit(dev); 4310 dsa_unregister_switch(dev->ds); 4311 4312 if (dev->reset_gpio) 4313 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4314 4315 } 4316 EXPORT_SYMBOL(ksz_switch_remove); 4317 4318 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 4319 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 4320 MODULE_LICENSE("GPL"); 4321