1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2024 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/if_hsr.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/of.h> 23 #include <linux/of_mdio.h> 24 #include <linux/of_net.h> 25 #include <linux/micrel_phy.h> 26 #include <net/dsa.h> 27 #include <net/ieee8021q.h> 28 #include <net/pkt_cls.h> 29 #include <net/switchdev.h> 30 31 #include "ksz_common.h" 32 #include "ksz_dcb.h" 33 #include "ksz_ptp.h" 34 #include "ksz8.h" 35 #include "ksz9477.h" 36 #include "lan937x.h" 37 38 #define MIB_COUNTER_NUM 0x20 39 40 struct ksz_stats_raw { 41 u64 rx_hi; 42 u64 rx_undersize; 43 u64 rx_fragments; 44 u64 rx_oversize; 45 u64 rx_jabbers; 46 u64 rx_symbol_err; 47 u64 rx_crc_err; 48 u64 rx_align_err; 49 u64 rx_mac_ctrl; 50 u64 rx_pause; 51 u64 rx_bcast; 52 u64 rx_mcast; 53 u64 rx_ucast; 54 u64 rx_64_or_less; 55 u64 rx_65_127; 56 u64 rx_128_255; 57 u64 rx_256_511; 58 u64 rx_512_1023; 59 u64 rx_1024_1522; 60 u64 rx_1523_2000; 61 u64 rx_2001; 62 u64 tx_hi; 63 u64 tx_late_col; 64 u64 tx_pause; 65 u64 tx_bcast; 66 u64 tx_mcast; 67 u64 tx_ucast; 68 u64 tx_deferred; 69 u64 tx_total_col; 70 u64 tx_exc_col; 71 u64 tx_single_col; 72 u64 tx_mult_col; 73 u64 rx_total; 74 u64 tx_total; 75 u64 rx_discards; 76 u64 tx_discards; 77 }; 78 79 struct ksz88xx_stats_raw { 80 u64 rx; 81 u64 rx_hi; 82 u64 rx_undersize; 83 u64 rx_fragments; 84 u64 rx_oversize; 85 u64 rx_jabbers; 86 u64 rx_symbol_err; 87 u64 rx_crc_err; 88 u64 rx_align_err; 89 u64 rx_mac_ctrl; 90 u64 rx_pause; 91 u64 rx_bcast; 92 u64 rx_mcast; 93 u64 rx_ucast; 94 u64 rx_64_or_less; 95 u64 rx_65_127; 96 u64 rx_128_255; 97 u64 rx_256_511; 98 u64 rx_512_1023; 99 u64 rx_1024_1522; 100 u64 tx; 101 u64 tx_hi; 102 u64 tx_late_col; 103 u64 tx_pause; 104 u64 tx_bcast; 105 u64 tx_mcast; 106 u64 tx_ucast; 107 u64 tx_deferred; 108 u64 tx_total_col; 109 u64 tx_exc_col; 110 u64 tx_single_col; 111 u64 tx_mult_col; 112 u64 rx_discards; 113 u64 tx_discards; 114 }; 115 116 static const struct ksz_mib_names ksz88xx_mib_names[] = { 117 { 0x00, "rx" }, 118 { 0x01, "rx_hi" }, 119 { 0x02, "rx_undersize" }, 120 { 0x03, "rx_fragments" }, 121 { 0x04, "rx_oversize" }, 122 { 0x05, "rx_jabbers" }, 123 { 0x06, "rx_symbol_err" }, 124 { 0x07, "rx_crc_err" }, 125 { 0x08, "rx_align_err" }, 126 { 0x09, "rx_mac_ctrl" }, 127 { 0x0a, "rx_pause" }, 128 { 0x0b, "rx_bcast" }, 129 { 0x0c, "rx_mcast" }, 130 { 0x0d, "rx_ucast" }, 131 { 0x0e, "rx_64_or_less" }, 132 { 0x0f, "rx_65_127" }, 133 { 0x10, "rx_128_255" }, 134 { 0x11, "rx_256_511" }, 135 { 0x12, "rx_512_1023" }, 136 { 0x13, "rx_1024_1522" }, 137 { 0x14, "tx" }, 138 { 0x15, "tx_hi" }, 139 { 0x16, "tx_late_col" }, 140 { 0x17, "tx_pause" }, 141 { 0x18, "tx_bcast" }, 142 { 0x19, "tx_mcast" }, 143 { 0x1a, "tx_ucast" }, 144 { 0x1b, "tx_deferred" }, 145 { 0x1c, "tx_total_col" }, 146 { 0x1d, "tx_exc_col" }, 147 { 0x1e, "tx_single_col" }, 148 { 0x1f, "tx_mult_col" }, 149 { 0x100, "rx_discards" }, 150 { 0x101, "tx_discards" }, 151 }; 152 153 static const struct ksz_mib_names ksz9477_mib_names[] = { 154 { 0x00, "rx_hi" }, 155 { 0x01, "rx_undersize" }, 156 { 0x02, "rx_fragments" }, 157 { 0x03, "rx_oversize" }, 158 { 0x04, "rx_jabbers" }, 159 { 0x05, "rx_symbol_err" }, 160 { 0x06, "rx_crc_err" }, 161 { 0x07, "rx_align_err" }, 162 { 0x08, "rx_mac_ctrl" }, 163 { 0x09, "rx_pause" }, 164 { 0x0A, "rx_bcast" }, 165 { 0x0B, "rx_mcast" }, 166 { 0x0C, "rx_ucast" }, 167 { 0x0D, "rx_64_or_less" }, 168 { 0x0E, "rx_65_127" }, 169 { 0x0F, "rx_128_255" }, 170 { 0x10, "rx_256_511" }, 171 { 0x11, "rx_512_1023" }, 172 { 0x12, "rx_1024_1522" }, 173 { 0x13, "rx_1523_2000" }, 174 { 0x14, "rx_2001" }, 175 { 0x15, "tx_hi" }, 176 { 0x16, "tx_late_col" }, 177 { 0x17, "tx_pause" }, 178 { 0x18, "tx_bcast" }, 179 { 0x19, "tx_mcast" }, 180 { 0x1A, "tx_ucast" }, 181 { 0x1B, "tx_deferred" }, 182 { 0x1C, "tx_total_col" }, 183 { 0x1D, "tx_exc_col" }, 184 { 0x1E, "tx_single_col" }, 185 { 0x1F, "tx_mult_col" }, 186 { 0x80, "rx_total" }, 187 { 0x81, "tx_total" }, 188 { 0x82, "rx_discards" }, 189 { 0x83, "tx_discards" }, 190 }; 191 192 struct ksz_driver_strength_prop { 193 const char *name; 194 int offset; 195 int value; 196 }; 197 198 enum ksz_driver_strength_type { 199 KSZ_DRIVER_STRENGTH_HI, 200 KSZ_DRIVER_STRENGTH_LO, 201 KSZ_DRIVER_STRENGTH_IO, 202 }; 203 204 /** 205 * struct ksz_drive_strength - drive strength mapping 206 * @reg_val: register value 207 * @microamp: microamp value 208 */ 209 struct ksz_drive_strength { 210 u32 reg_val; 211 u32 microamp; 212 }; 213 214 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants 215 * 216 * This values are not documented in KSZ9477 variants but confirmed by 217 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893 218 * and KSZ8563 are using same register (drive strength) settings like KSZ8795. 219 * 220 * Documentation in KSZ8795CLX provides more information with some 221 * recommendations: 222 * - for high speed signals 223 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using 224 * 2.5V or 3.3V VDDIO. 225 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with 226 * using 1.8V VDDIO. 227 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V 228 * or 3.3V VDDIO. 229 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO. 230 * 5. In same interface, the heavy loading should use higher one of the 231 * drive current strength. 232 * - for low speed signals 233 * 1. 3.3V VDDIO, use either 4 mA or 8 mA. 234 * 2. 2.5V VDDIO, use either 8 mA or 12 mA. 235 * 3. 1.8V VDDIO, use either 12 mA or 16 mA. 236 * 4. If it is heavy loading, can use higher drive current strength. 237 */ 238 static const struct ksz_drive_strength ksz9477_drive_strengths[] = { 239 { SW_DRIVE_STRENGTH_2MA, 2000 }, 240 { SW_DRIVE_STRENGTH_4MA, 4000 }, 241 { SW_DRIVE_STRENGTH_8MA, 8000 }, 242 { SW_DRIVE_STRENGTH_12MA, 12000 }, 243 { SW_DRIVE_STRENGTH_16MA, 16000 }, 244 { SW_DRIVE_STRENGTH_20MA, 20000 }, 245 { SW_DRIVE_STRENGTH_24MA, 24000 }, 246 { SW_DRIVE_STRENGTH_28MA, 28000 }, 247 }; 248 249 /* ksz88x3_drive_strengths - Drive strength mapping for KSZ8863, KSZ8873, .. 250 * variants. 251 * This values are documented in KSZ8873 and KSZ8863 datasheets. 252 */ 253 static const struct ksz_drive_strength ksz88x3_drive_strengths[] = { 254 { 0, 8000 }, 255 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 }, 256 }; 257 258 static void ksz88x3_phylink_mac_config(struct phylink_config *config, 259 unsigned int mode, 260 const struct phylink_link_state *state); 261 static void ksz_phylink_mac_config(struct phylink_config *config, 262 unsigned int mode, 263 const struct phylink_link_state *state); 264 static void ksz_phylink_mac_link_down(struct phylink_config *config, 265 unsigned int mode, 266 phy_interface_t interface); 267 268 static const struct phylink_mac_ops ksz88x3_phylink_mac_ops = { 269 .mac_config = ksz88x3_phylink_mac_config, 270 .mac_link_down = ksz_phylink_mac_link_down, 271 .mac_link_up = ksz8_phylink_mac_link_up, 272 }; 273 274 static const struct phylink_mac_ops ksz8_phylink_mac_ops = { 275 .mac_config = ksz_phylink_mac_config, 276 .mac_link_down = ksz_phylink_mac_link_down, 277 .mac_link_up = ksz8_phylink_mac_link_up, 278 }; 279 280 static const struct ksz_dev_ops ksz88xx_dev_ops = { 281 .setup = ksz8_setup, 282 .get_port_addr = ksz8_get_port_addr, 283 .cfg_port_member = ksz8_cfg_port_member, 284 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 285 .port_setup = ksz8_port_setup, 286 .r_phy = ksz8_r_phy, 287 .w_phy = ksz8_w_phy, 288 .r_mib_cnt = ksz8_r_mib_cnt, 289 .r_mib_pkt = ksz8_r_mib_pkt, 290 .r_mib_stat64 = ksz88xx_r_mib_stats64, 291 .freeze_mib = ksz8_freeze_mib, 292 .port_init_cnt = ksz8_port_init_cnt, 293 .fdb_dump = ksz8_fdb_dump, 294 .fdb_add = ksz8_fdb_add, 295 .fdb_del = ksz8_fdb_del, 296 .mdb_add = ksz8_mdb_add, 297 .mdb_del = ksz8_mdb_del, 298 .vlan_filtering = ksz8_port_vlan_filtering, 299 .vlan_add = ksz8_port_vlan_add, 300 .vlan_del = ksz8_port_vlan_del, 301 .mirror_add = ksz8_port_mirror_add, 302 .mirror_del = ksz8_port_mirror_del, 303 .get_caps = ksz8_get_caps, 304 .config_cpu_port = ksz8_config_cpu_port, 305 .enable_stp_addr = ksz8_enable_stp_addr, 306 .reset = ksz8_reset_switch, 307 .init = ksz8_switch_init, 308 .exit = ksz8_switch_exit, 309 .change_mtu = ksz8_change_mtu, 310 .pme_write8 = ksz8_pme_write8, 311 .pme_pread8 = ksz8_pme_pread8, 312 .pme_pwrite8 = ksz8_pme_pwrite8, 313 }; 314 315 static const struct ksz_dev_ops ksz87xx_dev_ops = { 316 .setup = ksz8_setup, 317 .get_port_addr = ksz8_get_port_addr, 318 .cfg_port_member = ksz8_cfg_port_member, 319 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 320 .port_setup = ksz8_port_setup, 321 .r_phy = ksz8_r_phy, 322 .w_phy = ksz8_w_phy, 323 .r_mib_cnt = ksz8_r_mib_cnt, 324 .r_mib_pkt = ksz8_r_mib_pkt, 325 .r_mib_stat64 = ksz_r_mib_stats64, 326 .freeze_mib = ksz8_freeze_mib, 327 .port_init_cnt = ksz8_port_init_cnt, 328 .fdb_dump = ksz8_fdb_dump, 329 .fdb_add = ksz8_fdb_add, 330 .fdb_del = ksz8_fdb_del, 331 .mdb_add = ksz8_mdb_add, 332 .mdb_del = ksz8_mdb_del, 333 .vlan_filtering = ksz8_port_vlan_filtering, 334 .vlan_add = ksz8_port_vlan_add, 335 .vlan_del = ksz8_port_vlan_del, 336 .mirror_add = ksz8_port_mirror_add, 337 .mirror_del = ksz8_port_mirror_del, 338 .get_caps = ksz8_get_caps, 339 .config_cpu_port = ksz8_config_cpu_port, 340 .enable_stp_addr = ksz8_enable_stp_addr, 341 .reset = ksz8_reset_switch, 342 .init = ksz8_switch_init, 343 .exit = ksz8_switch_exit, 344 .change_mtu = ksz8_change_mtu, 345 .pme_write8 = ksz8_pme_write8, 346 .pme_pread8 = ksz8_pme_pread8, 347 .pme_pwrite8 = ksz8_pme_pwrite8, 348 }; 349 350 static void ksz9477_phylink_mac_link_up(struct phylink_config *config, 351 struct phy_device *phydev, 352 unsigned int mode, 353 phy_interface_t interface, 354 int speed, int duplex, bool tx_pause, 355 bool rx_pause); 356 357 static const struct phylink_mac_ops ksz9477_phylink_mac_ops = { 358 .mac_config = ksz_phylink_mac_config, 359 .mac_link_down = ksz_phylink_mac_link_down, 360 .mac_link_up = ksz9477_phylink_mac_link_up, 361 }; 362 363 static const struct ksz_dev_ops ksz9477_dev_ops = { 364 .setup = ksz9477_setup, 365 .get_port_addr = ksz9477_get_port_addr, 366 .cfg_port_member = ksz9477_cfg_port_member, 367 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 368 .port_setup = ksz9477_port_setup, 369 .set_ageing_time = ksz9477_set_ageing_time, 370 .r_phy = ksz9477_r_phy, 371 .w_phy = ksz9477_w_phy, 372 .r_mib_cnt = ksz9477_r_mib_cnt, 373 .r_mib_pkt = ksz9477_r_mib_pkt, 374 .r_mib_stat64 = ksz_r_mib_stats64, 375 .freeze_mib = ksz9477_freeze_mib, 376 .port_init_cnt = ksz9477_port_init_cnt, 377 .vlan_filtering = ksz9477_port_vlan_filtering, 378 .vlan_add = ksz9477_port_vlan_add, 379 .vlan_del = ksz9477_port_vlan_del, 380 .mirror_add = ksz9477_port_mirror_add, 381 .mirror_del = ksz9477_port_mirror_del, 382 .get_caps = ksz9477_get_caps, 383 .fdb_dump = ksz9477_fdb_dump, 384 .fdb_add = ksz9477_fdb_add, 385 .fdb_del = ksz9477_fdb_del, 386 .mdb_add = ksz9477_mdb_add, 387 .mdb_del = ksz9477_mdb_del, 388 .change_mtu = ksz9477_change_mtu, 389 .pme_write8 = ksz_write8, 390 .pme_pread8 = ksz_pread8, 391 .pme_pwrite8 = ksz_pwrite8, 392 .config_cpu_port = ksz9477_config_cpu_port, 393 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc, 394 .enable_stp_addr = ksz9477_enable_stp_addr, 395 .reset = ksz9477_reset_switch, 396 .init = ksz9477_switch_init, 397 .exit = ksz9477_switch_exit, 398 }; 399 400 static const struct phylink_mac_ops lan937x_phylink_mac_ops = { 401 .mac_config = ksz_phylink_mac_config, 402 .mac_link_down = ksz_phylink_mac_link_down, 403 .mac_link_up = ksz9477_phylink_mac_link_up, 404 }; 405 406 static const struct ksz_dev_ops lan937x_dev_ops = { 407 .setup = lan937x_setup, 408 .teardown = lan937x_teardown, 409 .get_port_addr = ksz9477_get_port_addr, 410 .cfg_port_member = ksz9477_cfg_port_member, 411 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 412 .port_setup = lan937x_port_setup, 413 .set_ageing_time = lan937x_set_ageing_time, 414 .mdio_bus_preinit = lan937x_mdio_bus_preinit, 415 .create_phy_addr_map = lan937x_create_phy_addr_map, 416 .r_phy = lan937x_r_phy, 417 .w_phy = lan937x_w_phy, 418 .r_mib_cnt = ksz9477_r_mib_cnt, 419 .r_mib_pkt = ksz9477_r_mib_pkt, 420 .r_mib_stat64 = ksz_r_mib_stats64, 421 .freeze_mib = ksz9477_freeze_mib, 422 .port_init_cnt = ksz9477_port_init_cnt, 423 .vlan_filtering = ksz9477_port_vlan_filtering, 424 .vlan_add = ksz9477_port_vlan_add, 425 .vlan_del = ksz9477_port_vlan_del, 426 .mirror_add = ksz9477_port_mirror_add, 427 .mirror_del = ksz9477_port_mirror_del, 428 .get_caps = lan937x_phylink_get_caps, 429 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 430 .fdb_dump = ksz9477_fdb_dump, 431 .fdb_add = ksz9477_fdb_add, 432 .fdb_del = ksz9477_fdb_del, 433 .mdb_add = ksz9477_mdb_add, 434 .mdb_del = ksz9477_mdb_del, 435 .change_mtu = lan937x_change_mtu, 436 .config_cpu_port = lan937x_config_cpu_port, 437 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 438 .enable_stp_addr = ksz9477_enable_stp_addr, 439 .reset = lan937x_reset_switch, 440 .init = lan937x_switch_init, 441 .exit = lan937x_switch_exit, 442 }; 443 444 static const u16 ksz8795_regs[] = { 445 [REG_SW_MAC_ADDR] = 0x68, 446 [REG_IND_CTRL_0] = 0x6E, 447 [REG_IND_DATA_8] = 0x70, 448 [REG_IND_DATA_CHECK] = 0x72, 449 [REG_IND_DATA_HI] = 0x71, 450 [REG_IND_DATA_LO] = 0x75, 451 [REG_IND_MIB_CHECK] = 0x74, 452 [REG_IND_BYTE] = 0xA0, 453 [P_FORCE_CTRL] = 0x0C, 454 [P_LINK_STATUS] = 0x0E, 455 [P_LOCAL_CTRL] = 0x07, 456 [P_NEG_RESTART_CTRL] = 0x0D, 457 [P_REMOTE_STATUS] = 0x08, 458 [P_SPEED_STATUS] = 0x09, 459 [S_TAIL_TAG_CTRL] = 0x0C, 460 [P_STP_CTRL] = 0x02, 461 [S_START_CTRL] = 0x01, 462 [S_BROADCAST_CTRL] = 0x06, 463 [S_MULTICAST_CTRL] = 0x04, 464 [P_XMII_CTRL_0] = 0x06, 465 [P_XMII_CTRL_1] = 0x06, 466 [REG_SW_PME_CTRL] = 0x8003, 467 [REG_PORT_PME_STATUS] = 0x8003, 468 [REG_PORT_PME_CTRL] = 0x8007, 469 }; 470 471 static const u32 ksz8795_masks[] = { 472 [PORT_802_1P_REMAPPING] = BIT(7), 473 [SW_TAIL_TAG_ENABLE] = BIT(1), 474 [MIB_COUNTER_OVERFLOW] = BIT(6), 475 [MIB_COUNTER_VALID] = BIT(5), 476 [VLAN_TABLE_FID] = GENMASK(6, 0), 477 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 478 [VLAN_TABLE_VALID] = BIT(12), 479 [STATIC_MAC_TABLE_VALID] = BIT(21), 480 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 481 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 482 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 483 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 484 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 485 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 486 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 487 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 488 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 489 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 490 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 491 [P_MII_TX_FLOW_CTRL] = BIT(5), 492 [P_MII_RX_FLOW_CTRL] = BIT(5), 493 }; 494 495 static const u8 ksz8795_xmii_ctrl0[] = { 496 [P_MII_100MBIT] = 0, 497 [P_MII_10MBIT] = 1, 498 [P_MII_FULL_DUPLEX] = 0, 499 [P_MII_HALF_DUPLEX] = 1, 500 }; 501 502 static const u8 ksz8795_xmii_ctrl1[] = { 503 [P_RGMII_SEL] = 3, 504 [P_GMII_SEL] = 2, 505 [P_RMII_SEL] = 1, 506 [P_MII_SEL] = 0, 507 [P_GMII_1GBIT] = 1, 508 [P_GMII_NOT_1GBIT] = 0, 509 }; 510 511 static const u8 ksz8795_shifts[] = { 512 [VLAN_TABLE_MEMBERSHIP_S] = 7, 513 [VLAN_TABLE] = 16, 514 [STATIC_MAC_FWD_PORTS] = 16, 515 [STATIC_MAC_FID] = 24, 516 [DYNAMIC_MAC_ENTRIES_H] = 3, 517 [DYNAMIC_MAC_ENTRIES] = 29, 518 [DYNAMIC_MAC_FID] = 16, 519 [DYNAMIC_MAC_TIMESTAMP] = 27, 520 [DYNAMIC_MAC_SRC_PORT] = 24, 521 }; 522 523 static const u16 ksz8863_regs[] = { 524 [REG_SW_MAC_ADDR] = 0x70, 525 [REG_IND_CTRL_0] = 0x79, 526 [REG_IND_DATA_8] = 0x7B, 527 [REG_IND_DATA_CHECK] = 0x7B, 528 [REG_IND_DATA_HI] = 0x7C, 529 [REG_IND_DATA_LO] = 0x80, 530 [REG_IND_MIB_CHECK] = 0x80, 531 [P_FORCE_CTRL] = 0x0C, 532 [P_LINK_STATUS] = 0x0E, 533 [P_LOCAL_CTRL] = 0x0C, 534 [P_NEG_RESTART_CTRL] = 0x0D, 535 [P_REMOTE_STATUS] = 0x0E, 536 [P_SPEED_STATUS] = 0x0F, 537 [S_TAIL_TAG_CTRL] = 0x03, 538 [P_STP_CTRL] = 0x02, 539 [S_START_CTRL] = 0x01, 540 [S_BROADCAST_CTRL] = 0x06, 541 [S_MULTICAST_CTRL] = 0x04, 542 }; 543 544 static const u32 ksz8863_masks[] = { 545 [PORT_802_1P_REMAPPING] = BIT(3), 546 [SW_TAIL_TAG_ENABLE] = BIT(6), 547 [MIB_COUNTER_OVERFLOW] = BIT(7), 548 [MIB_COUNTER_VALID] = BIT(6), 549 [VLAN_TABLE_FID] = GENMASK(15, 12), 550 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 551 [VLAN_TABLE_VALID] = BIT(19), 552 [STATIC_MAC_TABLE_VALID] = BIT(19), 553 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 554 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 555 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 556 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 557 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 558 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 559 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 560 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 561 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 562 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 563 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 564 }; 565 566 static u8 ksz8863_shifts[] = { 567 [VLAN_TABLE_MEMBERSHIP_S] = 16, 568 [STATIC_MAC_FWD_PORTS] = 16, 569 [STATIC_MAC_FID] = 22, 570 [DYNAMIC_MAC_ENTRIES_H] = 8, 571 [DYNAMIC_MAC_ENTRIES] = 24, 572 [DYNAMIC_MAC_FID] = 16, 573 [DYNAMIC_MAC_TIMESTAMP] = 22, 574 [DYNAMIC_MAC_SRC_PORT] = 20, 575 }; 576 577 static const u16 ksz8895_regs[] = { 578 [REG_SW_MAC_ADDR] = 0x68, 579 [REG_IND_CTRL_0] = 0x6E, 580 [REG_IND_DATA_8] = 0x70, 581 [REG_IND_DATA_CHECK] = 0x72, 582 [REG_IND_DATA_HI] = 0x71, 583 [REG_IND_DATA_LO] = 0x75, 584 [REG_IND_MIB_CHECK] = 0x75, 585 [P_FORCE_CTRL] = 0x0C, 586 [P_LINK_STATUS] = 0x0E, 587 [P_LOCAL_CTRL] = 0x0C, 588 [P_NEG_RESTART_CTRL] = 0x0D, 589 [P_REMOTE_STATUS] = 0x0E, 590 [P_SPEED_STATUS] = 0x09, 591 [S_TAIL_TAG_CTRL] = 0x0C, 592 [P_STP_CTRL] = 0x02, 593 [S_START_CTRL] = 0x01, 594 [S_BROADCAST_CTRL] = 0x06, 595 [S_MULTICAST_CTRL] = 0x04, 596 }; 597 598 static const u32 ksz8895_masks[] = { 599 [PORT_802_1P_REMAPPING] = BIT(7), 600 [SW_TAIL_TAG_ENABLE] = BIT(1), 601 [MIB_COUNTER_OVERFLOW] = BIT(7), 602 [MIB_COUNTER_VALID] = BIT(6), 603 [VLAN_TABLE_FID] = GENMASK(6, 0), 604 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 605 [VLAN_TABLE_VALID] = BIT(12), 606 [STATIC_MAC_TABLE_VALID] = BIT(21), 607 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 608 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 609 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 610 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 611 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 612 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 613 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 614 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 615 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 616 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 617 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 618 }; 619 620 static const u8 ksz8895_shifts[] = { 621 [VLAN_TABLE_MEMBERSHIP_S] = 7, 622 [VLAN_TABLE] = 13, 623 [STATIC_MAC_FWD_PORTS] = 16, 624 [STATIC_MAC_FID] = 24, 625 [DYNAMIC_MAC_ENTRIES_H] = 3, 626 [DYNAMIC_MAC_ENTRIES] = 29, 627 [DYNAMIC_MAC_FID] = 16, 628 [DYNAMIC_MAC_TIMESTAMP] = 27, 629 [DYNAMIC_MAC_SRC_PORT] = 24, 630 }; 631 632 static const u16 ksz9477_regs[] = { 633 [REG_SW_MAC_ADDR] = 0x0302, 634 [P_STP_CTRL] = 0x0B04, 635 [S_START_CTRL] = 0x0300, 636 [S_BROADCAST_CTRL] = 0x0332, 637 [S_MULTICAST_CTRL] = 0x0331, 638 [P_XMII_CTRL_0] = 0x0300, 639 [P_XMII_CTRL_1] = 0x0301, 640 [REG_SW_PME_CTRL] = 0x0006, 641 [REG_PORT_PME_STATUS] = 0x0013, 642 [REG_PORT_PME_CTRL] = 0x0017, 643 }; 644 645 static const u32 ksz9477_masks[] = { 646 [ALU_STAT_WRITE] = 0, 647 [ALU_STAT_READ] = 1, 648 [P_MII_TX_FLOW_CTRL] = BIT(5), 649 [P_MII_RX_FLOW_CTRL] = BIT(3), 650 }; 651 652 static const u8 ksz9477_shifts[] = { 653 [ALU_STAT_INDEX] = 16, 654 }; 655 656 static const u8 ksz9477_xmii_ctrl0[] = { 657 [P_MII_100MBIT] = 1, 658 [P_MII_10MBIT] = 0, 659 [P_MII_FULL_DUPLEX] = 1, 660 [P_MII_HALF_DUPLEX] = 0, 661 }; 662 663 static const u8 ksz9477_xmii_ctrl1[] = { 664 [P_RGMII_SEL] = 0, 665 [P_RMII_SEL] = 1, 666 [P_GMII_SEL] = 2, 667 [P_MII_SEL] = 3, 668 [P_GMII_1GBIT] = 0, 669 [P_GMII_NOT_1GBIT] = 1, 670 }; 671 672 static const u32 lan937x_masks[] = { 673 [ALU_STAT_WRITE] = 1, 674 [ALU_STAT_READ] = 2, 675 [P_MII_TX_FLOW_CTRL] = BIT(5), 676 [P_MII_RX_FLOW_CTRL] = BIT(3), 677 }; 678 679 static const u8 lan937x_shifts[] = { 680 [ALU_STAT_INDEX] = 8, 681 }; 682 683 static const struct regmap_range ksz8563_valid_regs[] = { 684 regmap_reg_range(0x0000, 0x0003), 685 regmap_reg_range(0x0006, 0x0006), 686 regmap_reg_range(0x000f, 0x001f), 687 regmap_reg_range(0x0100, 0x0100), 688 regmap_reg_range(0x0104, 0x0107), 689 regmap_reg_range(0x010d, 0x010d), 690 regmap_reg_range(0x0110, 0x0113), 691 regmap_reg_range(0x0120, 0x012b), 692 regmap_reg_range(0x0201, 0x0201), 693 regmap_reg_range(0x0210, 0x0213), 694 regmap_reg_range(0x0300, 0x0300), 695 regmap_reg_range(0x0302, 0x031b), 696 regmap_reg_range(0x0320, 0x032b), 697 regmap_reg_range(0x0330, 0x0336), 698 regmap_reg_range(0x0338, 0x033e), 699 regmap_reg_range(0x0340, 0x035f), 700 regmap_reg_range(0x0370, 0x0370), 701 regmap_reg_range(0x0378, 0x0378), 702 regmap_reg_range(0x037c, 0x037d), 703 regmap_reg_range(0x0390, 0x0393), 704 regmap_reg_range(0x0400, 0x040e), 705 regmap_reg_range(0x0410, 0x042f), 706 regmap_reg_range(0x0500, 0x0519), 707 regmap_reg_range(0x0520, 0x054b), 708 regmap_reg_range(0x0550, 0x05b3), 709 710 /* port 1 */ 711 regmap_reg_range(0x1000, 0x1001), 712 regmap_reg_range(0x1004, 0x100b), 713 regmap_reg_range(0x1013, 0x1013), 714 regmap_reg_range(0x1017, 0x1017), 715 regmap_reg_range(0x101b, 0x101b), 716 regmap_reg_range(0x101f, 0x1021), 717 regmap_reg_range(0x1030, 0x1030), 718 regmap_reg_range(0x1100, 0x1111), 719 regmap_reg_range(0x111a, 0x111d), 720 regmap_reg_range(0x1122, 0x1127), 721 regmap_reg_range(0x112a, 0x112b), 722 regmap_reg_range(0x1136, 0x1139), 723 regmap_reg_range(0x113e, 0x113f), 724 regmap_reg_range(0x1400, 0x1401), 725 regmap_reg_range(0x1403, 0x1403), 726 regmap_reg_range(0x1410, 0x1417), 727 regmap_reg_range(0x1420, 0x1423), 728 regmap_reg_range(0x1500, 0x1507), 729 regmap_reg_range(0x1600, 0x1612), 730 regmap_reg_range(0x1800, 0x180f), 731 regmap_reg_range(0x1900, 0x1907), 732 regmap_reg_range(0x1914, 0x191b), 733 regmap_reg_range(0x1a00, 0x1a03), 734 regmap_reg_range(0x1a04, 0x1a08), 735 regmap_reg_range(0x1b00, 0x1b01), 736 regmap_reg_range(0x1b04, 0x1b04), 737 regmap_reg_range(0x1c00, 0x1c05), 738 regmap_reg_range(0x1c08, 0x1c1b), 739 740 /* port 2 */ 741 regmap_reg_range(0x2000, 0x2001), 742 regmap_reg_range(0x2004, 0x200b), 743 regmap_reg_range(0x2013, 0x2013), 744 regmap_reg_range(0x2017, 0x2017), 745 regmap_reg_range(0x201b, 0x201b), 746 regmap_reg_range(0x201f, 0x2021), 747 regmap_reg_range(0x2030, 0x2030), 748 regmap_reg_range(0x2100, 0x2111), 749 regmap_reg_range(0x211a, 0x211d), 750 regmap_reg_range(0x2122, 0x2127), 751 regmap_reg_range(0x212a, 0x212b), 752 regmap_reg_range(0x2136, 0x2139), 753 regmap_reg_range(0x213e, 0x213f), 754 regmap_reg_range(0x2400, 0x2401), 755 regmap_reg_range(0x2403, 0x2403), 756 regmap_reg_range(0x2410, 0x2417), 757 regmap_reg_range(0x2420, 0x2423), 758 regmap_reg_range(0x2500, 0x2507), 759 regmap_reg_range(0x2600, 0x2612), 760 regmap_reg_range(0x2800, 0x280f), 761 regmap_reg_range(0x2900, 0x2907), 762 regmap_reg_range(0x2914, 0x291b), 763 regmap_reg_range(0x2a00, 0x2a03), 764 regmap_reg_range(0x2a04, 0x2a08), 765 regmap_reg_range(0x2b00, 0x2b01), 766 regmap_reg_range(0x2b04, 0x2b04), 767 regmap_reg_range(0x2c00, 0x2c05), 768 regmap_reg_range(0x2c08, 0x2c1b), 769 770 /* port 3 */ 771 regmap_reg_range(0x3000, 0x3001), 772 regmap_reg_range(0x3004, 0x300b), 773 regmap_reg_range(0x3013, 0x3013), 774 regmap_reg_range(0x3017, 0x3017), 775 regmap_reg_range(0x301b, 0x301b), 776 regmap_reg_range(0x301f, 0x3021), 777 regmap_reg_range(0x3030, 0x3030), 778 regmap_reg_range(0x3300, 0x3301), 779 regmap_reg_range(0x3303, 0x3303), 780 regmap_reg_range(0x3400, 0x3401), 781 regmap_reg_range(0x3403, 0x3403), 782 regmap_reg_range(0x3410, 0x3417), 783 regmap_reg_range(0x3420, 0x3423), 784 regmap_reg_range(0x3500, 0x3507), 785 regmap_reg_range(0x3600, 0x3612), 786 regmap_reg_range(0x3800, 0x380f), 787 regmap_reg_range(0x3900, 0x3907), 788 regmap_reg_range(0x3914, 0x391b), 789 regmap_reg_range(0x3a00, 0x3a03), 790 regmap_reg_range(0x3a04, 0x3a08), 791 regmap_reg_range(0x3b00, 0x3b01), 792 regmap_reg_range(0x3b04, 0x3b04), 793 regmap_reg_range(0x3c00, 0x3c05), 794 regmap_reg_range(0x3c08, 0x3c1b), 795 }; 796 797 static const struct regmap_access_table ksz8563_register_set = { 798 .yes_ranges = ksz8563_valid_regs, 799 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 800 }; 801 802 static const struct regmap_range ksz9477_valid_regs[] = { 803 regmap_reg_range(0x0000, 0x0003), 804 regmap_reg_range(0x0006, 0x0006), 805 regmap_reg_range(0x0010, 0x001f), 806 regmap_reg_range(0x0100, 0x0100), 807 regmap_reg_range(0x0103, 0x0107), 808 regmap_reg_range(0x010d, 0x010d), 809 regmap_reg_range(0x0110, 0x0113), 810 regmap_reg_range(0x0120, 0x012b), 811 regmap_reg_range(0x0201, 0x0201), 812 regmap_reg_range(0x0210, 0x0213), 813 regmap_reg_range(0x0300, 0x0300), 814 regmap_reg_range(0x0302, 0x031b), 815 regmap_reg_range(0x0320, 0x032b), 816 regmap_reg_range(0x0330, 0x0336), 817 regmap_reg_range(0x0338, 0x033b), 818 regmap_reg_range(0x033e, 0x033e), 819 regmap_reg_range(0x0340, 0x035f), 820 regmap_reg_range(0x0370, 0x0370), 821 regmap_reg_range(0x0378, 0x0378), 822 regmap_reg_range(0x037c, 0x037d), 823 regmap_reg_range(0x0390, 0x0393), 824 regmap_reg_range(0x0400, 0x040e), 825 regmap_reg_range(0x0410, 0x042f), 826 regmap_reg_range(0x0444, 0x044b), 827 regmap_reg_range(0x0450, 0x046f), 828 regmap_reg_range(0x0500, 0x0519), 829 regmap_reg_range(0x0520, 0x054b), 830 regmap_reg_range(0x0550, 0x05b3), 831 regmap_reg_range(0x0604, 0x060b), 832 regmap_reg_range(0x0610, 0x0612), 833 regmap_reg_range(0x0614, 0x062c), 834 regmap_reg_range(0x0640, 0x0645), 835 regmap_reg_range(0x0648, 0x064d), 836 837 /* port 1 */ 838 regmap_reg_range(0x1000, 0x1001), 839 regmap_reg_range(0x1013, 0x1013), 840 regmap_reg_range(0x1017, 0x1017), 841 regmap_reg_range(0x101b, 0x101b), 842 regmap_reg_range(0x101f, 0x1020), 843 regmap_reg_range(0x1030, 0x1030), 844 regmap_reg_range(0x1100, 0x1115), 845 regmap_reg_range(0x111a, 0x111f), 846 regmap_reg_range(0x1120, 0x112b), 847 regmap_reg_range(0x1134, 0x113b), 848 regmap_reg_range(0x113c, 0x113f), 849 regmap_reg_range(0x1400, 0x1401), 850 regmap_reg_range(0x1403, 0x1403), 851 regmap_reg_range(0x1410, 0x1417), 852 regmap_reg_range(0x1420, 0x1423), 853 regmap_reg_range(0x1500, 0x1507), 854 regmap_reg_range(0x1600, 0x1613), 855 regmap_reg_range(0x1800, 0x180f), 856 regmap_reg_range(0x1820, 0x1827), 857 regmap_reg_range(0x1830, 0x1837), 858 regmap_reg_range(0x1840, 0x184b), 859 regmap_reg_range(0x1900, 0x1907), 860 regmap_reg_range(0x1914, 0x191b), 861 regmap_reg_range(0x1920, 0x1920), 862 regmap_reg_range(0x1923, 0x1927), 863 regmap_reg_range(0x1a00, 0x1a03), 864 regmap_reg_range(0x1a04, 0x1a07), 865 regmap_reg_range(0x1b00, 0x1b01), 866 regmap_reg_range(0x1b04, 0x1b04), 867 regmap_reg_range(0x1c00, 0x1c05), 868 regmap_reg_range(0x1c08, 0x1c1b), 869 870 /* port 2 */ 871 regmap_reg_range(0x2000, 0x2001), 872 regmap_reg_range(0x2013, 0x2013), 873 regmap_reg_range(0x2017, 0x2017), 874 regmap_reg_range(0x201b, 0x201b), 875 regmap_reg_range(0x201f, 0x2020), 876 regmap_reg_range(0x2030, 0x2030), 877 regmap_reg_range(0x2100, 0x2115), 878 regmap_reg_range(0x211a, 0x211f), 879 regmap_reg_range(0x2120, 0x212b), 880 regmap_reg_range(0x2134, 0x213b), 881 regmap_reg_range(0x213c, 0x213f), 882 regmap_reg_range(0x2400, 0x2401), 883 regmap_reg_range(0x2403, 0x2403), 884 regmap_reg_range(0x2410, 0x2417), 885 regmap_reg_range(0x2420, 0x2423), 886 regmap_reg_range(0x2500, 0x2507), 887 regmap_reg_range(0x2600, 0x2613), 888 regmap_reg_range(0x2800, 0x280f), 889 regmap_reg_range(0x2820, 0x2827), 890 regmap_reg_range(0x2830, 0x2837), 891 regmap_reg_range(0x2840, 0x284b), 892 regmap_reg_range(0x2900, 0x2907), 893 regmap_reg_range(0x2914, 0x291b), 894 regmap_reg_range(0x2920, 0x2920), 895 regmap_reg_range(0x2923, 0x2927), 896 regmap_reg_range(0x2a00, 0x2a03), 897 regmap_reg_range(0x2a04, 0x2a07), 898 regmap_reg_range(0x2b00, 0x2b01), 899 regmap_reg_range(0x2b04, 0x2b04), 900 regmap_reg_range(0x2c00, 0x2c05), 901 regmap_reg_range(0x2c08, 0x2c1b), 902 903 /* port 3 */ 904 regmap_reg_range(0x3000, 0x3001), 905 regmap_reg_range(0x3013, 0x3013), 906 regmap_reg_range(0x3017, 0x3017), 907 regmap_reg_range(0x301b, 0x301b), 908 regmap_reg_range(0x301f, 0x3020), 909 regmap_reg_range(0x3030, 0x3030), 910 regmap_reg_range(0x3100, 0x3115), 911 regmap_reg_range(0x311a, 0x311f), 912 regmap_reg_range(0x3120, 0x312b), 913 regmap_reg_range(0x3134, 0x313b), 914 regmap_reg_range(0x313c, 0x313f), 915 regmap_reg_range(0x3400, 0x3401), 916 regmap_reg_range(0x3403, 0x3403), 917 regmap_reg_range(0x3410, 0x3417), 918 regmap_reg_range(0x3420, 0x3423), 919 regmap_reg_range(0x3500, 0x3507), 920 regmap_reg_range(0x3600, 0x3613), 921 regmap_reg_range(0x3800, 0x380f), 922 regmap_reg_range(0x3820, 0x3827), 923 regmap_reg_range(0x3830, 0x3837), 924 regmap_reg_range(0x3840, 0x384b), 925 regmap_reg_range(0x3900, 0x3907), 926 regmap_reg_range(0x3914, 0x391b), 927 regmap_reg_range(0x3920, 0x3920), 928 regmap_reg_range(0x3923, 0x3927), 929 regmap_reg_range(0x3a00, 0x3a03), 930 regmap_reg_range(0x3a04, 0x3a07), 931 regmap_reg_range(0x3b00, 0x3b01), 932 regmap_reg_range(0x3b04, 0x3b04), 933 regmap_reg_range(0x3c00, 0x3c05), 934 regmap_reg_range(0x3c08, 0x3c1b), 935 936 /* port 4 */ 937 regmap_reg_range(0x4000, 0x4001), 938 regmap_reg_range(0x4013, 0x4013), 939 regmap_reg_range(0x4017, 0x4017), 940 regmap_reg_range(0x401b, 0x401b), 941 regmap_reg_range(0x401f, 0x4020), 942 regmap_reg_range(0x4030, 0x4030), 943 regmap_reg_range(0x4100, 0x4115), 944 regmap_reg_range(0x411a, 0x411f), 945 regmap_reg_range(0x4120, 0x412b), 946 regmap_reg_range(0x4134, 0x413b), 947 regmap_reg_range(0x413c, 0x413f), 948 regmap_reg_range(0x4400, 0x4401), 949 regmap_reg_range(0x4403, 0x4403), 950 regmap_reg_range(0x4410, 0x4417), 951 regmap_reg_range(0x4420, 0x4423), 952 regmap_reg_range(0x4500, 0x4507), 953 regmap_reg_range(0x4600, 0x4613), 954 regmap_reg_range(0x4800, 0x480f), 955 regmap_reg_range(0x4820, 0x4827), 956 regmap_reg_range(0x4830, 0x4837), 957 regmap_reg_range(0x4840, 0x484b), 958 regmap_reg_range(0x4900, 0x4907), 959 regmap_reg_range(0x4914, 0x491b), 960 regmap_reg_range(0x4920, 0x4920), 961 regmap_reg_range(0x4923, 0x4927), 962 regmap_reg_range(0x4a00, 0x4a03), 963 regmap_reg_range(0x4a04, 0x4a07), 964 regmap_reg_range(0x4b00, 0x4b01), 965 regmap_reg_range(0x4b04, 0x4b04), 966 regmap_reg_range(0x4c00, 0x4c05), 967 regmap_reg_range(0x4c08, 0x4c1b), 968 969 /* port 5 */ 970 regmap_reg_range(0x5000, 0x5001), 971 regmap_reg_range(0x5013, 0x5013), 972 regmap_reg_range(0x5017, 0x5017), 973 regmap_reg_range(0x501b, 0x501b), 974 regmap_reg_range(0x501f, 0x5020), 975 regmap_reg_range(0x5030, 0x5030), 976 regmap_reg_range(0x5100, 0x5115), 977 regmap_reg_range(0x511a, 0x511f), 978 regmap_reg_range(0x5120, 0x512b), 979 regmap_reg_range(0x5134, 0x513b), 980 regmap_reg_range(0x513c, 0x513f), 981 regmap_reg_range(0x5400, 0x5401), 982 regmap_reg_range(0x5403, 0x5403), 983 regmap_reg_range(0x5410, 0x5417), 984 regmap_reg_range(0x5420, 0x5423), 985 regmap_reg_range(0x5500, 0x5507), 986 regmap_reg_range(0x5600, 0x5613), 987 regmap_reg_range(0x5800, 0x580f), 988 regmap_reg_range(0x5820, 0x5827), 989 regmap_reg_range(0x5830, 0x5837), 990 regmap_reg_range(0x5840, 0x584b), 991 regmap_reg_range(0x5900, 0x5907), 992 regmap_reg_range(0x5914, 0x591b), 993 regmap_reg_range(0x5920, 0x5920), 994 regmap_reg_range(0x5923, 0x5927), 995 regmap_reg_range(0x5a00, 0x5a03), 996 regmap_reg_range(0x5a04, 0x5a07), 997 regmap_reg_range(0x5b00, 0x5b01), 998 regmap_reg_range(0x5b04, 0x5b04), 999 regmap_reg_range(0x5c00, 0x5c05), 1000 regmap_reg_range(0x5c08, 0x5c1b), 1001 1002 /* port 6 */ 1003 regmap_reg_range(0x6000, 0x6001), 1004 regmap_reg_range(0x6013, 0x6013), 1005 regmap_reg_range(0x6017, 0x6017), 1006 regmap_reg_range(0x601b, 0x601b), 1007 regmap_reg_range(0x601f, 0x6020), 1008 regmap_reg_range(0x6030, 0x6030), 1009 regmap_reg_range(0x6300, 0x6301), 1010 regmap_reg_range(0x6400, 0x6401), 1011 regmap_reg_range(0x6403, 0x6403), 1012 regmap_reg_range(0x6410, 0x6417), 1013 regmap_reg_range(0x6420, 0x6423), 1014 regmap_reg_range(0x6500, 0x6507), 1015 regmap_reg_range(0x6600, 0x6613), 1016 regmap_reg_range(0x6800, 0x680f), 1017 regmap_reg_range(0x6820, 0x6827), 1018 regmap_reg_range(0x6830, 0x6837), 1019 regmap_reg_range(0x6840, 0x684b), 1020 regmap_reg_range(0x6900, 0x6907), 1021 regmap_reg_range(0x6914, 0x691b), 1022 regmap_reg_range(0x6920, 0x6920), 1023 regmap_reg_range(0x6923, 0x6927), 1024 regmap_reg_range(0x6a00, 0x6a03), 1025 regmap_reg_range(0x6a04, 0x6a07), 1026 regmap_reg_range(0x6b00, 0x6b01), 1027 regmap_reg_range(0x6b04, 0x6b04), 1028 regmap_reg_range(0x6c00, 0x6c05), 1029 regmap_reg_range(0x6c08, 0x6c1b), 1030 1031 /* port 7 */ 1032 regmap_reg_range(0x7000, 0x7001), 1033 regmap_reg_range(0x7013, 0x7013), 1034 regmap_reg_range(0x7017, 0x7017), 1035 regmap_reg_range(0x701b, 0x701b), 1036 regmap_reg_range(0x701f, 0x7020), 1037 regmap_reg_range(0x7030, 0x7030), 1038 regmap_reg_range(0x7200, 0x7203), 1039 regmap_reg_range(0x7206, 0x7207), 1040 regmap_reg_range(0x7300, 0x7301), 1041 regmap_reg_range(0x7400, 0x7401), 1042 regmap_reg_range(0x7403, 0x7403), 1043 regmap_reg_range(0x7410, 0x7417), 1044 regmap_reg_range(0x7420, 0x7423), 1045 regmap_reg_range(0x7500, 0x7507), 1046 regmap_reg_range(0x7600, 0x7613), 1047 regmap_reg_range(0x7800, 0x780f), 1048 regmap_reg_range(0x7820, 0x7827), 1049 regmap_reg_range(0x7830, 0x7837), 1050 regmap_reg_range(0x7840, 0x784b), 1051 regmap_reg_range(0x7900, 0x7907), 1052 regmap_reg_range(0x7914, 0x791b), 1053 regmap_reg_range(0x7920, 0x7920), 1054 regmap_reg_range(0x7923, 0x7927), 1055 regmap_reg_range(0x7a00, 0x7a03), 1056 regmap_reg_range(0x7a04, 0x7a07), 1057 regmap_reg_range(0x7b00, 0x7b01), 1058 regmap_reg_range(0x7b04, 0x7b04), 1059 regmap_reg_range(0x7c00, 0x7c05), 1060 regmap_reg_range(0x7c08, 0x7c1b), 1061 }; 1062 1063 static const struct regmap_access_table ksz9477_register_set = { 1064 .yes_ranges = ksz9477_valid_regs, 1065 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 1066 }; 1067 1068 static const struct regmap_range ksz9896_valid_regs[] = { 1069 regmap_reg_range(0x0000, 0x0003), 1070 regmap_reg_range(0x0006, 0x0006), 1071 regmap_reg_range(0x0010, 0x001f), 1072 regmap_reg_range(0x0100, 0x0100), 1073 regmap_reg_range(0x0103, 0x0107), 1074 regmap_reg_range(0x010d, 0x010d), 1075 regmap_reg_range(0x0110, 0x0113), 1076 regmap_reg_range(0x0120, 0x0127), 1077 regmap_reg_range(0x0201, 0x0201), 1078 regmap_reg_range(0x0210, 0x0213), 1079 regmap_reg_range(0x0300, 0x0300), 1080 regmap_reg_range(0x0302, 0x030b), 1081 regmap_reg_range(0x0310, 0x031b), 1082 regmap_reg_range(0x0320, 0x032b), 1083 regmap_reg_range(0x0330, 0x0336), 1084 regmap_reg_range(0x0338, 0x033b), 1085 regmap_reg_range(0x033e, 0x033e), 1086 regmap_reg_range(0x0340, 0x035f), 1087 regmap_reg_range(0x0370, 0x0370), 1088 regmap_reg_range(0x0378, 0x0378), 1089 regmap_reg_range(0x037c, 0x037d), 1090 regmap_reg_range(0x0390, 0x0393), 1091 regmap_reg_range(0x0400, 0x040e), 1092 regmap_reg_range(0x0410, 0x042f), 1093 1094 /* port 1 */ 1095 regmap_reg_range(0x1000, 0x1001), 1096 regmap_reg_range(0x1013, 0x1013), 1097 regmap_reg_range(0x1017, 0x1017), 1098 regmap_reg_range(0x101b, 0x101b), 1099 regmap_reg_range(0x101f, 0x1020), 1100 regmap_reg_range(0x1030, 0x1030), 1101 regmap_reg_range(0x1100, 0x1115), 1102 regmap_reg_range(0x111a, 0x111f), 1103 regmap_reg_range(0x1122, 0x1127), 1104 regmap_reg_range(0x112a, 0x112b), 1105 regmap_reg_range(0x1136, 0x1139), 1106 regmap_reg_range(0x113e, 0x113f), 1107 regmap_reg_range(0x1400, 0x1401), 1108 regmap_reg_range(0x1403, 0x1403), 1109 regmap_reg_range(0x1410, 0x1417), 1110 regmap_reg_range(0x1420, 0x1423), 1111 regmap_reg_range(0x1500, 0x1507), 1112 regmap_reg_range(0x1600, 0x1612), 1113 regmap_reg_range(0x1800, 0x180f), 1114 regmap_reg_range(0x1820, 0x1827), 1115 regmap_reg_range(0x1830, 0x1837), 1116 regmap_reg_range(0x1840, 0x184b), 1117 regmap_reg_range(0x1900, 0x1907), 1118 regmap_reg_range(0x1914, 0x1915), 1119 regmap_reg_range(0x1a00, 0x1a03), 1120 regmap_reg_range(0x1a04, 0x1a07), 1121 regmap_reg_range(0x1b00, 0x1b01), 1122 regmap_reg_range(0x1b04, 0x1b04), 1123 1124 /* port 2 */ 1125 regmap_reg_range(0x2000, 0x2001), 1126 regmap_reg_range(0x2013, 0x2013), 1127 regmap_reg_range(0x2017, 0x2017), 1128 regmap_reg_range(0x201b, 0x201b), 1129 regmap_reg_range(0x201f, 0x2020), 1130 regmap_reg_range(0x2030, 0x2030), 1131 regmap_reg_range(0x2100, 0x2115), 1132 regmap_reg_range(0x211a, 0x211f), 1133 regmap_reg_range(0x2122, 0x2127), 1134 regmap_reg_range(0x212a, 0x212b), 1135 regmap_reg_range(0x2136, 0x2139), 1136 regmap_reg_range(0x213e, 0x213f), 1137 regmap_reg_range(0x2400, 0x2401), 1138 regmap_reg_range(0x2403, 0x2403), 1139 regmap_reg_range(0x2410, 0x2417), 1140 regmap_reg_range(0x2420, 0x2423), 1141 regmap_reg_range(0x2500, 0x2507), 1142 regmap_reg_range(0x2600, 0x2612), 1143 regmap_reg_range(0x2800, 0x280f), 1144 regmap_reg_range(0x2820, 0x2827), 1145 regmap_reg_range(0x2830, 0x2837), 1146 regmap_reg_range(0x2840, 0x284b), 1147 regmap_reg_range(0x2900, 0x2907), 1148 regmap_reg_range(0x2914, 0x2915), 1149 regmap_reg_range(0x2a00, 0x2a03), 1150 regmap_reg_range(0x2a04, 0x2a07), 1151 regmap_reg_range(0x2b00, 0x2b01), 1152 regmap_reg_range(0x2b04, 0x2b04), 1153 1154 /* port 3 */ 1155 regmap_reg_range(0x3000, 0x3001), 1156 regmap_reg_range(0x3013, 0x3013), 1157 regmap_reg_range(0x3017, 0x3017), 1158 regmap_reg_range(0x301b, 0x301b), 1159 regmap_reg_range(0x301f, 0x3020), 1160 regmap_reg_range(0x3030, 0x3030), 1161 regmap_reg_range(0x3100, 0x3115), 1162 regmap_reg_range(0x311a, 0x311f), 1163 regmap_reg_range(0x3122, 0x3127), 1164 regmap_reg_range(0x312a, 0x312b), 1165 regmap_reg_range(0x3136, 0x3139), 1166 regmap_reg_range(0x313e, 0x313f), 1167 regmap_reg_range(0x3400, 0x3401), 1168 regmap_reg_range(0x3403, 0x3403), 1169 regmap_reg_range(0x3410, 0x3417), 1170 regmap_reg_range(0x3420, 0x3423), 1171 regmap_reg_range(0x3500, 0x3507), 1172 regmap_reg_range(0x3600, 0x3612), 1173 regmap_reg_range(0x3800, 0x380f), 1174 regmap_reg_range(0x3820, 0x3827), 1175 regmap_reg_range(0x3830, 0x3837), 1176 regmap_reg_range(0x3840, 0x384b), 1177 regmap_reg_range(0x3900, 0x3907), 1178 regmap_reg_range(0x3914, 0x3915), 1179 regmap_reg_range(0x3a00, 0x3a03), 1180 regmap_reg_range(0x3a04, 0x3a07), 1181 regmap_reg_range(0x3b00, 0x3b01), 1182 regmap_reg_range(0x3b04, 0x3b04), 1183 1184 /* port 4 */ 1185 regmap_reg_range(0x4000, 0x4001), 1186 regmap_reg_range(0x4013, 0x4013), 1187 regmap_reg_range(0x4017, 0x4017), 1188 regmap_reg_range(0x401b, 0x401b), 1189 regmap_reg_range(0x401f, 0x4020), 1190 regmap_reg_range(0x4030, 0x4030), 1191 regmap_reg_range(0x4100, 0x4115), 1192 regmap_reg_range(0x411a, 0x411f), 1193 regmap_reg_range(0x4122, 0x4127), 1194 regmap_reg_range(0x412a, 0x412b), 1195 regmap_reg_range(0x4136, 0x4139), 1196 regmap_reg_range(0x413e, 0x413f), 1197 regmap_reg_range(0x4400, 0x4401), 1198 regmap_reg_range(0x4403, 0x4403), 1199 regmap_reg_range(0x4410, 0x4417), 1200 regmap_reg_range(0x4420, 0x4423), 1201 regmap_reg_range(0x4500, 0x4507), 1202 regmap_reg_range(0x4600, 0x4612), 1203 regmap_reg_range(0x4800, 0x480f), 1204 regmap_reg_range(0x4820, 0x4827), 1205 regmap_reg_range(0x4830, 0x4837), 1206 regmap_reg_range(0x4840, 0x484b), 1207 regmap_reg_range(0x4900, 0x4907), 1208 regmap_reg_range(0x4914, 0x4915), 1209 regmap_reg_range(0x4a00, 0x4a03), 1210 regmap_reg_range(0x4a04, 0x4a07), 1211 regmap_reg_range(0x4b00, 0x4b01), 1212 regmap_reg_range(0x4b04, 0x4b04), 1213 1214 /* port 5 */ 1215 regmap_reg_range(0x5000, 0x5001), 1216 regmap_reg_range(0x5013, 0x5013), 1217 regmap_reg_range(0x5017, 0x5017), 1218 regmap_reg_range(0x501b, 0x501b), 1219 regmap_reg_range(0x501f, 0x5020), 1220 regmap_reg_range(0x5030, 0x5030), 1221 regmap_reg_range(0x5100, 0x5115), 1222 regmap_reg_range(0x511a, 0x511f), 1223 regmap_reg_range(0x5122, 0x5127), 1224 regmap_reg_range(0x512a, 0x512b), 1225 regmap_reg_range(0x5136, 0x5139), 1226 regmap_reg_range(0x513e, 0x513f), 1227 regmap_reg_range(0x5400, 0x5401), 1228 regmap_reg_range(0x5403, 0x5403), 1229 regmap_reg_range(0x5410, 0x5417), 1230 regmap_reg_range(0x5420, 0x5423), 1231 regmap_reg_range(0x5500, 0x5507), 1232 regmap_reg_range(0x5600, 0x5612), 1233 regmap_reg_range(0x5800, 0x580f), 1234 regmap_reg_range(0x5820, 0x5827), 1235 regmap_reg_range(0x5830, 0x5837), 1236 regmap_reg_range(0x5840, 0x584b), 1237 regmap_reg_range(0x5900, 0x5907), 1238 regmap_reg_range(0x5914, 0x5915), 1239 regmap_reg_range(0x5a00, 0x5a03), 1240 regmap_reg_range(0x5a04, 0x5a07), 1241 regmap_reg_range(0x5b00, 0x5b01), 1242 regmap_reg_range(0x5b04, 0x5b04), 1243 1244 /* port 6 */ 1245 regmap_reg_range(0x6000, 0x6001), 1246 regmap_reg_range(0x6013, 0x6013), 1247 regmap_reg_range(0x6017, 0x6017), 1248 regmap_reg_range(0x601b, 0x601b), 1249 regmap_reg_range(0x601f, 0x6020), 1250 regmap_reg_range(0x6030, 0x6030), 1251 regmap_reg_range(0x6100, 0x6115), 1252 regmap_reg_range(0x611a, 0x611f), 1253 regmap_reg_range(0x6122, 0x6127), 1254 regmap_reg_range(0x612a, 0x612b), 1255 regmap_reg_range(0x6136, 0x6139), 1256 regmap_reg_range(0x613e, 0x613f), 1257 regmap_reg_range(0x6300, 0x6301), 1258 regmap_reg_range(0x6400, 0x6401), 1259 regmap_reg_range(0x6403, 0x6403), 1260 regmap_reg_range(0x6410, 0x6417), 1261 regmap_reg_range(0x6420, 0x6423), 1262 regmap_reg_range(0x6500, 0x6507), 1263 regmap_reg_range(0x6600, 0x6612), 1264 regmap_reg_range(0x6800, 0x680f), 1265 regmap_reg_range(0x6820, 0x6827), 1266 regmap_reg_range(0x6830, 0x6837), 1267 regmap_reg_range(0x6840, 0x684b), 1268 regmap_reg_range(0x6900, 0x6907), 1269 regmap_reg_range(0x6914, 0x6915), 1270 regmap_reg_range(0x6a00, 0x6a03), 1271 regmap_reg_range(0x6a04, 0x6a07), 1272 regmap_reg_range(0x6b00, 0x6b01), 1273 regmap_reg_range(0x6b04, 0x6b04), 1274 }; 1275 1276 static const struct regmap_access_table ksz9896_register_set = { 1277 .yes_ranges = ksz9896_valid_regs, 1278 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1279 }; 1280 1281 static const struct regmap_range ksz8873_valid_regs[] = { 1282 regmap_reg_range(0x00, 0x01), 1283 /* global control register */ 1284 regmap_reg_range(0x02, 0x0f), 1285 1286 /* port registers */ 1287 regmap_reg_range(0x10, 0x1d), 1288 regmap_reg_range(0x1e, 0x1f), 1289 regmap_reg_range(0x20, 0x2d), 1290 regmap_reg_range(0x2e, 0x2f), 1291 regmap_reg_range(0x30, 0x39), 1292 regmap_reg_range(0x3f, 0x3f), 1293 1294 /* advanced control registers */ 1295 regmap_reg_range(0x60, 0x6f), 1296 regmap_reg_range(0x70, 0x75), 1297 regmap_reg_range(0x76, 0x78), 1298 regmap_reg_range(0x79, 0x7a), 1299 regmap_reg_range(0x7b, 0x83), 1300 regmap_reg_range(0x8e, 0x99), 1301 regmap_reg_range(0x9a, 0xa5), 1302 regmap_reg_range(0xa6, 0xa6), 1303 regmap_reg_range(0xa7, 0xaa), 1304 regmap_reg_range(0xab, 0xae), 1305 regmap_reg_range(0xaf, 0xba), 1306 regmap_reg_range(0xbb, 0xbc), 1307 regmap_reg_range(0xbd, 0xbd), 1308 regmap_reg_range(0xc0, 0xc0), 1309 regmap_reg_range(0xc2, 0xc2), 1310 regmap_reg_range(0xc3, 0xc3), 1311 regmap_reg_range(0xc4, 0xc4), 1312 regmap_reg_range(0xc6, 0xc6), 1313 }; 1314 1315 static const struct regmap_access_table ksz8873_register_set = { 1316 .yes_ranges = ksz8873_valid_regs, 1317 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), 1318 }; 1319 1320 const struct ksz_chip_data ksz_switch_chips[] = { 1321 [KSZ8563] = { 1322 .chip_id = KSZ8563_CHIP_ID, 1323 .dev_name = "KSZ8563", 1324 .num_vlans = 4096, 1325 .num_alus = 4096, 1326 .num_statics = 16, 1327 .cpu_ports = 0x07, /* can be configured as cpu port */ 1328 .port_cnt = 3, /* total port count */ 1329 .port_nirqs = 3, 1330 .num_tx_queues = 4, 1331 .num_ipms = 8, 1332 .tc_cbs_supported = true, 1333 .ops = &ksz9477_dev_ops, 1334 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1335 .mib_names = ksz9477_mib_names, 1336 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1337 .reg_mib_cnt = MIB_COUNTER_NUM, 1338 .regs = ksz9477_regs, 1339 .masks = ksz9477_masks, 1340 .shifts = ksz9477_shifts, 1341 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1342 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1343 .supports_mii = {false, false, true}, 1344 .supports_rmii = {false, false, true}, 1345 .supports_rgmii = {false, false, true}, 1346 .internal_phy = {true, true, false}, 1347 .gbit_capable = {false, false, true}, 1348 .wr_table = &ksz8563_register_set, 1349 .rd_table = &ksz8563_register_set, 1350 }, 1351 1352 [KSZ8795] = { 1353 .chip_id = KSZ8795_CHIP_ID, 1354 .dev_name = "KSZ8795", 1355 .num_vlans = 4096, 1356 .num_alus = 0, 1357 .num_statics = 32, 1358 .cpu_ports = 0x10, /* can be configured as cpu port */ 1359 .port_cnt = 5, /* total cpu and user ports */ 1360 .num_tx_queues = 4, 1361 .num_ipms = 4, 1362 .ops = &ksz87xx_dev_ops, 1363 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1364 .ksz87xx_eee_link_erratum = true, 1365 .mib_names = ksz9477_mib_names, 1366 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1367 .reg_mib_cnt = MIB_COUNTER_NUM, 1368 .regs = ksz8795_regs, 1369 .masks = ksz8795_masks, 1370 .shifts = ksz8795_shifts, 1371 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1372 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1373 .supports_mii = {false, false, false, false, true}, 1374 .supports_rmii = {false, false, false, false, true}, 1375 .supports_rgmii = {false, false, false, false, true}, 1376 .internal_phy = {true, true, true, true, false}, 1377 }, 1378 1379 [KSZ8794] = { 1380 /* WARNING 1381 * ======= 1382 * KSZ8794 is similar to KSZ8795, except the port map 1383 * contains a gap between external and CPU ports, the 1384 * port map is NOT continuous. The per-port register 1385 * map is shifted accordingly too, i.e. registers at 1386 * offset 0x40 are NOT used on KSZ8794 and they ARE 1387 * used on KSZ8795 for external port 3. 1388 * external cpu 1389 * KSZ8794 0,1,2 4 1390 * KSZ8795 0,1,2,3 4 1391 * KSZ8765 0,1,2,3 4 1392 * port_cnt is configured as 5, even though it is 4 1393 */ 1394 .chip_id = KSZ8794_CHIP_ID, 1395 .dev_name = "KSZ8794", 1396 .num_vlans = 4096, 1397 .num_alus = 0, 1398 .num_statics = 32, 1399 .cpu_ports = 0x10, /* can be configured as cpu port */ 1400 .port_cnt = 5, /* total cpu and user ports */ 1401 .num_tx_queues = 4, 1402 .num_ipms = 4, 1403 .ops = &ksz87xx_dev_ops, 1404 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1405 .ksz87xx_eee_link_erratum = true, 1406 .mib_names = ksz9477_mib_names, 1407 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1408 .reg_mib_cnt = MIB_COUNTER_NUM, 1409 .regs = ksz8795_regs, 1410 .masks = ksz8795_masks, 1411 .shifts = ksz8795_shifts, 1412 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1413 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1414 .supports_mii = {false, false, false, false, true}, 1415 .supports_rmii = {false, false, false, false, true}, 1416 .supports_rgmii = {false, false, false, false, true}, 1417 .internal_phy = {true, true, true, false, false}, 1418 }, 1419 1420 [KSZ8765] = { 1421 .chip_id = KSZ8765_CHIP_ID, 1422 .dev_name = "KSZ8765", 1423 .num_vlans = 4096, 1424 .num_alus = 0, 1425 .num_statics = 32, 1426 .cpu_ports = 0x10, /* can be configured as cpu port */ 1427 .port_cnt = 5, /* total cpu and user ports */ 1428 .num_tx_queues = 4, 1429 .num_ipms = 4, 1430 .ops = &ksz87xx_dev_ops, 1431 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1432 .ksz87xx_eee_link_erratum = true, 1433 .mib_names = ksz9477_mib_names, 1434 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1435 .reg_mib_cnt = MIB_COUNTER_NUM, 1436 .regs = ksz8795_regs, 1437 .masks = ksz8795_masks, 1438 .shifts = ksz8795_shifts, 1439 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1440 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1441 .supports_mii = {false, false, false, false, true}, 1442 .supports_rmii = {false, false, false, false, true}, 1443 .supports_rgmii = {false, false, false, false, true}, 1444 .internal_phy = {true, true, true, true, false}, 1445 }, 1446 1447 [KSZ88X3] = { 1448 .chip_id = KSZ88X3_CHIP_ID, 1449 .dev_name = "KSZ8863/KSZ8873", 1450 .num_vlans = 16, 1451 .num_alus = 0, 1452 .num_statics = 8, 1453 .cpu_ports = 0x4, /* can be configured as cpu port */ 1454 .port_cnt = 3, 1455 .num_tx_queues = 4, 1456 .num_ipms = 4, 1457 .ops = &ksz88xx_dev_ops, 1458 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1459 .mib_names = ksz88xx_mib_names, 1460 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1461 .reg_mib_cnt = MIB_COUNTER_NUM, 1462 .regs = ksz8863_regs, 1463 .masks = ksz8863_masks, 1464 .shifts = ksz8863_shifts, 1465 .supports_mii = {false, false, true}, 1466 .supports_rmii = {false, false, true}, 1467 .internal_phy = {true, true, false}, 1468 .wr_table = &ksz8873_register_set, 1469 .rd_table = &ksz8873_register_set, 1470 }, 1471 1472 [KSZ8864] = { 1473 /* WARNING 1474 * ======= 1475 * KSZ8864 is similar to KSZ8895, except the first port 1476 * does not exist. 1477 * external cpu 1478 * KSZ8864 1,2,3 4 1479 * KSZ8895 0,1,2,3 4 1480 * port_cnt is configured as 5, even though it is 4 1481 */ 1482 .chip_id = KSZ8864_CHIP_ID, 1483 .dev_name = "KSZ8864", 1484 .num_vlans = 4096, 1485 .num_alus = 0, 1486 .num_statics = 32, 1487 .cpu_ports = 0x10, /* can be configured as cpu port */ 1488 .port_cnt = 5, /* total cpu and user ports */ 1489 .num_tx_queues = 4, 1490 .num_ipms = 4, 1491 .ops = &ksz88xx_dev_ops, 1492 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1493 .mib_names = ksz88xx_mib_names, 1494 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1495 .reg_mib_cnt = MIB_COUNTER_NUM, 1496 .regs = ksz8895_regs, 1497 .masks = ksz8895_masks, 1498 .shifts = ksz8895_shifts, 1499 .supports_mii = {false, false, false, false, true}, 1500 .supports_rmii = {false, false, false, false, true}, 1501 .internal_phy = {false, true, true, true, false}, 1502 }, 1503 1504 [KSZ8895] = { 1505 .chip_id = KSZ8895_CHIP_ID, 1506 .dev_name = "KSZ8895", 1507 .num_vlans = 4096, 1508 .num_alus = 0, 1509 .num_statics = 32, 1510 .cpu_ports = 0x10, /* can be configured as cpu port */ 1511 .port_cnt = 5, /* total cpu and user ports */ 1512 .num_tx_queues = 4, 1513 .num_ipms = 4, 1514 .ops = &ksz88xx_dev_ops, 1515 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1516 .mib_names = ksz88xx_mib_names, 1517 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1518 .reg_mib_cnt = MIB_COUNTER_NUM, 1519 .regs = ksz8895_regs, 1520 .masks = ksz8895_masks, 1521 .shifts = ksz8895_shifts, 1522 .supports_mii = {false, false, false, false, true}, 1523 .supports_rmii = {false, false, false, false, true}, 1524 .internal_phy = {true, true, true, true, false}, 1525 }, 1526 1527 [KSZ9477] = { 1528 .chip_id = KSZ9477_CHIP_ID, 1529 .dev_name = "KSZ9477", 1530 .num_vlans = 4096, 1531 .num_alus = 4096, 1532 .num_statics = 16, 1533 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1534 .port_cnt = 7, /* total physical port count */ 1535 .port_nirqs = 4, 1536 .num_tx_queues = 4, 1537 .num_ipms = 8, 1538 .tc_cbs_supported = true, 1539 .ops = &ksz9477_dev_ops, 1540 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1541 .phy_errata_9477 = true, 1542 .mib_names = ksz9477_mib_names, 1543 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1544 .reg_mib_cnt = MIB_COUNTER_NUM, 1545 .regs = ksz9477_regs, 1546 .masks = ksz9477_masks, 1547 .shifts = ksz9477_shifts, 1548 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1549 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1550 .supports_mii = {false, false, false, false, 1551 false, true, false}, 1552 .supports_rmii = {false, false, false, false, 1553 false, true, false}, 1554 .supports_rgmii = {false, false, false, false, 1555 false, true, false}, 1556 .internal_phy = {true, true, true, true, 1557 true, false, false}, 1558 .gbit_capable = {true, true, true, true, true, true, true}, 1559 .wr_table = &ksz9477_register_set, 1560 .rd_table = &ksz9477_register_set, 1561 }, 1562 1563 [KSZ9896] = { 1564 .chip_id = KSZ9896_CHIP_ID, 1565 .dev_name = "KSZ9896", 1566 .num_vlans = 4096, 1567 .num_alus = 4096, 1568 .num_statics = 16, 1569 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1570 .port_cnt = 6, /* total physical port count */ 1571 .port_nirqs = 2, 1572 .num_tx_queues = 4, 1573 .num_ipms = 8, 1574 .ops = &ksz9477_dev_ops, 1575 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1576 .phy_errata_9477 = true, 1577 .mib_names = ksz9477_mib_names, 1578 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1579 .reg_mib_cnt = MIB_COUNTER_NUM, 1580 .regs = ksz9477_regs, 1581 .masks = ksz9477_masks, 1582 .shifts = ksz9477_shifts, 1583 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1584 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1585 .supports_mii = {false, false, false, false, 1586 false, true}, 1587 .supports_rmii = {false, false, false, false, 1588 false, true}, 1589 .supports_rgmii = {false, false, false, false, 1590 false, true}, 1591 .internal_phy = {true, true, true, true, 1592 true, false}, 1593 .gbit_capable = {true, true, true, true, true, true}, 1594 .wr_table = &ksz9896_register_set, 1595 .rd_table = &ksz9896_register_set, 1596 }, 1597 1598 [KSZ9897] = { 1599 .chip_id = KSZ9897_CHIP_ID, 1600 .dev_name = "KSZ9897", 1601 .num_vlans = 4096, 1602 .num_alus = 4096, 1603 .num_statics = 16, 1604 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1605 .port_cnt = 7, /* total physical port count */ 1606 .port_nirqs = 2, 1607 .num_tx_queues = 4, 1608 .num_ipms = 8, 1609 .ops = &ksz9477_dev_ops, 1610 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1611 .phy_errata_9477 = true, 1612 .mib_names = ksz9477_mib_names, 1613 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1614 .reg_mib_cnt = MIB_COUNTER_NUM, 1615 .regs = ksz9477_regs, 1616 .masks = ksz9477_masks, 1617 .shifts = ksz9477_shifts, 1618 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1619 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1620 .supports_mii = {false, false, false, false, 1621 false, true, true}, 1622 .supports_rmii = {false, false, false, false, 1623 false, true, true}, 1624 .supports_rgmii = {false, false, false, false, 1625 false, true, true}, 1626 .internal_phy = {true, true, true, true, 1627 true, false, false}, 1628 .gbit_capable = {true, true, true, true, true, true, true}, 1629 }, 1630 1631 [KSZ9893] = { 1632 .chip_id = KSZ9893_CHIP_ID, 1633 .dev_name = "KSZ9893", 1634 .num_vlans = 4096, 1635 .num_alus = 4096, 1636 .num_statics = 16, 1637 .cpu_ports = 0x07, /* can be configured as cpu port */ 1638 .port_cnt = 3, /* total port count */ 1639 .port_nirqs = 2, 1640 .num_tx_queues = 4, 1641 .num_ipms = 8, 1642 .ops = &ksz9477_dev_ops, 1643 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1644 .mib_names = ksz9477_mib_names, 1645 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1646 .reg_mib_cnt = MIB_COUNTER_NUM, 1647 .regs = ksz9477_regs, 1648 .masks = ksz9477_masks, 1649 .shifts = ksz9477_shifts, 1650 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1651 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1652 .supports_mii = {false, false, true}, 1653 .supports_rmii = {false, false, true}, 1654 .supports_rgmii = {false, false, true}, 1655 .internal_phy = {true, true, false}, 1656 .gbit_capable = {true, true, true}, 1657 }, 1658 1659 [KSZ9563] = { 1660 .chip_id = KSZ9563_CHIP_ID, 1661 .dev_name = "KSZ9563", 1662 .num_vlans = 4096, 1663 .num_alus = 4096, 1664 .num_statics = 16, 1665 .cpu_ports = 0x07, /* can be configured as cpu port */ 1666 .port_cnt = 3, /* total port count */ 1667 .port_nirqs = 3, 1668 .num_tx_queues = 4, 1669 .num_ipms = 8, 1670 .tc_cbs_supported = true, 1671 .ops = &ksz9477_dev_ops, 1672 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1673 .mib_names = ksz9477_mib_names, 1674 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1675 .reg_mib_cnt = MIB_COUNTER_NUM, 1676 .regs = ksz9477_regs, 1677 .masks = ksz9477_masks, 1678 .shifts = ksz9477_shifts, 1679 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1680 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1681 .supports_mii = {false, false, true}, 1682 .supports_rmii = {false, false, true}, 1683 .supports_rgmii = {false, false, true}, 1684 .internal_phy = {true, true, false}, 1685 .gbit_capable = {true, true, true}, 1686 }, 1687 1688 [KSZ8567] = { 1689 .chip_id = KSZ8567_CHIP_ID, 1690 .dev_name = "KSZ8567", 1691 .num_vlans = 4096, 1692 .num_alus = 4096, 1693 .num_statics = 16, 1694 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1695 .port_cnt = 7, /* total port count */ 1696 .port_nirqs = 3, 1697 .num_tx_queues = 4, 1698 .num_ipms = 8, 1699 .tc_cbs_supported = true, 1700 .ops = &ksz9477_dev_ops, 1701 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1702 .phy_errata_9477 = true, 1703 .mib_names = ksz9477_mib_names, 1704 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1705 .reg_mib_cnt = MIB_COUNTER_NUM, 1706 .regs = ksz9477_regs, 1707 .masks = ksz9477_masks, 1708 .shifts = ksz9477_shifts, 1709 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1710 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1711 .supports_mii = {false, false, false, false, 1712 false, true, true}, 1713 .supports_rmii = {false, false, false, false, 1714 false, true, true}, 1715 .supports_rgmii = {false, false, false, false, 1716 false, true, true}, 1717 .internal_phy = {true, true, true, true, 1718 true, false, false}, 1719 .gbit_capable = {false, false, false, false, false, 1720 true, true}, 1721 }, 1722 1723 [KSZ9567] = { 1724 .chip_id = KSZ9567_CHIP_ID, 1725 .dev_name = "KSZ9567", 1726 .num_vlans = 4096, 1727 .num_alus = 4096, 1728 .num_statics = 16, 1729 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1730 .port_cnt = 7, /* total physical port count */ 1731 .port_nirqs = 3, 1732 .num_tx_queues = 4, 1733 .num_ipms = 8, 1734 .tc_cbs_supported = true, 1735 .ops = &ksz9477_dev_ops, 1736 .mib_names = ksz9477_mib_names, 1737 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1738 .reg_mib_cnt = MIB_COUNTER_NUM, 1739 .regs = ksz9477_regs, 1740 .masks = ksz9477_masks, 1741 .shifts = ksz9477_shifts, 1742 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1743 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1744 .supports_mii = {false, false, false, false, 1745 false, true, true}, 1746 .supports_rmii = {false, false, false, false, 1747 false, true, true}, 1748 .supports_rgmii = {false, false, false, false, 1749 false, true, true}, 1750 .internal_phy = {true, true, true, true, 1751 true, false, false}, 1752 .gbit_capable = {true, true, true, true, true, true, true}, 1753 }, 1754 1755 [LAN9370] = { 1756 .chip_id = LAN9370_CHIP_ID, 1757 .dev_name = "LAN9370", 1758 .num_vlans = 4096, 1759 .num_alus = 1024, 1760 .num_statics = 256, 1761 .cpu_ports = 0x10, /* can be configured as cpu port */ 1762 .port_cnt = 5, /* total physical port count */ 1763 .port_nirqs = 6, 1764 .num_tx_queues = 8, 1765 .num_ipms = 8, 1766 .tc_cbs_supported = true, 1767 .phy_side_mdio_supported = true, 1768 .ops = &lan937x_dev_ops, 1769 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1770 .mib_names = ksz9477_mib_names, 1771 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1772 .reg_mib_cnt = MIB_COUNTER_NUM, 1773 .regs = ksz9477_regs, 1774 .masks = lan937x_masks, 1775 .shifts = lan937x_shifts, 1776 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1777 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1778 .supports_mii = {false, false, false, false, true}, 1779 .supports_rmii = {false, false, false, false, true}, 1780 .supports_rgmii = {false, false, false, false, true}, 1781 .internal_phy = {true, true, true, true, false}, 1782 }, 1783 1784 [LAN9371] = { 1785 .chip_id = LAN9371_CHIP_ID, 1786 .dev_name = "LAN9371", 1787 .num_vlans = 4096, 1788 .num_alus = 1024, 1789 .num_statics = 256, 1790 .cpu_ports = 0x30, /* can be configured as cpu port */ 1791 .port_cnt = 6, /* total physical port count */ 1792 .port_nirqs = 6, 1793 .num_tx_queues = 8, 1794 .num_ipms = 8, 1795 .tc_cbs_supported = true, 1796 .phy_side_mdio_supported = true, 1797 .ops = &lan937x_dev_ops, 1798 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1799 .mib_names = ksz9477_mib_names, 1800 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1801 .reg_mib_cnt = MIB_COUNTER_NUM, 1802 .regs = ksz9477_regs, 1803 .masks = lan937x_masks, 1804 .shifts = lan937x_shifts, 1805 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1806 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1807 .supports_mii = {false, false, false, false, true, true}, 1808 .supports_rmii = {false, false, false, false, true, true}, 1809 .supports_rgmii = {false, false, false, false, true, true}, 1810 .internal_phy = {true, true, true, true, false, false}, 1811 }, 1812 1813 [LAN9372] = { 1814 .chip_id = LAN9372_CHIP_ID, 1815 .dev_name = "LAN9372", 1816 .num_vlans = 4096, 1817 .num_alus = 1024, 1818 .num_statics = 256, 1819 .cpu_ports = 0x30, /* can be configured as cpu port */ 1820 .port_cnt = 8, /* total physical port count */ 1821 .port_nirqs = 6, 1822 .num_tx_queues = 8, 1823 .num_ipms = 8, 1824 .tc_cbs_supported = true, 1825 .phy_side_mdio_supported = true, 1826 .ops = &lan937x_dev_ops, 1827 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1828 .mib_names = ksz9477_mib_names, 1829 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1830 .reg_mib_cnt = MIB_COUNTER_NUM, 1831 .regs = ksz9477_regs, 1832 .masks = lan937x_masks, 1833 .shifts = lan937x_shifts, 1834 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1835 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1836 .supports_mii = {false, false, false, false, 1837 true, true, false, false}, 1838 .supports_rmii = {false, false, false, false, 1839 true, true, false, false}, 1840 .supports_rgmii = {false, false, false, false, 1841 true, true, false, false}, 1842 .internal_phy = {true, true, true, true, 1843 false, false, true, true}, 1844 }, 1845 1846 [LAN9373] = { 1847 .chip_id = LAN9373_CHIP_ID, 1848 .dev_name = "LAN9373", 1849 .num_vlans = 4096, 1850 .num_alus = 1024, 1851 .num_statics = 256, 1852 .cpu_ports = 0x38, /* can be configured as cpu port */ 1853 .port_cnt = 5, /* total physical port count */ 1854 .port_nirqs = 6, 1855 .num_tx_queues = 8, 1856 .num_ipms = 8, 1857 .tc_cbs_supported = true, 1858 .phy_side_mdio_supported = true, 1859 .ops = &lan937x_dev_ops, 1860 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1861 .mib_names = ksz9477_mib_names, 1862 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1863 .reg_mib_cnt = MIB_COUNTER_NUM, 1864 .regs = ksz9477_regs, 1865 .masks = lan937x_masks, 1866 .shifts = lan937x_shifts, 1867 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1868 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1869 .supports_mii = {false, false, false, false, 1870 true, true, false, false}, 1871 .supports_rmii = {false, false, false, false, 1872 true, true, false, false}, 1873 .supports_rgmii = {false, false, false, false, 1874 true, true, false, false}, 1875 .internal_phy = {true, true, true, false, 1876 false, false, true, true}, 1877 }, 1878 1879 [LAN9374] = { 1880 .chip_id = LAN9374_CHIP_ID, 1881 .dev_name = "LAN9374", 1882 .num_vlans = 4096, 1883 .num_alus = 1024, 1884 .num_statics = 256, 1885 .cpu_ports = 0x30, /* can be configured as cpu port */ 1886 .port_cnt = 8, /* total physical port count */ 1887 .port_nirqs = 6, 1888 .num_tx_queues = 8, 1889 .num_ipms = 8, 1890 .tc_cbs_supported = true, 1891 .phy_side_mdio_supported = true, 1892 .ops = &lan937x_dev_ops, 1893 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1894 .mib_names = ksz9477_mib_names, 1895 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1896 .reg_mib_cnt = MIB_COUNTER_NUM, 1897 .regs = ksz9477_regs, 1898 .masks = lan937x_masks, 1899 .shifts = lan937x_shifts, 1900 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1901 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1902 .supports_mii = {false, false, false, false, 1903 true, true, false, false}, 1904 .supports_rmii = {false, false, false, false, 1905 true, true, false, false}, 1906 .supports_rgmii = {false, false, false, false, 1907 true, true, false, false}, 1908 .internal_phy = {true, true, true, true, 1909 false, false, true, true}, 1910 }, 1911 }; 1912 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1913 1914 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1915 { 1916 int i; 1917 1918 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1919 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1920 1921 if (chip->chip_id == prod_num) 1922 return chip; 1923 } 1924 1925 return NULL; 1926 } 1927 1928 static int ksz_check_device_id(struct ksz_device *dev) 1929 { 1930 const struct ksz_chip_data *expected_chip_data; 1931 u32 expected_chip_id; 1932 1933 if (dev->pdata) { 1934 expected_chip_id = dev->pdata->chip_id; 1935 expected_chip_data = ksz_lookup_info(expected_chip_id); 1936 if (WARN_ON(!expected_chip_data)) 1937 return -ENODEV; 1938 } else { 1939 expected_chip_data = of_device_get_match_data(dev->dev); 1940 expected_chip_id = expected_chip_data->chip_id; 1941 } 1942 1943 if (expected_chip_id != dev->chip_id) { 1944 dev_err(dev->dev, 1945 "Device tree specifies chip %s but found %s, please fix it!\n", 1946 expected_chip_data->dev_name, dev->info->dev_name); 1947 return -ENODEV; 1948 } 1949 1950 return 0; 1951 } 1952 1953 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1954 struct phylink_config *config) 1955 { 1956 struct ksz_device *dev = ds->priv; 1957 1958 if (dev->info->supports_mii[port]) 1959 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1960 1961 if (dev->info->supports_rmii[port]) 1962 __set_bit(PHY_INTERFACE_MODE_RMII, 1963 config->supported_interfaces); 1964 1965 if (dev->info->supports_rgmii[port]) 1966 phy_interface_set_rgmii(config->supported_interfaces); 1967 1968 if (dev->info->internal_phy[port]) { 1969 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1970 config->supported_interfaces); 1971 /* Compatibility for phylib's default interface type when the 1972 * phy-mode property is absent 1973 */ 1974 __set_bit(PHY_INTERFACE_MODE_GMII, 1975 config->supported_interfaces); 1976 } 1977 1978 if (dev->dev_ops->get_caps) 1979 dev->dev_ops->get_caps(dev, port, config); 1980 } 1981 1982 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 1983 { 1984 struct ethtool_pause_stats *pstats; 1985 struct rtnl_link_stats64 *stats; 1986 struct ksz_stats_raw *raw; 1987 struct ksz_port_mib *mib; 1988 int ret; 1989 1990 mib = &dev->ports[port].mib; 1991 stats = &mib->stats64; 1992 pstats = &mib->pause_stats; 1993 raw = (struct ksz_stats_raw *)mib->counters; 1994 1995 spin_lock(&mib->stats64_lock); 1996 1997 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1998 raw->rx_pause; 1999 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2000 raw->tx_pause; 2001 2002 /* HW counters are counting bytes + FCS which is not acceptable 2003 * for rtnl_link_stats64 interface 2004 */ 2005 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 2006 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 2007 2008 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2009 raw->rx_oversize; 2010 2011 stats->rx_crc_errors = raw->rx_crc_err; 2012 stats->rx_frame_errors = raw->rx_align_err; 2013 stats->rx_dropped = raw->rx_discards; 2014 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2015 stats->rx_frame_errors + stats->rx_dropped; 2016 2017 stats->tx_window_errors = raw->tx_late_col; 2018 stats->tx_fifo_errors = raw->tx_discards; 2019 stats->tx_aborted_errors = raw->tx_exc_col; 2020 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2021 stats->tx_aborted_errors; 2022 2023 stats->multicast = raw->rx_mcast; 2024 stats->collisions = raw->tx_total_col; 2025 2026 pstats->tx_pause_frames = raw->tx_pause; 2027 pstats->rx_pause_frames = raw->rx_pause; 2028 2029 spin_unlock(&mib->stats64_lock); 2030 2031 if (dev->info->phy_errata_9477) { 2032 ret = ksz9477_errata_monitor(dev, port, raw->tx_late_col); 2033 if (ret) 2034 dev_err(dev->dev, "Failed to monitor transmission halt\n"); 2035 } 2036 } 2037 2038 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 2039 { 2040 struct ethtool_pause_stats *pstats; 2041 struct rtnl_link_stats64 *stats; 2042 struct ksz88xx_stats_raw *raw; 2043 struct ksz_port_mib *mib; 2044 2045 mib = &dev->ports[port].mib; 2046 stats = &mib->stats64; 2047 pstats = &mib->pause_stats; 2048 raw = (struct ksz88xx_stats_raw *)mib->counters; 2049 2050 spin_lock(&mib->stats64_lock); 2051 2052 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 2053 raw->rx_pause; 2054 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2055 raw->tx_pause; 2056 2057 /* HW counters are counting bytes + FCS which is not acceptable 2058 * for rtnl_link_stats64 interface 2059 */ 2060 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 2061 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 2062 2063 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2064 raw->rx_oversize; 2065 2066 stats->rx_crc_errors = raw->rx_crc_err; 2067 stats->rx_frame_errors = raw->rx_align_err; 2068 stats->rx_dropped = raw->rx_discards; 2069 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2070 stats->rx_frame_errors + stats->rx_dropped; 2071 2072 stats->tx_window_errors = raw->tx_late_col; 2073 stats->tx_fifo_errors = raw->tx_discards; 2074 stats->tx_aborted_errors = raw->tx_exc_col; 2075 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2076 stats->tx_aborted_errors; 2077 2078 stats->multicast = raw->rx_mcast; 2079 stats->collisions = raw->tx_total_col; 2080 2081 pstats->tx_pause_frames = raw->tx_pause; 2082 pstats->rx_pause_frames = raw->rx_pause; 2083 2084 spin_unlock(&mib->stats64_lock); 2085 } 2086 2087 static void ksz_get_stats64(struct dsa_switch *ds, int port, 2088 struct rtnl_link_stats64 *s) 2089 { 2090 struct ksz_device *dev = ds->priv; 2091 struct ksz_port_mib *mib; 2092 2093 mib = &dev->ports[port].mib; 2094 2095 spin_lock(&mib->stats64_lock); 2096 memcpy(s, &mib->stats64, sizeof(*s)); 2097 spin_unlock(&mib->stats64_lock); 2098 } 2099 2100 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 2101 struct ethtool_pause_stats *pause_stats) 2102 { 2103 struct ksz_device *dev = ds->priv; 2104 struct ksz_port_mib *mib; 2105 2106 mib = &dev->ports[port].mib; 2107 2108 spin_lock(&mib->stats64_lock); 2109 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 2110 spin_unlock(&mib->stats64_lock); 2111 } 2112 2113 static void ksz_get_strings(struct dsa_switch *ds, int port, 2114 u32 stringset, uint8_t *buf) 2115 { 2116 struct ksz_device *dev = ds->priv; 2117 int i; 2118 2119 if (stringset != ETH_SS_STATS) 2120 return; 2121 2122 for (i = 0; i < dev->info->mib_cnt; i++) 2123 ethtool_puts(&buf, dev->info->mib_names[i].string); 2124 } 2125 2126 /** 2127 * ksz_update_port_member - Adjust port forwarding rules based on STP state and 2128 * isolation settings. 2129 * @dev: A pointer to the struct ksz_device representing the device. 2130 * @port: The port number to adjust. 2131 * 2132 * This function dynamically adjusts the port membership configuration for a 2133 * specified port and other device ports, based on Spanning Tree Protocol (STP) 2134 * states and port isolation settings. Each port, including the CPU port, has a 2135 * membership register, represented as a bitfield, where each bit corresponds 2136 * to a port number. A set bit indicates permission to forward frames to that 2137 * port. This function iterates over all ports, updating the membership register 2138 * to reflect current forwarding permissions: 2139 * 2140 * 1. Forwards frames only to ports that are part of the same bridge group and 2141 * in the BR_STATE_FORWARDING state. 2142 * 2. Takes into account the isolation status of ports; ports in the 2143 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward 2144 * frames to each other, even if they are in the same bridge group. 2145 * 3. Ensures that the CPU port is included in the membership based on its 2146 * upstream port configuration, allowing for management and control traffic 2147 * to flow as required. 2148 */ 2149 static void ksz_update_port_member(struct ksz_device *dev, int port) 2150 { 2151 struct ksz_port *p = &dev->ports[port]; 2152 struct dsa_switch *ds = dev->ds; 2153 u8 port_member = 0, cpu_port; 2154 const struct dsa_port *dp; 2155 int i, j; 2156 2157 if (!dsa_is_user_port(ds, port)) 2158 return; 2159 2160 dp = dsa_to_port(ds, port); 2161 cpu_port = BIT(dsa_upstream_port(ds, port)); 2162 2163 for (i = 0; i < ds->num_ports; i++) { 2164 const struct dsa_port *other_dp = dsa_to_port(ds, i); 2165 struct ksz_port *other_p = &dev->ports[i]; 2166 u8 val = 0; 2167 2168 if (!dsa_is_user_port(ds, i)) 2169 continue; 2170 if (port == i) 2171 continue; 2172 if (!dsa_port_bridge_same(dp, other_dp)) 2173 continue; 2174 if (other_p->stp_state != BR_STATE_FORWARDING) 2175 continue; 2176 2177 /* At this point we know that "port" and "other" port [i] are in 2178 * the same bridge group and that "other" port [i] is in 2179 * forwarding stp state. If "port" is also in forwarding stp 2180 * state, we can allow forwarding from port [port] to port [i]. 2181 * Except if both ports are isolated. 2182 */ 2183 if (p->stp_state == BR_STATE_FORWARDING && 2184 !(p->isolated && other_p->isolated)) { 2185 val |= BIT(port); 2186 port_member |= BIT(i); 2187 } 2188 2189 /* Retain port [i]'s relationship to other ports than [port] */ 2190 for (j = 0; j < ds->num_ports; j++) { 2191 const struct dsa_port *third_dp; 2192 struct ksz_port *third_p; 2193 2194 if (j == i) 2195 continue; 2196 if (j == port) 2197 continue; 2198 if (!dsa_is_user_port(ds, j)) 2199 continue; 2200 third_p = &dev->ports[j]; 2201 if (third_p->stp_state != BR_STATE_FORWARDING) 2202 continue; 2203 2204 third_dp = dsa_to_port(ds, j); 2205 2206 /* Now we updating relation of the "other" port [i] to 2207 * the "third" port [j]. We already know that "other" 2208 * port [i] is in forwarding stp state and that "third" 2209 * port [j] is in forwarding stp state too. 2210 * We need to check if "other" port [i] and "third" port 2211 * [j] are in the same bridge group and not isolated 2212 * before allowing forwarding from port [i] to port [j]. 2213 */ 2214 if (dsa_port_bridge_same(other_dp, third_dp) && 2215 !(other_p->isolated && third_p->isolated)) 2216 val |= BIT(j); 2217 } 2218 2219 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 2220 } 2221 2222 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 2223 } 2224 2225 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 2226 { 2227 struct ksz_device *dev = bus->priv; 2228 u16 val; 2229 int ret; 2230 2231 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 2232 if (ret < 0) 2233 return ret; 2234 2235 return val; 2236 } 2237 2238 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 2239 u16 val) 2240 { 2241 struct ksz_device *dev = bus->priv; 2242 2243 return dev->dev_ops->w_phy(dev, addr, regnum, val); 2244 } 2245 2246 /** 2247 * ksz_parent_mdio_read - Read data from a PHY register on the parent MDIO bus. 2248 * @bus: MDIO bus structure. 2249 * @addr: PHY address on the parent MDIO bus. 2250 * @regnum: Register number to read. 2251 * 2252 * This function provides a direct read operation on the parent MDIO bus for 2253 * accessing PHY registers. By bypassing SPI or I2C, it uses the parent MDIO bus 2254 * to retrieve data from the PHY registers at the specified address and register 2255 * number. 2256 * 2257 * Return: Value of the PHY register, or a negative error code on failure. 2258 */ 2259 static int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum) 2260 { 2261 struct ksz_device *dev = bus->priv; 2262 2263 return mdiobus_read_nested(dev->parent_mdio_bus, addr, regnum); 2264 } 2265 2266 /** 2267 * ksz_parent_mdio_write - Write data to a PHY register on the parent MDIO bus. 2268 * @bus: MDIO bus structure. 2269 * @addr: PHY address on the parent MDIO bus. 2270 * @regnum: Register number to write to. 2271 * @val: Value to write to the PHY register. 2272 * 2273 * This function provides a direct write operation on the parent MDIO bus for 2274 * accessing PHY registers. Bypassing SPI or I2C, it uses the parent MDIO bus 2275 * to modify the PHY register values at the specified address. 2276 * 2277 * Return: 0 on success, or a negative error code on failure. 2278 */ 2279 static int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum, 2280 u16 val) 2281 { 2282 struct ksz_device *dev = bus->priv; 2283 2284 return mdiobus_write_nested(dev->parent_mdio_bus, addr, regnum, val); 2285 } 2286 2287 /** 2288 * ksz_phy_addr_to_port - Map a PHY address to the corresponding switch port. 2289 * @dev: Pointer to device structure. 2290 * @addr: PHY address to map to a port. 2291 * 2292 * This function finds the corresponding switch port for a given PHY address by 2293 * iterating over all user ports on the device. It checks if a port's PHY 2294 * address in `phy_addr_map` matches the specified address and if the port 2295 * contains an internal PHY. If a match is found, the index of the port is 2296 * returned. 2297 * 2298 * Return: Port index on success, or -EINVAL if no matching port is found. 2299 */ 2300 static int ksz_phy_addr_to_port(struct ksz_device *dev, int addr) 2301 { 2302 struct dsa_switch *ds = dev->ds; 2303 struct dsa_port *dp; 2304 2305 dsa_switch_for_each_user_port(dp, ds) { 2306 if (dev->info->internal_phy[dp->index] && 2307 dev->phy_addr_map[dp->index] == addr) 2308 return dp->index; 2309 } 2310 2311 return -EINVAL; 2312 } 2313 2314 /** 2315 * ksz_irq_phy_setup - Configure IRQs for PHYs in the KSZ device. 2316 * @dev: Pointer to the KSZ device structure. 2317 * 2318 * Sets up IRQs for each active PHY connected to the KSZ switch by mapping the 2319 * appropriate IRQs for each PHY and assigning them to the `user_mii_bus` in 2320 * the DSA switch structure. Each IRQ is mapped based on the port's IRQ domain. 2321 * 2322 * Return: 0 on success, or a negative error code on failure. 2323 */ 2324 static int ksz_irq_phy_setup(struct ksz_device *dev) 2325 { 2326 struct dsa_switch *ds = dev->ds; 2327 int phy, port; 2328 int irq; 2329 int ret; 2330 2331 for (phy = 0; phy < PHY_MAX_ADDR; phy++) { 2332 if (BIT(phy) & ds->phys_mii_mask) { 2333 port = ksz_phy_addr_to_port(dev, phy); 2334 if (port < 0) { 2335 ret = port; 2336 goto out; 2337 } 2338 2339 irq = irq_find_mapping(dev->ports[port].pirq.domain, 2340 PORT_SRC_PHY_INT); 2341 if (irq < 0) { 2342 ret = irq; 2343 goto out; 2344 } 2345 ds->user_mii_bus->irq[phy] = irq; 2346 } 2347 } 2348 return 0; 2349 out: 2350 while (phy--) 2351 if (BIT(phy) & ds->phys_mii_mask) 2352 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2353 2354 return ret; 2355 } 2356 2357 /** 2358 * ksz_irq_phy_free - Release IRQ mappings for PHYs in the KSZ device. 2359 * @dev: Pointer to the KSZ device structure. 2360 * 2361 * Releases any IRQ mappings previously assigned to active PHYs in the KSZ 2362 * switch by disposing of each mapped IRQ in the `user_mii_bus` structure. 2363 */ 2364 static void ksz_irq_phy_free(struct ksz_device *dev) 2365 { 2366 struct dsa_switch *ds = dev->ds; 2367 int phy; 2368 2369 for (phy = 0; phy < PHY_MAX_ADDR; phy++) 2370 if (BIT(phy) & ds->phys_mii_mask) 2371 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2372 } 2373 2374 /** 2375 * ksz_parse_dt_phy_config - Parse and validate PHY configuration from DT 2376 * @dev: pointer to the KSZ device structure 2377 * @bus: pointer to the MII bus structure 2378 * @mdio_np: pointer to the MDIO node in the device tree 2379 * 2380 * This function parses and validates PHY configurations for each user port 2381 * defined in the device tree for a KSZ switch device. It verifies that the 2382 * `phy-handle` properties are correctly set and that the internal PHYs match 2383 * expected addresses and parent nodes. Sets up the PHY mask in the MII bus if 2384 * all validations pass. Logs error messages for any mismatches or missing data. 2385 * 2386 * Return: 0 on success, or a negative error code on failure. 2387 */ 2388 static int ksz_parse_dt_phy_config(struct ksz_device *dev, struct mii_bus *bus, 2389 struct device_node *mdio_np) 2390 { 2391 struct device_node *phy_node, *phy_parent_node; 2392 bool phys_are_valid = true; 2393 struct dsa_port *dp; 2394 u32 phy_addr; 2395 int ret; 2396 2397 dsa_switch_for_each_user_port(dp, dev->ds) { 2398 if (!dev->info->internal_phy[dp->index]) 2399 continue; 2400 2401 phy_node = of_parse_phandle(dp->dn, "phy-handle", 0); 2402 if (!phy_node) { 2403 dev_err(dev->dev, "failed to parse phy-handle for port %d.\n", 2404 dp->index); 2405 phys_are_valid = false; 2406 continue; 2407 } 2408 2409 phy_parent_node = of_get_parent(phy_node); 2410 if (!phy_parent_node) { 2411 dev_err(dev->dev, "failed to get PHY-parent node for port %d\n", 2412 dp->index); 2413 phys_are_valid = false; 2414 } else if (phy_parent_node != mdio_np) { 2415 dev_err(dev->dev, "PHY-parent node mismatch for port %d, expected %pOF, got %pOF\n", 2416 dp->index, mdio_np, phy_parent_node); 2417 phys_are_valid = false; 2418 } else { 2419 ret = of_property_read_u32(phy_node, "reg", &phy_addr); 2420 if (ret < 0) { 2421 dev_err(dev->dev, "failed to read PHY address for port %d. Error %d\n", 2422 dp->index, ret); 2423 phys_are_valid = false; 2424 } else if (phy_addr != dev->phy_addr_map[dp->index]) { 2425 dev_err(dev->dev, "PHY address mismatch for port %d, expected 0x%x, got 0x%x\n", 2426 dp->index, dev->phy_addr_map[dp->index], 2427 phy_addr); 2428 phys_are_valid = false; 2429 } else { 2430 bus->phy_mask |= BIT(phy_addr); 2431 } 2432 } 2433 2434 of_node_put(phy_node); 2435 of_node_put(phy_parent_node); 2436 } 2437 2438 if (!phys_are_valid) 2439 return -EINVAL; 2440 2441 return 0; 2442 } 2443 2444 /** 2445 * ksz_mdio_register - Register and configure the MDIO bus for the KSZ device. 2446 * @dev: Pointer to the KSZ device structure. 2447 * 2448 * This function sets up and registers an MDIO bus for the KSZ switch device, 2449 * allowing access to its internal PHYs. If the device supports side MDIO, 2450 * the function will configure the external MDIO controller specified by the 2451 * "mdio-parent-bus" device tree property to directly manage internal PHYs. 2452 * Otherwise, SPI or I2C access is set up for PHY access. 2453 * 2454 * Return: 0 on success, or a negative error code on failure. 2455 */ 2456 static int ksz_mdio_register(struct ksz_device *dev) 2457 { 2458 struct device_node *parent_bus_node; 2459 struct mii_bus *parent_bus = NULL; 2460 struct dsa_switch *ds = dev->ds; 2461 struct device_node *mdio_np; 2462 struct mii_bus *bus; 2463 int ret, i; 2464 2465 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 2466 if (!mdio_np) 2467 return 0; 2468 2469 parent_bus_node = of_parse_phandle(mdio_np, "mdio-parent-bus", 0); 2470 if (parent_bus_node && !dev->info->phy_side_mdio_supported) { 2471 dev_err(dev->dev, "Side MDIO bus is not supported for this HW, ignoring 'mdio-parent-bus' property.\n"); 2472 ret = -EINVAL; 2473 2474 goto put_mdio_node; 2475 } else if (parent_bus_node) { 2476 parent_bus = of_mdio_find_bus(parent_bus_node); 2477 if (!parent_bus) { 2478 ret = -EPROBE_DEFER; 2479 2480 goto put_mdio_node; 2481 } 2482 2483 dev->parent_mdio_bus = parent_bus; 2484 } 2485 2486 bus = devm_mdiobus_alloc(ds->dev); 2487 if (!bus) { 2488 ret = -ENOMEM; 2489 goto put_mdio_node; 2490 } 2491 2492 if (dev->dev_ops->mdio_bus_preinit) { 2493 ret = dev->dev_ops->mdio_bus_preinit(dev, !!parent_bus); 2494 if (ret) 2495 goto put_mdio_node; 2496 } 2497 2498 if (dev->dev_ops->create_phy_addr_map) { 2499 ret = dev->dev_ops->create_phy_addr_map(dev, !!parent_bus); 2500 if (ret) 2501 goto put_mdio_node; 2502 } else { 2503 for (i = 0; i < dev->info->port_cnt; i++) 2504 dev->phy_addr_map[i] = i; 2505 } 2506 2507 bus->priv = dev; 2508 if (parent_bus) { 2509 bus->read = ksz_parent_mdio_read; 2510 bus->write = ksz_parent_mdio_write; 2511 bus->name = "KSZ side MDIO"; 2512 snprintf(bus->id, MII_BUS_ID_SIZE, "ksz-side-mdio-%d", 2513 ds->index); 2514 } else { 2515 bus->read = ksz_sw_mdio_read; 2516 bus->write = ksz_sw_mdio_write; 2517 bus->name = "ksz user smi"; 2518 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 2519 } 2520 2521 ret = ksz_parse_dt_phy_config(dev, bus, mdio_np); 2522 if (ret) 2523 goto put_mdio_node; 2524 2525 ds->phys_mii_mask = bus->phy_mask; 2526 bus->parent = ds->dev; 2527 2528 ds->user_mii_bus = bus; 2529 2530 if (dev->irq > 0) { 2531 ret = ksz_irq_phy_setup(dev); 2532 if (ret) 2533 goto put_mdio_node; 2534 } 2535 2536 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 2537 if (ret) { 2538 dev_err(ds->dev, "unable to register MDIO bus %s\n", 2539 bus->id); 2540 if (dev->irq > 0) 2541 ksz_irq_phy_free(dev); 2542 } 2543 2544 put_mdio_node: 2545 of_node_put(mdio_np); 2546 of_node_put(parent_bus_node); 2547 2548 return ret; 2549 } 2550 2551 static void ksz_irq_mask(struct irq_data *d) 2552 { 2553 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2554 2555 kirq->masked |= BIT(d->hwirq); 2556 } 2557 2558 static void ksz_irq_unmask(struct irq_data *d) 2559 { 2560 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2561 2562 kirq->masked &= ~BIT(d->hwirq); 2563 } 2564 2565 static void ksz_irq_bus_lock(struct irq_data *d) 2566 { 2567 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2568 2569 mutex_lock(&kirq->dev->lock_irq); 2570 } 2571 2572 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 2573 { 2574 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2575 struct ksz_device *dev = kirq->dev; 2576 int ret; 2577 2578 ret = ksz_write8(dev, kirq->reg_mask, kirq->masked); 2579 if (ret) 2580 dev_err(dev->dev, "failed to change IRQ mask\n"); 2581 2582 mutex_unlock(&dev->lock_irq); 2583 } 2584 2585 static const struct irq_chip ksz_irq_chip = { 2586 .name = "ksz-irq", 2587 .irq_mask = ksz_irq_mask, 2588 .irq_unmask = ksz_irq_unmask, 2589 .irq_bus_lock = ksz_irq_bus_lock, 2590 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 2591 }; 2592 2593 static int ksz_irq_domain_map(struct irq_domain *d, 2594 unsigned int irq, irq_hw_number_t hwirq) 2595 { 2596 irq_set_chip_data(irq, d->host_data); 2597 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 2598 irq_set_noprobe(irq); 2599 2600 return 0; 2601 } 2602 2603 static const struct irq_domain_ops ksz_irq_domain_ops = { 2604 .map = ksz_irq_domain_map, 2605 .xlate = irq_domain_xlate_twocell, 2606 }; 2607 2608 static void ksz_irq_free(struct ksz_irq *kirq) 2609 { 2610 int irq, virq; 2611 2612 free_irq(kirq->irq_num, kirq); 2613 2614 for (irq = 0; irq < kirq->nirqs; irq++) { 2615 virq = irq_find_mapping(kirq->domain, irq); 2616 irq_dispose_mapping(virq); 2617 } 2618 2619 irq_domain_remove(kirq->domain); 2620 } 2621 2622 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 2623 { 2624 struct ksz_irq *kirq = dev_id; 2625 unsigned int nhandled = 0; 2626 struct ksz_device *dev; 2627 unsigned int sub_irq; 2628 u8 data; 2629 int ret; 2630 u8 n; 2631 2632 dev = kirq->dev; 2633 2634 /* Read interrupt status register */ 2635 ret = ksz_read8(dev, kirq->reg_status, &data); 2636 if (ret) 2637 goto out; 2638 2639 for (n = 0; n < kirq->nirqs; ++n) { 2640 if (data & BIT(n)) { 2641 sub_irq = irq_find_mapping(kirq->domain, n); 2642 handle_nested_irq(sub_irq); 2643 ++nhandled; 2644 } 2645 } 2646 out: 2647 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2648 } 2649 2650 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 2651 { 2652 int ret, n; 2653 2654 kirq->dev = dev; 2655 kirq->masked = ~0; 2656 2657 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0, 2658 &ksz_irq_domain_ops, kirq); 2659 if (!kirq->domain) 2660 return -ENOMEM; 2661 2662 for (n = 0; n < kirq->nirqs; n++) 2663 irq_create_mapping(kirq->domain, n); 2664 2665 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2666 IRQF_ONESHOT, kirq->name, kirq); 2667 if (ret) 2668 goto out; 2669 2670 return 0; 2671 2672 out: 2673 ksz_irq_free(kirq); 2674 2675 return ret; 2676 } 2677 2678 static int ksz_girq_setup(struct ksz_device *dev) 2679 { 2680 struct ksz_irq *girq = &dev->girq; 2681 2682 girq->nirqs = dev->info->port_cnt; 2683 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2684 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2685 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2686 2687 girq->irq_num = dev->irq; 2688 2689 return ksz_irq_common_setup(dev, girq); 2690 } 2691 2692 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2693 { 2694 struct ksz_irq *pirq = &dev->ports[p].pirq; 2695 2696 pirq->nirqs = dev->info->port_nirqs; 2697 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2698 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2699 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2700 2701 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2702 if (pirq->irq_num < 0) 2703 return pirq->irq_num; 2704 2705 return ksz_irq_common_setup(dev, pirq); 2706 } 2707 2708 static int ksz_parse_drive_strength(struct ksz_device *dev); 2709 2710 static int ksz_setup(struct dsa_switch *ds) 2711 { 2712 struct ksz_device *dev = ds->priv; 2713 struct dsa_port *dp; 2714 struct ksz_port *p; 2715 const u16 *regs; 2716 int ret; 2717 2718 regs = dev->info->regs; 2719 2720 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2721 dev->info->num_vlans, GFP_KERNEL); 2722 if (!dev->vlan_cache) 2723 return -ENOMEM; 2724 2725 ret = dev->dev_ops->reset(dev); 2726 if (ret) { 2727 dev_err(ds->dev, "failed to reset switch\n"); 2728 return ret; 2729 } 2730 2731 ret = ksz_parse_drive_strength(dev); 2732 if (ret) 2733 return ret; 2734 2735 /* set broadcast storm protection 10% rate */ 2736 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2737 BROADCAST_STORM_RATE, 2738 (BROADCAST_STORM_VALUE * 2739 BROADCAST_STORM_PROT_RATE) / 100); 2740 2741 dev->dev_ops->config_cpu_port(ds); 2742 2743 dev->dev_ops->enable_stp_addr(dev); 2744 2745 ds->num_tx_queues = dev->info->num_tx_queues; 2746 2747 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 2748 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2749 2750 ksz_init_mib_timer(dev); 2751 2752 ds->configure_vlan_while_not_filtering = false; 2753 ds->dscp_prio_mapping_is_global = true; 2754 2755 if (dev->dev_ops->setup) { 2756 ret = dev->dev_ops->setup(ds); 2757 if (ret) 2758 return ret; 2759 } 2760 2761 /* Start with learning disabled on standalone user ports, and enabled 2762 * on the CPU port. In lack of other finer mechanisms, learning on the 2763 * CPU port will avoid flooding bridge local addresses on the network 2764 * in some cases. 2765 */ 2766 p = &dev->ports[dev->cpu_port]; 2767 p->learning = true; 2768 2769 if (dev->irq > 0) { 2770 ret = ksz_girq_setup(dev); 2771 if (ret) 2772 return ret; 2773 2774 dsa_switch_for_each_user_port(dp, dev->ds) { 2775 ret = ksz_pirq_setup(dev, dp->index); 2776 if (ret) 2777 goto out_girq; 2778 2779 ret = ksz_ptp_irq_setup(ds, dp->index); 2780 if (ret) 2781 goto out_pirq; 2782 } 2783 } 2784 2785 ret = ksz_ptp_clock_register(ds); 2786 if (ret) { 2787 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret); 2788 goto out_ptpirq; 2789 } 2790 2791 ret = ksz_mdio_register(dev); 2792 if (ret < 0) { 2793 dev_err(dev->dev, "failed to register the mdio"); 2794 goto out_ptp_clock_unregister; 2795 } 2796 2797 ret = ksz_dcb_init(dev); 2798 if (ret) 2799 goto out_ptp_clock_unregister; 2800 2801 /* start switch */ 2802 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 2803 SW_START, SW_START); 2804 2805 return 0; 2806 2807 out_ptp_clock_unregister: 2808 ksz_ptp_clock_unregister(ds); 2809 out_ptpirq: 2810 if (dev->irq > 0) 2811 dsa_switch_for_each_user_port(dp, dev->ds) 2812 ksz_ptp_irq_free(ds, dp->index); 2813 out_pirq: 2814 if (dev->irq > 0) 2815 dsa_switch_for_each_user_port(dp, dev->ds) 2816 ksz_irq_free(&dev->ports[dp->index].pirq); 2817 out_girq: 2818 if (dev->irq > 0) 2819 ksz_irq_free(&dev->girq); 2820 2821 return ret; 2822 } 2823 2824 static void ksz_teardown(struct dsa_switch *ds) 2825 { 2826 struct ksz_device *dev = ds->priv; 2827 struct dsa_port *dp; 2828 2829 ksz_ptp_clock_unregister(ds); 2830 2831 if (dev->irq > 0) { 2832 dsa_switch_for_each_user_port(dp, dev->ds) { 2833 ksz_ptp_irq_free(ds, dp->index); 2834 2835 ksz_irq_free(&dev->ports[dp->index].pirq); 2836 } 2837 2838 ksz_irq_free(&dev->girq); 2839 } 2840 2841 if (dev->dev_ops->teardown) 2842 dev->dev_ops->teardown(ds); 2843 } 2844 2845 static void port_r_cnt(struct ksz_device *dev, int port) 2846 { 2847 struct ksz_port_mib *mib = &dev->ports[port].mib; 2848 u64 *dropped; 2849 2850 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2851 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2852 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2853 &mib->counters[mib->cnt_ptr]); 2854 ++mib->cnt_ptr; 2855 } 2856 2857 /* last one in storage */ 2858 dropped = &mib->counters[dev->info->mib_cnt]; 2859 2860 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2861 while (mib->cnt_ptr < dev->info->mib_cnt) { 2862 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2863 dropped, &mib->counters[mib->cnt_ptr]); 2864 ++mib->cnt_ptr; 2865 } 2866 mib->cnt_ptr = 0; 2867 } 2868 2869 static void ksz_mib_read_work(struct work_struct *work) 2870 { 2871 struct ksz_device *dev = container_of(work, struct ksz_device, 2872 mib_read.work); 2873 struct ksz_port_mib *mib; 2874 struct ksz_port *p; 2875 int i; 2876 2877 for (i = 0; i < dev->info->port_cnt; i++) { 2878 if (dsa_is_unused_port(dev->ds, i)) 2879 continue; 2880 2881 p = &dev->ports[i]; 2882 mib = &p->mib; 2883 mutex_lock(&mib->cnt_mutex); 2884 2885 /* Only read MIB counters when the port is told to do. 2886 * If not, read only dropped counters when link is not up. 2887 */ 2888 if (!p->read) { 2889 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 2890 2891 if (!netif_carrier_ok(dp->user)) 2892 mib->cnt_ptr = dev->info->reg_mib_cnt; 2893 } 2894 port_r_cnt(dev, i); 2895 p->read = false; 2896 2897 if (dev->dev_ops->r_mib_stat64) 2898 dev->dev_ops->r_mib_stat64(dev, i); 2899 2900 mutex_unlock(&mib->cnt_mutex); 2901 } 2902 2903 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 2904 } 2905 2906 void ksz_init_mib_timer(struct ksz_device *dev) 2907 { 2908 int i; 2909 2910 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 2911 2912 for (i = 0; i < dev->info->port_cnt; i++) { 2913 struct ksz_port_mib *mib = &dev->ports[i].mib; 2914 2915 dev->dev_ops->port_init_cnt(dev, i); 2916 2917 mib->cnt_ptr = 0; 2918 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 2919 } 2920 } 2921 2922 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 2923 { 2924 struct ksz_device *dev = ds->priv; 2925 u16 val = 0xffff; 2926 int ret; 2927 2928 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 2929 if (ret) 2930 return ret; 2931 2932 return val; 2933 } 2934 2935 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 2936 { 2937 struct ksz_device *dev = ds->priv; 2938 int ret; 2939 2940 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 2941 if (ret) 2942 return ret; 2943 2944 return 0; 2945 } 2946 2947 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 2948 { 2949 struct ksz_device *dev = ds->priv; 2950 2951 switch (dev->chip_id) { 2952 case KSZ88X3_CHIP_ID: 2953 /* Silicon Errata Sheet (DS80000830A): 2954 * Port 1 does not work with LinkMD Cable-Testing. 2955 * Port 1 does not respond to received PAUSE control frames. 2956 */ 2957 if (!port) 2958 return MICREL_KSZ8_P1_ERRATA; 2959 break; 2960 case KSZ8567_CHIP_ID: 2961 /* KSZ8567R Errata DS80000752C Module 4 */ 2962 case KSZ8765_CHIP_ID: 2963 case KSZ8794_CHIP_ID: 2964 case KSZ8795_CHIP_ID: 2965 /* KSZ879x/KSZ877x/KSZ876x Errata DS80000687C Module 2 */ 2966 case KSZ9477_CHIP_ID: 2967 /* KSZ9477S Errata DS80000754A Module 4 */ 2968 case KSZ9567_CHIP_ID: 2969 /* KSZ9567S Errata DS80000756A Module 4 */ 2970 case KSZ9896_CHIP_ID: 2971 /* KSZ9896C Errata DS80000757A Module 3 */ 2972 case KSZ9897_CHIP_ID: 2973 /* KSZ9897R Errata DS80000758C Module 4 */ 2974 /* Energy Efficient Ethernet (EEE) feature select must be manually disabled 2975 * The EEE feature is enabled by default, but it is not fully 2976 * operational. It must be manually disabled through register 2977 * controls. If not disabled, the PHY ports can auto-negotiate 2978 * to enable EEE, and this feature can cause link drops when 2979 * linked to another device supporting EEE. 2980 * 2981 * The same item appears in the errata for all switches above. 2982 */ 2983 return MICREL_NO_EEE; 2984 } 2985 2986 return 0; 2987 } 2988 2989 static void ksz_phylink_mac_link_down(struct phylink_config *config, 2990 unsigned int mode, 2991 phy_interface_t interface) 2992 { 2993 struct dsa_port *dp = dsa_phylink_to_port(config); 2994 struct ksz_device *dev = dp->ds->priv; 2995 2996 /* Read all MIB counters when the link is going down. */ 2997 dev->ports[dp->index].read = true; 2998 /* timer started */ 2999 if (dev->mib_read_interval) 3000 schedule_delayed_work(&dev->mib_read, 0); 3001 } 3002 3003 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 3004 { 3005 struct ksz_device *dev = ds->priv; 3006 3007 if (sset != ETH_SS_STATS) 3008 return 0; 3009 3010 return dev->info->mib_cnt; 3011 } 3012 3013 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 3014 uint64_t *buf) 3015 { 3016 const struct dsa_port *dp = dsa_to_port(ds, port); 3017 struct ksz_device *dev = ds->priv; 3018 struct ksz_port_mib *mib; 3019 3020 mib = &dev->ports[port].mib; 3021 mutex_lock(&mib->cnt_mutex); 3022 3023 /* Only read dropped counters if no link. */ 3024 if (!netif_carrier_ok(dp->user)) 3025 mib->cnt_ptr = dev->info->reg_mib_cnt; 3026 port_r_cnt(dev, port); 3027 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 3028 mutex_unlock(&mib->cnt_mutex); 3029 } 3030 3031 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 3032 struct dsa_bridge bridge, 3033 bool *tx_fwd_offload, 3034 struct netlink_ext_ack *extack) 3035 { 3036 /* port_stp_state_set() will be called after to put the port in 3037 * appropriate state so there is no need to do anything. 3038 */ 3039 3040 return 0; 3041 } 3042 3043 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 3044 struct dsa_bridge bridge) 3045 { 3046 /* port_stp_state_set() will be called after to put the port in 3047 * forwarding state so there is no need to do anything. 3048 */ 3049 } 3050 3051 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 3052 { 3053 struct ksz_device *dev = ds->priv; 3054 3055 dev->dev_ops->flush_dyn_mac_table(dev, port); 3056 } 3057 3058 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 3059 { 3060 struct ksz_device *dev = ds->priv; 3061 3062 if (!dev->dev_ops->set_ageing_time) 3063 return -EOPNOTSUPP; 3064 3065 return dev->dev_ops->set_ageing_time(dev, msecs); 3066 } 3067 3068 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 3069 const unsigned char *addr, u16 vid, 3070 struct dsa_db db) 3071 { 3072 struct ksz_device *dev = ds->priv; 3073 3074 if (!dev->dev_ops->fdb_add) 3075 return -EOPNOTSUPP; 3076 3077 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 3078 } 3079 3080 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 3081 const unsigned char *addr, 3082 u16 vid, struct dsa_db db) 3083 { 3084 struct ksz_device *dev = ds->priv; 3085 3086 if (!dev->dev_ops->fdb_del) 3087 return -EOPNOTSUPP; 3088 3089 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 3090 } 3091 3092 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 3093 dsa_fdb_dump_cb_t *cb, void *data) 3094 { 3095 struct ksz_device *dev = ds->priv; 3096 3097 if (!dev->dev_ops->fdb_dump) 3098 return -EOPNOTSUPP; 3099 3100 return dev->dev_ops->fdb_dump(dev, port, cb, data); 3101 } 3102 3103 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 3104 const struct switchdev_obj_port_mdb *mdb, 3105 struct dsa_db db) 3106 { 3107 struct ksz_device *dev = ds->priv; 3108 3109 if (!dev->dev_ops->mdb_add) 3110 return -EOPNOTSUPP; 3111 3112 return dev->dev_ops->mdb_add(dev, port, mdb, db); 3113 } 3114 3115 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 3116 const struct switchdev_obj_port_mdb *mdb, 3117 struct dsa_db db) 3118 { 3119 struct ksz_device *dev = ds->priv; 3120 3121 if (!dev->dev_ops->mdb_del) 3122 return -EOPNOTSUPP; 3123 3124 return dev->dev_ops->mdb_del(dev, port, mdb, db); 3125 } 3126 3127 static int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev, 3128 int port) 3129 { 3130 u32 queue_map = 0; 3131 int ipm; 3132 3133 for (ipm = 0; ipm < dev->info->num_ipms; ipm++) { 3134 int queue; 3135 3136 /* Traffic Type (TT) is corresponding to the Internal Priority 3137 * Map (IPM) in the switch. Traffic Class (TC) is 3138 * corresponding to the queue in the switch. 3139 */ 3140 queue = ieee8021q_tt_to_tc(ipm, dev->info->num_tx_queues); 3141 if (queue < 0) 3142 return queue; 3143 3144 queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S); 3145 } 3146 3147 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3148 } 3149 3150 static int ksz_port_setup(struct dsa_switch *ds, int port) 3151 { 3152 struct ksz_device *dev = ds->priv; 3153 int ret; 3154 3155 if (!dsa_is_user_port(ds, port)) 3156 return 0; 3157 3158 /* setup user port */ 3159 dev->dev_ops->port_setup(dev, port, false); 3160 3161 if (!is_ksz8(dev)) { 3162 ret = ksz9477_set_default_prio_queue_mapping(dev, port); 3163 if (ret) 3164 return ret; 3165 } 3166 3167 /* port_stp_state_set() will be called after to enable the port so 3168 * there is no need to do anything. 3169 */ 3170 3171 return ksz_dcb_init_port(dev, port); 3172 } 3173 3174 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 3175 { 3176 struct ksz_device *dev = ds->priv; 3177 struct ksz_port *p; 3178 const u16 *regs; 3179 u8 data; 3180 3181 regs = dev->info->regs; 3182 3183 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 3184 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 3185 3186 p = &dev->ports[port]; 3187 3188 switch (state) { 3189 case BR_STATE_DISABLED: 3190 data |= PORT_LEARN_DISABLE; 3191 break; 3192 case BR_STATE_LISTENING: 3193 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 3194 break; 3195 case BR_STATE_LEARNING: 3196 data |= PORT_RX_ENABLE; 3197 if (!p->learning) 3198 data |= PORT_LEARN_DISABLE; 3199 break; 3200 case BR_STATE_FORWARDING: 3201 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 3202 if (!p->learning) 3203 data |= PORT_LEARN_DISABLE; 3204 break; 3205 case BR_STATE_BLOCKING: 3206 data |= PORT_LEARN_DISABLE; 3207 break; 3208 default: 3209 dev_err(ds->dev, "invalid STP state: %d\n", state); 3210 return; 3211 } 3212 3213 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 3214 3215 p->stp_state = state; 3216 3217 ksz_update_port_member(dev, port); 3218 } 3219 3220 static void ksz_port_teardown(struct dsa_switch *ds, int port) 3221 { 3222 struct ksz_device *dev = ds->priv; 3223 3224 switch (dev->chip_id) { 3225 case KSZ8563_CHIP_ID: 3226 case KSZ8567_CHIP_ID: 3227 case KSZ9477_CHIP_ID: 3228 case KSZ9563_CHIP_ID: 3229 case KSZ9567_CHIP_ID: 3230 case KSZ9893_CHIP_ID: 3231 case KSZ9896_CHIP_ID: 3232 case KSZ9897_CHIP_ID: 3233 if (dsa_is_user_port(ds, port)) 3234 ksz9477_port_acl_free(dev, port); 3235 } 3236 } 3237 3238 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 3239 struct switchdev_brport_flags flags, 3240 struct netlink_ext_ack *extack) 3241 { 3242 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED)) 3243 return -EINVAL; 3244 3245 return 0; 3246 } 3247 3248 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 3249 struct switchdev_brport_flags flags, 3250 struct netlink_ext_ack *extack) 3251 { 3252 struct ksz_device *dev = ds->priv; 3253 struct ksz_port *p = &dev->ports[port]; 3254 3255 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) { 3256 if (flags.mask & BR_LEARNING) 3257 p->learning = !!(flags.val & BR_LEARNING); 3258 3259 if (flags.mask & BR_ISOLATED) 3260 p->isolated = !!(flags.val & BR_ISOLATED); 3261 3262 /* Make the change take effect immediately */ 3263 ksz_port_stp_state_set(ds, port, p->stp_state); 3264 } 3265 3266 return 0; 3267 } 3268 3269 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 3270 int port, 3271 enum dsa_tag_protocol mp) 3272 { 3273 struct ksz_device *dev = ds->priv; 3274 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 3275 3276 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev)) 3277 proto = DSA_TAG_PROTO_KSZ8795; 3278 3279 if (dev->chip_id == KSZ88X3_CHIP_ID || 3280 dev->chip_id == KSZ8563_CHIP_ID || 3281 dev->chip_id == KSZ9893_CHIP_ID || 3282 dev->chip_id == KSZ9563_CHIP_ID) 3283 proto = DSA_TAG_PROTO_KSZ9893; 3284 3285 if (dev->chip_id == KSZ8567_CHIP_ID || 3286 dev->chip_id == KSZ9477_CHIP_ID || 3287 dev->chip_id == KSZ9896_CHIP_ID || 3288 dev->chip_id == KSZ9897_CHIP_ID || 3289 dev->chip_id == KSZ9567_CHIP_ID) 3290 proto = DSA_TAG_PROTO_KSZ9477; 3291 3292 if (is_lan937x(dev)) 3293 proto = DSA_TAG_PROTO_LAN937X; 3294 3295 return proto; 3296 } 3297 3298 static int ksz_connect_tag_protocol(struct dsa_switch *ds, 3299 enum dsa_tag_protocol proto) 3300 { 3301 struct ksz_tagger_data *tagger_data; 3302 3303 switch (proto) { 3304 case DSA_TAG_PROTO_KSZ8795: 3305 return 0; 3306 case DSA_TAG_PROTO_KSZ9893: 3307 case DSA_TAG_PROTO_KSZ9477: 3308 case DSA_TAG_PROTO_LAN937X: 3309 tagger_data = ksz_tagger_data(ds); 3310 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 3311 return 0; 3312 default: 3313 return -EPROTONOSUPPORT; 3314 } 3315 } 3316 3317 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 3318 bool flag, struct netlink_ext_ack *extack) 3319 { 3320 struct ksz_device *dev = ds->priv; 3321 3322 if (!dev->dev_ops->vlan_filtering) 3323 return -EOPNOTSUPP; 3324 3325 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 3326 } 3327 3328 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 3329 const struct switchdev_obj_port_vlan *vlan, 3330 struct netlink_ext_ack *extack) 3331 { 3332 struct ksz_device *dev = ds->priv; 3333 3334 if (!dev->dev_ops->vlan_add) 3335 return -EOPNOTSUPP; 3336 3337 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 3338 } 3339 3340 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 3341 const struct switchdev_obj_port_vlan *vlan) 3342 { 3343 struct ksz_device *dev = ds->priv; 3344 3345 if (!dev->dev_ops->vlan_del) 3346 return -EOPNOTSUPP; 3347 3348 return dev->dev_ops->vlan_del(dev, port, vlan); 3349 } 3350 3351 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 3352 struct dsa_mall_mirror_tc_entry *mirror, 3353 bool ingress, struct netlink_ext_ack *extack) 3354 { 3355 struct ksz_device *dev = ds->priv; 3356 3357 if (!dev->dev_ops->mirror_add) 3358 return -EOPNOTSUPP; 3359 3360 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 3361 } 3362 3363 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 3364 struct dsa_mall_mirror_tc_entry *mirror) 3365 { 3366 struct ksz_device *dev = ds->priv; 3367 3368 if (dev->dev_ops->mirror_del) 3369 dev->dev_ops->mirror_del(dev, port, mirror); 3370 } 3371 3372 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 3373 { 3374 struct ksz_device *dev = ds->priv; 3375 3376 if (!dev->dev_ops->change_mtu) 3377 return -EOPNOTSUPP; 3378 3379 return dev->dev_ops->change_mtu(dev, port, mtu); 3380 } 3381 3382 static int ksz_max_mtu(struct dsa_switch *ds, int port) 3383 { 3384 struct ksz_device *dev = ds->priv; 3385 3386 switch (dev->chip_id) { 3387 case KSZ8795_CHIP_ID: 3388 case KSZ8794_CHIP_ID: 3389 case KSZ8765_CHIP_ID: 3390 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3391 case KSZ88X3_CHIP_ID: 3392 case KSZ8864_CHIP_ID: 3393 case KSZ8895_CHIP_ID: 3394 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3395 case KSZ8563_CHIP_ID: 3396 case KSZ8567_CHIP_ID: 3397 case KSZ9477_CHIP_ID: 3398 case KSZ9563_CHIP_ID: 3399 case KSZ9567_CHIP_ID: 3400 case KSZ9893_CHIP_ID: 3401 case KSZ9896_CHIP_ID: 3402 case KSZ9897_CHIP_ID: 3403 case LAN9370_CHIP_ID: 3404 case LAN9371_CHIP_ID: 3405 case LAN9372_CHIP_ID: 3406 case LAN9373_CHIP_ID: 3407 case LAN9374_CHIP_ID: 3408 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3409 } 3410 3411 return -EOPNOTSUPP; 3412 } 3413 3414 static int ksz_validate_eee(struct dsa_switch *ds, int port) 3415 { 3416 struct ksz_device *dev = ds->priv; 3417 3418 if (!dev->info->internal_phy[port]) 3419 return -EOPNOTSUPP; 3420 3421 switch (dev->chip_id) { 3422 case KSZ8563_CHIP_ID: 3423 case KSZ8567_CHIP_ID: 3424 case KSZ9477_CHIP_ID: 3425 case KSZ9563_CHIP_ID: 3426 case KSZ9567_CHIP_ID: 3427 case KSZ9893_CHIP_ID: 3428 case KSZ9896_CHIP_ID: 3429 case KSZ9897_CHIP_ID: 3430 return 0; 3431 } 3432 3433 return -EOPNOTSUPP; 3434 } 3435 3436 static int ksz_get_mac_eee(struct dsa_switch *ds, int port, 3437 struct ethtool_keee *e) 3438 { 3439 int ret; 3440 3441 ret = ksz_validate_eee(ds, port); 3442 if (ret) 3443 return ret; 3444 3445 /* There is no documented control of Tx LPI configuration. */ 3446 e->tx_lpi_enabled = true; 3447 3448 /* There is no documented control of Tx LPI timer. According to tests 3449 * Tx LPI timer seems to be set by default to minimal value. 3450 */ 3451 e->tx_lpi_timer = 0; 3452 3453 return 0; 3454 } 3455 3456 static int ksz_set_mac_eee(struct dsa_switch *ds, int port, 3457 struct ethtool_keee *e) 3458 { 3459 struct ksz_device *dev = ds->priv; 3460 int ret; 3461 3462 ret = ksz_validate_eee(ds, port); 3463 if (ret) 3464 return ret; 3465 3466 if (!e->tx_lpi_enabled) { 3467 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 3468 return -EINVAL; 3469 } 3470 3471 if (e->tx_lpi_timer) { 3472 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 3473 return -EINVAL; 3474 } 3475 3476 return 0; 3477 } 3478 3479 static void ksz_set_xmii(struct ksz_device *dev, int port, 3480 phy_interface_t interface) 3481 { 3482 const u8 *bitval = dev->info->xmii_ctrl1; 3483 struct ksz_port *p = &dev->ports[port]; 3484 const u16 *regs = dev->info->regs; 3485 u8 data8; 3486 3487 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3488 3489 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 3490 P_RGMII_ID_EG_ENABLE); 3491 3492 switch (interface) { 3493 case PHY_INTERFACE_MODE_MII: 3494 data8 |= bitval[P_MII_SEL]; 3495 break; 3496 case PHY_INTERFACE_MODE_RMII: 3497 data8 |= bitval[P_RMII_SEL]; 3498 break; 3499 case PHY_INTERFACE_MODE_GMII: 3500 data8 |= bitval[P_GMII_SEL]; 3501 break; 3502 case PHY_INTERFACE_MODE_RGMII: 3503 case PHY_INTERFACE_MODE_RGMII_ID: 3504 case PHY_INTERFACE_MODE_RGMII_TXID: 3505 case PHY_INTERFACE_MODE_RGMII_RXID: 3506 data8 |= bitval[P_RGMII_SEL]; 3507 /* On KSZ9893, disable RGMII in-band status support */ 3508 if (dev->chip_id == KSZ9893_CHIP_ID || 3509 dev->chip_id == KSZ8563_CHIP_ID || 3510 dev->chip_id == KSZ9563_CHIP_ID || 3511 is_lan937x(dev)) 3512 data8 &= ~P_MII_MAC_MODE; 3513 break; 3514 default: 3515 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 3516 phy_modes(interface), port); 3517 return; 3518 } 3519 3520 if (p->rgmii_tx_val) 3521 data8 |= P_RGMII_ID_EG_ENABLE; 3522 3523 if (p->rgmii_rx_val) 3524 data8 |= P_RGMII_ID_IG_ENABLE; 3525 3526 /* Write the updated value */ 3527 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3528 } 3529 3530 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 3531 { 3532 const u8 *bitval = dev->info->xmii_ctrl1; 3533 const u16 *regs = dev->info->regs; 3534 phy_interface_t interface; 3535 u8 data8; 3536 u8 val; 3537 3538 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3539 3540 val = FIELD_GET(P_MII_SEL_M, data8); 3541 3542 if (val == bitval[P_MII_SEL]) { 3543 if (gbit) 3544 interface = PHY_INTERFACE_MODE_GMII; 3545 else 3546 interface = PHY_INTERFACE_MODE_MII; 3547 } else if (val == bitval[P_RMII_SEL]) { 3548 interface = PHY_INTERFACE_MODE_RMII; 3549 } else { 3550 interface = PHY_INTERFACE_MODE_RGMII; 3551 if (data8 & P_RGMII_ID_EG_ENABLE) 3552 interface = PHY_INTERFACE_MODE_RGMII_TXID; 3553 if (data8 & P_RGMII_ID_IG_ENABLE) { 3554 interface = PHY_INTERFACE_MODE_RGMII_RXID; 3555 if (data8 & P_RGMII_ID_EG_ENABLE) 3556 interface = PHY_INTERFACE_MODE_RGMII_ID; 3557 } 3558 } 3559 3560 return interface; 3561 } 3562 3563 static void ksz88x3_phylink_mac_config(struct phylink_config *config, 3564 unsigned int mode, 3565 const struct phylink_link_state *state) 3566 { 3567 struct dsa_port *dp = dsa_phylink_to_port(config); 3568 struct ksz_device *dev = dp->ds->priv; 3569 3570 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN); 3571 } 3572 3573 static void ksz_phylink_mac_config(struct phylink_config *config, 3574 unsigned int mode, 3575 const struct phylink_link_state *state) 3576 { 3577 struct dsa_port *dp = dsa_phylink_to_port(config); 3578 struct ksz_device *dev = dp->ds->priv; 3579 int port = dp->index; 3580 3581 /* Internal PHYs */ 3582 if (dev->info->internal_phy[port]) 3583 return; 3584 3585 if (phylink_autoneg_inband(mode)) { 3586 dev_err(dev->dev, "In-band AN not supported!\n"); 3587 return; 3588 } 3589 3590 ksz_set_xmii(dev, port, state->interface); 3591 3592 if (dev->dev_ops->setup_rgmii_delay) 3593 dev->dev_ops->setup_rgmii_delay(dev, port); 3594 } 3595 3596 bool ksz_get_gbit(struct ksz_device *dev, int port) 3597 { 3598 const u8 *bitval = dev->info->xmii_ctrl1; 3599 const u16 *regs = dev->info->regs; 3600 bool gbit = false; 3601 u8 data8; 3602 bool val; 3603 3604 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3605 3606 val = FIELD_GET(P_GMII_1GBIT_M, data8); 3607 3608 if (val == bitval[P_GMII_1GBIT]) 3609 gbit = true; 3610 3611 return gbit; 3612 } 3613 3614 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 3615 { 3616 const u8 *bitval = dev->info->xmii_ctrl1; 3617 const u16 *regs = dev->info->regs; 3618 u8 data8; 3619 3620 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3621 3622 data8 &= ~P_GMII_1GBIT_M; 3623 3624 if (gbit) 3625 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 3626 else 3627 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 3628 3629 /* Write the updated value */ 3630 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3631 } 3632 3633 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 3634 { 3635 const u8 *bitval = dev->info->xmii_ctrl0; 3636 const u16 *regs = dev->info->regs; 3637 u8 data8; 3638 3639 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 3640 3641 data8 &= ~P_MII_100MBIT_M; 3642 3643 if (speed == SPEED_100) 3644 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 3645 else 3646 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 3647 3648 /* Write the updated value */ 3649 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 3650 } 3651 3652 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 3653 { 3654 if (speed == SPEED_1000) 3655 ksz_set_gbit(dev, port, true); 3656 else 3657 ksz_set_gbit(dev, port, false); 3658 3659 if (speed == SPEED_100 || speed == SPEED_10) 3660 ksz_set_100_10mbit(dev, port, speed); 3661 } 3662 3663 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 3664 bool tx_pause, bool rx_pause) 3665 { 3666 const u8 *bitval = dev->info->xmii_ctrl0; 3667 const u32 *masks = dev->info->masks; 3668 const u16 *regs = dev->info->regs; 3669 u8 mask; 3670 u8 val; 3671 3672 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 3673 masks[P_MII_RX_FLOW_CTRL]; 3674 3675 if (duplex == DUPLEX_FULL) 3676 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 3677 else 3678 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 3679 3680 if (tx_pause) 3681 val |= masks[P_MII_TX_FLOW_CTRL]; 3682 3683 if (rx_pause) 3684 val |= masks[P_MII_RX_FLOW_CTRL]; 3685 3686 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 3687 } 3688 3689 static void ksz9477_phylink_mac_link_up(struct phylink_config *config, 3690 struct phy_device *phydev, 3691 unsigned int mode, 3692 phy_interface_t interface, 3693 int speed, int duplex, bool tx_pause, 3694 bool rx_pause) 3695 { 3696 struct dsa_port *dp = dsa_phylink_to_port(config); 3697 struct ksz_device *dev = dp->ds->priv; 3698 int port = dp->index; 3699 struct ksz_port *p; 3700 3701 p = &dev->ports[port]; 3702 3703 /* Internal PHYs */ 3704 if (dev->info->internal_phy[port]) 3705 return; 3706 3707 p->phydev.speed = speed; 3708 3709 ksz_port_set_xmii_speed(dev, port, speed); 3710 3711 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 3712 } 3713 3714 static int ksz_switch_detect(struct ksz_device *dev) 3715 { 3716 u8 id1, id2, id4; 3717 u16 id16; 3718 u32 id32; 3719 int ret; 3720 3721 /* read chip id */ 3722 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 3723 if (ret) 3724 return ret; 3725 3726 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 3727 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 3728 3729 switch (id1) { 3730 case KSZ87_FAMILY_ID: 3731 if (id2 == KSZ87_CHIP_ID_95) { 3732 u8 val; 3733 3734 dev->chip_id = KSZ8795_CHIP_ID; 3735 3736 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 3737 if (val & KSZ8_PORT_FIBER_MODE) 3738 dev->chip_id = KSZ8765_CHIP_ID; 3739 } else if (id2 == KSZ87_CHIP_ID_94) { 3740 dev->chip_id = KSZ8794_CHIP_ID; 3741 } else { 3742 return -ENODEV; 3743 } 3744 break; 3745 case KSZ88_FAMILY_ID: 3746 if (id2 == KSZ88_CHIP_ID_63) 3747 dev->chip_id = KSZ88X3_CHIP_ID; 3748 else 3749 return -ENODEV; 3750 break; 3751 case KSZ8895_FAMILY_ID: 3752 if (id2 == KSZ8895_CHIP_ID_95 || 3753 id2 == KSZ8895_CHIP_ID_95R) 3754 dev->chip_id = KSZ8895_CHIP_ID; 3755 else 3756 return -ENODEV; 3757 ret = ksz_read8(dev, REG_KSZ8864_CHIP_ID, &id4); 3758 if (ret) 3759 return ret; 3760 if (id4 & SW_KSZ8864) 3761 dev->chip_id = KSZ8864_CHIP_ID; 3762 break; 3763 default: 3764 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 3765 if (ret) 3766 return ret; 3767 3768 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 3769 id32 &= ~0xFF; 3770 3771 switch (id32) { 3772 case KSZ9477_CHIP_ID: 3773 case KSZ9896_CHIP_ID: 3774 case KSZ9897_CHIP_ID: 3775 case KSZ9567_CHIP_ID: 3776 case KSZ8567_CHIP_ID: 3777 case LAN9370_CHIP_ID: 3778 case LAN9371_CHIP_ID: 3779 case LAN9372_CHIP_ID: 3780 case LAN9373_CHIP_ID: 3781 case LAN9374_CHIP_ID: 3782 dev->chip_id = id32; 3783 break; 3784 case KSZ9893_CHIP_ID: 3785 ret = ksz_read8(dev, REG_CHIP_ID4, 3786 &id4); 3787 if (ret) 3788 return ret; 3789 3790 if (id4 == SKU_ID_KSZ8563) 3791 dev->chip_id = KSZ8563_CHIP_ID; 3792 else if (id4 == SKU_ID_KSZ9563) 3793 dev->chip_id = KSZ9563_CHIP_ID; 3794 else 3795 dev->chip_id = KSZ9893_CHIP_ID; 3796 3797 break; 3798 default: 3799 dev_err(dev->dev, 3800 "unsupported switch detected %x)\n", id32); 3801 return -ENODEV; 3802 } 3803 } 3804 return 0; 3805 } 3806 3807 static int ksz_cls_flower_add(struct dsa_switch *ds, int port, 3808 struct flow_cls_offload *cls, bool ingress) 3809 { 3810 struct ksz_device *dev = ds->priv; 3811 3812 switch (dev->chip_id) { 3813 case KSZ8563_CHIP_ID: 3814 case KSZ8567_CHIP_ID: 3815 case KSZ9477_CHIP_ID: 3816 case KSZ9563_CHIP_ID: 3817 case KSZ9567_CHIP_ID: 3818 case KSZ9893_CHIP_ID: 3819 case KSZ9896_CHIP_ID: 3820 case KSZ9897_CHIP_ID: 3821 return ksz9477_cls_flower_add(ds, port, cls, ingress); 3822 } 3823 3824 return -EOPNOTSUPP; 3825 } 3826 3827 static int ksz_cls_flower_del(struct dsa_switch *ds, int port, 3828 struct flow_cls_offload *cls, bool ingress) 3829 { 3830 struct ksz_device *dev = ds->priv; 3831 3832 switch (dev->chip_id) { 3833 case KSZ8563_CHIP_ID: 3834 case KSZ8567_CHIP_ID: 3835 case KSZ9477_CHIP_ID: 3836 case KSZ9563_CHIP_ID: 3837 case KSZ9567_CHIP_ID: 3838 case KSZ9893_CHIP_ID: 3839 case KSZ9896_CHIP_ID: 3840 case KSZ9897_CHIP_ID: 3841 return ksz9477_cls_flower_del(ds, port, cls, ingress); 3842 } 3843 3844 return -EOPNOTSUPP; 3845 } 3846 3847 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 3848 * is converted to Hex-decimal using the successive multiplication method. On 3849 * every step, integer part is taken and decimal part is carry forwarded. 3850 */ 3851 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 3852 { 3853 u32 cinc = 0; 3854 u32 txrate; 3855 u32 rate; 3856 u8 temp; 3857 u8 i; 3858 3859 txrate = idle_slope - send_slope; 3860 3861 if (!txrate) 3862 return -EINVAL; 3863 3864 rate = idle_slope; 3865 3866 /* 24 bit register */ 3867 for (i = 0; i < 6; i++) { 3868 rate = rate * 16; 3869 3870 temp = rate / txrate; 3871 3872 rate %= txrate; 3873 3874 cinc = ((cinc << 4) | temp); 3875 } 3876 3877 *bw = cinc; 3878 3879 return 0; 3880 } 3881 3882 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 3883 u8 shaper) 3884 { 3885 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 3886 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 3887 FIELD_PREP(MTI_SHAPING_M, shaper)); 3888 } 3889 3890 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 3891 struct tc_cbs_qopt_offload *qopt) 3892 { 3893 struct ksz_device *dev = ds->priv; 3894 int ret; 3895 u32 bw; 3896 3897 if (!dev->info->tc_cbs_supported) 3898 return -EOPNOTSUPP; 3899 3900 if (qopt->queue > dev->info->num_tx_queues) 3901 return -EINVAL; 3902 3903 /* Queue Selection */ 3904 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 3905 if (ret) 3906 return ret; 3907 3908 if (!qopt->enable) 3909 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3910 MTI_SHAPING_OFF); 3911 3912 /* High Credit */ 3913 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 3914 qopt->hicredit); 3915 if (ret) 3916 return ret; 3917 3918 /* Low Credit */ 3919 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 3920 qopt->locredit); 3921 if (ret) 3922 return ret; 3923 3924 /* Credit Increment Register */ 3925 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 3926 if (ret) 3927 return ret; 3928 3929 if (dev->dev_ops->tc_cbs_set_cinc) { 3930 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 3931 if (ret) 3932 return ret; 3933 } 3934 3935 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3936 MTI_SHAPING_SRP); 3937 } 3938 3939 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 3940 { 3941 int queue, ret; 3942 3943 /* Configuration will not take effect until the last Port Queue X 3944 * Egress Limit Control Register is written. 3945 */ 3946 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3947 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 3948 KSZ9477_OUT_RATE_NO_LIMIT); 3949 if (ret) 3950 return ret; 3951 } 3952 3953 return 0; 3954 } 3955 3956 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 3957 int band) 3958 { 3959 /* Compared to queues, bands prioritize packets differently. In strict 3960 * priority mode, the lowest priority is assigned to Queue 0 while the 3961 * highest priority is given to Band 0. 3962 */ 3963 return p->bands - 1 - band; 3964 } 3965 3966 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 3967 { 3968 int ret; 3969 3970 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3971 if (ret) 3972 return ret; 3973 3974 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3975 MTI_SHAPING_OFF); 3976 } 3977 3978 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 3979 int weight) 3980 { 3981 int ret; 3982 3983 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3984 if (ret) 3985 return ret; 3986 3987 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3988 MTI_SHAPING_OFF); 3989 if (ret) 3990 return ret; 3991 3992 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 3993 } 3994 3995 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 3996 struct tc_ets_qopt_offload_replace_params *p) 3997 { 3998 int ret, band, tc_prio; 3999 u32 queue_map = 0; 4000 4001 /* In order to ensure proper prioritization, it is necessary to set the 4002 * rate limit for the related queue to zero. Otherwise strict priority 4003 * or WRR mode will not work. This is a hardware limitation. 4004 */ 4005 ret = ksz_disable_egress_rate_limit(dev, port); 4006 if (ret) 4007 return ret; 4008 4009 /* Configure queue scheduling mode for all bands. Currently only strict 4010 * prio mode is supported. 4011 */ 4012 for (band = 0; band < p->bands; band++) { 4013 int queue = ksz_ets_band_to_queue(p, band); 4014 4015 ret = ksz_queue_set_strict(dev, port, queue); 4016 if (ret) 4017 return ret; 4018 } 4019 4020 /* Configure the mapping between traffic classes and queues. Note: 4021 * priomap variable support 16 traffic classes, but the chip can handle 4022 * only 8 classes. 4023 */ 4024 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 4025 int queue; 4026 4027 if (tc_prio >= dev->info->num_ipms) 4028 break; 4029 4030 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 4031 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 4032 } 4033 4034 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 4035 } 4036 4037 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 4038 { 4039 int ret, queue; 4040 4041 /* To restore the default chip configuration, set all queues to use the 4042 * WRR scheduler with a weight of 1. 4043 */ 4044 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 4045 ret = ksz_queue_set_wrr(dev, port, queue, 4046 KSZ9477_DEFAULT_WRR_WEIGHT); 4047 if (ret) 4048 return ret; 4049 } 4050 4051 /* Revert the queue mapping for TC-priority to its default setting on 4052 * the chip. 4053 */ 4054 return ksz9477_set_default_prio_queue_mapping(dev, port); 4055 } 4056 4057 static int ksz_tc_ets_validate(struct ksz_device *dev, int port, 4058 struct tc_ets_qopt_offload_replace_params *p) 4059 { 4060 int band; 4061 4062 /* Since it is not feasible to share one port among multiple qdisc, 4063 * the user must configure all available queues appropriately. 4064 */ 4065 if (p->bands != dev->info->num_tx_queues) { 4066 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 4067 dev->info->num_tx_queues); 4068 return -EOPNOTSUPP; 4069 } 4070 4071 for (band = 0; band < p->bands; ++band) { 4072 /* The KSZ switches utilize a weighted round robin configuration 4073 * where a certain number of packets can be transmitted from a 4074 * queue before the next queue is serviced. For more information 4075 * on this, refer to section 5.2.8.4 of the KSZ8565R 4076 * documentation on the Port Transmit Queue Control 1 Register. 4077 * However, the current ETS Qdisc implementation (as of February 4078 * 2023) assigns a weight to each queue based on the number of 4079 * bytes or extrapolated bandwidth in percentages. Since this 4080 * differs from the KSZ switches' method and we don't want to 4081 * fake support by converting bytes to packets, it is better to 4082 * return an error instead. 4083 */ 4084 if (p->quanta[band]) { 4085 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 4086 return -EOPNOTSUPP; 4087 } 4088 } 4089 4090 return 0; 4091 } 4092 4093 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 4094 struct tc_ets_qopt_offload *qopt) 4095 { 4096 struct ksz_device *dev = ds->priv; 4097 int ret; 4098 4099 if (is_ksz8(dev)) 4100 return -EOPNOTSUPP; 4101 4102 if (qopt->parent != TC_H_ROOT) { 4103 dev_err(dev->dev, "Parent should be \"root\"\n"); 4104 return -EOPNOTSUPP; 4105 } 4106 4107 switch (qopt->command) { 4108 case TC_ETS_REPLACE: 4109 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 4110 if (ret) 4111 return ret; 4112 4113 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 4114 case TC_ETS_DESTROY: 4115 return ksz_tc_ets_del(dev, port); 4116 case TC_ETS_STATS: 4117 case TC_ETS_GRAFT: 4118 return -EOPNOTSUPP; 4119 } 4120 4121 return -EOPNOTSUPP; 4122 } 4123 4124 static int ksz_setup_tc(struct dsa_switch *ds, int port, 4125 enum tc_setup_type type, void *type_data) 4126 { 4127 switch (type) { 4128 case TC_SETUP_QDISC_CBS: 4129 return ksz_setup_tc_cbs(ds, port, type_data); 4130 case TC_SETUP_QDISC_ETS: 4131 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 4132 default: 4133 return -EOPNOTSUPP; 4134 } 4135 } 4136 4137 /** 4138 * ksz_handle_wake_reason - Handle wake reason on a specified port. 4139 * @dev: The device structure. 4140 * @port: The port number. 4141 * 4142 * This function reads the PME (Power Management Event) status register of a 4143 * specified port to determine the wake reason. If there is no wake event, it 4144 * returns early. Otherwise, it logs the wake reason which could be due to a 4145 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register 4146 * is then cleared to acknowledge the handling of the wake event. 4147 * 4148 * Return: 0 on success, or an error code on failure. 4149 */ 4150 int ksz_handle_wake_reason(struct ksz_device *dev, int port) 4151 { 4152 const struct ksz_dev_ops *ops = dev->dev_ops; 4153 const u16 *regs = dev->info->regs; 4154 u8 pme_status; 4155 int ret; 4156 4157 ret = ops->pme_pread8(dev, port, regs[REG_PORT_PME_STATUS], 4158 &pme_status); 4159 if (ret) 4160 return ret; 4161 4162 if (!pme_status) 4163 return 0; 4164 4165 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port, 4166 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "", 4167 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "", 4168 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : ""); 4169 4170 return ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_STATUS], 4171 pme_status); 4172 } 4173 4174 /** 4175 * ksz_get_wol - Get Wake-on-LAN settings for a specified port. 4176 * @ds: The dsa_switch structure. 4177 * @port: The port number. 4178 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 4179 * 4180 * This function checks the device PME wakeup_source flag and chip_id. 4181 * If enabled and supported, it sets the supported and active WoL 4182 * flags. 4183 */ 4184 static void ksz_get_wol(struct dsa_switch *ds, int port, 4185 struct ethtool_wolinfo *wol) 4186 { 4187 struct ksz_device *dev = ds->priv; 4188 const u16 *regs = dev->info->regs; 4189 u8 pme_ctrl; 4190 int ret; 4191 4192 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4193 return; 4194 4195 if (!dev->wakeup_source) 4196 return; 4197 4198 wol->supported = WAKE_PHY; 4199 4200 /* Check if the current MAC address on this port can be set 4201 * as global for WAKE_MAGIC support. The result may vary 4202 * dynamically based on other ports configurations. 4203 */ 4204 if (ksz_is_port_mac_global_usable(dev->ds, port)) 4205 wol->supported |= WAKE_MAGIC; 4206 4207 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 4208 &pme_ctrl); 4209 if (ret) 4210 return; 4211 4212 if (pme_ctrl & PME_WOL_MAGICPKT) 4213 wol->wolopts |= WAKE_MAGIC; 4214 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY)) 4215 wol->wolopts |= WAKE_PHY; 4216 } 4217 4218 /** 4219 * ksz_set_wol - Set Wake-on-LAN settings for a specified port. 4220 * @ds: The dsa_switch structure. 4221 * @port: The port number. 4222 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 4223 * 4224 * This function configures Wake-on-LAN (WoL) settings for a specified 4225 * port. It validates the provided WoL options, checks if PME is 4226 * enabled and supported, clears any previous wake reasons, and sets 4227 * the Magic Packet flag in the port's PME control register if 4228 * specified. 4229 * 4230 * Return: 0 on success, or other error codes on failure. 4231 */ 4232 static int ksz_set_wol(struct dsa_switch *ds, int port, 4233 struct ethtool_wolinfo *wol) 4234 { 4235 u8 pme_ctrl = 0, pme_ctrl_old = 0; 4236 struct ksz_device *dev = ds->priv; 4237 const u16 *regs = dev->info->regs; 4238 bool magic_switched_off; 4239 bool magic_switched_on; 4240 int ret; 4241 4242 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC)) 4243 return -EINVAL; 4244 4245 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4246 return -EOPNOTSUPP; 4247 4248 if (!dev->wakeup_source) 4249 return -EOPNOTSUPP; 4250 4251 ret = ksz_handle_wake_reason(dev, port); 4252 if (ret) 4253 return ret; 4254 4255 if (wol->wolopts & WAKE_MAGIC) 4256 pme_ctrl |= PME_WOL_MAGICPKT; 4257 if (wol->wolopts & WAKE_PHY) 4258 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY; 4259 4260 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 4261 &pme_ctrl_old); 4262 if (ret) 4263 return ret; 4264 4265 if (pme_ctrl_old == pme_ctrl) 4266 return 0; 4267 4268 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) && 4269 !(pme_ctrl & PME_WOL_MAGICPKT); 4270 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) && 4271 (pme_ctrl & PME_WOL_MAGICPKT); 4272 4273 /* To keep reference count of MAC address, we should do this 4274 * operation only on change of WOL settings. 4275 */ 4276 if (magic_switched_on) { 4277 ret = ksz_switch_macaddr_get(dev->ds, port, NULL); 4278 if (ret) 4279 return ret; 4280 } else if (magic_switched_off) { 4281 ksz_switch_macaddr_put(dev->ds); 4282 } 4283 4284 ret = dev->dev_ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 4285 pme_ctrl); 4286 if (ret) { 4287 if (magic_switched_on) 4288 ksz_switch_macaddr_put(dev->ds); 4289 return ret; 4290 } 4291 4292 return 0; 4293 } 4294 4295 /** 4296 * ksz_wol_pre_shutdown - Prepares the switch device for shutdown while 4297 * considering Wake-on-LAN (WoL) settings. 4298 * @dev: The switch device structure. 4299 * @wol_enabled: Pointer to a boolean which will be set to true if WoL is 4300 * enabled on any port. 4301 * 4302 * This function prepares the switch device for a safe shutdown while taking 4303 * into account the Wake-on-LAN (WoL) settings on the user ports. It updates 4304 * the wol_enabled flag accordingly to reflect whether WoL is active on any 4305 * port. 4306 */ 4307 static void ksz_wol_pre_shutdown(struct ksz_device *dev, bool *wol_enabled) 4308 { 4309 const struct ksz_dev_ops *ops = dev->dev_ops; 4310 const u16 *regs = dev->info->regs; 4311 u8 pme_pin_en = PME_ENABLE; 4312 struct dsa_port *dp; 4313 int ret; 4314 4315 *wol_enabled = false; 4316 4317 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4318 return; 4319 4320 if (!dev->wakeup_source) 4321 return; 4322 4323 dsa_switch_for_each_user_port(dp, dev->ds) { 4324 u8 pme_ctrl = 0; 4325 4326 ret = ops->pme_pread8(dev, dp->index, 4327 regs[REG_PORT_PME_CTRL], &pme_ctrl); 4328 if (!ret && pme_ctrl) 4329 *wol_enabled = true; 4330 4331 /* make sure there are no pending wake events which would 4332 * prevent the device from going to sleep/shutdown. 4333 */ 4334 ksz_handle_wake_reason(dev, dp->index); 4335 } 4336 4337 /* Now we are save to enable PME pin. */ 4338 if (*wol_enabled) { 4339 if (dev->pme_active_high) 4340 pme_pin_en |= PME_POLARITY; 4341 ops->pme_write8(dev, regs[REG_SW_PME_CTRL], pme_pin_en); 4342 if (ksz_is_ksz87xx(dev)) 4343 ksz_write8(dev, KSZ87XX_REG_INT_EN, KSZ87XX_INT_PME_MASK); 4344 } 4345 } 4346 4347 static int ksz_port_set_mac_address(struct dsa_switch *ds, int port, 4348 const unsigned char *addr) 4349 { 4350 struct dsa_port *dp = dsa_to_port(ds, port); 4351 struct ethtool_wolinfo wol; 4352 4353 if (dp->hsr_dev) { 4354 dev_err(ds->dev, 4355 "Cannot change MAC address on port %d with active HSR offload\n", 4356 port); 4357 return -EBUSY; 4358 } 4359 4360 /* Need to initialize variable as the code to fill in settings may 4361 * not be executed. 4362 */ 4363 wol.wolopts = 0; 4364 4365 ksz_get_wol(ds, dp->index, &wol); 4366 if (wol.wolopts & WAKE_MAGIC) { 4367 dev_err(ds->dev, 4368 "Cannot change MAC address on port %d with active Wake on Magic Packet\n", 4369 port); 4370 return -EBUSY; 4371 } 4372 4373 return 0; 4374 } 4375 4376 /** 4377 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port 4378 * can be used as a global address. 4379 * @ds: Pointer to the DSA switch structure. 4380 * @port: The port number on which the MAC address is to be checked. 4381 * 4382 * This function examines the MAC address set on the specified port and 4383 * determines if it can be used as a global address for the switch. 4384 * 4385 * Return: true if the port's MAC address can be used as a global address, false 4386 * otherwise. 4387 */ 4388 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port) 4389 { 4390 struct net_device *user = dsa_to_port(ds, port)->user; 4391 const unsigned char *addr = user->dev_addr; 4392 struct ksz_switch_macaddr *switch_macaddr; 4393 struct ksz_device *dev = ds->priv; 4394 4395 ASSERT_RTNL(); 4396 4397 switch_macaddr = dev->switch_macaddr; 4398 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr)) 4399 return false; 4400 4401 return true; 4402 } 4403 4404 /** 4405 * ksz_switch_macaddr_get - Program the switch's MAC address register. 4406 * @ds: DSA switch instance. 4407 * @port: Port number. 4408 * @extack: Netlink extended acknowledgment. 4409 * 4410 * This function programs the switch's MAC address register with the MAC address 4411 * of the requesting user port. This single address is used by the switch for 4412 * multiple features like HSR self-address filtering and WoL. Other user ports 4413 * can share ownership of this address as long as their MAC address is the same. 4414 * The MAC addresses of user ports must not change while they have ownership of 4415 * the switch MAC address. 4416 * 4417 * Return: 0 on success, or other error codes on failure. 4418 */ 4419 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 4420 struct netlink_ext_ack *extack) 4421 { 4422 struct net_device *user = dsa_to_port(ds, port)->user; 4423 const unsigned char *addr = user->dev_addr; 4424 struct ksz_switch_macaddr *switch_macaddr; 4425 struct ksz_device *dev = ds->priv; 4426 const u16 *regs = dev->info->regs; 4427 int i, ret; 4428 4429 /* Make sure concurrent MAC address changes are blocked */ 4430 ASSERT_RTNL(); 4431 4432 switch_macaddr = dev->switch_macaddr; 4433 if (switch_macaddr) { 4434 if (!ether_addr_equal(switch_macaddr->addr, addr)) { 4435 NL_SET_ERR_MSG_FMT_MOD(extack, 4436 "Switch already configured for MAC address %pM", 4437 switch_macaddr->addr); 4438 return -EBUSY; 4439 } 4440 4441 refcount_inc(&switch_macaddr->refcount); 4442 return 0; 4443 } 4444 4445 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL); 4446 if (!switch_macaddr) 4447 return -ENOMEM; 4448 4449 ether_addr_copy(switch_macaddr->addr, addr); 4450 refcount_set(&switch_macaddr->refcount, 1); 4451 dev->switch_macaddr = switch_macaddr; 4452 4453 /* Program the switch MAC address to hardware */ 4454 for (i = 0; i < ETH_ALEN; i++) { 4455 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, addr[i]); 4456 if (ret) 4457 goto macaddr_drop; 4458 } 4459 4460 return 0; 4461 4462 macaddr_drop: 4463 dev->switch_macaddr = NULL; 4464 refcount_set(&switch_macaddr->refcount, 0); 4465 kfree(switch_macaddr); 4466 4467 return ret; 4468 } 4469 4470 void ksz_switch_macaddr_put(struct dsa_switch *ds) 4471 { 4472 struct ksz_switch_macaddr *switch_macaddr; 4473 struct ksz_device *dev = ds->priv; 4474 const u16 *regs = dev->info->regs; 4475 int i; 4476 4477 /* Make sure concurrent MAC address changes are blocked */ 4478 ASSERT_RTNL(); 4479 4480 switch_macaddr = dev->switch_macaddr; 4481 if (!refcount_dec_and_test(&switch_macaddr->refcount)) 4482 return; 4483 4484 for (i = 0; i < ETH_ALEN; i++) 4485 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0); 4486 4487 dev->switch_macaddr = NULL; 4488 kfree(switch_macaddr); 4489 } 4490 4491 static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr, 4492 struct netlink_ext_ack *extack) 4493 { 4494 struct ksz_device *dev = ds->priv; 4495 enum hsr_version ver; 4496 int ret; 4497 4498 ret = hsr_get_version(hsr, &ver); 4499 if (ret) 4500 return ret; 4501 4502 if (dev->chip_id != KSZ9477_CHIP_ID) { 4503 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload"); 4504 return -EOPNOTSUPP; 4505 } 4506 4507 /* KSZ9477 can support HW offloading of only 1 HSR device */ 4508 if (dev->hsr_dev && hsr != dev->hsr_dev) { 4509 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR"); 4510 return -EOPNOTSUPP; 4511 } 4512 4513 /* KSZ9477 only supports HSR v0 and v1 */ 4514 if (!(ver == HSR_V0 || ver == HSR_V1)) { 4515 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported"); 4516 return -EOPNOTSUPP; 4517 } 4518 4519 /* KSZ9477 can only perform HSR offloading for up to two ports */ 4520 if (hweight8(dev->hsr_ports) >= 2) { 4521 NL_SET_ERR_MSG_MOD(extack, 4522 "Cannot offload more than two ports - using software HSR"); 4523 return -EOPNOTSUPP; 4524 } 4525 4526 /* Self MAC address filtering, to avoid frames traversing 4527 * the HSR ring more than once. 4528 */ 4529 ret = ksz_switch_macaddr_get(ds, port, extack); 4530 if (ret) 4531 return ret; 4532 4533 ksz9477_hsr_join(ds, port, hsr); 4534 dev->hsr_dev = hsr; 4535 dev->hsr_ports |= BIT(port); 4536 4537 return 0; 4538 } 4539 4540 static int ksz_hsr_leave(struct dsa_switch *ds, int port, 4541 struct net_device *hsr) 4542 { 4543 struct ksz_device *dev = ds->priv; 4544 4545 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID); 4546 4547 ksz9477_hsr_leave(ds, port, hsr); 4548 dev->hsr_ports &= ~BIT(port); 4549 if (!dev->hsr_ports) 4550 dev->hsr_dev = NULL; 4551 4552 ksz_switch_macaddr_put(ds); 4553 4554 return 0; 4555 } 4556 4557 static const struct dsa_switch_ops ksz_switch_ops = { 4558 .get_tag_protocol = ksz_get_tag_protocol, 4559 .connect_tag_protocol = ksz_connect_tag_protocol, 4560 .get_phy_flags = ksz_get_phy_flags, 4561 .setup = ksz_setup, 4562 .teardown = ksz_teardown, 4563 .phy_read = ksz_phy_read16, 4564 .phy_write = ksz_phy_write16, 4565 .phylink_get_caps = ksz_phylink_get_caps, 4566 .port_setup = ksz_port_setup, 4567 .set_ageing_time = ksz_set_ageing_time, 4568 .get_strings = ksz_get_strings, 4569 .get_ethtool_stats = ksz_get_ethtool_stats, 4570 .get_sset_count = ksz_sset_count, 4571 .port_bridge_join = ksz_port_bridge_join, 4572 .port_bridge_leave = ksz_port_bridge_leave, 4573 .port_hsr_join = ksz_hsr_join, 4574 .port_hsr_leave = ksz_hsr_leave, 4575 .port_set_mac_address = ksz_port_set_mac_address, 4576 .port_stp_state_set = ksz_port_stp_state_set, 4577 .port_teardown = ksz_port_teardown, 4578 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 4579 .port_bridge_flags = ksz_port_bridge_flags, 4580 .port_fast_age = ksz_port_fast_age, 4581 .port_vlan_filtering = ksz_port_vlan_filtering, 4582 .port_vlan_add = ksz_port_vlan_add, 4583 .port_vlan_del = ksz_port_vlan_del, 4584 .port_fdb_dump = ksz_port_fdb_dump, 4585 .port_fdb_add = ksz_port_fdb_add, 4586 .port_fdb_del = ksz_port_fdb_del, 4587 .port_mdb_add = ksz_port_mdb_add, 4588 .port_mdb_del = ksz_port_mdb_del, 4589 .port_mirror_add = ksz_port_mirror_add, 4590 .port_mirror_del = ksz_port_mirror_del, 4591 .get_stats64 = ksz_get_stats64, 4592 .get_pause_stats = ksz_get_pause_stats, 4593 .port_change_mtu = ksz_change_mtu, 4594 .port_max_mtu = ksz_max_mtu, 4595 .get_wol = ksz_get_wol, 4596 .set_wol = ksz_set_wol, 4597 .get_ts_info = ksz_get_ts_info, 4598 .port_hwtstamp_get = ksz_hwtstamp_get, 4599 .port_hwtstamp_set = ksz_hwtstamp_set, 4600 .port_txtstamp = ksz_port_txtstamp, 4601 .port_rxtstamp = ksz_port_rxtstamp, 4602 .cls_flower_add = ksz_cls_flower_add, 4603 .cls_flower_del = ksz_cls_flower_del, 4604 .port_setup_tc = ksz_setup_tc, 4605 .get_mac_eee = ksz_get_mac_eee, 4606 .set_mac_eee = ksz_set_mac_eee, 4607 .port_get_default_prio = ksz_port_get_default_prio, 4608 .port_set_default_prio = ksz_port_set_default_prio, 4609 .port_get_dscp_prio = ksz_port_get_dscp_prio, 4610 .port_add_dscp_prio = ksz_port_add_dscp_prio, 4611 .port_del_dscp_prio = ksz_port_del_dscp_prio, 4612 .port_get_apptrust = ksz_port_get_apptrust, 4613 .port_set_apptrust = ksz_port_set_apptrust, 4614 }; 4615 4616 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 4617 { 4618 struct dsa_switch *ds; 4619 struct ksz_device *swdev; 4620 4621 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 4622 if (!ds) 4623 return NULL; 4624 4625 ds->dev = base; 4626 ds->num_ports = DSA_MAX_PORTS; 4627 ds->ops = &ksz_switch_ops; 4628 4629 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 4630 if (!swdev) 4631 return NULL; 4632 4633 ds->priv = swdev; 4634 swdev->dev = base; 4635 4636 swdev->ds = ds; 4637 swdev->priv = priv; 4638 4639 return swdev; 4640 } 4641 EXPORT_SYMBOL(ksz_switch_alloc); 4642 4643 /** 4644 * ksz_switch_shutdown - Shutdown routine for the switch device. 4645 * @dev: The switch device structure. 4646 * 4647 * This function is responsible for initiating a shutdown sequence for the 4648 * switch device. It invokes the reset operation defined in the device 4649 * operations, if available, to reset the switch. Subsequently, it calls the 4650 * DSA framework's shutdown function to ensure a proper shutdown of the DSA 4651 * switch. 4652 */ 4653 void ksz_switch_shutdown(struct ksz_device *dev) 4654 { 4655 bool wol_enabled = false; 4656 4657 ksz_wol_pre_shutdown(dev, &wol_enabled); 4658 4659 if (dev->dev_ops->reset && !wol_enabled) 4660 dev->dev_ops->reset(dev); 4661 4662 dsa_switch_shutdown(dev->ds); 4663 } 4664 EXPORT_SYMBOL(ksz_switch_shutdown); 4665 4666 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 4667 struct device_node *port_dn) 4668 { 4669 phy_interface_t phy_mode = dev->ports[port_num].interface; 4670 int rx_delay = -1, tx_delay = -1; 4671 4672 if (!phy_interface_mode_is_rgmii(phy_mode)) 4673 return; 4674 4675 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 4676 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 4677 4678 if (rx_delay == -1 && tx_delay == -1) { 4679 dev_warn(dev->dev, 4680 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 4681 "please update device tree to specify \"rx-internal-delay-ps\" and " 4682 "\"tx-internal-delay-ps\"", 4683 port_num); 4684 4685 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 4686 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 4687 rx_delay = 2000; 4688 4689 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 4690 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 4691 tx_delay = 2000; 4692 } 4693 4694 if (rx_delay < 0) 4695 rx_delay = 0; 4696 if (tx_delay < 0) 4697 tx_delay = 0; 4698 4699 dev->ports[port_num].rgmii_rx_val = rx_delay; 4700 dev->ports[port_num].rgmii_tx_val = tx_delay; 4701 } 4702 4703 /** 4704 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding 4705 * register value. 4706 * @array: The array of drive strength values to search. 4707 * @array_size: The size of the array. 4708 * @microamp: The drive strength value in microamp to be converted. 4709 * 4710 * This function searches the array of drive strength values for the given 4711 * microamp value and returns the corresponding register value for that drive. 4712 * 4713 * Returns: If found, the corresponding register value for that drive strength 4714 * is returned. Otherwise, -EINVAL is returned indicating an invalid value. 4715 */ 4716 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array, 4717 size_t array_size, int microamp) 4718 { 4719 int i; 4720 4721 for (i = 0; i < array_size; i++) { 4722 if (array[i].microamp == microamp) 4723 return array[i].reg_val; 4724 } 4725 4726 return -EINVAL; 4727 } 4728 4729 /** 4730 * ksz_drive_strength_error() - Report invalid drive strength value 4731 * @dev: ksz device 4732 * @array: The array of drive strength values to search. 4733 * @array_size: The size of the array. 4734 * @microamp: Invalid drive strength value in microamp 4735 * 4736 * This function logs an error message when an unsupported drive strength value 4737 * is detected. It lists out all the supported drive strength values for 4738 * reference in the error message. 4739 */ 4740 static void ksz_drive_strength_error(struct ksz_device *dev, 4741 const struct ksz_drive_strength *array, 4742 size_t array_size, int microamp) 4743 { 4744 char supported_values[100]; 4745 size_t remaining_size; 4746 int added_len; 4747 char *ptr; 4748 int i; 4749 4750 remaining_size = sizeof(supported_values); 4751 ptr = supported_values; 4752 4753 for (i = 0; i < array_size; i++) { 4754 added_len = snprintf(ptr, remaining_size, 4755 i == 0 ? "%d" : ", %d", array[i].microamp); 4756 4757 if (added_len >= remaining_size) 4758 break; 4759 4760 ptr += added_len; 4761 remaining_size -= added_len; 4762 } 4763 4764 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n", 4765 microamp, supported_values); 4766 } 4767 4768 /** 4769 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477 4770 * chip variants. 4771 * @dev: ksz device 4772 * @props: Array of drive strength properties to be applied 4773 * @num_props: Number of properties in the array 4774 * 4775 * This function configures the drive strength for various KSZ9477 chip variants 4776 * based on the provided properties. It handles chip-specific nuances and 4777 * ensures only valid drive strengths are written to the respective chip. 4778 * 4779 * Return: 0 on successful configuration, a negative error code on failure. 4780 */ 4781 static int ksz9477_drive_strength_write(struct ksz_device *dev, 4782 struct ksz_driver_strength_prop *props, 4783 int num_props) 4784 { 4785 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths); 4786 int i, ret, reg; 4787 u8 mask = 0; 4788 u8 val = 0; 4789 4790 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1) 4791 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4792 props[KSZ_DRIVER_STRENGTH_IO].name); 4793 4794 if (dev->chip_id == KSZ8795_CHIP_ID || 4795 dev->chip_id == KSZ8794_CHIP_ID || 4796 dev->chip_id == KSZ8765_CHIP_ID) 4797 reg = KSZ8795_REG_SW_CTRL_20; 4798 else 4799 reg = KSZ9477_REG_SW_IO_STRENGTH; 4800 4801 for (i = 0; i < num_props; i++) { 4802 if (props[i].value == -1) 4803 continue; 4804 4805 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths, 4806 array_size, props[i].value); 4807 if (ret < 0) { 4808 ksz_drive_strength_error(dev, ksz9477_drive_strengths, 4809 array_size, props[i].value); 4810 return ret; 4811 } 4812 4813 mask |= SW_DRIVE_STRENGTH_M << props[i].offset; 4814 val |= ret << props[i].offset; 4815 } 4816 4817 return ksz_rmw8(dev, reg, mask, val); 4818 } 4819 4820 /** 4821 * ksz88x3_drive_strength_write() - Set the drive strength configuration for 4822 * KSZ8863 compatible chip variants. 4823 * @dev: ksz device 4824 * @props: Array of drive strength properties to be set 4825 * @num_props: Number of properties in the array 4826 * 4827 * This function applies the specified drive strength settings to KSZ88X3 chip 4828 * variants (KSZ8873, KSZ8863). 4829 * It ensures the configurations align with what the chip variant supports and 4830 * warns or errors out on unsupported settings. 4831 * 4832 * Return: 0 on success, error code otherwise 4833 */ 4834 static int ksz88x3_drive_strength_write(struct ksz_device *dev, 4835 struct ksz_driver_strength_prop *props, 4836 int num_props) 4837 { 4838 size_t array_size = ARRAY_SIZE(ksz88x3_drive_strengths); 4839 int microamp; 4840 int i, ret; 4841 4842 for (i = 0; i < num_props; i++) { 4843 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO) 4844 continue; 4845 4846 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4847 props[i].name); 4848 } 4849 4850 microamp = props[KSZ_DRIVER_STRENGTH_IO].value; 4851 ret = ksz_drive_strength_to_reg(ksz88x3_drive_strengths, array_size, 4852 microamp); 4853 if (ret < 0) { 4854 ksz_drive_strength_error(dev, ksz88x3_drive_strengths, 4855 array_size, microamp); 4856 return ret; 4857 } 4858 4859 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12, 4860 KSZ8873_DRIVE_STRENGTH_16MA, ret); 4861 } 4862 4863 /** 4864 * ksz_parse_drive_strength() - Extract and apply drive strength configurations 4865 * from device tree properties. 4866 * @dev: ksz device 4867 * 4868 * This function reads the specified drive strength properties from the 4869 * device tree, validates against the supported chip variants, and sets 4870 * them accordingly. An error should be critical here, as the drive strength 4871 * settings are crucial for EMI compliance. 4872 * 4873 * Return: 0 on success, error code otherwise 4874 */ 4875 static int ksz_parse_drive_strength(struct ksz_device *dev) 4876 { 4877 struct ksz_driver_strength_prop of_props[] = { 4878 [KSZ_DRIVER_STRENGTH_HI] = { 4879 .name = "microchip,hi-drive-strength-microamp", 4880 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S, 4881 .value = -1, 4882 }, 4883 [KSZ_DRIVER_STRENGTH_LO] = { 4884 .name = "microchip,lo-drive-strength-microamp", 4885 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S, 4886 .value = -1, 4887 }, 4888 [KSZ_DRIVER_STRENGTH_IO] = { 4889 .name = "microchip,io-drive-strength-microamp", 4890 .offset = 0, /* don't care */ 4891 .value = -1, 4892 }, 4893 }; 4894 struct device_node *np = dev->dev->of_node; 4895 bool have_any_prop = false; 4896 int i, ret; 4897 4898 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4899 ret = of_property_read_u32(np, of_props[i].name, 4900 &of_props[i].value); 4901 if (ret && ret != -EINVAL) 4902 dev_warn(dev->dev, "Failed to read %s\n", 4903 of_props[i].name); 4904 if (ret) 4905 continue; 4906 4907 have_any_prop = true; 4908 } 4909 4910 if (!have_any_prop) 4911 return 0; 4912 4913 switch (dev->chip_id) { 4914 case KSZ88X3_CHIP_ID: 4915 return ksz88x3_drive_strength_write(dev, of_props, 4916 ARRAY_SIZE(of_props)); 4917 case KSZ8795_CHIP_ID: 4918 case KSZ8794_CHIP_ID: 4919 case KSZ8765_CHIP_ID: 4920 case KSZ8563_CHIP_ID: 4921 case KSZ8567_CHIP_ID: 4922 case KSZ9477_CHIP_ID: 4923 case KSZ9563_CHIP_ID: 4924 case KSZ9567_CHIP_ID: 4925 case KSZ9893_CHIP_ID: 4926 case KSZ9896_CHIP_ID: 4927 case KSZ9897_CHIP_ID: 4928 return ksz9477_drive_strength_write(dev, of_props, 4929 ARRAY_SIZE(of_props)); 4930 default: 4931 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4932 if (of_props[i].value == -1) 4933 continue; 4934 4935 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4936 of_props[i].name); 4937 } 4938 } 4939 4940 return 0; 4941 } 4942 4943 int ksz_switch_register(struct ksz_device *dev) 4944 { 4945 const struct ksz_chip_data *info; 4946 struct device_node *ports; 4947 phy_interface_t interface; 4948 unsigned int port_num; 4949 int ret; 4950 int i; 4951 4952 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 4953 GPIOD_OUT_LOW); 4954 if (IS_ERR(dev->reset_gpio)) 4955 return PTR_ERR(dev->reset_gpio); 4956 4957 if (dev->reset_gpio) { 4958 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4959 usleep_range(10000, 12000); 4960 gpiod_set_value_cansleep(dev->reset_gpio, 0); 4961 msleep(100); 4962 } 4963 4964 mutex_init(&dev->dev_mutex); 4965 mutex_init(&dev->regmap_mutex); 4966 mutex_init(&dev->alu_mutex); 4967 mutex_init(&dev->vlan_mutex); 4968 4969 ret = ksz_switch_detect(dev); 4970 if (ret) 4971 return ret; 4972 4973 info = ksz_lookup_info(dev->chip_id); 4974 if (!info) 4975 return -ENODEV; 4976 4977 /* Update the compatible info with the probed one */ 4978 dev->info = info; 4979 4980 dev_info(dev->dev, "found switch: %s, rev %i\n", 4981 dev->info->dev_name, dev->chip_rev); 4982 4983 ret = ksz_check_device_id(dev); 4984 if (ret) 4985 return ret; 4986 4987 dev->dev_ops = dev->info->ops; 4988 4989 ret = dev->dev_ops->init(dev); 4990 if (ret) 4991 return ret; 4992 4993 dev->ports = devm_kzalloc(dev->dev, 4994 dev->info->port_cnt * sizeof(struct ksz_port), 4995 GFP_KERNEL); 4996 if (!dev->ports) 4997 return -ENOMEM; 4998 4999 for (i = 0; i < dev->info->port_cnt; i++) { 5000 spin_lock_init(&dev->ports[i].mib.stats64_lock); 5001 mutex_init(&dev->ports[i].mib.cnt_mutex); 5002 dev->ports[i].mib.counters = 5003 devm_kzalloc(dev->dev, 5004 sizeof(u64) * (dev->info->mib_cnt + 1), 5005 GFP_KERNEL); 5006 if (!dev->ports[i].mib.counters) 5007 return -ENOMEM; 5008 5009 dev->ports[i].ksz_dev = dev; 5010 dev->ports[i].num = i; 5011 } 5012 5013 /* set the real number of ports */ 5014 dev->ds->num_ports = dev->info->port_cnt; 5015 5016 /* set the phylink ops */ 5017 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops; 5018 5019 /* Host port interface will be self detected, or specifically set in 5020 * device tree. 5021 */ 5022 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 5023 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 5024 if (dev->dev->of_node) { 5025 ret = of_get_phy_mode(dev->dev->of_node, &interface); 5026 if (ret == 0) 5027 dev->compat_interface = interface; 5028 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 5029 if (!ports) 5030 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 5031 if (ports) { 5032 for_each_available_child_of_node_scoped(ports, port) { 5033 if (of_property_read_u32(port, "reg", 5034 &port_num)) 5035 continue; 5036 if (!(dev->port_mask & BIT(port_num))) { 5037 of_node_put(ports); 5038 return -EINVAL; 5039 } 5040 of_get_phy_mode(port, 5041 &dev->ports[port_num].interface); 5042 5043 ksz_parse_rgmii_delay(dev, port_num, port); 5044 } 5045 of_node_put(ports); 5046 } 5047 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 5048 "microchip,synclko-125"); 5049 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 5050 "microchip,synclko-disable"); 5051 if (dev->synclko_125 && dev->synclko_disable) { 5052 dev_err(dev->dev, "inconsistent synclko settings\n"); 5053 return -EINVAL; 5054 } 5055 5056 dev->wakeup_source = of_property_read_bool(dev->dev->of_node, 5057 "wakeup-source"); 5058 dev->pme_active_high = of_property_read_bool(dev->dev->of_node, 5059 "microchip,pme-active-high"); 5060 } 5061 5062 ret = dsa_register_switch(dev->ds); 5063 if (ret) { 5064 dev->dev_ops->exit(dev); 5065 return ret; 5066 } 5067 5068 /* Read MIB counters every 30 seconds to avoid overflow. */ 5069 dev->mib_read_interval = msecs_to_jiffies(5000); 5070 5071 /* Start the MIB timer. */ 5072 schedule_delayed_work(&dev->mib_read, 0); 5073 5074 return ret; 5075 } 5076 EXPORT_SYMBOL(ksz_switch_register); 5077 5078 void ksz_switch_remove(struct ksz_device *dev) 5079 { 5080 /* timer started */ 5081 if (dev->mib_read_interval) { 5082 dev->mib_read_interval = 0; 5083 cancel_delayed_work_sync(&dev->mib_read); 5084 } 5085 5086 dev->dev_ops->exit(dev); 5087 dsa_unregister_switch(dev->ds); 5088 5089 if (dev->reset_gpio) 5090 gpiod_set_value_cansleep(dev->reset_gpio, 1); 5091 5092 } 5093 EXPORT_SYMBOL(ksz_switch_remove); 5094 5095 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 5096 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 5097 MODULE_LICENSE("GPL"); 5098