1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/if_hsr.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/of.h> 23 #include <linux/of_mdio.h> 24 #include <linux/of_net.h> 25 #include <linux/micrel_phy.h> 26 #include <net/dsa.h> 27 #include <net/ieee8021q.h> 28 #include <net/pkt_cls.h> 29 #include <net/switchdev.h> 30 31 #include "ksz_common.h" 32 #include "ksz_dcb.h" 33 #include "ksz_ptp.h" 34 #include "ksz8.h" 35 #include "ksz9477.h" 36 #include "lan937x.h" 37 38 #define MIB_COUNTER_NUM 0x20 39 40 struct ksz_stats_raw { 41 u64 rx_hi; 42 u64 rx_undersize; 43 u64 rx_fragments; 44 u64 rx_oversize; 45 u64 rx_jabbers; 46 u64 rx_symbol_err; 47 u64 rx_crc_err; 48 u64 rx_align_err; 49 u64 rx_mac_ctrl; 50 u64 rx_pause; 51 u64 rx_bcast; 52 u64 rx_mcast; 53 u64 rx_ucast; 54 u64 rx_64_or_less; 55 u64 rx_65_127; 56 u64 rx_128_255; 57 u64 rx_256_511; 58 u64 rx_512_1023; 59 u64 rx_1024_1522; 60 u64 rx_1523_2000; 61 u64 rx_2001; 62 u64 tx_hi; 63 u64 tx_late_col; 64 u64 tx_pause; 65 u64 tx_bcast; 66 u64 tx_mcast; 67 u64 tx_ucast; 68 u64 tx_deferred; 69 u64 tx_total_col; 70 u64 tx_exc_col; 71 u64 tx_single_col; 72 u64 tx_mult_col; 73 u64 rx_total; 74 u64 tx_total; 75 u64 rx_discards; 76 u64 tx_discards; 77 }; 78 79 struct ksz88xx_stats_raw { 80 u64 rx; 81 u64 rx_hi; 82 u64 rx_undersize; 83 u64 rx_fragments; 84 u64 rx_oversize; 85 u64 rx_jabbers; 86 u64 rx_symbol_err; 87 u64 rx_crc_err; 88 u64 rx_align_err; 89 u64 rx_mac_ctrl; 90 u64 rx_pause; 91 u64 rx_bcast; 92 u64 rx_mcast; 93 u64 rx_ucast; 94 u64 rx_64_or_less; 95 u64 rx_65_127; 96 u64 rx_128_255; 97 u64 rx_256_511; 98 u64 rx_512_1023; 99 u64 rx_1024_1522; 100 u64 tx; 101 u64 tx_hi; 102 u64 tx_late_col; 103 u64 tx_pause; 104 u64 tx_bcast; 105 u64 tx_mcast; 106 u64 tx_ucast; 107 u64 tx_deferred; 108 u64 tx_total_col; 109 u64 tx_exc_col; 110 u64 tx_single_col; 111 u64 tx_mult_col; 112 u64 rx_discards; 113 u64 tx_discards; 114 }; 115 116 static const struct ksz_mib_names ksz88xx_mib_names[] = { 117 { 0x00, "rx" }, 118 { 0x01, "rx_hi" }, 119 { 0x02, "rx_undersize" }, 120 { 0x03, "rx_fragments" }, 121 { 0x04, "rx_oversize" }, 122 { 0x05, "rx_jabbers" }, 123 { 0x06, "rx_symbol_err" }, 124 { 0x07, "rx_crc_err" }, 125 { 0x08, "rx_align_err" }, 126 { 0x09, "rx_mac_ctrl" }, 127 { 0x0a, "rx_pause" }, 128 { 0x0b, "rx_bcast" }, 129 { 0x0c, "rx_mcast" }, 130 { 0x0d, "rx_ucast" }, 131 { 0x0e, "rx_64_or_less" }, 132 { 0x0f, "rx_65_127" }, 133 { 0x10, "rx_128_255" }, 134 { 0x11, "rx_256_511" }, 135 { 0x12, "rx_512_1023" }, 136 { 0x13, "rx_1024_1522" }, 137 { 0x14, "tx" }, 138 { 0x15, "tx_hi" }, 139 { 0x16, "tx_late_col" }, 140 { 0x17, "tx_pause" }, 141 { 0x18, "tx_bcast" }, 142 { 0x19, "tx_mcast" }, 143 { 0x1a, "tx_ucast" }, 144 { 0x1b, "tx_deferred" }, 145 { 0x1c, "tx_total_col" }, 146 { 0x1d, "tx_exc_col" }, 147 { 0x1e, "tx_single_col" }, 148 { 0x1f, "tx_mult_col" }, 149 { 0x100, "rx_discards" }, 150 { 0x101, "tx_discards" }, 151 }; 152 153 static const struct ksz_mib_names ksz9477_mib_names[] = { 154 { 0x00, "rx_hi" }, 155 { 0x01, "rx_undersize" }, 156 { 0x02, "rx_fragments" }, 157 { 0x03, "rx_oversize" }, 158 { 0x04, "rx_jabbers" }, 159 { 0x05, "rx_symbol_err" }, 160 { 0x06, "rx_crc_err" }, 161 { 0x07, "rx_align_err" }, 162 { 0x08, "rx_mac_ctrl" }, 163 { 0x09, "rx_pause" }, 164 { 0x0A, "rx_bcast" }, 165 { 0x0B, "rx_mcast" }, 166 { 0x0C, "rx_ucast" }, 167 { 0x0D, "rx_64_or_less" }, 168 { 0x0E, "rx_65_127" }, 169 { 0x0F, "rx_128_255" }, 170 { 0x10, "rx_256_511" }, 171 { 0x11, "rx_512_1023" }, 172 { 0x12, "rx_1024_1522" }, 173 { 0x13, "rx_1523_2000" }, 174 { 0x14, "rx_2001" }, 175 { 0x15, "tx_hi" }, 176 { 0x16, "tx_late_col" }, 177 { 0x17, "tx_pause" }, 178 { 0x18, "tx_bcast" }, 179 { 0x19, "tx_mcast" }, 180 { 0x1A, "tx_ucast" }, 181 { 0x1B, "tx_deferred" }, 182 { 0x1C, "tx_total_col" }, 183 { 0x1D, "tx_exc_col" }, 184 { 0x1E, "tx_single_col" }, 185 { 0x1F, "tx_mult_col" }, 186 { 0x80, "rx_total" }, 187 { 0x81, "tx_total" }, 188 { 0x82, "rx_discards" }, 189 { 0x83, "tx_discards" }, 190 }; 191 192 struct ksz_driver_strength_prop { 193 const char *name; 194 int offset; 195 int value; 196 }; 197 198 enum ksz_driver_strength_type { 199 KSZ_DRIVER_STRENGTH_HI, 200 KSZ_DRIVER_STRENGTH_LO, 201 KSZ_DRIVER_STRENGTH_IO, 202 }; 203 204 /** 205 * struct ksz_drive_strength - drive strength mapping 206 * @reg_val: register value 207 * @microamp: microamp value 208 */ 209 struct ksz_drive_strength { 210 u32 reg_val; 211 u32 microamp; 212 }; 213 214 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants 215 * 216 * This values are not documented in KSZ9477 variants but confirmed by 217 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893 218 * and KSZ8563 are using same register (drive strength) settings like KSZ8795. 219 * 220 * Documentation in KSZ8795CLX provides more information with some 221 * recommendations: 222 * - for high speed signals 223 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using 224 * 2.5V or 3.3V VDDIO. 225 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with 226 * using 1.8V VDDIO. 227 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V 228 * or 3.3V VDDIO. 229 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO. 230 * 5. In same interface, the heavy loading should use higher one of the 231 * drive current strength. 232 * - for low speed signals 233 * 1. 3.3V VDDIO, use either 4 mA or 8 mA. 234 * 2. 2.5V VDDIO, use either 8 mA or 12 mA. 235 * 3. 1.8V VDDIO, use either 12 mA or 16 mA. 236 * 4. If it is heavy loading, can use higher drive current strength. 237 */ 238 static const struct ksz_drive_strength ksz9477_drive_strengths[] = { 239 { SW_DRIVE_STRENGTH_2MA, 2000 }, 240 { SW_DRIVE_STRENGTH_4MA, 4000 }, 241 { SW_DRIVE_STRENGTH_8MA, 8000 }, 242 { SW_DRIVE_STRENGTH_12MA, 12000 }, 243 { SW_DRIVE_STRENGTH_16MA, 16000 }, 244 { SW_DRIVE_STRENGTH_20MA, 20000 }, 245 { SW_DRIVE_STRENGTH_24MA, 24000 }, 246 { SW_DRIVE_STRENGTH_28MA, 28000 }, 247 }; 248 249 /* ksz8830_drive_strengths - Drive strength mapping for KSZ8830, KSZ8873, .. 250 * variants. 251 * This values are documented in KSZ8873 and KSZ8863 datasheets. 252 */ 253 static const struct ksz_drive_strength ksz8830_drive_strengths[] = { 254 { 0, 8000 }, 255 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 }, 256 }; 257 258 static void ksz8830_phylink_mac_config(struct phylink_config *config, 259 unsigned int mode, 260 const struct phylink_link_state *state); 261 static void ksz_phylink_mac_config(struct phylink_config *config, 262 unsigned int mode, 263 const struct phylink_link_state *state); 264 static void ksz_phylink_mac_link_down(struct phylink_config *config, 265 unsigned int mode, 266 phy_interface_t interface); 267 268 static const struct phylink_mac_ops ksz8830_phylink_mac_ops = { 269 .mac_config = ksz8830_phylink_mac_config, 270 .mac_link_down = ksz_phylink_mac_link_down, 271 .mac_link_up = ksz8_phylink_mac_link_up, 272 }; 273 274 static const struct phylink_mac_ops ksz8_phylink_mac_ops = { 275 .mac_config = ksz_phylink_mac_config, 276 .mac_link_down = ksz_phylink_mac_link_down, 277 .mac_link_up = ksz8_phylink_mac_link_up, 278 }; 279 280 static const struct ksz_dev_ops ksz88x3_dev_ops = { 281 .setup = ksz8_setup, 282 .get_port_addr = ksz8_get_port_addr, 283 .cfg_port_member = ksz8_cfg_port_member, 284 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 285 .port_setup = ksz8_port_setup, 286 .r_phy = ksz8_r_phy, 287 .w_phy = ksz8_w_phy, 288 .r_mib_cnt = ksz8_r_mib_cnt, 289 .r_mib_pkt = ksz8_r_mib_pkt, 290 .r_mib_stat64 = ksz88xx_r_mib_stats64, 291 .freeze_mib = ksz8_freeze_mib, 292 .port_init_cnt = ksz8_port_init_cnt, 293 .fdb_dump = ksz8_fdb_dump, 294 .fdb_add = ksz8_fdb_add, 295 .fdb_del = ksz8_fdb_del, 296 .mdb_add = ksz8_mdb_add, 297 .mdb_del = ksz8_mdb_del, 298 .vlan_filtering = ksz8_port_vlan_filtering, 299 .vlan_add = ksz8_port_vlan_add, 300 .vlan_del = ksz8_port_vlan_del, 301 .mirror_add = ksz8_port_mirror_add, 302 .mirror_del = ksz8_port_mirror_del, 303 .get_caps = ksz8_get_caps, 304 .config_cpu_port = ksz8_config_cpu_port, 305 .enable_stp_addr = ksz8_enable_stp_addr, 306 .reset = ksz8_reset_switch, 307 .init = ksz8_switch_init, 308 .exit = ksz8_switch_exit, 309 .change_mtu = ksz8_change_mtu, 310 .pme_write8 = ksz8_pme_write8, 311 .pme_pread8 = ksz8_pme_pread8, 312 .pme_pwrite8 = ksz8_pme_pwrite8, 313 }; 314 315 static const struct ksz_dev_ops ksz87xx_dev_ops = { 316 .setup = ksz8_setup, 317 .get_port_addr = ksz8_get_port_addr, 318 .cfg_port_member = ksz8_cfg_port_member, 319 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 320 .port_setup = ksz8_port_setup, 321 .r_phy = ksz8_r_phy, 322 .w_phy = ksz8_w_phy, 323 .r_mib_cnt = ksz8_r_mib_cnt, 324 .r_mib_pkt = ksz8_r_mib_pkt, 325 .r_mib_stat64 = ksz_r_mib_stats64, 326 .freeze_mib = ksz8_freeze_mib, 327 .port_init_cnt = ksz8_port_init_cnt, 328 .fdb_dump = ksz8_fdb_dump, 329 .fdb_add = ksz8_fdb_add, 330 .fdb_del = ksz8_fdb_del, 331 .mdb_add = ksz8_mdb_add, 332 .mdb_del = ksz8_mdb_del, 333 .vlan_filtering = ksz8_port_vlan_filtering, 334 .vlan_add = ksz8_port_vlan_add, 335 .vlan_del = ksz8_port_vlan_del, 336 .mirror_add = ksz8_port_mirror_add, 337 .mirror_del = ksz8_port_mirror_del, 338 .get_caps = ksz8_get_caps, 339 .config_cpu_port = ksz8_config_cpu_port, 340 .enable_stp_addr = ksz8_enable_stp_addr, 341 .reset = ksz8_reset_switch, 342 .init = ksz8_switch_init, 343 .exit = ksz8_switch_exit, 344 .change_mtu = ksz8_change_mtu, 345 .pme_write8 = ksz8_pme_write8, 346 .pme_pread8 = ksz8_pme_pread8, 347 .pme_pwrite8 = ksz8_pme_pwrite8, 348 }; 349 350 static void ksz9477_phylink_mac_link_up(struct phylink_config *config, 351 struct phy_device *phydev, 352 unsigned int mode, 353 phy_interface_t interface, 354 int speed, int duplex, bool tx_pause, 355 bool rx_pause); 356 357 static const struct phylink_mac_ops ksz9477_phylink_mac_ops = { 358 .mac_config = ksz_phylink_mac_config, 359 .mac_link_down = ksz_phylink_mac_link_down, 360 .mac_link_up = ksz9477_phylink_mac_link_up, 361 }; 362 363 static const struct ksz_dev_ops ksz9477_dev_ops = { 364 .setup = ksz9477_setup, 365 .get_port_addr = ksz9477_get_port_addr, 366 .cfg_port_member = ksz9477_cfg_port_member, 367 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 368 .port_setup = ksz9477_port_setup, 369 .set_ageing_time = ksz9477_set_ageing_time, 370 .r_phy = ksz9477_r_phy, 371 .w_phy = ksz9477_w_phy, 372 .r_mib_cnt = ksz9477_r_mib_cnt, 373 .r_mib_pkt = ksz9477_r_mib_pkt, 374 .r_mib_stat64 = ksz_r_mib_stats64, 375 .freeze_mib = ksz9477_freeze_mib, 376 .port_init_cnt = ksz9477_port_init_cnt, 377 .vlan_filtering = ksz9477_port_vlan_filtering, 378 .vlan_add = ksz9477_port_vlan_add, 379 .vlan_del = ksz9477_port_vlan_del, 380 .mirror_add = ksz9477_port_mirror_add, 381 .mirror_del = ksz9477_port_mirror_del, 382 .get_caps = ksz9477_get_caps, 383 .fdb_dump = ksz9477_fdb_dump, 384 .fdb_add = ksz9477_fdb_add, 385 .fdb_del = ksz9477_fdb_del, 386 .mdb_add = ksz9477_mdb_add, 387 .mdb_del = ksz9477_mdb_del, 388 .change_mtu = ksz9477_change_mtu, 389 .pme_write8 = ksz_write8, 390 .pme_pread8 = ksz_pread8, 391 .pme_pwrite8 = ksz_pwrite8, 392 .config_cpu_port = ksz9477_config_cpu_port, 393 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc, 394 .enable_stp_addr = ksz9477_enable_stp_addr, 395 .reset = ksz9477_reset_switch, 396 .init = ksz9477_switch_init, 397 .exit = ksz9477_switch_exit, 398 }; 399 400 static const struct phylink_mac_ops lan937x_phylink_mac_ops = { 401 .mac_config = ksz_phylink_mac_config, 402 .mac_link_down = ksz_phylink_mac_link_down, 403 .mac_link_up = ksz9477_phylink_mac_link_up, 404 }; 405 406 static const struct ksz_dev_ops lan937x_dev_ops = { 407 .setup = lan937x_setup, 408 .teardown = lan937x_teardown, 409 .get_port_addr = ksz9477_get_port_addr, 410 .cfg_port_member = ksz9477_cfg_port_member, 411 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 412 .port_setup = lan937x_port_setup, 413 .set_ageing_time = lan937x_set_ageing_time, 414 .r_phy = lan937x_r_phy, 415 .w_phy = lan937x_w_phy, 416 .r_mib_cnt = ksz9477_r_mib_cnt, 417 .r_mib_pkt = ksz9477_r_mib_pkt, 418 .r_mib_stat64 = ksz_r_mib_stats64, 419 .freeze_mib = ksz9477_freeze_mib, 420 .port_init_cnt = ksz9477_port_init_cnt, 421 .vlan_filtering = ksz9477_port_vlan_filtering, 422 .vlan_add = ksz9477_port_vlan_add, 423 .vlan_del = ksz9477_port_vlan_del, 424 .mirror_add = ksz9477_port_mirror_add, 425 .mirror_del = ksz9477_port_mirror_del, 426 .get_caps = lan937x_phylink_get_caps, 427 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 428 .fdb_dump = ksz9477_fdb_dump, 429 .fdb_add = ksz9477_fdb_add, 430 .fdb_del = ksz9477_fdb_del, 431 .mdb_add = ksz9477_mdb_add, 432 .mdb_del = ksz9477_mdb_del, 433 .change_mtu = lan937x_change_mtu, 434 .config_cpu_port = lan937x_config_cpu_port, 435 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 436 .enable_stp_addr = ksz9477_enable_stp_addr, 437 .reset = lan937x_reset_switch, 438 .init = lan937x_switch_init, 439 .exit = lan937x_switch_exit, 440 }; 441 442 static const u16 ksz8795_regs[] = { 443 [REG_SW_MAC_ADDR] = 0x68, 444 [REG_IND_CTRL_0] = 0x6E, 445 [REG_IND_DATA_8] = 0x70, 446 [REG_IND_DATA_CHECK] = 0x72, 447 [REG_IND_DATA_HI] = 0x71, 448 [REG_IND_DATA_LO] = 0x75, 449 [REG_IND_MIB_CHECK] = 0x74, 450 [REG_IND_BYTE] = 0xA0, 451 [P_FORCE_CTRL] = 0x0C, 452 [P_LINK_STATUS] = 0x0E, 453 [P_LOCAL_CTRL] = 0x07, 454 [P_NEG_RESTART_CTRL] = 0x0D, 455 [P_REMOTE_STATUS] = 0x08, 456 [P_SPEED_STATUS] = 0x09, 457 [S_TAIL_TAG_CTRL] = 0x0C, 458 [P_STP_CTRL] = 0x02, 459 [S_START_CTRL] = 0x01, 460 [S_BROADCAST_CTRL] = 0x06, 461 [S_MULTICAST_CTRL] = 0x04, 462 [P_XMII_CTRL_0] = 0x06, 463 [P_XMII_CTRL_1] = 0x06, 464 [REG_SW_PME_CTRL] = 0x8003, 465 [REG_PORT_PME_STATUS] = 0x8003, 466 [REG_PORT_PME_CTRL] = 0x8007, 467 }; 468 469 static const u32 ksz8795_masks[] = { 470 [PORT_802_1P_REMAPPING] = BIT(7), 471 [SW_TAIL_TAG_ENABLE] = BIT(1), 472 [MIB_COUNTER_OVERFLOW] = BIT(6), 473 [MIB_COUNTER_VALID] = BIT(5), 474 [VLAN_TABLE_FID] = GENMASK(6, 0), 475 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 476 [VLAN_TABLE_VALID] = BIT(12), 477 [STATIC_MAC_TABLE_VALID] = BIT(21), 478 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 479 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 480 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 481 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 482 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 483 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 484 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 485 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 486 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 487 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 488 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 489 [P_MII_TX_FLOW_CTRL] = BIT(5), 490 [P_MII_RX_FLOW_CTRL] = BIT(5), 491 }; 492 493 static const u8 ksz8795_xmii_ctrl0[] = { 494 [P_MII_100MBIT] = 0, 495 [P_MII_10MBIT] = 1, 496 [P_MII_FULL_DUPLEX] = 0, 497 [P_MII_HALF_DUPLEX] = 1, 498 }; 499 500 static const u8 ksz8795_xmii_ctrl1[] = { 501 [P_RGMII_SEL] = 3, 502 [P_GMII_SEL] = 2, 503 [P_RMII_SEL] = 1, 504 [P_MII_SEL] = 0, 505 [P_GMII_1GBIT] = 1, 506 [P_GMII_NOT_1GBIT] = 0, 507 }; 508 509 static const u8 ksz8795_shifts[] = { 510 [VLAN_TABLE_MEMBERSHIP_S] = 7, 511 [VLAN_TABLE] = 16, 512 [STATIC_MAC_FWD_PORTS] = 16, 513 [STATIC_MAC_FID] = 24, 514 [DYNAMIC_MAC_ENTRIES_H] = 3, 515 [DYNAMIC_MAC_ENTRIES] = 29, 516 [DYNAMIC_MAC_FID] = 16, 517 [DYNAMIC_MAC_TIMESTAMP] = 27, 518 [DYNAMIC_MAC_SRC_PORT] = 24, 519 }; 520 521 static const u16 ksz8863_regs[] = { 522 [REG_SW_MAC_ADDR] = 0x70, 523 [REG_IND_CTRL_0] = 0x79, 524 [REG_IND_DATA_8] = 0x7B, 525 [REG_IND_DATA_CHECK] = 0x7B, 526 [REG_IND_DATA_HI] = 0x7C, 527 [REG_IND_DATA_LO] = 0x80, 528 [REG_IND_MIB_CHECK] = 0x80, 529 [P_FORCE_CTRL] = 0x0C, 530 [P_LINK_STATUS] = 0x0E, 531 [P_LOCAL_CTRL] = 0x0C, 532 [P_NEG_RESTART_CTRL] = 0x0D, 533 [P_REMOTE_STATUS] = 0x0E, 534 [P_SPEED_STATUS] = 0x0F, 535 [S_TAIL_TAG_CTRL] = 0x03, 536 [P_STP_CTRL] = 0x02, 537 [S_START_CTRL] = 0x01, 538 [S_BROADCAST_CTRL] = 0x06, 539 [S_MULTICAST_CTRL] = 0x04, 540 }; 541 542 static const u32 ksz8863_masks[] = { 543 [PORT_802_1P_REMAPPING] = BIT(3), 544 [SW_TAIL_TAG_ENABLE] = BIT(6), 545 [MIB_COUNTER_OVERFLOW] = BIT(7), 546 [MIB_COUNTER_VALID] = BIT(6), 547 [VLAN_TABLE_FID] = GENMASK(15, 12), 548 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 549 [VLAN_TABLE_VALID] = BIT(19), 550 [STATIC_MAC_TABLE_VALID] = BIT(19), 551 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 552 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 553 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 554 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 555 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 556 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 557 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 558 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 559 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 560 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 561 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 562 }; 563 564 static u8 ksz8863_shifts[] = { 565 [VLAN_TABLE_MEMBERSHIP_S] = 16, 566 [STATIC_MAC_FWD_PORTS] = 16, 567 [STATIC_MAC_FID] = 22, 568 [DYNAMIC_MAC_ENTRIES_H] = 8, 569 [DYNAMIC_MAC_ENTRIES] = 24, 570 [DYNAMIC_MAC_FID] = 16, 571 [DYNAMIC_MAC_TIMESTAMP] = 22, 572 [DYNAMIC_MAC_SRC_PORT] = 20, 573 }; 574 575 static const u16 ksz9477_regs[] = { 576 [REG_SW_MAC_ADDR] = 0x0302, 577 [P_STP_CTRL] = 0x0B04, 578 [S_START_CTRL] = 0x0300, 579 [S_BROADCAST_CTRL] = 0x0332, 580 [S_MULTICAST_CTRL] = 0x0331, 581 [P_XMII_CTRL_0] = 0x0300, 582 [P_XMII_CTRL_1] = 0x0301, 583 [REG_SW_PME_CTRL] = 0x0006, 584 [REG_PORT_PME_STATUS] = 0x0013, 585 [REG_PORT_PME_CTRL] = 0x0017, 586 }; 587 588 static const u32 ksz9477_masks[] = { 589 [ALU_STAT_WRITE] = 0, 590 [ALU_STAT_READ] = 1, 591 [P_MII_TX_FLOW_CTRL] = BIT(5), 592 [P_MII_RX_FLOW_CTRL] = BIT(3), 593 }; 594 595 static const u8 ksz9477_shifts[] = { 596 [ALU_STAT_INDEX] = 16, 597 }; 598 599 static const u8 ksz9477_xmii_ctrl0[] = { 600 [P_MII_100MBIT] = 1, 601 [P_MII_10MBIT] = 0, 602 [P_MII_FULL_DUPLEX] = 1, 603 [P_MII_HALF_DUPLEX] = 0, 604 }; 605 606 static const u8 ksz9477_xmii_ctrl1[] = { 607 [P_RGMII_SEL] = 0, 608 [P_RMII_SEL] = 1, 609 [P_GMII_SEL] = 2, 610 [P_MII_SEL] = 3, 611 [P_GMII_1GBIT] = 0, 612 [P_GMII_NOT_1GBIT] = 1, 613 }; 614 615 static const u32 lan937x_masks[] = { 616 [ALU_STAT_WRITE] = 1, 617 [ALU_STAT_READ] = 2, 618 [P_MII_TX_FLOW_CTRL] = BIT(5), 619 [P_MII_RX_FLOW_CTRL] = BIT(3), 620 }; 621 622 static const u8 lan937x_shifts[] = { 623 [ALU_STAT_INDEX] = 8, 624 }; 625 626 static const struct regmap_range ksz8563_valid_regs[] = { 627 regmap_reg_range(0x0000, 0x0003), 628 regmap_reg_range(0x0006, 0x0006), 629 regmap_reg_range(0x000f, 0x001f), 630 regmap_reg_range(0x0100, 0x0100), 631 regmap_reg_range(0x0104, 0x0107), 632 regmap_reg_range(0x010d, 0x010d), 633 regmap_reg_range(0x0110, 0x0113), 634 regmap_reg_range(0x0120, 0x012b), 635 regmap_reg_range(0x0201, 0x0201), 636 regmap_reg_range(0x0210, 0x0213), 637 regmap_reg_range(0x0300, 0x0300), 638 regmap_reg_range(0x0302, 0x031b), 639 regmap_reg_range(0x0320, 0x032b), 640 regmap_reg_range(0x0330, 0x0336), 641 regmap_reg_range(0x0338, 0x033e), 642 regmap_reg_range(0x0340, 0x035f), 643 regmap_reg_range(0x0370, 0x0370), 644 regmap_reg_range(0x0378, 0x0378), 645 regmap_reg_range(0x037c, 0x037d), 646 regmap_reg_range(0x0390, 0x0393), 647 regmap_reg_range(0x0400, 0x040e), 648 regmap_reg_range(0x0410, 0x042f), 649 regmap_reg_range(0x0500, 0x0519), 650 regmap_reg_range(0x0520, 0x054b), 651 regmap_reg_range(0x0550, 0x05b3), 652 653 /* port 1 */ 654 regmap_reg_range(0x1000, 0x1001), 655 regmap_reg_range(0x1004, 0x100b), 656 regmap_reg_range(0x1013, 0x1013), 657 regmap_reg_range(0x1017, 0x1017), 658 regmap_reg_range(0x101b, 0x101b), 659 regmap_reg_range(0x101f, 0x1021), 660 regmap_reg_range(0x1030, 0x1030), 661 regmap_reg_range(0x1100, 0x1111), 662 regmap_reg_range(0x111a, 0x111d), 663 regmap_reg_range(0x1122, 0x1127), 664 regmap_reg_range(0x112a, 0x112b), 665 regmap_reg_range(0x1136, 0x1139), 666 regmap_reg_range(0x113e, 0x113f), 667 regmap_reg_range(0x1400, 0x1401), 668 regmap_reg_range(0x1403, 0x1403), 669 regmap_reg_range(0x1410, 0x1417), 670 regmap_reg_range(0x1420, 0x1423), 671 regmap_reg_range(0x1500, 0x1507), 672 regmap_reg_range(0x1600, 0x1612), 673 regmap_reg_range(0x1800, 0x180f), 674 regmap_reg_range(0x1900, 0x1907), 675 regmap_reg_range(0x1914, 0x191b), 676 regmap_reg_range(0x1a00, 0x1a03), 677 regmap_reg_range(0x1a04, 0x1a08), 678 regmap_reg_range(0x1b00, 0x1b01), 679 regmap_reg_range(0x1b04, 0x1b04), 680 regmap_reg_range(0x1c00, 0x1c05), 681 regmap_reg_range(0x1c08, 0x1c1b), 682 683 /* port 2 */ 684 regmap_reg_range(0x2000, 0x2001), 685 regmap_reg_range(0x2004, 0x200b), 686 regmap_reg_range(0x2013, 0x2013), 687 regmap_reg_range(0x2017, 0x2017), 688 regmap_reg_range(0x201b, 0x201b), 689 regmap_reg_range(0x201f, 0x2021), 690 regmap_reg_range(0x2030, 0x2030), 691 regmap_reg_range(0x2100, 0x2111), 692 regmap_reg_range(0x211a, 0x211d), 693 regmap_reg_range(0x2122, 0x2127), 694 regmap_reg_range(0x212a, 0x212b), 695 regmap_reg_range(0x2136, 0x2139), 696 regmap_reg_range(0x213e, 0x213f), 697 regmap_reg_range(0x2400, 0x2401), 698 regmap_reg_range(0x2403, 0x2403), 699 regmap_reg_range(0x2410, 0x2417), 700 regmap_reg_range(0x2420, 0x2423), 701 regmap_reg_range(0x2500, 0x2507), 702 regmap_reg_range(0x2600, 0x2612), 703 regmap_reg_range(0x2800, 0x280f), 704 regmap_reg_range(0x2900, 0x2907), 705 regmap_reg_range(0x2914, 0x291b), 706 regmap_reg_range(0x2a00, 0x2a03), 707 regmap_reg_range(0x2a04, 0x2a08), 708 regmap_reg_range(0x2b00, 0x2b01), 709 regmap_reg_range(0x2b04, 0x2b04), 710 regmap_reg_range(0x2c00, 0x2c05), 711 regmap_reg_range(0x2c08, 0x2c1b), 712 713 /* port 3 */ 714 regmap_reg_range(0x3000, 0x3001), 715 regmap_reg_range(0x3004, 0x300b), 716 regmap_reg_range(0x3013, 0x3013), 717 regmap_reg_range(0x3017, 0x3017), 718 regmap_reg_range(0x301b, 0x301b), 719 regmap_reg_range(0x301f, 0x3021), 720 regmap_reg_range(0x3030, 0x3030), 721 regmap_reg_range(0x3300, 0x3301), 722 regmap_reg_range(0x3303, 0x3303), 723 regmap_reg_range(0x3400, 0x3401), 724 regmap_reg_range(0x3403, 0x3403), 725 regmap_reg_range(0x3410, 0x3417), 726 regmap_reg_range(0x3420, 0x3423), 727 regmap_reg_range(0x3500, 0x3507), 728 regmap_reg_range(0x3600, 0x3612), 729 regmap_reg_range(0x3800, 0x380f), 730 regmap_reg_range(0x3900, 0x3907), 731 regmap_reg_range(0x3914, 0x391b), 732 regmap_reg_range(0x3a00, 0x3a03), 733 regmap_reg_range(0x3a04, 0x3a08), 734 regmap_reg_range(0x3b00, 0x3b01), 735 regmap_reg_range(0x3b04, 0x3b04), 736 regmap_reg_range(0x3c00, 0x3c05), 737 regmap_reg_range(0x3c08, 0x3c1b), 738 }; 739 740 static const struct regmap_access_table ksz8563_register_set = { 741 .yes_ranges = ksz8563_valid_regs, 742 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 743 }; 744 745 static const struct regmap_range ksz9477_valid_regs[] = { 746 regmap_reg_range(0x0000, 0x0003), 747 regmap_reg_range(0x0006, 0x0006), 748 regmap_reg_range(0x0010, 0x001f), 749 regmap_reg_range(0x0100, 0x0100), 750 regmap_reg_range(0x0103, 0x0107), 751 regmap_reg_range(0x010d, 0x010d), 752 regmap_reg_range(0x0110, 0x0113), 753 regmap_reg_range(0x0120, 0x012b), 754 regmap_reg_range(0x0201, 0x0201), 755 regmap_reg_range(0x0210, 0x0213), 756 regmap_reg_range(0x0300, 0x0300), 757 regmap_reg_range(0x0302, 0x031b), 758 regmap_reg_range(0x0320, 0x032b), 759 regmap_reg_range(0x0330, 0x0336), 760 regmap_reg_range(0x0338, 0x033b), 761 regmap_reg_range(0x033e, 0x033e), 762 regmap_reg_range(0x0340, 0x035f), 763 regmap_reg_range(0x0370, 0x0370), 764 regmap_reg_range(0x0378, 0x0378), 765 regmap_reg_range(0x037c, 0x037d), 766 regmap_reg_range(0x0390, 0x0393), 767 regmap_reg_range(0x0400, 0x040e), 768 regmap_reg_range(0x0410, 0x042f), 769 regmap_reg_range(0x0444, 0x044b), 770 regmap_reg_range(0x0450, 0x046f), 771 regmap_reg_range(0x0500, 0x0519), 772 regmap_reg_range(0x0520, 0x054b), 773 regmap_reg_range(0x0550, 0x05b3), 774 regmap_reg_range(0x0604, 0x060b), 775 regmap_reg_range(0x0610, 0x0612), 776 regmap_reg_range(0x0614, 0x062c), 777 regmap_reg_range(0x0640, 0x0645), 778 regmap_reg_range(0x0648, 0x064d), 779 780 /* port 1 */ 781 regmap_reg_range(0x1000, 0x1001), 782 regmap_reg_range(0x1013, 0x1013), 783 regmap_reg_range(0x1017, 0x1017), 784 regmap_reg_range(0x101b, 0x101b), 785 regmap_reg_range(0x101f, 0x1020), 786 regmap_reg_range(0x1030, 0x1030), 787 regmap_reg_range(0x1100, 0x1115), 788 regmap_reg_range(0x111a, 0x111f), 789 regmap_reg_range(0x1120, 0x112b), 790 regmap_reg_range(0x1134, 0x113b), 791 regmap_reg_range(0x113c, 0x113f), 792 regmap_reg_range(0x1400, 0x1401), 793 regmap_reg_range(0x1403, 0x1403), 794 regmap_reg_range(0x1410, 0x1417), 795 regmap_reg_range(0x1420, 0x1423), 796 regmap_reg_range(0x1500, 0x1507), 797 regmap_reg_range(0x1600, 0x1613), 798 regmap_reg_range(0x1800, 0x180f), 799 regmap_reg_range(0x1820, 0x1827), 800 regmap_reg_range(0x1830, 0x1837), 801 regmap_reg_range(0x1840, 0x184b), 802 regmap_reg_range(0x1900, 0x1907), 803 regmap_reg_range(0x1914, 0x191b), 804 regmap_reg_range(0x1920, 0x1920), 805 regmap_reg_range(0x1923, 0x1927), 806 regmap_reg_range(0x1a00, 0x1a03), 807 regmap_reg_range(0x1a04, 0x1a07), 808 regmap_reg_range(0x1b00, 0x1b01), 809 regmap_reg_range(0x1b04, 0x1b04), 810 regmap_reg_range(0x1c00, 0x1c05), 811 regmap_reg_range(0x1c08, 0x1c1b), 812 813 /* port 2 */ 814 regmap_reg_range(0x2000, 0x2001), 815 regmap_reg_range(0x2013, 0x2013), 816 regmap_reg_range(0x2017, 0x2017), 817 regmap_reg_range(0x201b, 0x201b), 818 regmap_reg_range(0x201f, 0x2020), 819 regmap_reg_range(0x2030, 0x2030), 820 regmap_reg_range(0x2100, 0x2115), 821 regmap_reg_range(0x211a, 0x211f), 822 regmap_reg_range(0x2120, 0x212b), 823 regmap_reg_range(0x2134, 0x213b), 824 regmap_reg_range(0x213c, 0x213f), 825 regmap_reg_range(0x2400, 0x2401), 826 regmap_reg_range(0x2403, 0x2403), 827 regmap_reg_range(0x2410, 0x2417), 828 regmap_reg_range(0x2420, 0x2423), 829 regmap_reg_range(0x2500, 0x2507), 830 regmap_reg_range(0x2600, 0x2613), 831 regmap_reg_range(0x2800, 0x280f), 832 regmap_reg_range(0x2820, 0x2827), 833 regmap_reg_range(0x2830, 0x2837), 834 regmap_reg_range(0x2840, 0x284b), 835 regmap_reg_range(0x2900, 0x2907), 836 regmap_reg_range(0x2914, 0x291b), 837 regmap_reg_range(0x2920, 0x2920), 838 regmap_reg_range(0x2923, 0x2927), 839 regmap_reg_range(0x2a00, 0x2a03), 840 regmap_reg_range(0x2a04, 0x2a07), 841 regmap_reg_range(0x2b00, 0x2b01), 842 regmap_reg_range(0x2b04, 0x2b04), 843 regmap_reg_range(0x2c00, 0x2c05), 844 regmap_reg_range(0x2c08, 0x2c1b), 845 846 /* port 3 */ 847 regmap_reg_range(0x3000, 0x3001), 848 regmap_reg_range(0x3013, 0x3013), 849 regmap_reg_range(0x3017, 0x3017), 850 regmap_reg_range(0x301b, 0x301b), 851 regmap_reg_range(0x301f, 0x3020), 852 regmap_reg_range(0x3030, 0x3030), 853 regmap_reg_range(0x3100, 0x3115), 854 regmap_reg_range(0x311a, 0x311f), 855 regmap_reg_range(0x3120, 0x312b), 856 regmap_reg_range(0x3134, 0x313b), 857 regmap_reg_range(0x313c, 0x313f), 858 regmap_reg_range(0x3400, 0x3401), 859 regmap_reg_range(0x3403, 0x3403), 860 regmap_reg_range(0x3410, 0x3417), 861 regmap_reg_range(0x3420, 0x3423), 862 regmap_reg_range(0x3500, 0x3507), 863 regmap_reg_range(0x3600, 0x3613), 864 regmap_reg_range(0x3800, 0x380f), 865 regmap_reg_range(0x3820, 0x3827), 866 regmap_reg_range(0x3830, 0x3837), 867 regmap_reg_range(0x3840, 0x384b), 868 regmap_reg_range(0x3900, 0x3907), 869 regmap_reg_range(0x3914, 0x391b), 870 regmap_reg_range(0x3920, 0x3920), 871 regmap_reg_range(0x3923, 0x3927), 872 regmap_reg_range(0x3a00, 0x3a03), 873 regmap_reg_range(0x3a04, 0x3a07), 874 regmap_reg_range(0x3b00, 0x3b01), 875 regmap_reg_range(0x3b04, 0x3b04), 876 regmap_reg_range(0x3c00, 0x3c05), 877 regmap_reg_range(0x3c08, 0x3c1b), 878 879 /* port 4 */ 880 regmap_reg_range(0x4000, 0x4001), 881 regmap_reg_range(0x4013, 0x4013), 882 regmap_reg_range(0x4017, 0x4017), 883 regmap_reg_range(0x401b, 0x401b), 884 regmap_reg_range(0x401f, 0x4020), 885 regmap_reg_range(0x4030, 0x4030), 886 regmap_reg_range(0x4100, 0x4115), 887 regmap_reg_range(0x411a, 0x411f), 888 regmap_reg_range(0x4120, 0x412b), 889 regmap_reg_range(0x4134, 0x413b), 890 regmap_reg_range(0x413c, 0x413f), 891 regmap_reg_range(0x4400, 0x4401), 892 regmap_reg_range(0x4403, 0x4403), 893 regmap_reg_range(0x4410, 0x4417), 894 regmap_reg_range(0x4420, 0x4423), 895 regmap_reg_range(0x4500, 0x4507), 896 regmap_reg_range(0x4600, 0x4613), 897 regmap_reg_range(0x4800, 0x480f), 898 regmap_reg_range(0x4820, 0x4827), 899 regmap_reg_range(0x4830, 0x4837), 900 regmap_reg_range(0x4840, 0x484b), 901 regmap_reg_range(0x4900, 0x4907), 902 regmap_reg_range(0x4914, 0x491b), 903 regmap_reg_range(0x4920, 0x4920), 904 regmap_reg_range(0x4923, 0x4927), 905 regmap_reg_range(0x4a00, 0x4a03), 906 regmap_reg_range(0x4a04, 0x4a07), 907 regmap_reg_range(0x4b00, 0x4b01), 908 regmap_reg_range(0x4b04, 0x4b04), 909 regmap_reg_range(0x4c00, 0x4c05), 910 regmap_reg_range(0x4c08, 0x4c1b), 911 912 /* port 5 */ 913 regmap_reg_range(0x5000, 0x5001), 914 regmap_reg_range(0x5013, 0x5013), 915 regmap_reg_range(0x5017, 0x5017), 916 regmap_reg_range(0x501b, 0x501b), 917 regmap_reg_range(0x501f, 0x5020), 918 regmap_reg_range(0x5030, 0x5030), 919 regmap_reg_range(0x5100, 0x5115), 920 regmap_reg_range(0x511a, 0x511f), 921 regmap_reg_range(0x5120, 0x512b), 922 regmap_reg_range(0x5134, 0x513b), 923 regmap_reg_range(0x513c, 0x513f), 924 regmap_reg_range(0x5400, 0x5401), 925 regmap_reg_range(0x5403, 0x5403), 926 regmap_reg_range(0x5410, 0x5417), 927 regmap_reg_range(0x5420, 0x5423), 928 regmap_reg_range(0x5500, 0x5507), 929 regmap_reg_range(0x5600, 0x5613), 930 regmap_reg_range(0x5800, 0x580f), 931 regmap_reg_range(0x5820, 0x5827), 932 regmap_reg_range(0x5830, 0x5837), 933 regmap_reg_range(0x5840, 0x584b), 934 regmap_reg_range(0x5900, 0x5907), 935 regmap_reg_range(0x5914, 0x591b), 936 regmap_reg_range(0x5920, 0x5920), 937 regmap_reg_range(0x5923, 0x5927), 938 regmap_reg_range(0x5a00, 0x5a03), 939 regmap_reg_range(0x5a04, 0x5a07), 940 regmap_reg_range(0x5b00, 0x5b01), 941 regmap_reg_range(0x5b04, 0x5b04), 942 regmap_reg_range(0x5c00, 0x5c05), 943 regmap_reg_range(0x5c08, 0x5c1b), 944 945 /* port 6 */ 946 regmap_reg_range(0x6000, 0x6001), 947 regmap_reg_range(0x6013, 0x6013), 948 regmap_reg_range(0x6017, 0x6017), 949 regmap_reg_range(0x601b, 0x601b), 950 regmap_reg_range(0x601f, 0x6020), 951 regmap_reg_range(0x6030, 0x6030), 952 regmap_reg_range(0x6300, 0x6301), 953 regmap_reg_range(0x6400, 0x6401), 954 regmap_reg_range(0x6403, 0x6403), 955 regmap_reg_range(0x6410, 0x6417), 956 regmap_reg_range(0x6420, 0x6423), 957 regmap_reg_range(0x6500, 0x6507), 958 regmap_reg_range(0x6600, 0x6613), 959 regmap_reg_range(0x6800, 0x680f), 960 regmap_reg_range(0x6820, 0x6827), 961 regmap_reg_range(0x6830, 0x6837), 962 regmap_reg_range(0x6840, 0x684b), 963 regmap_reg_range(0x6900, 0x6907), 964 regmap_reg_range(0x6914, 0x691b), 965 regmap_reg_range(0x6920, 0x6920), 966 regmap_reg_range(0x6923, 0x6927), 967 regmap_reg_range(0x6a00, 0x6a03), 968 regmap_reg_range(0x6a04, 0x6a07), 969 regmap_reg_range(0x6b00, 0x6b01), 970 regmap_reg_range(0x6b04, 0x6b04), 971 regmap_reg_range(0x6c00, 0x6c05), 972 regmap_reg_range(0x6c08, 0x6c1b), 973 974 /* port 7 */ 975 regmap_reg_range(0x7000, 0x7001), 976 regmap_reg_range(0x7013, 0x7013), 977 regmap_reg_range(0x7017, 0x7017), 978 regmap_reg_range(0x701b, 0x701b), 979 regmap_reg_range(0x701f, 0x7020), 980 regmap_reg_range(0x7030, 0x7030), 981 regmap_reg_range(0x7200, 0x7203), 982 regmap_reg_range(0x7206, 0x7207), 983 regmap_reg_range(0x7300, 0x7301), 984 regmap_reg_range(0x7400, 0x7401), 985 regmap_reg_range(0x7403, 0x7403), 986 regmap_reg_range(0x7410, 0x7417), 987 regmap_reg_range(0x7420, 0x7423), 988 regmap_reg_range(0x7500, 0x7507), 989 regmap_reg_range(0x7600, 0x7613), 990 regmap_reg_range(0x7800, 0x780f), 991 regmap_reg_range(0x7820, 0x7827), 992 regmap_reg_range(0x7830, 0x7837), 993 regmap_reg_range(0x7840, 0x784b), 994 regmap_reg_range(0x7900, 0x7907), 995 regmap_reg_range(0x7914, 0x791b), 996 regmap_reg_range(0x7920, 0x7920), 997 regmap_reg_range(0x7923, 0x7927), 998 regmap_reg_range(0x7a00, 0x7a03), 999 regmap_reg_range(0x7a04, 0x7a07), 1000 regmap_reg_range(0x7b00, 0x7b01), 1001 regmap_reg_range(0x7b04, 0x7b04), 1002 regmap_reg_range(0x7c00, 0x7c05), 1003 regmap_reg_range(0x7c08, 0x7c1b), 1004 }; 1005 1006 static const struct regmap_access_table ksz9477_register_set = { 1007 .yes_ranges = ksz9477_valid_regs, 1008 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 1009 }; 1010 1011 static const struct regmap_range ksz9896_valid_regs[] = { 1012 regmap_reg_range(0x0000, 0x0003), 1013 regmap_reg_range(0x0006, 0x0006), 1014 regmap_reg_range(0x0010, 0x001f), 1015 regmap_reg_range(0x0100, 0x0100), 1016 regmap_reg_range(0x0103, 0x0107), 1017 regmap_reg_range(0x010d, 0x010d), 1018 regmap_reg_range(0x0110, 0x0113), 1019 regmap_reg_range(0x0120, 0x0127), 1020 regmap_reg_range(0x0201, 0x0201), 1021 regmap_reg_range(0x0210, 0x0213), 1022 regmap_reg_range(0x0300, 0x0300), 1023 regmap_reg_range(0x0302, 0x030b), 1024 regmap_reg_range(0x0310, 0x031b), 1025 regmap_reg_range(0x0320, 0x032b), 1026 regmap_reg_range(0x0330, 0x0336), 1027 regmap_reg_range(0x0338, 0x033b), 1028 regmap_reg_range(0x033e, 0x033e), 1029 regmap_reg_range(0x0340, 0x035f), 1030 regmap_reg_range(0x0370, 0x0370), 1031 regmap_reg_range(0x0378, 0x0378), 1032 regmap_reg_range(0x037c, 0x037d), 1033 regmap_reg_range(0x0390, 0x0393), 1034 regmap_reg_range(0x0400, 0x040e), 1035 regmap_reg_range(0x0410, 0x042f), 1036 1037 /* port 1 */ 1038 regmap_reg_range(0x1000, 0x1001), 1039 regmap_reg_range(0x1013, 0x1013), 1040 regmap_reg_range(0x1017, 0x1017), 1041 regmap_reg_range(0x101b, 0x101b), 1042 regmap_reg_range(0x101f, 0x1020), 1043 regmap_reg_range(0x1030, 0x1030), 1044 regmap_reg_range(0x1100, 0x1115), 1045 regmap_reg_range(0x111a, 0x111f), 1046 regmap_reg_range(0x1122, 0x1127), 1047 regmap_reg_range(0x112a, 0x112b), 1048 regmap_reg_range(0x1136, 0x1139), 1049 regmap_reg_range(0x113e, 0x113f), 1050 regmap_reg_range(0x1400, 0x1401), 1051 regmap_reg_range(0x1403, 0x1403), 1052 regmap_reg_range(0x1410, 0x1417), 1053 regmap_reg_range(0x1420, 0x1423), 1054 regmap_reg_range(0x1500, 0x1507), 1055 regmap_reg_range(0x1600, 0x1612), 1056 regmap_reg_range(0x1800, 0x180f), 1057 regmap_reg_range(0x1820, 0x1827), 1058 regmap_reg_range(0x1830, 0x1837), 1059 regmap_reg_range(0x1840, 0x184b), 1060 regmap_reg_range(0x1900, 0x1907), 1061 regmap_reg_range(0x1914, 0x1915), 1062 regmap_reg_range(0x1a00, 0x1a03), 1063 regmap_reg_range(0x1a04, 0x1a07), 1064 regmap_reg_range(0x1b00, 0x1b01), 1065 regmap_reg_range(0x1b04, 0x1b04), 1066 1067 /* port 2 */ 1068 regmap_reg_range(0x2000, 0x2001), 1069 regmap_reg_range(0x2013, 0x2013), 1070 regmap_reg_range(0x2017, 0x2017), 1071 regmap_reg_range(0x201b, 0x201b), 1072 regmap_reg_range(0x201f, 0x2020), 1073 regmap_reg_range(0x2030, 0x2030), 1074 regmap_reg_range(0x2100, 0x2115), 1075 regmap_reg_range(0x211a, 0x211f), 1076 regmap_reg_range(0x2122, 0x2127), 1077 regmap_reg_range(0x212a, 0x212b), 1078 regmap_reg_range(0x2136, 0x2139), 1079 regmap_reg_range(0x213e, 0x213f), 1080 regmap_reg_range(0x2400, 0x2401), 1081 regmap_reg_range(0x2403, 0x2403), 1082 regmap_reg_range(0x2410, 0x2417), 1083 regmap_reg_range(0x2420, 0x2423), 1084 regmap_reg_range(0x2500, 0x2507), 1085 regmap_reg_range(0x2600, 0x2612), 1086 regmap_reg_range(0x2800, 0x280f), 1087 regmap_reg_range(0x2820, 0x2827), 1088 regmap_reg_range(0x2830, 0x2837), 1089 regmap_reg_range(0x2840, 0x284b), 1090 regmap_reg_range(0x2900, 0x2907), 1091 regmap_reg_range(0x2914, 0x2915), 1092 regmap_reg_range(0x2a00, 0x2a03), 1093 regmap_reg_range(0x2a04, 0x2a07), 1094 regmap_reg_range(0x2b00, 0x2b01), 1095 regmap_reg_range(0x2b04, 0x2b04), 1096 1097 /* port 3 */ 1098 regmap_reg_range(0x3000, 0x3001), 1099 regmap_reg_range(0x3013, 0x3013), 1100 regmap_reg_range(0x3017, 0x3017), 1101 regmap_reg_range(0x301b, 0x301b), 1102 regmap_reg_range(0x301f, 0x3020), 1103 regmap_reg_range(0x3030, 0x3030), 1104 regmap_reg_range(0x3100, 0x3115), 1105 regmap_reg_range(0x311a, 0x311f), 1106 regmap_reg_range(0x3122, 0x3127), 1107 regmap_reg_range(0x312a, 0x312b), 1108 regmap_reg_range(0x3136, 0x3139), 1109 regmap_reg_range(0x313e, 0x313f), 1110 regmap_reg_range(0x3400, 0x3401), 1111 regmap_reg_range(0x3403, 0x3403), 1112 regmap_reg_range(0x3410, 0x3417), 1113 regmap_reg_range(0x3420, 0x3423), 1114 regmap_reg_range(0x3500, 0x3507), 1115 regmap_reg_range(0x3600, 0x3612), 1116 regmap_reg_range(0x3800, 0x380f), 1117 regmap_reg_range(0x3820, 0x3827), 1118 regmap_reg_range(0x3830, 0x3837), 1119 regmap_reg_range(0x3840, 0x384b), 1120 regmap_reg_range(0x3900, 0x3907), 1121 regmap_reg_range(0x3914, 0x3915), 1122 regmap_reg_range(0x3a00, 0x3a03), 1123 regmap_reg_range(0x3a04, 0x3a07), 1124 regmap_reg_range(0x3b00, 0x3b01), 1125 regmap_reg_range(0x3b04, 0x3b04), 1126 1127 /* port 4 */ 1128 regmap_reg_range(0x4000, 0x4001), 1129 regmap_reg_range(0x4013, 0x4013), 1130 regmap_reg_range(0x4017, 0x4017), 1131 regmap_reg_range(0x401b, 0x401b), 1132 regmap_reg_range(0x401f, 0x4020), 1133 regmap_reg_range(0x4030, 0x4030), 1134 regmap_reg_range(0x4100, 0x4115), 1135 regmap_reg_range(0x411a, 0x411f), 1136 regmap_reg_range(0x4122, 0x4127), 1137 regmap_reg_range(0x412a, 0x412b), 1138 regmap_reg_range(0x4136, 0x4139), 1139 regmap_reg_range(0x413e, 0x413f), 1140 regmap_reg_range(0x4400, 0x4401), 1141 regmap_reg_range(0x4403, 0x4403), 1142 regmap_reg_range(0x4410, 0x4417), 1143 regmap_reg_range(0x4420, 0x4423), 1144 regmap_reg_range(0x4500, 0x4507), 1145 regmap_reg_range(0x4600, 0x4612), 1146 regmap_reg_range(0x4800, 0x480f), 1147 regmap_reg_range(0x4820, 0x4827), 1148 regmap_reg_range(0x4830, 0x4837), 1149 regmap_reg_range(0x4840, 0x484b), 1150 regmap_reg_range(0x4900, 0x4907), 1151 regmap_reg_range(0x4914, 0x4915), 1152 regmap_reg_range(0x4a00, 0x4a03), 1153 regmap_reg_range(0x4a04, 0x4a07), 1154 regmap_reg_range(0x4b00, 0x4b01), 1155 regmap_reg_range(0x4b04, 0x4b04), 1156 1157 /* port 5 */ 1158 regmap_reg_range(0x5000, 0x5001), 1159 regmap_reg_range(0x5013, 0x5013), 1160 regmap_reg_range(0x5017, 0x5017), 1161 regmap_reg_range(0x501b, 0x501b), 1162 regmap_reg_range(0x501f, 0x5020), 1163 regmap_reg_range(0x5030, 0x5030), 1164 regmap_reg_range(0x5100, 0x5115), 1165 regmap_reg_range(0x511a, 0x511f), 1166 regmap_reg_range(0x5122, 0x5127), 1167 regmap_reg_range(0x512a, 0x512b), 1168 regmap_reg_range(0x5136, 0x5139), 1169 regmap_reg_range(0x513e, 0x513f), 1170 regmap_reg_range(0x5400, 0x5401), 1171 regmap_reg_range(0x5403, 0x5403), 1172 regmap_reg_range(0x5410, 0x5417), 1173 regmap_reg_range(0x5420, 0x5423), 1174 regmap_reg_range(0x5500, 0x5507), 1175 regmap_reg_range(0x5600, 0x5612), 1176 regmap_reg_range(0x5800, 0x580f), 1177 regmap_reg_range(0x5820, 0x5827), 1178 regmap_reg_range(0x5830, 0x5837), 1179 regmap_reg_range(0x5840, 0x584b), 1180 regmap_reg_range(0x5900, 0x5907), 1181 regmap_reg_range(0x5914, 0x5915), 1182 regmap_reg_range(0x5a00, 0x5a03), 1183 regmap_reg_range(0x5a04, 0x5a07), 1184 regmap_reg_range(0x5b00, 0x5b01), 1185 regmap_reg_range(0x5b04, 0x5b04), 1186 1187 /* port 6 */ 1188 regmap_reg_range(0x6000, 0x6001), 1189 regmap_reg_range(0x6013, 0x6013), 1190 regmap_reg_range(0x6017, 0x6017), 1191 regmap_reg_range(0x601b, 0x601b), 1192 regmap_reg_range(0x601f, 0x6020), 1193 regmap_reg_range(0x6030, 0x6030), 1194 regmap_reg_range(0x6100, 0x6115), 1195 regmap_reg_range(0x611a, 0x611f), 1196 regmap_reg_range(0x6122, 0x6127), 1197 regmap_reg_range(0x612a, 0x612b), 1198 regmap_reg_range(0x6136, 0x6139), 1199 regmap_reg_range(0x613e, 0x613f), 1200 regmap_reg_range(0x6300, 0x6301), 1201 regmap_reg_range(0x6400, 0x6401), 1202 regmap_reg_range(0x6403, 0x6403), 1203 regmap_reg_range(0x6410, 0x6417), 1204 regmap_reg_range(0x6420, 0x6423), 1205 regmap_reg_range(0x6500, 0x6507), 1206 regmap_reg_range(0x6600, 0x6612), 1207 regmap_reg_range(0x6800, 0x680f), 1208 regmap_reg_range(0x6820, 0x6827), 1209 regmap_reg_range(0x6830, 0x6837), 1210 regmap_reg_range(0x6840, 0x684b), 1211 regmap_reg_range(0x6900, 0x6907), 1212 regmap_reg_range(0x6914, 0x6915), 1213 regmap_reg_range(0x6a00, 0x6a03), 1214 regmap_reg_range(0x6a04, 0x6a07), 1215 regmap_reg_range(0x6b00, 0x6b01), 1216 regmap_reg_range(0x6b04, 0x6b04), 1217 }; 1218 1219 static const struct regmap_access_table ksz9896_register_set = { 1220 .yes_ranges = ksz9896_valid_regs, 1221 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1222 }; 1223 1224 static const struct regmap_range ksz8873_valid_regs[] = { 1225 regmap_reg_range(0x00, 0x01), 1226 /* global control register */ 1227 regmap_reg_range(0x02, 0x0f), 1228 1229 /* port registers */ 1230 regmap_reg_range(0x10, 0x1d), 1231 regmap_reg_range(0x1e, 0x1f), 1232 regmap_reg_range(0x20, 0x2d), 1233 regmap_reg_range(0x2e, 0x2f), 1234 regmap_reg_range(0x30, 0x39), 1235 regmap_reg_range(0x3f, 0x3f), 1236 1237 /* advanced control registers */ 1238 regmap_reg_range(0x60, 0x6f), 1239 regmap_reg_range(0x70, 0x75), 1240 regmap_reg_range(0x76, 0x78), 1241 regmap_reg_range(0x79, 0x7a), 1242 regmap_reg_range(0x7b, 0x83), 1243 regmap_reg_range(0x8e, 0x99), 1244 regmap_reg_range(0x9a, 0xa5), 1245 regmap_reg_range(0xa6, 0xa6), 1246 regmap_reg_range(0xa7, 0xaa), 1247 regmap_reg_range(0xab, 0xae), 1248 regmap_reg_range(0xaf, 0xba), 1249 regmap_reg_range(0xbb, 0xbc), 1250 regmap_reg_range(0xbd, 0xbd), 1251 regmap_reg_range(0xc0, 0xc0), 1252 regmap_reg_range(0xc2, 0xc2), 1253 regmap_reg_range(0xc3, 0xc3), 1254 regmap_reg_range(0xc4, 0xc4), 1255 regmap_reg_range(0xc6, 0xc6), 1256 }; 1257 1258 static const struct regmap_access_table ksz8873_register_set = { 1259 .yes_ranges = ksz8873_valid_regs, 1260 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), 1261 }; 1262 1263 const struct ksz_chip_data ksz_switch_chips[] = { 1264 [KSZ8563] = { 1265 .chip_id = KSZ8563_CHIP_ID, 1266 .dev_name = "KSZ8563", 1267 .num_vlans = 4096, 1268 .num_alus = 4096, 1269 .num_statics = 16, 1270 .cpu_ports = 0x07, /* can be configured as cpu port */ 1271 .port_cnt = 3, /* total port count */ 1272 .port_nirqs = 3, 1273 .num_tx_queues = 4, 1274 .num_ipms = 8, 1275 .tc_cbs_supported = true, 1276 .ops = &ksz9477_dev_ops, 1277 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1278 .mib_names = ksz9477_mib_names, 1279 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1280 .reg_mib_cnt = MIB_COUNTER_NUM, 1281 .regs = ksz9477_regs, 1282 .masks = ksz9477_masks, 1283 .shifts = ksz9477_shifts, 1284 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1285 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1286 .supports_mii = {false, false, true}, 1287 .supports_rmii = {false, false, true}, 1288 .supports_rgmii = {false, false, true}, 1289 .internal_phy = {true, true, false}, 1290 .gbit_capable = {false, false, true}, 1291 .wr_table = &ksz8563_register_set, 1292 .rd_table = &ksz8563_register_set, 1293 }, 1294 1295 [KSZ8795] = { 1296 .chip_id = KSZ8795_CHIP_ID, 1297 .dev_name = "KSZ8795", 1298 .num_vlans = 4096, 1299 .num_alus = 0, 1300 .num_statics = 32, 1301 .cpu_ports = 0x10, /* can be configured as cpu port */ 1302 .port_cnt = 5, /* total cpu and user ports */ 1303 .num_tx_queues = 4, 1304 .num_ipms = 4, 1305 .ops = &ksz87xx_dev_ops, 1306 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1307 .ksz87xx_eee_link_erratum = true, 1308 .mib_names = ksz9477_mib_names, 1309 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1310 .reg_mib_cnt = MIB_COUNTER_NUM, 1311 .regs = ksz8795_regs, 1312 .masks = ksz8795_masks, 1313 .shifts = ksz8795_shifts, 1314 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1315 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1316 .supports_mii = {false, false, false, false, true}, 1317 .supports_rmii = {false, false, false, false, true}, 1318 .supports_rgmii = {false, false, false, false, true}, 1319 .internal_phy = {true, true, true, true, false}, 1320 }, 1321 1322 [KSZ8794] = { 1323 /* WARNING 1324 * ======= 1325 * KSZ8794 is similar to KSZ8795, except the port map 1326 * contains a gap between external and CPU ports, the 1327 * port map is NOT continuous. The per-port register 1328 * map is shifted accordingly too, i.e. registers at 1329 * offset 0x40 are NOT used on KSZ8794 and they ARE 1330 * used on KSZ8795 for external port 3. 1331 * external cpu 1332 * KSZ8794 0,1,2 4 1333 * KSZ8795 0,1,2,3 4 1334 * KSZ8765 0,1,2,3 4 1335 * port_cnt is configured as 5, even though it is 4 1336 */ 1337 .chip_id = KSZ8794_CHIP_ID, 1338 .dev_name = "KSZ8794", 1339 .num_vlans = 4096, 1340 .num_alus = 0, 1341 .num_statics = 32, 1342 .cpu_ports = 0x10, /* can be configured as cpu port */ 1343 .port_cnt = 5, /* total cpu and user ports */ 1344 .num_tx_queues = 4, 1345 .num_ipms = 4, 1346 .ops = &ksz87xx_dev_ops, 1347 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1348 .ksz87xx_eee_link_erratum = true, 1349 .mib_names = ksz9477_mib_names, 1350 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1351 .reg_mib_cnt = MIB_COUNTER_NUM, 1352 .regs = ksz8795_regs, 1353 .masks = ksz8795_masks, 1354 .shifts = ksz8795_shifts, 1355 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1356 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1357 .supports_mii = {false, false, false, false, true}, 1358 .supports_rmii = {false, false, false, false, true}, 1359 .supports_rgmii = {false, false, false, false, true}, 1360 .internal_phy = {true, true, true, false, false}, 1361 }, 1362 1363 [KSZ8765] = { 1364 .chip_id = KSZ8765_CHIP_ID, 1365 .dev_name = "KSZ8765", 1366 .num_vlans = 4096, 1367 .num_alus = 0, 1368 .num_statics = 32, 1369 .cpu_ports = 0x10, /* can be configured as cpu port */ 1370 .port_cnt = 5, /* total cpu and user ports */ 1371 .num_tx_queues = 4, 1372 .num_ipms = 4, 1373 .ops = &ksz87xx_dev_ops, 1374 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1375 .ksz87xx_eee_link_erratum = true, 1376 .mib_names = ksz9477_mib_names, 1377 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1378 .reg_mib_cnt = MIB_COUNTER_NUM, 1379 .regs = ksz8795_regs, 1380 .masks = ksz8795_masks, 1381 .shifts = ksz8795_shifts, 1382 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1383 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1384 .supports_mii = {false, false, false, false, true}, 1385 .supports_rmii = {false, false, false, false, true}, 1386 .supports_rgmii = {false, false, false, false, true}, 1387 .internal_phy = {true, true, true, true, false}, 1388 }, 1389 1390 [KSZ8830] = { 1391 .chip_id = KSZ8830_CHIP_ID, 1392 .dev_name = "KSZ8863/KSZ8873", 1393 .num_vlans = 16, 1394 .num_alus = 0, 1395 .num_statics = 8, 1396 .cpu_ports = 0x4, /* can be configured as cpu port */ 1397 .port_cnt = 3, 1398 .num_tx_queues = 4, 1399 .num_ipms = 4, 1400 .ops = &ksz88x3_dev_ops, 1401 .phylink_mac_ops = &ksz8830_phylink_mac_ops, 1402 .mib_names = ksz88xx_mib_names, 1403 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1404 .reg_mib_cnt = MIB_COUNTER_NUM, 1405 .regs = ksz8863_regs, 1406 .masks = ksz8863_masks, 1407 .shifts = ksz8863_shifts, 1408 .supports_mii = {false, false, true}, 1409 .supports_rmii = {false, false, true}, 1410 .internal_phy = {true, true, false}, 1411 .wr_table = &ksz8873_register_set, 1412 .rd_table = &ksz8873_register_set, 1413 }, 1414 1415 [KSZ9477] = { 1416 .chip_id = KSZ9477_CHIP_ID, 1417 .dev_name = "KSZ9477", 1418 .num_vlans = 4096, 1419 .num_alus = 4096, 1420 .num_statics = 16, 1421 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1422 .port_cnt = 7, /* total physical port count */ 1423 .port_nirqs = 4, 1424 .num_tx_queues = 4, 1425 .num_ipms = 8, 1426 .tc_cbs_supported = true, 1427 .ops = &ksz9477_dev_ops, 1428 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1429 .phy_errata_9477 = true, 1430 .mib_names = ksz9477_mib_names, 1431 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1432 .reg_mib_cnt = MIB_COUNTER_NUM, 1433 .regs = ksz9477_regs, 1434 .masks = ksz9477_masks, 1435 .shifts = ksz9477_shifts, 1436 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1437 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1438 .supports_mii = {false, false, false, false, 1439 false, true, false}, 1440 .supports_rmii = {false, false, false, false, 1441 false, true, false}, 1442 .supports_rgmii = {false, false, false, false, 1443 false, true, false}, 1444 .internal_phy = {true, true, true, true, 1445 true, false, false}, 1446 .gbit_capable = {true, true, true, true, true, true, true}, 1447 .wr_table = &ksz9477_register_set, 1448 .rd_table = &ksz9477_register_set, 1449 }, 1450 1451 [KSZ9896] = { 1452 .chip_id = KSZ9896_CHIP_ID, 1453 .dev_name = "KSZ9896", 1454 .num_vlans = 4096, 1455 .num_alus = 4096, 1456 .num_statics = 16, 1457 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1458 .port_cnt = 6, /* total physical port count */ 1459 .port_nirqs = 2, 1460 .num_tx_queues = 4, 1461 .num_ipms = 8, 1462 .ops = &ksz9477_dev_ops, 1463 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1464 .phy_errata_9477 = true, 1465 .mib_names = ksz9477_mib_names, 1466 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1467 .reg_mib_cnt = MIB_COUNTER_NUM, 1468 .regs = ksz9477_regs, 1469 .masks = ksz9477_masks, 1470 .shifts = ksz9477_shifts, 1471 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1472 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1473 .supports_mii = {false, false, false, false, 1474 false, true}, 1475 .supports_rmii = {false, false, false, false, 1476 false, true}, 1477 .supports_rgmii = {false, false, false, false, 1478 false, true}, 1479 .internal_phy = {true, true, true, true, 1480 true, false}, 1481 .gbit_capable = {true, true, true, true, true, true}, 1482 .wr_table = &ksz9896_register_set, 1483 .rd_table = &ksz9896_register_set, 1484 }, 1485 1486 [KSZ9897] = { 1487 .chip_id = KSZ9897_CHIP_ID, 1488 .dev_name = "KSZ9897", 1489 .num_vlans = 4096, 1490 .num_alus = 4096, 1491 .num_statics = 16, 1492 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1493 .port_cnt = 7, /* total physical port count */ 1494 .port_nirqs = 2, 1495 .num_tx_queues = 4, 1496 .num_ipms = 8, 1497 .ops = &ksz9477_dev_ops, 1498 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1499 .phy_errata_9477 = true, 1500 .mib_names = ksz9477_mib_names, 1501 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1502 .reg_mib_cnt = MIB_COUNTER_NUM, 1503 .regs = ksz9477_regs, 1504 .masks = ksz9477_masks, 1505 .shifts = ksz9477_shifts, 1506 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1507 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1508 .supports_mii = {false, false, false, false, 1509 false, true, true}, 1510 .supports_rmii = {false, false, false, false, 1511 false, true, true}, 1512 .supports_rgmii = {false, false, false, false, 1513 false, true, true}, 1514 .internal_phy = {true, true, true, true, 1515 true, false, false}, 1516 .gbit_capable = {true, true, true, true, true, true, true}, 1517 }, 1518 1519 [KSZ9893] = { 1520 .chip_id = KSZ9893_CHIP_ID, 1521 .dev_name = "KSZ9893", 1522 .num_vlans = 4096, 1523 .num_alus = 4096, 1524 .num_statics = 16, 1525 .cpu_ports = 0x07, /* can be configured as cpu port */ 1526 .port_cnt = 3, /* total port count */ 1527 .port_nirqs = 2, 1528 .num_tx_queues = 4, 1529 .num_ipms = 8, 1530 .ops = &ksz9477_dev_ops, 1531 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1532 .mib_names = ksz9477_mib_names, 1533 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1534 .reg_mib_cnt = MIB_COUNTER_NUM, 1535 .regs = ksz9477_regs, 1536 .masks = ksz9477_masks, 1537 .shifts = ksz9477_shifts, 1538 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1539 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1540 .supports_mii = {false, false, true}, 1541 .supports_rmii = {false, false, true}, 1542 .supports_rgmii = {false, false, true}, 1543 .internal_phy = {true, true, false}, 1544 .gbit_capable = {true, true, true}, 1545 }, 1546 1547 [KSZ9563] = { 1548 .chip_id = KSZ9563_CHIP_ID, 1549 .dev_name = "KSZ9563", 1550 .num_vlans = 4096, 1551 .num_alus = 4096, 1552 .num_statics = 16, 1553 .cpu_ports = 0x07, /* can be configured as cpu port */ 1554 .port_cnt = 3, /* total port count */ 1555 .port_nirqs = 3, 1556 .num_tx_queues = 4, 1557 .num_ipms = 8, 1558 .tc_cbs_supported = true, 1559 .ops = &ksz9477_dev_ops, 1560 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1561 .mib_names = ksz9477_mib_names, 1562 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1563 .reg_mib_cnt = MIB_COUNTER_NUM, 1564 .regs = ksz9477_regs, 1565 .masks = ksz9477_masks, 1566 .shifts = ksz9477_shifts, 1567 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1568 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1569 .supports_mii = {false, false, true}, 1570 .supports_rmii = {false, false, true}, 1571 .supports_rgmii = {false, false, true}, 1572 .internal_phy = {true, true, false}, 1573 .gbit_capable = {true, true, true}, 1574 }, 1575 1576 [KSZ8567] = { 1577 .chip_id = KSZ8567_CHIP_ID, 1578 .dev_name = "KSZ8567", 1579 .num_vlans = 4096, 1580 .num_alus = 4096, 1581 .num_statics = 16, 1582 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1583 .port_cnt = 7, /* total port count */ 1584 .port_nirqs = 3, 1585 .num_tx_queues = 4, 1586 .num_ipms = 8, 1587 .tc_cbs_supported = true, 1588 .ops = &ksz9477_dev_ops, 1589 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1590 .phy_errata_9477 = true, 1591 .mib_names = ksz9477_mib_names, 1592 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1593 .reg_mib_cnt = MIB_COUNTER_NUM, 1594 .regs = ksz9477_regs, 1595 .masks = ksz9477_masks, 1596 .shifts = ksz9477_shifts, 1597 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1598 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1599 .supports_mii = {false, false, false, false, 1600 false, true, true}, 1601 .supports_rmii = {false, false, false, false, 1602 false, true, true}, 1603 .supports_rgmii = {false, false, false, false, 1604 false, true, true}, 1605 .internal_phy = {true, true, true, true, 1606 true, false, false}, 1607 .gbit_capable = {false, false, false, false, false, 1608 true, true}, 1609 }, 1610 1611 [KSZ9567] = { 1612 .chip_id = KSZ9567_CHIP_ID, 1613 .dev_name = "KSZ9567", 1614 .num_vlans = 4096, 1615 .num_alus = 4096, 1616 .num_statics = 16, 1617 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1618 .port_cnt = 7, /* total physical port count */ 1619 .port_nirqs = 3, 1620 .num_tx_queues = 4, 1621 .num_ipms = 8, 1622 .tc_cbs_supported = true, 1623 .ops = &ksz9477_dev_ops, 1624 .mib_names = ksz9477_mib_names, 1625 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1626 .reg_mib_cnt = MIB_COUNTER_NUM, 1627 .regs = ksz9477_regs, 1628 .masks = ksz9477_masks, 1629 .shifts = ksz9477_shifts, 1630 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1631 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1632 .supports_mii = {false, false, false, false, 1633 false, true, true}, 1634 .supports_rmii = {false, false, false, false, 1635 false, true, true}, 1636 .supports_rgmii = {false, false, false, false, 1637 false, true, true}, 1638 .internal_phy = {true, true, true, true, 1639 true, false, false}, 1640 .gbit_capable = {true, true, true, true, true, true, true}, 1641 }, 1642 1643 [LAN9370] = { 1644 .chip_id = LAN9370_CHIP_ID, 1645 .dev_name = "LAN9370", 1646 .num_vlans = 4096, 1647 .num_alus = 1024, 1648 .num_statics = 256, 1649 .cpu_ports = 0x10, /* can be configured as cpu port */ 1650 .port_cnt = 5, /* total physical port count */ 1651 .port_nirqs = 6, 1652 .num_tx_queues = 8, 1653 .num_ipms = 8, 1654 .tc_cbs_supported = true, 1655 .ops = &lan937x_dev_ops, 1656 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1657 .mib_names = ksz9477_mib_names, 1658 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1659 .reg_mib_cnt = MIB_COUNTER_NUM, 1660 .regs = ksz9477_regs, 1661 .masks = lan937x_masks, 1662 .shifts = lan937x_shifts, 1663 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1664 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1665 .supports_mii = {false, false, false, false, true}, 1666 .supports_rmii = {false, false, false, false, true}, 1667 .supports_rgmii = {false, false, false, false, true}, 1668 .internal_phy = {true, true, true, true, false}, 1669 }, 1670 1671 [LAN9371] = { 1672 .chip_id = LAN9371_CHIP_ID, 1673 .dev_name = "LAN9371", 1674 .num_vlans = 4096, 1675 .num_alus = 1024, 1676 .num_statics = 256, 1677 .cpu_ports = 0x30, /* can be configured as cpu port */ 1678 .port_cnt = 6, /* total physical port count */ 1679 .port_nirqs = 6, 1680 .num_tx_queues = 8, 1681 .num_ipms = 8, 1682 .tc_cbs_supported = true, 1683 .ops = &lan937x_dev_ops, 1684 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1685 .mib_names = ksz9477_mib_names, 1686 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1687 .reg_mib_cnt = MIB_COUNTER_NUM, 1688 .regs = ksz9477_regs, 1689 .masks = lan937x_masks, 1690 .shifts = lan937x_shifts, 1691 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1692 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1693 .supports_mii = {false, false, false, false, true, true}, 1694 .supports_rmii = {false, false, false, false, true, true}, 1695 .supports_rgmii = {false, false, false, false, true, true}, 1696 .internal_phy = {true, true, true, true, false, false}, 1697 }, 1698 1699 [LAN9372] = { 1700 .chip_id = LAN9372_CHIP_ID, 1701 .dev_name = "LAN9372", 1702 .num_vlans = 4096, 1703 .num_alus = 1024, 1704 .num_statics = 256, 1705 .cpu_ports = 0x30, /* can be configured as cpu port */ 1706 .port_cnt = 8, /* total physical port count */ 1707 .port_nirqs = 6, 1708 .num_tx_queues = 8, 1709 .num_ipms = 8, 1710 .tc_cbs_supported = true, 1711 .ops = &lan937x_dev_ops, 1712 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1713 .mib_names = ksz9477_mib_names, 1714 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1715 .reg_mib_cnt = MIB_COUNTER_NUM, 1716 .regs = ksz9477_regs, 1717 .masks = lan937x_masks, 1718 .shifts = lan937x_shifts, 1719 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1720 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1721 .supports_mii = {false, false, false, false, 1722 true, true, false, false}, 1723 .supports_rmii = {false, false, false, false, 1724 true, true, false, false}, 1725 .supports_rgmii = {false, false, false, false, 1726 true, true, false, false}, 1727 .internal_phy = {true, true, true, true, 1728 false, false, true, true}, 1729 }, 1730 1731 [LAN9373] = { 1732 .chip_id = LAN9373_CHIP_ID, 1733 .dev_name = "LAN9373", 1734 .num_vlans = 4096, 1735 .num_alus = 1024, 1736 .num_statics = 256, 1737 .cpu_ports = 0x38, /* can be configured as cpu port */ 1738 .port_cnt = 5, /* total physical port count */ 1739 .port_nirqs = 6, 1740 .num_tx_queues = 8, 1741 .num_ipms = 8, 1742 .tc_cbs_supported = true, 1743 .ops = &lan937x_dev_ops, 1744 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1745 .mib_names = ksz9477_mib_names, 1746 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1747 .reg_mib_cnt = MIB_COUNTER_NUM, 1748 .regs = ksz9477_regs, 1749 .masks = lan937x_masks, 1750 .shifts = lan937x_shifts, 1751 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1752 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1753 .supports_mii = {false, false, false, false, 1754 true, true, false, false}, 1755 .supports_rmii = {false, false, false, false, 1756 true, true, false, false}, 1757 .supports_rgmii = {false, false, false, false, 1758 true, true, false, false}, 1759 .internal_phy = {true, true, true, false, 1760 false, false, true, true}, 1761 }, 1762 1763 [LAN9374] = { 1764 .chip_id = LAN9374_CHIP_ID, 1765 .dev_name = "LAN9374", 1766 .num_vlans = 4096, 1767 .num_alus = 1024, 1768 .num_statics = 256, 1769 .cpu_ports = 0x30, /* can be configured as cpu port */ 1770 .port_cnt = 8, /* total physical port count */ 1771 .port_nirqs = 6, 1772 .num_tx_queues = 8, 1773 .num_ipms = 8, 1774 .tc_cbs_supported = true, 1775 .ops = &lan937x_dev_ops, 1776 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1777 .mib_names = ksz9477_mib_names, 1778 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1779 .reg_mib_cnt = MIB_COUNTER_NUM, 1780 .regs = ksz9477_regs, 1781 .masks = lan937x_masks, 1782 .shifts = lan937x_shifts, 1783 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1784 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1785 .supports_mii = {false, false, false, false, 1786 true, true, false, false}, 1787 .supports_rmii = {false, false, false, false, 1788 true, true, false, false}, 1789 .supports_rgmii = {false, false, false, false, 1790 true, true, false, false}, 1791 .internal_phy = {true, true, true, true, 1792 false, false, true, true}, 1793 }, 1794 }; 1795 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1796 1797 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1798 { 1799 int i; 1800 1801 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1802 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1803 1804 if (chip->chip_id == prod_num) 1805 return chip; 1806 } 1807 1808 return NULL; 1809 } 1810 1811 static int ksz_check_device_id(struct ksz_device *dev) 1812 { 1813 const struct ksz_chip_data *expected_chip_data; 1814 u32 expected_chip_id; 1815 1816 if (dev->pdata) { 1817 expected_chip_id = dev->pdata->chip_id; 1818 expected_chip_data = ksz_lookup_info(expected_chip_id); 1819 if (WARN_ON(!expected_chip_data)) 1820 return -ENODEV; 1821 } else { 1822 expected_chip_data = of_device_get_match_data(dev->dev); 1823 expected_chip_id = expected_chip_data->chip_id; 1824 } 1825 1826 if (expected_chip_id != dev->chip_id) { 1827 dev_err(dev->dev, 1828 "Device tree specifies chip %s but found %s, please fix it!\n", 1829 expected_chip_data->dev_name, dev->info->dev_name); 1830 return -ENODEV; 1831 } 1832 1833 return 0; 1834 } 1835 1836 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1837 struct phylink_config *config) 1838 { 1839 struct ksz_device *dev = ds->priv; 1840 1841 if (dev->info->supports_mii[port]) 1842 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1843 1844 if (dev->info->supports_rmii[port]) 1845 __set_bit(PHY_INTERFACE_MODE_RMII, 1846 config->supported_interfaces); 1847 1848 if (dev->info->supports_rgmii[port]) 1849 phy_interface_set_rgmii(config->supported_interfaces); 1850 1851 if (dev->info->internal_phy[port]) { 1852 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1853 config->supported_interfaces); 1854 /* Compatibility for phylib's default interface type when the 1855 * phy-mode property is absent 1856 */ 1857 __set_bit(PHY_INTERFACE_MODE_GMII, 1858 config->supported_interfaces); 1859 } 1860 1861 if (dev->dev_ops->get_caps) 1862 dev->dev_ops->get_caps(dev, port, config); 1863 } 1864 1865 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 1866 { 1867 struct ethtool_pause_stats *pstats; 1868 struct rtnl_link_stats64 *stats; 1869 struct ksz_stats_raw *raw; 1870 struct ksz_port_mib *mib; 1871 int ret; 1872 1873 mib = &dev->ports[port].mib; 1874 stats = &mib->stats64; 1875 pstats = &mib->pause_stats; 1876 raw = (struct ksz_stats_raw *)mib->counters; 1877 1878 spin_lock(&mib->stats64_lock); 1879 1880 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1881 raw->rx_pause; 1882 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1883 raw->tx_pause; 1884 1885 /* HW counters are counting bytes + FCS which is not acceptable 1886 * for rtnl_link_stats64 interface 1887 */ 1888 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 1889 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 1890 1891 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1892 raw->rx_oversize; 1893 1894 stats->rx_crc_errors = raw->rx_crc_err; 1895 stats->rx_frame_errors = raw->rx_align_err; 1896 stats->rx_dropped = raw->rx_discards; 1897 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1898 stats->rx_frame_errors + stats->rx_dropped; 1899 1900 stats->tx_window_errors = raw->tx_late_col; 1901 stats->tx_fifo_errors = raw->tx_discards; 1902 stats->tx_aborted_errors = raw->tx_exc_col; 1903 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1904 stats->tx_aborted_errors; 1905 1906 stats->multicast = raw->rx_mcast; 1907 stats->collisions = raw->tx_total_col; 1908 1909 pstats->tx_pause_frames = raw->tx_pause; 1910 pstats->rx_pause_frames = raw->rx_pause; 1911 1912 spin_unlock(&mib->stats64_lock); 1913 1914 if (dev->info->phy_errata_9477) { 1915 ret = ksz9477_errata_monitor(dev, port, raw->tx_late_col); 1916 if (ret) 1917 dev_err(dev->dev, "Failed to monitor transmission halt\n"); 1918 } 1919 } 1920 1921 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 1922 { 1923 struct ethtool_pause_stats *pstats; 1924 struct rtnl_link_stats64 *stats; 1925 struct ksz88xx_stats_raw *raw; 1926 struct ksz_port_mib *mib; 1927 1928 mib = &dev->ports[port].mib; 1929 stats = &mib->stats64; 1930 pstats = &mib->pause_stats; 1931 raw = (struct ksz88xx_stats_raw *)mib->counters; 1932 1933 spin_lock(&mib->stats64_lock); 1934 1935 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1936 raw->rx_pause; 1937 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1938 raw->tx_pause; 1939 1940 /* HW counters are counting bytes + FCS which is not acceptable 1941 * for rtnl_link_stats64 interface 1942 */ 1943 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 1944 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 1945 1946 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1947 raw->rx_oversize; 1948 1949 stats->rx_crc_errors = raw->rx_crc_err; 1950 stats->rx_frame_errors = raw->rx_align_err; 1951 stats->rx_dropped = raw->rx_discards; 1952 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1953 stats->rx_frame_errors + stats->rx_dropped; 1954 1955 stats->tx_window_errors = raw->tx_late_col; 1956 stats->tx_fifo_errors = raw->tx_discards; 1957 stats->tx_aborted_errors = raw->tx_exc_col; 1958 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1959 stats->tx_aborted_errors; 1960 1961 stats->multicast = raw->rx_mcast; 1962 stats->collisions = raw->tx_total_col; 1963 1964 pstats->tx_pause_frames = raw->tx_pause; 1965 pstats->rx_pause_frames = raw->rx_pause; 1966 1967 spin_unlock(&mib->stats64_lock); 1968 } 1969 1970 static void ksz_get_stats64(struct dsa_switch *ds, int port, 1971 struct rtnl_link_stats64 *s) 1972 { 1973 struct ksz_device *dev = ds->priv; 1974 struct ksz_port_mib *mib; 1975 1976 mib = &dev->ports[port].mib; 1977 1978 spin_lock(&mib->stats64_lock); 1979 memcpy(s, &mib->stats64, sizeof(*s)); 1980 spin_unlock(&mib->stats64_lock); 1981 } 1982 1983 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 1984 struct ethtool_pause_stats *pause_stats) 1985 { 1986 struct ksz_device *dev = ds->priv; 1987 struct ksz_port_mib *mib; 1988 1989 mib = &dev->ports[port].mib; 1990 1991 spin_lock(&mib->stats64_lock); 1992 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 1993 spin_unlock(&mib->stats64_lock); 1994 } 1995 1996 static void ksz_get_strings(struct dsa_switch *ds, int port, 1997 u32 stringset, uint8_t *buf) 1998 { 1999 struct ksz_device *dev = ds->priv; 2000 int i; 2001 2002 if (stringset != ETH_SS_STATS) 2003 return; 2004 2005 for (i = 0; i < dev->info->mib_cnt; i++) { 2006 memcpy(buf + i * ETH_GSTRING_LEN, 2007 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 2008 } 2009 } 2010 2011 /** 2012 * ksz_update_port_member - Adjust port forwarding rules based on STP state and 2013 * isolation settings. 2014 * @dev: A pointer to the struct ksz_device representing the device. 2015 * @port: The port number to adjust. 2016 * 2017 * This function dynamically adjusts the port membership configuration for a 2018 * specified port and other device ports, based on Spanning Tree Protocol (STP) 2019 * states and port isolation settings. Each port, including the CPU port, has a 2020 * membership register, represented as a bitfield, where each bit corresponds 2021 * to a port number. A set bit indicates permission to forward frames to that 2022 * port. This function iterates over all ports, updating the membership register 2023 * to reflect current forwarding permissions: 2024 * 2025 * 1. Forwards frames only to ports that are part of the same bridge group and 2026 * in the BR_STATE_FORWARDING state. 2027 * 2. Takes into account the isolation status of ports; ports in the 2028 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward 2029 * frames to each other, even if they are in the same bridge group. 2030 * 3. Ensures that the CPU port is included in the membership based on its 2031 * upstream port configuration, allowing for management and control traffic 2032 * to flow as required. 2033 */ 2034 static void ksz_update_port_member(struct ksz_device *dev, int port) 2035 { 2036 struct ksz_port *p = &dev->ports[port]; 2037 struct dsa_switch *ds = dev->ds; 2038 u8 port_member = 0, cpu_port; 2039 const struct dsa_port *dp; 2040 int i, j; 2041 2042 if (!dsa_is_user_port(ds, port)) 2043 return; 2044 2045 dp = dsa_to_port(ds, port); 2046 cpu_port = BIT(dsa_upstream_port(ds, port)); 2047 2048 for (i = 0; i < ds->num_ports; i++) { 2049 const struct dsa_port *other_dp = dsa_to_port(ds, i); 2050 struct ksz_port *other_p = &dev->ports[i]; 2051 u8 val = 0; 2052 2053 if (!dsa_is_user_port(ds, i)) 2054 continue; 2055 if (port == i) 2056 continue; 2057 if (!dsa_port_bridge_same(dp, other_dp)) 2058 continue; 2059 if (other_p->stp_state != BR_STATE_FORWARDING) 2060 continue; 2061 2062 /* At this point we know that "port" and "other" port [i] are in 2063 * the same bridge group and that "other" port [i] is in 2064 * forwarding stp state. If "port" is also in forwarding stp 2065 * state, we can allow forwarding from port [port] to port [i]. 2066 * Except if both ports are isolated. 2067 */ 2068 if (p->stp_state == BR_STATE_FORWARDING && 2069 !(p->isolated && other_p->isolated)) { 2070 val |= BIT(port); 2071 port_member |= BIT(i); 2072 } 2073 2074 /* Retain port [i]'s relationship to other ports than [port] */ 2075 for (j = 0; j < ds->num_ports; j++) { 2076 const struct dsa_port *third_dp; 2077 struct ksz_port *third_p; 2078 2079 if (j == i) 2080 continue; 2081 if (j == port) 2082 continue; 2083 if (!dsa_is_user_port(ds, j)) 2084 continue; 2085 third_p = &dev->ports[j]; 2086 if (third_p->stp_state != BR_STATE_FORWARDING) 2087 continue; 2088 2089 third_dp = dsa_to_port(ds, j); 2090 2091 /* Now we updating relation of the "other" port [i] to 2092 * the "third" port [j]. We already know that "other" 2093 * port [i] is in forwarding stp state and that "third" 2094 * port [j] is in forwarding stp state too. 2095 * We need to check if "other" port [i] and "third" port 2096 * [j] are in the same bridge group and not isolated 2097 * before allowing forwarding from port [i] to port [j]. 2098 */ 2099 if (dsa_port_bridge_same(other_dp, third_dp) && 2100 !(other_p->isolated && third_p->isolated)) 2101 val |= BIT(j); 2102 } 2103 2104 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 2105 } 2106 2107 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 2108 } 2109 2110 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 2111 { 2112 struct ksz_device *dev = bus->priv; 2113 u16 val; 2114 int ret; 2115 2116 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 2117 if (ret < 0) 2118 return ret; 2119 2120 return val; 2121 } 2122 2123 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 2124 u16 val) 2125 { 2126 struct ksz_device *dev = bus->priv; 2127 2128 return dev->dev_ops->w_phy(dev, addr, regnum, val); 2129 } 2130 2131 static int ksz_irq_phy_setup(struct ksz_device *dev) 2132 { 2133 struct dsa_switch *ds = dev->ds; 2134 int phy; 2135 int irq; 2136 int ret; 2137 2138 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) { 2139 if (BIT(phy) & ds->phys_mii_mask) { 2140 irq = irq_find_mapping(dev->ports[phy].pirq.domain, 2141 PORT_SRC_PHY_INT); 2142 if (irq < 0) { 2143 ret = irq; 2144 goto out; 2145 } 2146 ds->user_mii_bus->irq[phy] = irq; 2147 } 2148 } 2149 return 0; 2150 out: 2151 while (phy--) 2152 if (BIT(phy) & ds->phys_mii_mask) 2153 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2154 2155 return ret; 2156 } 2157 2158 static void ksz_irq_phy_free(struct ksz_device *dev) 2159 { 2160 struct dsa_switch *ds = dev->ds; 2161 int phy; 2162 2163 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) 2164 if (BIT(phy) & ds->phys_mii_mask) 2165 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2166 } 2167 2168 static int ksz_mdio_register(struct ksz_device *dev) 2169 { 2170 struct dsa_switch *ds = dev->ds; 2171 struct device_node *mdio_np; 2172 struct mii_bus *bus; 2173 int ret; 2174 2175 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 2176 if (!mdio_np) 2177 return 0; 2178 2179 bus = devm_mdiobus_alloc(ds->dev); 2180 if (!bus) { 2181 of_node_put(mdio_np); 2182 return -ENOMEM; 2183 } 2184 2185 bus->priv = dev; 2186 bus->read = ksz_sw_mdio_read; 2187 bus->write = ksz_sw_mdio_write; 2188 bus->name = "ksz user smi"; 2189 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 2190 bus->parent = ds->dev; 2191 bus->phy_mask = ~ds->phys_mii_mask; 2192 2193 ds->user_mii_bus = bus; 2194 2195 if (dev->irq > 0) { 2196 ret = ksz_irq_phy_setup(dev); 2197 if (ret) { 2198 of_node_put(mdio_np); 2199 return ret; 2200 } 2201 } 2202 2203 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 2204 if (ret) { 2205 dev_err(ds->dev, "unable to register MDIO bus %s\n", 2206 bus->id); 2207 if (dev->irq > 0) 2208 ksz_irq_phy_free(dev); 2209 } 2210 2211 of_node_put(mdio_np); 2212 2213 return ret; 2214 } 2215 2216 static void ksz_irq_mask(struct irq_data *d) 2217 { 2218 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2219 2220 kirq->masked |= BIT(d->hwirq); 2221 } 2222 2223 static void ksz_irq_unmask(struct irq_data *d) 2224 { 2225 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2226 2227 kirq->masked &= ~BIT(d->hwirq); 2228 } 2229 2230 static void ksz_irq_bus_lock(struct irq_data *d) 2231 { 2232 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2233 2234 mutex_lock(&kirq->dev->lock_irq); 2235 } 2236 2237 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 2238 { 2239 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2240 struct ksz_device *dev = kirq->dev; 2241 int ret; 2242 2243 ret = ksz_write8(dev, kirq->reg_mask, kirq->masked); 2244 if (ret) 2245 dev_err(dev->dev, "failed to change IRQ mask\n"); 2246 2247 mutex_unlock(&dev->lock_irq); 2248 } 2249 2250 static const struct irq_chip ksz_irq_chip = { 2251 .name = "ksz-irq", 2252 .irq_mask = ksz_irq_mask, 2253 .irq_unmask = ksz_irq_unmask, 2254 .irq_bus_lock = ksz_irq_bus_lock, 2255 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 2256 }; 2257 2258 static int ksz_irq_domain_map(struct irq_domain *d, 2259 unsigned int irq, irq_hw_number_t hwirq) 2260 { 2261 irq_set_chip_data(irq, d->host_data); 2262 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 2263 irq_set_noprobe(irq); 2264 2265 return 0; 2266 } 2267 2268 static const struct irq_domain_ops ksz_irq_domain_ops = { 2269 .map = ksz_irq_domain_map, 2270 .xlate = irq_domain_xlate_twocell, 2271 }; 2272 2273 static void ksz_irq_free(struct ksz_irq *kirq) 2274 { 2275 int irq, virq; 2276 2277 free_irq(kirq->irq_num, kirq); 2278 2279 for (irq = 0; irq < kirq->nirqs; irq++) { 2280 virq = irq_find_mapping(kirq->domain, irq); 2281 irq_dispose_mapping(virq); 2282 } 2283 2284 irq_domain_remove(kirq->domain); 2285 } 2286 2287 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 2288 { 2289 struct ksz_irq *kirq = dev_id; 2290 unsigned int nhandled = 0; 2291 struct ksz_device *dev; 2292 unsigned int sub_irq; 2293 u8 data; 2294 int ret; 2295 u8 n; 2296 2297 dev = kirq->dev; 2298 2299 /* Read interrupt status register */ 2300 ret = ksz_read8(dev, kirq->reg_status, &data); 2301 if (ret) 2302 goto out; 2303 2304 for (n = 0; n < kirq->nirqs; ++n) { 2305 if (data & BIT(n)) { 2306 sub_irq = irq_find_mapping(kirq->domain, n); 2307 handle_nested_irq(sub_irq); 2308 ++nhandled; 2309 } 2310 } 2311 out: 2312 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2313 } 2314 2315 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 2316 { 2317 int ret, n; 2318 2319 kirq->dev = dev; 2320 kirq->masked = ~0; 2321 2322 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0, 2323 &ksz_irq_domain_ops, kirq); 2324 if (!kirq->domain) 2325 return -ENOMEM; 2326 2327 for (n = 0; n < kirq->nirqs; n++) 2328 irq_create_mapping(kirq->domain, n); 2329 2330 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2331 IRQF_ONESHOT, kirq->name, kirq); 2332 if (ret) 2333 goto out; 2334 2335 return 0; 2336 2337 out: 2338 ksz_irq_free(kirq); 2339 2340 return ret; 2341 } 2342 2343 static int ksz_girq_setup(struct ksz_device *dev) 2344 { 2345 struct ksz_irq *girq = &dev->girq; 2346 2347 girq->nirqs = dev->info->port_cnt; 2348 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2349 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2350 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2351 2352 girq->irq_num = dev->irq; 2353 2354 return ksz_irq_common_setup(dev, girq); 2355 } 2356 2357 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2358 { 2359 struct ksz_irq *pirq = &dev->ports[p].pirq; 2360 2361 pirq->nirqs = dev->info->port_nirqs; 2362 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2363 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2364 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2365 2366 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2367 if (pirq->irq_num < 0) 2368 return pirq->irq_num; 2369 2370 return ksz_irq_common_setup(dev, pirq); 2371 } 2372 2373 static int ksz_parse_drive_strength(struct ksz_device *dev); 2374 2375 static int ksz_setup(struct dsa_switch *ds) 2376 { 2377 struct ksz_device *dev = ds->priv; 2378 struct dsa_port *dp; 2379 struct ksz_port *p; 2380 const u16 *regs; 2381 int ret; 2382 2383 regs = dev->info->regs; 2384 2385 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2386 dev->info->num_vlans, GFP_KERNEL); 2387 if (!dev->vlan_cache) 2388 return -ENOMEM; 2389 2390 ret = dev->dev_ops->reset(dev); 2391 if (ret) { 2392 dev_err(ds->dev, "failed to reset switch\n"); 2393 return ret; 2394 } 2395 2396 ret = ksz_parse_drive_strength(dev); 2397 if (ret) 2398 return ret; 2399 2400 /* set broadcast storm protection 10% rate */ 2401 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2402 BROADCAST_STORM_RATE, 2403 (BROADCAST_STORM_VALUE * 2404 BROADCAST_STORM_PROT_RATE) / 100); 2405 2406 dev->dev_ops->config_cpu_port(ds); 2407 2408 dev->dev_ops->enable_stp_addr(dev); 2409 2410 ds->num_tx_queues = dev->info->num_tx_queues; 2411 2412 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 2413 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2414 2415 ksz_init_mib_timer(dev); 2416 2417 ds->configure_vlan_while_not_filtering = false; 2418 ds->dscp_prio_mapping_is_global = true; 2419 2420 if (dev->dev_ops->setup) { 2421 ret = dev->dev_ops->setup(ds); 2422 if (ret) 2423 return ret; 2424 } 2425 2426 /* Start with learning disabled on standalone user ports, and enabled 2427 * on the CPU port. In lack of other finer mechanisms, learning on the 2428 * CPU port will avoid flooding bridge local addresses on the network 2429 * in some cases. 2430 */ 2431 p = &dev->ports[dev->cpu_port]; 2432 p->learning = true; 2433 2434 if (dev->irq > 0) { 2435 ret = ksz_girq_setup(dev); 2436 if (ret) 2437 return ret; 2438 2439 dsa_switch_for_each_user_port(dp, dev->ds) { 2440 ret = ksz_pirq_setup(dev, dp->index); 2441 if (ret) 2442 goto out_girq; 2443 2444 ret = ksz_ptp_irq_setup(ds, dp->index); 2445 if (ret) 2446 goto out_pirq; 2447 } 2448 } 2449 2450 ret = ksz_ptp_clock_register(ds); 2451 if (ret) { 2452 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret); 2453 goto out_ptpirq; 2454 } 2455 2456 ret = ksz_mdio_register(dev); 2457 if (ret < 0) { 2458 dev_err(dev->dev, "failed to register the mdio"); 2459 goto out_ptp_clock_unregister; 2460 } 2461 2462 ret = ksz_dcb_init(dev); 2463 if (ret) 2464 goto out_ptp_clock_unregister; 2465 2466 /* start switch */ 2467 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 2468 SW_START, SW_START); 2469 2470 return 0; 2471 2472 out_ptp_clock_unregister: 2473 ksz_ptp_clock_unregister(ds); 2474 out_ptpirq: 2475 if (dev->irq > 0) 2476 dsa_switch_for_each_user_port(dp, dev->ds) 2477 ksz_ptp_irq_free(ds, dp->index); 2478 out_pirq: 2479 if (dev->irq > 0) 2480 dsa_switch_for_each_user_port(dp, dev->ds) 2481 ksz_irq_free(&dev->ports[dp->index].pirq); 2482 out_girq: 2483 if (dev->irq > 0) 2484 ksz_irq_free(&dev->girq); 2485 2486 return ret; 2487 } 2488 2489 static void ksz_teardown(struct dsa_switch *ds) 2490 { 2491 struct ksz_device *dev = ds->priv; 2492 struct dsa_port *dp; 2493 2494 ksz_ptp_clock_unregister(ds); 2495 2496 if (dev->irq > 0) { 2497 dsa_switch_for_each_user_port(dp, dev->ds) { 2498 ksz_ptp_irq_free(ds, dp->index); 2499 2500 ksz_irq_free(&dev->ports[dp->index].pirq); 2501 } 2502 2503 ksz_irq_free(&dev->girq); 2504 } 2505 2506 if (dev->dev_ops->teardown) 2507 dev->dev_ops->teardown(ds); 2508 } 2509 2510 static void port_r_cnt(struct ksz_device *dev, int port) 2511 { 2512 struct ksz_port_mib *mib = &dev->ports[port].mib; 2513 u64 *dropped; 2514 2515 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2516 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2517 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2518 &mib->counters[mib->cnt_ptr]); 2519 ++mib->cnt_ptr; 2520 } 2521 2522 /* last one in storage */ 2523 dropped = &mib->counters[dev->info->mib_cnt]; 2524 2525 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2526 while (mib->cnt_ptr < dev->info->mib_cnt) { 2527 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2528 dropped, &mib->counters[mib->cnt_ptr]); 2529 ++mib->cnt_ptr; 2530 } 2531 mib->cnt_ptr = 0; 2532 } 2533 2534 static void ksz_mib_read_work(struct work_struct *work) 2535 { 2536 struct ksz_device *dev = container_of(work, struct ksz_device, 2537 mib_read.work); 2538 struct ksz_port_mib *mib; 2539 struct ksz_port *p; 2540 int i; 2541 2542 for (i = 0; i < dev->info->port_cnt; i++) { 2543 if (dsa_is_unused_port(dev->ds, i)) 2544 continue; 2545 2546 p = &dev->ports[i]; 2547 mib = &p->mib; 2548 mutex_lock(&mib->cnt_mutex); 2549 2550 /* Only read MIB counters when the port is told to do. 2551 * If not, read only dropped counters when link is not up. 2552 */ 2553 if (!p->read) { 2554 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 2555 2556 if (!netif_carrier_ok(dp->user)) 2557 mib->cnt_ptr = dev->info->reg_mib_cnt; 2558 } 2559 port_r_cnt(dev, i); 2560 p->read = false; 2561 2562 if (dev->dev_ops->r_mib_stat64) 2563 dev->dev_ops->r_mib_stat64(dev, i); 2564 2565 mutex_unlock(&mib->cnt_mutex); 2566 } 2567 2568 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 2569 } 2570 2571 void ksz_init_mib_timer(struct ksz_device *dev) 2572 { 2573 int i; 2574 2575 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 2576 2577 for (i = 0; i < dev->info->port_cnt; i++) { 2578 struct ksz_port_mib *mib = &dev->ports[i].mib; 2579 2580 dev->dev_ops->port_init_cnt(dev, i); 2581 2582 mib->cnt_ptr = 0; 2583 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 2584 } 2585 } 2586 2587 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 2588 { 2589 struct ksz_device *dev = ds->priv; 2590 u16 val = 0xffff; 2591 int ret; 2592 2593 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 2594 if (ret) 2595 return ret; 2596 2597 return val; 2598 } 2599 2600 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 2601 { 2602 struct ksz_device *dev = ds->priv; 2603 int ret; 2604 2605 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 2606 if (ret) 2607 return ret; 2608 2609 return 0; 2610 } 2611 2612 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 2613 { 2614 struct ksz_device *dev = ds->priv; 2615 2616 switch (dev->chip_id) { 2617 case KSZ8830_CHIP_ID: 2618 /* Silicon Errata Sheet (DS80000830A): 2619 * Port 1 does not work with LinkMD Cable-Testing. 2620 * Port 1 does not respond to received PAUSE control frames. 2621 */ 2622 if (!port) 2623 return MICREL_KSZ8_P1_ERRATA; 2624 break; 2625 case KSZ8567_CHIP_ID: 2626 case KSZ9477_CHIP_ID: 2627 case KSZ9567_CHIP_ID: 2628 case KSZ9896_CHIP_ID: 2629 case KSZ9897_CHIP_ID: 2630 /* KSZ9477 Errata DS80000754C 2631 * 2632 * Module 4: Energy Efficient Ethernet (EEE) feature select must 2633 * be manually disabled 2634 * The EEE feature is enabled by default, but it is not fully 2635 * operational. It must be manually disabled through register 2636 * controls. If not disabled, the PHY ports can auto-negotiate 2637 * to enable EEE, and this feature can cause link drops when 2638 * linked to another device supporting EEE. 2639 * 2640 * The same item appears in the errata for the KSZ9567, KSZ9896, 2641 * and KSZ9897. 2642 * 2643 * A similar item appears in the errata for the KSZ8567, but 2644 * provides an alternative workaround. For now, use the simple 2645 * workaround of disabling the EEE feature for this device too. 2646 */ 2647 return MICREL_NO_EEE; 2648 } 2649 2650 return 0; 2651 } 2652 2653 static void ksz_phylink_mac_link_down(struct phylink_config *config, 2654 unsigned int mode, 2655 phy_interface_t interface) 2656 { 2657 struct dsa_port *dp = dsa_phylink_to_port(config); 2658 struct ksz_device *dev = dp->ds->priv; 2659 2660 /* Read all MIB counters when the link is going down. */ 2661 dev->ports[dp->index].read = true; 2662 /* timer started */ 2663 if (dev->mib_read_interval) 2664 schedule_delayed_work(&dev->mib_read, 0); 2665 } 2666 2667 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 2668 { 2669 struct ksz_device *dev = ds->priv; 2670 2671 if (sset != ETH_SS_STATS) 2672 return 0; 2673 2674 return dev->info->mib_cnt; 2675 } 2676 2677 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 2678 uint64_t *buf) 2679 { 2680 const struct dsa_port *dp = dsa_to_port(ds, port); 2681 struct ksz_device *dev = ds->priv; 2682 struct ksz_port_mib *mib; 2683 2684 mib = &dev->ports[port].mib; 2685 mutex_lock(&mib->cnt_mutex); 2686 2687 /* Only read dropped counters if no link. */ 2688 if (!netif_carrier_ok(dp->user)) 2689 mib->cnt_ptr = dev->info->reg_mib_cnt; 2690 port_r_cnt(dev, port); 2691 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 2692 mutex_unlock(&mib->cnt_mutex); 2693 } 2694 2695 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 2696 struct dsa_bridge bridge, 2697 bool *tx_fwd_offload, 2698 struct netlink_ext_ack *extack) 2699 { 2700 /* port_stp_state_set() will be called after to put the port in 2701 * appropriate state so there is no need to do anything. 2702 */ 2703 2704 return 0; 2705 } 2706 2707 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 2708 struct dsa_bridge bridge) 2709 { 2710 /* port_stp_state_set() will be called after to put the port in 2711 * forwarding state so there is no need to do anything. 2712 */ 2713 } 2714 2715 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 2716 { 2717 struct ksz_device *dev = ds->priv; 2718 2719 dev->dev_ops->flush_dyn_mac_table(dev, port); 2720 } 2721 2722 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 2723 { 2724 struct ksz_device *dev = ds->priv; 2725 2726 if (!dev->dev_ops->set_ageing_time) 2727 return -EOPNOTSUPP; 2728 2729 return dev->dev_ops->set_ageing_time(dev, msecs); 2730 } 2731 2732 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 2733 const unsigned char *addr, u16 vid, 2734 struct dsa_db db) 2735 { 2736 struct ksz_device *dev = ds->priv; 2737 2738 if (!dev->dev_ops->fdb_add) 2739 return -EOPNOTSUPP; 2740 2741 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 2742 } 2743 2744 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 2745 const unsigned char *addr, 2746 u16 vid, struct dsa_db db) 2747 { 2748 struct ksz_device *dev = ds->priv; 2749 2750 if (!dev->dev_ops->fdb_del) 2751 return -EOPNOTSUPP; 2752 2753 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 2754 } 2755 2756 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 2757 dsa_fdb_dump_cb_t *cb, void *data) 2758 { 2759 struct ksz_device *dev = ds->priv; 2760 2761 if (!dev->dev_ops->fdb_dump) 2762 return -EOPNOTSUPP; 2763 2764 return dev->dev_ops->fdb_dump(dev, port, cb, data); 2765 } 2766 2767 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 2768 const struct switchdev_obj_port_mdb *mdb, 2769 struct dsa_db db) 2770 { 2771 struct ksz_device *dev = ds->priv; 2772 2773 if (!dev->dev_ops->mdb_add) 2774 return -EOPNOTSUPP; 2775 2776 return dev->dev_ops->mdb_add(dev, port, mdb, db); 2777 } 2778 2779 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 2780 const struct switchdev_obj_port_mdb *mdb, 2781 struct dsa_db db) 2782 { 2783 struct ksz_device *dev = ds->priv; 2784 2785 if (!dev->dev_ops->mdb_del) 2786 return -EOPNOTSUPP; 2787 2788 return dev->dev_ops->mdb_del(dev, port, mdb, db); 2789 } 2790 2791 static int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev, 2792 int port) 2793 { 2794 u32 queue_map = 0; 2795 int ipm; 2796 2797 for (ipm = 0; ipm < dev->info->num_ipms; ipm++) { 2798 int queue; 2799 2800 /* Traffic Type (TT) is corresponding to the Internal Priority 2801 * Map (IPM) in the switch. Traffic Class (TC) is 2802 * corresponding to the queue in the switch. 2803 */ 2804 queue = ieee8021q_tt_to_tc(ipm, dev->info->num_tx_queues); 2805 if (queue < 0) 2806 return queue; 2807 2808 queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S); 2809 } 2810 2811 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 2812 } 2813 2814 static int ksz_port_setup(struct dsa_switch *ds, int port) 2815 { 2816 struct ksz_device *dev = ds->priv; 2817 int ret; 2818 2819 if (!dsa_is_user_port(ds, port)) 2820 return 0; 2821 2822 /* setup user port */ 2823 dev->dev_ops->port_setup(dev, port, false); 2824 2825 if (!is_ksz8(dev)) { 2826 ret = ksz9477_set_default_prio_queue_mapping(dev, port); 2827 if (ret) 2828 return ret; 2829 } 2830 2831 /* port_stp_state_set() will be called after to enable the port so 2832 * there is no need to do anything. 2833 */ 2834 2835 return ksz_dcb_init_port(dev, port); 2836 } 2837 2838 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 2839 { 2840 struct ksz_device *dev = ds->priv; 2841 struct ksz_port *p; 2842 const u16 *regs; 2843 u8 data; 2844 2845 regs = dev->info->regs; 2846 2847 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 2848 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2849 2850 p = &dev->ports[port]; 2851 2852 switch (state) { 2853 case BR_STATE_DISABLED: 2854 data |= PORT_LEARN_DISABLE; 2855 break; 2856 case BR_STATE_LISTENING: 2857 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2858 break; 2859 case BR_STATE_LEARNING: 2860 data |= PORT_RX_ENABLE; 2861 if (!p->learning) 2862 data |= PORT_LEARN_DISABLE; 2863 break; 2864 case BR_STATE_FORWARDING: 2865 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 2866 if (!p->learning) 2867 data |= PORT_LEARN_DISABLE; 2868 break; 2869 case BR_STATE_BLOCKING: 2870 data |= PORT_LEARN_DISABLE; 2871 break; 2872 default: 2873 dev_err(ds->dev, "invalid STP state: %d\n", state); 2874 return; 2875 } 2876 2877 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 2878 2879 p->stp_state = state; 2880 2881 ksz_update_port_member(dev, port); 2882 } 2883 2884 static void ksz_port_teardown(struct dsa_switch *ds, int port) 2885 { 2886 struct ksz_device *dev = ds->priv; 2887 2888 switch (dev->chip_id) { 2889 case KSZ8563_CHIP_ID: 2890 case KSZ8567_CHIP_ID: 2891 case KSZ9477_CHIP_ID: 2892 case KSZ9563_CHIP_ID: 2893 case KSZ9567_CHIP_ID: 2894 case KSZ9893_CHIP_ID: 2895 case KSZ9896_CHIP_ID: 2896 case KSZ9897_CHIP_ID: 2897 if (dsa_is_user_port(ds, port)) 2898 ksz9477_port_acl_free(dev, port); 2899 } 2900 } 2901 2902 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 2903 struct switchdev_brport_flags flags, 2904 struct netlink_ext_ack *extack) 2905 { 2906 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED)) 2907 return -EINVAL; 2908 2909 return 0; 2910 } 2911 2912 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 2913 struct switchdev_brport_flags flags, 2914 struct netlink_ext_ack *extack) 2915 { 2916 struct ksz_device *dev = ds->priv; 2917 struct ksz_port *p = &dev->ports[port]; 2918 2919 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) { 2920 if (flags.mask & BR_LEARNING) 2921 p->learning = !!(flags.val & BR_LEARNING); 2922 2923 if (flags.mask & BR_ISOLATED) 2924 p->isolated = !!(flags.val & BR_ISOLATED); 2925 2926 /* Make the change take effect immediately */ 2927 ksz_port_stp_state_set(ds, port, p->stp_state); 2928 } 2929 2930 return 0; 2931 } 2932 2933 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 2934 int port, 2935 enum dsa_tag_protocol mp) 2936 { 2937 struct ksz_device *dev = ds->priv; 2938 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 2939 2940 if (dev->chip_id == KSZ8795_CHIP_ID || 2941 dev->chip_id == KSZ8794_CHIP_ID || 2942 dev->chip_id == KSZ8765_CHIP_ID) 2943 proto = DSA_TAG_PROTO_KSZ8795; 2944 2945 if (dev->chip_id == KSZ8830_CHIP_ID || 2946 dev->chip_id == KSZ8563_CHIP_ID || 2947 dev->chip_id == KSZ9893_CHIP_ID || 2948 dev->chip_id == KSZ9563_CHIP_ID) 2949 proto = DSA_TAG_PROTO_KSZ9893; 2950 2951 if (dev->chip_id == KSZ8567_CHIP_ID || 2952 dev->chip_id == KSZ9477_CHIP_ID || 2953 dev->chip_id == KSZ9896_CHIP_ID || 2954 dev->chip_id == KSZ9897_CHIP_ID || 2955 dev->chip_id == KSZ9567_CHIP_ID) 2956 proto = DSA_TAG_PROTO_KSZ9477; 2957 2958 if (is_lan937x(dev)) 2959 proto = DSA_TAG_PROTO_LAN937X; 2960 2961 return proto; 2962 } 2963 2964 static int ksz_connect_tag_protocol(struct dsa_switch *ds, 2965 enum dsa_tag_protocol proto) 2966 { 2967 struct ksz_tagger_data *tagger_data; 2968 2969 switch (proto) { 2970 case DSA_TAG_PROTO_KSZ8795: 2971 return 0; 2972 case DSA_TAG_PROTO_KSZ9893: 2973 case DSA_TAG_PROTO_KSZ9477: 2974 case DSA_TAG_PROTO_LAN937X: 2975 tagger_data = ksz_tagger_data(ds); 2976 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 2977 return 0; 2978 default: 2979 return -EPROTONOSUPPORT; 2980 } 2981 } 2982 2983 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 2984 bool flag, struct netlink_ext_ack *extack) 2985 { 2986 struct ksz_device *dev = ds->priv; 2987 2988 if (!dev->dev_ops->vlan_filtering) 2989 return -EOPNOTSUPP; 2990 2991 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 2992 } 2993 2994 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 2995 const struct switchdev_obj_port_vlan *vlan, 2996 struct netlink_ext_ack *extack) 2997 { 2998 struct ksz_device *dev = ds->priv; 2999 3000 if (!dev->dev_ops->vlan_add) 3001 return -EOPNOTSUPP; 3002 3003 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 3004 } 3005 3006 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 3007 const struct switchdev_obj_port_vlan *vlan) 3008 { 3009 struct ksz_device *dev = ds->priv; 3010 3011 if (!dev->dev_ops->vlan_del) 3012 return -EOPNOTSUPP; 3013 3014 return dev->dev_ops->vlan_del(dev, port, vlan); 3015 } 3016 3017 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 3018 struct dsa_mall_mirror_tc_entry *mirror, 3019 bool ingress, struct netlink_ext_ack *extack) 3020 { 3021 struct ksz_device *dev = ds->priv; 3022 3023 if (!dev->dev_ops->mirror_add) 3024 return -EOPNOTSUPP; 3025 3026 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 3027 } 3028 3029 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 3030 struct dsa_mall_mirror_tc_entry *mirror) 3031 { 3032 struct ksz_device *dev = ds->priv; 3033 3034 if (dev->dev_ops->mirror_del) 3035 dev->dev_ops->mirror_del(dev, port, mirror); 3036 } 3037 3038 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 3039 { 3040 struct ksz_device *dev = ds->priv; 3041 3042 if (!dev->dev_ops->change_mtu) 3043 return -EOPNOTSUPP; 3044 3045 return dev->dev_ops->change_mtu(dev, port, mtu); 3046 } 3047 3048 static int ksz_max_mtu(struct dsa_switch *ds, int port) 3049 { 3050 struct ksz_device *dev = ds->priv; 3051 3052 switch (dev->chip_id) { 3053 case KSZ8795_CHIP_ID: 3054 case KSZ8794_CHIP_ID: 3055 case KSZ8765_CHIP_ID: 3056 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3057 case KSZ8830_CHIP_ID: 3058 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3059 case KSZ8563_CHIP_ID: 3060 case KSZ8567_CHIP_ID: 3061 case KSZ9477_CHIP_ID: 3062 case KSZ9563_CHIP_ID: 3063 case KSZ9567_CHIP_ID: 3064 case KSZ9893_CHIP_ID: 3065 case KSZ9896_CHIP_ID: 3066 case KSZ9897_CHIP_ID: 3067 case LAN9370_CHIP_ID: 3068 case LAN9371_CHIP_ID: 3069 case LAN9372_CHIP_ID: 3070 case LAN9373_CHIP_ID: 3071 case LAN9374_CHIP_ID: 3072 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3073 } 3074 3075 return -EOPNOTSUPP; 3076 } 3077 3078 static int ksz_validate_eee(struct dsa_switch *ds, int port) 3079 { 3080 struct ksz_device *dev = ds->priv; 3081 3082 if (!dev->info->internal_phy[port]) 3083 return -EOPNOTSUPP; 3084 3085 switch (dev->chip_id) { 3086 case KSZ8563_CHIP_ID: 3087 case KSZ8567_CHIP_ID: 3088 case KSZ9477_CHIP_ID: 3089 case KSZ9563_CHIP_ID: 3090 case KSZ9567_CHIP_ID: 3091 case KSZ9893_CHIP_ID: 3092 case KSZ9896_CHIP_ID: 3093 case KSZ9897_CHIP_ID: 3094 return 0; 3095 } 3096 3097 return -EOPNOTSUPP; 3098 } 3099 3100 static int ksz_get_mac_eee(struct dsa_switch *ds, int port, 3101 struct ethtool_keee *e) 3102 { 3103 int ret; 3104 3105 ret = ksz_validate_eee(ds, port); 3106 if (ret) 3107 return ret; 3108 3109 /* There is no documented control of Tx LPI configuration. */ 3110 e->tx_lpi_enabled = true; 3111 3112 /* There is no documented control of Tx LPI timer. According to tests 3113 * Tx LPI timer seems to be set by default to minimal value. 3114 */ 3115 e->tx_lpi_timer = 0; 3116 3117 return 0; 3118 } 3119 3120 static int ksz_set_mac_eee(struct dsa_switch *ds, int port, 3121 struct ethtool_keee *e) 3122 { 3123 struct ksz_device *dev = ds->priv; 3124 int ret; 3125 3126 ret = ksz_validate_eee(ds, port); 3127 if (ret) 3128 return ret; 3129 3130 if (!e->tx_lpi_enabled) { 3131 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 3132 return -EINVAL; 3133 } 3134 3135 if (e->tx_lpi_timer) { 3136 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 3137 return -EINVAL; 3138 } 3139 3140 return 0; 3141 } 3142 3143 static void ksz_set_xmii(struct ksz_device *dev, int port, 3144 phy_interface_t interface) 3145 { 3146 const u8 *bitval = dev->info->xmii_ctrl1; 3147 struct ksz_port *p = &dev->ports[port]; 3148 const u16 *regs = dev->info->regs; 3149 u8 data8; 3150 3151 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3152 3153 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 3154 P_RGMII_ID_EG_ENABLE); 3155 3156 switch (interface) { 3157 case PHY_INTERFACE_MODE_MII: 3158 data8 |= bitval[P_MII_SEL]; 3159 break; 3160 case PHY_INTERFACE_MODE_RMII: 3161 data8 |= bitval[P_RMII_SEL]; 3162 break; 3163 case PHY_INTERFACE_MODE_GMII: 3164 data8 |= bitval[P_GMII_SEL]; 3165 break; 3166 case PHY_INTERFACE_MODE_RGMII: 3167 case PHY_INTERFACE_MODE_RGMII_ID: 3168 case PHY_INTERFACE_MODE_RGMII_TXID: 3169 case PHY_INTERFACE_MODE_RGMII_RXID: 3170 data8 |= bitval[P_RGMII_SEL]; 3171 /* On KSZ9893, disable RGMII in-band status support */ 3172 if (dev->chip_id == KSZ9893_CHIP_ID || 3173 dev->chip_id == KSZ8563_CHIP_ID || 3174 dev->chip_id == KSZ9563_CHIP_ID || 3175 is_lan937x(dev)) 3176 data8 &= ~P_MII_MAC_MODE; 3177 break; 3178 default: 3179 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 3180 phy_modes(interface), port); 3181 return; 3182 } 3183 3184 if (p->rgmii_tx_val) 3185 data8 |= P_RGMII_ID_EG_ENABLE; 3186 3187 if (p->rgmii_rx_val) 3188 data8 |= P_RGMII_ID_IG_ENABLE; 3189 3190 /* Write the updated value */ 3191 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3192 } 3193 3194 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 3195 { 3196 const u8 *bitval = dev->info->xmii_ctrl1; 3197 const u16 *regs = dev->info->regs; 3198 phy_interface_t interface; 3199 u8 data8; 3200 u8 val; 3201 3202 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3203 3204 val = FIELD_GET(P_MII_SEL_M, data8); 3205 3206 if (val == bitval[P_MII_SEL]) { 3207 if (gbit) 3208 interface = PHY_INTERFACE_MODE_GMII; 3209 else 3210 interface = PHY_INTERFACE_MODE_MII; 3211 } else if (val == bitval[P_RMII_SEL]) { 3212 interface = PHY_INTERFACE_MODE_RMII; 3213 } else { 3214 interface = PHY_INTERFACE_MODE_RGMII; 3215 if (data8 & P_RGMII_ID_EG_ENABLE) 3216 interface = PHY_INTERFACE_MODE_RGMII_TXID; 3217 if (data8 & P_RGMII_ID_IG_ENABLE) { 3218 interface = PHY_INTERFACE_MODE_RGMII_RXID; 3219 if (data8 & P_RGMII_ID_EG_ENABLE) 3220 interface = PHY_INTERFACE_MODE_RGMII_ID; 3221 } 3222 } 3223 3224 return interface; 3225 } 3226 3227 static void ksz8830_phylink_mac_config(struct phylink_config *config, 3228 unsigned int mode, 3229 const struct phylink_link_state *state) 3230 { 3231 struct dsa_port *dp = dsa_phylink_to_port(config); 3232 struct ksz_device *dev = dp->ds->priv; 3233 3234 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN); 3235 } 3236 3237 static void ksz_phylink_mac_config(struct phylink_config *config, 3238 unsigned int mode, 3239 const struct phylink_link_state *state) 3240 { 3241 struct dsa_port *dp = dsa_phylink_to_port(config); 3242 struct ksz_device *dev = dp->ds->priv; 3243 int port = dp->index; 3244 3245 /* Internal PHYs */ 3246 if (dev->info->internal_phy[port]) 3247 return; 3248 3249 if (phylink_autoneg_inband(mode)) { 3250 dev_err(dev->dev, "In-band AN not supported!\n"); 3251 return; 3252 } 3253 3254 ksz_set_xmii(dev, port, state->interface); 3255 3256 if (dev->dev_ops->setup_rgmii_delay) 3257 dev->dev_ops->setup_rgmii_delay(dev, port); 3258 } 3259 3260 bool ksz_get_gbit(struct ksz_device *dev, int port) 3261 { 3262 const u8 *bitval = dev->info->xmii_ctrl1; 3263 const u16 *regs = dev->info->regs; 3264 bool gbit = false; 3265 u8 data8; 3266 bool val; 3267 3268 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3269 3270 val = FIELD_GET(P_GMII_1GBIT_M, data8); 3271 3272 if (val == bitval[P_GMII_1GBIT]) 3273 gbit = true; 3274 3275 return gbit; 3276 } 3277 3278 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 3279 { 3280 const u8 *bitval = dev->info->xmii_ctrl1; 3281 const u16 *regs = dev->info->regs; 3282 u8 data8; 3283 3284 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3285 3286 data8 &= ~P_GMII_1GBIT_M; 3287 3288 if (gbit) 3289 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 3290 else 3291 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 3292 3293 /* Write the updated value */ 3294 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3295 } 3296 3297 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 3298 { 3299 const u8 *bitval = dev->info->xmii_ctrl0; 3300 const u16 *regs = dev->info->regs; 3301 u8 data8; 3302 3303 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 3304 3305 data8 &= ~P_MII_100MBIT_M; 3306 3307 if (speed == SPEED_100) 3308 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 3309 else 3310 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 3311 3312 /* Write the updated value */ 3313 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 3314 } 3315 3316 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 3317 { 3318 if (speed == SPEED_1000) 3319 ksz_set_gbit(dev, port, true); 3320 else 3321 ksz_set_gbit(dev, port, false); 3322 3323 if (speed == SPEED_100 || speed == SPEED_10) 3324 ksz_set_100_10mbit(dev, port, speed); 3325 } 3326 3327 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 3328 bool tx_pause, bool rx_pause) 3329 { 3330 const u8 *bitval = dev->info->xmii_ctrl0; 3331 const u32 *masks = dev->info->masks; 3332 const u16 *regs = dev->info->regs; 3333 u8 mask; 3334 u8 val; 3335 3336 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 3337 masks[P_MII_RX_FLOW_CTRL]; 3338 3339 if (duplex == DUPLEX_FULL) 3340 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 3341 else 3342 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 3343 3344 if (tx_pause) 3345 val |= masks[P_MII_TX_FLOW_CTRL]; 3346 3347 if (rx_pause) 3348 val |= masks[P_MII_RX_FLOW_CTRL]; 3349 3350 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 3351 } 3352 3353 static void ksz9477_phylink_mac_link_up(struct phylink_config *config, 3354 struct phy_device *phydev, 3355 unsigned int mode, 3356 phy_interface_t interface, 3357 int speed, int duplex, bool tx_pause, 3358 bool rx_pause) 3359 { 3360 struct dsa_port *dp = dsa_phylink_to_port(config); 3361 struct ksz_device *dev = dp->ds->priv; 3362 int port = dp->index; 3363 struct ksz_port *p; 3364 3365 p = &dev->ports[port]; 3366 3367 /* Internal PHYs */ 3368 if (dev->info->internal_phy[port]) 3369 return; 3370 3371 p->phydev.speed = speed; 3372 3373 ksz_port_set_xmii_speed(dev, port, speed); 3374 3375 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 3376 } 3377 3378 static int ksz_switch_detect(struct ksz_device *dev) 3379 { 3380 u8 id1, id2, id4; 3381 u16 id16; 3382 u32 id32; 3383 int ret; 3384 3385 /* read chip id */ 3386 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 3387 if (ret) 3388 return ret; 3389 3390 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 3391 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 3392 3393 switch (id1) { 3394 case KSZ87_FAMILY_ID: 3395 if (id2 == KSZ87_CHIP_ID_95) { 3396 u8 val; 3397 3398 dev->chip_id = KSZ8795_CHIP_ID; 3399 3400 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 3401 if (val & KSZ8_PORT_FIBER_MODE) 3402 dev->chip_id = KSZ8765_CHIP_ID; 3403 } else if (id2 == KSZ87_CHIP_ID_94) { 3404 dev->chip_id = KSZ8794_CHIP_ID; 3405 } else { 3406 return -ENODEV; 3407 } 3408 break; 3409 case KSZ88_FAMILY_ID: 3410 if (id2 == KSZ88_CHIP_ID_63) 3411 dev->chip_id = KSZ8830_CHIP_ID; 3412 else 3413 return -ENODEV; 3414 break; 3415 default: 3416 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 3417 if (ret) 3418 return ret; 3419 3420 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 3421 id32 &= ~0xFF; 3422 3423 switch (id32) { 3424 case KSZ9477_CHIP_ID: 3425 case KSZ9896_CHIP_ID: 3426 case KSZ9897_CHIP_ID: 3427 case KSZ9567_CHIP_ID: 3428 case KSZ8567_CHIP_ID: 3429 case LAN9370_CHIP_ID: 3430 case LAN9371_CHIP_ID: 3431 case LAN9372_CHIP_ID: 3432 case LAN9373_CHIP_ID: 3433 case LAN9374_CHIP_ID: 3434 dev->chip_id = id32; 3435 break; 3436 case KSZ9893_CHIP_ID: 3437 ret = ksz_read8(dev, REG_CHIP_ID4, 3438 &id4); 3439 if (ret) 3440 return ret; 3441 3442 if (id4 == SKU_ID_KSZ8563) 3443 dev->chip_id = KSZ8563_CHIP_ID; 3444 else if (id4 == SKU_ID_KSZ9563) 3445 dev->chip_id = KSZ9563_CHIP_ID; 3446 else 3447 dev->chip_id = KSZ9893_CHIP_ID; 3448 3449 break; 3450 default: 3451 dev_err(dev->dev, 3452 "unsupported switch detected %x)\n", id32); 3453 return -ENODEV; 3454 } 3455 } 3456 return 0; 3457 } 3458 3459 static int ksz_cls_flower_add(struct dsa_switch *ds, int port, 3460 struct flow_cls_offload *cls, bool ingress) 3461 { 3462 struct ksz_device *dev = ds->priv; 3463 3464 switch (dev->chip_id) { 3465 case KSZ8563_CHIP_ID: 3466 case KSZ8567_CHIP_ID: 3467 case KSZ9477_CHIP_ID: 3468 case KSZ9563_CHIP_ID: 3469 case KSZ9567_CHIP_ID: 3470 case KSZ9893_CHIP_ID: 3471 case KSZ9896_CHIP_ID: 3472 case KSZ9897_CHIP_ID: 3473 return ksz9477_cls_flower_add(ds, port, cls, ingress); 3474 } 3475 3476 return -EOPNOTSUPP; 3477 } 3478 3479 static int ksz_cls_flower_del(struct dsa_switch *ds, int port, 3480 struct flow_cls_offload *cls, bool ingress) 3481 { 3482 struct ksz_device *dev = ds->priv; 3483 3484 switch (dev->chip_id) { 3485 case KSZ8563_CHIP_ID: 3486 case KSZ8567_CHIP_ID: 3487 case KSZ9477_CHIP_ID: 3488 case KSZ9563_CHIP_ID: 3489 case KSZ9567_CHIP_ID: 3490 case KSZ9893_CHIP_ID: 3491 case KSZ9896_CHIP_ID: 3492 case KSZ9897_CHIP_ID: 3493 return ksz9477_cls_flower_del(ds, port, cls, ingress); 3494 } 3495 3496 return -EOPNOTSUPP; 3497 } 3498 3499 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 3500 * is converted to Hex-decimal using the successive multiplication method. On 3501 * every step, integer part is taken and decimal part is carry forwarded. 3502 */ 3503 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 3504 { 3505 u32 cinc = 0; 3506 u32 txrate; 3507 u32 rate; 3508 u8 temp; 3509 u8 i; 3510 3511 txrate = idle_slope - send_slope; 3512 3513 if (!txrate) 3514 return -EINVAL; 3515 3516 rate = idle_slope; 3517 3518 /* 24 bit register */ 3519 for (i = 0; i < 6; i++) { 3520 rate = rate * 16; 3521 3522 temp = rate / txrate; 3523 3524 rate %= txrate; 3525 3526 cinc = ((cinc << 4) | temp); 3527 } 3528 3529 *bw = cinc; 3530 3531 return 0; 3532 } 3533 3534 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 3535 u8 shaper) 3536 { 3537 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 3538 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 3539 FIELD_PREP(MTI_SHAPING_M, shaper)); 3540 } 3541 3542 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 3543 struct tc_cbs_qopt_offload *qopt) 3544 { 3545 struct ksz_device *dev = ds->priv; 3546 int ret; 3547 u32 bw; 3548 3549 if (!dev->info->tc_cbs_supported) 3550 return -EOPNOTSUPP; 3551 3552 if (qopt->queue > dev->info->num_tx_queues) 3553 return -EINVAL; 3554 3555 /* Queue Selection */ 3556 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 3557 if (ret) 3558 return ret; 3559 3560 if (!qopt->enable) 3561 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3562 MTI_SHAPING_OFF); 3563 3564 /* High Credit */ 3565 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 3566 qopt->hicredit); 3567 if (ret) 3568 return ret; 3569 3570 /* Low Credit */ 3571 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 3572 qopt->locredit); 3573 if (ret) 3574 return ret; 3575 3576 /* Credit Increment Register */ 3577 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 3578 if (ret) 3579 return ret; 3580 3581 if (dev->dev_ops->tc_cbs_set_cinc) { 3582 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 3583 if (ret) 3584 return ret; 3585 } 3586 3587 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3588 MTI_SHAPING_SRP); 3589 } 3590 3591 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 3592 { 3593 int queue, ret; 3594 3595 /* Configuration will not take effect until the last Port Queue X 3596 * Egress Limit Control Register is written. 3597 */ 3598 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3599 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 3600 KSZ9477_OUT_RATE_NO_LIMIT); 3601 if (ret) 3602 return ret; 3603 } 3604 3605 return 0; 3606 } 3607 3608 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 3609 int band) 3610 { 3611 /* Compared to queues, bands prioritize packets differently. In strict 3612 * priority mode, the lowest priority is assigned to Queue 0 while the 3613 * highest priority is given to Band 0. 3614 */ 3615 return p->bands - 1 - band; 3616 } 3617 3618 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 3619 { 3620 int ret; 3621 3622 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3623 if (ret) 3624 return ret; 3625 3626 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3627 MTI_SHAPING_OFF); 3628 } 3629 3630 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 3631 int weight) 3632 { 3633 int ret; 3634 3635 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3636 if (ret) 3637 return ret; 3638 3639 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3640 MTI_SHAPING_OFF); 3641 if (ret) 3642 return ret; 3643 3644 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 3645 } 3646 3647 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 3648 struct tc_ets_qopt_offload_replace_params *p) 3649 { 3650 int ret, band, tc_prio; 3651 u32 queue_map = 0; 3652 3653 /* In order to ensure proper prioritization, it is necessary to set the 3654 * rate limit for the related queue to zero. Otherwise strict priority 3655 * or WRR mode will not work. This is a hardware limitation. 3656 */ 3657 ret = ksz_disable_egress_rate_limit(dev, port); 3658 if (ret) 3659 return ret; 3660 3661 /* Configure queue scheduling mode for all bands. Currently only strict 3662 * prio mode is supported. 3663 */ 3664 for (band = 0; band < p->bands; band++) { 3665 int queue = ksz_ets_band_to_queue(p, band); 3666 3667 ret = ksz_queue_set_strict(dev, port, queue); 3668 if (ret) 3669 return ret; 3670 } 3671 3672 /* Configure the mapping between traffic classes and queues. Note: 3673 * priomap variable support 16 traffic classes, but the chip can handle 3674 * only 8 classes. 3675 */ 3676 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 3677 int queue; 3678 3679 if (tc_prio >= dev->info->num_ipms) 3680 break; 3681 3682 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 3683 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3684 } 3685 3686 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3687 } 3688 3689 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 3690 { 3691 int ret, queue; 3692 3693 /* To restore the default chip configuration, set all queues to use the 3694 * WRR scheduler with a weight of 1. 3695 */ 3696 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3697 ret = ksz_queue_set_wrr(dev, port, queue, 3698 KSZ9477_DEFAULT_WRR_WEIGHT); 3699 if (ret) 3700 return ret; 3701 } 3702 3703 /* Revert the queue mapping for TC-priority to its default setting on 3704 * the chip. 3705 */ 3706 return ksz9477_set_default_prio_queue_mapping(dev, port); 3707 } 3708 3709 static int ksz_tc_ets_validate(struct ksz_device *dev, int port, 3710 struct tc_ets_qopt_offload_replace_params *p) 3711 { 3712 int band; 3713 3714 /* Since it is not feasible to share one port among multiple qdisc, 3715 * the user must configure all available queues appropriately. 3716 */ 3717 if (p->bands != dev->info->num_tx_queues) { 3718 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 3719 dev->info->num_tx_queues); 3720 return -EOPNOTSUPP; 3721 } 3722 3723 for (band = 0; band < p->bands; ++band) { 3724 /* The KSZ switches utilize a weighted round robin configuration 3725 * where a certain number of packets can be transmitted from a 3726 * queue before the next queue is serviced. For more information 3727 * on this, refer to section 5.2.8.4 of the KSZ8565R 3728 * documentation on the Port Transmit Queue Control 1 Register. 3729 * However, the current ETS Qdisc implementation (as of February 3730 * 2023) assigns a weight to each queue based on the number of 3731 * bytes or extrapolated bandwidth in percentages. Since this 3732 * differs from the KSZ switches' method and we don't want to 3733 * fake support by converting bytes to packets, it is better to 3734 * return an error instead. 3735 */ 3736 if (p->quanta[band]) { 3737 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 3738 return -EOPNOTSUPP; 3739 } 3740 } 3741 3742 return 0; 3743 } 3744 3745 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 3746 struct tc_ets_qopt_offload *qopt) 3747 { 3748 struct ksz_device *dev = ds->priv; 3749 int ret; 3750 3751 if (is_ksz8(dev)) 3752 return -EOPNOTSUPP; 3753 3754 if (qopt->parent != TC_H_ROOT) { 3755 dev_err(dev->dev, "Parent should be \"root\"\n"); 3756 return -EOPNOTSUPP; 3757 } 3758 3759 switch (qopt->command) { 3760 case TC_ETS_REPLACE: 3761 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 3762 if (ret) 3763 return ret; 3764 3765 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 3766 case TC_ETS_DESTROY: 3767 return ksz_tc_ets_del(dev, port); 3768 case TC_ETS_STATS: 3769 case TC_ETS_GRAFT: 3770 return -EOPNOTSUPP; 3771 } 3772 3773 return -EOPNOTSUPP; 3774 } 3775 3776 static int ksz_setup_tc(struct dsa_switch *ds, int port, 3777 enum tc_setup_type type, void *type_data) 3778 { 3779 switch (type) { 3780 case TC_SETUP_QDISC_CBS: 3781 return ksz_setup_tc_cbs(ds, port, type_data); 3782 case TC_SETUP_QDISC_ETS: 3783 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 3784 default: 3785 return -EOPNOTSUPP; 3786 } 3787 } 3788 3789 /** 3790 * ksz_handle_wake_reason - Handle wake reason on a specified port. 3791 * @dev: The device structure. 3792 * @port: The port number. 3793 * 3794 * This function reads the PME (Power Management Event) status register of a 3795 * specified port to determine the wake reason. If there is no wake event, it 3796 * returns early. Otherwise, it logs the wake reason which could be due to a 3797 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register 3798 * is then cleared to acknowledge the handling of the wake event. 3799 * 3800 * Return: 0 on success, or an error code on failure. 3801 */ 3802 int ksz_handle_wake_reason(struct ksz_device *dev, int port) 3803 { 3804 const struct ksz_dev_ops *ops = dev->dev_ops; 3805 const u16 *regs = dev->info->regs; 3806 u8 pme_status; 3807 int ret; 3808 3809 ret = ops->pme_pread8(dev, port, regs[REG_PORT_PME_STATUS], 3810 &pme_status); 3811 if (ret) 3812 return ret; 3813 3814 if (!pme_status) 3815 return 0; 3816 3817 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port, 3818 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "", 3819 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "", 3820 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : ""); 3821 3822 return ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_STATUS], 3823 pme_status); 3824 } 3825 3826 /** 3827 * ksz_get_wol - Get Wake-on-LAN settings for a specified port. 3828 * @ds: The dsa_switch structure. 3829 * @port: The port number. 3830 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 3831 * 3832 * This function checks the device PME wakeup_source flag and chip_id. 3833 * If enabled and supported, it sets the supported and active WoL 3834 * flags. 3835 */ 3836 static void ksz_get_wol(struct dsa_switch *ds, int port, 3837 struct ethtool_wolinfo *wol) 3838 { 3839 struct ksz_device *dev = ds->priv; 3840 const u16 *regs = dev->info->regs; 3841 u8 pme_ctrl; 3842 int ret; 3843 3844 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 3845 return; 3846 3847 if (!dev->wakeup_source) 3848 return; 3849 3850 wol->supported = WAKE_PHY; 3851 3852 /* Check if the current MAC address on this port can be set 3853 * as global for WAKE_MAGIC support. The result may vary 3854 * dynamically based on other ports configurations. 3855 */ 3856 if (ksz_is_port_mac_global_usable(dev->ds, port)) 3857 wol->supported |= WAKE_MAGIC; 3858 3859 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 3860 &pme_ctrl); 3861 if (ret) 3862 return; 3863 3864 if (pme_ctrl & PME_WOL_MAGICPKT) 3865 wol->wolopts |= WAKE_MAGIC; 3866 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY)) 3867 wol->wolopts |= WAKE_PHY; 3868 } 3869 3870 /** 3871 * ksz_set_wol - Set Wake-on-LAN settings for a specified port. 3872 * @ds: The dsa_switch structure. 3873 * @port: The port number. 3874 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 3875 * 3876 * This function configures Wake-on-LAN (WoL) settings for a specified 3877 * port. It validates the provided WoL options, checks if PME is 3878 * enabled and supported, clears any previous wake reasons, and sets 3879 * the Magic Packet flag in the port's PME control register if 3880 * specified. 3881 * 3882 * Return: 0 on success, or other error codes on failure. 3883 */ 3884 static int ksz_set_wol(struct dsa_switch *ds, int port, 3885 struct ethtool_wolinfo *wol) 3886 { 3887 u8 pme_ctrl = 0, pme_ctrl_old = 0; 3888 struct ksz_device *dev = ds->priv; 3889 const u16 *regs = dev->info->regs; 3890 bool magic_switched_off; 3891 bool magic_switched_on; 3892 int ret; 3893 3894 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC)) 3895 return -EINVAL; 3896 3897 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 3898 return -EOPNOTSUPP; 3899 3900 if (!dev->wakeup_source) 3901 return -EOPNOTSUPP; 3902 3903 ret = ksz_handle_wake_reason(dev, port); 3904 if (ret) 3905 return ret; 3906 3907 if (wol->wolopts & WAKE_MAGIC) 3908 pme_ctrl |= PME_WOL_MAGICPKT; 3909 if (wol->wolopts & WAKE_PHY) 3910 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY; 3911 3912 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 3913 &pme_ctrl_old); 3914 if (ret) 3915 return ret; 3916 3917 if (pme_ctrl_old == pme_ctrl) 3918 return 0; 3919 3920 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) && 3921 !(pme_ctrl & PME_WOL_MAGICPKT); 3922 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) && 3923 (pme_ctrl & PME_WOL_MAGICPKT); 3924 3925 /* To keep reference count of MAC address, we should do this 3926 * operation only on change of WOL settings. 3927 */ 3928 if (magic_switched_on) { 3929 ret = ksz_switch_macaddr_get(dev->ds, port, NULL); 3930 if (ret) 3931 return ret; 3932 } else if (magic_switched_off) { 3933 ksz_switch_macaddr_put(dev->ds); 3934 } 3935 3936 ret = dev->dev_ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 3937 pme_ctrl); 3938 if (ret) { 3939 if (magic_switched_on) 3940 ksz_switch_macaddr_put(dev->ds); 3941 return ret; 3942 } 3943 3944 return 0; 3945 } 3946 3947 /** 3948 * ksz_wol_pre_shutdown - Prepares the switch device for shutdown while 3949 * considering Wake-on-LAN (WoL) settings. 3950 * @dev: The switch device structure. 3951 * @wol_enabled: Pointer to a boolean which will be set to true if WoL is 3952 * enabled on any port. 3953 * 3954 * This function prepares the switch device for a safe shutdown while taking 3955 * into account the Wake-on-LAN (WoL) settings on the user ports. It updates 3956 * the wol_enabled flag accordingly to reflect whether WoL is active on any 3957 * port. 3958 */ 3959 static void ksz_wol_pre_shutdown(struct ksz_device *dev, bool *wol_enabled) 3960 { 3961 const struct ksz_dev_ops *ops = dev->dev_ops; 3962 const u16 *regs = dev->info->regs; 3963 u8 pme_pin_en = PME_ENABLE; 3964 struct dsa_port *dp; 3965 int ret; 3966 3967 *wol_enabled = false; 3968 3969 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 3970 return; 3971 3972 if (!dev->wakeup_source) 3973 return; 3974 3975 dsa_switch_for_each_user_port(dp, dev->ds) { 3976 u8 pme_ctrl = 0; 3977 3978 ret = ops->pme_pread8(dev, dp->index, 3979 regs[REG_PORT_PME_CTRL], &pme_ctrl); 3980 if (!ret && pme_ctrl) 3981 *wol_enabled = true; 3982 3983 /* make sure there are no pending wake events which would 3984 * prevent the device from going to sleep/shutdown. 3985 */ 3986 ksz_handle_wake_reason(dev, dp->index); 3987 } 3988 3989 /* Now we are save to enable PME pin. */ 3990 if (*wol_enabled) { 3991 if (dev->pme_active_high) 3992 pme_pin_en |= PME_POLARITY; 3993 ops->pme_write8(dev, regs[REG_SW_PME_CTRL], pme_pin_en); 3994 if (ksz_is_ksz87xx(dev)) 3995 ksz_write8(dev, KSZ87XX_REG_INT_EN, KSZ87XX_INT_PME_MASK); 3996 } 3997 } 3998 3999 static int ksz_port_set_mac_address(struct dsa_switch *ds, int port, 4000 const unsigned char *addr) 4001 { 4002 struct dsa_port *dp = dsa_to_port(ds, port); 4003 struct ethtool_wolinfo wol; 4004 4005 if (dp->hsr_dev) { 4006 dev_err(ds->dev, 4007 "Cannot change MAC address on port %d with active HSR offload\n", 4008 port); 4009 return -EBUSY; 4010 } 4011 4012 /* Need to initialize variable as the code to fill in settings may 4013 * not be executed. 4014 */ 4015 wol.wolopts = 0; 4016 4017 ksz_get_wol(ds, dp->index, &wol); 4018 if (wol.wolopts & WAKE_MAGIC) { 4019 dev_err(ds->dev, 4020 "Cannot change MAC address on port %d with active Wake on Magic Packet\n", 4021 port); 4022 return -EBUSY; 4023 } 4024 4025 return 0; 4026 } 4027 4028 /** 4029 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port 4030 * can be used as a global address. 4031 * @ds: Pointer to the DSA switch structure. 4032 * @port: The port number on which the MAC address is to be checked. 4033 * 4034 * This function examines the MAC address set on the specified port and 4035 * determines if it can be used as a global address for the switch. 4036 * 4037 * Return: true if the port's MAC address can be used as a global address, false 4038 * otherwise. 4039 */ 4040 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port) 4041 { 4042 struct net_device *user = dsa_to_port(ds, port)->user; 4043 const unsigned char *addr = user->dev_addr; 4044 struct ksz_switch_macaddr *switch_macaddr; 4045 struct ksz_device *dev = ds->priv; 4046 4047 ASSERT_RTNL(); 4048 4049 switch_macaddr = dev->switch_macaddr; 4050 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr)) 4051 return false; 4052 4053 return true; 4054 } 4055 4056 /** 4057 * ksz_switch_macaddr_get - Program the switch's MAC address register. 4058 * @ds: DSA switch instance. 4059 * @port: Port number. 4060 * @extack: Netlink extended acknowledgment. 4061 * 4062 * This function programs the switch's MAC address register with the MAC address 4063 * of the requesting user port. This single address is used by the switch for 4064 * multiple features like HSR self-address filtering and WoL. Other user ports 4065 * can share ownership of this address as long as their MAC address is the same. 4066 * The MAC addresses of user ports must not change while they have ownership of 4067 * the switch MAC address. 4068 * 4069 * Return: 0 on success, or other error codes on failure. 4070 */ 4071 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 4072 struct netlink_ext_ack *extack) 4073 { 4074 struct net_device *user = dsa_to_port(ds, port)->user; 4075 const unsigned char *addr = user->dev_addr; 4076 struct ksz_switch_macaddr *switch_macaddr; 4077 struct ksz_device *dev = ds->priv; 4078 const u16 *regs = dev->info->regs; 4079 int i, ret; 4080 4081 /* Make sure concurrent MAC address changes are blocked */ 4082 ASSERT_RTNL(); 4083 4084 switch_macaddr = dev->switch_macaddr; 4085 if (switch_macaddr) { 4086 if (!ether_addr_equal(switch_macaddr->addr, addr)) { 4087 NL_SET_ERR_MSG_FMT_MOD(extack, 4088 "Switch already configured for MAC address %pM", 4089 switch_macaddr->addr); 4090 return -EBUSY; 4091 } 4092 4093 refcount_inc(&switch_macaddr->refcount); 4094 return 0; 4095 } 4096 4097 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL); 4098 if (!switch_macaddr) 4099 return -ENOMEM; 4100 4101 ether_addr_copy(switch_macaddr->addr, addr); 4102 refcount_set(&switch_macaddr->refcount, 1); 4103 dev->switch_macaddr = switch_macaddr; 4104 4105 /* Program the switch MAC address to hardware */ 4106 for (i = 0; i < ETH_ALEN; i++) { 4107 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, addr[i]); 4108 if (ret) 4109 goto macaddr_drop; 4110 } 4111 4112 return 0; 4113 4114 macaddr_drop: 4115 dev->switch_macaddr = NULL; 4116 refcount_set(&switch_macaddr->refcount, 0); 4117 kfree(switch_macaddr); 4118 4119 return ret; 4120 } 4121 4122 void ksz_switch_macaddr_put(struct dsa_switch *ds) 4123 { 4124 struct ksz_switch_macaddr *switch_macaddr; 4125 struct ksz_device *dev = ds->priv; 4126 const u16 *regs = dev->info->regs; 4127 int i; 4128 4129 /* Make sure concurrent MAC address changes are blocked */ 4130 ASSERT_RTNL(); 4131 4132 switch_macaddr = dev->switch_macaddr; 4133 if (!refcount_dec_and_test(&switch_macaddr->refcount)) 4134 return; 4135 4136 for (i = 0; i < ETH_ALEN; i++) 4137 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0); 4138 4139 dev->switch_macaddr = NULL; 4140 kfree(switch_macaddr); 4141 } 4142 4143 static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr, 4144 struct netlink_ext_ack *extack) 4145 { 4146 struct ksz_device *dev = ds->priv; 4147 enum hsr_version ver; 4148 int ret; 4149 4150 ret = hsr_get_version(hsr, &ver); 4151 if (ret) 4152 return ret; 4153 4154 if (dev->chip_id != KSZ9477_CHIP_ID) { 4155 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload"); 4156 return -EOPNOTSUPP; 4157 } 4158 4159 /* KSZ9477 can support HW offloading of only 1 HSR device */ 4160 if (dev->hsr_dev && hsr != dev->hsr_dev) { 4161 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR"); 4162 return -EOPNOTSUPP; 4163 } 4164 4165 /* KSZ9477 only supports HSR v0 and v1 */ 4166 if (!(ver == HSR_V0 || ver == HSR_V1)) { 4167 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported"); 4168 return -EOPNOTSUPP; 4169 } 4170 4171 /* KSZ9477 can only perform HSR offloading for up to two ports */ 4172 if (hweight8(dev->hsr_ports) >= 2) { 4173 NL_SET_ERR_MSG_MOD(extack, 4174 "Cannot offload more than two ports - using software HSR"); 4175 return -EOPNOTSUPP; 4176 } 4177 4178 /* Self MAC address filtering, to avoid frames traversing 4179 * the HSR ring more than once. 4180 */ 4181 ret = ksz_switch_macaddr_get(ds, port, extack); 4182 if (ret) 4183 return ret; 4184 4185 ksz9477_hsr_join(ds, port, hsr); 4186 dev->hsr_dev = hsr; 4187 dev->hsr_ports |= BIT(port); 4188 4189 return 0; 4190 } 4191 4192 static int ksz_hsr_leave(struct dsa_switch *ds, int port, 4193 struct net_device *hsr) 4194 { 4195 struct ksz_device *dev = ds->priv; 4196 4197 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID); 4198 4199 ksz9477_hsr_leave(ds, port, hsr); 4200 dev->hsr_ports &= ~BIT(port); 4201 if (!dev->hsr_ports) 4202 dev->hsr_dev = NULL; 4203 4204 ksz_switch_macaddr_put(ds); 4205 4206 return 0; 4207 } 4208 4209 static const struct dsa_switch_ops ksz_switch_ops = { 4210 .get_tag_protocol = ksz_get_tag_protocol, 4211 .connect_tag_protocol = ksz_connect_tag_protocol, 4212 .get_phy_flags = ksz_get_phy_flags, 4213 .setup = ksz_setup, 4214 .teardown = ksz_teardown, 4215 .phy_read = ksz_phy_read16, 4216 .phy_write = ksz_phy_write16, 4217 .phylink_get_caps = ksz_phylink_get_caps, 4218 .port_setup = ksz_port_setup, 4219 .set_ageing_time = ksz_set_ageing_time, 4220 .get_strings = ksz_get_strings, 4221 .get_ethtool_stats = ksz_get_ethtool_stats, 4222 .get_sset_count = ksz_sset_count, 4223 .port_bridge_join = ksz_port_bridge_join, 4224 .port_bridge_leave = ksz_port_bridge_leave, 4225 .port_hsr_join = ksz_hsr_join, 4226 .port_hsr_leave = ksz_hsr_leave, 4227 .port_set_mac_address = ksz_port_set_mac_address, 4228 .port_stp_state_set = ksz_port_stp_state_set, 4229 .port_teardown = ksz_port_teardown, 4230 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 4231 .port_bridge_flags = ksz_port_bridge_flags, 4232 .port_fast_age = ksz_port_fast_age, 4233 .port_vlan_filtering = ksz_port_vlan_filtering, 4234 .port_vlan_add = ksz_port_vlan_add, 4235 .port_vlan_del = ksz_port_vlan_del, 4236 .port_fdb_dump = ksz_port_fdb_dump, 4237 .port_fdb_add = ksz_port_fdb_add, 4238 .port_fdb_del = ksz_port_fdb_del, 4239 .port_mdb_add = ksz_port_mdb_add, 4240 .port_mdb_del = ksz_port_mdb_del, 4241 .port_mirror_add = ksz_port_mirror_add, 4242 .port_mirror_del = ksz_port_mirror_del, 4243 .get_stats64 = ksz_get_stats64, 4244 .get_pause_stats = ksz_get_pause_stats, 4245 .port_change_mtu = ksz_change_mtu, 4246 .port_max_mtu = ksz_max_mtu, 4247 .get_wol = ksz_get_wol, 4248 .set_wol = ksz_set_wol, 4249 .get_ts_info = ksz_get_ts_info, 4250 .port_hwtstamp_get = ksz_hwtstamp_get, 4251 .port_hwtstamp_set = ksz_hwtstamp_set, 4252 .port_txtstamp = ksz_port_txtstamp, 4253 .port_rxtstamp = ksz_port_rxtstamp, 4254 .cls_flower_add = ksz_cls_flower_add, 4255 .cls_flower_del = ksz_cls_flower_del, 4256 .port_setup_tc = ksz_setup_tc, 4257 .get_mac_eee = ksz_get_mac_eee, 4258 .set_mac_eee = ksz_set_mac_eee, 4259 .port_get_default_prio = ksz_port_get_default_prio, 4260 .port_set_default_prio = ksz_port_set_default_prio, 4261 .port_get_dscp_prio = ksz_port_get_dscp_prio, 4262 .port_add_dscp_prio = ksz_port_add_dscp_prio, 4263 .port_del_dscp_prio = ksz_port_del_dscp_prio, 4264 .port_get_apptrust = ksz_port_get_apptrust, 4265 .port_set_apptrust = ksz_port_set_apptrust, 4266 }; 4267 4268 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 4269 { 4270 struct dsa_switch *ds; 4271 struct ksz_device *swdev; 4272 4273 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 4274 if (!ds) 4275 return NULL; 4276 4277 ds->dev = base; 4278 ds->num_ports = DSA_MAX_PORTS; 4279 ds->ops = &ksz_switch_ops; 4280 4281 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 4282 if (!swdev) 4283 return NULL; 4284 4285 ds->priv = swdev; 4286 swdev->dev = base; 4287 4288 swdev->ds = ds; 4289 swdev->priv = priv; 4290 4291 return swdev; 4292 } 4293 EXPORT_SYMBOL(ksz_switch_alloc); 4294 4295 /** 4296 * ksz_switch_shutdown - Shutdown routine for the switch device. 4297 * @dev: The switch device structure. 4298 * 4299 * This function is responsible for initiating a shutdown sequence for the 4300 * switch device. It invokes the reset operation defined in the device 4301 * operations, if available, to reset the switch. Subsequently, it calls the 4302 * DSA framework's shutdown function to ensure a proper shutdown of the DSA 4303 * switch. 4304 */ 4305 void ksz_switch_shutdown(struct ksz_device *dev) 4306 { 4307 bool wol_enabled = false; 4308 4309 ksz_wol_pre_shutdown(dev, &wol_enabled); 4310 4311 if (dev->dev_ops->reset && !wol_enabled) 4312 dev->dev_ops->reset(dev); 4313 4314 dsa_switch_shutdown(dev->ds); 4315 } 4316 EXPORT_SYMBOL(ksz_switch_shutdown); 4317 4318 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 4319 struct device_node *port_dn) 4320 { 4321 phy_interface_t phy_mode = dev->ports[port_num].interface; 4322 int rx_delay = -1, tx_delay = -1; 4323 4324 if (!phy_interface_mode_is_rgmii(phy_mode)) 4325 return; 4326 4327 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 4328 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 4329 4330 if (rx_delay == -1 && tx_delay == -1) { 4331 dev_warn(dev->dev, 4332 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 4333 "please update device tree to specify \"rx-internal-delay-ps\" and " 4334 "\"tx-internal-delay-ps\"", 4335 port_num); 4336 4337 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 4338 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 4339 rx_delay = 2000; 4340 4341 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 4342 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 4343 tx_delay = 2000; 4344 } 4345 4346 if (rx_delay < 0) 4347 rx_delay = 0; 4348 if (tx_delay < 0) 4349 tx_delay = 0; 4350 4351 dev->ports[port_num].rgmii_rx_val = rx_delay; 4352 dev->ports[port_num].rgmii_tx_val = tx_delay; 4353 } 4354 4355 /** 4356 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding 4357 * register value. 4358 * @array: The array of drive strength values to search. 4359 * @array_size: The size of the array. 4360 * @microamp: The drive strength value in microamp to be converted. 4361 * 4362 * This function searches the array of drive strength values for the given 4363 * microamp value and returns the corresponding register value for that drive. 4364 * 4365 * Returns: If found, the corresponding register value for that drive strength 4366 * is returned. Otherwise, -EINVAL is returned indicating an invalid value. 4367 */ 4368 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array, 4369 size_t array_size, int microamp) 4370 { 4371 int i; 4372 4373 for (i = 0; i < array_size; i++) { 4374 if (array[i].microamp == microamp) 4375 return array[i].reg_val; 4376 } 4377 4378 return -EINVAL; 4379 } 4380 4381 /** 4382 * ksz_drive_strength_error() - Report invalid drive strength value 4383 * @dev: ksz device 4384 * @array: The array of drive strength values to search. 4385 * @array_size: The size of the array. 4386 * @microamp: Invalid drive strength value in microamp 4387 * 4388 * This function logs an error message when an unsupported drive strength value 4389 * is detected. It lists out all the supported drive strength values for 4390 * reference in the error message. 4391 */ 4392 static void ksz_drive_strength_error(struct ksz_device *dev, 4393 const struct ksz_drive_strength *array, 4394 size_t array_size, int microamp) 4395 { 4396 char supported_values[100]; 4397 size_t remaining_size; 4398 int added_len; 4399 char *ptr; 4400 int i; 4401 4402 remaining_size = sizeof(supported_values); 4403 ptr = supported_values; 4404 4405 for (i = 0; i < array_size; i++) { 4406 added_len = snprintf(ptr, remaining_size, 4407 i == 0 ? "%d" : ", %d", array[i].microamp); 4408 4409 if (added_len >= remaining_size) 4410 break; 4411 4412 ptr += added_len; 4413 remaining_size -= added_len; 4414 } 4415 4416 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n", 4417 microamp, supported_values); 4418 } 4419 4420 /** 4421 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477 4422 * chip variants. 4423 * @dev: ksz device 4424 * @props: Array of drive strength properties to be applied 4425 * @num_props: Number of properties in the array 4426 * 4427 * This function configures the drive strength for various KSZ9477 chip variants 4428 * based on the provided properties. It handles chip-specific nuances and 4429 * ensures only valid drive strengths are written to the respective chip. 4430 * 4431 * Return: 0 on successful configuration, a negative error code on failure. 4432 */ 4433 static int ksz9477_drive_strength_write(struct ksz_device *dev, 4434 struct ksz_driver_strength_prop *props, 4435 int num_props) 4436 { 4437 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths); 4438 int i, ret, reg; 4439 u8 mask = 0; 4440 u8 val = 0; 4441 4442 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1) 4443 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4444 props[KSZ_DRIVER_STRENGTH_IO].name); 4445 4446 if (dev->chip_id == KSZ8795_CHIP_ID || 4447 dev->chip_id == KSZ8794_CHIP_ID || 4448 dev->chip_id == KSZ8765_CHIP_ID) 4449 reg = KSZ8795_REG_SW_CTRL_20; 4450 else 4451 reg = KSZ9477_REG_SW_IO_STRENGTH; 4452 4453 for (i = 0; i < num_props; i++) { 4454 if (props[i].value == -1) 4455 continue; 4456 4457 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths, 4458 array_size, props[i].value); 4459 if (ret < 0) { 4460 ksz_drive_strength_error(dev, ksz9477_drive_strengths, 4461 array_size, props[i].value); 4462 return ret; 4463 } 4464 4465 mask |= SW_DRIVE_STRENGTH_M << props[i].offset; 4466 val |= ret << props[i].offset; 4467 } 4468 4469 return ksz_rmw8(dev, reg, mask, val); 4470 } 4471 4472 /** 4473 * ksz8830_drive_strength_write() - Set the drive strength configuration for 4474 * KSZ8830 compatible chip variants. 4475 * @dev: ksz device 4476 * @props: Array of drive strength properties to be set 4477 * @num_props: Number of properties in the array 4478 * 4479 * This function applies the specified drive strength settings to KSZ8830 chip 4480 * variants (KSZ8873, KSZ8863). 4481 * It ensures the configurations align with what the chip variant supports and 4482 * warns or errors out on unsupported settings. 4483 * 4484 * Return: 0 on success, error code otherwise 4485 */ 4486 static int ksz8830_drive_strength_write(struct ksz_device *dev, 4487 struct ksz_driver_strength_prop *props, 4488 int num_props) 4489 { 4490 size_t array_size = ARRAY_SIZE(ksz8830_drive_strengths); 4491 int microamp; 4492 int i, ret; 4493 4494 for (i = 0; i < num_props; i++) { 4495 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO) 4496 continue; 4497 4498 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4499 props[i].name); 4500 } 4501 4502 microamp = props[KSZ_DRIVER_STRENGTH_IO].value; 4503 ret = ksz_drive_strength_to_reg(ksz8830_drive_strengths, array_size, 4504 microamp); 4505 if (ret < 0) { 4506 ksz_drive_strength_error(dev, ksz8830_drive_strengths, 4507 array_size, microamp); 4508 return ret; 4509 } 4510 4511 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12, 4512 KSZ8873_DRIVE_STRENGTH_16MA, ret); 4513 } 4514 4515 /** 4516 * ksz_parse_drive_strength() - Extract and apply drive strength configurations 4517 * from device tree properties. 4518 * @dev: ksz device 4519 * 4520 * This function reads the specified drive strength properties from the 4521 * device tree, validates against the supported chip variants, and sets 4522 * them accordingly. An error should be critical here, as the drive strength 4523 * settings are crucial for EMI compliance. 4524 * 4525 * Return: 0 on success, error code otherwise 4526 */ 4527 static int ksz_parse_drive_strength(struct ksz_device *dev) 4528 { 4529 struct ksz_driver_strength_prop of_props[] = { 4530 [KSZ_DRIVER_STRENGTH_HI] = { 4531 .name = "microchip,hi-drive-strength-microamp", 4532 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S, 4533 .value = -1, 4534 }, 4535 [KSZ_DRIVER_STRENGTH_LO] = { 4536 .name = "microchip,lo-drive-strength-microamp", 4537 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S, 4538 .value = -1, 4539 }, 4540 [KSZ_DRIVER_STRENGTH_IO] = { 4541 .name = "microchip,io-drive-strength-microamp", 4542 .offset = 0, /* don't care */ 4543 .value = -1, 4544 }, 4545 }; 4546 struct device_node *np = dev->dev->of_node; 4547 bool have_any_prop = false; 4548 int i, ret; 4549 4550 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4551 ret = of_property_read_u32(np, of_props[i].name, 4552 &of_props[i].value); 4553 if (ret && ret != -EINVAL) 4554 dev_warn(dev->dev, "Failed to read %s\n", 4555 of_props[i].name); 4556 if (ret) 4557 continue; 4558 4559 have_any_prop = true; 4560 } 4561 4562 if (!have_any_prop) 4563 return 0; 4564 4565 switch (dev->chip_id) { 4566 case KSZ8830_CHIP_ID: 4567 return ksz8830_drive_strength_write(dev, of_props, 4568 ARRAY_SIZE(of_props)); 4569 case KSZ8795_CHIP_ID: 4570 case KSZ8794_CHIP_ID: 4571 case KSZ8765_CHIP_ID: 4572 case KSZ8563_CHIP_ID: 4573 case KSZ8567_CHIP_ID: 4574 case KSZ9477_CHIP_ID: 4575 case KSZ9563_CHIP_ID: 4576 case KSZ9567_CHIP_ID: 4577 case KSZ9893_CHIP_ID: 4578 case KSZ9896_CHIP_ID: 4579 case KSZ9897_CHIP_ID: 4580 return ksz9477_drive_strength_write(dev, of_props, 4581 ARRAY_SIZE(of_props)); 4582 default: 4583 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4584 if (of_props[i].value == -1) 4585 continue; 4586 4587 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4588 of_props[i].name); 4589 } 4590 } 4591 4592 return 0; 4593 } 4594 4595 int ksz_switch_register(struct ksz_device *dev) 4596 { 4597 const struct ksz_chip_data *info; 4598 struct device_node *port, *ports; 4599 phy_interface_t interface; 4600 unsigned int port_num; 4601 int ret; 4602 int i; 4603 4604 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 4605 GPIOD_OUT_LOW); 4606 if (IS_ERR(dev->reset_gpio)) 4607 return PTR_ERR(dev->reset_gpio); 4608 4609 if (dev->reset_gpio) { 4610 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4611 usleep_range(10000, 12000); 4612 gpiod_set_value_cansleep(dev->reset_gpio, 0); 4613 msleep(100); 4614 } 4615 4616 mutex_init(&dev->dev_mutex); 4617 mutex_init(&dev->regmap_mutex); 4618 mutex_init(&dev->alu_mutex); 4619 mutex_init(&dev->vlan_mutex); 4620 4621 ret = ksz_switch_detect(dev); 4622 if (ret) 4623 return ret; 4624 4625 info = ksz_lookup_info(dev->chip_id); 4626 if (!info) 4627 return -ENODEV; 4628 4629 /* Update the compatible info with the probed one */ 4630 dev->info = info; 4631 4632 dev_info(dev->dev, "found switch: %s, rev %i\n", 4633 dev->info->dev_name, dev->chip_rev); 4634 4635 ret = ksz_check_device_id(dev); 4636 if (ret) 4637 return ret; 4638 4639 dev->dev_ops = dev->info->ops; 4640 4641 ret = dev->dev_ops->init(dev); 4642 if (ret) 4643 return ret; 4644 4645 dev->ports = devm_kzalloc(dev->dev, 4646 dev->info->port_cnt * sizeof(struct ksz_port), 4647 GFP_KERNEL); 4648 if (!dev->ports) 4649 return -ENOMEM; 4650 4651 for (i = 0; i < dev->info->port_cnt; i++) { 4652 spin_lock_init(&dev->ports[i].mib.stats64_lock); 4653 mutex_init(&dev->ports[i].mib.cnt_mutex); 4654 dev->ports[i].mib.counters = 4655 devm_kzalloc(dev->dev, 4656 sizeof(u64) * (dev->info->mib_cnt + 1), 4657 GFP_KERNEL); 4658 if (!dev->ports[i].mib.counters) 4659 return -ENOMEM; 4660 4661 dev->ports[i].ksz_dev = dev; 4662 dev->ports[i].num = i; 4663 } 4664 4665 /* set the real number of ports */ 4666 dev->ds->num_ports = dev->info->port_cnt; 4667 4668 /* set the phylink ops */ 4669 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops; 4670 4671 /* Host port interface will be self detected, or specifically set in 4672 * device tree. 4673 */ 4674 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 4675 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 4676 if (dev->dev->of_node) { 4677 ret = of_get_phy_mode(dev->dev->of_node, &interface); 4678 if (ret == 0) 4679 dev->compat_interface = interface; 4680 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 4681 if (!ports) 4682 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 4683 if (ports) { 4684 for_each_available_child_of_node(ports, port) { 4685 if (of_property_read_u32(port, "reg", 4686 &port_num)) 4687 continue; 4688 if (!(dev->port_mask & BIT(port_num))) { 4689 of_node_put(port); 4690 of_node_put(ports); 4691 return -EINVAL; 4692 } 4693 of_get_phy_mode(port, 4694 &dev->ports[port_num].interface); 4695 4696 ksz_parse_rgmii_delay(dev, port_num, port); 4697 } 4698 of_node_put(ports); 4699 } 4700 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 4701 "microchip,synclko-125"); 4702 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 4703 "microchip,synclko-disable"); 4704 if (dev->synclko_125 && dev->synclko_disable) { 4705 dev_err(dev->dev, "inconsistent synclko settings\n"); 4706 return -EINVAL; 4707 } 4708 4709 dev->wakeup_source = of_property_read_bool(dev->dev->of_node, 4710 "wakeup-source"); 4711 dev->pme_active_high = of_property_read_bool(dev->dev->of_node, 4712 "microchip,pme-active-high"); 4713 } 4714 4715 ret = dsa_register_switch(dev->ds); 4716 if (ret) { 4717 dev->dev_ops->exit(dev); 4718 return ret; 4719 } 4720 4721 /* Read MIB counters every 30 seconds to avoid overflow. */ 4722 dev->mib_read_interval = msecs_to_jiffies(5000); 4723 4724 /* Start the MIB timer. */ 4725 schedule_delayed_work(&dev->mib_read, 0); 4726 4727 return ret; 4728 } 4729 EXPORT_SYMBOL(ksz_switch_register); 4730 4731 void ksz_switch_remove(struct ksz_device *dev) 4732 { 4733 /* timer started */ 4734 if (dev->mib_read_interval) { 4735 dev->mib_read_interval = 0; 4736 cancel_delayed_work_sync(&dev->mib_read); 4737 } 4738 4739 dev->dev_ops->exit(dev); 4740 dsa_unregister_switch(dev->ds); 4741 4742 if (dev->reset_gpio) 4743 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4744 4745 } 4746 EXPORT_SYMBOL(ksz_switch_remove); 4747 4748 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 4749 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 4750 MODULE_LICENSE("GPL"); 4751