1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2025 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/of.h> 22 #include <linux/of_mdio.h> 23 #include <linux/of_net.h> 24 #include <linux/micrel_phy.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <net/dsa.h> 27 #include <net/ieee8021q.h> 28 #include <net/pkt_cls.h> 29 #include <net/switchdev.h> 30 31 #include "ksz_common.h" 32 #include "ksz_dcb.h" 33 #include "ksz_ptp.h" 34 #include "ksz8.h" 35 #include "ksz9477.h" 36 #include "lan937x.h" 37 38 #define MIB_COUNTER_NUM 0x20 39 40 struct ksz_stats_raw { 41 u64 rx_hi; 42 u64 rx_undersize; 43 u64 rx_fragments; 44 u64 rx_oversize; 45 u64 rx_jabbers; 46 u64 rx_symbol_err; 47 u64 rx_crc_err; 48 u64 rx_align_err; 49 u64 rx_mac_ctrl; 50 u64 rx_pause; 51 u64 rx_bcast; 52 u64 rx_mcast; 53 u64 rx_ucast; 54 u64 rx_64_or_less; 55 u64 rx_65_127; 56 u64 rx_128_255; 57 u64 rx_256_511; 58 u64 rx_512_1023; 59 u64 rx_1024_1522; 60 u64 rx_1523_2000; 61 u64 rx_2001; 62 u64 tx_hi; 63 u64 tx_late_col; 64 u64 tx_pause; 65 u64 tx_bcast; 66 u64 tx_mcast; 67 u64 tx_ucast; 68 u64 tx_deferred; 69 u64 tx_total_col; 70 u64 tx_exc_col; 71 u64 tx_single_col; 72 u64 tx_mult_col; 73 u64 rx_total; 74 u64 tx_total; 75 u64 rx_discards; 76 u64 tx_discards; 77 }; 78 79 struct ksz88xx_stats_raw { 80 u64 rx; 81 u64 rx_hi; 82 u64 rx_undersize; 83 u64 rx_fragments; 84 u64 rx_oversize; 85 u64 rx_jabbers; 86 u64 rx_symbol_err; 87 u64 rx_crc_err; 88 u64 rx_align_err; 89 u64 rx_mac_ctrl; 90 u64 rx_pause; 91 u64 rx_bcast; 92 u64 rx_mcast; 93 u64 rx_ucast; 94 u64 rx_64_or_less; 95 u64 rx_65_127; 96 u64 rx_128_255; 97 u64 rx_256_511; 98 u64 rx_512_1023; 99 u64 rx_1024_1522; 100 u64 tx; 101 u64 tx_hi; 102 u64 tx_late_col; 103 u64 tx_pause; 104 u64 tx_bcast; 105 u64 tx_mcast; 106 u64 tx_ucast; 107 u64 tx_deferred; 108 u64 tx_total_col; 109 u64 tx_exc_col; 110 u64 tx_single_col; 111 u64 tx_mult_col; 112 u64 rx_discards; 113 u64 tx_discards; 114 }; 115 116 static const struct ksz_mib_names ksz88xx_mib_names[] = { 117 { 0x00, "rx" }, 118 { 0x01, "rx_hi" }, 119 { 0x02, "rx_undersize" }, 120 { 0x03, "rx_fragments" }, 121 { 0x04, "rx_oversize" }, 122 { 0x05, "rx_jabbers" }, 123 { 0x06, "rx_symbol_err" }, 124 { 0x07, "rx_crc_err" }, 125 { 0x08, "rx_align_err" }, 126 { 0x09, "rx_mac_ctrl" }, 127 { 0x0a, "rx_pause" }, 128 { 0x0b, "rx_bcast" }, 129 { 0x0c, "rx_mcast" }, 130 { 0x0d, "rx_ucast" }, 131 { 0x0e, "rx_64_or_less" }, 132 { 0x0f, "rx_65_127" }, 133 { 0x10, "rx_128_255" }, 134 { 0x11, "rx_256_511" }, 135 { 0x12, "rx_512_1023" }, 136 { 0x13, "rx_1024_1522" }, 137 { 0x14, "tx" }, 138 { 0x15, "tx_hi" }, 139 { 0x16, "tx_late_col" }, 140 { 0x17, "tx_pause" }, 141 { 0x18, "tx_bcast" }, 142 { 0x19, "tx_mcast" }, 143 { 0x1a, "tx_ucast" }, 144 { 0x1b, "tx_deferred" }, 145 { 0x1c, "tx_total_col" }, 146 { 0x1d, "tx_exc_col" }, 147 { 0x1e, "tx_single_col" }, 148 { 0x1f, "tx_mult_col" }, 149 { 0x100, "rx_discards" }, 150 { 0x101, "tx_discards" }, 151 }; 152 153 static const struct ksz_mib_names ksz9477_mib_names[] = { 154 { 0x00, "rx_hi" }, 155 { 0x01, "rx_undersize" }, 156 { 0x02, "rx_fragments" }, 157 { 0x03, "rx_oversize" }, 158 { 0x04, "rx_jabbers" }, 159 { 0x05, "rx_symbol_err" }, 160 { 0x06, "rx_crc_err" }, 161 { 0x07, "rx_align_err" }, 162 { 0x08, "rx_mac_ctrl" }, 163 { 0x09, "rx_pause" }, 164 { 0x0A, "rx_bcast" }, 165 { 0x0B, "rx_mcast" }, 166 { 0x0C, "rx_ucast" }, 167 { 0x0D, "rx_64_or_less" }, 168 { 0x0E, "rx_65_127" }, 169 { 0x0F, "rx_128_255" }, 170 { 0x10, "rx_256_511" }, 171 { 0x11, "rx_512_1023" }, 172 { 0x12, "rx_1024_1522" }, 173 { 0x13, "rx_1523_2000" }, 174 { 0x14, "rx_2001" }, 175 { 0x15, "tx_hi" }, 176 { 0x16, "tx_late_col" }, 177 { 0x17, "tx_pause" }, 178 { 0x18, "tx_bcast" }, 179 { 0x19, "tx_mcast" }, 180 { 0x1A, "tx_ucast" }, 181 { 0x1B, "tx_deferred" }, 182 { 0x1C, "tx_total_col" }, 183 { 0x1D, "tx_exc_col" }, 184 { 0x1E, "tx_single_col" }, 185 { 0x1F, "tx_mult_col" }, 186 { 0x80, "rx_total" }, 187 { 0x81, "tx_total" }, 188 { 0x82, "rx_discards" }, 189 { 0x83, "tx_discards" }, 190 }; 191 192 struct ksz_driver_strength_prop { 193 const char *name; 194 int offset; 195 int value; 196 }; 197 198 enum ksz_driver_strength_type { 199 KSZ_DRIVER_STRENGTH_HI, 200 KSZ_DRIVER_STRENGTH_LO, 201 KSZ_DRIVER_STRENGTH_IO, 202 }; 203 204 /** 205 * struct ksz_drive_strength - drive strength mapping 206 * @reg_val: register value 207 * @microamp: microamp value 208 */ 209 struct ksz_drive_strength { 210 u32 reg_val; 211 u32 microamp; 212 }; 213 214 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants 215 * 216 * This values are not documented in KSZ9477 variants but confirmed by 217 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893 218 * and KSZ8563 are using same register (drive strength) settings like KSZ8795. 219 * 220 * Documentation in KSZ8795CLX provides more information with some 221 * recommendations: 222 * - for high speed signals 223 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using 224 * 2.5V or 3.3V VDDIO. 225 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with 226 * using 1.8V VDDIO. 227 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V 228 * or 3.3V VDDIO. 229 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO. 230 * 5. In same interface, the heavy loading should use higher one of the 231 * drive current strength. 232 * - for low speed signals 233 * 1. 3.3V VDDIO, use either 4 mA or 8 mA. 234 * 2. 2.5V VDDIO, use either 8 mA or 12 mA. 235 * 3. 1.8V VDDIO, use either 12 mA or 16 mA. 236 * 4. If it is heavy loading, can use higher drive current strength. 237 */ 238 static const struct ksz_drive_strength ksz9477_drive_strengths[] = { 239 { SW_DRIVE_STRENGTH_2MA, 2000 }, 240 { SW_DRIVE_STRENGTH_4MA, 4000 }, 241 { SW_DRIVE_STRENGTH_8MA, 8000 }, 242 { SW_DRIVE_STRENGTH_12MA, 12000 }, 243 { SW_DRIVE_STRENGTH_16MA, 16000 }, 244 { SW_DRIVE_STRENGTH_20MA, 20000 }, 245 { SW_DRIVE_STRENGTH_24MA, 24000 }, 246 { SW_DRIVE_STRENGTH_28MA, 28000 }, 247 }; 248 249 /* ksz88x3_drive_strengths - Drive strength mapping for KSZ8863, KSZ8873, .. 250 * variants. 251 * This values are documented in KSZ8873 and KSZ8863 datasheets. 252 */ 253 static const struct ksz_drive_strength ksz88x3_drive_strengths[] = { 254 { 0, 8000 }, 255 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 }, 256 }; 257 258 /** 259 * ksz_phylink_mac_disable_tx_lpi() - Callback to signal LPI support (Dummy) 260 * @config: phylink config structure 261 * 262 * This function is a dummy handler. See ksz_phylink_mac_enable_tx_lpi() for 263 * a detailed explanation of EEE/LPI handling in KSZ switches. 264 */ 265 void ksz_phylink_mac_disable_tx_lpi(struct phylink_config *config) 266 { 267 } 268 269 /** 270 * ksz_phylink_mac_enable_tx_lpi() - Callback to signal LPI support (Dummy) 271 * @config: phylink config structure 272 * @timer: timer value before entering LPI (unused) 273 * @tx_clock_stop: whether to stop the TX clock in LPI mode (unused) 274 * 275 * This function signals to phylink that the driver architecture supports 276 * LPI management, enabling phylink to control EEE advertisement during 277 * negotiation according to IEEE Std 802.3 (Clause 78). 278 * 279 * Hardware Management of EEE/LPI State: 280 * For KSZ switch ports with integrated PHYs (e.g., KSZ9893R ports 1-2), 281 * observation and testing suggest that the actual EEE / Low Power Idle (LPI) 282 * state transitions are managed autonomously by the hardware based on 283 * the auto-negotiation results. (Note: While the datasheet describes EEE 284 * operation based on negotiation, it doesn't explicitly detail the internal 285 * MAC/PHY interaction, so autonomous hardware management of the MAC state 286 * for LPI is inferred from observed behavior). 287 * This hardware control, consistent with the switch's ability to operate 288 * autonomously via strapping, means MAC-level software intervention is not 289 * required or exposed for managing the LPI state once EEE is negotiated. 290 * (Ref: KSZ9893R Data Sheet DS00002420D, primarily Section 4.7.5 explaining 291 * EEE, also Sections 4.1.7 on Auto-Negotiation and 3.2.1 on Configuration 292 * Straps). 293 * 294 * Additionally, ports configured as MAC interfaces (e.g., KSZ9893R port 3) 295 * lack documented MAC-level LPI control. 296 * 297 * Therefore, this callback performs no action and serves primarily to inform 298 * phylink of LPI awareness and to document the inferred hardware behavior. 299 * 300 * Returns: 0 (Always success) 301 */ 302 int ksz_phylink_mac_enable_tx_lpi(struct phylink_config *config, 303 u32 timer, bool tx_clock_stop) 304 { 305 return 0; 306 } 307 308 static const u16 ksz8463_regs[] = { 309 [REG_SW_MAC_ADDR] = 0x10, 310 [REG_IND_CTRL_0] = 0x30, 311 [REG_IND_DATA_8] = 0x26, 312 [REG_IND_DATA_CHECK] = 0x26, 313 [REG_IND_DATA_HI] = 0x28, 314 [REG_IND_DATA_LO] = 0x2C, 315 [REG_IND_MIB_CHECK] = 0x2F, 316 [P_FORCE_CTRL] = 0x0C, 317 [P_LINK_STATUS] = 0x0E, 318 [P_LOCAL_CTRL] = 0x0C, 319 [P_NEG_RESTART_CTRL] = 0x0D, 320 [P_REMOTE_STATUS] = 0x0E, 321 [P_SPEED_STATUS] = 0x0F, 322 [S_TAIL_TAG_CTRL] = 0xAD, 323 [P_STP_CTRL] = 0x6F, 324 [S_START_CTRL] = 0x01, 325 [S_BROADCAST_CTRL] = 0x06, 326 [S_MULTICAST_CTRL] = 0x04, 327 [PTP_CLK_CTRL] = 0x0600, 328 [PTP_RTC_NANOSEC] = 0x0604, 329 [PTP_RTC_SEC] = 0x0608, 330 [PTP_RTC_SUB_NANOSEC] = 0x060C, 331 [PTP_SUBNANOSEC_RATE] = 0x0610, 332 [PTP_MSG_CONF1] = 0x0620, 333 }; 334 335 static const u32 ksz8463_masks[] = { 336 [PORT_802_1P_REMAPPING] = BIT(3), 337 [SW_TAIL_TAG_ENABLE] = BIT(0), 338 [MIB_COUNTER_OVERFLOW] = BIT(7), 339 [MIB_COUNTER_VALID] = BIT(6), 340 [VLAN_TABLE_FID] = GENMASK(15, 12), 341 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 342 [VLAN_TABLE_VALID] = BIT(19), 343 [STATIC_MAC_TABLE_VALID] = BIT(19), 344 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 345 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 346 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 347 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 348 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 349 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 350 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 351 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 352 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 353 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 354 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 355 }; 356 357 static u8 ksz8463_shifts[] = { 358 [VLAN_TABLE_MEMBERSHIP_S] = 16, 359 [STATIC_MAC_FWD_PORTS] = 16, 360 [STATIC_MAC_FID] = 22, 361 [DYNAMIC_MAC_ENTRIES_H] = 8, 362 [DYNAMIC_MAC_ENTRIES] = 24, 363 [DYNAMIC_MAC_FID] = 16, 364 [DYNAMIC_MAC_TIMESTAMP] = 22, 365 [DYNAMIC_MAC_SRC_PORT] = 20, 366 }; 367 368 static const u16 ksz8795_regs[] = { 369 [REG_SW_MAC_ADDR] = 0x68, 370 [REG_IND_CTRL_0] = 0x6E, 371 [REG_IND_DATA_8] = 0x70, 372 [REG_IND_DATA_CHECK] = 0x72, 373 [REG_IND_DATA_HI] = 0x71, 374 [REG_IND_DATA_LO] = 0x75, 375 [REG_IND_MIB_CHECK] = 0x74, 376 [REG_IND_BYTE] = 0xA0, 377 [P_FORCE_CTRL] = 0x0C, 378 [P_LINK_STATUS] = 0x0E, 379 [P_LOCAL_CTRL] = 0x07, 380 [P_NEG_RESTART_CTRL] = 0x0D, 381 [P_REMOTE_STATUS] = 0x08, 382 [P_SPEED_STATUS] = 0x09, 383 [S_TAIL_TAG_CTRL] = 0x0C, 384 [P_STP_CTRL] = 0x02, 385 [S_START_CTRL] = 0x01, 386 [S_BROADCAST_CTRL] = 0x06, 387 [S_MULTICAST_CTRL] = 0x04, 388 [P_XMII_CTRL_0] = 0x06, 389 [P_XMII_CTRL_1] = 0x06, 390 [REG_SW_PME_CTRL] = 0x8003, 391 [REG_PORT_PME_STATUS] = 0x8003, 392 [REG_PORT_PME_CTRL] = 0x8007, 393 }; 394 395 static const u32 ksz8795_masks[] = { 396 [PORT_802_1P_REMAPPING] = BIT(7), 397 [SW_TAIL_TAG_ENABLE] = BIT(1), 398 [MIB_COUNTER_OVERFLOW] = BIT(6), 399 [MIB_COUNTER_VALID] = BIT(5), 400 [VLAN_TABLE_FID] = GENMASK(6, 0), 401 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 402 [VLAN_TABLE_VALID] = BIT(12), 403 [STATIC_MAC_TABLE_VALID] = BIT(21), 404 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 405 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 406 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 407 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 408 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 409 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 410 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 411 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 412 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 413 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 414 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 415 [P_MII_TX_FLOW_CTRL] = BIT(5), 416 [P_MII_RX_FLOW_CTRL] = BIT(5), 417 }; 418 419 static const u8 ksz8795_xmii_ctrl0[] = { 420 [P_MII_100MBIT] = 0, 421 [P_MII_10MBIT] = 1, 422 [P_MII_FULL_DUPLEX] = 0, 423 [P_MII_HALF_DUPLEX] = 1, 424 }; 425 426 static const u8 ksz8795_xmii_ctrl1[] = { 427 [P_RGMII_SEL] = 3, 428 [P_GMII_SEL] = 2, 429 [P_RMII_SEL] = 1, 430 [P_MII_SEL] = 0, 431 [P_GMII_1GBIT] = 1, 432 [P_GMII_NOT_1GBIT] = 0, 433 }; 434 435 static const u8 ksz8795_shifts[] = { 436 [VLAN_TABLE_MEMBERSHIP_S] = 7, 437 [VLAN_TABLE] = 16, 438 [STATIC_MAC_FWD_PORTS] = 16, 439 [STATIC_MAC_FID] = 24, 440 [DYNAMIC_MAC_ENTRIES_H] = 3, 441 [DYNAMIC_MAC_ENTRIES] = 29, 442 [DYNAMIC_MAC_FID] = 16, 443 [DYNAMIC_MAC_TIMESTAMP] = 27, 444 [DYNAMIC_MAC_SRC_PORT] = 24, 445 }; 446 447 static const u16 ksz8863_regs[] = { 448 [REG_SW_MAC_ADDR] = 0x70, 449 [REG_IND_CTRL_0] = 0x79, 450 [REG_IND_DATA_8] = 0x7B, 451 [REG_IND_DATA_CHECK] = 0x7B, 452 [REG_IND_DATA_HI] = 0x7C, 453 [REG_IND_DATA_LO] = 0x80, 454 [REG_IND_MIB_CHECK] = 0x80, 455 [P_FORCE_CTRL] = 0x0C, 456 [P_LINK_STATUS] = 0x0E, 457 [P_LOCAL_CTRL] = 0x0C, 458 [P_NEG_RESTART_CTRL] = 0x0D, 459 [P_REMOTE_STATUS] = 0x0E, 460 [P_SPEED_STATUS] = 0x0F, 461 [S_TAIL_TAG_CTRL] = 0x03, 462 [P_STP_CTRL] = 0x02, 463 [S_START_CTRL] = 0x01, 464 [S_BROADCAST_CTRL] = 0x06, 465 [S_MULTICAST_CTRL] = 0x04, 466 }; 467 468 static const u32 ksz8863_masks[] = { 469 [PORT_802_1P_REMAPPING] = BIT(3), 470 [SW_TAIL_TAG_ENABLE] = BIT(6), 471 [MIB_COUNTER_OVERFLOW] = BIT(7), 472 [MIB_COUNTER_VALID] = BIT(6), 473 [VLAN_TABLE_FID] = GENMASK(15, 12), 474 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 475 [VLAN_TABLE_VALID] = BIT(19), 476 [STATIC_MAC_TABLE_VALID] = BIT(19), 477 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 478 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 479 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 480 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 481 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 482 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 483 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 484 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 485 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 486 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 487 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 488 }; 489 490 static u8 ksz8863_shifts[] = { 491 [VLAN_TABLE_MEMBERSHIP_S] = 16, 492 [STATIC_MAC_FWD_PORTS] = 16, 493 [STATIC_MAC_FID] = 22, 494 [DYNAMIC_MAC_ENTRIES_H] = 8, 495 [DYNAMIC_MAC_ENTRIES] = 24, 496 [DYNAMIC_MAC_FID] = 16, 497 [DYNAMIC_MAC_TIMESTAMP] = 22, 498 [DYNAMIC_MAC_SRC_PORT] = 20, 499 }; 500 501 static const u16 ksz8895_regs[] = { 502 [REG_SW_MAC_ADDR] = 0x68, 503 [REG_IND_CTRL_0] = 0x6E, 504 [REG_IND_DATA_8] = 0x70, 505 [REG_IND_DATA_CHECK] = 0x72, 506 [REG_IND_DATA_HI] = 0x71, 507 [REG_IND_DATA_LO] = 0x75, 508 [REG_IND_MIB_CHECK] = 0x75, 509 [P_FORCE_CTRL] = 0x0C, 510 [P_LINK_STATUS] = 0x0E, 511 [P_LOCAL_CTRL] = 0x0C, 512 [P_NEG_RESTART_CTRL] = 0x0D, 513 [P_REMOTE_STATUS] = 0x0E, 514 [P_SPEED_STATUS] = 0x09, 515 [S_TAIL_TAG_CTRL] = 0x0C, 516 [P_STP_CTRL] = 0x02, 517 [S_START_CTRL] = 0x01, 518 [S_BROADCAST_CTRL] = 0x06, 519 [S_MULTICAST_CTRL] = 0x04, 520 }; 521 522 static const u32 ksz8895_masks[] = { 523 [PORT_802_1P_REMAPPING] = BIT(7), 524 [SW_TAIL_TAG_ENABLE] = BIT(1), 525 [MIB_COUNTER_OVERFLOW] = BIT(7), 526 [MIB_COUNTER_VALID] = BIT(6), 527 [VLAN_TABLE_FID] = GENMASK(6, 0), 528 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 529 [VLAN_TABLE_VALID] = BIT(12), 530 [STATIC_MAC_TABLE_VALID] = BIT(21), 531 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 532 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 533 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 534 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 535 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 536 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 537 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 538 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 539 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 540 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 541 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 542 }; 543 544 static const u8 ksz8895_shifts[] = { 545 [VLAN_TABLE_MEMBERSHIP_S] = 7, 546 [VLAN_TABLE] = 13, 547 [STATIC_MAC_FWD_PORTS] = 16, 548 [STATIC_MAC_FID] = 24, 549 [DYNAMIC_MAC_ENTRIES_H] = 3, 550 [DYNAMIC_MAC_ENTRIES] = 29, 551 [DYNAMIC_MAC_FID] = 16, 552 [DYNAMIC_MAC_TIMESTAMP] = 27, 553 [DYNAMIC_MAC_SRC_PORT] = 24, 554 }; 555 556 static const u16 ksz9477_regs[] = { 557 [REG_SW_MAC_ADDR] = 0x0302, 558 [P_STP_CTRL] = 0x0B04, 559 [S_START_CTRL] = 0x0300, 560 [S_BROADCAST_CTRL] = 0x0332, 561 [S_MULTICAST_CTRL] = 0x0331, 562 [P_XMII_CTRL_0] = 0x0300, 563 [P_XMII_CTRL_1] = 0x0301, 564 [REG_SW_PME_CTRL] = 0x0006, 565 [REG_PORT_PME_STATUS] = 0x0013, 566 [REG_PORT_PME_CTRL] = 0x0017, 567 [PTP_CLK_CTRL] = 0x0500, 568 [PTP_RTC_SUB_NANOSEC] = 0x0502, 569 [PTP_RTC_NANOSEC] = 0x0504, 570 [PTP_RTC_SEC] = 0x0508, 571 [PTP_SUBNANOSEC_RATE] = 0x050C, 572 [PTP_MSG_CONF1] = 0x0514, 573 }; 574 575 static const u32 ksz9477_masks[] = { 576 [ALU_STAT_WRITE] = 0, 577 [ALU_STAT_READ] = 1, 578 [ALU_STAT_DIRECT] = 0, 579 [ALU_RESV_MCAST_ADDR] = BIT(1), 580 [P_MII_TX_FLOW_CTRL] = BIT(5), 581 [P_MII_RX_FLOW_CTRL] = BIT(3), 582 }; 583 584 static const u8 ksz9477_shifts[] = { 585 [ALU_STAT_INDEX] = 16, 586 }; 587 588 static const u8 ksz9477_xmii_ctrl0[] = { 589 [P_MII_100MBIT] = 1, 590 [P_MII_10MBIT] = 0, 591 [P_MII_FULL_DUPLEX] = 1, 592 [P_MII_HALF_DUPLEX] = 0, 593 }; 594 595 static const u8 ksz9477_xmii_ctrl1[] = { 596 [P_RGMII_SEL] = 0, 597 [P_RMII_SEL] = 1, 598 [P_GMII_SEL] = 2, 599 [P_MII_SEL] = 3, 600 [P_GMII_1GBIT] = 0, 601 [P_GMII_NOT_1GBIT] = 1, 602 }; 603 604 static const u32 lan937x_masks[] = { 605 [ALU_STAT_WRITE] = 1, 606 [ALU_STAT_READ] = 2, 607 [ALU_STAT_DIRECT] = BIT(3), 608 [ALU_RESV_MCAST_ADDR] = BIT(2), 609 [P_MII_TX_FLOW_CTRL] = BIT(5), 610 [P_MII_RX_FLOW_CTRL] = BIT(3), 611 }; 612 613 static const u8 lan937x_shifts[] = { 614 [ALU_STAT_INDEX] = 8, 615 }; 616 617 static const struct regmap_range ksz8563_valid_regs[] = { 618 regmap_reg_range(0x0000, 0x0003), 619 regmap_reg_range(0x0006, 0x0006), 620 regmap_reg_range(0x000f, 0x001f), 621 regmap_reg_range(0x0100, 0x0100), 622 regmap_reg_range(0x0104, 0x0107), 623 regmap_reg_range(0x010d, 0x010d), 624 regmap_reg_range(0x0110, 0x0113), 625 regmap_reg_range(0x0120, 0x012b), 626 regmap_reg_range(0x0201, 0x0201), 627 regmap_reg_range(0x0210, 0x0213), 628 regmap_reg_range(0x0300, 0x0300), 629 regmap_reg_range(0x0302, 0x031b), 630 regmap_reg_range(0x0320, 0x032b), 631 regmap_reg_range(0x0330, 0x0336), 632 regmap_reg_range(0x0338, 0x033e), 633 regmap_reg_range(0x0340, 0x035f), 634 regmap_reg_range(0x0370, 0x0370), 635 regmap_reg_range(0x0378, 0x0378), 636 regmap_reg_range(0x037c, 0x037d), 637 regmap_reg_range(0x0390, 0x0393), 638 regmap_reg_range(0x0400, 0x040e), 639 regmap_reg_range(0x0410, 0x042f), 640 regmap_reg_range(0x0500, 0x0519), 641 regmap_reg_range(0x0520, 0x054b), 642 regmap_reg_range(0x0550, 0x05b3), 643 644 /* port 1 */ 645 regmap_reg_range(0x1000, 0x1001), 646 regmap_reg_range(0x1004, 0x100b), 647 regmap_reg_range(0x1013, 0x1013), 648 regmap_reg_range(0x1017, 0x1017), 649 regmap_reg_range(0x101b, 0x101b), 650 regmap_reg_range(0x101f, 0x1021), 651 regmap_reg_range(0x1030, 0x1030), 652 regmap_reg_range(0x1100, 0x1111), 653 regmap_reg_range(0x111a, 0x111d), 654 regmap_reg_range(0x1122, 0x1127), 655 regmap_reg_range(0x112a, 0x112b), 656 regmap_reg_range(0x1136, 0x1139), 657 regmap_reg_range(0x113e, 0x113f), 658 regmap_reg_range(0x1400, 0x1401), 659 regmap_reg_range(0x1403, 0x1403), 660 regmap_reg_range(0x1410, 0x1417), 661 regmap_reg_range(0x1420, 0x1423), 662 regmap_reg_range(0x1500, 0x1507), 663 regmap_reg_range(0x1600, 0x1612), 664 regmap_reg_range(0x1800, 0x180f), 665 regmap_reg_range(0x1900, 0x1907), 666 regmap_reg_range(0x1914, 0x191b), 667 regmap_reg_range(0x1a00, 0x1a03), 668 regmap_reg_range(0x1a04, 0x1a08), 669 regmap_reg_range(0x1b00, 0x1b01), 670 regmap_reg_range(0x1b04, 0x1b04), 671 regmap_reg_range(0x1c00, 0x1c05), 672 regmap_reg_range(0x1c08, 0x1c1b), 673 674 /* port 2 */ 675 regmap_reg_range(0x2000, 0x2001), 676 regmap_reg_range(0x2004, 0x200b), 677 regmap_reg_range(0x2013, 0x2013), 678 regmap_reg_range(0x2017, 0x2017), 679 regmap_reg_range(0x201b, 0x201b), 680 regmap_reg_range(0x201f, 0x2021), 681 regmap_reg_range(0x2030, 0x2030), 682 regmap_reg_range(0x2100, 0x2111), 683 regmap_reg_range(0x211a, 0x211d), 684 regmap_reg_range(0x2122, 0x2127), 685 regmap_reg_range(0x212a, 0x212b), 686 regmap_reg_range(0x2136, 0x2139), 687 regmap_reg_range(0x213e, 0x213f), 688 regmap_reg_range(0x2400, 0x2401), 689 regmap_reg_range(0x2403, 0x2403), 690 regmap_reg_range(0x2410, 0x2417), 691 regmap_reg_range(0x2420, 0x2423), 692 regmap_reg_range(0x2500, 0x2507), 693 regmap_reg_range(0x2600, 0x2612), 694 regmap_reg_range(0x2800, 0x280f), 695 regmap_reg_range(0x2900, 0x2907), 696 regmap_reg_range(0x2914, 0x291b), 697 regmap_reg_range(0x2a00, 0x2a03), 698 regmap_reg_range(0x2a04, 0x2a08), 699 regmap_reg_range(0x2b00, 0x2b01), 700 regmap_reg_range(0x2b04, 0x2b04), 701 regmap_reg_range(0x2c00, 0x2c05), 702 regmap_reg_range(0x2c08, 0x2c1b), 703 704 /* port 3 */ 705 regmap_reg_range(0x3000, 0x3001), 706 regmap_reg_range(0x3004, 0x300b), 707 regmap_reg_range(0x3013, 0x3013), 708 regmap_reg_range(0x3017, 0x3017), 709 regmap_reg_range(0x301b, 0x301b), 710 regmap_reg_range(0x301f, 0x3021), 711 regmap_reg_range(0x3030, 0x3030), 712 regmap_reg_range(0x3300, 0x3301), 713 regmap_reg_range(0x3303, 0x3303), 714 regmap_reg_range(0x3400, 0x3401), 715 regmap_reg_range(0x3403, 0x3403), 716 regmap_reg_range(0x3410, 0x3417), 717 regmap_reg_range(0x3420, 0x3423), 718 regmap_reg_range(0x3500, 0x3507), 719 regmap_reg_range(0x3600, 0x3612), 720 regmap_reg_range(0x3800, 0x380f), 721 regmap_reg_range(0x3900, 0x3907), 722 regmap_reg_range(0x3914, 0x391b), 723 regmap_reg_range(0x3a00, 0x3a03), 724 regmap_reg_range(0x3a04, 0x3a08), 725 regmap_reg_range(0x3b00, 0x3b01), 726 regmap_reg_range(0x3b04, 0x3b04), 727 regmap_reg_range(0x3c00, 0x3c05), 728 regmap_reg_range(0x3c08, 0x3c1b), 729 }; 730 731 static const struct regmap_access_table ksz8563_register_set = { 732 .yes_ranges = ksz8563_valid_regs, 733 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 734 }; 735 736 static const struct regmap_range ksz9477_valid_regs[] = { 737 regmap_reg_range(0x0000, 0x0003), 738 regmap_reg_range(0x0006, 0x0006), 739 regmap_reg_range(0x0010, 0x001f), 740 regmap_reg_range(0x0100, 0x0100), 741 regmap_reg_range(0x0103, 0x0107), 742 regmap_reg_range(0x010d, 0x010d), 743 regmap_reg_range(0x0110, 0x0113), 744 regmap_reg_range(0x0120, 0x012b), 745 regmap_reg_range(0x0201, 0x0201), 746 regmap_reg_range(0x0210, 0x0213), 747 regmap_reg_range(0x0300, 0x0300), 748 regmap_reg_range(0x0302, 0x031b), 749 regmap_reg_range(0x0320, 0x032b), 750 regmap_reg_range(0x0330, 0x0336), 751 regmap_reg_range(0x0338, 0x033b), 752 regmap_reg_range(0x033e, 0x033e), 753 regmap_reg_range(0x0340, 0x035f), 754 regmap_reg_range(0x0370, 0x0370), 755 regmap_reg_range(0x0378, 0x0378), 756 regmap_reg_range(0x037c, 0x037d), 757 regmap_reg_range(0x0390, 0x0393), 758 regmap_reg_range(0x0400, 0x040e), 759 regmap_reg_range(0x0410, 0x042f), 760 regmap_reg_range(0x0444, 0x044b), 761 regmap_reg_range(0x0450, 0x046f), 762 regmap_reg_range(0x0500, 0x0519), 763 regmap_reg_range(0x0520, 0x054b), 764 regmap_reg_range(0x0550, 0x05b3), 765 regmap_reg_range(0x0604, 0x060b), 766 regmap_reg_range(0x0610, 0x0612), 767 regmap_reg_range(0x0614, 0x062c), 768 regmap_reg_range(0x0640, 0x0645), 769 regmap_reg_range(0x0648, 0x064d), 770 771 /* port 1 */ 772 regmap_reg_range(0x1000, 0x1001), 773 regmap_reg_range(0x1013, 0x1013), 774 regmap_reg_range(0x1017, 0x1017), 775 regmap_reg_range(0x101b, 0x101b), 776 regmap_reg_range(0x101f, 0x1020), 777 regmap_reg_range(0x1030, 0x1030), 778 regmap_reg_range(0x1100, 0x1115), 779 regmap_reg_range(0x111a, 0x111f), 780 regmap_reg_range(0x1120, 0x112b), 781 regmap_reg_range(0x1134, 0x113b), 782 regmap_reg_range(0x113c, 0x113f), 783 regmap_reg_range(0x1400, 0x1401), 784 regmap_reg_range(0x1403, 0x1403), 785 regmap_reg_range(0x1410, 0x1417), 786 regmap_reg_range(0x1420, 0x1423), 787 regmap_reg_range(0x1500, 0x1507), 788 regmap_reg_range(0x1600, 0x1613), 789 regmap_reg_range(0x1800, 0x180f), 790 regmap_reg_range(0x1820, 0x1827), 791 regmap_reg_range(0x1830, 0x1837), 792 regmap_reg_range(0x1840, 0x184b), 793 regmap_reg_range(0x1900, 0x1907), 794 regmap_reg_range(0x1914, 0x191b), 795 regmap_reg_range(0x1920, 0x1920), 796 regmap_reg_range(0x1923, 0x1927), 797 regmap_reg_range(0x1a00, 0x1a03), 798 regmap_reg_range(0x1a04, 0x1a07), 799 regmap_reg_range(0x1b00, 0x1b01), 800 regmap_reg_range(0x1b04, 0x1b04), 801 regmap_reg_range(0x1c00, 0x1c05), 802 regmap_reg_range(0x1c08, 0x1c1b), 803 804 /* port 2 */ 805 regmap_reg_range(0x2000, 0x2001), 806 regmap_reg_range(0x2013, 0x2013), 807 regmap_reg_range(0x2017, 0x2017), 808 regmap_reg_range(0x201b, 0x201b), 809 regmap_reg_range(0x201f, 0x2020), 810 regmap_reg_range(0x2030, 0x2030), 811 regmap_reg_range(0x2100, 0x2115), 812 regmap_reg_range(0x211a, 0x211f), 813 regmap_reg_range(0x2120, 0x212b), 814 regmap_reg_range(0x2134, 0x213b), 815 regmap_reg_range(0x213c, 0x213f), 816 regmap_reg_range(0x2400, 0x2401), 817 regmap_reg_range(0x2403, 0x2403), 818 regmap_reg_range(0x2410, 0x2417), 819 regmap_reg_range(0x2420, 0x2423), 820 regmap_reg_range(0x2500, 0x2507), 821 regmap_reg_range(0x2600, 0x2613), 822 regmap_reg_range(0x2800, 0x280f), 823 regmap_reg_range(0x2820, 0x2827), 824 regmap_reg_range(0x2830, 0x2837), 825 regmap_reg_range(0x2840, 0x284b), 826 regmap_reg_range(0x2900, 0x2907), 827 regmap_reg_range(0x2914, 0x291b), 828 regmap_reg_range(0x2920, 0x2920), 829 regmap_reg_range(0x2923, 0x2927), 830 regmap_reg_range(0x2a00, 0x2a03), 831 regmap_reg_range(0x2a04, 0x2a07), 832 regmap_reg_range(0x2b00, 0x2b01), 833 regmap_reg_range(0x2b04, 0x2b04), 834 regmap_reg_range(0x2c00, 0x2c05), 835 regmap_reg_range(0x2c08, 0x2c1b), 836 837 /* port 3 */ 838 regmap_reg_range(0x3000, 0x3001), 839 regmap_reg_range(0x3013, 0x3013), 840 regmap_reg_range(0x3017, 0x3017), 841 regmap_reg_range(0x301b, 0x301b), 842 regmap_reg_range(0x301f, 0x3020), 843 regmap_reg_range(0x3030, 0x3030), 844 regmap_reg_range(0x3100, 0x3115), 845 regmap_reg_range(0x311a, 0x311f), 846 regmap_reg_range(0x3120, 0x312b), 847 regmap_reg_range(0x3134, 0x313b), 848 regmap_reg_range(0x313c, 0x313f), 849 regmap_reg_range(0x3400, 0x3401), 850 regmap_reg_range(0x3403, 0x3403), 851 regmap_reg_range(0x3410, 0x3417), 852 regmap_reg_range(0x3420, 0x3423), 853 regmap_reg_range(0x3500, 0x3507), 854 regmap_reg_range(0x3600, 0x3613), 855 regmap_reg_range(0x3800, 0x380f), 856 regmap_reg_range(0x3820, 0x3827), 857 regmap_reg_range(0x3830, 0x3837), 858 regmap_reg_range(0x3840, 0x384b), 859 regmap_reg_range(0x3900, 0x3907), 860 regmap_reg_range(0x3914, 0x391b), 861 regmap_reg_range(0x3920, 0x3920), 862 regmap_reg_range(0x3923, 0x3927), 863 regmap_reg_range(0x3a00, 0x3a03), 864 regmap_reg_range(0x3a04, 0x3a07), 865 regmap_reg_range(0x3b00, 0x3b01), 866 regmap_reg_range(0x3b04, 0x3b04), 867 regmap_reg_range(0x3c00, 0x3c05), 868 regmap_reg_range(0x3c08, 0x3c1b), 869 870 /* port 4 */ 871 regmap_reg_range(0x4000, 0x4001), 872 regmap_reg_range(0x4013, 0x4013), 873 regmap_reg_range(0x4017, 0x4017), 874 regmap_reg_range(0x401b, 0x401b), 875 regmap_reg_range(0x401f, 0x4020), 876 regmap_reg_range(0x4030, 0x4030), 877 regmap_reg_range(0x4100, 0x4115), 878 regmap_reg_range(0x411a, 0x411f), 879 regmap_reg_range(0x4120, 0x412b), 880 regmap_reg_range(0x4134, 0x413b), 881 regmap_reg_range(0x413c, 0x413f), 882 regmap_reg_range(0x4400, 0x4401), 883 regmap_reg_range(0x4403, 0x4403), 884 regmap_reg_range(0x4410, 0x4417), 885 regmap_reg_range(0x4420, 0x4423), 886 regmap_reg_range(0x4500, 0x4507), 887 regmap_reg_range(0x4600, 0x4613), 888 regmap_reg_range(0x4800, 0x480f), 889 regmap_reg_range(0x4820, 0x4827), 890 regmap_reg_range(0x4830, 0x4837), 891 regmap_reg_range(0x4840, 0x484b), 892 regmap_reg_range(0x4900, 0x4907), 893 regmap_reg_range(0x4914, 0x491b), 894 regmap_reg_range(0x4920, 0x4920), 895 regmap_reg_range(0x4923, 0x4927), 896 regmap_reg_range(0x4a00, 0x4a03), 897 regmap_reg_range(0x4a04, 0x4a07), 898 regmap_reg_range(0x4b00, 0x4b01), 899 regmap_reg_range(0x4b04, 0x4b04), 900 regmap_reg_range(0x4c00, 0x4c05), 901 regmap_reg_range(0x4c08, 0x4c1b), 902 903 /* port 5 */ 904 regmap_reg_range(0x5000, 0x5001), 905 regmap_reg_range(0x5013, 0x5013), 906 regmap_reg_range(0x5017, 0x5017), 907 regmap_reg_range(0x501b, 0x501b), 908 regmap_reg_range(0x501f, 0x5020), 909 regmap_reg_range(0x5030, 0x5030), 910 regmap_reg_range(0x5100, 0x5115), 911 regmap_reg_range(0x511a, 0x511f), 912 regmap_reg_range(0x5120, 0x512b), 913 regmap_reg_range(0x5134, 0x513b), 914 regmap_reg_range(0x513c, 0x513f), 915 regmap_reg_range(0x5400, 0x5401), 916 regmap_reg_range(0x5403, 0x5403), 917 regmap_reg_range(0x5410, 0x5417), 918 regmap_reg_range(0x5420, 0x5423), 919 regmap_reg_range(0x5500, 0x5507), 920 regmap_reg_range(0x5600, 0x5613), 921 regmap_reg_range(0x5800, 0x580f), 922 regmap_reg_range(0x5820, 0x5827), 923 regmap_reg_range(0x5830, 0x5837), 924 regmap_reg_range(0x5840, 0x584b), 925 regmap_reg_range(0x5900, 0x5907), 926 regmap_reg_range(0x5914, 0x591b), 927 regmap_reg_range(0x5920, 0x5920), 928 regmap_reg_range(0x5923, 0x5927), 929 regmap_reg_range(0x5a00, 0x5a03), 930 regmap_reg_range(0x5a04, 0x5a07), 931 regmap_reg_range(0x5b00, 0x5b01), 932 regmap_reg_range(0x5b04, 0x5b04), 933 regmap_reg_range(0x5c00, 0x5c05), 934 regmap_reg_range(0x5c08, 0x5c1b), 935 936 /* port 6 */ 937 regmap_reg_range(0x6000, 0x6001), 938 regmap_reg_range(0x6013, 0x6013), 939 regmap_reg_range(0x6017, 0x6017), 940 regmap_reg_range(0x601b, 0x601b), 941 regmap_reg_range(0x601f, 0x6020), 942 regmap_reg_range(0x6030, 0x6030), 943 regmap_reg_range(0x6300, 0x6301), 944 regmap_reg_range(0x6400, 0x6401), 945 regmap_reg_range(0x6403, 0x6403), 946 regmap_reg_range(0x6410, 0x6417), 947 regmap_reg_range(0x6420, 0x6423), 948 regmap_reg_range(0x6500, 0x6507), 949 regmap_reg_range(0x6600, 0x6613), 950 regmap_reg_range(0x6800, 0x680f), 951 regmap_reg_range(0x6820, 0x6827), 952 regmap_reg_range(0x6830, 0x6837), 953 regmap_reg_range(0x6840, 0x684b), 954 regmap_reg_range(0x6900, 0x6907), 955 regmap_reg_range(0x6914, 0x691b), 956 regmap_reg_range(0x6920, 0x6920), 957 regmap_reg_range(0x6923, 0x6927), 958 regmap_reg_range(0x6a00, 0x6a03), 959 regmap_reg_range(0x6a04, 0x6a07), 960 regmap_reg_range(0x6b00, 0x6b01), 961 regmap_reg_range(0x6b04, 0x6b04), 962 regmap_reg_range(0x6c00, 0x6c05), 963 regmap_reg_range(0x6c08, 0x6c1b), 964 965 /* port 7 */ 966 regmap_reg_range(0x7000, 0x7001), 967 regmap_reg_range(0x7013, 0x7013), 968 regmap_reg_range(0x7017, 0x7017), 969 regmap_reg_range(0x701b, 0x701b), 970 regmap_reg_range(0x701f, 0x7020), 971 regmap_reg_range(0x7030, 0x7030), 972 regmap_reg_range(0x7200, 0x7207), 973 regmap_reg_range(0x7300, 0x7301), 974 regmap_reg_range(0x7400, 0x7401), 975 regmap_reg_range(0x7403, 0x7403), 976 regmap_reg_range(0x7410, 0x7417), 977 regmap_reg_range(0x7420, 0x7423), 978 regmap_reg_range(0x7500, 0x7507), 979 regmap_reg_range(0x7600, 0x7613), 980 regmap_reg_range(0x7800, 0x780f), 981 regmap_reg_range(0x7820, 0x7827), 982 regmap_reg_range(0x7830, 0x7837), 983 regmap_reg_range(0x7840, 0x784b), 984 regmap_reg_range(0x7900, 0x7907), 985 regmap_reg_range(0x7914, 0x791b), 986 regmap_reg_range(0x7920, 0x7920), 987 regmap_reg_range(0x7923, 0x7927), 988 regmap_reg_range(0x7a00, 0x7a03), 989 regmap_reg_range(0x7a04, 0x7a07), 990 regmap_reg_range(0x7b00, 0x7b01), 991 regmap_reg_range(0x7b04, 0x7b04), 992 regmap_reg_range(0x7c00, 0x7c05), 993 regmap_reg_range(0x7c08, 0x7c1b), 994 }; 995 996 static const struct regmap_access_table ksz9477_register_set = { 997 .yes_ranges = ksz9477_valid_regs, 998 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 999 }; 1000 1001 static const struct regmap_range ksz9896_valid_regs[] = { 1002 regmap_reg_range(0x0000, 0x0003), 1003 regmap_reg_range(0x0006, 0x0006), 1004 regmap_reg_range(0x0010, 0x001f), 1005 regmap_reg_range(0x0100, 0x0100), 1006 regmap_reg_range(0x0103, 0x0107), 1007 regmap_reg_range(0x010d, 0x010d), 1008 regmap_reg_range(0x0110, 0x0113), 1009 regmap_reg_range(0x0120, 0x0127), 1010 regmap_reg_range(0x0201, 0x0201), 1011 regmap_reg_range(0x0210, 0x0213), 1012 regmap_reg_range(0x0300, 0x0300), 1013 regmap_reg_range(0x0302, 0x030b), 1014 regmap_reg_range(0x0310, 0x031b), 1015 regmap_reg_range(0x0320, 0x032b), 1016 regmap_reg_range(0x0330, 0x0336), 1017 regmap_reg_range(0x0338, 0x033b), 1018 regmap_reg_range(0x033e, 0x033e), 1019 regmap_reg_range(0x0340, 0x035f), 1020 regmap_reg_range(0x0370, 0x0370), 1021 regmap_reg_range(0x0378, 0x0378), 1022 regmap_reg_range(0x037c, 0x037d), 1023 regmap_reg_range(0x0390, 0x0393), 1024 regmap_reg_range(0x0400, 0x040e), 1025 regmap_reg_range(0x0410, 0x042f), 1026 1027 /* port 1 */ 1028 regmap_reg_range(0x1000, 0x1001), 1029 regmap_reg_range(0x1013, 0x1013), 1030 regmap_reg_range(0x1017, 0x1017), 1031 regmap_reg_range(0x101b, 0x101b), 1032 regmap_reg_range(0x101f, 0x1020), 1033 regmap_reg_range(0x1030, 0x1030), 1034 regmap_reg_range(0x1100, 0x1115), 1035 regmap_reg_range(0x111a, 0x111f), 1036 regmap_reg_range(0x1120, 0x112b), 1037 regmap_reg_range(0x1134, 0x113b), 1038 regmap_reg_range(0x113c, 0x113f), 1039 regmap_reg_range(0x1400, 0x1401), 1040 regmap_reg_range(0x1403, 0x1403), 1041 regmap_reg_range(0x1410, 0x1417), 1042 regmap_reg_range(0x1420, 0x1423), 1043 regmap_reg_range(0x1500, 0x1507), 1044 regmap_reg_range(0x1600, 0x1612), 1045 regmap_reg_range(0x1800, 0x180f), 1046 regmap_reg_range(0x1820, 0x1827), 1047 regmap_reg_range(0x1830, 0x1837), 1048 regmap_reg_range(0x1840, 0x184b), 1049 regmap_reg_range(0x1900, 0x1907), 1050 regmap_reg_range(0x1914, 0x1915), 1051 regmap_reg_range(0x1a00, 0x1a03), 1052 regmap_reg_range(0x1a04, 0x1a07), 1053 regmap_reg_range(0x1b00, 0x1b01), 1054 regmap_reg_range(0x1b04, 0x1b04), 1055 1056 /* port 2 */ 1057 regmap_reg_range(0x2000, 0x2001), 1058 regmap_reg_range(0x2013, 0x2013), 1059 regmap_reg_range(0x2017, 0x2017), 1060 regmap_reg_range(0x201b, 0x201b), 1061 regmap_reg_range(0x201f, 0x2020), 1062 regmap_reg_range(0x2030, 0x2030), 1063 regmap_reg_range(0x2100, 0x2115), 1064 regmap_reg_range(0x211a, 0x211f), 1065 regmap_reg_range(0x2120, 0x212b), 1066 regmap_reg_range(0x2134, 0x213b), 1067 regmap_reg_range(0x213c, 0x213f), 1068 regmap_reg_range(0x2400, 0x2401), 1069 regmap_reg_range(0x2403, 0x2403), 1070 regmap_reg_range(0x2410, 0x2417), 1071 regmap_reg_range(0x2420, 0x2423), 1072 regmap_reg_range(0x2500, 0x2507), 1073 regmap_reg_range(0x2600, 0x2612), 1074 regmap_reg_range(0x2800, 0x280f), 1075 regmap_reg_range(0x2820, 0x2827), 1076 regmap_reg_range(0x2830, 0x2837), 1077 regmap_reg_range(0x2840, 0x284b), 1078 regmap_reg_range(0x2900, 0x2907), 1079 regmap_reg_range(0x2914, 0x2915), 1080 regmap_reg_range(0x2a00, 0x2a03), 1081 regmap_reg_range(0x2a04, 0x2a07), 1082 regmap_reg_range(0x2b00, 0x2b01), 1083 regmap_reg_range(0x2b04, 0x2b04), 1084 1085 /* port 3 */ 1086 regmap_reg_range(0x3000, 0x3001), 1087 regmap_reg_range(0x3013, 0x3013), 1088 regmap_reg_range(0x3017, 0x3017), 1089 regmap_reg_range(0x301b, 0x301b), 1090 regmap_reg_range(0x301f, 0x3020), 1091 regmap_reg_range(0x3030, 0x3030), 1092 regmap_reg_range(0x3100, 0x3115), 1093 regmap_reg_range(0x311a, 0x311f), 1094 regmap_reg_range(0x3120, 0x312b), 1095 regmap_reg_range(0x3134, 0x313b), 1096 regmap_reg_range(0x313c, 0x313f), 1097 regmap_reg_range(0x3400, 0x3401), 1098 regmap_reg_range(0x3403, 0x3403), 1099 regmap_reg_range(0x3410, 0x3417), 1100 regmap_reg_range(0x3420, 0x3423), 1101 regmap_reg_range(0x3500, 0x3507), 1102 regmap_reg_range(0x3600, 0x3612), 1103 regmap_reg_range(0x3800, 0x380f), 1104 regmap_reg_range(0x3820, 0x3827), 1105 regmap_reg_range(0x3830, 0x3837), 1106 regmap_reg_range(0x3840, 0x384b), 1107 regmap_reg_range(0x3900, 0x3907), 1108 regmap_reg_range(0x3914, 0x3915), 1109 regmap_reg_range(0x3a00, 0x3a03), 1110 regmap_reg_range(0x3a04, 0x3a07), 1111 regmap_reg_range(0x3b00, 0x3b01), 1112 regmap_reg_range(0x3b04, 0x3b04), 1113 1114 /* port 4 */ 1115 regmap_reg_range(0x4000, 0x4001), 1116 regmap_reg_range(0x4013, 0x4013), 1117 regmap_reg_range(0x4017, 0x4017), 1118 regmap_reg_range(0x401b, 0x401b), 1119 regmap_reg_range(0x401f, 0x4020), 1120 regmap_reg_range(0x4030, 0x4030), 1121 regmap_reg_range(0x4100, 0x4115), 1122 regmap_reg_range(0x411a, 0x411f), 1123 regmap_reg_range(0x4120, 0x412b), 1124 regmap_reg_range(0x4134, 0x413b), 1125 regmap_reg_range(0x413c, 0x413f), 1126 regmap_reg_range(0x4400, 0x4401), 1127 regmap_reg_range(0x4403, 0x4403), 1128 regmap_reg_range(0x4410, 0x4417), 1129 regmap_reg_range(0x4420, 0x4423), 1130 regmap_reg_range(0x4500, 0x4507), 1131 regmap_reg_range(0x4600, 0x4612), 1132 regmap_reg_range(0x4800, 0x480f), 1133 regmap_reg_range(0x4820, 0x4827), 1134 regmap_reg_range(0x4830, 0x4837), 1135 regmap_reg_range(0x4840, 0x484b), 1136 regmap_reg_range(0x4900, 0x4907), 1137 regmap_reg_range(0x4914, 0x4915), 1138 regmap_reg_range(0x4a00, 0x4a03), 1139 regmap_reg_range(0x4a04, 0x4a07), 1140 regmap_reg_range(0x4b00, 0x4b01), 1141 regmap_reg_range(0x4b04, 0x4b04), 1142 1143 /* port 5 */ 1144 regmap_reg_range(0x5000, 0x5001), 1145 regmap_reg_range(0x5013, 0x5013), 1146 regmap_reg_range(0x5017, 0x5017), 1147 regmap_reg_range(0x501b, 0x501b), 1148 regmap_reg_range(0x501f, 0x5020), 1149 regmap_reg_range(0x5030, 0x5030), 1150 regmap_reg_range(0x5100, 0x5115), 1151 regmap_reg_range(0x511a, 0x511f), 1152 regmap_reg_range(0x5120, 0x512b), 1153 regmap_reg_range(0x5134, 0x513b), 1154 regmap_reg_range(0x513c, 0x513f), 1155 regmap_reg_range(0x5400, 0x5401), 1156 regmap_reg_range(0x5403, 0x5403), 1157 regmap_reg_range(0x5410, 0x5417), 1158 regmap_reg_range(0x5420, 0x5423), 1159 regmap_reg_range(0x5500, 0x5507), 1160 regmap_reg_range(0x5600, 0x5612), 1161 regmap_reg_range(0x5800, 0x580f), 1162 regmap_reg_range(0x5820, 0x5827), 1163 regmap_reg_range(0x5830, 0x5837), 1164 regmap_reg_range(0x5840, 0x584b), 1165 regmap_reg_range(0x5900, 0x5907), 1166 regmap_reg_range(0x5914, 0x5915), 1167 regmap_reg_range(0x5a00, 0x5a03), 1168 regmap_reg_range(0x5a04, 0x5a07), 1169 regmap_reg_range(0x5b00, 0x5b01), 1170 regmap_reg_range(0x5b04, 0x5b04), 1171 1172 /* port 6 */ 1173 regmap_reg_range(0x6000, 0x6001), 1174 regmap_reg_range(0x6013, 0x6013), 1175 regmap_reg_range(0x6017, 0x6017), 1176 regmap_reg_range(0x601b, 0x601b), 1177 regmap_reg_range(0x601f, 0x6020), 1178 regmap_reg_range(0x6030, 0x6030), 1179 regmap_reg_range(0x6100, 0x6115), 1180 regmap_reg_range(0x611a, 0x611f), 1181 regmap_reg_range(0x6120, 0x612b), 1182 regmap_reg_range(0x6134, 0x613b), 1183 regmap_reg_range(0x613c, 0x613f), 1184 regmap_reg_range(0x6300, 0x6301), 1185 regmap_reg_range(0x6400, 0x6401), 1186 regmap_reg_range(0x6403, 0x6403), 1187 regmap_reg_range(0x6410, 0x6417), 1188 regmap_reg_range(0x6420, 0x6423), 1189 regmap_reg_range(0x6500, 0x6507), 1190 regmap_reg_range(0x6600, 0x6612), 1191 regmap_reg_range(0x6800, 0x680f), 1192 regmap_reg_range(0x6820, 0x6827), 1193 regmap_reg_range(0x6830, 0x6837), 1194 regmap_reg_range(0x6840, 0x684b), 1195 regmap_reg_range(0x6900, 0x6907), 1196 regmap_reg_range(0x6914, 0x6915), 1197 regmap_reg_range(0x6a00, 0x6a03), 1198 regmap_reg_range(0x6a04, 0x6a07), 1199 regmap_reg_range(0x6b00, 0x6b01), 1200 regmap_reg_range(0x6b04, 0x6b04), 1201 }; 1202 1203 static const struct regmap_access_table ksz9896_register_set = { 1204 .yes_ranges = ksz9896_valid_regs, 1205 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1206 }; 1207 1208 static const struct regmap_range ksz8873_valid_regs[] = { 1209 regmap_reg_range(0x00, 0x01), 1210 /* global control register */ 1211 regmap_reg_range(0x02, 0x0f), 1212 1213 /* port registers */ 1214 regmap_reg_range(0x10, 0x1d), 1215 regmap_reg_range(0x1e, 0x1f), 1216 regmap_reg_range(0x20, 0x2d), 1217 regmap_reg_range(0x2e, 0x2f), 1218 regmap_reg_range(0x30, 0x39), 1219 regmap_reg_range(0x3f, 0x3f), 1220 1221 /* advanced control registers */ 1222 regmap_reg_range(0x43, 0x43), 1223 regmap_reg_range(0x60, 0x6f), 1224 regmap_reg_range(0x70, 0x75), 1225 regmap_reg_range(0x76, 0x78), 1226 regmap_reg_range(0x79, 0x7a), 1227 regmap_reg_range(0x7b, 0x83), 1228 regmap_reg_range(0x8e, 0x99), 1229 regmap_reg_range(0x9a, 0xa5), 1230 regmap_reg_range(0xa6, 0xa6), 1231 regmap_reg_range(0xa7, 0xaa), 1232 regmap_reg_range(0xab, 0xae), 1233 regmap_reg_range(0xaf, 0xba), 1234 regmap_reg_range(0xbb, 0xbc), 1235 regmap_reg_range(0xbd, 0xbd), 1236 regmap_reg_range(0xc0, 0xc0), 1237 regmap_reg_range(0xc2, 0xc2), 1238 regmap_reg_range(0xc3, 0xc3), 1239 regmap_reg_range(0xc4, 0xc4), 1240 regmap_reg_range(0xc6, 0xc6), 1241 }; 1242 1243 static const struct regmap_access_table ksz8873_register_set = { 1244 .yes_ranges = ksz8873_valid_regs, 1245 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), 1246 }; 1247 1248 const struct ksz_chip_data ksz_switch_chips[] = { 1249 [KSZ8463] = { 1250 .chip_id = KSZ8463_CHIP_ID, 1251 .dev_name = "KSZ8463", 1252 .num_vlans = 16, 1253 .num_alus = 0, 1254 .num_statics = 8, 1255 .cpu_ports = 0x4, /* can be configured as cpu port */ 1256 .port_cnt = 3, 1257 .num_tx_queues = 4, 1258 .num_ipms = 4, 1259 .ops = &ksz8463_dev_ops, 1260 .switch_ops = &ksz8463_switch_ops, 1261 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1262 .mib_names = ksz88xx_mib_names, 1263 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1264 .reg_mib_cnt = MIB_COUNTER_NUM, 1265 .regs = ksz8463_regs, 1266 .masks = ksz8463_masks, 1267 .shifts = ksz8463_shifts, 1268 .supports_mii = {false, false, true}, 1269 .supports_rmii = {false, false, true}, 1270 .internal_phy = {true, true, false}, 1271 }, 1272 1273 [KSZ8563] = { 1274 .chip_id = KSZ8563_CHIP_ID, 1275 .dev_name = "KSZ8563", 1276 .num_vlans = 4096, 1277 .num_alus = 4096, 1278 .num_statics = 16, 1279 .cpu_ports = 0x07, /* can be configured as cpu port */ 1280 .port_cnt = 3, /* total port count */ 1281 .port_nirqs = 3, 1282 .num_tx_queues = 4, 1283 .num_ipms = 8, 1284 .tc_cbs_supported = true, 1285 .ops = &ksz9477_dev_ops, 1286 .switch_ops = &ksz9477_switch_ops, 1287 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1288 .mib_names = ksz9477_mib_names, 1289 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1290 .reg_mib_cnt = MIB_COUNTER_NUM, 1291 .regs = ksz9477_regs, 1292 .masks = ksz9477_masks, 1293 .shifts = ksz9477_shifts, 1294 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1295 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1296 .supports_mii = {false, false, true}, 1297 .supports_rmii = {false, false, true}, 1298 .supports_rgmii = {false, false, true}, 1299 .internal_phy = {true, true, false}, 1300 .gbit_capable = {false, false, true}, 1301 .ptp_capable = true, 1302 .wr_table = &ksz8563_register_set, 1303 .rd_table = &ksz8563_register_set, 1304 }, 1305 1306 [KSZ8795] = { 1307 .chip_id = KSZ8795_CHIP_ID, 1308 .dev_name = "KSZ8795", 1309 .num_vlans = 4096, 1310 .num_alus = 0, 1311 .num_statics = 32, 1312 .cpu_ports = 0x10, /* can be configured as cpu port */ 1313 .port_cnt = 5, /* total cpu and user ports */ 1314 .num_tx_queues = 4, 1315 .num_ipms = 4, 1316 .ops = &ksz87xx_dev_ops, 1317 .switch_ops = &ksz87xx_switch_ops, 1318 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1319 .ksz87xx_eee_link_erratum = true, 1320 .mib_names = ksz9477_mib_names, 1321 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1322 .reg_mib_cnt = MIB_COUNTER_NUM, 1323 .regs = ksz8795_regs, 1324 .masks = ksz8795_masks, 1325 .shifts = ksz8795_shifts, 1326 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1327 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1328 .supports_mii = {false, false, false, false, true}, 1329 .supports_rmii = {false, false, false, false, true}, 1330 .supports_rgmii = {false, false, false, false, true}, 1331 .internal_phy = {true, true, true, true, false}, 1332 }, 1333 1334 [KSZ8794] = { 1335 /* WARNING 1336 * ======= 1337 * KSZ8794 is similar to KSZ8795, except the port map 1338 * contains a gap between external and CPU ports, the 1339 * port map is NOT continuous. The per-port register 1340 * map is shifted accordingly too, i.e. registers at 1341 * offset 0x40 are NOT used on KSZ8794 and they ARE 1342 * used on KSZ8795 for external port 3. 1343 * external cpu 1344 * KSZ8794 0,1,2 4 1345 * KSZ8795 0,1,2,3 4 1346 * KSZ8765 0,1,2,3 4 1347 * port_cnt is configured as 5, even though it is 4 1348 */ 1349 .chip_id = KSZ8794_CHIP_ID, 1350 .dev_name = "KSZ8794", 1351 .num_vlans = 4096, 1352 .num_alus = 0, 1353 .num_statics = 32, 1354 .cpu_ports = 0x10, /* can be configured as cpu port */ 1355 .port_cnt = 5, /* total cpu and user ports */ 1356 .num_tx_queues = 4, 1357 .num_ipms = 4, 1358 .ops = &ksz87xx_dev_ops, 1359 .switch_ops = &ksz87xx_switch_ops, 1360 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1361 .ksz87xx_eee_link_erratum = true, 1362 .mib_names = ksz9477_mib_names, 1363 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1364 .reg_mib_cnt = MIB_COUNTER_NUM, 1365 .regs = ksz8795_regs, 1366 .masks = ksz8795_masks, 1367 .shifts = ksz8795_shifts, 1368 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1369 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1370 .supports_mii = {false, false, false, false, true}, 1371 .supports_rmii = {false, false, false, false, true}, 1372 .supports_rgmii = {false, false, false, false, true}, 1373 .internal_phy = {true, true, true, false, false}, 1374 }, 1375 1376 [KSZ8765] = { 1377 .chip_id = KSZ8765_CHIP_ID, 1378 .dev_name = "KSZ8765", 1379 .num_vlans = 4096, 1380 .num_alus = 0, 1381 .num_statics = 32, 1382 .cpu_ports = 0x10, /* can be configured as cpu port */ 1383 .port_cnt = 5, /* total cpu and user ports */ 1384 .num_tx_queues = 4, 1385 .num_ipms = 4, 1386 .ops = &ksz87xx_dev_ops, 1387 .switch_ops = &ksz87xx_switch_ops, 1388 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1389 .ksz87xx_eee_link_erratum = true, 1390 .mib_names = ksz9477_mib_names, 1391 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1392 .reg_mib_cnt = MIB_COUNTER_NUM, 1393 .regs = ksz8795_regs, 1394 .masks = ksz8795_masks, 1395 .shifts = ksz8795_shifts, 1396 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1397 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1398 .supports_mii = {false, false, false, false, true}, 1399 .supports_rmii = {false, false, false, false, true}, 1400 .supports_rgmii = {false, false, false, false, true}, 1401 .internal_phy = {true, true, true, true, false}, 1402 }, 1403 1404 [KSZ88X3] = { 1405 .chip_id = KSZ88X3_CHIP_ID, 1406 .dev_name = "KSZ8863/KSZ8873", 1407 .num_vlans = 16, 1408 .num_alus = 0, 1409 .num_statics = 8, 1410 .cpu_ports = 0x4, /* can be configured as cpu port */ 1411 .port_cnt = 3, 1412 .num_tx_queues = 4, 1413 .num_ipms = 4, 1414 .ops = &ksz88xx_dev_ops, 1415 .switch_ops = &ksz88xx_switch_ops, 1416 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1417 .mib_names = ksz88xx_mib_names, 1418 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1419 .reg_mib_cnt = MIB_COUNTER_NUM, 1420 .regs = ksz8863_regs, 1421 .masks = ksz8863_masks, 1422 .shifts = ksz8863_shifts, 1423 .supports_mii = {false, false, true}, 1424 .supports_rmii = {false, false, true}, 1425 .internal_phy = {true, true, false}, 1426 .wr_table = &ksz8873_register_set, 1427 .rd_table = &ksz8873_register_set, 1428 }, 1429 1430 [KSZ8864] = { 1431 /* WARNING 1432 * ======= 1433 * KSZ8864 is similar to KSZ8895, except the first port 1434 * does not exist. 1435 * external cpu 1436 * KSZ8864 1,2,3 4 1437 * KSZ8895 0,1,2,3 4 1438 * port_cnt is configured as 5, even though it is 4 1439 */ 1440 .chip_id = KSZ8864_CHIP_ID, 1441 .dev_name = "KSZ8864", 1442 .num_vlans = 4096, 1443 .num_alus = 0, 1444 .num_statics = 32, 1445 .cpu_ports = 0x10, /* can be configured as cpu port */ 1446 .port_cnt = 5, /* total cpu and user ports */ 1447 .num_tx_queues = 4, 1448 .num_ipms = 4, 1449 .ops = &ksz88xx_dev_ops, 1450 .switch_ops = &ksz88xx_switch_ops, 1451 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1452 .mib_names = ksz88xx_mib_names, 1453 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1454 .reg_mib_cnt = MIB_COUNTER_NUM, 1455 .regs = ksz8895_regs, 1456 .masks = ksz8895_masks, 1457 .shifts = ksz8895_shifts, 1458 .supports_mii = {false, false, false, false, true}, 1459 .supports_rmii = {false, false, false, false, true}, 1460 .internal_phy = {false, true, true, true, false}, 1461 }, 1462 1463 [KSZ8895] = { 1464 .chip_id = KSZ8895_CHIP_ID, 1465 .dev_name = "KSZ8895", 1466 .num_vlans = 4096, 1467 .num_alus = 0, 1468 .num_statics = 32, 1469 .cpu_ports = 0x10, /* can be configured as cpu port */ 1470 .port_cnt = 5, /* total cpu and user ports */ 1471 .num_tx_queues = 4, 1472 .num_ipms = 4, 1473 .ops = &ksz88xx_dev_ops, 1474 .switch_ops = &ksz88xx_switch_ops, 1475 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1476 .mib_names = ksz88xx_mib_names, 1477 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1478 .reg_mib_cnt = MIB_COUNTER_NUM, 1479 .regs = ksz8895_regs, 1480 .masks = ksz8895_masks, 1481 .shifts = ksz8895_shifts, 1482 .supports_mii = {false, false, false, false, true}, 1483 .supports_rmii = {false, false, false, false, true}, 1484 .internal_phy = {true, true, true, true, false}, 1485 }, 1486 1487 [KSZ9477] = { 1488 .chip_id = KSZ9477_CHIP_ID, 1489 .dev_name = "KSZ9477", 1490 .num_vlans = 4096, 1491 .num_alus = 4096, 1492 .num_statics = 16, 1493 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1494 .port_cnt = 7, /* total physical port count */ 1495 .port_nirqs = 4, 1496 .num_tx_queues = 4, 1497 .num_ipms = 8, 1498 .tc_cbs_supported = true, 1499 .ops = &ksz9477_dev_ops, 1500 .switch_ops = &ksz9477_switch_ops, 1501 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1502 .phy_errata_9477 = true, 1503 .mib_names = ksz9477_mib_names, 1504 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1505 .reg_mib_cnt = MIB_COUNTER_NUM, 1506 .regs = ksz9477_regs, 1507 .masks = ksz9477_masks, 1508 .shifts = ksz9477_shifts, 1509 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1510 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1511 .supports_mii = {false, false, false, false, 1512 false, true, false}, 1513 .supports_rmii = {false, false, false, false, 1514 false, true, false}, 1515 .supports_rgmii = {false, false, false, false, 1516 false, true, false}, 1517 .internal_phy = {true, true, true, true, 1518 true, false, false}, 1519 .gbit_capable = {true, true, true, true, true, true, true}, 1520 .ptp_capable = true, 1521 .sgmii_port = 7, 1522 .wr_table = &ksz9477_register_set, 1523 .rd_table = &ksz9477_register_set, 1524 }, 1525 1526 [KSZ9896] = { 1527 .chip_id = KSZ9896_CHIP_ID, 1528 .dev_name = "KSZ9896", 1529 .num_vlans = 4096, 1530 .num_alus = 4096, 1531 .num_statics = 16, 1532 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1533 .port_cnt = 6, /* total physical port count */ 1534 .port_nirqs = 2, 1535 .num_tx_queues = 4, 1536 .num_ipms = 8, 1537 .ops = &ksz9477_dev_ops, 1538 .switch_ops = &ksz9477_switch_ops, 1539 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1540 .phy_errata_9477 = true, 1541 .mib_names = ksz9477_mib_names, 1542 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1543 .reg_mib_cnt = MIB_COUNTER_NUM, 1544 .regs = ksz9477_regs, 1545 .masks = ksz9477_masks, 1546 .shifts = ksz9477_shifts, 1547 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1548 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1549 .supports_mii = {false, false, false, false, 1550 false, true}, 1551 .supports_rmii = {false, false, false, false, 1552 false, true}, 1553 .supports_rgmii = {false, false, false, false, 1554 false, true}, 1555 .internal_phy = {true, true, true, true, 1556 true, false}, 1557 .gbit_capable = {true, true, true, true, true, true}, 1558 .wr_table = &ksz9896_register_set, 1559 .rd_table = &ksz9896_register_set, 1560 }, 1561 1562 [KSZ9897] = { 1563 .chip_id = KSZ9897_CHIP_ID, 1564 .dev_name = "KSZ9897", 1565 .num_vlans = 4096, 1566 .num_alus = 4096, 1567 .num_statics = 16, 1568 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1569 .port_cnt = 7, /* total physical port count */ 1570 .port_nirqs = 2, 1571 .num_tx_queues = 4, 1572 .num_ipms = 8, 1573 .ops = &ksz9477_dev_ops, 1574 .switch_ops = &ksz9477_switch_ops, 1575 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1576 .phy_errata_9477 = true, 1577 .mib_names = ksz9477_mib_names, 1578 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1579 .reg_mib_cnt = MIB_COUNTER_NUM, 1580 .regs = ksz9477_regs, 1581 .masks = ksz9477_masks, 1582 .shifts = ksz9477_shifts, 1583 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1584 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1585 .supports_mii = {false, false, false, false, 1586 false, true, true}, 1587 .supports_rmii = {false, false, false, false, 1588 false, true, true}, 1589 .supports_rgmii = {false, false, false, false, 1590 false, true, true}, 1591 .internal_phy = {true, true, true, true, 1592 true, false, false}, 1593 .gbit_capable = {true, true, true, true, true, true, true}, 1594 }, 1595 1596 [KSZ9893] = { 1597 .chip_id = KSZ9893_CHIP_ID, 1598 .dev_name = "KSZ9893", 1599 .num_vlans = 4096, 1600 .num_alus = 4096, 1601 .num_statics = 16, 1602 .cpu_ports = 0x07, /* can be configured as cpu port */ 1603 .port_cnt = 3, /* total port count */ 1604 .port_nirqs = 2, 1605 .num_tx_queues = 4, 1606 .num_ipms = 8, 1607 .ops = &ksz9477_dev_ops, 1608 .switch_ops = &ksz9477_switch_ops, 1609 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1610 .mib_names = ksz9477_mib_names, 1611 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1612 .reg_mib_cnt = MIB_COUNTER_NUM, 1613 .regs = ksz9477_regs, 1614 .masks = ksz9477_masks, 1615 .shifts = ksz9477_shifts, 1616 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1617 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1618 .supports_mii = {false, false, true}, 1619 .supports_rmii = {false, false, true}, 1620 .supports_rgmii = {false, false, true}, 1621 .internal_phy = {true, true, false}, 1622 .gbit_capable = {true, true, true}, 1623 }, 1624 1625 [KSZ9563] = { 1626 .chip_id = KSZ9563_CHIP_ID, 1627 .dev_name = "KSZ9563", 1628 .num_vlans = 4096, 1629 .num_alus = 4096, 1630 .num_statics = 16, 1631 .cpu_ports = 0x07, /* can be configured as cpu port */ 1632 .port_cnt = 3, /* total port count */ 1633 .port_nirqs = 3, 1634 .num_tx_queues = 4, 1635 .num_ipms = 8, 1636 .tc_cbs_supported = true, 1637 .ops = &ksz9477_dev_ops, 1638 .switch_ops = &ksz9477_switch_ops, 1639 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1640 .mib_names = ksz9477_mib_names, 1641 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1642 .reg_mib_cnt = MIB_COUNTER_NUM, 1643 .regs = ksz9477_regs, 1644 .masks = ksz9477_masks, 1645 .shifts = ksz9477_shifts, 1646 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1647 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1648 .supports_mii = {false, false, true}, 1649 .supports_rmii = {false, false, true}, 1650 .supports_rgmii = {false, false, true}, 1651 .internal_phy = {true, true, false}, 1652 .gbit_capable = {true, true, true}, 1653 .ptp_capable = true, 1654 }, 1655 1656 [KSZ8567] = { 1657 .chip_id = KSZ8567_CHIP_ID, 1658 .dev_name = "KSZ8567", 1659 .num_vlans = 4096, 1660 .num_alus = 4096, 1661 .num_statics = 16, 1662 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1663 .port_cnt = 7, /* total port count */ 1664 .port_nirqs = 3, 1665 .num_tx_queues = 4, 1666 .num_ipms = 8, 1667 .tc_cbs_supported = true, 1668 .ops = &ksz9477_dev_ops, 1669 .switch_ops = &ksz9477_switch_ops, 1670 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1671 .phy_errata_9477 = true, 1672 .mib_names = ksz9477_mib_names, 1673 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1674 .reg_mib_cnt = MIB_COUNTER_NUM, 1675 .regs = ksz9477_regs, 1676 .masks = ksz9477_masks, 1677 .shifts = ksz9477_shifts, 1678 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1679 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1680 .supports_mii = {false, false, false, false, 1681 false, true, true}, 1682 .supports_rmii = {false, false, false, false, 1683 false, true, true}, 1684 .supports_rgmii = {false, false, false, false, 1685 false, true, true}, 1686 .internal_phy = {true, true, true, true, 1687 true, false, false}, 1688 .gbit_capable = {false, false, false, false, false, 1689 true, true}, 1690 .ptp_capable = true, 1691 }, 1692 1693 [KSZ9567] = { 1694 .chip_id = KSZ9567_CHIP_ID, 1695 .dev_name = "KSZ9567", 1696 .num_vlans = 4096, 1697 .num_alus = 4096, 1698 .num_statics = 16, 1699 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1700 .port_cnt = 7, /* total physical port count */ 1701 .port_nirqs = 3, 1702 .num_tx_queues = 4, 1703 .num_ipms = 8, 1704 .tc_cbs_supported = true, 1705 .ops = &ksz9477_dev_ops, 1706 .switch_ops = &ksz9477_switch_ops, 1707 .mib_names = ksz9477_mib_names, 1708 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1709 .reg_mib_cnt = MIB_COUNTER_NUM, 1710 .regs = ksz9477_regs, 1711 .masks = ksz9477_masks, 1712 .shifts = ksz9477_shifts, 1713 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1714 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1715 .supports_mii = {false, false, false, false, 1716 false, true, true}, 1717 .supports_rmii = {false, false, false, false, 1718 false, true, true}, 1719 .supports_rgmii = {false, false, false, false, 1720 false, true, true}, 1721 .internal_phy = {true, true, true, true, 1722 true, false, false}, 1723 .gbit_capable = {true, true, true, true, true, true, true}, 1724 .ptp_capable = true, 1725 }, 1726 1727 [LAN9370] = { 1728 .chip_id = LAN9370_CHIP_ID, 1729 .dev_name = "LAN9370", 1730 .num_vlans = 4096, 1731 .num_alus = 1024, 1732 .num_statics = 256, 1733 .cpu_ports = 0x10, /* can be configured as cpu port */ 1734 .port_cnt = 5, /* total physical port count */ 1735 .port_nirqs = 6, 1736 .num_tx_queues = 8, 1737 .num_ipms = 8, 1738 .tc_cbs_supported = true, 1739 .phy_side_mdio_supported = true, 1740 .ops = &lan937x_dev_ops, 1741 .switch_ops = &lan937x_switch_ops, 1742 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1743 .mib_names = ksz9477_mib_names, 1744 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1745 .reg_mib_cnt = MIB_COUNTER_NUM, 1746 .regs = ksz9477_regs, 1747 .masks = lan937x_masks, 1748 .shifts = lan937x_shifts, 1749 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1750 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1751 .supports_mii = {false, false, false, false, true}, 1752 .supports_rmii = {false, false, false, false, true}, 1753 .supports_rgmii = {false, false, false, false, true}, 1754 .internal_phy = {true, true, true, true, false}, 1755 .ptp_capable = true, 1756 }, 1757 1758 [LAN9371] = { 1759 .chip_id = LAN9371_CHIP_ID, 1760 .dev_name = "LAN9371", 1761 .num_vlans = 4096, 1762 .num_alus = 1024, 1763 .num_statics = 256, 1764 .cpu_ports = 0x30, /* can be configured as cpu port */ 1765 .port_cnt = 6, /* total physical port count */ 1766 .port_nirqs = 6, 1767 .num_tx_queues = 8, 1768 .num_ipms = 8, 1769 .tc_cbs_supported = true, 1770 .phy_side_mdio_supported = true, 1771 .ops = &lan937x_dev_ops, 1772 .switch_ops = &lan937x_switch_ops, 1773 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1774 .mib_names = ksz9477_mib_names, 1775 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1776 .reg_mib_cnt = MIB_COUNTER_NUM, 1777 .regs = ksz9477_regs, 1778 .masks = lan937x_masks, 1779 .shifts = lan937x_shifts, 1780 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1781 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1782 .supports_mii = {false, false, false, false, true, true}, 1783 .supports_rmii = {false, false, false, false, true, true}, 1784 .supports_rgmii = {false, false, false, false, true, true}, 1785 .internal_phy = {true, true, true, true, false, false}, 1786 .ptp_capable = true, 1787 }, 1788 1789 [LAN9372] = { 1790 .chip_id = LAN9372_CHIP_ID, 1791 .dev_name = "LAN9372", 1792 .num_vlans = 4096, 1793 .num_alus = 1024, 1794 .num_statics = 256, 1795 .cpu_ports = 0x30, /* can be configured as cpu port */ 1796 .port_cnt = 8, /* total physical port count */ 1797 .port_nirqs = 6, 1798 .num_tx_queues = 8, 1799 .num_ipms = 8, 1800 .tc_cbs_supported = true, 1801 .phy_side_mdio_supported = true, 1802 .ops = &lan937x_dev_ops, 1803 .switch_ops = &lan937x_switch_ops, 1804 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1805 .mib_names = ksz9477_mib_names, 1806 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1807 .reg_mib_cnt = MIB_COUNTER_NUM, 1808 .regs = ksz9477_regs, 1809 .masks = lan937x_masks, 1810 .shifts = lan937x_shifts, 1811 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1812 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1813 .supports_mii = {false, false, false, false, 1814 true, true, false, false}, 1815 .supports_rmii = {false, false, false, false, 1816 true, true, false, false}, 1817 .supports_rgmii = {false, false, false, false, 1818 true, true, false, false}, 1819 .internal_phy = {true, true, true, true, 1820 false, false, true, true}, 1821 .ptp_capable = true, 1822 }, 1823 1824 [LAN9373] = { 1825 .chip_id = LAN9373_CHIP_ID, 1826 .dev_name = "LAN9373", 1827 .num_vlans = 4096, 1828 .num_alus = 1024, 1829 .num_statics = 256, 1830 .cpu_ports = 0x38, /* can be configured as cpu port */ 1831 .port_cnt = 5, /* total physical port count */ 1832 .port_nirqs = 6, 1833 .num_tx_queues = 8, 1834 .num_ipms = 8, 1835 .tc_cbs_supported = true, 1836 .phy_side_mdio_supported = true, 1837 .ops = &lan937x_dev_ops, 1838 .switch_ops = &lan937x_switch_ops, 1839 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1840 .mib_names = ksz9477_mib_names, 1841 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1842 .reg_mib_cnt = MIB_COUNTER_NUM, 1843 .regs = ksz9477_regs, 1844 .masks = lan937x_masks, 1845 .shifts = lan937x_shifts, 1846 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1847 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1848 .supports_mii = {false, false, false, false, 1849 true, true, false, false}, 1850 .supports_rmii = {false, false, false, false, 1851 true, true, false, false}, 1852 .supports_rgmii = {false, false, false, false, 1853 true, true, false, false}, 1854 .internal_phy = {true, true, true, false, 1855 false, false, true, true}, 1856 .ptp_capable = true, 1857 }, 1858 1859 [LAN9374] = { 1860 .chip_id = LAN9374_CHIP_ID, 1861 .dev_name = "LAN9374", 1862 .num_vlans = 4096, 1863 .num_alus = 1024, 1864 .num_statics = 256, 1865 .cpu_ports = 0x30, /* can be configured as cpu port */ 1866 .port_cnt = 8, /* total physical port count */ 1867 .port_nirqs = 6, 1868 .num_tx_queues = 8, 1869 .num_ipms = 8, 1870 .tc_cbs_supported = true, 1871 .phy_side_mdio_supported = true, 1872 .ops = &lan937x_dev_ops, 1873 .switch_ops = &lan937x_switch_ops, 1874 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1875 .mib_names = ksz9477_mib_names, 1876 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1877 .reg_mib_cnt = MIB_COUNTER_NUM, 1878 .regs = ksz9477_regs, 1879 .masks = lan937x_masks, 1880 .shifts = lan937x_shifts, 1881 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1882 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1883 .supports_mii = {false, false, false, false, 1884 true, true, false, false}, 1885 .supports_rmii = {false, false, false, false, 1886 true, true, false, false}, 1887 .supports_rgmii = {false, false, false, false, 1888 true, true, false, false}, 1889 .internal_phy = {true, true, true, true, 1890 false, false, true, true}, 1891 .ptp_capable = true, 1892 }, 1893 1894 [LAN9646] = { 1895 .chip_id = LAN9646_CHIP_ID, 1896 .dev_name = "LAN9646", 1897 .num_vlans = 4096, 1898 .num_alus = 4096, 1899 .num_statics = 16, 1900 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1901 .port_cnt = 7, /* total physical port count */ 1902 .port_nirqs = 4, 1903 .num_tx_queues = 4, 1904 .num_ipms = 8, 1905 .ops = &ksz9477_dev_ops, 1906 .switch_ops = &ksz9477_switch_ops, 1907 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1908 .phy_errata_9477 = true, 1909 .mib_names = ksz9477_mib_names, 1910 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1911 .reg_mib_cnt = MIB_COUNTER_NUM, 1912 .regs = ksz9477_regs, 1913 .masks = ksz9477_masks, 1914 .shifts = ksz9477_shifts, 1915 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1916 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1917 .supports_mii = {false, false, false, false, 1918 false, true, true}, 1919 .supports_rmii = {false, false, false, false, 1920 false, true, true}, 1921 .supports_rgmii = {false, false, false, false, 1922 false, true, true}, 1923 .internal_phy = {true, true, true, true, 1924 true, false, false}, 1925 .gbit_capable = {true, true, true, true, true, true, true}, 1926 .sgmii_port = 7, 1927 .wr_table = &ksz9477_register_set, 1928 .rd_table = &ksz9477_register_set, 1929 }, 1930 }; 1931 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1932 1933 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1934 { 1935 int i; 1936 1937 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1938 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1939 1940 if (chip->chip_id == prod_num) 1941 return chip; 1942 } 1943 1944 return NULL; 1945 } 1946 1947 static int ksz_check_device_id(struct ksz_device *dev) 1948 { 1949 const struct ksz_chip_data *expected_chip_data; 1950 u32 expected_chip_id; 1951 1952 if (dev->pdata) { 1953 expected_chip_id = dev->pdata->chip_id; 1954 expected_chip_data = ksz_lookup_info(expected_chip_id); 1955 if (WARN_ON(!expected_chip_data)) 1956 return -ENODEV; 1957 } else { 1958 expected_chip_data = of_device_get_match_data(dev->dev); 1959 expected_chip_id = expected_chip_data->chip_id; 1960 } 1961 1962 if (expected_chip_id != dev->chip_id) { 1963 dev_err(dev->dev, 1964 "Device tree specifies chip %s but found %s, please fix it!\n", 1965 expected_chip_data->dev_name, dev->info->dev_name); 1966 return -ENODEV; 1967 } 1968 1969 return 0; 1970 } 1971 1972 void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1973 struct phylink_config *config) 1974 { 1975 struct ksz_device *dev = ds->priv; 1976 1977 if (dev->info->supports_mii[port]) 1978 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1979 1980 if (dev->info->supports_rmii[port]) 1981 __set_bit(PHY_INTERFACE_MODE_RMII, 1982 config->supported_interfaces); 1983 1984 if (dev->info->supports_rgmii[port]) 1985 phy_interface_set_rgmii(config->supported_interfaces); 1986 1987 if (dev->info->internal_phy[port]) { 1988 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1989 config->supported_interfaces); 1990 /* Compatibility for phylib's default interface type when the 1991 * phy-mode property is absent 1992 */ 1993 __set_bit(PHY_INTERFACE_MODE_GMII, 1994 config->supported_interfaces); 1995 } 1996 1997 if (ds->ops->support_eee && ds->ops->support_eee(ds, port)) { 1998 memcpy(config->lpi_interfaces, config->supported_interfaces, 1999 sizeof(config->lpi_interfaces)); 2000 2001 config->lpi_capabilities = MAC_100FD; 2002 if (dev->info->gbit_capable[port]) 2003 config->lpi_capabilities |= MAC_1000FD; 2004 2005 /* EEE is fully operational */ 2006 config->eee_enabled_default = true; 2007 } 2008 } 2009 2010 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 2011 { 2012 struct ethtool_pause_stats *pstats; 2013 struct rtnl_link_stats64 *stats; 2014 struct ksz_stats_raw *raw; 2015 struct ksz_port_mib *mib; 2016 int ret; 2017 2018 mib = &dev->ports[port].mib; 2019 stats = &mib->stats64; 2020 pstats = &mib->pause_stats; 2021 raw = (struct ksz_stats_raw *)mib->counters; 2022 2023 spin_lock(&mib->stats64_lock); 2024 2025 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 2026 raw->rx_pause; 2027 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2028 raw->tx_pause; 2029 2030 /* HW counters are counting bytes + FCS which is not acceptable 2031 * for rtnl_link_stats64 interface 2032 */ 2033 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 2034 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 2035 2036 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2037 raw->rx_oversize; 2038 2039 stats->rx_crc_errors = raw->rx_crc_err; 2040 stats->rx_frame_errors = raw->rx_align_err; 2041 stats->rx_dropped = raw->rx_discards; 2042 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2043 stats->rx_frame_errors + stats->rx_dropped; 2044 2045 stats->tx_window_errors = raw->tx_late_col; 2046 stats->tx_fifo_errors = raw->tx_discards; 2047 stats->tx_aborted_errors = raw->tx_exc_col; 2048 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2049 stats->tx_aborted_errors; 2050 2051 stats->multicast = raw->rx_mcast; 2052 stats->collisions = raw->tx_total_col; 2053 2054 pstats->tx_pause_frames = raw->tx_pause; 2055 pstats->rx_pause_frames = raw->rx_pause; 2056 2057 spin_unlock(&mib->stats64_lock); 2058 2059 if (dev->info->phy_errata_9477 && !ksz_is_sgmii_port(dev, port)) { 2060 ret = ksz9477_errata_monitor(dev, port, raw->tx_late_col); 2061 if (ret) 2062 dev_err(dev->dev, "Failed to monitor transmission halt\n"); 2063 } 2064 } 2065 2066 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 2067 { 2068 struct ethtool_pause_stats *pstats; 2069 struct rtnl_link_stats64 *stats; 2070 struct ksz88xx_stats_raw *raw; 2071 struct ksz_port_mib *mib; 2072 2073 mib = &dev->ports[port].mib; 2074 stats = &mib->stats64; 2075 pstats = &mib->pause_stats; 2076 raw = (struct ksz88xx_stats_raw *)mib->counters; 2077 2078 spin_lock(&mib->stats64_lock); 2079 2080 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 2081 raw->rx_pause; 2082 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2083 raw->tx_pause; 2084 2085 /* HW counters are counting bytes + FCS which is not acceptable 2086 * for rtnl_link_stats64 interface 2087 */ 2088 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 2089 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 2090 2091 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2092 raw->rx_oversize; 2093 2094 stats->rx_crc_errors = raw->rx_crc_err; 2095 stats->rx_frame_errors = raw->rx_align_err; 2096 stats->rx_dropped = raw->rx_discards; 2097 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2098 stats->rx_frame_errors + stats->rx_dropped; 2099 2100 stats->tx_window_errors = raw->tx_late_col; 2101 stats->tx_fifo_errors = raw->tx_discards; 2102 stats->tx_aborted_errors = raw->tx_exc_col; 2103 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2104 stats->tx_aborted_errors; 2105 2106 stats->multicast = raw->rx_mcast; 2107 stats->collisions = raw->tx_total_col; 2108 2109 pstats->tx_pause_frames = raw->tx_pause; 2110 pstats->rx_pause_frames = raw->rx_pause; 2111 2112 spin_unlock(&mib->stats64_lock); 2113 } 2114 2115 void ksz_get_stats64(struct dsa_switch *ds, int port, 2116 struct rtnl_link_stats64 *s) 2117 { 2118 struct ksz_device *dev = ds->priv; 2119 struct ksz_port_mib *mib; 2120 2121 mib = &dev->ports[port].mib; 2122 2123 spin_lock(&mib->stats64_lock); 2124 memcpy(s, &mib->stats64, sizeof(*s)); 2125 spin_unlock(&mib->stats64_lock); 2126 } 2127 2128 void ksz_get_pause_stats(struct dsa_switch *ds, int port, 2129 struct ethtool_pause_stats *pause_stats) 2130 { 2131 struct ksz_device *dev = ds->priv; 2132 struct ksz_port_mib *mib; 2133 2134 mib = &dev->ports[port].mib; 2135 2136 spin_lock(&mib->stats64_lock); 2137 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 2138 spin_unlock(&mib->stats64_lock); 2139 } 2140 2141 void ksz_get_strings(struct dsa_switch *ds, int port, 2142 u32 stringset, uint8_t *buf) 2143 { 2144 struct ksz_device *dev = ds->priv; 2145 int i; 2146 2147 if (stringset != ETH_SS_STATS) 2148 return; 2149 2150 for (i = 0; i < dev->info->mib_cnt; i++) 2151 ethtool_puts(&buf, dev->info->mib_names[i].string); 2152 } 2153 2154 /** 2155 * ksz_update_port_member - Adjust port forwarding rules based on STP state and 2156 * isolation settings. 2157 * @dev: A pointer to the struct ksz_device representing the device. 2158 * @port: The port number to adjust. 2159 * 2160 * This function dynamically adjusts the port membership configuration for a 2161 * specified port and other device ports, based on Spanning Tree Protocol (STP) 2162 * states and port isolation settings. Each port, including the CPU port, has a 2163 * membership register, represented as a bitfield, where each bit corresponds 2164 * to a port number. A set bit indicates permission to forward frames to that 2165 * port. This function iterates over all ports, updating the membership register 2166 * to reflect current forwarding permissions: 2167 * 2168 * 1. Forwards frames only to ports that are part of the same bridge group and 2169 * in the BR_STATE_FORWARDING state. 2170 * 2. Takes into account the isolation status of ports; ports in the 2171 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward 2172 * frames to each other, even if they are in the same bridge group. 2173 * 3. Ensures that the CPU port is included in the membership based on its 2174 * upstream port configuration, allowing for management and control traffic 2175 * to flow as required. 2176 */ 2177 static void ksz_update_port_member(struct ksz_device *dev, int port) 2178 { 2179 struct ksz_port *p = &dev->ports[port]; 2180 struct dsa_switch *ds = dev->ds; 2181 u8 port_member = 0, cpu_port; 2182 const struct dsa_port *dp; 2183 int i, j; 2184 2185 if (!dsa_is_user_port(ds, port)) 2186 return; 2187 2188 dp = dsa_to_port(ds, port); 2189 cpu_port = BIT(dsa_upstream_port(ds, port)); 2190 2191 for (i = 0; i < ds->num_ports; i++) { 2192 const struct dsa_port *other_dp = dsa_to_port(ds, i); 2193 struct ksz_port *other_p = &dev->ports[i]; 2194 u8 val = 0; 2195 2196 if (!dsa_is_user_port(ds, i)) 2197 continue; 2198 if (port == i) 2199 continue; 2200 if (!dsa_port_bridge_same(dp, other_dp)) 2201 continue; 2202 if (other_p->stp_state != BR_STATE_FORWARDING) 2203 continue; 2204 2205 /* At this point we know that "port" and "other" port [i] are in 2206 * the same bridge group and that "other" port [i] is in 2207 * forwarding stp state. If "port" is also in forwarding stp 2208 * state, we can allow forwarding from port [port] to port [i]. 2209 * Except if both ports are isolated. 2210 */ 2211 if (p->stp_state == BR_STATE_FORWARDING && 2212 !(p->isolated && other_p->isolated)) { 2213 val |= BIT(port); 2214 port_member |= BIT(i); 2215 } 2216 2217 /* Retain port [i]'s relationship to other ports than [port] */ 2218 for (j = 0; j < ds->num_ports; j++) { 2219 const struct dsa_port *third_dp; 2220 struct ksz_port *third_p; 2221 2222 if (j == i) 2223 continue; 2224 if (j == port) 2225 continue; 2226 if (!dsa_is_user_port(ds, j)) 2227 continue; 2228 third_p = &dev->ports[j]; 2229 if (third_p->stp_state != BR_STATE_FORWARDING) 2230 continue; 2231 2232 third_dp = dsa_to_port(ds, j); 2233 2234 /* Now we updating relation of the "other" port [i] to 2235 * the "third" port [j]. We already know that "other" 2236 * port [i] is in forwarding stp state and that "third" 2237 * port [j] is in forwarding stp state too. 2238 * We need to check if "other" port [i] and "third" port 2239 * [j] are in the same bridge group and not isolated 2240 * before allowing forwarding from port [i] to port [j]. 2241 */ 2242 if (dsa_port_bridge_same(other_dp, third_dp) && 2243 !(other_p->isolated && third_p->isolated)) 2244 val |= BIT(j); 2245 } 2246 2247 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 2248 } 2249 2250 /* HSR ports are setup once so need to use the assigned membership 2251 * when the port is enabled. 2252 */ 2253 if (!port_member && p->stp_state == BR_STATE_FORWARDING && 2254 (dev->hsr_ports & BIT(port))) 2255 port_member = dev->hsr_ports; 2256 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 2257 } 2258 2259 int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 2260 { 2261 struct ksz_device *dev = bus->priv; 2262 struct dsa_switch *ds = dev->ds; 2263 2264 return ds->ops->phy_read(ds, addr, regnum); 2265 } 2266 2267 int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val) 2268 { 2269 struct ksz_device *dev = bus->priv; 2270 struct dsa_switch *ds = dev->ds; 2271 2272 return ds->ops->phy_write(ds, addr, regnum, val); 2273 } 2274 2275 /** 2276 * ksz_parent_mdio_read - Read data from a PHY register on the parent MDIO bus. 2277 * @bus: MDIO bus structure. 2278 * @addr: PHY address on the parent MDIO bus. 2279 * @regnum: Register number to read. 2280 * 2281 * This function provides a direct read operation on the parent MDIO bus for 2282 * accessing PHY registers. By bypassing SPI or I2C, it uses the parent MDIO bus 2283 * to retrieve data from the PHY registers at the specified address and register 2284 * number. 2285 * 2286 * Return: Value of the PHY register, or a negative error code on failure. 2287 */ 2288 int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum) 2289 { 2290 struct ksz_device *dev = bus->priv; 2291 2292 return mdiobus_read_nested(dev->parent_mdio_bus, addr, regnum); 2293 } 2294 2295 /** 2296 * ksz_parent_mdio_write - Write data to a PHY register on the parent MDIO bus. 2297 * @bus: MDIO bus structure. 2298 * @addr: PHY address on the parent MDIO bus. 2299 * @regnum: Register number to write to. 2300 * @val: Value to write to the PHY register. 2301 * 2302 * This function provides a direct write operation on the parent MDIO bus for 2303 * accessing PHY registers. Bypassing SPI or I2C, it uses the parent MDIO bus 2304 * to modify the PHY register values at the specified address. 2305 * 2306 * Return: 0 on success, or a negative error code on failure. 2307 */ 2308 int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val) 2309 { 2310 struct ksz_device *dev = bus->priv; 2311 2312 return mdiobus_write_nested(dev->parent_mdio_bus, addr, regnum, val); 2313 } 2314 2315 /** 2316 * ksz_phy_addr_to_port - Map a PHY address to the corresponding switch port. 2317 * @dev: Pointer to device structure. 2318 * @addr: PHY address to map to a port. 2319 * 2320 * This function finds the corresponding switch port for a given PHY address by 2321 * iterating over all user ports on the device. It checks if a port's PHY 2322 * address in `phy_addr_map` matches the specified address and if the port 2323 * contains an internal PHY. If a match is found, the index of the port is 2324 * returned. 2325 * 2326 * Return: Port index on success, or -EINVAL if no matching port is found. 2327 */ 2328 static int ksz_phy_addr_to_port(struct ksz_device *dev, int addr) 2329 { 2330 struct dsa_switch *ds = dev->ds; 2331 struct dsa_port *dp; 2332 2333 dsa_switch_for_each_user_port(dp, ds) { 2334 if (dev->info->internal_phy[dp->index] && 2335 dev->phy_addr_map[dp->index] == addr) 2336 return dp->index; 2337 } 2338 2339 return -EINVAL; 2340 } 2341 2342 /** 2343 * ksz_irq_phy_setup - Configure IRQs for PHYs in the KSZ device. 2344 * @dev: Pointer to the KSZ device structure. 2345 * 2346 * Sets up IRQs for each active PHY connected to the KSZ switch by mapping the 2347 * appropriate IRQs for each PHY and assigning them to the `user_mii_bus` in 2348 * the DSA switch structure. Each IRQ is mapped based on the port's IRQ domain. 2349 * 2350 * Return: 0 on success, or a negative error code on failure. 2351 */ 2352 static int ksz_irq_phy_setup(struct ksz_device *dev) 2353 { 2354 struct dsa_switch *ds = dev->ds; 2355 int phy, port; 2356 int irq; 2357 int ret; 2358 2359 for (phy = 0; phy < PHY_MAX_ADDR; phy++) { 2360 if (BIT(phy) & ds->phys_mii_mask) { 2361 port = ksz_phy_addr_to_port(dev, phy); 2362 if (port < 0) { 2363 ret = port; 2364 goto out; 2365 } 2366 2367 irq = irq_find_mapping(dev->ports[port].pirq.domain, 2368 PORT_SRC_PHY_INT); 2369 if (!irq) { 2370 ret = -EINVAL; 2371 goto out; 2372 } 2373 ds->user_mii_bus->irq[phy] = irq; 2374 } 2375 } 2376 return 0; 2377 out: 2378 while (phy--) 2379 if (BIT(phy) & ds->phys_mii_mask) 2380 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2381 2382 return ret; 2383 } 2384 2385 /** 2386 * ksz_irq_phy_free - Release IRQ mappings for PHYs in the KSZ device. 2387 * @dev: Pointer to the KSZ device structure. 2388 * 2389 * Releases any IRQ mappings previously assigned to active PHYs in the KSZ 2390 * switch by disposing of each mapped IRQ in the `user_mii_bus` structure. 2391 */ 2392 static void ksz_irq_phy_free(struct ksz_device *dev) 2393 { 2394 struct dsa_switch *ds = dev->ds; 2395 int phy; 2396 2397 for (phy = 0; phy < PHY_MAX_ADDR; phy++) 2398 if (BIT(phy) & ds->phys_mii_mask) 2399 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2400 } 2401 2402 /** 2403 * ksz_parse_dt_phy_config - Parse and validate PHY configuration from DT 2404 * @dev: pointer to the KSZ device structure 2405 * @bus: pointer to the MII bus structure 2406 * @mdio_np: pointer to the MDIO node in the device tree 2407 * 2408 * This function parses and validates PHY configurations for each user port 2409 * defined in the device tree for a KSZ switch device. It verifies that the 2410 * `phy-handle` properties are correctly set and that the internal PHYs match 2411 * expected addresses and parent nodes. Sets up the PHY mask in the MII bus if 2412 * all validations pass. Logs error messages for any mismatches or missing data. 2413 * 2414 * Return: 0 on success, or a negative error code on failure. 2415 */ 2416 int ksz_parse_dt_phy_config(struct ksz_device *dev, struct mii_bus *bus, 2417 struct device_node *mdio_np) 2418 { 2419 struct device_node *phy_node, *phy_parent_node; 2420 bool phys_are_valid = true; 2421 struct dsa_port *dp; 2422 u32 phy_addr; 2423 int ret; 2424 2425 dsa_switch_for_each_user_port(dp, dev->ds) { 2426 if (!dev->info->internal_phy[dp->index]) 2427 continue; 2428 2429 phy_node = of_parse_phandle(dp->dn, "phy-handle", 0); 2430 if (!phy_node) { 2431 dev_err(dev->dev, "failed to parse phy-handle for port %d.\n", 2432 dp->index); 2433 phys_are_valid = false; 2434 continue; 2435 } 2436 2437 phy_parent_node = of_get_parent(phy_node); 2438 if (!phy_parent_node) { 2439 dev_err(dev->dev, "failed to get PHY-parent node for port %d\n", 2440 dp->index); 2441 phys_are_valid = false; 2442 } else if (phy_parent_node != mdio_np) { 2443 dev_err(dev->dev, "PHY-parent node mismatch for port %d, expected %pOF, got %pOF\n", 2444 dp->index, mdio_np, phy_parent_node); 2445 phys_are_valid = false; 2446 } else { 2447 ret = of_property_read_u32(phy_node, "reg", &phy_addr); 2448 if (ret < 0) { 2449 dev_err(dev->dev, "failed to read PHY address for port %d. Error %d\n", 2450 dp->index, ret); 2451 phys_are_valid = false; 2452 } else if (phy_addr != dev->phy_addr_map[dp->index]) { 2453 dev_err(dev->dev, "PHY address mismatch for port %d, expected 0x%x, got 0x%x\n", 2454 dp->index, dev->phy_addr_map[dp->index], 2455 phy_addr); 2456 phys_are_valid = false; 2457 } else { 2458 bus->phy_mask |= BIT(phy_addr); 2459 } 2460 } 2461 2462 of_node_put(phy_node); 2463 of_node_put(phy_parent_node); 2464 } 2465 2466 if (!phys_are_valid) 2467 return -EINVAL; 2468 2469 return 0; 2470 } 2471 2472 /** 2473 * ksz_mdio_register - Register and configure the MDIO bus for the KSZ device. 2474 * @dev: Pointer to the KSZ device structure. 2475 * 2476 * This function sets up and registers an MDIO bus for the KSZ switch device, 2477 * allowing access to its internal PHYs. If the device supports side MDIO, 2478 * the function will configure the external MDIO controller specified by the 2479 * "mdio-parent-bus" device tree property to directly manage internal PHYs. 2480 * Otherwise, SPI or I2C access is set up for PHY access. 2481 * 2482 * Return: 0 on success, or a negative error code on failure. 2483 */ 2484 int ksz_mdio_register(struct ksz_device *dev) 2485 { 2486 struct device_node *parent_bus_node; 2487 struct mii_bus *parent_bus = NULL; 2488 struct dsa_switch *ds = dev->ds; 2489 struct device_node *mdio_np; 2490 struct mii_bus *bus; 2491 int ret, i; 2492 2493 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 2494 if (!mdio_np) 2495 return 0; 2496 2497 parent_bus_node = of_parse_phandle(mdio_np, "mdio-parent-bus", 0); 2498 if (parent_bus_node && !dev->info->phy_side_mdio_supported) { 2499 dev_err(dev->dev, "Side MDIO bus is not supported for this HW, ignoring 'mdio-parent-bus' property.\n"); 2500 ret = -EINVAL; 2501 2502 goto put_mdio_node; 2503 } else if (parent_bus_node) { 2504 parent_bus = of_mdio_find_bus(parent_bus_node); 2505 if (!parent_bus) { 2506 ret = -EPROBE_DEFER; 2507 2508 goto put_mdio_node; 2509 } 2510 2511 dev->parent_mdio_bus = parent_bus; 2512 } 2513 2514 bus = devm_mdiobus_alloc(ds->dev); 2515 if (!bus) { 2516 ret = -ENOMEM; 2517 goto put_mdio_node; 2518 } 2519 2520 for (i = 0; i < dev->info->port_cnt; i++) 2521 dev->phy_addr_map[i] = i; 2522 2523 bus->priv = dev; 2524 if (parent_bus) { 2525 bus->read = ksz_parent_mdio_read; 2526 bus->write = ksz_parent_mdio_write; 2527 bus->name = "KSZ side MDIO"; 2528 snprintf(bus->id, MII_BUS_ID_SIZE, "ksz-side-mdio-%d", 2529 ds->index); 2530 } else { 2531 bus->read = ksz_sw_mdio_read; 2532 bus->write = ksz_sw_mdio_write; 2533 bus->name = "ksz user smi"; 2534 if (ds->dst->index != 0) { 2535 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d-%d", ds->dst->index, ds->index); 2536 } else { 2537 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 2538 } 2539 } 2540 2541 ret = ksz_parse_dt_phy_config(dev, bus, mdio_np); 2542 if (ret) 2543 goto put_mdio_node; 2544 2545 ds->phys_mii_mask = bus->phy_mask; 2546 bus->parent = ds->dev; 2547 2548 ds->user_mii_bus = bus; 2549 2550 if (dev->irq > 0) { 2551 ret = ksz_irq_phy_setup(dev); 2552 if (ret) 2553 goto put_mdio_node; 2554 } 2555 2556 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 2557 if (ret) { 2558 dev_err(ds->dev, "unable to register MDIO bus %s\n", 2559 bus->id); 2560 if (dev->irq > 0) 2561 ksz_irq_phy_free(dev); 2562 } 2563 2564 put_mdio_node: 2565 of_node_put(mdio_np); 2566 of_node_put(parent_bus_node); 2567 2568 return ret; 2569 } 2570 2571 static void ksz_irq_mask(struct irq_data *d) 2572 { 2573 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2574 2575 kirq->masked |= BIT(d->hwirq); 2576 } 2577 2578 static void ksz_irq_unmask(struct irq_data *d) 2579 { 2580 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2581 2582 kirq->masked &= ~BIT(d->hwirq); 2583 } 2584 2585 static void ksz_irq_bus_lock(struct irq_data *d) 2586 { 2587 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2588 2589 mutex_lock(&kirq->dev->lock_irq); 2590 } 2591 2592 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 2593 { 2594 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2595 struct ksz_device *dev = kirq->dev; 2596 int ret; 2597 2598 ret = ksz_write8(dev, kirq->reg_mask, kirq->masked); 2599 if (ret) 2600 dev_err(dev->dev, "failed to change IRQ mask\n"); 2601 2602 mutex_unlock(&dev->lock_irq); 2603 } 2604 2605 static const struct irq_chip ksz_irq_chip = { 2606 .name = "ksz-irq", 2607 .irq_mask = ksz_irq_mask, 2608 .irq_unmask = ksz_irq_unmask, 2609 .irq_bus_lock = ksz_irq_bus_lock, 2610 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 2611 }; 2612 2613 static int ksz_irq_domain_map(struct irq_domain *d, 2614 unsigned int irq, irq_hw_number_t hwirq) 2615 { 2616 irq_set_chip_data(irq, d->host_data); 2617 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 2618 irq_set_noprobe(irq); 2619 2620 return 0; 2621 } 2622 2623 static const struct irq_domain_ops ksz_irq_domain_ops = { 2624 .map = ksz_irq_domain_map, 2625 .xlate = irq_domain_xlate_twocell, 2626 }; 2627 2628 void ksz_irq_free(struct ksz_irq *kirq) 2629 { 2630 int irq, virq; 2631 2632 free_irq(kirq->irq_num, kirq); 2633 2634 for (irq = 0; irq < kirq->nirqs; irq++) { 2635 virq = irq_find_mapping(kirq->domain, irq); 2636 irq_dispose_mapping(virq); 2637 } 2638 2639 irq_domain_remove(kirq->domain); 2640 } 2641 2642 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 2643 { 2644 struct ksz_irq *kirq = dev_id; 2645 unsigned int nhandled = 0; 2646 struct ksz_device *dev; 2647 unsigned int sub_irq; 2648 u8 data; 2649 int ret; 2650 u8 n; 2651 2652 dev = kirq->dev; 2653 2654 /* Read interrupt status register */ 2655 ret = ksz_read8(dev, kirq->reg_status, &data); 2656 if (ret) 2657 goto out; 2658 2659 for (n = 0; n < kirq->nirqs; ++n) { 2660 if (data & BIT(n)) { 2661 sub_irq = irq_find_mapping(kirq->domain, n); 2662 handle_nested_irq(sub_irq); 2663 ++nhandled; 2664 } 2665 } 2666 out: 2667 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2668 } 2669 2670 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 2671 { 2672 int ret, n; 2673 2674 kirq->dev = dev; 2675 2676 kirq->domain = irq_domain_create_simple(dev_fwnode(dev->dev), kirq->nirqs, 0, 2677 &ksz_irq_domain_ops, kirq); 2678 if (!kirq->domain) 2679 return -ENOMEM; 2680 2681 for (n = 0; n < kirq->nirqs; n++) 2682 irq_create_mapping(kirq->domain, n); 2683 2684 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2685 IRQF_ONESHOT, kirq->name, kirq); 2686 if (ret) 2687 goto out; 2688 2689 return 0; 2690 2691 out: 2692 ksz_irq_free(kirq); 2693 2694 return ret; 2695 } 2696 2697 int ksz_girq_setup(struct ksz_device *dev) 2698 { 2699 struct ksz_irq *girq = &dev->girq; 2700 2701 girq->nirqs = dev->info->port_cnt; 2702 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2703 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2704 girq->masked = ~0; 2705 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2706 2707 girq->irq_num = dev->irq; 2708 2709 return ksz_irq_common_setup(dev, girq); 2710 } 2711 2712 int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2713 { 2714 struct ksz_irq *pirq = &dev->ports[p].pirq; 2715 2716 pirq->nirqs = dev->info->port_nirqs; 2717 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2718 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2719 pirq->masked = ~0; 2720 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2721 2722 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2723 if (!pirq->irq_num) 2724 return -EINVAL; 2725 2726 return ksz_irq_common_setup(dev, pirq); 2727 } 2728 2729 void ksz_teardown(struct dsa_switch *ds) 2730 { 2731 struct ksz_device *dev = ds->priv; 2732 struct dsa_port *dp; 2733 2734 if (dev->info->ptp_capable) 2735 ksz_ptp_clock_unregister(ds); 2736 2737 if (dev->irq > 0) { 2738 dsa_switch_for_each_user_port(dp, dev->ds) { 2739 if (dev->info->ptp_capable) 2740 ksz_ptp_irq_free(ds, dp->index); 2741 2742 ksz_irq_free(&dev->ports[dp->index].pirq); 2743 } 2744 2745 ksz_irq_free(&dev->girq); 2746 } 2747 } 2748 2749 static void port_r_cnt(struct ksz_device *dev, int port) 2750 { 2751 struct ksz_port_mib *mib = &dev->ports[port].mib; 2752 u64 *dropped; 2753 2754 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2755 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2756 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2757 &mib->counters[mib->cnt_ptr]); 2758 ++mib->cnt_ptr; 2759 } 2760 2761 /* last one in storage */ 2762 dropped = &mib->counters[dev->info->mib_cnt]; 2763 2764 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2765 while (mib->cnt_ptr < dev->info->mib_cnt) { 2766 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2767 dropped, &mib->counters[mib->cnt_ptr]); 2768 ++mib->cnt_ptr; 2769 } 2770 mib->cnt_ptr = 0; 2771 } 2772 2773 static void ksz_mib_read_work(struct work_struct *work) 2774 { 2775 struct ksz_device *dev = container_of(work, struct ksz_device, 2776 mib_read.work); 2777 struct ksz_port_mib *mib; 2778 struct ksz_port *p; 2779 int i; 2780 2781 for (i = 0; i < dev->info->port_cnt; i++) { 2782 if (dsa_is_unused_port(dev->ds, i)) 2783 continue; 2784 2785 p = &dev->ports[i]; 2786 mib = &p->mib; 2787 mutex_lock(&mib->cnt_mutex); 2788 2789 /* Only read MIB counters when the port is told to do. 2790 * If not, read only dropped counters when link is not up. 2791 */ 2792 if (!p->read) { 2793 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 2794 2795 if (!netif_carrier_ok(dp->user)) 2796 mib->cnt_ptr = dev->info->reg_mib_cnt; 2797 } 2798 port_r_cnt(dev, i); 2799 p->read = false; 2800 2801 if (dev->dev_ops->r_mib_stat64) 2802 dev->dev_ops->r_mib_stat64(dev, i); 2803 2804 mutex_unlock(&mib->cnt_mutex); 2805 } 2806 2807 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 2808 } 2809 2810 void ksz_init_mib_timer(struct ksz_device *dev) 2811 { 2812 int i; 2813 2814 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 2815 2816 for (i = 0; i < dev->info->port_cnt; i++) { 2817 struct ksz_port_mib *mib = &dev->ports[i].mib; 2818 2819 dev->dev_ops->port_init_cnt(dev, i); 2820 2821 mib->cnt_ptr = 0; 2822 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 2823 } 2824 } 2825 2826 void ksz_phylink_mac_link_down(struct phylink_config *config, 2827 unsigned int mode, 2828 phy_interface_t interface) 2829 { 2830 struct dsa_port *dp = dsa_phylink_to_port(config); 2831 struct ksz_device *dev = dp->ds->priv; 2832 2833 /* Read all MIB counters when the link is going down. */ 2834 dev->ports[dp->index].read = true; 2835 /* timer started */ 2836 if (dev->mib_read_interval) 2837 schedule_delayed_work(&dev->mib_read, 0); 2838 } 2839 2840 int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 2841 { 2842 struct ksz_device *dev = ds->priv; 2843 2844 if (sset != ETH_SS_STATS) 2845 return 0; 2846 2847 return dev->info->mib_cnt; 2848 } 2849 2850 void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 2851 uint64_t *buf) 2852 { 2853 const struct dsa_port *dp = dsa_to_port(ds, port); 2854 struct ksz_device *dev = ds->priv; 2855 struct ksz_port_mib *mib; 2856 2857 mib = &dev->ports[port].mib; 2858 mutex_lock(&mib->cnt_mutex); 2859 2860 /* Only read dropped counters if no link. */ 2861 if (!netif_carrier_ok(dp->user)) 2862 mib->cnt_ptr = dev->info->reg_mib_cnt; 2863 port_r_cnt(dev, port); 2864 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 2865 mutex_unlock(&mib->cnt_mutex); 2866 } 2867 2868 int ksz_port_bridge_join(struct dsa_switch *ds, int port, 2869 struct dsa_bridge bridge, 2870 bool *tx_fwd_offload, 2871 struct netlink_ext_ack *extack) 2872 { 2873 /* port_stp_state_set() will be called after to put the port in 2874 * appropriate state so there is no need to do anything. 2875 */ 2876 2877 return 0; 2878 } 2879 2880 void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 2881 struct dsa_bridge bridge) 2882 { 2883 /* port_stp_state_set() will be called after to put the port in 2884 * forwarding state so there is no need to do anything. 2885 */ 2886 } 2887 2888 int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev, int port) 2889 { 2890 u32 queue_map = 0; 2891 int ipm; 2892 2893 for (ipm = 0; ipm < dev->info->num_ipms; ipm++) { 2894 int queue; 2895 2896 /* Traffic Type (TT) is corresponding to the Internal Priority 2897 * Map (IPM) in the switch. Traffic Class (TC) is 2898 * corresponding to the queue in the switch. 2899 */ 2900 queue = ieee8021q_tt_to_tc(ipm, dev->info->num_tx_queues); 2901 if (queue < 0) 2902 return queue; 2903 2904 queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S); 2905 } 2906 2907 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 2908 } 2909 2910 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 2911 { 2912 struct ksz_device *dev = ds->priv; 2913 struct ksz_port *p; 2914 const u16 *regs; 2915 u8 data; 2916 2917 regs = dev->info->regs; 2918 2919 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 2920 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2921 2922 p = &dev->ports[port]; 2923 2924 switch (state) { 2925 case BR_STATE_DISABLED: 2926 data |= PORT_LEARN_DISABLE; 2927 break; 2928 case BR_STATE_LISTENING: 2929 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2930 break; 2931 case BR_STATE_LEARNING: 2932 data |= PORT_RX_ENABLE; 2933 if (!p->learning) 2934 data |= PORT_LEARN_DISABLE; 2935 break; 2936 case BR_STATE_FORWARDING: 2937 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 2938 if (!p->learning) 2939 data |= PORT_LEARN_DISABLE; 2940 break; 2941 case BR_STATE_BLOCKING: 2942 data |= PORT_LEARN_DISABLE; 2943 break; 2944 default: 2945 dev_err(ds->dev, "invalid STP state: %d\n", state); 2946 return; 2947 } 2948 2949 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 2950 2951 p->stp_state = state; 2952 2953 ksz_update_port_member(dev, port); 2954 } 2955 2956 int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 2957 struct switchdev_brport_flags flags, 2958 struct netlink_ext_ack *extack) 2959 { 2960 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED)) 2961 return -EINVAL; 2962 2963 return 0; 2964 } 2965 2966 int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 2967 struct switchdev_brport_flags flags, 2968 struct netlink_ext_ack *extack) 2969 { 2970 struct ksz_device *dev = ds->priv; 2971 struct ksz_port *p = &dev->ports[port]; 2972 2973 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) { 2974 if (flags.mask & BR_LEARNING) 2975 p->learning = !!(flags.val & BR_LEARNING); 2976 2977 if (flags.mask & BR_ISOLATED) 2978 p->isolated = !!(flags.val & BR_ISOLATED); 2979 2980 /* Make the change take effect immediately */ 2981 ksz_port_stp_state_set(ds, port, p->stp_state); 2982 } 2983 2984 return 0; 2985 } 2986 2987 int ksz_max_mtu(struct dsa_switch *ds, int port) 2988 { 2989 struct ksz_device *dev = ds->priv; 2990 2991 switch (dev->chip_id) { 2992 case KSZ8795_CHIP_ID: 2993 case KSZ8794_CHIP_ID: 2994 case KSZ8765_CHIP_ID: 2995 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2996 case KSZ8463_CHIP_ID: 2997 case KSZ88X3_CHIP_ID: 2998 case KSZ8864_CHIP_ID: 2999 case KSZ8895_CHIP_ID: 3000 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3001 case KSZ8563_CHIP_ID: 3002 case KSZ8567_CHIP_ID: 3003 case KSZ9477_CHIP_ID: 3004 case KSZ9563_CHIP_ID: 3005 case KSZ9567_CHIP_ID: 3006 case KSZ9893_CHIP_ID: 3007 case KSZ9896_CHIP_ID: 3008 case KSZ9897_CHIP_ID: 3009 case LAN9370_CHIP_ID: 3010 case LAN9371_CHIP_ID: 3011 case LAN9372_CHIP_ID: 3012 case LAN9373_CHIP_ID: 3013 case LAN9374_CHIP_ID: 3014 case LAN9646_CHIP_ID: 3015 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3016 } 3017 3018 return -EOPNOTSUPP; 3019 } 3020 3021 int ksz_set_mac_eee(struct dsa_switch *ds, int port, 3022 struct ethtool_keee *e) 3023 { 3024 struct ksz_device *dev = ds->priv; 3025 3026 if (!e->tx_lpi_enabled) { 3027 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 3028 return -EINVAL; 3029 } 3030 3031 if (e->tx_lpi_timer) { 3032 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 3033 return -EINVAL; 3034 } 3035 3036 return 0; 3037 } 3038 3039 void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface) 3040 { 3041 const u8 *bitval = dev->info->xmii_ctrl1; 3042 struct ksz_port *p = &dev->ports[port]; 3043 const u16 *regs = dev->info->regs; 3044 u8 data8; 3045 3046 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3047 3048 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 3049 P_RGMII_ID_EG_ENABLE); 3050 3051 switch (interface) { 3052 case PHY_INTERFACE_MODE_MII: 3053 data8 |= bitval[P_MII_SEL]; 3054 break; 3055 case PHY_INTERFACE_MODE_RMII: 3056 data8 |= bitval[P_RMII_SEL]; 3057 break; 3058 case PHY_INTERFACE_MODE_GMII: 3059 data8 |= bitval[P_GMII_SEL]; 3060 break; 3061 case PHY_INTERFACE_MODE_RGMII: 3062 case PHY_INTERFACE_MODE_RGMII_ID: 3063 case PHY_INTERFACE_MODE_RGMII_TXID: 3064 case PHY_INTERFACE_MODE_RGMII_RXID: 3065 data8 |= bitval[P_RGMII_SEL]; 3066 /* On KSZ9893, disable RGMII in-band status support */ 3067 if (dev->chip_id == KSZ9893_CHIP_ID || 3068 dev->chip_id == KSZ8563_CHIP_ID || 3069 dev->chip_id == KSZ9563_CHIP_ID || 3070 is_lan937x(dev)) 3071 data8 &= ~P_MII_MAC_MODE; 3072 break; 3073 default: 3074 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 3075 phy_modes(interface), port); 3076 return; 3077 } 3078 3079 if (p->rgmii_tx_val) 3080 data8 |= P_RGMII_ID_EG_ENABLE; 3081 3082 if (p->rgmii_rx_val) 3083 data8 |= P_RGMII_ID_IG_ENABLE; 3084 3085 /* Write the updated value */ 3086 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3087 } 3088 3089 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 3090 { 3091 const u8 *bitval = dev->info->xmii_ctrl1; 3092 const u16 *regs = dev->info->regs; 3093 phy_interface_t interface; 3094 u8 data8; 3095 u8 val; 3096 3097 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3098 3099 val = FIELD_GET(P_MII_SEL_M, data8); 3100 3101 if (val == bitval[P_MII_SEL]) { 3102 if (gbit) 3103 interface = PHY_INTERFACE_MODE_GMII; 3104 else 3105 interface = PHY_INTERFACE_MODE_MII; 3106 } else if (val == bitval[P_RMII_SEL]) { 3107 interface = PHY_INTERFACE_MODE_RMII; 3108 } else { 3109 interface = PHY_INTERFACE_MODE_RGMII; 3110 if (data8 & P_RGMII_ID_EG_ENABLE) 3111 interface = PHY_INTERFACE_MODE_RGMII_TXID; 3112 if (data8 & P_RGMII_ID_IG_ENABLE) { 3113 interface = PHY_INTERFACE_MODE_RGMII_RXID; 3114 if (data8 & P_RGMII_ID_EG_ENABLE) 3115 interface = PHY_INTERFACE_MODE_RGMII_ID; 3116 } 3117 } 3118 3119 return interface; 3120 } 3121 3122 bool ksz_phylink_need_config(struct phylink_config *config, 3123 unsigned int mode) 3124 { 3125 struct dsa_port *dp = dsa_phylink_to_port(config); 3126 struct ksz_device *dev = dp->ds->priv; 3127 int port = dp->index; 3128 3129 /* Internal PHYs */ 3130 if (dev->info->internal_phy[port]) 3131 return false; 3132 3133 /* No need to configure XMII control register when using SGMII. */ 3134 if (ksz_is_sgmii_port(dev, port)) 3135 return false; 3136 3137 if (phylink_autoneg_inband(mode)) { 3138 dev_err(dev->dev, "In-band AN not supported!\n"); 3139 return false; 3140 } 3141 3142 return true; 3143 } 3144 3145 void ksz_phylink_mac_config(struct phylink_config *config, 3146 unsigned int mode, 3147 const struct phylink_link_state *state) 3148 { 3149 struct dsa_port *dp = dsa_phylink_to_port(config); 3150 struct ksz_device *dev = dp->ds->priv; 3151 int port = dp->index; 3152 3153 if (ksz_phylink_need_config(config, mode)) 3154 ksz_set_xmii(dev, port, state->interface); 3155 } 3156 3157 bool ksz_get_gbit(struct ksz_device *dev, int port) 3158 { 3159 const u8 *bitval = dev->info->xmii_ctrl1; 3160 const u16 *regs = dev->info->regs; 3161 bool gbit = false; 3162 u8 data8; 3163 bool val; 3164 3165 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3166 3167 val = FIELD_GET(P_GMII_1GBIT_M, data8); 3168 3169 if (val == bitval[P_GMII_1GBIT]) 3170 gbit = true; 3171 3172 return gbit; 3173 } 3174 3175 static int ksz_switch_detect(struct ksz_device *dev) 3176 { 3177 u8 id1, id2, id4; 3178 u16 id16; 3179 u32 id32; 3180 int ret; 3181 3182 /* read chip id */ 3183 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 3184 if (ret) 3185 return ret; 3186 3187 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 3188 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 3189 3190 switch (id1) { 3191 case KSZ84_FAMILY_ID: 3192 dev->chip_id = KSZ8463_CHIP_ID; 3193 break; 3194 case KSZ87_FAMILY_ID: 3195 if (id2 == KSZ87_CHIP_ID_95) { 3196 u8 val; 3197 3198 dev->chip_id = KSZ8795_CHIP_ID; 3199 3200 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 3201 if (val & KSZ8_PORT_FIBER_MODE) 3202 dev->chip_id = KSZ8765_CHIP_ID; 3203 } else if (id2 == KSZ87_CHIP_ID_94) { 3204 dev->chip_id = KSZ8794_CHIP_ID; 3205 } else { 3206 return -ENODEV; 3207 } 3208 break; 3209 case KSZ88_FAMILY_ID: 3210 if (id2 == KSZ88_CHIP_ID_63) 3211 dev->chip_id = KSZ88X3_CHIP_ID; 3212 else 3213 return -ENODEV; 3214 break; 3215 case KSZ8895_FAMILY_ID: 3216 if (id2 == KSZ8895_CHIP_ID_95 || 3217 id2 == KSZ8895_CHIP_ID_95R) 3218 dev->chip_id = KSZ8895_CHIP_ID; 3219 else 3220 return -ENODEV; 3221 ret = ksz_read8(dev, REG_KSZ8864_CHIP_ID, &id4); 3222 if (ret) 3223 return ret; 3224 if (id4 & SW_KSZ8864) 3225 dev->chip_id = KSZ8864_CHIP_ID; 3226 break; 3227 default: 3228 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 3229 if (ret) 3230 return ret; 3231 3232 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 3233 id32 &= ~0xFF; 3234 3235 switch (id32) { 3236 case KSZ9477_CHIP_ID: 3237 case KSZ9896_CHIP_ID: 3238 case KSZ9897_CHIP_ID: 3239 case KSZ9567_CHIP_ID: 3240 case KSZ8567_CHIP_ID: 3241 case LAN9370_CHIP_ID: 3242 case LAN9371_CHIP_ID: 3243 case LAN9372_CHIP_ID: 3244 case LAN9373_CHIP_ID: 3245 case LAN9374_CHIP_ID: 3246 3247 /* LAN9646 does not have its own chip id. */ 3248 if (dev->chip_id != LAN9646_CHIP_ID) 3249 dev->chip_id = id32; 3250 break; 3251 case KSZ9893_CHIP_ID: 3252 ret = ksz_read8(dev, REG_CHIP_ID4, 3253 &id4); 3254 if (ret) 3255 return ret; 3256 3257 if (id4 == SKU_ID_KSZ8563) 3258 dev->chip_id = KSZ8563_CHIP_ID; 3259 else if (id4 == SKU_ID_KSZ9563) 3260 dev->chip_id = KSZ9563_CHIP_ID; 3261 else 3262 dev->chip_id = KSZ9893_CHIP_ID; 3263 3264 break; 3265 default: 3266 dev_err(dev->dev, 3267 "unsupported switch detected %x)\n", id32); 3268 return -ENODEV; 3269 } 3270 } 3271 return 0; 3272 } 3273 3274 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 3275 * is converted to Hex-decimal using the successive multiplication method. On 3276 * every step, integer part is taken and decimal part is carry forwarded. 3277 */ 3278 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 3279 { 3280 u32 cinc = 0; 3281 u32 txrate; 3282 u32 rate; 3283 u8 temp; 3284 u8 i; 3285 3286 txrate = idle_slope - send_slope; 3287 3288 if (!txrate) 3289 return -EINVAL; 3290 3291 rate = idle_slope; 3292 3293 /* 24 bit register */ 3294 for (i = 0; i < 6; i++) { 3295 rate = rate * 16; 3296 3297 temp = rate / txrate; 3298 3299 rate %= txrate; 3300 3301 cinc = ((cinc << 4) | temp); 3302 } 3303 3304 *bw = cinc; 3305 3306 return 0; 3307 } 3308 3309 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 3310 u8 shaper) 3311 { 3312 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 3313 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 3314 FIELD_PREP(MTI_SHAPING_M, shaper)); 3315 } 3316 3317 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 3318 struct tc_cbs_qopt_offload *qopt) 3319 { 3320 struct ksz_device *dev = ds->priv; 3321 int ret; 3322 u32 bw; 3323 3324 if (!dev->info->tc_cbs_supported) 3325 return -EOPNOTSUPP; 3326 3327 if (qopt->queue > dev->info->num_tx_queues) 3328 return -EINVAL; 3329 3330 /* Queue Selection */ 3331 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 3332 if (ret) 3333 return ret; 3334 3335 if (!qopt->enable) 3336 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3337 MTI_SHAPING_OFF); 3338 3339 /* High Credit */ 3340 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 3341 qopt->hicredit); 3342 if (ret) 3343 return ret; 3344 3345 /* Low Credit */ 3346 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 3347 qopt->locredit); 3348 if (ret) 3349 return ret; 3350 3351 /* Credit Increment Register */ 3352 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 3353 if (ret) 3354 return ret; 3355 3356 if (dev->dev_ops->tc_cbs_set_cinc) { 3357 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 3358 if (ret) 3359 return ret; 3360 } 3361 3362 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3363 MTI_SHAPING_SRP); 3364 } 3365 3366 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 3367 { 3368 int queue, ret; 3369 3370 /* Configuration will not take effect until the last Port Queue X 3371 * Egress Limit Control Register is written. 3372 */ 3373 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3374 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 3375 KSZ9477_OUT_RATE_NO_LIMIT); 3376 if (ret) 3377 return ret; 3378 } 3379 3380 return 0; 3381 } 3382 3383 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 3384 int band) 3385 { 3386 /* Compared to queues, bands prioritize packets differently. In strict 3387 * priority mode, the lowest priority is assigned to Queue 0 while the 3388 * highest priority is given to Band 0. 3389 */ 3390 return p->bands - 1 - band; 3391 } 3392 3393 static u8 ksz8463_tc_ctrl(int port, int queue) 3394 { 3395 u8 reg; 3396 3397 reg = 0xC8 + port * 4; 3398 reg += ((3 - queue) / 2) * 2; 3399 reg++; 3400 reg -= (queue & 1); 3401 return reg; 3402 } 3403 3404 /** 3405 * ksz88x3_tc_ets_add - Configure ETS (Enhanced Transmission Selection) 3406 * for a port on KSZ88x3 switch 3407 * @dev: Pointer to the KSZ switch device structure 3408 * @port: Port number to configure 3409 * @p: Pointer to offload replace parameters describing ETS bands and mapping 3410 * 3411 * The KSZ88x3 supports two scheduling modes: Strict Priority and 3412 * Weighted Fair Queuing (WFQ). Both modes have fixed behavior: 3413 * - No configurable queue-to-priority mapping 3414 * - No weight adjustment in WFQ mode 3415 * 3416 * This function configures the switch to use strict priority mode by 3417 * clearing the WFQ enable bit for all queues associated with ETS bands. 3418 * If strict priority is not explicitly requested, the switch will default 3419 * to WFQ mode. 3420 * 3421 * Return: 0 on success, or a negative error code on failure 3422 */ 3423 static int ksz88x3_tc_ets_add(struct ksz_device *dev, int port, 3424 struct tc_ets_qopt_offload_replace_params *p) 3425 { 3426 int ret, band; 3427 3428 /* Only strict priority mode is supported for now. 3429 * WFQ is implicitly enabled when strict mode is disabled. 3430 */ 3431 for (band = 0; band < p->bands; band++) { 3432 int queue = ksz_ets_band_to_queue(p, band); 3433 u8 reg; 3434 3435 /* Calculate TXQ Split Control register address for this 3436 * port/queue 3437 */ 3438 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue); 3439 if (ksz_is_ksz8463(dev)) 3440 reg = ksz8463_tc_ctrl(port, queue); 3441 3442 /* Clear WFQ enable bit to select strict priority scheduling */ 3443 ret = ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE, 0); 3444 if (ret) 3445 return ret; 3446 } 3447 3448 return 0; 3449 } 3450 3451 /** 3452 * ksz88x3_tc_ets_del - Reset ETS (Enhanced Transmission Selection) config 3453 * for a port on KSZ88x3 switch 3454 * @dev: Pointer to the KSZ switch device structure 3455 * @port: Port number to reset 3456 * 3457 * The KSZ88x3 supports only fixed scheduling modes: Strict Priority or 3458 * Weighted Fair Queuing (WFQ), with no reconfiguration of weights or 3459 * queue mapping. This function resets the port’s scheduling mode to 3460 * the default, which is WFQ, by enabling the WFQ bit for all queues. 3461 * 3462 * Return: 0 on success, or a negative error code on failure 3463 */ 3464 static int ksz88x3_tc_ets_del(struct ksz_device *dev, int port) 3465 { 3466 int ret, queue; 3467 3468 /* Iterate over all transmit queues for this port */ 3469 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3470 u8 reg; 3471 3472 /* Calculate TXQ Split Control register address for this 3473 * port/queue 3474 */ 3475 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue); 3476 if (ksz_is_ksz8463(dev)) 3477 reg = ksz8463_tc_ctrl(port, queue); 3478 3479 /* Set WFQ enable bit to revert back to default scheduling 3480 * mode 3481 */ 3482 ret = ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE, 3483 KSZ8873_TXQ_WFQ_ENABLE); 3484 if (ret) 3485 return ret; 3486 } 3487 3488 return 0; 3489 } 3490 3491 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 3492 { 3493 int ret; 3494 3495 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3496 if (ret) 3497 return ret; 3498 3499 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3500 MTI_SHAPING_OFF); 3501 } 3502 3503 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 3504 int weight) 3505 { 3506 int ret; 3507 3508 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3509 if (ret) 3510 return ret; 3511 3512 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3513 MTI_SHAPING_OFF); 3514 if (ret) 3515 return ret; 3516 3517 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 3518 } 3519 3520 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 3521 struct tc_ets_qopt_offload_replace_params *p) 3522 { 3523 int ret, band, tc_prio; 3524 u32 queue_map = 0; 3525 3526 /* In order to ensure proper prioritization, it is necessary to set the 3527 * rate limit for the related queue to zero. Otherwise strict priority 3528 * or WRR mode will not work. This is a hardware limitation. 3529 */ 3530 ret = ksz_disable_egress_rate_limit(dev, port); 3531 if (ret) 3532 return ret; 3533 3534 /* Configure queue scheduling mode for all bands. Currently only strict 3535 * prio mode is supported. 3536 */ 3537 for (band = 0; band < p->bands; band++) { 3538 int queue = ksz_ets_band_to_queue(p, band); 3539 3540 ret = ksz_queue_set_strict(dev, port, queue); 3541 if (ret) 3542 return ret; 3543 } 3544 3545 /* Configure the mapping between traffic classes and queues. Note: 3546 * priomap variable support 16 traffic classes, but the chip can handle 3547 * only 8 classes. 3548 */ 3549 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 3550 int queue; 3551 3552 if (tc_prio >= dev->info->num_ipms) 3553 break; 3554 3555 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 3556 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3557 } 3558 3559 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3560 } 3561 3562 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 3563 { 3564 int ret, queue; 3565 3566 /* To restore the default chip configuration, set all queues to use the 3567 * WRR scheduler with a weight of 1. 3568 */ 3569 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3570 ret = ksz_queue_set_wrr(dev, port, queue, 3571 KSZ9477_DEFAULT_WRR_WEIGHT); 3572 3573 if (ret) 3574 return ret; 3575 } 3576 3577 /* Revert the queue mapping for TC-priority to its default setting on 3578 * the chip. 3579 */ 3580 return ksz9477_set_default_prio_queue_mapping(dev, port); 3581 } 3582 3583 static int ksz_tc_ets_validate(struct ksz_device *dev, int port, 3584 struct tc_ets_qopt_offload_replace_params *p) 3585 { 3586 int band; 3587 3588 /* Since it is not feasible to share one port among multiple qdisc, 3589 * the user must configure all available queues appropriately. 3590 */ 3591 if (p->bands != dev->info->num_tx_queues) { 3592 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 3593 dev->info->num_tx_queues); 3594 return -EOPNOTSUPP; 3595 } 3596 3597 for (band = 0; band < p->bands; ++band) { 3598 /* The KSZ switches utilize a weighted round robin configuration 3599 * where a certain number of packets can be transmitted from a 3600 * queue before the next queue is serviced. For more information 3601 * on this, refer to section 5.2.8.4 of the KSZ8565R 3602 * documentation on the Port Transmit Queue Control 1 Register. 3603 * However, the current ETS Qdisc implementation (as of February 3604 * 2023) assigns a weight to each queue based on the number of 3605 * bytes or extrapolated bandwidth in percentages. Since this 3606 * differs from the KSZ switches' method and we don't want to 3607 * fake support by converting bytes to packets, it is better to 3608 * return an error instead. 3609 */ 3610 if (p->quanta[band]) { 3611 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 3612 return -EOPNOTSUPP; 3613 } 3614 } 3615 3616 return 0; 3617 } 3618 3619 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 3620 struct tc_ets_qopt_offload *qopt) 3621 { 3622 struct ksz_device *dev = ds->priv; 3623 int ret; 3624 3625 if (is_ksz8(dev) && !(ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev))) 3626 return -EOPNOTSUPP; 3627 3628 if (qopt->parent != TC_H_ROOT) { 3629 dev_err(dev->dev, "Parent should be \"root\"\n"); 3630 return -EOPNOTSUPP; 3631 } 3632 3633 switch (qopt->command) { 3634 case TC_ETS_REPLACE: 3635 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 3636 if (ret) 3637 return ret; 3638 3639 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 3640 return ksz88x3_tc_ets_add(dev, port, 3641 &qopt->replace_params); 3642 else 3643 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 3644 case TC_ETS_DESTROY: 3645 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 3646 return ksz88x3_tc_ets_del(dev, port); 3647 else 3648 return ksz_tc_ets_del(dev, port); 3649 case TC_ETS_STATS: 3650 case TC_ETS_GRAFT: 3651 return -EOPNOTSUPP; 3652 } 3653 3654 return -EOPNOTSUPP; 3655 } 3656 3657 int ksz_setup_tc(struct dsa_switch *ds, int port, 3658 enum tc_setup_type type, void *type_data) 3659 { 3660 switch (type) { 3661 case TC_SETUP_QDISC_CBS: 3662 return ksz_setup_tc_cbs(ds, port, type_data); 3663 case TC_SETUP_QDISC_ETS: 3664 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 3665 default: 3666 return -EOPNOTSUPP; 3667 } 3668 } 3669 3670 /** 3671 * ksz_handle_wake_reason - Handle wake reason on a specified port. 3672 * @dev: The device structure. 3673 * @port: The port number. 3674 * 3675 * This function reads the PME (Power Management Event) status register of a 3676 * specified port to determine the wake reason. If there is no wake event, it 3677 * returns early. Otherwise, it logs the wake reason which could be due to a 3678 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register 3679 * is then cleared to acknowledge the handling of the wake event. 3680 * 3681 * Return: 0 on success, or an error code on failure. 3682 */ 3683 int ksz_handle_wake_reason(struct ksz_device *dev, int port) 3684 { 3685 const struct ksz_dev_ops *ops = dev->dev_ops; 3686 const u16 *regs = dev->info->regs; 3687 u8 pme_status; 3688 int ret; 3689 3690 ret = ops->pme_pread8(dev, port, regs[REG_PORT_PME_STATUS], 3691 &pme_status); 3692 if (ret) 3693 return ret; 3694 3695 if (!pme_status) 3696 return 0; 3697 3698 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port, 3699 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "", 3700 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "", 3701 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : ""); 3702 3703 return ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_STATUS], 3704 pme_status); 3705 } 3706 3707 /** 3708 * ksz_get_wol - Get Wake-on-LAN settings for a specified port. 3709 * @ds: The dsa_switch structure. 3710 * @port: The port number. 3711 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 3712 * 3713 * This function checks the device PME wakeup_source flag and chip_id. 3714 * If enabled and supported, it sets the supported and active WoL 3715 * flags. 3716 */ 3717 void ksz_get_wol(struct dsa_switch *ds, int port, 3718 struct ethtool_wolinfo *wol) 3719 { 3720 struct ksz_device *dev = ds->priv; 3721 const u16 *regs = dev->info->regs; 3722 u8 pme_ctrl; 3723 int ret; 3724 3725 if (!dev->wakeup_source) 3726 return; 3727 3728 wol->supported = WAKE_PHY; 3729 3730 /* Check if the current MAC address on this port can be set 3731 * as global for WAKE_MAGIC support. The result may vary 3732 * dynamically based on other ports configurations. 3733 */ 3734 if (ksz_is_port_mac_global_usable(dev->ds, port)) 3735 wol->supported |= WAKE_MAGIC; 3736 3737 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 3738 &pme_ctrl); 3739 if (ret) 3740 return; 3741 3742 if (pme_ctrl & PME_WOL_MAGICPKT) 3743 wol->wolopts |= WAKE_MAGIC; 3744 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY)) 3745 wol->wolopts |= WAKE_PHY; 3746 } 3747 3748 /** 3749 * ksz_set_wol - Set Wake-on-LAN settings for a specified port. 3750 * @ds: The dsa_switch structure. 3751 * @port: The port number. 3752 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 3753 * 3754 * This function configures Wake-on-LAN (WoL) settings for a specified 3755 * port. It validates the provided WoL options, checks if PME is 3756 * enabled and supported, clears any previous wake reasons, and sets 3757 * the Magic Packet flag in the port's PME control register if 3758 * specified. 3759 * 3760 * Return: 0 on success, or other error codes on failure. 3761 */ 3762 int ksz_set_wol(struct dsa_switch *ds, int port, 3763 struct ethtool_wolinfo *wol) 3764 { 3765 u8 pme_ctrl = 0, pme_ctrl_old = 0; 3766 struct ksz_device *dev = ds->priv; 3767 const u16 *regs = dev->info->regs; 3768 bool magic_switched_off; 3769 bool magic_switched_on; 3770 int ret; 3771 3772 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC)) 3773 return -EINVAL; 3774 3775 if (!dev->wakeup_source) 3776 return -EOPNOTSUPP; 3777 3778 ret = ksz_handle_wake_reason(dev, port); 3779 if (ret) 3780 return ret; 3781 3782 if (wol->wolopts & WAKE_MAGIC) 3783 pme_ctrl |= PME_WOL_MAGICPKT; 3784 if (wol->wolopts & WAKE_PHY) 3785 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY; 3786 3787 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 3788 &pme_ctrl_old); 3789 if (ret) 3790 return ret; 3791 3792 if (pme_ctrl_old == pme_ctrl) 3793 return 0; 3794 3795 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) && 3796 !(pme_ctrl & PME_WOL_MAGICPKT); 3797 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) && 3798 (pme_ctrl & PME_WOL_MAGICPKT); 3799 3800 /* To keep reference count of MAC address, we should do this 3801 * operation only on change of WOL settings. 3802 */ 3803 if (magic_switched_on) { 3804 ret = ksz_switch_macaddr_get(dev->ds, port, NULL); 3805 if (ret) 3806 return ret; 3807 } else if (magic_switched_off) { 3808 ksz_switch_macaddr_put(dev->ds); 3809 } 3810 3811 ret = dev->dev_ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 3812 pme_ctrl); 3813 if (ret) { 3814 if (magic_switched_on) 3815 ksz_switch_macaddr_put(dev->ds); 3816 return ret; 3817 } 3818 3819 return 0; 3820 } 3821 3822 /** 3823 * ksz_wol_pre_shutdown - Prepares the switch device for shutdown while 3824 * considering Wake-on-LAN (WoL) settings. 3825 * @dev: The switch device structure. 3826 * 3827 * This function prepares the switch device for a safe shutdown while taking 3828 * into account the Wake-on-LAN (WoL) settings on the user ports. 3829 */ 3830 static void ksz_wol_pre_shutdown(struct ksz_device *dev) 3831 { 3832 const struct ksz_dev_ops *ops = dev->dev_ops; 3833 const u16 *regs = dev->info->regs; 3834 struct dsa_switch *ds = dev->ds; 3835 u8 pme_pin_en = PME_ENABLE; 3836 bool wol_enabled = false; 3837 struct dsa_port *dp; 3838 int ret; 3839 3840 if (!ds->ops->set_wol) 3841 return; 3842 3843 if (!dev->wakeup_source) 3844 return; 3845 3846 dsa_switch_for_each_user_port(dp, dev->ds) { 3847 u8 pme_ctrl = 0; 3848 3849 ret = ops->pme_pread8(dev, dp->index, 3850 regs[REG_PORT_PME_CTRL], &pme_ctrl); 3851 if (!ret && pme_ctrl) 3852 wol_enabled = true; 3853 3854 /* make sure there are no pending wake events which would 3855 * prevent the device from going to sleep/shutdown. 3856 */ 3857 ksz_handle_wake_reason(dev, dp->index); 3858 } 3859 3860 /* Now we are save to enable PME pin. */ 3861 if (wol_enabled) { 3862 if (dev->pme_active_high) 3863 pme_pin_en |= PME_POLARITY; 3864 ops->pme_write8(dev, regs[REG_SW_PME_CTRL], pme_pin_en); 3865 if (ksz_is_ksz87xx(dev)) 3866 ksz_write8(dev, KSZ87XX_REG_INT_EN, KSZ87XX_INT_PME_MASK); 3867 } 3868 } 3869 3870 int ksz_port_set_mac_address(struct dsa_switch *ds, int port, 3871 const unsigned char *addr) 3872 { 3873 struct dsa_port *dp = dsa_to_port(ds, port); 3874 struct ethtool_wolinfo wol; 3875 3876 if (dp->hsr_dev) { 3877 dev_err(ds->dev, 3878 "Cannot change MAC address on port %d with active HSR offload\n", 3879 port); 3880 return -EBUSY; 3881 } 3882 3883 /* Need to initialize variable as the code to fill in settings may 3884 * not be executed. 3885 */ 3886 wol.wolopts = 0; 3887 3888 if (ds->ops->get_wol) 3889 ds->ops->get_wol(ds, dp->index, &wol); 3890 if (wol.wolopts & WAKE_MAGIC) { 3891 dev_err(ds->dev, 3892 "Cannot change MAC address on port %d with active Wake on Magic Packet\n", 3893 port); 3894 return -EBUSY; 3895 } 3896 3897 return 0; 3898 } 3899 3900 /** 3901 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port 3902 * can be used as a global address. 3903 * @ds: Pointer to the DSA switch structure. 3904 * @port: The port number on which the MAC address is to be checked. 3905 * 3906 * This function examines the MAC address set on the specified port and 3907 * determines if it can be used as a global address for the switch. 3908 * 3909 * Return: true if the port's MAC address can be used as a global address, false 3910 * otherwise. 3911 */ 3912 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port) 3913 { 3914 struct net_device *user = dsa_to_port(ds, port)->user; 3915 const unsigned char *addr = user->dev_addr; 3916 struct ksz_switch_macaddr *switch_macaddr; 3917 struct ksz_device *dev = ds->priv; 3918 3919 ASSERT_RTNL(); 3920 3921 switch_macaddr = dev->switch_macaddr; 3922 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr)) 3923 return false; 3924 3925 return true; 3926 } 3927 3928 /** 3929 * ksz_switch_macaddr_get - Program the switch's MAC address register. 3930 * @ds: DSA switch instance. 3931 * @port: Port number. 3932 * @extack: Netlink extended acknowledgment. 3933 * 3934 * This function programs the switch's MAC address register with the MAC address 3935 * of the requesting user port. This single address is used by the switch for 3936 * multiple features like HSR self-address filtering and WoL. Other user ports 3937 * can share ownership of this address as long as their MAC address is the same. 3938 * The MAC addresses of user ports must not change while they have ownership of 3939 * the switch MAC address. 3940 * 3941 * Return: 0 on success, or other error codes on failure. 3942 */ 3943 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 3944 struct netlink_ext_ack *extack) 3945 { 3946 struct net_device *user = dsa_to_port(ds, port)->user; 3947 const unsigned char *addr = user->dev_addr; 3948 struct ksz_switch_macaddr *switch_macaddr; 3949 struct ksz_device *dev = ds->priv; 3950 const u16 *regs = dev->info->regs; 3951 int i, ret; 3952 3953 /* Make sure concurrent MAC address changes are blocked */ 3954 ASSERT_RTNL(); 3955 3956 switch_macaddr = dev->switch_macaddr; 3957 if (switch_macaddr) { 3958 if (!ether_addr_equal(switch_macaddr->addr, addr)) { 3959 NL_SET_ERR_MSG_FMT_MOD(extack, 3960 "Switch already configured for MAC address %pM", 3961 switch_macaddr->addr); 3962 return -EBUSY; 3963 } 3964 3965 refcount_inc(&switch_macaddr->refcount); 3966 return 0; 3967 } 3968 3969 switch_macaddr = kzalloc_obj(*switch_macaddr); 3970 if (!switch_macaddr) 3971 return -ENOMEM; 3972 3973 ether_addr_copy(switch_macaddr->addr, addr); 3974 refcount_set(&switch_macaddr->refcount, 1); 3975 dev->switch_macaddr = switch_macaddr; 3976 3977 /* Program the switch MAC address to hardware */ 3978 for (i = 0; i < ETH_ALEN; i++) { 3979 if (ksz_is_ksz8463(dev)) { 3980 u16 addr16 = ((u16)addr[i] << 8) | addr[i + 1]; 3981 3982 ret = ksz_write16(dev, regs[REG_SW_MAC_ADDR] + i, 3983 addr16); 3984 i++; 3985 } else { 3986 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 3987 addr[i]); 3988 } 3989 if (ret) 3990 goto macaddr_drop; 3991 } 3992 3993 return 0; 3994 3995 macaddr_drop: 3996 dev->switch_macaddr = NULL; 3997 refcount_set(&switch_macaddr->refcount, 0); 3998 kfree(switch_macaddr); 3999 4000 return ret; 4001 } 4002 4003 void ksz_switch_macaddr_put(struct dsa_switch *ds) 4004 { 4005 struct ksz_switch_macaddr *switch_macaddr; 4006 struct ksz_device *dev = ds->priv; 4007 const u16 *regs = dev->info->regs; 4008 int i; 4009 4010 /* Make sure concurrent MAC address changes are blocked */ 4011 ASSERT_RTNL(); 4012 4013 switch_macaddr = dev->switch_macaddr; 4014 if (!refcount_dec_and_test(&switch_macaddr->refcount)) 4015 return; 4016 4017 for (i = 0; i < ETH_ALEN; i++) 4018 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0); 4019 4020 dev->switch_macaddr = NULL; 4021 kfree(switch_macaddr); 4022 } 4023 4024 int ksz_suspend(struct dsa_switch *ds) 4025 { 4026 struct ksz_device *dev = ds->priv; 4027 4028 cancel_delayed_work_sync(&dev->mib_read); 4029 return 0; 4030 } 4031 4032 int ksz_resume(struct dsa_switch *ds) 4033 { 4034 struct ksz_device *dev = ds->priv; 4035 4036 if (dev->mib_read_interval) 4037 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 4038 return 0; 4039 } 4040 4041 struct ksz_device *ksz_switch_alloc(struct device *base, 4042 const struct ksz_chip_data *chip, 4043 void *priv) 4044 { 4045 struct dsa_switch *ds; 4046 struct ksz_device *swdev; 4047 4048 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 4049 if (!ds) 4050 return NULL; 4051 4052 ds->dev = base; 4053 ds->num_ports = DSA_MAX_PORTS; 4054 ds->ops = chip->switch_ops; 4055 4056 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 4057 if (!swdev) 4058 return NULL; 4059 4060 ds->priv = swdev; 4061 swdev->dev = base; 4062 4063 swdev->ds = ds; 4064 swdev->priv = priv; 4065 4066 return swdev; 4067 } 4068 EXPORT_SYMBOL(ksz_switch_alloc); 4069 4070 /** 4071 * ksz_switch_shutdown - Shutdown routine for the switch device. 4072 * @dev: The switch device structure. 4073 * 4074 * This function is responsible for initiating a shutdown sequence for the 4075 * switch device. Subsequently, it calls the DSA framework's shutdown function 4076 * to ensure a proper shutdown of the DSA switch. 4077 */ 4078 void ksz_switch_shutdown(struct ksz_device *dev) 4079 { 4080 ksz_wol_pre_shutdown(dev); 4081 dsa_switch_shutdown(dev->ds); 4082 } 4083 EXPORT_SYMBOL(ksz_switch_shutdown); 4084 4085 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 4086 struct device_node *port_dn) 4087 { 4088 phy_interface_t phy_mode = dev->ports[port_num].interface; 4089 int rx_delay = -1, tx_delay = -1; 4090 4091 if (!phy_interface_mode_is_rgmii(phy_mode)) 4092 return; 4093 4094 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 4095 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 4096 4097 if (rx_delay == -1 && tx_delay == -1) { 4098 dev_warn(dev->dev, 4099 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 4100 "please update device tree to specify \"rx-internal-delay-ps\" and " 4101 "\"tx-internal-delay-ps\"", 4102 port_num); 4103 4104 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 4105 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 4106 rx_delay = 2000; 4107 4108 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 4109 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 4110 tx_delay = 2000; 4111 } 4112 4113 if (rx_delay < 0) 4114 rx_delay = 0; 4115 if (tx_delay < 0) 4116 tx_delay = 0; 4117 4118 dev->ports[port_num].rgmii_rx_val = rx_delay; 4119 dev->ports[port_num].rgmii_tx_val = tx_delay; 4120 } 4121 4122 /** 4123 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding 4124 * register value. 4125 * @array: The array of drive strength values to search. 4126 * @array_size: The size of the array. 4127 * @microamp: The drive strength value in microamp to be converted. 4128 * 4129 * This function searches the array of drive strength values for the given 4130 * microamp value and returns the corresponding register value for that drive. 4131 * 4132 * Returns: If found, the corresponding register value for that drive strength 4133 * is returned. Otherwise, -EINVAL is returned indicating an invalid value. 4134 */ 4135 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array, 4136 size_t array_size, int microamp) 4137 { 4138 int i; 4139 4140 for (i = 0; i < array_size; i++) { 4141 if (array[i].microamp == microamp) 4142 return array[i].reg_val; 4143 } 4144 4145 return -EINVAL; 4146 } 4147 4148 /** 4149 * ksz_drive_strength_error() - Report invalid drive strength value 4150 * @dev: ksz device 4151 * @array: The array of drive strength values to search. 4152 * @array_size: The size of the array. 4153 * @microamp: Invalid drive strength value in microamp 4154 * 4155 * This function logs an error message when an unsupported drive strength value 4156 * is detected. It lists out all the supported drive strength values for 4157 * reference in the error message. 4158 */ 4159 static void ksz_drive_strength_error(struct ksz_device *dev, 4160 const struct ksz_drive_strength *array, 4161 size_t array_size, int microamp) 4162 { 4163 char supported_values[100]; 4164 size_t remaining_size; 4165 int added_len; 4166 char *ptr; 4167 int i; 4168 4169 remaining_size = sizeof(supported_values); 4170 ptr = supported_values; 4171 4172 for (i = 0; i < array_size; i++) { 4173 added_len = snprintf(ptr, remaining_size, 4174 i == 0 ? "%d" : ", %d", array[i].microamp); 4175 4176 if (added_len >= remaining_size) 4177 break; 4178 4179 ptr += added_len; 4180 remaining_size -= added_len; 4181 } 4182 4183 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n", 4184 microamp, supported_values); 4185 } 4186 4187 /** 4188 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477 4189 * chip variants. 4190 * @dev: ksz device 4191 * @props: Array of drive strength properties to be applied 4192 * @num_props: Number of properties in the array 4193 * 4194 * This function configures the drive strength for various KSZ9477 chip variants 4195 * based on the provided properties. It handles chip-specific nuances and 4196 * ensures only valid drive strengths are written to the respective chip. 4197 * 4198 * Return: 0 on successful configuration, a negative error code on failure. 4199 */ 4200 static int ksz9477_drive_strength_write(struct ksz_device *dev, 4201 struct ksz_driver_strength_prop *props, 4202 int num_props) 4203 { 4204 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths); 4205 int i, ret, reg; 4206 u8 mask = 0; 4207 u8 val = 0; 4208 4209 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1) 4210 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4211 props[KSZ_DRIVER_STRENGTH_IO].name); 4212 4213 if (dev->chip_id == KSZ8795_CHIP_ID || 4214 dev->chip_id == KSZ8794_CHIP_ID || 4215 dev->chip_id == KSZ8765_CHIP_ID) 4216 reg = KSZ8795_REG_SW_CTRL_20; 4217 else 4218 reg = KSZ9477_REG_SW_IO_STRENGTH; 4219 4220 for (i = 0; i < num_props; i++) { 4221 if (props[i].value == -1) 4222 continue; 4223 4224 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths, 4225 array_size, props[i].value); 4226 if (ret < 0) { 4227 ksz_drive_strength_error(dev, ksz9477_drive_strengths, 4228 array_size, props[i].value); 4229 return ret; 4230 } 4231 4232 mask |= SW_DRIVE_STRENGTH_M << props[i].offset; 4233 val |= ret << props[i].offset; 4234 } 4235 4236 return ksz_rmw8(dev, reg, mask, val); 4237 } 4238 4239 /** 4240 * ksz88x3_drive_strength_write() - Set the drive strength configuration for 4241 * KSZ8863 compatible chip variants. 4242 * @dev: ksz device 4243 * @props: Array of drive strength properties to be set 4244 * @num_props: Number of properties in the array 4245 * 4246 * This function applies the specified drive strength settings to KSZ88X3 chip 4247 * variants (KSZ8873, KSZ8863). 4248 * It ensures the configurations align with what the chip variant supports and 4249 * warns or errors out on unsupported settings. 4250 * 4251 * Return: 0 on success, error code otherwise 4252 */ 4253 static int ksz88x3_drive_strength_write(struct ksz_device *dev, 4254 struct ksz_driver_strength_prop *props, 4255 int num_props) 4256 { 4257 size_t array_size = ARRAY_SIZE(ksz88x3_drive_strengths); 4258 int microamp; 4259 int i, ret; 4260 4261 for (i = 0; i < num_props; i++) { 4262 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO) 4263 continue; 4264 4265 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4266 props[i].name); 4267 } 4268 4269 microamp = props[KSZ_DRIVER_STRENGTH_IO].value; 4270 ret = ksz_drive_strength_to_reg(ksz88x3_drive_strengths, array_size, 4271 microamp); 4272 if (ret < 0) { 4273 ksz_drive_strength_error(dev, ksz88x3_drive_strengths, 4274 array_size, microamp); 4275 return ret; 4276 } 4277 4278 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12, 4279 KSZ8873_DRIVE_STRENGTH_16MA, ret); 4280 } 4281 4282 /** 4283 * ksz_parse_drive_strength() - Extract and apply drive strength configurations 4284 * from device tree properties. 4285 * @dev: ksz device 4286 * 4287 * This function reads the specified drive strength properties from the 4288 * device tree, validates against the supported chip variants, and sets 4289 * them accordingly. An error should be critical here, as the drive strength 4290 * settings are crucial for EMI compliance. 4291 * 4292 * Return: 0 on success, error code otherwise 4293 */ 4294 int ksz_parse_drive_strength(struct ksz_device *dev) 4295 { 4296 struct ksz_driver_strength_prop of_props[] = { 4297 [KSZ_DRIVER_STRENGTH_HI] = { 4298 .name = "microchip,hi-drive-strength-microamp", 4299 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S, 4300 .value = -1, 4301 }, 4302 [KSZ_DRIVER_STRENGTH_LO] = { 4303 .name = "microchip,lo-drive-strength-microamp", 4304 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S, 4305 .value = -1, 4306 }, 4307 [KSZ_DRIVER_STRENGTH_IO] = { 4308 .name = "microchip,io-drive-strength-microamp", 4309 .offset = 0, /* don't care */ 4310 .value = -1, 4311 }, 4312 }; 4313 struct device_node *np = dev->dev->of_node; 4314 bool have_any_prop = false; 4315 int i, ret; 4316 4317 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4318 ret = of_property_read_u32(np, of_props[i].name, 4319 &of_props[i].value); 4320 if (ret && ret != -EINVAL) 4321 dev_warn(dev->dev, "Failed to read %s\n", 4322 of_props[i].name); 4323 if (ret) 4324 continue; 4325 4326 have_any_prop = true; 4327 } 4328 4329 if (!have_any_prop) 4330 return 0; 4331 4332 switch (dev->chip_id) { 4333 case KSZ88X3_CHIP_ID: 4334 return ksz88x3_drive_strength_write(dev, of_props, 4335 ARRAY_SIZE(of_props)); 4336 case KSZ8795_CHIP_ID: 4337 case KSZ8794_CHIP_ID: 4338 case KSZ8765_CHIP_ID: 4339 case KSZ8563_CHIP_ID: 4340 case KSZ8567_CHIP_ID: 4341 case KSZ9477_CHIP_ID: 4342 case KSZ9563_CHIP_ID: 4343 case KSZ9567_CHIP_ID: 4344 case KSZ9893_CHIP_ID: 4345 case KSZ9896_CHIP_ID: 4346 case KSZ9897_CHIP_ID: 4347 case LAN9646_CHIP_ID: 4348 return ksz9477_drive_strength_write(dev, of_props, 4349 ARRAY_SIZE(of_props)); 4350 default: 4351 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4352 if (of_props[i].value == -1) 4353 continue; 4354 4355 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4356 of_props[i].name); 4357 } 4358 } 4359 4360 return 0; 4361 } 4362 4363 static int ksz8463_configure_straps_spi(struct ksz_device *dev) 4364 { 4365 struct pinctrl *pinctrl; 4366 struct gpio_desc *rxd0; 4367 struct gpio_desc *rxd1; 4368 4369 rxd0 = devm_gpiod_get_index_optional(dev->dev, "straps-rxd", 0, GPIOD_OUT_LOW); 4370 if (IS_ERR(rxd0)) 4371 return PTR_ERR(rxd0); 4372 4373 rxd1 = devm_gpiod_get_index_optional(dev->dev, "straps-rxd", 1, GPIOD_OUT_HIGH); 4374 if (IS_ERR(rxd1)) 4375 return PTR_ERR(rxd1); 4376 4377 if (!rxd0 && !rxd1) 4378 return 0; 4379 4380 if ((rxd0 && !rxd1) || (rxd1 && !rxd0)) 4381 return -EINVAL; 4382 4383 pinctrl = devm_pinctrl_get_select(dev->dev, "reset"); 4384 if (IS_ERR(pinctrl)) 4385 return PTR_ERR(pinctrl); 4386 4387 return 0; 4388 } 4389 4390 static int ksz8463_release_straps_spi(struct ksz_device *dev) 4391 { 4392 return pinctrl_select_default_state(dev->dev); 4393 } 4394 4395 int ksz_switch_register(struct ksz_device *dev) 4396 { 4397 const struct ksz_chip_data *info; 4398 struct device_node *ports; 4399 phy_interface_t interface; 4400 unsigned int port_num; 4401 int ret; 4402 int i; 4403 4404 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 4405 GPIOD_OUT_LOW); 4406 if (IS_ERR(dev->reset_gpio)) 4407 return PTR_ERR(dev->reset_gpio); 4408 4409 if (dev->reset_gpio) { 4410 if (of_device_is_compatible(dev->dev->of_node, "microchip,ksz8463")) { 4411 ret = ksz8463_configure_straps_spi(dev); 4412 if (ret) 4413 return ret; 4414 } 4415 4416 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4417 usleep_range(10000, 12000); 4418 gpiod_set_value_cansleep(dev->reset_gpio, 0); 4419 msleep(100); 4420 4421 if (of_device_is_compatible(dev->dev->of_node, "microchip,ksz8463")) { 4422 ret = ksz8463_release_straps_spi(dev); 4423 if (ret) 4424 return ret; 4425 } 4426 } 4427 4428 mutex_init(&dev->dev_mutex); 4429 mutex_init(&dev->regmap_mutex); 4430 mutex_init(&dev->alu_mutex); 4431 mutex_init(&dev->vlan_mutex); 4432 4433 ret = ksz_switch_detect(dev); 4434 if (ret) 4435 return ret; 4436 4437 info = ksz_lookup_info(dev->chip_id); 4438 if (!info) 4439 return -ENODEV; 4440 4441 /* Update the compatible info with the probed one */ 4442 dev->info = info; 4443 4444 dev_info(dev->dev, "found switch: %s, rev %i\n", 4445 dev->info->dev_name, dev->chip_rev); 4446 4447 ret = ksz_check_device_id(dev); 4448 if (ret) 4449 return ret; 4450 4451 dev->dev_ops = dev->info->ops; 4452 4453 ret = dev->dev_ops->init(dev); 4454 if (ret) 4455 return ret; 4456 4457 dev->ports = devm_kzalloc(dev->dev, 4458 dev->info->port_cnt * sizeof(struct ksz_port), 4459 GFP_KERNEL); 4460 if (!dev->ports) 4461 return -ENOMEM; 4462 4463 for (i = 0; i < dev->info->port_cnt; i++) { 4464 spin_lock_init(&dev->ports[i].mib.stats64_lock); 4465 mutex_init(&dev->ports[i].mib.cnt_mutex); 4466 dev->ports[i].mib.counters = 4467 devm_kzalloc(dev->dev, 4468 sizeof(u64) * (dev->info->mib_cnt + 1), 4469 GFP_KERNEL); 4470 if (!dev->ports[i].mib.counters) 4471 return -ENOMEM; 4472 4473 dev->ports[i].ksz_dev = dev; 4474 dev->ports[i].num = i; 4475 } 4476 4477 /* set the real number of ports */ 4478 dev->ds->num_ports = dev->info->port_cnt; 4479 4480 /* set the phylink ops */ 4481 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops; 4482 4483 /* Host port interface will be self detected, or specifically set in 4484 * device tree. 4485 */ 4486 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 4487 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 4488 if (dev->dev->of_node) { 4489 ret = of_get_phy_mode(dev->dev->of_node, &interface); 4490 if (ret == 0) 4491 dev->compat_interface = interface; 4492 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 4493 if (!ports) 4494 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 4495 if (ports) { 4496 for_each_available_child_of_node_scoped(ports, port) { 4497 if (of_property_read_u32(port, "reg", 4498 &port_num)) 4499 continue; 4500 if (!(dev->port_mask & BIT(port_num))) { 4501 of_node_put(ports); 4502 return -EINVAL; 4503 } 4504 of_get_phy_mode(port, 4505 &dev->ports[port_num].interface); 4506 4507 ksz_parse_rgmii_delay(dev, port_num, port); 4508 dev->ports[port_num].fiber = 4509 of_property_read_bool(port, 4510 "micrel,fiber-mode"); 4511 } 4512 of_node_put(ports); 4513 } 4514 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 4515 "microchip,synclko-125"); 4516 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 4517 "microchip,synclko-disable"); 4518 if (dev->synclko_125 && dev->synclko_disable) { 4519 dev_err(dev->dev, "inconsistent synclko settings\n"); 4520 return -EINVAL; 4521 } 4522 4523 dev->wakeup_source = of_property_read_bool(dev->dev->of_node, 4524 "wakeup-source"); 4525 dev->pme_active_high = of_property_read_bool(dev->dev->of_node, 4526 "microchip,pme-active-high"); 4527 } 4528 4529 ret = dsa_register_switch(dev->ds); 4530 if (ret) 4531 return ret; 4532 4533 /* Read MIB counters every 30 seconds to avoid overflow. */ 4534 dev->mib_read_interval = msecs_to_jiffies(5000); 4535 4536 /* Start the MIB timer. */ 4537 schedule_delayed_work(&dev->mib_read, 0); 4538 4539 return ret; 4540 } 4541 EXPORT_SYMBOL(ksz_switch_register); 4542 4543 void ksz_switch_remove(struct ksz_device *dev) 4544 { 4545 /* timer started */ 4546 if (dev->mib_read_interval) { 4547 dev->mib_read_interval = 0; 4548 cancel_delayed_work_sync(&dev->mib_read); 4549 } 4550 4551 dsa_unregister_switch(dev->ds); 4552 } 4553 EXPORT_SYMBOL(ksz_switch_remove); 4554 4555 #ifdef CONFIG_PM_SLEEP 4556 int ksz_switch_suspend(struct device *dev) 4557 { 4558 struct ksz_device *priv = dev_get_drvdata(dev); 4559 4560 return dsa_switch_suspend(priv->ds); 4561 } 4562 EXPORT_SYMBOL(ksz_switch_suspend); 4563 4564 int ksz_switch_resume(struct device *dev) 4565 { 4566 struct ksz_device *priv = dev_get_drvdata(dev); 4567 4568 return dsa_switch_resume(priv->ds); 4569 } 4570 EXPORT_SYMBOL(ksz_switch_resume); 4571 #endif 4572 4573 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 4574 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 4575 MODULE_LICENSE("GPL"); 4576