1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2024 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/if_hsr.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/of.h> 23 #include <linux/of_mdio.h> 24 #include <linux/of_net.h> 25 #include <linux/micrel_phy.h> 26 #include <net/dsa.h> 27 #include <net/ieee8021q.h> 28 #include <net/pkt_cls.h> 29 #include <net/switchdev.h> 30 31 #include "ksz_common.h" 32 #include "ksz_dcb.h" 33 #include "ksz_ptp.h" 34 #include "ksz8.h" 35 #include "ksz9477.h" 36 #include "lan937x.h" 37 38 #define MIB_COUNTER_NUM 0x20 39 40 struct ksz_stats_raw { 41 u64 rx_hi; 42 u64 rx_undersize; 43 u64 rx_fragments; 44 u64 rx_oversize; 45 u64 rx_jabbers; 46 u64 rx_symbol_err; 47 u64 rx_crc_err; 48 u64 rx_align_err; 49 u64 rx_mac_ctrl; 50 u64 rx_pause; 51 u64 rx_bcast; 52 u64 rx_mcast; 53 u64 rx_ucast; 54 u64 rx_64_or_less; 55 u64 rx_65_127; 56 u64 rx_128_255; 57 u64 rx_256_511; 58 u64 rx_512_1023; 59 u64 rx_1024_1522; 60 u64 rx_1523_2000; 61 u64 rx_2001; 62 u64 tx_hi; 63 u64 tx_late_col; 64 u64 tx_pause; 65 u64 tx_bcast; 66 u64 tx_mcast; 67 u64 tx_ucast; 68 u64 tx_deferred; 69 u64 tx_total_col; 70 u64 tx_exc_col; 71 u64 tx_single_col; 72 u64 tx_mult_col; 73 u64 rx_total; 74 u64 tx_total; 75 u64 rx_discards; 76 u64 tx_discards; 77 }; 78 79 struct ksz88xx_stats_raw { 80 u64 rx; 81 u64 rx_hi; 82 u64 rx_undersize; 83 u64 rx_fragments; 84 u64 rx_oversize; 85 u64 rx_jabbers; 86 u64 rx_symbol_err; 87 u64 rx_crc_err; 88 u64 rx_align_err; 89 u64 rx_mac_ctrl; 90 u64 rx_pause; 91 u64 rx_bcast; 92 u64 rx_mcast; 93 u64 rx_ucast; 94 u64 rx_64_or_less; 95 u64 rx_65_127; 96 u64 rx_128_255; 97 u64 rx_256_511; 98 u64 rx_512_1023; 99 u64 rx_1024_1522; 100 u64 tx; 101 u64 tx_hi; 102 u64 tx_late_col; 103 u64 tx_pause; 104 u64 tx_bcast; 105 u64 tx_mcast; 106 u64 tx_ucast; 107 u64 tx_deferred; 108 u64 tx_total_col; 109 u64 tx_exc_col; 110 u64 tx_single_col; 111 u64 tx_mult_col; 112 u64 rx_discards; 113 u64 tx_discards; 114 }; 115 116 static const struct ksz_mib_names ksz88xx_mib_names[] = { 117 { 0x00, "rx" }, 118 { 0x01, "rx_hi" }, 119 { 0x02, "rx_undersize" }, 120 { 0x03, "rx_fragments" }, 121 { 0x04, "rx_oversize" }, 122 { 0x05, "rx_jabbers" }, 123 { 0x06, "rx_symbol_err" }, 124 { 0x07, "rx_crc_err" }, 125 { 0x08, "rx_align_err" }, 126 { 0x09, "rx_mac_ctrl" }, 127 { 0x0a, "rx_pause" }, 128 { 0x0b, "rx_bcast" }, 129 { 0x0c, "rx_mcast" }, 130 { 0x0d, "rx_ucast" }, 131 { 0x0e, "rx_64_or_less" }, 132 { 0x0f, "rx_65_127" }, 133 { 0x10, "rx_128_255" }, 134 { 0x11, "rx_256_511" }, 135 { 0x12, "rx_512_1023" }, 136 { 0x13, "rx_1024_1522" }, 137 { 0x14, "tx" }, 138 { 0x15, "tx_hi" }, 139 { 0x16, "tx_late_col" }, 140 { 0x17, "tx_pause" }, 141 { 0x18, "tx_bcast" }, 142 { 0x19, "tx_mcast" }, 143 { 0x1a, "tx_ucast" }, 144 { 0x1b, "tx_deferred" }, 145 { 0x1c, "tx_total_col" }, 146 { 0x1d, "tx_exc_col" }, 147 { 0x1e, "tx_single_col" }, 148 { 0x1f, "tx_mult_col" }, 149 { 0x100, "rx_discards" }, 150 { 0x101, "tx_discards" }, 151 }; 152 153 static const struct ksz_mib_names ksz9477_mib_names[] = { 154 { 0x00, "rx_hi" }, 155 { 0x01, "rx_undersize" }, 156 { 0x02, "rx_fragments" }, 157 { 0x03, "rx_oversize" }, 158 { 0x04, "rx_jabbers" }, 159 { 0x05, "rx_symbol_err" }, 160 { 0x06, "rx_crc_err" }, 161 { 0x07, "rx_align_err" }, 162 { 0x08, "rx_mac_ctrl" }, 163 { 0x09, "rx_pause" }, 164 { 0x0A, "rx_bcast" }, 165 { 0x0B, "rx_mcast" }, 166 { 0x0C, "rx_ucast" }, 167 { 0x0D, "rx_64_or_less" }, 168 { 0x0E, "rx_65_127" }, 169 { 0x0F, "rx_128_255" }, 170 { 0x10, "rx_256_511" }, 171 { 0x11, "rx_512_1023" }, 172 { 0x12, "rx_1024_1522" }, 173 { 0x13, "rx_1523_2000" }, 174 { 0x14, "rx_2001" }, 175 { 0x15, "tx_hi" }, 176 { 0x16, "tx_late_col" }, 177 { 0x17, "tx_pause" }, 178 { 0x18, "tx_bcast" }, 179 { 0x19, "tx_mcast" }, 180 { 0x1A, "tx_ucast" }, 181 { 0x1B, "tx_deferred" }, 182 { 0x1C, "tx_total_col" }, 183 { 0x1D, "tx_exc_col" }, 184 { 0x1E, "tx_single_col" }, 185 { 0x1F, "tx_mult_col" }, 186 { 0x80, "rx_total" }, 187 { 0x81, "tx_total" }, 188 { 0x82, "rx_discards" }, 189 { 0x83, "tx_discards" }, 190 }; 191 192 struct ksz_driver_strength_prop { 193 const char *name; 194 int offset; 195 int value; 196 }; 197 198 enum ksz_driver_strength_type { 199 KSZ_DRIVER_STRENGTH_HI, 200 KSZ_DRIVER_STRENGTH_LO, 201 KSZ_DRIVER_STRENGTH_IO, 202 }; 203 204 /** 205 * struct ksz_drive_strength - drive strength mapping 206 * @reg_val: register value 207 * @microamp: microamp value 208 */ 209 struct ksz_drive_strength { 210 u32 reg_val; 211 u32 microamp; 212 }; 213 214 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants 215 * 216 * This values are not documented in KSZ9477 variants but confirmed by 217 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893 218 * and KSZ8563 are using same register (drive strength) settings like KSZ8795. 219 * 220 * Documentation in KSZ8795CLX provides more information with some 221 * recommendations: 222 * - for high speed signals 223 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using 224 * 2.5V or 3.3V VDDIO. 225 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with 226 * using 1.8V VDDIO. 227 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V 228 * or 3.3V VDDIO. 229 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO. 230 * 5. In same interface, the heavy loading should use higher one of the 231 * drive current strength. 232 * - for low speed signals 233 * 1. 3.3V VDDIO, use either 4 mA or 8 mA. 234 * 2. 2.5V VDDIO, use either 8 mA or 12 mA. 235 * 3. 1.8V VDDIO, use either 12 mA or 16 mA. 236 * 4. If it is heavy loading, can use higher drive current strength. 237 */ 238 static const struct ksz_drive_strength ksz9477_drive_strengths[] = { 239 { SW_DRIVE_STRENGTH_2MA, 2000 }, 240 { SW_DRIVE_STRENGTH_4MA, 4000 }, 241 { SW_DRIVE_STRENGTH_8MA, 8000 }, 242 { SW_DRIVE_STRENGTH_12MA, 12000 }, 243 { SW_DRIVE_STRENGTH_16MA, 16000 }, 244 { SW_DRIVE_STRENGTH_20MA, 20000 }, 245 { SW_DRIVE_STRENGTH_24MA, 24000 }, 246 { SW_DRIVE_STRENGTH_28MA, 28000 }, 247 }; 248 249 /* ksz88x3_drive_strengths - Drive strength mapping for KSZ8863, KSZ8873, .. 250 * variants. 251 * This values are documented in KSZ8873 and KSZ8863 datasheets. 252 */ 253 static const struct ksz_drive_strength ksz88x3_drive_strengths[] = { 254 { 0, 8000 }, 255 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 }, 256 }; 257 258 static void ksz88x3_phylink_mac_config(struct phylink_config *config, 259 unsigned int mode, 260 const struct phylink_link_state *state); 261 static void ksz_phylink_mac_config(struct phylink_config *config, 262 unsigned int mode, 263 const struct phylink_link_state *state); 264 static void ksz_phylink_mac_link_down(struct phylink_config *config, 265 unsigned int mode, 266 phy_interface_t interface); 267 268 /** 269 * ksz_phylink_mac_disable_tx_lpi() - Callback to signal LPI support (Dummy) 270 * @config: phylink config structure 271 * 272 * This function is a dummy handler. See ksz_phylink_mac_enable_tx_lpi() for 273 * a detailed explanation of EEE/LPI handling in KSZ switches. 274 */ 275 static void ksz_phylink_mac_disable_tx_lpi(struct phylink_config *config) 276 { 277 } 278 279 /** 280 * ksz_phylink_mac_enable_tx_lpi() - Callback to signal LPI support (Dummy) 281 * @config: phylink config structure 282 * @timer: timer value before entering LPI (unused) 283 * @tx_clock_stop: whether to stop the TX clock in LPI mode (unused) 284 * 285 * This function signals to phylink that the driver architecture supports 286 * LPI management, enabling phylink to control EEE advertisement during 287 * negotiation according to IEEE Std 802.3 (Clause 78). 288 * 289 * Hardware Management of EEE/LPI State: 290 * For KSZ switch ports with integrated PHYs (e.g., KSZ9893R ports 1-2), 291 * observation and testing suggest that the actual EEE / Low Power Idle (LPI) 292 * state transitions are managed autonomously by the hardware based on 293 * the auto-negotiation results. (Note: While the datasheet describes EEE 294 * operation based on negotiation, it doesn't explicitly detail the internal 295 * MAC/PHY interaction, so autonomous hardware management of the MAC state 296 * for LPI is inferred from observed behavior). 297 * This hardware control, consistent with the switch's ability to operate 298 * autonomously via strapping, means MAC-level software intervention is not 299 * required or exposed for managing the LPI state once EEE is negotiated. 300 * (Ref: KSZ9893R Data Sheet DS00002420D, primarily Section 4.7.5 explaining 301 * EEE, also Sections 4.1.7 on Auto-Negotiation and 3.2.1 on Configuration 302 * Straps). 303 * 304 * Additionally, ports configured as MAC interfaces (e.g., KSZ9893R port 3) 305 * lack documented MAC-level LPI control. 306 * 307 * Therefore, this callback performs no action and serves primarily to inform 308 * phylink of LPI awareness and to document the inferred hardware behavior. 309 * 310 * Returns: 0 (Always success) 311 */ 312 static int ksz_phylink_mac_enable_tx_lpi(struct phylink_config *config, 313 u32 timer, bool tx_clock_stop) 314 { 315 return 0; 316 } 317 318 static const struct phylink_mac_ops ksz88x3_phylink_mac_ops = { 319 .mac_config = ksz88x3_phylink_mac_config, 320 .mac_link_down = ksz_phylink_mac_link_down, 321 .mac_link_up = ksz8_phylink_mac_link_up, 322 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 323 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 324 }; 325 326 static const struct phylink_mac_ops ksz8_phylink_mac_ops = { 327 .mac_config = ksz_phylink_mac_config, 328 .mac_link_down = ksz_phylink_mac_link_down, 329 .mac_link_up = ksz8_phylink_mac_link_up, 330 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 331 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 332 }; 333 334 static const struct ksz_dev_ops ksz88xx_dev_ops = { 335 .setup = ksz8_setup, 336 .get_port_addr = ksz8_get_port_addr, 337 .cfg_port_member = ksz8_cfg_port_member, 338 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 339 .port_setup = ksz8_port_setup, 340 .r_phy = ksz8_r_phy, 341 .w_phy = ksz8_w_phy, 342 .r_mib_cnt = ksz8_r_mib_cnt, 343 .r_mib_pkt = ksz8_r_mib_pkt, 344 .r_mib_stat64 = ksz88xx_r_mib_stats64, 345 .freeze_mib = ksz8_freeze_mib, 346 .port_init_cnt = ksz8_port_init_cnt, 347 .fdb_dump = ksz8_fdb_dump, 348 .fdb_add = ksz8_fdb_add, 349 .fdb_del = ksz8_fdb_del, 350 .mdb_add = ksz8_mdb_add, 351 .mdb_del = ksz8_mdb_del, 352 .vlan_filtering = ksz8_port_vlan_filtering, 353 .vlan_add = ksz8_port_vlan_add, 354 .vlan_del = ksz8_port_vlan_del, 355 .mirror_add = ksz8_port_mirror_add, 356 .mirror_del = ksz8_port_mirror_del, 357 .get_caps = ksz8_get_caps, 358 .config_cpu_port = ksz8_config_cpu_port, 359 .enable_stp_addr = ksz8_enable_stp_addr, 360 .reset = ksz8_reset_switch, 361 .init = ksz8_switch_init, 362 .exit = ksz8_switch_exit, 363 .change_mtu = ksz8_change_mtu, 364 .pme_write8 = ksz8_pme_write8, 365 .pme_pread8 = ksz8_pme_pread8, 366 .pme_pwrite8 = ksz8_pme_pwrite8, 367 }; 368 369 static const struct ksz_dev_ops ksz87xx_dev_ops = { 370 .setup = ksz8_setup, 371 .get_port_addr = ksz8_get_port_addr, 372 .cfg_port_member = ksz8_cfg_port_member, 373 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 374 .port_setup = ksz8_port_setup, 375 .r_phy = ksz8_r_phy, 376 .w_phy = ksz8_w_phy, 377 .r_mib_cnt = ksz8_r_mib_cnt, 378 .r_mib_pkt = ksz8_r_mib_pkt, 379 .r_mib_stat64 = ksz_r_mib_stats64, 380 .freeze_mib = ksz8_freeze_mib, 381 .port_init_cnt = ksz8_port_init_cnt, 382 .fdb_dump = ksz8_fdb_dump, 383 .fdb_add = ksz8_fdb_add, 384 .fdb_del = ksz8_fdb_del, 385 .mdb_add = ksz8_mdb_add, 386 .mdb_del = ksz8_mdb_del, 387 .vlan_filtering = ksz8_port_vlan_filtering, 388 .vlan_add = ksz8_port_vlan_add, 389 .vlan_del = ksz8_port_vlan_del, 390 .mirror_add = ksz8_port_mirror_add, 391 .mirror_del = ksz8_port_mirror_del, 392 .get_caps = ksz8_get_caps, 393 .config_cpu_port = ksz8_config_cpu_port, 394 .enable_stp_addr = ksz8_enable_stp_addr, 395 .reset = ksz8_reset_switch, 396 .init = ksz8_switch_init, 397 .exit = ksz8_switch_exit, 398 .change_mtu = ksz8_change_mtu, 399 .pme_write8 = ksz8_pme_write8, 400 .pme_pread8 = ksz8_pme_pread8, 401 .pme_pwrite8 = ksz8_pme_pwrite8, 402 }; 403 404 static void ksz9477_phylink_mac_link_up(struct phylink_config *config, 405 struct phy_device *phydev, 406 unsigned int mode, 407 phy_interface_t interface, 408 int speed, int duplex, bool tx_pause, 409 bool rx_pause); 410 411 static const struct phylink_mac_ops ksz9477_phylink_mac_ops = { 412 .mac_config = ksz_phylink_mac_config, 413 .mac_link_down = ksz_phylink_mac_link_down, 414 .mac_link_up = ksz9477_phylink_mac_link_up, 415 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 416 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 417 }; 418 419 static const struct ksz_dev_ops ksz9477_dev_ops = { 420 .setup = ksz9477_setup, 421 .get_port_addr = ksz9477_get_port_addr, 422 .cfg_port_member = ksz9477_cfg_port_member, 423 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 424 .port_setup = ksz9477_port_setup, 425 .set_ageing_time = ksz9477_set_ageing_time, 426 .r_phy = ksz9477_r_phy, 427 .w_phy = ksz9477_w_phy, 428 .r_mib_cnt = ksz9477_r_mib_cnt, 429 .r_mib_pkt = ksz9477_r_mib_pkt, 430 .r_mib_stat64 = ksz_r_mib_stats64, 431 .freeze_mib = ksz9477_freeze_mib, 432 .port_init_cnt = ksz9477_port_init_cnt, 433 .vlan_filtering = ksz9477_port_vlan_filtering, 434 .vlan_add = ksz9477_port_vlan_add, 435 .vlan_del = ksz9477_port_vlan_del, 436 .mirror_add = ksz9477_port_mirror_add, 437 .mirror_del = ksz9477_port_mirror_del, 438 .get_caps = ksz9477_get_caps, 439 .fdb_dump = ksz9477_fdb_dump, 440 .fdb_add = ksz9477_fdb_add, 441 .fdb_del = ksz9477_fdb_del, 442 .mdb_add = ksz9477_mdb_add, 443 .mdb_del = ksz9477_mdb_del, 444 .change_mtu = ksz9477_change_mtu, 445 .pme_write8 = ksz_write8, 446 .pme_pread8 = ksz_pread8, 447 .pme_pwrite8 = ksz_pwrite8, 448 .config_cpu_port = ksz9477_config_cpu_port, 449 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc, 450 .enable_stp_addr = ksz9477_enable_stp_addr, 451 .reset = ksz9477_reset_switch, 452 .init = ksz9477_switch_init, 453 .exit = ksz9477_switch_exit, 454 }; 455 456 static const struct phylink_mac_ops lan937x_phylink_mac_ops = { 457 .mac_config = ksz_phylink_mac_config, 458 .mac_link_down = ksz_phylink_mac_link_down, 459 .mac_link_up = ksz9477_phylink_mac_link_up, 460 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 461 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 462 }; 463 464 static const struct ksz_dev_ops lan937x_dev_ops = { 465 .setup = lan937x_setup, 466 .teardown = lan937x_teardown, 467 .get_port_addr = ksz9477_get_port_addr, 468 .cfg_port_member = ksz9477_cfg_port_member, 469 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 470 .port_setup = lan937x_port_setup, 471 .set_ageing_time = lan937x_set_ageing_time, 472 .mdio_bus_preinit = lan937x_mdio_bus_preinit, 473 .create_phy_addr_map = lan937x_create_phy_addr_map, 474 .r_phy = lan937x_r_phy, 475 .w_phy = lan937x_w_phy, 476 .r_mib_cnt = ksz9477_r_mib_cnt, 477 .r_mib_pkt = ksz9477_r_mib_pkt, 478 .r_mib_stat64 = ksz_r_mib_stats64, 479 .freeze_mib = ksz9477_freeze_mib, 480 .port_init_cnt = ksz9477_port_init_cnt, 481 .vlan_filtering = ksz9477_port_vlan_filtering, 482 .vlan_add = ksz9477_port_vlan_add, 483 .vlan_del = ksz9477_port_vlan_del, 484 .mirror_add = ksz9477_port_mirror_add, 485 .mirror_del = ksz9477_port_mirror_del, 486 .get_caps = lan937x_phylink_get_caps, 487 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 488 .fdb_dump = ksz9477_fdb_dump, 489 .fdb_add = ksz9477_fdb_add, 490 .fdb_del = ksz9477_fdb_del, 491 .mdb_add = ksz9477_mdb_add, 492 .mdb_del = ksz9477_mdb_del, 493 .change_mtu = lan937x_change_mtu, 494 .config_cpu_port = lan937x_config_cpu_port, 495 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 496 .enable_stp_addr = ksz9477_enable_stp_addr, 497 .reset = lan937x_reset_switch, 498 .init = lan937x_switch_init, 499 .exit = lan937x_switch_exit, 500 }; 501 502 static const u16 ksz8795_regs[] = { 503 [REG_SW_MAC_ADDR] = 0x68, 504 [REG_IND_CTRL_0] = 0x6E, 505 [REG_IND_DATA_8] = 0x70, 506 [REG_IND_DATA_CHECK] = 0x72, 507 [REG_IND_DATA_HI] = 0x71, 508 [REG_IND_DATA_LO] = 0x75, 509 [REG_IND_MIB_CHECK] = 0x74, 510 [REG_IND_BYTE] = 0xA0, 511 [P_FORCE_CTRL] = 0x0C, 512 [P_LINK_STATUS] = 0x0E, 513 [P_LOCAL_CTRL] = 0x07, 514 [P_NEG_RESTART_CTRL] = 0x0D, 515 [P_REMOTE_STATUS] = 0x08, 516 [P_SPEED_STATUS] = 0x09, 517 [S_TAIL_TAG_CTRL] = 0x0C, 518 [P_STP_CTRL] = 0x02, 519 [S_START_CTRL] = 0x01, 520 [S_BROADCAST_CTRL] = 0x06, 521 [S_MULTICAST_CTRL] = 0x04, 522 [P_XMII_CTRL_0] = 0x06, 523 [P_XMII_CTRL_1] = 0x06, 524 [REG_SW_PME_CTRL] = 0x8003, 525 [REG_PORT_PME_STATUS] = 0x8003, 526 [REG_PORT_PME_CTRL] = 0x8007, 527 }; 528 529 static const u32 ksz8795_masks[] = { 530 [PORT_802_1P_REMAPPING] = BIT(7), 531 [SW_TAIL_TAG_ENABLE] = BIT(1), 532 [MIB_COUNTER_OVERFLOW] = BIT(6), 533 [MIB_COUNTER_VALID] = BIT(5), 534 [VLAN_TABLE_FID] = GENMASK(6, 0), 535 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 536 [VLAN_TABLE_VALID] = BIT(12), 537 [STATIC_MAC_TABLE_VALID] = BIT(21), 538 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 539 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 540 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 541 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 542 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 543 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 544 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 545 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 546 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 547 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 548 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 549 [P_MII_TX_FLOW_CTRL] = BIT(5), 550 [P_MII_RX_FLOW_CTRL] = BIT(5), 551 }; 552 553 static const u8 ksz8795_xmii_ctrl0[] = { 554 [P_MII_100MBIT] = 0, 555 [P_MII_10MBIT] = 1, 556 [P_MII_FULL_DUPLEX] = 0, 557 [P_MII_HALF_DUPLEX] = 1, 558 }; 559 560 static const u8 ksz8795_xmii_ctrl1[] = { 561 [P_RGMII_SEL] = 3, 562 [P_GMII_SEL] = 2, 563 [P_RMII_SEL] = 1, 564 [P_MII_SEL] = 0, 565 [P_GMII_1GBIT] = 1, 566 [P_GMII_NOT_1GBIT] = 0, 567 }; 568 569 static const u8 ksz8795_shifts[] = { 570 [VLAN_TABLE_MEMBERSHIP_S] = 7, 571 [VLAN_TABLE] = 16, 572 [STATIC_MAC_FWD_PORTS] = 16, 573 [STATIC_MAC_FID] = 24, 574 [DYNAMIC_MAC_ENTRIES_H] = 3, 575 [DYNAMIC_MAC_ENTRIES] = 29, 576 [DYNAMIC_MAC_FID] = 16, 577 [DYNAMIC_MAC_TIMESTAMP] = 27, 578 [DYNAMIC_MAC_SRC_PORT] = 24, 579 }; 580 581 static const u16 ksz8863_regs[] = { 582 [REG_SW_MAC_ADDR] = 0x70, 583 [REG_IND_CTRL_0] = 0x79, 584 [REG_IND_DATA_8] = 0x7B, 585 [REG_IND_DATA_CHECK] = 0x7B, 586 [REG_IND_DATA_HI] = 0x7C, 587 [REG_IND_DATA_LO] = 0x80, 588 [REG_IND_MIB_CHECK] = 0x80, 589 [P_FORCE_CTRL] = 0x0C, 590 [P_LINK_STATUS] = 0x0E, 591 [P_LOCAL_CTRL] = 0x0C, 592 [P_NEG_RESTART_CTRL] = 0x0D, 593 [P_REMOTE_STATUS] = 0x0E, 594 [P_SPEED_STATUS] = 0x0F, 595 [S_TAIL_TAG_CTRL] = 0x03, 596 [P_STP_CTRL] = 0x02, 597 [S_START_CTRL] = 0x01, 598 [S_BROADCAST_CTRL] = 0x06, 599 [S_MULTICAST_CTRL] = 0x04, 600 }; 601 602 static const u32 ksz8863_masks[] = { 603 [PORT_802_1P_REMAPPING] = BIT(3), 604 [SW_TAIL_TAG_ENABLE] = BIT(6), 605 [MIB_COUNTER_OVERFLOW] = BIT(7), 606 [MIB_COUNTER_VALID] = BIT(6), 607 [VLAN_TABLE_FID] = GENMASK(15, 12), 608 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 609 [VLAN_TABLE_VALID] = BIT(19), 610 [STATIC_MAC_TABLE_VALID] = BIT(19), 611 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 612 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 613 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 614 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 615 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 616 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 617 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 618 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 619 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 620 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 621 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 622 }; 623 624 static u8 ksz8863_shifts[] = { 625 [VLAN_TABLE_MEMBERSHIP_S] = 16, 626 [STATIC_MAC_FWD_PORTS] = 16, 627 [STATIC_MAC_FID] = 22, 628 [DYNAMIC_MAC_ENTRIES_H] = 8, 629 [DYNAMIC_MAC_ENTRIES] = 24, 630 [DYNAMIC_MAC_FID] = 16, 631 [DYNAMIC_MAC_TIMESTAMP] = 22, 632 [DYNAMIC_MAC_SRC_PORT] = 20, 633 }; 634 635 static const u16 ksz8895_regs[] = { 636 [REG_SW_MAC_ADDR] = 0x68, 637 [REG_IND_CTRL_0] = 0x6E, 638 [REG_IND_DATA_8] = 0x70, 639 [REG_IND_DATA_CHECK] = 0x72, 640 [REG_IND_DATA_HI] = 0x71, 641 [REG_IND_DATA_LO] = 0x75, 642 [REG_IND_MIB_CHECK] = 0x75, 643 [P_FORCE_CTRL] = 0x0C, 644 [P_LINK_STATUS] = 0x0E, 645 [P_LOCAL_CTRL] = 0x0C, 646 [P_NEG_RESTART_CTRL] = 0x0D, 647 [P_REMOTE_STATUS] = 0x0E, 648 [P_SPEED_STATUS] = 0x09, 649 [S_TAIL_TAG_CTRL] = 0x0C, 650 [P_STP_CTRL] = 0x02, 651 [S_START_CTRL] = 0x01, 652 [S_BROADCAST_CTRL] = 0x06, 653 [S_MULTICAST_CTRL] = 0x04, 654 }; 655 656 static const u32 ksz8895_masks[] = { 657 [PORT_802_1P_REMAPPING] = BIT(7), 658 [SW_TAIL_TAG_ENABLE] = BIT(1), 659 [MIB_COUNTER_OVERFLOW] = BIT(7), 660 [MIB_COUNTER_VALID] = BIT(6), 661 [VLAN_TABLE_FID] = GENMASK(6, 0), 662 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 663 [VLAN_TABLE_VALID] = BIT(12), 664 [STATIC_MAC_TABLE_VALID] = BIT(21), 665 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 666 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 667 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 668 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 669 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 670 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 671 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 672 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 673 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 674 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 675 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 676 }; 677 678 static const u8 ksz8895_shifts[] = { 679 [VLAN_TABLE_MEMBERSHIP_S] = 7, 680 [VLAN_TABLE] = 13, 681 [STATIC_MAC_FWD_PORTS] = 16, 682 [STATIC_MAC_FID] = 24, 683 [DYNAMIC_MAC_ENTRIES_H] = 3, 684 [DYNAMIC_MAC_ENTRIES] = 29, 685 [DYNAMIC_MAC_FID] = 16, 686 [DYNAMIC_MAC_TIMESTAMP] = 27, 687 [DYNAMIC_MAC_SRC_PORT] = 24, 688 }; 689 690 static const u16 ksz9477_regs[] = { 691 [REG_SW_MAC_ADDR] = 0x0302, 692 [P_STP_CTRL] = 0x0B04, 693 [S_START_CTRL] = 0x0300, 694 [S_BROADCAST_CTRL] = 0x0332, 695 [S_MULTICAST_CTRL] = 0x0331, 696 [P_XMII_CTRL_0] = 0x0300, 697 [P_XMII_CTRL_1] = 0x0301, 698 [REG_SW_PME_CTRL] = 0x0006, 699 [REG_PORT_PME_STATUS] = 0x0013, 700 [REG_PORT_PME_CTRL] = 0x0017, 701 }; 702 703 static const u32 ksz9477_masks[] = { 704 [ALU_STAT_WRITE] = 0, 705 [ALU_STAT_READ] = 1, 706 [P_MII_TX_FLOW_CTRL] = BIT(5), 707 [P_MII_RX_FLOW_CTRL] = BIT(3), 708 }; 709 710 static const u8 ksz9477_shifts[] = { 711 [ALU_STAT_INDEX] = 16, 712 }; 713 714 static const u8 ksz9477_xmii_ctrl0[] = { 715 [P_MII_100MBIT] = 1, 716 [P_MII_10MBIT] = 0, 717 [P_MII_FULL_DUPLEX] = 1, 718 [P_MII_HALF_DUPLEX] = 0, 719 }; 720 721 static const u8 ksz9477_xmii_ctrl1[] = { 722 [P_RGMII_SEL] = 0, 723 [P_RMII_SEL] = 1, 724 [P_GMII_SEL] = 2, 725 [P_MII_SEL] = 3, 726 [P_GMII_1GBIT] = 0, 727 [P_GMII_NOT_1GBIT] = 1, 728 }; 729 730 static const u32 lan937x_masks[] = { 731 [ALU_STAT_WRITE] = 1, 732 [ALU_STAT_READ] = 2, 733 [P_MII_TX_FLOW_CTRL] = BIT(5), 734 [P_MII_RX_FLOW_CTRL] = BIT(3), 735 }; 736 737 static const u8 lan937x_shifts[] = { 738 [ALU_STAT_INDEX] = 8, 739 }; 740 741 static const struct regmap_range ksz8563_valid_regs[] = { 742 regmap_reg_range(0x0000, 0x0003), 743 regmap_reg_range(0x0006, 0x0006), 744 regmap_reg_range(0x000f, 0x001f), 745 regmap_reg_range(0x0100, 0x0100), 746 regmap_reg_range(0x0104, 0x0107), 747 regmap_reg_range(0x010d, 0x010d), 748 regmap_reg_range(0x0110, 0x0113), 749 regmap_reg_range(0x0120, 0x012b), 750 regmap_reg_range(0x0201, 0x0201), 751 regmap_reg_range(0x0210, 0x0213), 752 regmap_reg_range(0x0300, 0x0300), 753 regmap_reg_range(0x0302, 0x031b), 754 regmap_reg_range(0x0320, 0x032b), 755 regmap_reg_range(0x0330, 0x0336), 756 regmap_reg_range(0x0338, 0x033e), 757 regmap_reg_range(0x0340, 0x035f), 758 regmap_reg_range(0x0370, 0x0370), 759 regmap_reg_range(0x0378, 0x0378), 760 regmap_reg_range(0x037c, 0x037d), 761 regmap_reg_range(0x0390, 0x0393), 762 regmap_reg_range(0x0400, 0x040e), 763 regmap_reg_range(0x0410, 0x042f), 764 regmap_reg_range(0x0500, 0x0519), 765 regmap_reg_range(0x0520, 0x054b), 766 regmap_reg_range(0x0550, 0x05b3), 767 768 /* port 1 */ 769 regmap_reg_range(0x1000, 0x1001), 770 regmap_reg_range(0x1004, 0x100b), 771 regmap_reg_range(0x1013, 0x1013), 772 regmap_reg_range(0x1017, 0x1017), 773 regmap_reg_range(0x101b, 0x101b), 774 regmap_reg_range(0x101f, 0x1021), 775 regmap_reg_range(0x1030, 0x1030), 776 regmap_reg_range(0x1100, 0x1111), 777 regmap_reg_range(0x111a, 0x111d), 778 regmap_reg_range(0x1122, 0x1127), 779 regmap_reg_range(0x112a, 0x112b), 780 regmap_reg_range(0x1136, 0x1139), 781 regmap_reg_range(0x113e, 0x113f), 782 regmap_reg_range(0x1400, 0x1401), 783 regmap_reg_range(0x1403, 0x1403), 784 regmap_reg_range(0x1410, 0x1417), 785 regmap_reg_range(0x1420, 0x1423), 786 regmap_reg_range(0x1500, 0x1507), 787 regmap_reg_range(0x1600, 0x1612), 788 regmap_reg_range(0x1800, 0x180f), 789 regmap_reg_range(0x1900, 0x1907), 790 regmap_reg_range(0x1914, 0x191b), 791 regmap_reg_range(0x1a00, 0x1a03), 792 regmap_reg_range(0x1a04, 0x1a08), 793 regmap_reg_range(0x1b00, 0x1b01), 794 regmap_reg_range(0x1b04, 0x1b04), 795 regmap_reg_range(0x1c00, 0x1c05), 796 regmap_reg_range(0x1c08, 0x1c1b), 797 798 /* port 2 */ 799 regmap_reg_range(0x2000, 0x2001), 800 regmap_reg_range(0x2004, 0x200b), 801 regmap_reg_range(0x2013, 0x2013), 802 regmap_reg_range(0x2017, 0x2017), 803 regmap_reg_range(0x201b, 0x201b), 804 regmap_reg_range(0x201f, 0x2021), 805 regmap_reg_range(0x2030, 0x2030), 806 regmap_reg_range(0x2100, 0x2111), 807 regmap_reg_range(0x211a, 0x211d), 808 regmap_reg_range(0x2122, 0x2127), 809 regmap_reg_range(0x212a, 0x212b), 810 regmap_reg_range(0x2136, 0x2139), 811 regmap_reg_range(0x213e, 0x213f), 812 regmap_reg_range(0x2400, 0x2401), 813 regmap_reg_range(0x2403, 0x2403), 814 regmap_reg_range(0x2410, 0x2417), 815 regmap_reg_range(0x2420, 0x2423), 816 regmap_reg_range(0x2500, 0x2507), 817 regmap_reg_range(0x2600, 0x2612), 818 regmap_reg_range(0x2800, 0x280f), 819 regmap_reg_range(0x2900, 0x2907), 820 regmap_reg_range(0x2914, 0x291b), 821 regmap_reg_range(0x2a00, 0x2a03), 822 regmap_reg_range(0x2a04, 0x2a08), 823 regmap_reg_range(0x2b00, 0x2b01), 824 regmap_reg_range(0x2b04, 0x2b04), 825 regmap_reg_range(0x2c00, 0x2c05), 826 regmap_reg_range(0x2c08, 0x2c1b), 827 828 /* port 3 */ 829 regmap_reg_range(0x3000, 0x3001), 830 regmap_reg_range(0x3004, 0x300b), 831 regmap_reg_range(0x3013, 0x3013), 832 regmap_reg_range(0x3017, 0x3017), 833 regmap_reg_range(0x301b, 0x301b), 834 regmap_reg_range(0x301f, 0x3021), 835 regmap_reg_range(0x3030, 0x3030), 836 regmap_reg_range(0x3300, 0x3301), 837 regmap_reg_range(0x3303, 0x3303), 838 regmap_reg_range(0x3400, 0x3401), 839 regmap_reg_range(0x3403, 0x3403), 840 regmap_reg_range(0x3410, 0x3417), 841 regmap_reg_range(0x3420, 0x3423), 842 regmap_reg_range(0x3500, 0x3507), 843 regmap_reg_range(0x3600, 0x3612), 844 regmap_reg_range(0x3800, 0x380f), 845 regmap_reg_range(0x3900, 0x3907), 846 regmap_reg_range(0x3914, 0x391b), 847 regmap_reg_range(0x3a00, 0x3a03), 848 regmap_reg_range(0x3a04, 0x3a08), 849 regmap_reg_range(0x3b00, 0x3b01), 850 regmap_reg_range(0x3b04, 0x3b04), 851 regmap_reg_range(0x3c00, 0x3c05), 852 regmap_reg_range(0x3c08, 0x3c1b), 853 }; 854 855 static const struct regmap_access_table ksz8563_register_set = { 856 .yes_ranges = ksz8563_valid_regs, 857 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 858 }; 859 860 static const struct regmap_range ksz9477_valid_regs[] = { 861 regmap_reg_range(0x0000, 0x0003), 862 regmap_reg_range(0x0006, 0x0006), 863 regmap_reg_range(0x0010, 0x001f), 864 regmap_reg_range(0x0100, 0x0100), 865 regmap_reg_range(0x0103, 0x0107), 866 regmap_reg_range(0x010d, 0x010d), 867 regmap_reg_range(0x0110, 0x0113), 868 regmap_reg_range(0x0120, 0x012b), 869 regmap_reg_range(0x0201, 0x0201), 870 regmap_reg_range(0x0210, 0x0213), 871 regmap_reg_range(0x0300, 0x0300), 872 regmap_reg_range(0x0302, 0x031b), 873 regmap_reg_range(0x0320, 0x032b), 874 regmap_reg_range(0x0330, 0x0336), 875 regmap_reg_range(0x0338, 0x033b), 876 regmap_reg_range(0x033e, 0x033e), 877 regmap_reg_range(0x0340, 0x035f), 878 regmap_reg_range(0x0370, 0x0370), 879 regmap_reg_range(0x0378, 0x0378), 880 regmap_reg_range(0x037c, 0x037d), 881 regmap_reg_range(0x0390, 0x0393), 882 regmap_reg_range(0x0400, 0x040e), 883 regmap_reg_range(0x0410, 0x042f), 884 regmap_reg_range(0x0444, 0x044b), 885 regmap_reg_range(0x0450, 0x046f), 886 regmap_reg_range(0x0500, 0x0519), 887 regmap_reg_range(0x0520, 0x054b), 888 regmap_reg_range(0x0550, 0x05b3), 889 regmap_reg_range(0x0604, 0x060b), 890 regmap_reg_range(0x0610, 0x0612), 891 regmap_reg_range(0x0614, 0x062c), 892 regmap_reg_range(0x0640, 0x0645), 893 regmap_reg_range(0x0648, 0x064d), 894 895 /* port 1 */ 896 regmap_reg_range(0x1000, 0x1001), 897 regmap_reg_range(0x1013, 0x1013), 898 regmap_reg_range(0x1017, 0x1017), 899 regmap_reg_range(0x101b, 0x101b), 900 regmap_reg_range(0x101f, 0x1020), 901 regmap_reg_range(0x1030, 0x1030), 902 regmap_reg_range(0x1100, 0x1115), 903 regmap_reg_range(0x111a, 0x111f), 904 regmap_reg_range(0x1120, 0x112b), 905 regmap_reg_range(0x1134, 0x113b), 906 regmap_reg_range(0x113c, 0x113f), 907 regmap_reg_range(0x1400, 0x1401), 908 regmap_reg_range(0x1403, 0x1403), 909 regmap_reg_range(0x1410, 0x1417), 910 regmap_reg_range(0x1420, 0x1423), 911 regmap_reg_range(0x1500, 0x1507), 912 regmap_reg_range(0x1600, 0x1613), 913 regmap_reg_range(0x1800, 0x180f), 914 regmap_reg_range(0x1820, 0x1827), 915 regmap_reg_range(0x1830, 0x1837), 916 regmap_reg_range(0x1840, 0x184b), 917 regmap_reg_range(0x1900, 0x1907), 918 regmap_reg_range(0x1914, 0x191b), 919 regmap_reg_range(0x1920, 0x1920), 920 regmap_reg_range(0x1923, 0x1927), 921 regmap_reg_range(0x1a00, 0x1a03), 922 regmap_reg_range(0x1a04, 0x1a07), 923 regmap_reg_range(0x1b00, 0x1b01), 924 regmap_reg_range(0x1b04, 0x1b04), 925 regmap_reg_range(0x1c00, 0x1c05), 926 regmap_reg_range(0x1c08, 0x1c1b), 927 928 /* port 2 */ 929 regmap_reg_range(0x2000, 0x2001), 930 regmap_reg_range(0x2013, 0x2013), 931 regmap_reg_range(0x2017, 0x2017), 932 regmap_reg_range(0x201b, 0x201b), 933 regmap_reg_range(0x201f, 0x2020), 934 regmap_reg_range(0x2030, 0x2030), 935 regmap_reg_range(0x2100, 0x2115), 936 regmap_reg_range(0x211a, 0x211f), 937 regmap_reg_range(0x2120, 0x212b), 938 regmap_reg_range(0x2134, 0x213b), 939 regmap_reg_range(0x213c, 0x213f), 940 regmap_reg_range(0x2400, 0x2401), 941 regmap_reg_range(0x2403, 0x2403), 942 regmap_reg_range(0x2410, 0x2417), 943 regmap_reg_range(0x2420, 0x2423), 944 regmap_reg_range(0x2500, 0x2507), 945 regmap_reg_range(0x2600, 0x2613), 946 regmap_reg_range(0x2800, 0x280f), 947 regmap_reg_range(0x2820, 0x2827), 948 regmap_reg_range(0x2830, 0x2837), 949 regmap_reg_range(0x2840, 0x284b), 950 regmap_reg_range(0x2900, 0x2907), 951 regmap_reg_range(0x2914, 0x291b), 952 regmap_reg_range(0x2920, 0x2920), 953 regmap_reg_range(0x2923, 0x2927), 954 regmap_reg_range(0x2a00, 0x2a03), 955 regmap_reg_range(0x2a04, 0x2a07), 956 regmap_reg_range(0x2b00, 0x2b01), 957 regmap_reg_range(0x2b04, 0x2b04), 958 regmap_reg_range(0x2c00, 0x2c05), 959 regmap_reg_range(0x2c08, 0x2c1b), 960 961 /* port 3 */ 962 regmap_reg_range(0x3000, 0x3001), 963 regmap_reg_range(0x3013, 0x3013), 964 regmap_reg_range(0x3017, 0x3017), 965 regmap_reg_range(0x301b, 0x301b), 966 regmap_reg_range(0x301f, 0x3020), 967 regmap_reg_range(0x3030, 0x3030), 968 regmap_reg_range(0x3100, 0x3115), 969 regmap_reg_range(0x311a, 0x311f), 970 regmap_reg_range(0x3120, 0x312b), 971 regmap_reg_range(0x3134, 0x313b), 972 regmap_reg_range(0x313c, 0x313f), 973 regmap_reg_range(0x3400, 0x3401), 974 regmap_reg_range(0x3403, 0x3403), 975 regmap_reg_range(0x3410, 0x3417), 976 regmap_reg_range(0x3420, 0x3423), 977 regmap_reg_range(0x3500, 0x3507), 978 regmap_reg_range(0x3600, 0x3613), 979 regmap_reg_range(0x3800, 0x380f), 980 regmap_reg_range(0x3820, 0x3827), 981 regmap_reg_range(0x3830, 0x3837), 982 regmap_reg_range(0x3840, 0x384b), 983 regmap_reg_range(0x3900, 0x3907), 984 regmap_reg_range(0x3914, 0x391b), 985 regmap_reg_range(0x3920, 0x3920), 986 regmap_reg_range(0x3923, 0x3927), 987 regmap_reg_range(0x3a00, 0x3a03), 988 regmap_reg_range(0x3a04, 0x3a07), 989 regmap_reg_range(0x3b00, 0x3b01), 990 regmap_reg_range(0x3b04, 0x3b04), 991 regmap_reg_range(0x3c00, 0x3c05), 992 regmap_reg_range(0x3c08, 0x3c1b), 993 994 /* port 4 */ 995 regmap_reg_range(0x4000, 0x4001), 996 regmap_reg_range(0x4013, 0x4013), 997 regmap_reg_range(0x4017, 0x4017), 998 regmap_reg_range(0x401b, 0x401b), 999 regmap_reg_range(0x401f, 0x4020), 1000 regmap_reg_range(0x4030, 0x4030), 1001 regmap_reg_range(0x4100, 0x4115), 1002 regmap_reg_range(0x411a, 0x411f), 1003 regmap_reg_range(0x4120, 0x412b), 1004 regmap_reg_range(0x4134, 0x413b), 1005 regmap_reg_range(0x413c, 0x413f), 1006 regmap_reg_range(0x4400, 0x4401), 1007 regmap_reg_range(0x4403, 0x4403), 1008 regmap_reg_range(0x4410, 0x4417), 1009 regmap_reg_range(0x4420, 0x4423), 1010 regmap_reg_range(0x4500, 0x4507), 1011 regmap_reg_range(0x4600, 0x4613), 1012 regmap_reg_range(0x4800, 0x480f), 1013 regmap_reg_range(0x4820, 0x4827), 1014 regmap_reg_range(0x4830, 0x4837), 1015 regmap_reg_range(0x4840, 0x484b), 1016 regmap_reg_range(0x4900, 0x4907), 1017 regmap_reg_range(0x4914, 0x491b), 1018 regmap_reg_range(0x4920, 0x4920), 1019 regmap_reg_range(0x4923, 0x4927), 1020 regmap_reg_range(0x4a00, 0x4a03), 1021 regmap_reg_range(0x4a04, 0x4a07), 1022 regmap_reg_range(0x4b00, 0x4b01), 1023 regmap_reg_range(0x4b04, 0x4b04), 1024 regmap_reg_range(0x4c00, 0x4c05), 1025 regmap_reg_range(0x4c08, 0x4c1b), 1026 1027 /* port 5 */ 1028 regmap_reg_range(0x5000, 0x5001), 1029 regmap_reg_range(0x5013, 0x5013), 1030 regmap_reg_range(0x5017, 0x5017), 1031 regmap_reg_range(0x501b, 0x501b), 1032 regmap_reg_range(0x501f, 0x5020), 1033 regmap_reg_range(0x5030, 0x5030), 1034 regmap_reg_range(0x5100, 0x5115), 1035 regmap_reg_range(0x511a, 0x511f), 1036 regmap_reg_range(0x5120, 0x512b), 1037 regmap_reg_range(0x5134, 0x513b), 1038 regmap_reg_range(0x513c, 0x513f), 1039 regmap_reg_range(0x5400, 0x5401), 1040 regmap_reg_range(0x5403, 0x5403), 1041 regmap_reg_range(0x5410, 0x5417), 1042 regmap_reg_range(0x5420, 0x5423), 1043 regmap_reg_range(0x5500, 0x5507), 1044 regmap_reg_range(0x5600, 0x5613), 1045 regmap_reg_range(0x5800, 0x580f), 1046 regmap_reg_range(0x5820, 0x5827), 1047 regmap_reg_range(0x5830, 0x5837), 1048 regmap_reg_range(0x5840, 0x584b), 1049 regmap_reg_range(0x5900, 0x5907), 1050 regmap_reg_range(0x5914, 0x591b), 1051 regmap_reg_range(0x5920, 0x5920), 1052 regmap_reg_range(0x5923, 0x5927), 1053 regmap_reg_range(0x5a00, 0x5a03), 1054 regmap_reg_range(0x5a04, 0x5a07), 1055 regmap_reg_range(0x5b00, 0x5b01), 1056 regmap_reg_range(0x5b04, 0x5b04), 1057 regmap_reg_range(0x5c00, 0x5c05), 1058 regmap_reg_range(0x5c08, 0x5c1b), 1059 1060 /* port 6 */ 1061 regmap_reg_range(0x6000, 0x6001), 1062 regmap_reg_range(0x6013, 0x6013), 1063 regmap_reg_range(0x6017, 0x6017), 1064 regmap_reg_range(0x601b, 0x601b), 1065 regmap_reg_range(0x601f, 0x6020), 1066 regmap_reg_range(0x6030, 0x6030), 1067 regmap_reg_range(0x6300, 0x6301), 1068 regmap_reg_range(0x6400, 0x6401), 1069 regmap_reg_range(0x6403, 0x6403), 1070 regmap_reg_range(0x6410, 0x6417), 1071 regmap_reg_range(0x6420, 0x6423), 1072 regmap_reg_range(0x6500, 0x6507), 1073 regmap_reg_range(0x6600, 0x6613), 1074 regmap_reg_range(0x6800, 0x680f), 1075 regmap_reg_range(0x6820, 0x6827), 1076 regmap_reg_range(0x6830, 0x6837), 1077 regmap_reg_range(0x6840, 0x684b), 1078 regmap_reg_range(0x6900, 0x6907), 1079 regmap_reg_range(0x6914, 0x691b), 1080 regmap_reg_range(0x6920, 0x6920), 1081 regmap_reg_range(0x6923, 0x6927), 1082 regmap_reg_range(0x6a00, 0x6a03), 1083 regmap_reg_range(0x6a04, 0x6a07), 1084 regmap_reg_range(0x6b00, 0x6b01), 1085 regmap_reg_range(0x6b04, 0x6b04), 1086 regmap_reg_range(0x6c00, 0x6c05), 1087 regmap_reg_range(0x6c08, 0x6c1b), 1088 1089 /* port 7 */ 1090 regmap_reg_range(0x7000, 0x7001), 1091 regmap_reg_range(0x7013, 0x7013), 1092 regmap_reg_range(0x7017, 0x7017), 1093 regmap_reg_range(0x701b, 0x701b), 1094 regmap_reg_range(0x701f, 0x7020), 1095 regmap_reg_range(0x7030, 0x7030), 1096 regmap_reg_range(0x7200, 0x7203), 1097 regmap_reg_range(0x7206, 0x7207), 1098 regmap_reg_range(0x7300, 0x7301), 1099 regmap_reg_range(0x7400, 0x7401), 1100 regmap_reg_range(0x7403, 0x7403), 1101 regmap_reg_range(0x7410, 0x7417), 1102 regmap_reg_range(0x7420, 0x7423), 1103 regmap_reg_range(0x7500, 0x7507), 1104 regmap_reg_range(0x7600, 0x7613), 1105 regmap_reg_range(0x7800, 0x780f), 1106 regmap_reg_range(0x7820, 0x7827), 1107 regmap_reg_range(0x7830, 0x7837), 1108 regmap_reg_range(0x7840, 0x784b), 1109 regmap_reg_range(0x7900, 0x7907), 1110 regmap_reg_range(0x7914, 0x791b), 1111 regmap_reg_range(0x7920, 0x7920), 1112 regmap_reg_range(0x7923, 0x7927), 1113 regmap_reg_range(0x7a00, 0x7a03), 1114 regmap_reg_range(0x7a04, 0x7a07), 1115 regmap_reg_range(0x7b00, 0x7b01), 1116 regmap_reg_range(0x7b04, 0x7b04), 1117 regmap_reg_range(0x7c00, 0x7c05), 1118 regmap_reg_range(0x7c08, 0x7c1b), 1119 }; 1120 1121 static const struct regmap_access_table ksz9477_register_set = { 1122 .yes_ranges = ksz9477_valid_regs, 1123 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 1124 }; 1125 1126 static const struct regmap_range ksz9896_valid_regs[] = { 1127 regmap_reg_range(0x0000, 0x0003), 1128 regmap_reg_range(0x0006, 0x0006), 1129 regmap_reg_range(0x0010, 0x001f), 1130 regmap_reg_range(0x0100, 0x0100), 1131 regmap_reg_range(0x0103, 0x0107), 1132 regmap_reg_range(0x010d, 0x010d), 1133 regmap_reg_range(0x0110, 0x0113), 1134 regmap_reg_range(0x0120, 0x0127), 1135 regmap_reg_range(0x0201, 0x0201), 1136 regmap_reg_range(0x0210, 0x0213), 1137 regmap_reg_range(0x0300, 0x0300), 1138 regmap_reg_range(0x0302, 0x030b), 1139 regmap_reg_range(0x0310, 0x031b), 1140 regmap_reg_range(0x0320, 0x032b), 1141 regmap_reg_range(0x0330, 0x0336), 1142 regmap_reg_range(0x0338, 0x033b), 1143 regmap_reg_range(0x033e, 0x033e), 1144 regmap_reg_range(0x0340, 0x035f), 1145 regmap_reg_range(0x0370, 0x0370), 1146 regmap_reg_range(0x0378, 0x0378), 1147 regmap_reg_range(0x037c, 0x037d), 1148 regmap_reg_range(0x0390, 0x0393), 1149 regmap_reg_range(0x0400, 0x040e), 1150 regmap_reg_range(0x0410, 0x042f), 1151 1152 /* port 1 */ 1153 regmap_reg_range(0x1000, 0x1001), 1154 regmap_reg_range(0x1013, 0x1013), 1155 regmap_reg_range(0x1017, 0x1017), 1156 regmap_reg_range(0x101b, 0x101b), 1157 regmap_reg_range(0x101f, 0x1020), 1158 regmap_reg_range(0x1030, 0x1030), 1159 regmap_reg_range(0x1100, 0x1115), 1160 regmap_reg_range(0x111a, 0x111f), 1161 regmap_reg_range(0x1120, 0x112b), 1162 regmap_reg_range(0x1134, 0x113b), 1163 regmap_reg_range(0x113c, 0x113f), 1164 regmap_reg_range(0x1400, 0x1401), 1165 regmap_reg_range(0x1403, 0x1403), 1166 regmap_reg_range(0x1410, 0x1417), 1167 regmap_reg_range(0x1420, 0x1423), 1168 regmap_reg_range(0x1500, 0x1507), 1169 regmap_reg_range(0x1600, 0x1612), 1170 regmap_reg_range(0x1800, 0x180f), 1171 regmap_reg_range(0x1820, 0x1827), 1172 regmap_reg_range(0x1830, 0x1837), 1173 regmap_reg_range(0x1840, 0x184b), 1174 regmap_reg_range(0x1900, 0x1907), 1175 regmap_reg_range(0x1914, 0x1915), 1176 regmap_reg_range(0x1a00, 0x1a03), 1177 regmap_reg_range(0x1a04, 0x1a07), 1178 regmap_reg_range(0x1b00, 0x1b01), 1179 regmap_reg_range(0x1b04, 0x1b04), 1180 1181 /* port 2 */ 1182 regmap_reg_range(0x2000, 0x2001), 1183 regmap_reg_range(0x2013, 0x2013), 1184 regmap_reg_range(0x2017, 0x2017), 1185 regmap_reg_range(0x201b, 0x201b), 1186 regmap_reg_range(0x201f, 0x2020), 1187 regmap_reg_range(0x2030, 0x2030), 1188 regmap_reg_range(0x2100, 0x2115), 1189 regmap_reg_range(0x211a, 0x211f), 1190 regmap_reg_range(0x2120, 0x212b), 1191 regmap_reg_range(0x2134, 0x213b), 1192 regmap_reg_range(0x213c, 0x213f), 1193 regmap_reg_range(0x2400, 0x2401), 1194 regmap_reg_range(0x2403, 0x2403), 1195 regmap_reg_range(0x2410, 0x2417), 1196 regmap_reg_range(0x2420, 0x2423), 1197 regmap_reg_range(0x2500, 0x2507), 1198 regmap_reg_range(0x2600, 0x2612), 1199 regmap_reg_range(0x2800, 0x280f), 1200 regmap_reg_range(0x2820, 0x2827), 1201 regmap_reg_range(0x2830, 0x2837), 1202 regmap_reg_range(0x2840, 0x284b), 1203 regmap_reg_range(0x2900, 0x2907), 1204 regmap_reg_range(0x2914, 0x2915), 1205 regmap_reg_range(0x2a00, 0x2a03), 1206 regmap_reg_range(0x2a04, 0x2a07), 1207 regmap_reg_range(0x2b00, 0x2b01), 1208 regmap_reg_range(0x2b04, 0x2b04), 1209 1210 /* port 3 */ 1211 regmap_reg_range(0x3000, 0x3001), 1212 regmap_reg_range(0x3013, 0x3013), 1213 regmap_reg_range(0x3017, 0x3017), 1214 regmap_reg_range(0x301b, 0x301b), 1215 regmap_reg_range(0x301f, 0x3020), 1216 regmap_reg_range(0x3030, 0x3030), 1217 regmap_reg_range(0x3100, 0x3115), 1218 regmap_reg_range(0x311a, 0x311f), 1219 regmap_reg_range(0x3120, 0x312b), 1220 regmap_reg_range(0x3134, 0x313b), 1221 regmap_reg_range(0x313c, 0x313f), 1222 regmap_reg_range(0x3400, 0x3401), 1223 regmap_reg_range(0x3403, 0x3403), 1224 regmap_reg_range(0x3410, 0x3417), 1225 regmap_reg_range(0x3420, 0x3423), 1226 regmap_reg_range(0x3500, 0x3507), 1227 regmap_reg_range(0x3600, 0x3612), 1228 regmap_reg_range(0x3800, 0x380f), 1229 regmap_reg_range(0x3820, 0x3827), 1230 regmap_reg_range(0x3830, 0x3837), 1231 regmap_reg_range(0x3840, 0x384b), 1232 regmap_reg_range(0x3900, 0x3907), 1233 regmap_reg_range(0x3914, 0x3915), 1234 regmap_reg_range(0x3a00, 0x3a03), 1235 regmap_reg_range(0x3a04, 0x3a07), 1236 regmap_reg_range(0x3b00, 0x3b01), 1237 regmap_reg_range(0x3b04, 0x3b04), 1238 1239 /* port 4 */ 1240 regmap_reg_range(0x4000, 0x4001), 1241 regmap_reg_range(0x4013, 0x4013), 1242 regmap_reg_range(0x4017, 0x4017), 1243 regmap_reg_range(0x401b, 0x401b), 1244 regmap_reg_range(0x401f, 0x4020), 1245 regmap_reg_range(0x4030, 0x4030), 1246 regmap_reg_range(0x4100, 0x4115), 1247 regmap_reg_range(0x411a, 0x411f), 1248 regmap_reg_range(0x4120, 0x412b), 1249 regmap_reg_range(0x4134, 0x413b), 1250 regmap_reg_range(0x413c, 0x413f), 1251 regmap_reg_range(0x4400, 0x4401), 1252 regmap_reg_range(0x4403, 0x4403), 1253 regmap_reg_range(0x4410, 0x4417), 1254 regmap_reg_range(0x4420, 0x4423), 1255 regmap_reg_range(0x4500, 0x4507), 1256 regmap_reg_range(0x4600, 0x4612), 1257 regmap_reg_range(0x4800, 0x480f), 1258 regmap_reg_range(0x4820, 0x4827), 1259 regmap_reg_range(0x4830, 0x4837), 1260 regmap_reg_range(0x4840, 0x484b), 1261 regmap_reg_range(0x4900, 0x4907), 1262 regmap_reg_range(0x4914, 0x4915), 1263 regmap_reg_range(0x4a00, 0x4a03), 1264 regmap_reg_range(0x4a04, 0x4a07), 1265 regmap_reg_range(0x4b00, 0x4b01), 1266 regmap_reg_range(0x4b04, 0x4b04), 1267 1268 /* port 5 */ 1269 regmap_reg_range(0x5000, 0x5001), 1270 regmap_reg_range(0x5013, 0x5013), 1271 regmap_reg_range(0x5017, 0x5017), 1272 regmap_reg_range(0x501b, 0x501b), 1273 regmap_reg_range(0x501f, 0x5020), 1274 regmap_reg_range(0x5030, 0x5030), 1275 regmap_reg_range(0x5100, 0x5115), 1276 regmap_reg_range(0x511a, 0x511f), 1277 regmap_reg_range(0x5120, 0x512b), 1278 regmap_reg_range(0x5134, 0x513b), 1279 regmap_reg_range(0x513c, 0x513f), 1280 regmap_reg_range(0x5400, 0x5401), 1281 regmap_reg_range(0x5403, 0x5403), 1282 regmap_reg_range(0x5410, 0x5417), 1283 regmap_reg_range(0x5420, 0x5423), 1284 regmap_reg_range(0x5500, 0x5507), 1285 regmap_reg_range(0x5600, 0x5612), 1286 regmap_reg_range(0x5800, 0x580f), 1287 regmap_reg_range(0x5820, 0x5827), 1288 regmap_reg_range(0x5830, 0x5837), 1289 regmap_reg_range(0x5840, 0x584b), 1290 regmap_reg_range(0x5900, 0x5907), 1291 regmap_reg_range(0x5914, 0x5915), 1292 regmap_reg_range(0x5a00, 0x5a03), 1293 regmap_reg_range(0x5a04, 0x5a07), 1294 regmap_reg_range(0x5b00, 0x5b01), 1295 regmap_reg_range(0x5b04, 0x5b04), 1296 1297 /* port 6 */ 1298 regmap_reg_range(0x6000, 0x6001), 1299 regmap_reg_range(0x6013, 0x6013), 1300 regmap_reg_range(0x6017, 0x6017), 1301 regmap_reg_range(0x601b, 0x601b), 1302 regmap_reg_range(0x601f, 0x6020), 1303 regmap_reg_range(0x6030, 0x6030), 1304 regmap_reg_range(0x6100, 0x6115), 1305 regmap_reg_range(0x611a, 0x611f), 1306 regmap_reg_range(0x6120, 0x612b), 1307 regmap_reg_range(0x6134, 0x613b), 1308 regmap_reg_range(0x613c, 0x613f), 1309 regmap_reg_range(0x6300, 0x6301), 1310 regmap_reg_range(0x6400, 0x6401), 1311 regmap_reg_range(0x6403, 0x6403), 1312 regmap_reg_range(0x6410, 0x6417), 1313 regmap_reg_range(0x6420, 0x6423), 1314 regmap_reg_range(0x6500, 0x6507), 1315 regmap_reg_range(0x6600, 0x6612), 1316 regmap_reg_range(0x6800, 0x680f), 1317 regmap_reg_range(0x6820, 0x6827), 1318 regmap_reg_range(0x6830, 0x6837), 1319 regmap_reg_range(0x6840, 0x684b), 1320 regmap_reg_range(0x6900, 0x6907), 1321 regmap_reg_range(0x6914, 0x6915), 1322 regmap_reg_range(0x6a00, 0x6a03), 1323 regmap_reg_range(0x6a04, 0x6a07), 1324 regmap_reg_range(0x6b00, 0x6b01), 1325 regmap_reg_range(0x6b04, 0x6b04), 1326 }; 1327 1328 static const struct regmap_access_table ksz9896_register_set = { 1329 .yes_ranges = ksz9896_valid_regs, 1330 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1331 }; 1332 1333 static const struct regmap_range ksz8873_valid_regs[] = { 1334 regmap_reg_range(0x00, 0x01), 1335 /* global control register */ 1336 regmap_reg_range(0x02, 0x0f), 1337 1338 /* port registers */ 1339 regmap_reg_range(0x10, 0x1d), 1340 regmap_reg_range(0x1e, 0x1f), 1341 regmap_reg_range(0x20, 0x2d), 1342 regmap_reg_range(0x2e, 0x2f), 1343 regmap_reg_range(0x30, 0x39), 1344 regmap_reg_range(0x3f, 0x3f), 1345 1346 /* advanced control registers */ 1347 regmap_reg_range(0x60, 0x6f), 1348 regmap_reg_range(0x70, 0x75), 1349 regmap_reg_range(0x76, 0x78), 1350 regmap_reg_range(0x79, 0x7a), 1351 regmap_reg_range(0x7b, 0x83), 1352 regmap_reg_range(0x8e, 0x99), 1353 regmap_reg_range(0x9a, 0xa5), 1354 regmap_reg_range(0xa6, 0xa6), 1355 regmap_reg_range(0xa7, 0xaa), 1356 regmap_reg_range(0xab, 0xae), 1357 regmap_reg_range(0xaf, 0xba), 1358 regmap_reg_range(0xbb, 0xbc), 1359 regmap_reg_range(0xbd, 0xbd), 1360 regmap_reg_range(0xc0, 0xc0), 1361 regmap_reg_range(0xc2, 0xc2), 1362 regmap_reg_range(0xc3, 0xc3), 1363 regmap_reg_range(0xc4, 0xc4), 1364 regmap_reg_range(0xc6, 0xc6), 1365 }; 1366 1367 static const struct regmap_access_table ksz8873_register_set = { 1368 .yes_ranges = ksz8873_valid_regs, 1369 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), 1370 }; 1371 1372 const struct ksz_chip_data ksz_switch_chips[] = { 1373 [KSZ8563] = { 1374 .chip_id = KSZ8563_CHIP_ID, 1375 .dev_name = "KSZ8563", 1376 .num_vlans = 4096, 1377 .num_alus = 4096, 1378 .num_statics = 16, 1379 .cpu_ports = 0x07, /* can be configured as cpu port */ 1380 .port_cnt = 3, /* total port count */ 1381 .port_nirqs = 3, 1382 .num_tx_queues = 4, 1383 .num_ipms = 8, 1384 .tc_cbs_supported = true, 1385 .ops = &ksz9477_dev_ops, 1386 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1387 .mib_names = ksz9477_mib_names, 1388 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1389 .reg_mib_cnt = MIB_COUNTER_NUM, 1390 .regs = ksz9477_regs, 1391 .masks = ksz9477_masks, 1392 .shifts = ksz9477_shifts, 1393 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1394 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1395 .supports_mii = {false, false, true}, 1396 .supports_rmii = {false, false, true}, 1397 .supports_rgmii = {false, false, true}, 1398 .internal_phy = {true, true, false}, 1399 .gbit_capable = {false, false, true}, 1400 .ptp_capable = true, 1401 .wr_table = &ksz8563_register_set, 1402 .rd_table = &ksz8563_register_set, 1403 }, 1404 1405 [KSZ8795] = { 1406 .chip_id = KSZ8795_CHIP_ID, 1407 .dev_name = "KSZ8795", 1408 .num_vlans = 4096, 1409 .num_alus = 0, 1410 .num_statics = 32, 1411 .cpu_ports = 0x10, /* can be configured as cpu port */ 1412 .port_cnt = 5, /* total cpu and user ports */ 1413 .num_tx_queues = 4, 1414 .num_ipms = 4, 1415 .ops = &ksz87xx_dev_ops, 1416 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1417 .ksz87xx_eee_link_erratum = true, 1418 .mib_names = ksz9477_mib_names, 1419 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1420 .reg_mib_cnt = MIB_COUNTER_NUM, 1421 .regs = ksz8795_regs, 1422 .masks = ksz8795_masks, 1423 .shifts = ksz8795_shifts, 1424 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1425 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1426 .supports_mii = {false, false, false, false, true}, 1427 .supports_rmii = {false, false, false, false, true}, 1428 .supports_rgmii = {false, false, false, false, true}, 1429 .internal_phy = {true, true, true, true, false}, 1430 }, 1431 1432 [KSZ8794] = { 1433 /* WARNING 1434 * ======= 1435 * KSZ8794 is similar to KSZ8795, except the port map 1436 * contains a gap between external and CPU ports, the 1437 * port map is NOT continuous. The per-port register 1438 * map is shifted accordingly too, i.e. registers at 1439 * offset 0x40 are NOT used on KSZ8794 and they ARE 1440 * used on KSZ8795 for external port 3. 1441 * external cpu 1442 * KSZ8794 0,1,2 4 1443 * KSZ8795 0,1,2,3 4 1444 * KSZ8765 0,1,2,3 4 1445 * port_cnt is configured as 5, even though it is 4 1446 */ 1447 .chip_id = KSZ8794_CHIP_ID, 1448 .dev_name = "KSZ8794", 1449 .num_vlans = 4096, 1450 .num_alus = 0, 1451 .num_statics = 32, 1452 .cpu_ports = 0x10, /* can be configured as cpu port */ 1453 .port_cnt = 5, /* total cpu and user ports */ 1454 .num_tx_queues = 4, 1455 .num_ipms = 4, 1456 .ops = &ksz87xx_dev_ops, 1457 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1458 .ksz87xx_eee_link_erratum = true, 1459 .mib_names = ksz9477_mib_names, 1460 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1461 .reg_mib_cnt = MIB_COUNTER_NUM, 1462 .regs = ksz8795_regs, 1463 .masks = ksz8795_masks, 1464 .shifts = ksz8795_shifts, 1465 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1466 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1467 .supports_mii = {false, false, false, false, true}, 1468 .supports_rmii = {false, false, false, false, true}, 1469 .supports_rgmii = {false, false, false, false, true}, 1470 .internal_phy = {true, true, true, false, false}, 1471 }, 1472 1473 [KSZ8765] = { 1474 .chip_id = KSZ8765_CHIP_ID, 1475 .dev_name = "KSZ8765", 1476 .num_vlans = 4096, 1477 .num_alus = 0, 1478 .num_statics = 32, 1479 .cpu_ports = 0x10, /* can be configured as cpu port */ 1480 .port_cnt = 5, /* total cpu and user ports */ 1481 .num_tx_queues = 4, 1482 .num_ipms = 4, 1483 .ops = &ksz87xx_dev_ops, 1484 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1485 .ksz87xx_eee_link_erratum = true, 1486 .mib_names = ksz9477_mib_names, 1487 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1488 .reg_mib_cnt = MIB_COUNTER_NUM, 1489 .regs = ksz8795_regs, 1490 .masks = ksz8795_masks, 1491 .shifts = ksz8795_shifts, 1492 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1493 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1494 .supports_mii = {false, false, false, false, true}, 1495 .supports_rmii = {false, false, false, false, true}, 1496 .supports_rgmii = {false, false, false, false, true}, 1497 .internal_phy = {true, true, true, true, false}, 1498 }, 1499 1500 [KSZ88X3] = { 1501 .chip_id = KSZ88X3_CHIP_ID, 1502 .dev_name = "KSZ8863/KSZ8873", 1503 .num_vlans = 16, 1504 .num_alus = 0, 1505 .num_statics = 8, 1506 .cpu_ports = 0x4, /* can be configured as cpu port */ 1507 .port_cnt = 3, 1508 .num_tx_queues = 4, 1509 .num_ipms = 4, 1510 .ops = &ksz88xx_dev_ops, 1511 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1512 .mib_names = ksz88xx_mib_names, 1513 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1514 .reg_mib_cnt = MIB_COUNTER_NUM, 1515 .regs = ksz8863_regs, 1516 .masks = ksz8863_masks, 1517 .shifts = ksz8863_shifts, 1518 .supports_mii = {false, false, true}, 1519 .supports_rmii = {false, false, true}, 1520 .internal_phy = {true, true, false}, 1521 .wr_table = &ksz8873_register_set, 1522 .rd_table = &ksz8873_register_set, 1523 }, 1524 1525 [KSZ8864] = { 1526 /* WARNING 1527 * ======= 1528 * KSZ8864 is similar to KSZ8895, except the first port 1529 * does not exist. 1530 * external cpu 1531 * KSZ8864 1,2,3 4 1532 * KSZ8895 0,1,2,3 4 1533 * port_cnt is configured as 5, even though it is 4 1534 */ 1535 .chip_id = KSZ8864_CHIP_ID, 1536 .dev_name = "KSZ8864", 1537 .num_vlans = 4096, 1538 .num_alus = 0, 1539 .num_statics = 32, 1540 .cpu_ports = 0x10, /* can be configured as cpu port */ 1541 .port_cnt = 5, /* total cpu and user ports */ 1542 .num_tx_queues = 4, 1543 .num_ipms = 4, 1544 .ops = &ksz88xx_dev_ops, 1545 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1546 .mib_names = ksz88xx_mib_names, 1547 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1548 .reg_mib_cnt = MIB_COUNTER_NUM, 1549 .regs = ksz8895_regs, 1550 .masks = ksz8895_masks, 1551 .shifts = ksz8895_shifts, 1552 .supports_mii = {false, false, false, false, true}, 1553 .supports_rmii = {false, false, false, false, true}, 1554 .internal_phy = {false, true, true, true, false}, 1555 }, 1556 1557 [KSZ8895] = { 1558 .chip_id = KSZ8895_CHIP_ID, 1559 .dev_name = "KSZ8895", 1560 .num_vlans = 4096, 1561 .num_alus = 0, 1562 .num_statics = 32, 1563 .cpu_ports = 0x10, /* can be configured as cpu port */ 1564 .port_cnt = 5, /* total cpu and user ports */ 1565 .num_tx_queues = 4, 1566 .num_ipms = 4, 1567 .ops = &ksz88xx_dev_ops, 1568 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1569 .mib_names = ksz88xx_mib_names, 1570 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1571 .reg_mib_cnt = MIB_COUNTER_NUM, 1572 .regs = ksz8895_regs, 1573 .masks = ksz8895_masks, 1574 .shifts = ksz8895_shifts, 1575 .supports_mii = {false, false, false, false, true}, 1576 .supports_rmii = {false, false, false, false, true}, 1577 .internal_phy = {true, true, true, true, false}, 1578 }, 1579 1580 [KSZ9477] = { 1581 .chip_id = KSZ9477_CHIP_ID, 1582 .dev_name = "KSZ9477", 1583 .num_vlans = 4096, 1584 .num_alus = 4096, 1585 .num_statics = 16, 1586 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1587 .port_cnt = 7, /* total physical port count */ 1588 .port_nirqs = 4, 1589 .num_tx_queues = 4, 1590 .num_ipms = 8, 1591 .tc_cbs_supported = true, 1592 .ops = &ksz9477_dev_ops, 1593 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1594 .phy_errata_9477 = true, 1595 .mib_names = ksz9477_mib_names, 1596 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1597 .reg_mib_cnt = MIB_COUNTER_NUM, 1598 .regs = ksz9477_regs, 1599 .masks = ksz9477_masks, 1600 .shifts = ksz9477_shifts, 1601 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1602 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1603 .supports_mii = {false, false, false, false, 1604 false, true, false}, 1605 .supports_rmii = {false, false, false, false, 1606 false, true, false}, 1607 .supports_rgmii = {false, false, false, false, 1608 false, true, false}, 1609 .internal_phy = {true, true, true, true, 1610 true, false, false}, 1611 .gbit_capable = {true, true, true, true, true, true, true}, 1612 .ptp_capable = true, 1613 .wr_table = &ksz9477_register_set, 1614 .rd_table = &ksz9477_register_set, 1615 }, 1616 1617 [KSZ9896] = { 1618 .chip_id = KSZ9896_CHIP_ID, 1619 .dev_name = "KSZ9896", 1620 .num_vlans = 4096, 1621 .num_alus = 4096, 1622 .num_statics = 16, 1623 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1624 .port_cnt = 6, /* total physical port count */ 1625 .port_nirqs = 2, 1626 .num_tx_queues = 4, 1627 .num_ipms = 8, 1628 .ops = &ksz9477_dev_ops, 1629 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1630 .phy_errata_9477 = true, 1631 .mib_names = ksz9477_mib_names, 1632 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1633 .reg_mib_cnt = MIB_COUNTER_NUM, 1634 .regs = ksz9477_regs, 1635 .masks = ksz9477_masks, 1636 .shifts = ksz9477_shifts, 1637 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1638 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1639 .supports_mii = {false, false, false, false, 1640 false, true}, 1641 .supports_rmii = {false, false, false, false, 1642 false, true}, 1643 .supports_rgmii = {false, false, false, false, 1644 false, true}, 1645 .internal_phy = {true, true, true, true, 1646 true, false}, 1647 .gbit_capable = {true, true, true, true, true, true}, 1648 .wr_table = &ksz9896_register_set, 1649 .rd_table = &ksz9896_register_set, 1650 }, 1651 1652 [KSZ9897] = { 1653 .chip_id = KSZ9897_CHIP_ID, 1654 .dev_name = "KSZ9897", 1655 .num_vlans = 4096, 1656 .num_alus = 4096, 1657 .num_statics = 16, 1658 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1659 .port_cnt = 7, /* total physical port count */ 1660 .port_nirqs = 2, 1661 .num_tx_queues = 4, 1662 .num_ipms = 8, 1663 .ops = &ksz9477_dev_ops, 1664 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1665 .phy_errata_9477 = true, 1666 .mib_names = ksz9477_mib_names, 1667 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1668 .reg_mib_cnt = MIB_COUNTER_NUM, 1669 .regs = ksz9477_regs, 1670 .masks = ksz9477_masks, 1671 .shifts = ksz9477_shifts, 1672 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1673 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1674 .supports_mii = {false, false, false, false, 1675 false, true, true}, 1676 .supports_rmii = {false, false, false, false, 1677 false, true, true}, 1678 .supports_rgmii = {false, false, false, false, 1679 false, true, true}, 1680 .internal_phy = {true, true, true, true, 1681 true, false, false}, 1682 .gbit_capable = {true, true, true, true, true, true, true}, 1683 }, 1684 1685 [KSZ9893] = { 1686 .chip_id = KSZ9893_CHIP_ID, 1687 .dev_name = "KSZ9893", 1688 .num_vlans = 4096, 1689 .num_alus = 4096, 1690 .num_statics = 16, 1691 .cpu_ports = 0x07, /* can be configured as cpu port */ 1692 .port_cnt = 3, /* total port count */ 1693 .port_nirqs = 2, 1694 .num_tx_queues = 4, 1695 .num_ipms = 8, 1696 .ops = &ksz9477_dev_ops, 1697 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1698 .mib_names = ksz9477_mib_names, 1699 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1700 .reg_mib_cnt = MIB_COUNTER_NUM, 1701 .regs = ksz9477_regs, 1702 .masks = ksz9477_masks, 1703 .shifts = ksz9477_shifts, 1704 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1705 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1706 .supports_mii = {false, false, true}, 1707 .supports_rmii = {false, false, true}, 1708 .supports_rgmii = {false, false, true}, 1709 .internal_phy = {true, true, false}, 1710 .gbit_capable = {true, true, true}, 1711 }, 1712 1713 [KSZ9563] = { 1714 .chip_id = KSZ9563_CHIP_ID, 1715 .dev_name = "KSZ9563", 1716 .num_vlans = 4096, 1717 .num_alus = 4096, 1718 .num_statics = 16, 1719 .cpu_ports = 0x07, /* can be configured as cpu port */ 1720 .port_cnt = 3, /* total port count */ 1721 .port_nirqs = 3, 1722 .num_tx_queues = 4, 1723 .num_ipms = 8, 1724 .tc_cbs_supported = true, 1725 .ops = &ksz9477_dev_ops, 1726 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1727 .mib_names = ksz9477_mib_names, 1728 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1729 .reg_mib_cnt = MIB_COUNTER_NUM, 1730 .regs = ksz9477_regs, 1731 .masks = ksz9477_masks, 1732 .shifts = ksz9477_shifts, 1733 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1734 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1735 .supports_mii = {false, false, true}, 1736 .supports_rmii = {false, false, true}, 1737 .supports_rgmii = {false, false, true}, 1738 .internal_phy = {true, true, false}, 1739 .gbit_capable = {true, true, true}, 1740 .ptp_capable = true, 1741 }, 1742 1743 [KSZ8567] = { 1744 .chip_id = KSZ8567_CHIP_ID, 1745 .dev_name = "KSZ8567", 1746 .num_vlans = 4096, 1747 .num_alus = 4096, 1748 .num_statics = 16, 1749 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1750 .port_cnt = 7, /* total port count */ 1751 .port_nirqs = 3, 1752 .num_tx_queues = 4, 1753 .num_ipms = 8, 1754 .tc_cbs_supported = true, 1755 .ops = &ksz9477_dev_ops, 1756 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1757 .phy_errata_9477 = true, 1758 .mib_names = ksz9477_mib_names, 1759 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1760 .reg_mib_cnt = MIB_COUNTER_NUM, 1761 .regs = ksz9477_regs, 1762 .masks = ksz9477_masks, 1763 .shifts = ksz9477_shifts, 1764 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1765 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1766 .supports_mii = {false, false, false, false, 1767 false, true, true}, 1768 .supports_rmii = {false, false, false, false, 1769 false, true, true}, 1770 .supports_rgmii = {false, false, false, false, 1771 false, true, true}, 1772 .internal_phy = {true, true, true, true, 1773 true, false, false}, 1774 .gbit_capable = {false, false, false, false, false, 1775 true, true}, 1776 .ptp_capable = true, 1777 }, 1778 1779 [KSZ9567] = { 1780 .chip_id = KSZ9567_CHIP_ID, 1781 .dev_name = "KSZ9567", 1782 .num_vlans = 4096, 1783 .num_alus = 4096, 1784 .num_statics = 16, 1785 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1786 .port_cnt = 7, /* total physical port count */ 1787 .port_nirqs = 3, 1788 .num_tx_queues = 4, 1789 .num_ipms = 8, 1790 .tc_cbs_supported = true, 1791 .ops = &ksz9477_dev_ops, 1792 .mib_names = ksz9477_mib_names, 1793 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1794 .reg_mib_cnt = MIB_COUNTER_NUM, 1795 .regs = ksz9477_regs, 1796 .masks = ksz9477_masks, 1797 .shifts = ksz9477_shifts, 1798 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1799 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1800 .supports_mii = {false, false, false, false, 1801 false, true, true}, 1802 .supports_rmii = {false, false, false, false, 1803 false, true, true}, 1804 .supports_rgmii = {false, false, false, false, 1805 false, true, true}, 1806 .internal_phy = {true, true, true, true, 1807 true, false, false}, 1808 .gbit_capable = {true, true, true, true, true, true, true}, 1809 .ptp_capable = true, 1810 }, 1811 1812 [LAN9370] = { 1813 .chip_id = LAN9370_CHIP_ID, 1814 .dev_name = "LAN9370", 1815 .num_vlans = 4096, 1816 .num_alus = 1024, 1817 .num_statics = 256, 1818 .cpu_ports = 0x10, /* can be configured as cpu port */ 1819 .port_cnt = 5, /* total physical port count */ 1820 .port_nirqs = 6, 1821 .num_tx_queues = 8, 1822 .num_ipms = 8, 1823 .tc_cbs_supported = true, 1824 .phy_side_mdio_supported = true, 1825 .ops = &lan937x_dev_ops, 1826 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1827 .mib_names = ksz9477_mib_names, 1828 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1829 .reg_mib_cnt = MIB_COUNTER_NUM, 1830 .regs = ksz9477_regs, 1831 .masks = lan937x_masks, 1832 .shifts = lan937x_shifts, 1833 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1834 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1835 .supports_mii = {false, false, false, false, true}, 1836 .supports_rmii = {false, false, false, false, true}, 1837 .supports_rgmii = {false, false, false, false, true}, 1838 .internal_phy = {true, true, true, true, false}, 1839 .ptp_capable = true, 1840 }, 1841 1842 [LAN9371] = { 1843 .chip_id = LAN9371_CHIP_ID, 1844 .dev_name = "LAN9371", 1845 .num_vlans = 4096, 1846 .num_alus = 1024, 1847 .num_statics = 256, 1848 .cpu_ports = 0x30, /* can be configured as cpu port */ 1849 .port_cnt = 6, /* total physical port count */ 1850 .port_nirqs = 6, 1851 .num_tx_queues = 8, 1852 .num_ipms = 8, 1853 .tc_cbs_supported = true, 1854 .phy_side_mdio_supported = true, 1855 .ops = &lan937x_dev_ops, 1856 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1857 .mib_names = ksz9477_mib_names, 1858 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1859 .reg_mib_cnt = MIB_COUNTER_NUM, 1860 .regs = ksz9477_regs, 1861 .masks = lan937x_masks, 1862 .shifts = lan937x_shifts, 1863 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1864 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1865 .supports_mii = {false, false, false, false, true, true}, 1866 .supports_rmii = {false, false, false, false, true, true}, 1867 .supports_rgmii = {false, false, false, false, true, true}, 1868 .internal_phy = {true, true, true, true, false, false}, 1869 .ptp_capable = true, 1870 }, 1871 1872 [LAN9372] = { 1873 .chip_id = LAN9372_CHIP_ID, 1874 .dev_name = "LAN9372", 1875 .num_vlans = 4096, 1876 .num_alus = 1024, 1877 .num_statics = 256, 1878 .cpu_ports = 0x30, /* can be configured as cpu port */ 1879 .port_cnt = 8, /* total physical port count */ 1880 .port_nirqs = 6, 1881 .num_tx_queues = 8, 1882 .num_ipms = 8, 1883 .tc_cbs_supported = true, 1884 .phy_side_mdio_supported = true, 1885 .ops = &lan937x_dev_ops, 1886 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1887 .mib_names = ksz9477_mib_names, 1888 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1889 .reg_mib_cnt = MIB_COUNTER_NUM, 1890 .regs = ksz9477_regs, 1891 .masks = lan937x_masks, 1892 .shifts = lan937x_shifts, 1893 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1894 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1895 .supports_mii = {false, false, false, false, 1896 true, true, false, false}, 1897 .supports_rmii = {false, false, false, false, 1898 true, true, false, false}, 1899 .supports_rgmii = {false, false, false, false, 1900 true, true, false, false}, 1901 .internal_phy = {true, true, true, true, 1902 false, false, true, true}, 1903 .ptp_capable = true, 1904 }, 1905 1906 [LAN9373] = { 1907 .chip_id = LAN9373_CHIP_ID, 1908 .dev_name = "LAN9373", 1909 .num_vlans = 4096, 1910 .num_alus = 1024, 1911 .num_statics = 256, 1912 .cpu_ports = 0x38, /* can be configured as cpu port */ 1913 .port_cnt = 5, /* total physical port count */ 1914 .port_nirqs = 6, 1915 .num_tx_queues = 8, 1916 .num_ipms = 8, 1917 .tc_cbs_supported = true, 1918 .phy_side_mdio_supported = true, 1919 .ops = &lan937x_dev_ops, 1920 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1921 .mib_names = ksz9477_mib_names, 1922 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1923 .reg_mib_cnt = MIB_COUNTER_NUM, 1924 .regs = ksz9477_regs, 1925 .masks = lan937x_masks, 1926 .shifts = lan937x_shifts, 1927 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1928 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1929 .supports_mii = {false, false, false, false, 1930 true, true, false, false}, 1931 .supports_rmii = {false, false, false, false, 1932 true, true, false, false}, 1933 .supports_rgmii = {false, false, false, false, 1934 true, true, false, false}, 1935 .internal_phy = {true, true, true, false, 1936 false, false, true, true}, 1937 .ptp_capable = true, 1938 }, 1939 1940 [LAN9374] = { 1941 .chip_id = LAN9374_CHIP_ID, 1942 .dev_name = "LAN9374", 1943 .num_vlans = 4096, 1944 .num_alus = 1024, 1945 .num_statics = 256, 1946 .cpu_ports = 0x30, /* can be configured as cpu port */ 1947 .port_cnt = 8, /* total physical port count */ 1948 .port_nirqs = 6, 1949 .num_tx_queues = 8, 1950 .num_ipms = 8, 1951 .tc_cbs_supported = true, 1952 .phy_side_mdio_supported = true, 1953 .ops = &lan937x_dev_ops, 1954 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1955 .mib_names = ksz9477_mib_names, 1956 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1957 .reg_mib_cnt = MIB_COUNTER_NUM, 1958 .regs = ksz9477_regs, 1959 .masks = lan937x_masks, 1960 .shifts = lan937x_shifts, 1961 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1962 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1963 .supports_mii = {false, false, false, false, 1964 true, true, false, false}, 1965 .supports_rmii = {false, false, false, false, 1966 true, true, false, false}, 1967 .supports_rgmii = {false, false, false, false, 1968 true, true, false, false}, 1969 .internal_phy = {true, true, true, true, 1970 false, false, true, true}, 1971 .ptp_capable = true, 1972 }, 1973 1974 [LAN9646] = { 1975 .chip_id = LAN9646_CHIP_ID, 1976 .dev_name = "LAN9646", 1977 .num_vlans = 4096, 1978 .num_alus = 4096, 1979 .num_statics = 16, 1980 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1981 .port_cnt = 7, /* total physical port count */ 1982 .port_nirqs = 4, 1983 .num_tx_queues = 4, 1984 .num_ipms = 8, 1985 .ops = &ksz9477_dev_ops, 1986 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1987 .phy_errata_9477 = true, 1988 .mib_names = ksz9477_mib_names, 1989 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1990 .reg_mib_cnt = MIB_COUNTER_NUM, 1991 .regs = ksz9477_regs, 1992 .masks = ksz9477_masks, 1993 .shifts = ksz9477_shifts, 1994 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1995 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1996 .supports_mii = {false, false, false, false, 1997 false, true, true}, 1998 .supports_rmii = {false, false, false, false, 1999 false, true, true}, 2000 .supports_rgmii = {false, false, false, false, 2001 false, true, true}, 2002 .internal_phy = {true, true, true, true, 2003 true, false, false}, 2004 .gbit_capable = {true, true, true, true, true, true, true}, 2005 .wr_table = &ksz9477_register_set, 2006 .rd_table = &ksz9477_register_set, 2007 }, 2008 }; 2009 EXPORT_SYMBOL_GPL(ksz_switch_chips); 2010 2011 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 2012 { 2013 int i; 2014 2015 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 2016 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 2017 2018 if (chip->chip_id == prod_num) 2019 return chip; 2020 } 2021 2022 return NULL; 2023 } 2024 2025 static int ksz_check_device_id(struct ksz_device *dev) 2026 { 2027 const struct ksz_chip_data *expected_chip_data; 2028 u32 expected_chip_id; 2029 2030 if (dev->pdata) { 2031 expected_chip_id = dev->pdata->chip_id; 2032 expected_chip_data = ksz_lookup_info(expected_chip_id); 2033 if (WARN_ON(!expected_chip_data)) 2034 return -ENODEV; 2035 } else { 2036 expected_chip_data = of_device_get_match_data(dev->dev); 2037 expected_chip_id = expected_chip_data->chip_id; 2038 } 2039 2040 if (expected_chip_id != dev->chip_id) { 2041 dev_err(dev->dev, 2042 "Device tree specifies chip %s but found %s, please fix it!\n", 2043 expected_chip_data->dev_name, dev->info->dev_name); 2044 return -ENODEV; 2045 } 2046 2047 return 0; 2048 } 2049 2050 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 2051 struct phylink_config *config) 2052 { 2053 struct ksz_device *dev = ds->priv; 2054 2055 if (dev->info->supports_mii[port]) 2056 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 2057 2058 if (dev->info->supports_rmii[port]) 2059 __set_bit(PHY_INTERFACE_MODE_RMII, 2060 config->supported_interfaces); 2061 2062 if (dev->info->supports_rgmii[port]) 2063 phy_interface_set_rgmii(config->supported_interfaces); 2064 2065 if (dev->info->internal_phy[port]) { 2066 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2067 config->supported_interfaces); 2068 /* Compatibility for phylib's default interface type when the 2069 * phy-mode property is absent 2070 */ 2071 __set_bit(PHY_INTERFACE_MODE_GMII, 2072 config->supported_interfaces); 2073 } 2074 2075 if (dev->dev_ops->get_caps) 2076 dev->dev_ops->get_caps(dev, port, config); 2077 2078 if (ds->ops->support_eee && ds->ops->support_eee(ds, port)) { 2079 memcpy(config->lpi_interfaces, config->supported_interfaces, 2080 sizeof(config->lpi_interfaces)); 2081 2082 config->lpi_capabilities = MAC_100FD; 2083 if (dev->info->gbit_capable[port]) 2084 config->lpi_capabilities |= MAC_1000FD; 2085 2086 /* EEE is fully operational */ 2087 config->eee_enabled_default = true; 2088 } 2089 } 2090 2091 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 2092 { 2093 struct ethtool_pause_stats *pstats; 2094 struct rtnl_link_stats64 *stats; 2095 struct ksz_stats_raw *raw; 2096 struct ksz_port_mib *mib; 2097 int ret; 2098 2099 mib = &dev->ports[port].mib; 2100 stats = &mib->stats64; 2101 pstats = &mib->pause_stats; 2102 raw = (struct ksz_stats_raw *)mib->counters; 2103 2104 spin_lock(&mib->stats64_lock); 2105 2106 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 2107 raw->rx_pause; 2108 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2109 raw->tx_pause; 2110 2111 /* HW counters are counting bytes + FCS which is not acceptable 2112 * for rtnl_link_stats64 interface 2113 */ 2114 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 2115 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 2116 2117 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2118 raw->rx_oversize; 2119 2120 stats->rx_crc_errors = raw->rx_crc_err; 2121 stats->rx_frame_errors = raw->rx_align_err; 2122 stats->rx_dropped = raw->rx_discards; 2123 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2124 stats->rx_frame_errors + stats->rx_dropped; 2125 2126 stats->tx_window_errors = raw->tx_late_col; 2127 stats->tx_fifo_errors = raw->tx_discards; 2128 stats->tx_aborted_errors = raw->tx_exc_col; 2129 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2130 stats->tx_aborted_errors; 2131 2132 stats->multicast = raw->rx_mcast; 2133 stats->collisions = raw->tx_total_col; 2134 2135 pstats->tx_pause_frames = raw->tx_pause; 2136 pstats->rx_pause_frames = raw->rx_pause; 2137 2138 spin_unlock(&mib->stats64_lock); 2139 2140 if (dev->info->phy_errata_9477) { 2141 ret = ksz9477_errata_monitor(dev, port, raw->tx_late_col); 2142 if (ret) 2143 dev_err(dev->dev, "Failed to monitor transmission halt\n"); 2144 } 2145 } 2146 2147 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 2148 { 2149 struct ethtool_pause_stats *pstats; 2150 struct rtnl_link_stats64 *stats; 2151 struct ksz88xx_stats_raw *raw; 2152 struct ksz_port_mib *mib; 2153 2154 mib = &dev->ports[port].mib; 2155 stats = &mib->stats64; 2156 pstats = &mib->pause_stats; 2157 raw = (struct ksz88xx_stats_raw *)mib->counters; 2158 2159 spin_lock(&mib->stats64_lock); 2160 2161 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 2162 raw->rx_pause; 2163 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2164 raw->tx_pause; 2165 2166 /* HW counters are counting bytes + FCS which is not acceptable 2167 * for rtnl_link_stats64 interface 2168 */ 2169 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 2170 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 2171 2172 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2173 raw->rx_oversize; 2174 2175 stats->rx_crc_errors = raw->rx_crc_err; 2176 stats->rx_frame_errors = raw->rx_align_err; 2177 stats->rx_dropped = raw->rx_discards; 2178 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2179 stats->rx_frame_errors + stats->rx_dropped; 2180 2181 stats->tx_window_errors = raw->tx_late_col; 2182 stats->tx_fifo_errors = raw->tx_discards; 2183 stats->tx_aborted_errors = raw->tx_exc_col; 2184 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2185 stats->tx_aborted_errors; 2186 2187 stats->multicast = raw->rx_mcast; 2188 stats->collisions = raw->tx_total_col; 2189 2190 pstats->tx_pause_frames = raw->tx_pause; 2191 pstats->rx_pause_frames = raw->rx_pause; 2192 2193 spin_unlock(&mib->stats64_lock); 2194 } 2195 2196 static void ksz_get_stats64(struct dsa_switch *ds, int port, 2197 struct rtnl_link_stats64 *s) 2198 { 2199 struct ksz_device *dev = ds->priv; 2200 struct ksz_port_mib *mib; 2201 2202 mib = &dev->ports[port].mib; 2203 2204 spin_lock(&mib->stats64_lock); 2205 memcpy(s, &mib->stats64, sizeof(*s)); 2206 spin_unlock(&mib->stats64_lock); 2207 } 2208 2209 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 2210 struct ethtool_pause_stats *pause_stats) 2211 { 2212 struct ksz_device *dev = ds->priv; 2213 struct ksz_port_mib *mib; 2214 2215 mib = &dev->ports[port].mib; 2216 2217 spin_lock(&mib->stats64_lock); 2218 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 2219 spin_unlock(&mib->stats64_lock); 2220 } 2221 2222 static void ksz_get_strings(struct dsa_switch *ds, int port, 2223 u32 stringset, uint8_t *buf) 2224 { 2225 struct ksz_device *dev = ds->priv; 2226 int i; 2227 2228 if (stringset != ETH_SS_STATS) 2229 return; 2230 2231 for (i = 0; i < dev->info->mib_cnt; i++) 2232 ethtool_puts(&buf, dev->info->mib_names[i].string); 2233 } 2234 2235 /** 2236 * ksz_update_port_member - Adjust port forwarding rules based on STP state and 2237 * isolation settings. 2238 * @dev: A pointer to the struct ksz_device representing the device. 2239 * @port: The port number to adjust. 2240 * 2241 * This function dynamically adjusts the port membership configuration for a 2242 * specified port and other device ports, based on Spanning Tree Protocol (STP) 2243 * states and port isolation settings. Each port, including the CPU port, has a 2244 * membership register, represented as a bitfield, where each bit corresponds 2245 * to a port number. A set bit indicates permission to forward frames to that 2246 * port. This function iterates over all ports, updating the membership register 2247 * to reflect current forwarding permissions: 2248 * 2249 * 1. Forwards frames only to ports that are part of the same bridge group and 2250 * in the BR_STATE_FORWARDING state. 2251 * 2. Takes into account the isolation status of ports; ports in the 2252 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward 2253 * frames to each other, even if they are in the same bridge group. 2254 * 3. Ensures that the CPU port is included in the membership based on its 2255 * upstream port configuration, allowing for management and control traffic 2256 * to flow as required. 2257 */ 2258 static void ksz_update_port_member(struct ksz_device *dev, int port) 2259 { 2260 struct ksz_port *p = &dev->ports[port]; 2261 struct dsa_switch *ds = dev->ds; 2262 u8 port_member = 0, cpu_port; 2263 const struct dsa_port *dp; 2264 int i, j; 2265 2266 if (!dsa_is_user_port(ds, port)) 2267 return; 2268 2269 dp = dsa_to_port(ds, port); 2270 cpu_port = BIT(dsa_upstream_port(ds, port)); 2271 2272 for (i = 0; i < ds->num_ports; i++) { 2273 const struct dsa_port *other_dp = dsa_to_port(ds, i); 2274 struct ksz_port *other_p = &dev->ports[i]; 2275 u8 val = 0; 2276 2277 if (!dsa_is_user_port(ds, i)) 2278 continue; 2279 if (port == i) 2280 continue; 2281 if (!dsa_port_bridge_same(dp, other_dp)) 2282 continue; 2283 if (other_p->stp_state != BR_STATE_FORWARDING) 2284 continue; 2285 2286 /* At this point we know that "port" and "other" port [i] are in 2287 * the same bridge group and that "other" port [i] is in 2288 * forwarding stp state. If "port" is also in forwarding stp 2289 * state, we can allow forwarding from port [port] to port [i]. 2290 * Except if both ports are isolated. 2291 */ 2292 if (p->stp_state == BR_STATE_FORWARDING && 2293 !(p->isolated && other_p->isolated)) { 2294 val |= BIT(port); 2295 port_member |= BIT(i); 2296 } 2297 2298 /* Retain port [i]'s relationship to other ports than [port] */ 2299 for (j = 0; j < ds->num_ports; j++) { 2300 const struct dsa_port *third_dp; 2301 struct ksz_port *third_p; 2302 2303 if (j == i) 2304 continue; 2305 if (j == port) 2306 continue; 2307 if (!dsa_is_user_port(ds, j)) 2308 continue; 2309 third_p = &dev->ports[j]; 2310 if (third_p->stp_state != BR_STATE_FORWARDING) 2311 continue; 2312 2313 third_dp = dsa_to_port(ds, j); 2314 2315 /* Now we updating relation of the "other" port [i] to 2316 * the "third" port [j]. We already know that "other" 2317 * port [i] is in forwarding stp state and that "third" 2318 * port [j] is in forwarding stp state too. 2319 * We need to check if "other" port [i] and "third" port 2320 * [j] are in the same bridge group and not isolated 2321 * before allowing forwarding from port [i] to port [j]. 2322 */ 2323 if (dsa_port_bridge_same(other_dp, third_dp) && 2324 !(other_p->isolated && third_p->isolated)) 2325 val |= BIT(j); 2326 } 2327 2328 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 2329 } 2330 2331 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 2332 } 2333 2334 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 2335 { 2336 struct ksz_device *dev = bus->priv; 2337 u16 val; 2338 int ret; 2339 2340 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 2341 if (ret < 0) 2342 return ret; 2343 2344 return val; 2345 } 2346 2347 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 2348 u16 val) 2349 { 2350 struct ksz_device *dev = bus->priv; 2351 2352 return dev->dev_ops->w_phy(dev, addr, regnum, val); 2353 } 2354 2355 /** 2356 * ksz_parent_mdio_read - Read data from a PHY register on the parent MDIO bus. 2357 * @bus: MDIO bus structure. 2358 * @addr: PHY address on the parent MDIO bus. 2359 * @regnum: Register number to read. 2360 * 2361 * This function provides a direct read operation on the parent MDIO bus for 2362 * accessing PHY registers. By bypassing SPI or I2C, it uses the parent MDIO bus 2363 * to retrieve data from the PHY registers at the specified address and register 2364 * number. 2365 * 2366 * Return: Value of the PHY register, or a negative error code on failure. 2367 */ 2368 static int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum) 2369 { 2370 struct ksz_device *dev = bus->priv; 2371 2372 return mdiobus_read_nested(dev->parent_mdio_bus, addr, regnum); 2373 } 2374 2375 /** 2376 * ksz_parent_mdio_write - Write data to a PHY register on the parent MDIO bus. 2377 * @bus: MDIO bus structure. 2378 * @addr: PHY address on the parent MDIO bus. 2379 * @regnum: Register number to write to. 2380 * @val: Value to write to the PHY register. 2381 * 2382 * This function provides a direct write operation on the parent MDIO bus for 2383 * accessing PHY registers. Bypassing SPI or I2C, it uses the parent MDIO bus 2384 * to modify the PHY register values at the specified address. 2385 * 2386 * Return: 0 on success, or a negative error code on failure. 2387 */ 2388 static int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum, 2389 u16 val) 2390 { 2391 struct ksz_device *dev = bus->priv; 2392 2393 return mdiobus_write_nested(dev->parent_mdio_bus, addr, regnum, val); 2394 } 2395 2396 /** 2397 * ksz_phy_addr_to_port - Map a PHY address to the corresponding switch port. 2398 * @dev: Pointer to device structure. 2399 * @addr: PHY address to map to a port. 2400 * 2401 * This function finds the corresponding switch port for a given PHY address by 2402 * iterating over all user ports on the device. It checks if a port's PHY 2403 * address in `phy_addr_map` matches the specified address and if the port 2404 * contains an internal PHY. If a match is found, the index of the port is 2405 * returned. 2406 * 2407 * Return: Port index on success, or -EINVAL if no matching port is found. 2408 */ 2409 static int ksz_phy_addr_to_port(struct ksz_device *dev, int addr) 2410 { 2411 struct dsa_switch *ds = dev->ds; 2412 struct dsa_port *dp; 2413 2414 dsa_switch_for_each_user_port(dp, ds) { 2415 if (dev->info->internal_phy[dp->index] && 2416 dev->phy_addr_map[dp->index] == addr) 2417 return dp->index; 2418 } 2419 2420 return -EINVAL; 2421 } 2422 2423 /** 2424 * ksz_irq_phy_setup - Configure IRQs for PHYs in the KSZ device. 2425 * @dev: Pointer to the KSZ device structure. 2426 * 2427 * Sets up IRQs for each active PHY connected to the KSZ switch by mapping the 2428 * appropriate IRQs for each PHY and assigning them to the `user_mii_bus` in 2429 * the DSA switch structure. Each IRQ is mapped based on the port's IRQ domain. 2430 * 2431 * Return: 0 on success, or a negative error code on failure. 2432 */ 2433 static int ksz_irq_phy_setup(struct ksz_device *dev) 2434 { 2435 struct dsa_switch *ds = dev->ds; 2436 int phy, port; 2437 int irq; 2438 int ret; 2439 2440 for (phy = 0; phy < PHY_MAX_ADDR; phy++) { 2441 if (BIT(phy) & ds->phys_mii_mask) { 2442 port = ksz_phy_addr_to_port(dev, phy); 2443 if (port < 0) { 2444 ret = port; 2445 goto out; 2446 } 2447 2448 irq = irq_find_mapping(dev->ports[port].pirq.domain, 2449 PORT_SRC_PHY_INT); 2450 if (irq < 0) { 2451 ret = irq; 2452 goto out; 2453 } 2454 ds->user_mii_bus->irq[phy] = irq; 2455 } 2456 } 2457 return 0; 2458 out: 2459 while (phy--) 2460 if (BIT(phy) & ds->phys_mii_mask) 2461 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2462 2463 return ret; 2464 } 2465 2466 /** 2467 * ksz_irq_phy_free - Release IRQ mappings for PHYs in the KSZ device. 2468 * @dev: Pointer to the KSZ device structure. 2469 * 2470 * Releases any IRQ mappings previously assigned to active PHYs in the KSZ 2471 * switch by disposing of each mapped IRQ in the `user_mii_bus` structure. 2472 */ 2473 static void ksz_irq_phy_free(struct ksz_device *dev) 2474 { 2475 struct dsa_switch *ds = dev->ds; 2476 int phy; 2477 2478 for (phy = 0; phy < PHY_MAX_ADDR; phy++) 2479 if (BIT(phy) & ds->phys_mii_mask) 2480 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2481 } 2482 2483 /** 2484 * ksz_parse_dt_phy_config - Parse and validate PHY configuration from DT 2485 * @dev: pointer to the KSZ device structure 2486 * @bus: pointer to the MII bus structure 2487 * @mdio_np: pointer to the MDIO node in the device tree 2488 * 2489 * This function parses and validates PHY configurations for each user port 2490 * defined in the device tree for a KSZ switch device. It verifies that the 2491 * `phy-handle` properties are correctly set and that the internal PHYs match 2492 * expected addresses and parent nodes. Sets up the PHY mask in the MII bus if 2493 * all validations pass. Logs error messages for any mismatches or missing data. 2494 * 2495 * Return: 0 on success, or a negative error code on failure. 2496 */ 2497 static int ksz_parse_dt_phy_config(struct ksz_device *dev, struct mii_bus *bus, 2498 struct device_node *mdio_np) 2499 { 2500 struct device_node *phy_node, *phy_parent_node; 2501 bool phys_are_valid = true; 2502 struct dsa_port *dp; 2503 u32 phy_addr; 2504 int ret; 2505 2506 dsa_switch_for_each_user_port(dp, dev->ds) { 2507 if (!dev->info->internal_phy[dp->index]) 2508 continue; 2509 2510 phy_node = of_parse_phandle(dp->dn, "phy-handle", 0); 2511 if (!phy_node) { 2512 dev_err(dev->dev, "failed to parse phy-handle for port %d.\n", 2513 dp->index); 2514 phys_are_valid = false; 2515 continue; 2516 } 2517 2518 phy_parent_node = of_get_parent(phy_node); 2519 if (!phy_parent_node) { 2520 dev_err(dev->dev, "failed to get PHY-parent node for port %d\n", 2521 dp->index); 2522 phys_are_valid = false; 2523 } else if (phy_parent_node != mdio_np) { 2524 dev_err(dev->dev, "PHY-parent node mismatch for port %d, expected %pOF, got %pOF\n", 2525 dp->index, mdio_np, phy_parent_node); 2526 phys_are_valid = false; 2527 } else { 2528 ret = of_property_read_u32(phy_node, "reg", &phy_addr); 2529 if (ret < 0) { 2530 dev_err(dev->dev, "failed to read PHY address for port %d. Error %d\n", 2531 dp->index, ret); 2532 phys_are_valid = false; 2533 } else if (phy_addr != dev->phy_addr_map[dp->index]) { 2534 dev_err(dev->dev, "PHY address mismatch for port %d, expected 0x%x, got 0x%x\n", 2535 dp->index, dev->phy_addr_map[dp->index], 2536 phy_addr); 2537 phys_are_valid = false; 2538 } else { 2539 bus->phy_mask |= BIT(phy_addr); 2540 } 2541 } 2542 2543 of_node_put(phy_node); 2544 of_node_put(phy_parent_node); 2545 } 2546 2547 if (!phys_are_valid) 2548 return -EINVAL; 2549 2550 return 0; 2551 } 2552 2553 /** 2554 * ksz_mdio_register - Register and configure the MDIO bus for the KSZ device. 2555 * @dev: Pointer to the KSZ device structure. 2556 * 2557 * This function sets up and registers an MDIO bus for the KSZ switch device, 2558 * allowing access to its internal PHYs. If the device supports side MDIO, 2559 * the function will configure the external MDIO controller specified by the 2560 * "mdio-parent-bus" device tree property to directly manage internal PHYs. 2561 * Otherwise, SPI or I2C access is set up for PHY access. 2562 * 2563 * Return: 0 on success, or a negative error code on failure. 2564 */ 2565 static int ksz_mdio_register(struct ksz_device *dev) 2566 { 2567 struct device_node *parent_bus_node; 2568 struct mii_bus *parent_bus = NULL; 2569 struct dsa_switch *ds = dev->ds; 2570 struct device_node *mdio_np; 2571 struct mii_bus *bus; 2572 int ret, i; 2573 2574 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 2575 if (!mdio_np) 2576 return 0; 2577 2578 parent_bus_node = of_parse_phandle(mdio_np, "mdio-parent-bus", 0); 2579 if (parent_bus_node && !dev->info->phy_side_mdio_supported) { 2580 dev_err(dev->dev, "Side MDIO bus is not supported for this HW, ignoring 'mdio-parent-bus' property.\n"); 2581 ret = -EINVAL; 2582 2583 goto put_mdio_node; 2584 } else if (parent_bus_node) { 2585 parent_bus = of_mdio_find_bus(parent_bus_node); 2586 if (!parent_bus) { 2587 ret = -EPROBE_DEFER; 2588 2589 goto put_mdio_node; 2590 } 2591 2592 dev->parent_mdio_bus = parent_bus; 2593 } 2594 2595 bus = devm_mdiobus_alloc(ds->dev); 2596 if (!bus) { 2597 ret = -ENOMEM; 2598 goto put_mdio_node; 2599 } 2600 2601 if (dev->dev_ops->mdio_bus_preinit) { 2602 ret = dev->dev_ops->mdio_bus_preinit(dev, !!parent_bus); 2603 if (ret) 2604 goto put_mdio_node; 2605 } 2606 2607 if (dev->dev_ops->create_phy_addr_map) { 2608 ret = dev->dev_ops->create_phy_addr_map(dev, !!parent_bus); 2609 if (ret) 2610 goto put_mdio_node; 2611 } else { 2612 for (i = 0; i < dev->info->port_cnt; i++) 2613 dev->phy_addr_map[i] = i; 2614 } 2615 2616 bus->priv = dev; 2617 if (parent_bus) { 2618 bus->read = ksz_parent_mdio_read; 2619 bus->write = ksz_parent_mdio_write; 2620 bus->name = "KSZ side MDIO"; 2621 snprintf(bus->id, MII_BUS_ID_SIZE, "ksz-side-mdio-%d", 2622 ds->index); 2623 } else { 2624 bus->read = ksz_sw_mdio_read; 2625 bus->write = ksz_sw_mdio_write; 2626 bus->name = "ksz user smi"; 2627 if (ds->dst->index != 0) { 2628 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d-%d", ds->dst->index, ds->index); 2629 } else { 2630 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 2631 } 2632 } 2633 2634 ret = ksz_parse_dt_phy_config(dev, bus, mdio_np); 2635 if (ret) 2636 goto put_mdio_node; 2637 2638 ds->phys_mii_mask = bus->phy_mask; 2639 bus->parent = ds->dev; 2640 2641 ds->user_mii_bus = bus; 2642 2643 if (dev->irq > 0) { 2644 ret = ksz_irq_phy_setup(dev); 2645 if (ret) 2646 goto put_mdio_node; 2647 } 2648 2649 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 2650 if (ret) { 2651 dev_err(ds->dev, "unable to register MDIO bus %s\n", 2652 bus->id); 2653 if (dev->irq > 0) 2654 ksz_irq_phy_free(dev); 2655 } 2656 2657 put_mdio_node: 2658 of_node_put(mdio_np); 2659 of_node_put(parent_bus_node); 2660 2661 return ret; 2662 } 2663 2664 static void ksz_irq_mask(struct irq_data *d) 2665 { 2666 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2667 2668 kirq->masked |= BIT(d->hwirq); 2669 } 2670 2671 static void ksz_irq_unmask(struct irq_data *d) 2672 { 2673 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2674 2675 kirq->masked &= ~BIT(d->hwirq); 2676 } 2677 2678 static void ksz_irq_bus_lock(struct irq_data *d) 2679 { 2680 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2681 2682 mutex_lock(&kirq->dev->lock_irq); 2683 } 2684 2685 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 2686 { 2687 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2688 struct ksz_device *dev = kirq->dev; 2689 int ret; 2690 2691 ret = ksz_write8(dev, kirq->reg_mask, kirq->masked); 2692 if (ret) 2693 dev_err(dev->dev, "failed to change IRQ mask\n"); 2694 2695 mutex_unlock(&dev->lock_irq); 2696 } 2697 2698 static const struct irq_chip ksz_irq_chip = { 2699 .name = "ksz-irq", 2700 .irq_mask = ksz_irq_mask, 2701 .irq_unmask = ksz_irq_unmask, 2702 .irq_bus_lock = ksz_irq_bus_lock, 2703 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 2704 }; 2705 2706 static int ksz_irq_domain_map(struct irq_domain *d, 2707 unsigned int irq, irq_hw_number_t hwirq) 2708 { 2709 irq_set_chip_data(irq, d->host_data); 2710 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 2711 irq_set_noprobe(irq); 2712 2713 return 0; 2714 } 2715 2716 static const struct irq_domain_ops ksz_irq_domain_ops = { 2717 .map = ksz_irq_domain_map, 2718 .xlate = irq_domain_xlate_twocell, 2719 }; 2720 2721 static void ksz_irq_free(struct ksz_irq *kirq) 2722 { 2723 int irq, virq; 2724 2725 free_irq(kirq->irq_num, kirq); 2726 2727 for (irq = 0; irq < kirq->nirqs; irq++) { 2728 virq = irq_find_mapping(kirq->domain, irq); 2729 irq_dispose_mapping(virq); 2730 } 2731 2732 irq_domain_remove(kirq->domain); 2733 } 2734 2735 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 2736 { 2737 struct ksz_irq *kirq = dev_id; 2738 unsigned int nhandled = 0; 2739 struct ksz_device *dev; 2740 unsigned int sub_irq; 2741 u8 data; 2742 int ret; 2743 u8 n; 2744 2745 dev = kirq->dev; 2746 2747 /* Read interrupt status register */ 2748 ret = ksz_read8(dev, kirq->reg_status, &data); 2749 if (ret) 2750 goto out; 2751 2752 for (n = 0; n < kirq->nirqs; ++n) { 2753 if (data & BIT(n)) { 2754 sub_irq = irq_find_mapping(kirq->domain, n); 2755 handle_nested_irq(sub_irq); 2756 ++nhandled; 2757 } 2758 } 2759 out: 2760 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2761 } 2762 2763 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 2764 { 2765 int ret, n; 2766 2767 kirq->dev = dev; 2768 kirq->masked = ~0; 2769 2770 kirq->domain = irq_domain_create_simple(of_fwnode_handle(dev->dev->of_node), 2771 kirq->nirqs, 0, 2772 &ksz_irq_domain_ops, kirq); 2773 if (!kirq->domain) 2774 return -ENOMEM; 2775 2776 for (n = 0; n < kirq->nirqs; n++) 2777 irq_create_mapping(kirq->domain, n); 2778 2779 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2780 IRQF_ONESHOT, kirq->name, kirq); 2781 if (ret) 2782 goto out; 2783 2784 return 0; 2785 2786 out: 2787 ksz_irq_free(kirq); 2788 2789 return ret; 2790 } 2791 2792 static int ksz_girq_setup(struct ksz_device *dev) 2793 { 2794 struct ksz_irq *girq = &dev->girq; 2795 2796 girq->nirqs = dev->info->port_cnt; 2797 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2798 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2799 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2800 2801 girq->irq_num = dev->irq; 2802 2803 return ksz_irq_common_setup(dev, girq); 2804 } 2805 2806 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2807 { 2808 struct ksz_irq *pirq = &dev->ports[p].pirq; 2809 2810 pirq->nirqs = dev->info->port_nirqs; 2811 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2812 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2813 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2814 2815 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2816 if (pirq->irq_num < 0) 2817 return pirq->irq_num; 2818 2819 return ksz_irq_common_setup(dev, pirq); 2820 } 2821 2822 static int ksz_parse_drive_strength(struct ksz_device *dev); 2823 2824 static int ksz_setup(struct dsa_switch *ds) 2825 { 2826 struct ksz_device *dev = ds->priv; 2827 struct dsa_port *dp; 2828 struct ksz_port *p; 2829 const u16 *regs; 2830 int ret; 2831 2832 regs = dev->info->regs; 2833 2834 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2835 dev->info->num_vlans, GFP_KERNEL); 2836 if (!dev->vlan_cache) 2837 return -ENOMEM; 2838 2839 ret = dev->dev_ops->reset(dev); 2840 if (ret) { 2841 dev_err(ds->dev, "failed to reset switch\n"); 2842 return ret; 2843 } 2844 2845 ret = ksz_parse_drive_strength(dev); 2846 if (ret) 2847 return ret; 2848 2849 /* set broadcast storm protection 10% rate */ 2850 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2851 BROADCAST_STORM_RATE, 2852 (BROADCAST_STORM_VALUE * 2853 BROADCAST_STORM_PROT_RATE) / 100); 2854 2855 dev->dev_ops->config_cpu_port(ds); 2856 2857 dev->dev_ops->enable_stp_addr(dev); 2858 2859 ds->num_tx_queues = dev->info->num_tx_queues; 2860 2861 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 2862 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2863 2864 ksz_init_mib_timer(dev); 2865 2866 ds->configure_vlan_while_not_filtering = false; 2867 ds->dscp_prio_mapping_is_global = true; 2868 2869 if (dev->dev_ops->setup) { 2870 ret = dev->dev_ops->setup(ds); 2871 if (ret) 2872 return ret; 2873 } 2874 2875 /* Start with learning disabled on standalone user ports, and enabled 2876 * on the CPU port. In lack of other finer mechanisms, learning on the 2877 * CPU port will avoid flooding bridge local addresses on the network 2878 * in some cases. 2879 */ 2880 p = &dev->ports[dev->cpu_port]; 2881 p->learning = true; 2882 2883 if (dev->irq > 0) { 2884 ret = ksz_girq_setup(dev); 2885 if (ret) 2886 return ret; 2887 2888 dsa_switch_for_each_user_port(dp, dev->ds) { 2889 ret = ksz_pirq_setup(dev, dp->index); 2890 if (ret) 2891 goto out_girq; 2892 2893 if (dev->info->ptp_capable) { 2894 ret = ksz_ptp_irq_setup(ds, dp->index); 2895 if (ret) 2896 goto out_pirq; 2897 } 2898 } 2899 } 2900 2901 if (dev->info->ptp_capable) { 2902 ret = ksz_ptp_clock_register(ds); 2903 if (ret) { 2904 dev_err(dev->dev, "Failed to register PTP clock: %d\n", 2905 ret); 2906 goto out_ptpirq; 2907 } 2908 } 2909 2910 ret = ksz_mdio_register(dev); 2911 if (ret < 0) { 2912 dev_err(dev->dev, "failed to register the mdio"); 2913 goto out_ptp_clock_unregister; 2914 } 2915 2916 ret = ksz_dcb_init(dev); 2917 if (ret) 2918 goto out_ptp_clock_unregister; 2919 2920 /* start switch */ 2921 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 2922 SW_START, SW_START); 2923 2924 return 0; 2925 2926 out_ptp_clock_unregister: 2927 if (dev->info->ptp_capable) 2928 ksz_ptp_clock_unregister(ds); 2929 out_ptpirq: 2930 if (dev->irq > 0 && dev->info->ptp_capable) 2931 dsa_switch_for_each_user_port(dp, dev->ds) 2932 ksz_ptp_irq_free(ds, dp->index); 2933 out_pirq: 2934 if (dev->irq > 0) 2935 dsa_switch_for_each_user_port(dp, dev->ds) 2936 ksz_irq_free(&dev->ports[dp->index].pirq); 2937 out_girq: 2938 if (dev->irq > 0) 2939 ksz_irq_free(&dev->girq); 2940 2941 return ret; 2942 } 2943 2944 static void ksz_teardown(struct dsa_switch *ds) 2945 { 2946 struct ksz_device *dev = ds->priv; 2947 struct dsa_port *dp; 2948 2949 if (dev->info->ptp_capable) 2950 ksz_ptp_clock_unregister(ds); 2951 2952 if (dev->irq > 0) { 2953 dsa_switch_for_each_user_port(dp, dev->ds) { 2954 if (dev->info->ptp_capable) 2955 ksz_ptp_irq_free(ds, dp->index); 2956 2957 ksz_irq_free(&dev->ports[dp->index].pirq); 2958 } 2959 2960 ksz_irq_free(&dev->girq); 2961 } 2962 2963 if (dev->dev_ops->teardown) 2964 dev->dev_ops->teardown(ds); 2965 } 2966 2967 static void port_r_cnt(struct ksz_device *dev, int port) 2968 { 2969 struct ksz_port_mib *mib = &dev->ports[port].mib; 2970 u64 *dropped; 2971 2972 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2973 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2974 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2975 &mib->counters[mib->cnt_ptr]); 2976 ++mib->cnt_ptr; 2977 } 2978 2979 /* last one in storage */ 2980 dropped = &mib->counters[dev->info->mib_cnt]; 2981 2982 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2983 while (mib->cnt_ptr < dev->info->mib_cnt) { 2984 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2985 dropped, &mib->counters[mib->cnt_ptr]); 2986 ++mib->cnt_ptr; 2987 } 2988 mib->cnt_ptr = 0; 2989 } 2990 2991 static void ksz_mib_read_work(struct work_struct *work) 2992 { 2993 struct ksz_device *dev = container_of(work, struct ksz_device, 2994 mib_read.work); 2995 struct ksz_port_mib *mib; 2996 struct ksz_port *p; 2997 int i; 2998 2999 for (i = 0; i < dev->info->port_cnt; i++) { 3000 if (dsa_is_unused_port(dev->ds, i)) 3001 continue; 3002 3003 p = &dev->ports[i]; 3004 mib = &p->mib; 3005 mutex_lock(&mib->cnt_mutex); 3006 3007 /* Only read MIB counters when the port is told to do. 3008 * If not, read only dropped counters when link is not up. 3009 */ 3010 if (!p->read) { 3011 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 3012 3013 if (!netif_carrier_ok(dp->user)) 3014 mib->cnt_ptr = dev->info->reg_mib_cnt; 3015 } 3016 port_r_cnt(dev, i); 3017 p->read = false; 3018 3019 if (dev->dev_ops->r_mib_stat64) 3020 dev->dev_ops->r_mib_stat64(dev, i); 3021 3022 mutex_unlock(&mib->cnt_mutex); 3023 } 3024 3025 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 3026 } 3027 3028 void ksz_init_mib_timer(struct ksz_device *dev) 3029 { 3030 int i; 3031 3032 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 3033 3034 for (i = 0; i < dev->info->port_cnt; i++) { 3035 struct ksz_port_mib *mib = &dev->ports[i].mib; 3036 3037 dev->dev_ops->port_init_cnt(dev, i); 3038 3039 mib->cnt_ptr = 0; 3040 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 3041 } 3042 } 3043 3044 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 3045 { 3046 struct ksz_device *dev = ds->priv; 3047 u16 val = 0xffff; 3048 int ret; 3049 3050 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 3051 if (ret) 3052 return ret; 3053 3054 return val; 3055 } 3056 3057 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 3058 { 3059 struct ksz_device *dev = ds->priv; 3060 int ret; 3061 3062 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 3063 if (ret) 3064 return ret; 3065 3066 return 0; 3067 } 3068 3069 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 3070 { 3071 struct ksz_device *dev = ds->priv; 3072 3073 switch (dev->chip_id) { 3074 case KSZ88X3_CHIP_ID: 3075 /* Silicon Errata Sheet (DS80000830A): 3076 * Port 1 does not work with LinkMD Cable-Testing. 3077 * Port 1 does not respond to received PAUSE control frames. 3078 */ 3079 if (!port) 3080 return MICREL_KSZ8_P1_ERRATA; 3081 break; 3082 } 3083 3084 return 0; 3085 } 3086 3087 static void ksz_phylink_mac_link_down(struct phylink_config *config, 3088 unsigned int mode, 3089 phy_interface_t interface) 3090 { 3091 struct dsa_port *dp = dsa_phylink_to_port(config); 3092 struct ksz_device *dev = dp->ds->priv; 3093 3094 /* Read all MIB counters when the link is going down. */ 3095 dev->ports[dp->index].read = true; 3096 /* timer started */ 3097 if (dev->mib_read_interval) 3098 schedule_delayed_work(&dev->mib_read, 0); 3099 } 3100 3101 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 3102 { 3103 struct ksz_device *dev = ds->priv; 3104 3105 if (sset != ETH_SS_STATS) 3106 return 0; 3107 3108 return dev->info->mib_cnt; 3109 } 3110 3111 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 3112 uint64_t *buf) 3113 { 3114 const struct dsa_port *dp = dsa_to_port(ds, port); 3115 struct ksz_device *dev = ds->priv; 3116 struct ksz_port_mib *mib; 3117 3118 mib = &dev->ports[port].mib; 3119 mutex_lock(&mib->cnt_mutex); 3120 3121 /* Only read dropped counters if no link. */ 3122 if (!netif_carrier_ok(dp->user)) 3123 mib->cnt_ptr = dev->info->reg_mib_cnt; 3124 port_r_cnt(dev, port); 3125 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 3126 mutex_unlock(&mib->cnt_mutex); 3127 } 3128 3129 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 3130 struct dsa_bridge bridge, 3131 bool *tx_fwd_offload, 3132 struct netlink_ext_ack *extack) 3133 { 3134 /* port_stp_state_set() will be called after to put the port in 3135 * appropriate state so there is no need to do anything. 3136 */ 3137 3138 return 0; 3139 } 3140 3141 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 3142 struct dsa_bridge bridge) 3143 { 3144 /* port_stp_state_set() will be called after to put the port in 3145 * forwarding state so there is no need to do anything. 3146 */ 3147 } 3148 3149 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 3150 { 3151 struct ksz_device *dev = ds->priv; 3152 3153 dev->dev_ops->flush_dyn_mac_table(dev, port); 3154 } 3155 3156 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 3157 { 3158 struct ksz_device *dev = ds->priv; 3159 3160 if (!dev->dev_ops->set_ageing_time) 3161 return -EOPNOTSUPP; 3162 3163 return dev->dev_ops->set_ageing_time(dev, msecs); 3164 } 3165 3166 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 3167 const unsigned char *addr, u16 vid, 3168 struct dsa_db db) 3169 { 3170 struct ksz_device *dev = ds->priv; 3171 3172 if (!dev->dev_ops->fdb_add) 3173 return -EOPNOTSUPP; 3174 3175 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 3176 } 3177 3178 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 3179 const unsigned char *addr, 3180 u16 vid, struct dsa_db db) 3181 { 3182 struct ksz_device *dev = ds->priv; 3183 3184 if (!dev->dev_ops->fdb_del) 3185 return -EOPNOTSUPP; 3186 3187 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 3188 } 3189 3190 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 3191 dsa_fdb_dump_cb_t *cb, void *data) 3192 { 3193 struct ksz_device *dev = ds->priv; 3194 3195 if (!dev->dev_ops->fdb_dump) 3196 return -EOPNOTSUPP; 3197 3198 return dev->dev_ops->fdb_dump(dev, port, cb, data); 3199 } 3200 3201 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 3202 const struct switchdev_obj_port_mdb *mdb, 3203 struct dsa_db db) 3204 { 3205 struct ksz_device *dev = ds->priv; 3206 3207 if (!dev->dev_ops->mdb_add) 3208 return -EOPNOTSUPP; 3209 3210 return dev->dev_ops->mdb_add(dev, port, mdb, db); 3211 } 3212 3213 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 3214 const struct switchdev_obj_port_mdb *mdb, 3215 struct dsa_db db) 3216 { 3217 struct ksz_device *dev = ds->priv; 3218 3219 if (!dev->dev_ops->mdb_del) 3220 return -EOPNOTSUPP; 3221 3222 return dev->dev_ops->mdb_del(dev, port, mdb, db); 3223 } 3224 3225 static int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev, 3226 int port) 3227 { 3228 u32 queue_map = 0; 3229 int ipm; 3230 3231 for (ipm = 0; ipm < dev->info->num_ipms; ipm++) { 3232 int queue; 3233 3234 /* Traffic Type (TT) is corresponding to the Internal Priority 3235 * Map (IPM) in the switch. Traffic Class (TC) is 3236 * corresponding to the queue in the switch. 3237 */ 3238 queue = ieee8021q_tt_to_tc(ipm, dev->info->num_tx_queues); 3239 if (queue < 0) 3240 return queue; 3241 3242 queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S); 3243 } 3244 3245 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3246 } 3247 3248 static int ksz_port_setup(struct dsa_switch *ds, int port) 3249 { 3250 struct ksz_device *dev = ds->priv; 3251 int ret; 3252 3253 if (!dsa_is_user_port(ds, port)) 3254 return 0; 3255 3256 /* setup user port */ 3257 dev->dev_ops->port_setup(dev, port, false); 3258 3259 if (!is_ksz8(dev)) { 3260 ret = ksz9477_set_default_prio_queue_mapping(dev, port); 3261 if (ret) 3262 return ret; 3263 } 3264 3265 /* port_stp_state_set() will be called after to enable the port so 3266 * there is no need to do anything. 3267 */ 3268 3269 return ksz_dcb_init_port(dev, port); 3270 } 3271 3272 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 3273 { 3274 struct ksz_device *dev = ds->priv; 3275 struct ksz_port *p; 3276 const u16 *regs; 3277 u8 data; 3278 3279 regs = dev->info->regs; 3280 3281 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 3282 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 3283 3284 p = &dev->ports[port]; 3285 3286 switch (state) { 3287 case BR_STATE_DISABLED: 3288 data |= PORT_LEARN_DISABLE; 3289 break; 3290 case BR_STATE_LISTENING: 3291 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 3292 break; 3293 case BR_STATE_LEARNING: 3294 data |= PORT_RX_ENABLE; 3295 if (!p->learning) 3296 data |= PORT_LEARN_DISABLE; 3297 break; 3298 case BR_STATE_FORWARDING: 3299 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 3300 if (!p->learning) 3301 data |= PORT_LEARN_DISABLE; 3302 break; 3303 case BR_STATE_BLOCKING: 3304 data |= PORT_LEARN_DISABLE; 3305 break; 3306 default: 3307 dev_err(ds->dev, "invalid STP state: %d\n", state); 3308 return; 3309 } 3310 3311 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 3312 3313 p->stp_state = state; 3314 3315 ksz_update_port_member(dev, port); 3316 } 3317 3318 static void ksz_port_teardown(struct dsa_switch *ds, int port) 3319 { 3320 struct ksz_device *dev = ds->priv; 3321 3322 switch (dev->chip_id) { 3323 case KSZ8563_CHIP_ID: 3324 case KSZ8567_CHIP_ID: 3325 case KSZ9477_CHIP_ID: 3326 case KSZ9563_CHIP_ID: 3327 case KSZ9567_CHIP_ID: 3328 case KSZ9893_CHIP_ID: 3329 case KSZ9896_CHIP_ID: 3330 case KSZ9897_CHIP_ID: 3331 case LAN9646_CHIP_ID: 3332 if (dsa_is_user_port(ds, port)) 3333 ksz9477_port_acl_free(dev, port); 3334 } 3335 } 3336 3337 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 3338 struct switchdev_brport_flags flags, 3339 struct netlink_ext_ack *extack) 3340 { 3341 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED)) 3342 return -EINVAL; 3343 3344 return 0; 3345 } 3346 3347 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 3348 struct switchdev_brport_flags flags, 3349 struct netlink_ext_ack *extack) 3350 { 3351 struct ksz_device *dev = ds->priv; 3352 struct ksz_port *p = &dev->ports[port]; 3353 3354 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) { 3355 if (flags.mask & BR_LEARNING) 3356 p->learning = !!(flags.val & BR_LEARNING); 3357 3358 if (flags.mask & BR_ISOLATED) 3359 p->isolated = !!(flags.val & BR_ISOLATED); 3360 3361 /* Make the change take effect immediately */ 3362 ksz_port_stp_state_set(ds, port, p->stp_state); 3363 } 3364 3365 return 0; 3366 } 3367 3368 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 3369 int port, 3370 enum dsa_tag_protocol mp) 3371 { 3372 struct ksz_device *dev = ds->priv; 3373 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 3374 3375 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev)) 3376 proto = DSA_TAG_PROTO_KSZ8795; 3377 3378 if (dev->chip_id == KSZ88X3_CHIP_ID || 3379 dev->chip_id == KSZ8563_CHIP_ID || 3380 dev->chip_id == KSZ9893_CHIP_ID || 3381 dev->chip_id == KSZ9563_CHIP_ID) 3382 proto = DSA_TAG_PROTO_KSZ9893; 3383 3384 if (dev->chip_id == KSZ8567_CHIP_ID || 3385 dev->chip_id == KSZ9477_CHIP_ID || 3386 dev->chip_id == KSZ9896_CHIP_ID || 3387 dev->chip_id == KSZ9897_CHIP_ID || 3388 dev->chip_id == KSZ9567_CHIP_ID || 3389 dev->chip_id == LAN9646_CHIP_ID) 3390 proto = DSA_TAG_PROTO_KSZ9477; 3391 3392 if (is_lan937x(dev)) 3393 proto = DSA_TAG_PROTO_LAN937X; 3394 3395 return proto; 3396 } 3397 3398 static int ksz_connect_tag_protocol(struct dsa_switch *ds, 3399 enum dsa_tag_protocol proto) 3400 { 3401 struct ksz_tagger_data *tagger_data; 3402 3403 switch (proto) { 3404 case DSA_TAG_PROTO_KSZ8795: 3405 return 0; 3406 case DSA_TAG_PROTO_KSZ9893: 3407 case DSA_TAG_PROTO_KSZ9477: 3408 case DSA_TAG_PROTO_LAN937X: 3409 tagger_data = ksz_tagger_data(ds); 3410 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 3411 return 0; 3412 default: 3413 return -EPROTONOSUPPORT; 3414 } 3415 } 3416 3417 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 3418 bool flag, struct netlink_ext_ack *extack) 3419 { 3420 struct ksz_device *dev = ds->priv; 3421 3422 if (!dev->dev_ops->vlan_filtering) 3423 return -EOPNOTSUPP; 3424 3425 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 3426 } 3427 3428 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 3429 const struct switchdev_obj_port_vlan *vlan, 3430 struct netlink_ext_ack *extack) 3431 { 3432 struct ksz_device *dev = ds->priv; 3433 3434 if (!dev->dev_ops->vlan_add) 3435 return -EOPNOTSUPP; 3436 3437 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 3438 } 3439 3440 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 3441 const struct switchdev_obj_port_vlan *vlan) 3442 { 3443 struct ksz_device *dev = ds->priv; 3444 3445 if (!dev->dev_ops->vlan_del) 3446 return -EOPNOTSUPP; 3447 3448 return dev->dev_ops->vlan_del(dev, port, vlan); 3449 } 3450 3451 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 3452 struct dsa_mall_mirror_tc_entry *mirror, 3453 bool ingress, struct netlink_ext_ack *extack) 3454 { 3455 struct ksz_device *dev = ds->priv; 3456 3457 if (!dev->dev_ops->mirror_add) 3458 return -EOPNOTSUPP; 3459 3460 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 3461 } 3462 3463 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 3464 struct dsa_mall_mirror_tc_entry *mirror) 3465 { 3466 struct ksz_device *dev = ds->priv; 3467 3468 if (dev->dev_ops->mirror_del) 3469 dev->dev_ops->mirror_del(dev, port, mirror); 3470 } 3471 3472 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 3473 { 3474 struct ksz_device *dev = ds->priv; 3475 3476 if (!dev->dev_ops->change_mtu) 3477 return -EOPNOTSUPP; 3478 3479 return dev->dev_ops->change_mtu(dev, port, mtu); 3480 } 3481 3482 static int ksz_max_mtu(struct dsa_switch *ds, int port) 3483 { 3484 struct ksz_device *dev = ds->priv; 3485 3486 switch (dev->chip_id) { 3487 case KSZ8795_CHIP_ID: 3488 case KSZ8794_CHIP_ID: 3489 case KSZ8765_CHIP_ID: 3490 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3491 case KSZ88X3_CHIP_ID: 3492 case KSZ8864_CHIP_ID: 3493 case KSZ8895_CHIP_ID: 3494 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3495 case KSZ8563_CHIP_ID: 3496 case KSZ8567_CHIP_ID: 3497 case KSZ9477_CHIP_ID: 3498 case KSZ9563_CHIP_ID: 3499 case KSZ9567_CHIP_ID: 3500 case KSZ9893_CHIP_ID: 3501 case KSZ9896_CHIP_ID: 3502 case KSZ9897_CHIP_ID: 3503 case LAN9370_CHIP_ID: 3504 case LAN9371_CHIP_ID: 3505 case LAN9372_CHIP_ID: 3506 case LAN9373_CHIP_ID: 3507 case LAN9374_CHIP_ID: 3508 case LAN9646_CHIP_ID: 3509 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3510 } 3511 3512 return -EOPNOTSUPP; 3513 } 3514 3515 /** 3516 * ksz_support_eee - Determine Energy Efficient Ethernet (EEE) support for a 3517 * port 3518 * @ds: Pointer to the DSA switch structure 3519 * @port: Port number to check 3520 * 3521 * This function also documents devices where EEE was initially advertised but 3522 * later withdrawn due to reliability issues, as described in official errata 3523 * documents. These devices are explicitly listed to record known limitations, 3524 * even if there is no technical necessity for runtime checks. 3525 * 3526 * Returns: true if the internal PHY on the given port supports fully 3527 * operational EEE, false otherwise. 3528 */ 3529 static bool ksz_support_eee(struct dsa_switch *ds, int port) 3530 { 3531 struct ksz_device *dev = ds->priv; 3532 3533 if (!dev->info->internal_phy[port]) 3534 return false; 3535 3536 switch (dev->chip_id) { 3537 case KSZ8563_CHIP_ID: 3538 case KSZ9563_CHIP_ID: 3539 case KSZ9893_CHIP_ID: 3540 return true; 3541 case KSZ8567_CHIP_ID: 3542 /* KSZ8567R Errata DS80000752C Module 4 */ 3543 case KSZ8765_CHIP_ID: 3544 case KSZ8794_CHIP_ID: 3545 case KSZ8795_CHIP_ID: 3546 /* KSZ879x/KSZ877x/KSZ876x Errata DS80000687C Module 2 */ 3547 case KSZ9477_CHIP_ID: 3548 /* KSZ9477S Errata DS80000754A Module 4 */ 3549 case KSZ9567_CHIP_ID: 3550 /* KSZ9567S Errata DS80000756A Module 4 */ 3551 case KSZ9896_CHIP_ID: 3552 /* KSZ9896C Errata DS80000757A Module 3 */ 3553 case KSZ9897_CHIP_ID: 3554 case LAN9646_CHIP_ID: 3555 /* KSZ9897R Errata DS80000758C Module 4 */ 3556 /* Energy Efficient Ethernet (EEE) feature select must be 3557 * manually disabled 3558 * The EEE feature is enabled by default, but it is not fully 3559 * operational. It must be manually disabled through register 3560 * controls. If not disabled, the PHY ports can auto-negotiate 3561 * to enable EEE, and this feature can cause link drops when 3562 * linked to another device supporting EEE. 3563 * 3564 * The same item appears in the errata for all switches above. 3565 */ 3566 break; 3567 } 3568 3569 return false; 3570 } 3571 3572 static int ksz_set_mac_eee(struct dsa_switch *ds, int port, 3573 struct ethtool_keee *e) 3574 { 3575 struct ksz_device *dev = ds->priv; 3576 3577 if (!e->tx_lpi_enabled) { 3578 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 3579 return -EINVAL; 3580 } 3581 3582 if (e->tx_lpi_timer) { 3583 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 3584 return -EINVAL; 3585 } 3586 3587 return 0; 3588 } 3589 3590 static void ksz_set_xmii(struct ksz_device *dev, int port, 3591 phy_interface_t interface) 3592 { 3593 const u8 *bitval = dev->info->xmii_ctrl1; 3594 struct ksz_port *p = &dev->ports[port]; 3595 const u16 *regs = dev->info->regs; 3596 u8 data8; 3597 3598 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3599 3600 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 3601 P_RGMII_ID_EG_ENABLE); 3602 3603 switch (interface) { 3604 case PHY_INTERFACE_MODE_MII: 3605 data8 |= bitval[P_MII_SEL]; 3606 break; 3607 case PHY_INTERFACE_MODE_RMII: 3608 data8 |= bitval[P_RMII_SEL]; 3609 break; 3610 case PHY_INTERFACE_MODE_GMII: 3611 data8 |= bitval[P_GMII_SEL]; 3612 break; 3613 case PHY_INTERFACE_MODE_RGMII: 3614 case PHY_INTERFACE_MODE_RGMII_ID: 3615 case PHY_INTERFACE_MODE_RGMII_TXID: 3616 case PHY_INTERFACE_MODE_RGMII_RXID: 3617 data8 |= bitval[P_RGMII_SEL]; 3618 /* On KSZ9893, disable RGMII in-band status support */ 3619 if (dev->chip_id == KSZ9893_CHIP_ID || 3620 dev->chip_id == KSZ8563_CHIP_ID || 3621 dev->chip_id == KSZ9563_CHIP_ID || 3622 is_lan937x(dev)) 3623 data8 &= ~P_MII_MAC_MODE; 3624 break; 3625 default: 3626 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 3627 phy_modes(interface), port); 3628 return; 3629 } 3630 3631 if (p->rgmii_tx_val) 3632 data8 |= P_RGMII_ID_EG_ENABLE; 3633 3634 if (p->rgmii_rx_val) 3635 data8 |= P_RGMII_ID_IG_ENABLE; 3636 3637 /* Write the updated value */ 3638 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3639 } 3640 3641 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 3642 { 3643 const u8 *bitval = dev->info->xmii_ctrl1; 3644 const u16 *regs = dev->info->regs; 3645 phy_interface_t interface; 3646 u8 data8; 3647 u8 val; 3648 3649 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3650 3651 val = FIELD_GET(P_MII_SEL_M, data8); 3652 3653 if (val == bitval[P_MII_SEL]) { 3654 if (gbit) 3655 interface = PHY_INTERFACE_MODE_GMII; 3656 else 3657 interface = PHY_INTERFACE_MODE_MII; 3658 } else if (val == bitval[P_RMII_SEL]) { 3659 interface = PHY_INTERFACE_MODE_RMII; 3660 } else { 3661 interface = PHY_INTERFACE_MODE_RGMII; 3662 if (data8 & P_RGMII_ID_EG_ENABLE) 3663 interface = PHY_INTERFACE_MODE_RGMII_TXID; 3664 if (data8 & P_RGMII_ID_IG_ENABLE) { 3665 interface = PHY_INTERFACE_MODE_RGMII_RXID; 3666 if (data8 & P_RGMII_ID_EG_ENABLE) 3667 interface = PHY_INTERFACE_MODE_RGMII_ID; 3668 } 3669 } 3670 3671 return interface; 3672 } 3673 3674 static void ksz88x3_phylink_mac_config(struct phylink_config *config, 3675 unsigned int mode, 3676 const struct phylink_link_state *state) 3677 { 3678 struct dsa_port *dp = dsa_phylink_to_port(config); 3679 struct ksz_device *dev = dp->ds->priv; 3680 3681 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN); 3682 } 3683 3684 static void ksz_phylink_mac_config(struct phylink_config *config, 3685 unsigned int mode, 3686 const struct phylink_link_state *state) 3687 { 3688 struct dsa_port *dp = dsa_phylink_to_port(config); 3689 struct ksz_device *dev = dp->ds->priv; 3690 int port = dp->index; 3691 3692 /* Internal PHYs */ 3693 if (dev->info->internal_phy[port]) 3694 return; 3695 3696 if (phylink_autoneg_inband(mode)) { 3697 dev_err(dev->dev, "In-band AN not supported!\n"); 3698 return; 3699 } 3700 3701 ksz_set_xmii(dev, port, state->interface); 3702 3703 if (dev->dev_ops->setup_rgmii_delay) 3704 dev->dev_ops->setup_rgmii_delay(dev, port); 3705 } 3706 3707 bool ksz_get_gbit(struct ksz_device *dev, int port) 3708 { 3709 const u8 *bitval = dev->info->xmii_ctrl1; 3710 const u16 *regs = dev->info->regs; 3711 bool gbit = false; 3712 u8 data8; 3713 bool val; 3714 3715 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3716 3717 val = FIELD_GET(P_GMII_1GBIT_M, data8); 3718 3719 if (val == bitval[P_GMII_1GBIT]) 3720 gbit = true; 3721 3722 return gbit; 3723 } 3724 3725 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 3726 { 3727 const u8 *bitval = dev->info->xmii_ctrl1; 3728 const u16 *regs = dev->info->regs; 3729 u8 data8; 3730 3731 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3732 3733 data8 &= ~P_GMII_1GBIT_M; 3734 3735 if (gbit) 3736 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 3737 else 3738 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 3739 3740 /* Write the updated value */ 3741 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3742 } 3743 3744 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 3745 { 3746 const u8 *bitval = dev->info->xmii_ctrl0; 3747 const u16 *regs = dev->info->regs; 3748 u8 data8; 3749 3750 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 3751 3752 data8 &= ~P_MII_100MBIT_M; 3753 3754 if (speed == SPEED_100) 3755 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 3756 else 3757 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 3758 3759 /* Write the updated value */ 3760 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 3761 } 3762 3763 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 3764 { 3765 if (speed == SPEED_1000) 3766 ksz_set_gbit(dev, port, true); 3767 else 3768 ksz_set_gbit(dev, port, false); 3769 3770 if (speed == SPEED_100 || speed == SPEED_10) 3771 ksz_set_100_10mbit(dev, port, speed); 3772 } 3773 3774 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 3775 bool tx_pause, bool rx_pause) 3776 { 3777 const u8 *bitval = dev->info->xmii_ctrl0; 3778 const u32 *masks = dev->info->masks; 3779 const u16 *regs = dev->info->regs; 3780 u8 mask; 3781 u8 val; 3782 3783 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 3784 masks[P_MII_RX_FLOW_CTRL]; 3785 3786 if (duplex == DUPLEX_FULL) 3787 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 3788 else 3789 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 3790 3791 if (tx_pause) 3792 val |= masks[P_MII_TX_FLOW_CTRL]; 3793 3794 if (rx_pause) 3795 val |= masks[P_MII_RX_FLOW_CTRL]; 3796 3797 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 3798 } 3799 3800 static void ksz9477_phylink_mac_link_up(struct phylink_config *config, 3801 struct phy_device *phydev, 3802 unsigned int mode, 3803 phy_interface_t interface, 3804 int speed, int duplex, bool tx_pause, 3805 bool rx_pause) 3806 { 3807 struct dsa_port *dp = dsa_phylink_to_port(config); 3808 struct ksz_device *dev = dp->ds->priv; 3809 int port = dp->index; 3810 struct ksz_port *p; 3811 3812 p = &dev->ports[port]; 3813 3814 /* Internal PHYs */ 3815 if (dev->info->internal_phy[port]) 3816 return; 3817 3818 p->phydev.speed = speed; 3819 3820 ksz_port_set_xmii_speed(dev, port, speed); 3821 3822 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 3823 } 3824 3825 static int ksz_switch_detect(struct ksz_device *dev) 3826 { 3827 u8 id1, id2, id4; 3828 u16 id16; 3829 u32 id32; 3830 int ret; 3831 3832 /* read chip id */ 3833 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 3834 if (ret) 3835 return ret; 3836 3837 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 3838 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 3839 3840 switch (id1) { 3841 case KSZ87_FAMILY_ID: 3842 if (id2 == KSZ87_CHIP_ID_95) { 3843 u8 val; 3844 3845 dev->chip_id = KSZ8795_CHIP_ID; 3846 3847 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 3848 if (val & KSZ8_PORT_FIBER_MODE) 3849 dev->chip_id = KSZ8765_CHIP_ID; 3850 } else if (id2 == KSZ87_CHIP_ID_94) { 3851 dev->chip_id = KSZ8794_CHIP_ID; 3852 } else { 3853 return -ENODEV; 3854 } 3855 break; 3856 case KSZ88_FAMILY_ID: 3857 if (id2 == KSZ88_CHIP_ID_63) 3858 dev->chip_id = KSZ88X3_CHIP_ID; 3859 else 3860 return -ENODEV; 3861 break; 3862 case KSZ8895_FAMILY_ID: 3863 if (id2 == KSZ8895_CHIP_ID_95 || 3864 id2 == KSZ8895_CHIP_ID_95R) 3865 dev->chip_id = KSZ8895_CHIP_ID; 3866 else 3867 return -ENODEV; 3868 ret = ksz_read8(dev, REG_KSZ8864_CHIP_ID, &id4); 3869 if (ret) 3870 return ret; 3871 if (id4 & SW_KSZ8864) 3872 dev->chip_id = KSZ8864_CHIP_ID; 3873 break; 3874 default: 3875 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 3876 if (ret) 3877 return ret; 3878 3879 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 3880 id32 &= ~0xFF; 3881 3882 switch (id32) { 3883 case KSZ9477_CHIP_ID: 3884 case KSZ9896_CHIP_ID: 3885 case KSZ9897_CHIP_ID: 3886 case KSZ9567_CHIP_ID: 3887 case KSZ8567_CHIP_ID: 3888 case LAN9370_CHIP_ID: 3889 case LAN9371_CHIP_ID: 3890 case LAN9372_CHIP_ID: 3891 case LAN9373_CHIP_ID: 3892 case LAN9374_CHIP_ID: 3893 3894 /* LAN9646 does not have its own chip id. */ 3895 if (dev->chip_id != LAN9646_CHIP_ID) 3896 dev->chip_id = id32; 3897 break; 3898 case KSZ9893_CHIP_ID: 3899 ret = ksz_read8(dev, REG_CHIP_ID4, 3900 &id4); 3901 if (ret) 3902 return ret; 3903 3904 if (id4 == SKU_ID_KSZ8563) 3905 dev->chip_id = KSZ8563_CHIP_ID; 3906 else if (id4 == SKU_ID_KSZ9563) 3907 dev->chip_id = KSZ9563_CHIP_ID; 3908 else 3909 dev->chip_id = KSZ9893_CHIP_ID; 3910 3911 break; 3912 default: 3913 dev_err(dev->dev, 3914 "unsupported switch detected %x)\n", id32); 3915 return -ENODEV; 3916 } 3917 } 3918 return 0; 3919 } 3920 3921 static int ksz_cls_flower_add(struct dsa_switch *ds, int port, 3922 struct flow_cls_offload *cls, bool ingress) 3923 { 3924 struct ksz_device *dev = ds->priv; 3925 3926 switch (dev->chip_id) { 3927 case KSZ8563_CHIP_ID: 3928 case KSZ8567_CHIP_ID: 3929 case KSZ9477_CHIP_ID: 3930 case KSZ9563_CHIP_ID: 3931 case KSZ9567_CHIP_ID: 3932 case KSZ9893_CHIP_ID: 3933 case KSZ9896_CHIP_ID: 3934 case KSZ9897_CHIP_ID: 3935 case LAN9646_CHIP_ID: 3936 return ksz9477_cls_flower_add(ds, port, cls, ingress); 3937 } 3938 3939 return -EOPNOTSUPP; 3940 } 3941 3942 static int ksz_cls_flower_del(struct dsa_switch *ds, int port, 3943 struct flow_cls_offload *cls, bool ingress) 3944 { 3945 struct ksz_device *dev = ds->priv; 3946 3947 switch (dev->chip_id) { 3948 case KSZ8563_CHIP_ID: 3949 case KSZ8567_CHIP_ID: 3950 case KSZ9477_CHIP_ID: 3951 case KSZ9563_CHIP_ID: 3952 case KSZ9567_CHIP_ID: 3953 case KSZ9893_CHIP_ID: 3954 case KSZ9896_CHIP_ID: 3955 case KSZ9897_CHIP_ID: 3956 case LAN9646_CHIP_ID: 3957 return ksz9477_cls_flower_del(ds, port, cls, ingress); 3958 } 3959 3960 return -EOPNOTSUPP; 3961 } 3962 3963 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 3964 * is converted to Hex-decimal using the successive multiplication method. On 3965 * every step, integer part is taken and decimal part is carry forwarded. 3966 */ 3967 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 3968 { 3969 u32 cinc = 0; 3970 u32 txrate; 3971 u32 rate; 3972 u8 temp; 3973 u8 i; 3974 3975 txrate = idle_slope - send_slope; 3976 3977 if (!txrate) 3978 return -EINVAL; 3979 3980 rate = idle_slope; 3981 3982 /* 24 bit register */ 3983 for (i = 0; i < 6; i++) { 3984 rate = rate * 16; 3985 3986 temp = rate / txrate; 3987 3988 rate %= txrate; 3989 3990 cinc = ((cinc << 4) | temp); 3991 } 3992 3993 *bw = cinc; 3994 3995 return 0; 3996 } 3997 3998 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 3999 u8 shaper) 4000 { 4001 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 4002 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 4003 FIELD_PREP(MTI_SHAPING_M, shaper)); 4004 } 4005 4006 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 4007 struct tc_cbs_qopt_offload *qopt) 4008 { 4009 struct ksz_device *dev = ds->priv; 4010 int ret; 4011 u32 bw; 4012 4013 if (!dev->info->tc_cbs_supported) 4014 return -EOPNOTSUPP; 4015 4016 if (qopt->queue > dev->info->num_tx_queues) 4017 return -EINVAL; 4018 4019 /* Queue Selection */ 4020 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 4021 if (ret) 4022 return ret; 4023 4024 if (!qopt->enable) 4025 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 4026 MTI_SHAPING_OFF); 4027 4028 /* High Credit */ 4029 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 4030 qopt->hicredit); 4031 if (ret) 4032 return ret; 4033 4034 /* Low Credit */ 4035 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 4036 qopt->locredit); 4037 if (ret) 4038 return ret; 4039 4040 /* Credit Increment Register */ 4041 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 4042 if (ret) 4043 return ret; 4044 4045 if (dev->dev_ops->tc_cbs_set_cinc) { 4046 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 4047 if (ret) 4048 return ret; 4049 } 4050 4051 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 4052 MTI_SHAPING_SRP); 4053 } 4054 4055 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 4056 { 4057 int queue, ret; 4058 4059 /* Configuration will not take effect until the last Port Queue X 4060 * Egress Limit Control Register is written. 4061 */ 4062 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 4063 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 4064 KSZ9477_OUT_RATE_NO_LIMIT); 4065 if (ret) 4066 return ret; 4067 } 4068 4069 return 0; 4070 } 4071 4072 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 4073 int band) 4074 { 4075 /* Compared to queues, bands prioritize packets differently. In strict 4076 * priority mode, the lowest priority is assigned to Queue 0 while the 4077 * highest priority is given to Band 0. 4078 */ 4079 return p->bands - 1 - band; 4080 } 4081 4082 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 4083 { 4084 int ret; 4085 4086 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 4087 if (ret) 4088 return ret; 4089 4090 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 4091 MTI_SHAPING_OFF); 4092 } 4093 4094 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 4095 int weight) 4096 { 4097 int ret; 4098 4099 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 4100 if (ret) 4101 return ret; 4102 4103 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 4104 MTI_SHAPING_OFF); 4105 if (ret) 4106 return ret; 4107 4108 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 4109 } 4110 4111 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 4112 struct tc_ets_qopt_offload_replace_params *p) 4113 { 4114 int ret, band, tc_prio; 4115 u32 queue_map = 0; 4116 4117 /* In order to ensure proper prioritization, it is necessary to set the 4118 * rate limit for the related queue to zero. Otherwise strict priority 4119 * or WRR mode will not work. This is a hardware limitation. 4120 */ 4121 ret = ksz_disable_egress_rate_limit(dev, port); 4122 if (ret) 4123 return ret; 4124 4125 /* Configure queue scheduling mode for all bands. Currently only strict 4126 * prio mode is supported. 4127 */ 4128 for (band = 0; band < p->bands; band++) { 4129 int queue = ksz_ets_band_to_queue(p, band); 4130 4131 ret = ksz_queue_set_strict(dev, port, queue); 4132 if (ret) 4133 return ret; 4134 } 4135 4136 /* Configure the mapping between traffic classes and queues. Note: 4137 * priomap variable support 16 traffic classes, but the chip can handle 4138 * only 8 classes. 4139 */ 4140 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 4141 int queue; 4142 4143 if (tc_prio >= dev->info->num_ipms) 4144 break; 4145 4146 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 4147 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 4148 } 4149 4150 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 4151 } 4152 4153 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 4154 { 4155 int ret, queue; 4156 4157 /* To restore the default chip configuration, set all queues to use the 4158 * WRR scheduler with a weight of 1. 4159 */ 4160 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 4161 ret = ksz_queue_set_wrr(dev, port, queue, 4162 KSZ9477_DEFAULT_WRR_WEIGHT); 4163 if (ret) 4164 return ret; 4165 } 4166 4167 /* Revert the queue mapping for TC-priority to its default setting on 4168 * the chip. 4169 */ 4170 return ksz9477_set_default_prio_queue_mapping(dev, port); 4171 } 4172 4173 static int ksz_tc_ets_validate(struct ksz_device *dev, int port, 4174 struct tc_ets_qopt_offload_replace_params *p) 4175 { 4176 int band; 4177 4178 /* Since it is not feasible to share one port among multiple qdisc, 4179 * the user must configure all available queues appropriately. 4180 */ 4181 if (p->bands != dev->info->num_tx_queues) { 4182 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 4183 dev->info->num_tx_queues); 4184 return -EOPNOTSUPP; 4185 } 4186 4187 for (band = 0; band < p->bands; ++band) { 4188 /* The KSZ switches utilize a weighted round robin configuration 4189 * where a certain number of packets can be transmitted from a 4190 * queue before the next queue is serviced. For more information 4191 * on this, refer to section 5.2.8.4 of the KSZ8565R 4192 * documentation on the Port Transmit Queue Control 1 Register. 4193 * However, the current ETS Qdisc implementation (as of February 4194 * 2023) assigns a weight to each queue based on the number of 4195 * bytes or extrapolated bandwidth in percentages. Since this 4196 * differs from the KSZ switches' method and we don't want to 4197 * fake support by converting bytes to packets, it is better to 4198 * return an error instead. 4199 */ 4200 if (p->quanta[band]) { 4201 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 4202 return -EOPNOTSUPP; 4203 } 4204 } 4205 4206 return 0; 4207 } 4208 4209 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 4210 struct tc_ets_qopt_offload *qopt) 4211 { 4212 struct ksz_device *dev = ds->priv; 4213 int ret; 4214 4215 if (is_ksz8(dev)) 4216 return -EOPNOTSUPP; 4217 4218 if (qopt->parent != TC_H_ROOT) { 4219 dev_err(dev->dev, "Parent should be \"root\"\n"); 4220 return -EOPNOTSUPP; 4221 } 4222 4223 switch (qopt->command) { 4224 case TC_ETS_REPLACE: 4225 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 4226 if (ret) 4227 return ret; 4228 4229 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 4230 case TC_ETS_DESTROY: 4231 return ksz_tc_ets_del(dev, port); 4232 case TC_ETS_STATS: 4233 case TC_ETS_GRAFT: 4234 return -EOPNOTSUPP; 4235 } 4236 4237 return -EOPNOTSUPP; 4238 } 4239 4240 static int ksz_setup_tc(struct dsa_switch *ds, int port, 4241 enum tc_setup_type type, void *type_data) 4242 { 4243 switch (type) { 4244 case TC_SETUP_QDISC_CBS: 4245 return ksz_setup_tc_cbs(ds, port, type_data); 4246 case TC_SETUP_QDISC_ETS: 4247 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 4248 default: 4249 return -EOPNOTSUPP; 4250 } 4251 } 4252 4253 /** 4254 * ksz_handle_wake_reason - Handle wake reason on a specified port. 4255 * @dev: The device structure. 4256 * @port: The port number. 4257 * 4258 * This function reads the PME (Power Management Event) status register of a 4259 * specified port to determine the wake reason. If there is no wake event, it 4260 * returns early. Otherwise, it logs the wake reason which could be due to a 4261 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register 4262 * is then cleared to acknowledge the handling of the wake event. 4263 * 4264 * Return: 0 on success, or an error code on failure. 4265 */ 4266 int ksz_handle_wake_reason(struct ksz_device *dev, int port) 4267 { 4268 const struct ksz_dev_ops *ops = dev->dev_ops; 4269 const u16 *regs = dev->info->regs; 4270 u8 pme_status; 4271 int ret; 4272 4273 ret = ops->pme_pread8(dev, port, regs[REG_PORT_PME_STATUS], 4274 &pme_status); 4275 if (ret) 4276 return ret; 4277 4278 if (!pme_status) 4279 return 0; 4280 4281 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port, 4282 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "", 4283 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "", 4284 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : ""); 4285 4286 return ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_STATUS], 4287 pme_status); 4288 } 4289 4290 /** 4291 * ksz_get_wol - Get Wake-on-LAN settings for a specified port. 4292 * @ds: The dsa_switch structure. 4293 * @port: The port number. 4294 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 4295 * 4296 * This function checks the device PME wakeup_source flag and chip_id. 4297 * If enabled and supported, it sets the supported and active WoL 4298 * flags. 4299 */ 4300 static void ksz_get_wol(struct dsa_switch *ds, int port, 4301 struct ethtool_wolinfo *wol) 4302 { 4303 struct ksz_device *dev = ds->priv; 4304 const u16 *regs = dev->info->regs; 4305 u8 pme_ctrl; 4306 int ret; 4307 4308 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4309 return; 4310 4311 if (!dev->wakeup_source) 4312 return; 4313 4314 wol->supported = WAKE_PHY; 4315 4316 /* Check if the current MAC address on this port can be set 4317 * as global for WAKE_MAGIC support. The result may vary 4318 * dynamically based on other ports configurations. 4319 */ 4320 if (ksz_is_port_mac_global_usable(dev->ds, port)) 4321 wol->supported |= WAKE_MAGIC; 4322 4323 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 4324 &pme_ctrl); 4325 if (ret) 4326 return; 4327 4328 if (pme_ctrl & PME_WOL_MAGICPKT) 4329 wol->wolopts |= WAKE_MAGIC; 4330 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY)) 4331 wol->wolopts |= WAKE_PHY; 4332 } 4333 4334 /** 4335 * ksz_set_wol - Set Wake-on-LAN settings for a specified port. 4336 * @ds: The dsa_switch structure. 4337 * @port: The port number. 4338 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 4339 * 4340 * This function configures Wake-on-LAN (WoL) settings for a specified 4341 * port. It validates the provided WoL options, checks if PME is 4342 * enabled and supported, clears any previous wake reasons, and sets 4343 * the Magic Packet flag in the port's PME control register if 4344 * specified. 4345 * 4346 * Return: 0 on success, or other error codes on failure. 4347 */ 4348 static int ksz_set_wol(struct dsa_switch *ds, int port, 4349 struct ethtool_wolinfo *wol) 4350 { 4351 u8 pme_ctrl = 0, pme_ctrl_old = 0; 4352 struct ksz_device *dev = ds->priv; 4353 const u16 *regs = dev->info->regs; 4354 bool magic_switched_off; 4355 bool magic_switched_on; 4356 int ret; 4357 4358 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC)) 4359 return -EINVAL; 4360 4361 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4362 return -EOPNOTSUPP; 4363 4364 if (!dev->wakeup_source) 4365 return -EOPNOTSUPP; 4366 4367 ret = ksz_handle_wake_reason(dev, port); 4368 if (ret) 4369 return ret; 4370 4371 if (wol->wolopts & WAKE_MAGIC) 4372 pme_ctrl |= PME_WOL_MAGICPKT; 4373 if (wol->wolopts & WAKE_PHY) 4374 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY; 4375 4376 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 4377 &pme_ctrl_old); 4378 if (ret) 4379 return ret; 4380 4381 if (pme_ctrl_old == pme_ctrl) 4382 return 0; 4383 4384 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) && 4385 !(pme_ctrl & PME_WOL_MAGICPKT); 4386 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) && 4387 (pme_ctrl & PME_WOL_MAGICPKT); 4388 4389 /* To keep reference count of MAC address, we should do this 4390 * operation only on change of WOL settings. 4391 */ 4392 if (magic_switched_on) { 4393 ret = ksz_switch_macaddr_get(dev->ds, port, NULL); 4394 if (ret) 4395 return ret; 4396 } else if (magic_switched_off) { 4397 ksz_switch_macaddr_put(dev->ds); 4398 } 4399 4400 ret = dev->dev_ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 4401 pme_ctrl); 4402 if (ret) { 4403 if (magic_switched_on) 4404 ksz_switch_macaddr_put(dev->ds); 4405 return ret; 4406 } 4407 4408 return 0; 4409 } 4410 4411 /** 4412 * ksz_wol_pre_shutdown - Prepares the switch device for shutdown while 4413 * considering Wake-on-LAN (WoL) settings. 4414 * @dev: The switch device structure. 4415 * @wol_enabled: Pointer to a boolean which will be set to true if WoL is 4416 * enabled on any port. 4417 * 4418 * This function prepares the switch device for a safe shutdown while taking 4419 * into account the Wake-on-LAN (WoL) settings on the user ports. It updates 4420 * the wol_enabled flag accordingly to reflect whether WoL is active on any 4421 * port. 4422 */ 4423 static void ksz_wol_pre_shutdown(struct ksz_device *dev, bool *wol_enabled) 4424 { 4425 const struct ksz_dev_ops *ops = dev->dev_ops; 4426 const u16 *regs = dev->info->regs; 4427 u8 pme_pin_en = PME_ENABLE; 4428 struct dsa_port *dp; 4429 int ret; 4430 4431 *wol_enabled = false; 4432 4433 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4434 return; 4435 4436 if (!dev->wakeup_source) 4437 return; 4438 4439 dsa_switch_for_each_user_port(dp, dev->ds) { 4440 u8 pme_ctrl = 0; 4441 4442 ret = ops->pme_pread8(dev, dp->index, 4443 regs[REG_PORT_PME_CTRL], &pme_ctrl); 4444 if (!ret && pme_ctrl) 4445 *wol_enabled = true; 4446 4447 /* make sure there are no pending wake events which would 4448 * prevent the device from going to sleep/shutdown. 4449 */ 4450 ksz_handle_wake_reason(dev, dp->index); 4451 } 4452 4453 /* Now we are save to enable PME pin. */ 4454 if (*wol_enabled) { 4455 if (dev->pme_active_high) 4456 pme_pin_en |= PME_POLARITY; 4457 ops->pme_write8(dev, regs[REG_SW_PME_CTRL], pme_pin_en); 4458 if (ksz_is_ksz87xx(dev)) 4459 ksz_write8(dev, KSZ87XX_REG_INT_EN, KSZ87XX_INT_PME_MASK); 4460 } 4461 } 4462 4463 static int ksz_port_set_mac_address(struct dsa_switch *ds, int port, 4464 const unsigned char *addr) 4465 { 4466 struct dsa_port *dp = dsa_to_port(ds, port); 4467 struct ethtool_wolinfo wol; 4468 4469 if (dp->hsr_dev) { 4470 dev_err(ds->dev, 4471 "Cannot change MAC address on port %d with active HSR offload\n", 4472 port); 4473 return -EBUSY; 4474 } 4475 4476 /* Need to initialize variable as the code to fill in settings may 4477 * not be executed. 4478 */ 4479 wol.wolopts = 0; 4480 4481 ksz_get_wol(ds, dp->index, &wol); 4482 if (wol.wolopts & WAKE_MAGIC) { 4483 dev_err(ds->dev, 4484 "Cannot change MAC address on port %d with active Wake on Magic Packet\n", 4485 port); 4486 return -EBUSY; 4487 } 4488 4489 return 0; 4490 } 4491 4492 /** 4493 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port 4494 * can be used as a global address. 4495 * @ds: Pointer to the DSA switch structure. 4496 * @port: The port number on which the MAC address is to be checked. 4497 * 4498 * This function examines the MAC address set on the specified port and 4499 * determines if it can be used as a global address for the switch. 4500 * 4501 * Return: true if the port's MAC address can be used as a global address, false 4502 * otherwise. 4503 */ 4504 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port) 4505 { 4506 struct net_device *user = dsa_to_port(ds, port)->user; 4507 const unsigned char *addr = user->dev_addr; 4508 struct ksz_switch_macaddr *switch_macaddr; 4509 struct ksz_device *dev = ds->priv; 4510 4511 ASSERT_RTNL(); 4512 4513 switch_macaddr = dev->switch_macaddr; 4514 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr)) 4515 return false; 4516 4517 return true; 4518 } 4519 4520 /** 4521 * ksz_switch_macaddr_get - Program the switch's MAC address register. 4522 * @ds: DSA switch instance. 4523 * @port: Port number. 4524 * @extack: Netlink extended acknowledgment. 4525 * 4526 * This function programs the switch's MAC address register with the MAC address 4527 * of the requesting user port. This single address is used by the switch for 4528 * multiple features like HSR self-address filtering and WoL. Other user ports 4529 * can share ownership of this address as long as their MAC address is the same. 4530 * The MAC addresses of user ports must not change while they have ownership of 4531 * the switch MAC address. 4532 * 4533 * Return: 0 on success, or other error codes on failure. 4534 */ 4535 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 4536 struct netlink_ext_ack *extack) 4537 { 4538 struct net_device *user = dsa_to_port(ds, port)->user; 4539 const unsigned char *addr = user->dev_addr; 4540 struct ksz_switch_macaddr *switch_macaddr; 4541 struct ksz_device *dev = ds->priv; 4542 const u16 *regs = dev->info->regs; 4543 int i, ret; 4544 4545 /* Make sure concurrent MAC address changes are blocked */ 4546 ASSERT_RTNL(); 4547 4548 switch_macaddr = dev->switch_macaddr; 4549 if (switch_macaddr) { 4550 if (!ether_addr_equal(switch_macaddr->addr, addr)) { 4551 NL_SET_ERR_MSG_FMT_MOD(extack, 4552 "Switch already configured for MAC address %pM", 4553 switch_macaddr->addr); 4554 return -EBUSY; 4555 } 4556 4557 refcount_inc(&switch_macaddr->refcount); 4558 return 0; 4559 } 4560 4561 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL); 4562 if (!switch_macaddr) 4563 return -ENOMEM; 4564 4565 ether_addr_copy(switch_macaddr->addr, addr); 4566 refcount_set(&switch_macaddr->refcount, 1); 4567 dev->switch_macaddr = switch_macaddr; 4568 4569 /* Program the switch MAC address to hardware */ 4570 for (i = 0; i < ETH_ALEN; i++) { 4571 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, addr[i]); 4572 if (ret) 4573 goto macaddr_drop; 4574 } 4575 4576 return 0; 4577 4578 macaddr_drop: 4579 dev->switch_macaddr = NULL; 4580 refcount_set(&switch_macaddr->refcount, 0); 4581 kfree(switch_macaddr); 4582 4583 return ret; 4584 } 4585 4586 void ksz_switch_macaddr_put(struct dsa_switch *ds) 4587 { 4588 struct ksz_switch_macaddr *switch_macaddr; 4589 struct ksz_device *dev = ds->priv; 4590 const u16 *regs = dev->info->regs; 4591 int i; 4592 4593 /* Make sure concurrent MAC address changes are blocked */ 4594 ASSERT_RTNL(); 4595 4596 switch_macaddr = dev->switch_macaddr; 4597 if (!refcount_dec_and_test(&switch_macaddr->refcount)) 4598 return; 4599 4600 for (i = 0; i < ETH_ALEN; i++) 4601 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0); 4602 4603 dev->switch_macaddr = NULL; 4604 kfree(switch_macaddr); 4605 } 4606 4607 static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr, 4608 struct netlink_ext_ack *extack) 4609 { 4610 struct ksz_device *dev = ds->priv; 4611 enum hsr_version ver; 4612 int ret; 4613 4614 ret = hsr_get_version(hsr, &ver); 4615 if (ret) 4616 return ret; 4617 4618 if (dev->chip_id != KSZ9477_CHIP_ID) { 4619 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload"); 4620 return -EOPNOTSUPP; 4621 } 4622 4623 /* KSZ9477 can support HW offloading of only 1 HSR device */ 4624 if (dev->hsr_dev && hsr != dev->hsr_dev) { 4625 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR"); 4626 return -EOPNOTSUPP; 4627 } 4628 4629 /* KSZ9477 only supports HSR v0 and v1 */ 4630 if (!(ver == HSR_V0 || ver == HSR_V1)) { 4631 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported"); 4632 return -EOPNOTSUPP; 4633 } 4634 4635 /* KSZ9477 can only perform HSR offloading for up to two ports */ 4636 if (hweight8(dev->hsr_ports) >= 2) { 4637 NL_SET_ERR_MSG_MOD(extack, 4638 "Cannot offload more than two ports - using software HSR"); 4639 return -EOPNOTSUPP; 4640 } 4641 4642 /* Self MAC address filtering, to avoid frames traversing 4643 * the HSR ring more than once. 4644 */ 4645 ret = ksz_switch_macaddr_get(ds, port, extack); 4646 if (ret) 4647 return ret; 4648 4649 ksz9477_hsr_join(ds, port, hsr); 4650 dev->hsr_dev = hsr; 4651 dev->hsr_ports |= BIT(port); 4652 4653 return 0; 4654 } 4655 4656 static int ksz_hsr_leave(struct dsa_switch *ds, int port, 4657 struct net_device *hsr) 4658 { 4659 struct ksz_device *dev = ds->priv; 4660 4661 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID); 4662 4663 ksz9477_hsr_leave(ds, port, hsr); 4664 dev->hsr_ports &= ~BIT(port); 4665 if (!dev->hsr_ports) 4666 dev->hsr_dev = NULL; 4667 4668 ksz_switch_macaddr_put(ds); 4669 4670 return 0; 4671 } 4672 4673 static int ksz_suspend(struct dsa_switch *ds) 4674 { 4675 struct ksz_device *dev = ds->priv; 4676 4677 cancel_delayed_work_sync(&dev->mib_read); 4678 return 0; 4679 } 4680 4681 static int ksz_resume(struct dsa_switch *ds) 4682 { 4683 struct ksz_device *dev = ds->priv; 4684 4685 if (dev->mib_read_interval) 4686 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 4687 return 0; 4688 } 4689 4690 static const struct dsa_switch_ops ksz_switch_ops = { 4691 .get_tag_protocol = ksz_get_tag_protocol, 4692 .connect_tag_protocol = ksz_connect_tag_protocol, 4693 .get_phy_flags = ksz_get_phy_flags, 4694 .setup = ksz_setup, 4695 .teardown = ksz_teardown, 4696 .phy_read = ksz_phy_read16, 4697 .phy_write = ksz_phy_write16, 4698 .phylink_get_caps = ksz_phylink_get_caps, 4699 .port_setup = ksz_port_setup, 4700 .set_ageing_time = ksz_set_ageing_time, 4701 .get_strings = ksz_get_strings, 4702 .get_ethtool_stats = ksz_get_ethtool_stats, 4703 .get_sset_count = ksz_sset_count, 4704 .port_bridge_join = ksz_port_bridge_join, 4705 .port_bridge_leave = ksz_port_bridge_leave, 4706 .port_hsr_join = ksz_hsr_join, 4707 .port_hsr_leave = ksz_hsr_leave, 4708 .port_set_mac_address = ksz_port_set_mac_address, 4709 .port_stp_state_set = ksz_port_stp_state_set, 4710 .port_teardown = ksz_port_teardown, 4711 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 4712 .port_bridge_flags = ksz_port_bridge_flags, 4713 .port_fast_age = ksz_port_fast_age, 4714 .port_vlan_filtering = ksz_port_vlan_filtering, 4715 .port_vlan_add = ksz_port_vlan_add, 4716 .port_vlan_del = ksz_port_vlan_del, 4717 .port_fdb_dump = ksz_port_fdb_dump, 4718 .port_fdb_add = ksz_port_fdb_add, 4719 .port_fdb_del = ksz_port_fdb_del, 4720 .port_mdb_add = ksz_port_mdb_add, 4721 .port_mdb_del = ksz_port_mdb_del, 4722 .port_mirror_add = ksz_port_mirror_add, 4723 .port_mirror_del = ksz_port_mirror_del, 4724 .get_stats64 = ksz_get_stats64, 4725 .get_pause_stats = ksz_get_pause_stats, 4726 .port_change_mtu = ksz_change_mtu, 4727 .port_max_mtu = ksz_max_mtu, 4728 .get_wol = ksz_get_wol, 4729 .set_wol = ksz_set_wol, 4730 .suspend = ksz_suspend, 4731 .resume = ksz_resume, 4732 .get_ts_info = ksz_get_ts_info, 4733 .port_hwtstamp_get = ksz_hwtstamp_get, 4734 .port_hwtstamp_set = ksz_hwtstamp_set, 4735 .port_txtstamp = ksz_port_txtstamp, 4736 .port_rxtstamp = ksz_port_rxtstamp, 4737 .cls_flower_add = ksz_cls_flower_add, 4738 .cls_flower_del = ksz_cls_flower_del, 4739 .port_setup_tc = ksz_setup_tc, 4740 .support_eee = ksz_support_eee, 4741 .set_mac_eee = ksz_set_mac_eee, 4742 .port_get_default_prio = ksz_port_get_default_prio, 4743 .port_set_default_prio = ksz_port_set_default_prio, 4744 .port_get_dscp_prio = ksz_port_get_dscp_prio, 4745 .port_add_dscp_prio = ksz_port_add_dscp_prio, 4746 .port_del_dscp_prio = ksz_port_del_dscp_prio, 4747 .port_get_apptrust = ksz_port_get_apptrust, 4748 .port_set_apptrust = ksz_port_set_apptrust, 4749 }; 4750 4751 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 4752 { 4753 struct dsa_switch *ds; 4754 struct ksz_device *swdev; 4755 4756 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 4757 if (!ds) 4758 return NULL; 4759 4760 ds->dev = base; 4761 ds->num_ports = DSA_MAX_PORTS; 4762 ds->ops = &ksz_switch_ops; 4763 4764 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 4765 if (!swdev) 4766 return NULL; 4767 4768 ds->priv = swdev; 4769 swdev->dev = base; 4770 4771 swdev->ds = ds; 4772 swdev->priv = priv; 4773 4774 return swdev; 4775 } 4776 EXPORT_SYMBOL(ksz_switch_alloc); 4777 4778 /** 4779 * ksz_switch_shutdown - Shutdown routine for the switch device. 4780 * @dev: The switch device structure. 4781 * 4782 * This function is responsible for initiating a shutdown sequence for the 4783 * switch device. It invokes the reset operation defined in the device 4784 * operations, if available, to reset the switch. Subsequently, it calls the 4785 * DSA framework's shutdown function to ensure a proper shutdown of the DSA 4786 * switch. 4787 */ 4788 void ksz_switch_shutdown(struct ksz_device *dev) 4789 { 4790 bool wol_enabled = false; 4791 4792 ksz_wol_pre_shutdown(dev, &wol_enabled); 4793 4794 if (dev->dev_ops->reset && !wol_enabled) 4795 dev->dev_ops->reset(dev); 4796 4797 dsa_switch_shutdown(dev->ds); 4798 } 4799 EXPORT_SYMBOL(ksz_switch_shutdown); 4800 4801 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 4802 struct device_node *port_dn) 4803 { 4804 phy_interface_t phy_mode = dev->ports[port_num].interface; 4805 int rx_delay = -1, tx_delay = -1; 4806 4807 if (!phy_interface_mode_is_rgmii(phy_mode)) 4808 return; 4809 4810 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 4811 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 4812 4813 if (rx_delay == -1 && tx_delay == -1) { 4814 dev_warn(dev->dev, 4815 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 4816 "please update device tree to specify \"rx-internal-delay-ps\" and " 4817 "\"tx-internal-delay-ps\"", 4818 port_num); 4819 4820 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 4821 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 4822 rx_delay = 2000; 4823 4824 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 4825 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 4826 tx_delay = 2000; 4827 } 4828 4829 if (rx_delay < 0) 4830 rx_delay = 0; 4831 if (tx_delay < 0) 4832 tx_delay = 0; 4833 4834 dev->ports[port_num].rgmii_rx_val = rx_delay; 4835 dev->ports[port_num].rgmii_tx_val = tx_delay; 4836 } 4837 4838 /** 4839 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding 4840 * register value. 4841 * @array: The array of drive strength values to search. 4842 * @array_size: The size of the array. 4843 * @microamp: The drive strength value in microamp to be converted. 4844 * 4845 * This function searches the array of drive strength values for the given 4846 * microamp value and returns the corresponding register value for that drive. 4847 * 4848 * Returns: If found, the corresponding register value for that drive strength 4849 * is returned. Otherwise, -EINVAL is returned indicating an invalid value. 4850 */ 4851 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array, 4852 size_t array_size, int microamp) 4853 { 4854 int i; 4855 4856 for (i = 0; i < array_size; i++) { 4857 if (array[i].microamp == microamp) 4858 return array[i].reg_val; 4859 } 4860 4861 return -EINVAL; 4862 } 4863 4864 /** 4865 * ksz_drive_strength_error() - Report invalid drive strength value 4866 * @dev: ksz device 4867 * @array: The array of drive strength values to search. 4868 * @array_size: The size of the array. 4869 * @microamp: Invalid drive strength value in microamp 4870 * 4871 * This function logs an error message when an unsupported drive strength value 4872 * is detected. It lists out all the supported drive strength values for 4873 * reference in the error message. 4874 */ 4875 static void ksz_drive_strength_error(struct ksz_device *dev, 4876 const struct ksz_drive_strength *array, 4877 size_t array_size, int microamp) 4878 { 4879 char supported_values[100]; 4880 size_t remaining_size; 4881 int added_len; 4882 char *ptr; 4883 int i; 4884 4885 remaining_size = sizeof(supported_values); 4886 ptr = supported_values; 4887 4888 for (i = 0; i < array_size; i++) { 4889 added_len = snprintf(ptr, remaining_size, 4890 i == 0 ? "%d" : ", %d", array[i].microamp); 4891 4892 if (added_len >= remaining_size) 4893 break; 4894 4895 ptr += added_len; 4896 remaining_size -= added_len; 4897 } 4898 4899 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n", 4900 microamp, supported_values); 4901 } 4902 4903 /** 4904 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477 4905 * chip variants. 4906 * @dev: ksz device 4907 * @props: Array of drive strength properties to be applied 4908 * @num_props: Number of properties in the array 4909 * 4910 * This function configures the drive strength for various KSZ9477 chip variants 4911 * based on the provided properties. It handles chip-specific nuances and 4912 * ensures only valid drive strengths are written to the respective chip. 4913 * 4914 * Return: 0 on successful configuration, a negative error code on failure. 4915 */ 4916 static int ksz9477_drive_strength_write(struct ksz_device *dev, 4917 struct ksz_driver_strength_prop *props, 4918 int num_props) 4919 { 4920 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths); 4921 int i, ret, reg; 4922 u8 mask = 0; 4923 u8 val = 0; 4924 4925 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1) 4926 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4927 props[KSZ_DRIVER_STRENGTH_IO].name); 4928 4929 if (dev->chip_id == KSZ8795_CHIP_ID || 4930 dev->chip_id == KSZ8794_CHIP_ID || 4931 dev->chip_id == KSZ8765_CHIP_ID) 4932 reg = KSZ8795_REG_SW_CTRL_20; 4933 else 4934 reg = KSZ9477_REG_SW_IO_STRENGTH; 4935 4936 for (i = 0; i < num_props; i++) { 4937 if (props[i].value == -1) 4938 continue; 4939 4940 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths, 4941 array_size, props[i].value); 4942 if (ret < 0) { 4943 ksz_drive_strength_error(dev, ksz9477_drive_strengths, 4944 array_size, props[i].value); 4945 return ret; 4946 } 4947 4948 mask |= SW_DRIVE_STRENGTH_M << props[i].offset; 4949 val |= ret << props[i].offset; 4950 } 4951 4952 return ksz_rmw8(dev, reg, mask, val); 4953 } 4954 4955 /** 4956 * ksz88x3_drive_strength_write() - Set the drive strength configuration for 4957 * KSZ8863 compatible chip variants. 4958 * @dev: ksz device 4959 * @props: Array of drive strength properties to be set 4960 * @num_props: Number of properties in the array 4961 * 4962 * This function applies the specified drive strength settings to KSZ88X3 chip 4963 * variants (KSZ8873, KSZ8863). 4964 * It ensures the configurations align with what the chip variant supports and 4965 * warns or errors out on unsupported settings. 4966 * 4967 * Return: 0 on success, error code otherwise 4968 */ 4969 static int ksz88x3_drive_strength_write(struct ksz_device *dev, 4970 struct ksz_driver_strength_prop *props, 4971 int num_props) 4972 { 4973 size_t array_size = ARRAY_SIZE(ksz88x3_drive_strengths); 4974 int microamp; 4975 int i, ret; 4976 4977 for (i = 0; i < num_props; i++) { 4978 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO) 4979 continue; 4980 4981 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4982 props[i].name); 4983 } 4984 4985 microamp = props[KSZ_DRIVER_STRENGTH_IO].value; 4986 ret = ksz_drive_strength_to_reg(ksz88x3_drive_strengths, array_size, 4987 microamp); 4988 if (ret < 0) { 4989 ksz_drive_strength_error(dev, ksz88x3_drive_strengths, 4990 array_size, microamp); 4991 return ret; 4992 } 4993 4994 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12, 4995 KSZ8873_DRIVE_STRENGTH_16MA, ret); 4996 } 4997 4998 /** 4999 * ksz_parse_drive_strength() - Extract and apply drive strength configurations 5000 * from device tree properties. 5001 * @dev: ksz device 5002 * 5003 * This function reads the specified drive strength properties from the 5004 * device tree, validates against the supported chip variants, and sets 5005 * them accordingly. An error should be critical here, as the drive strength 5006 * settings are crucial for EMI compliance. 5007 * 5008 * Return: 0 on success, error code otherwise 5009 */ 5010 static int ksz_parse_drive_strength(struct ksz_device *dev) 5011 { 5012 struct ksz_driver_strength_prop of_props[] = { 5013 [KSZ_DRIVER_STRENGTH_HI] = { 5014 .name = "microchip,hi-drive-strength-microamp", 5015 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S, 5016 .value = -1, 5017 }, 5018 [KSZ_DRIVER_STRENGTH_LO] = { 5019 .name = "microchip,lo-drive-strength-microamp", 5020 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S, 5021 .value = -1, 5022 }, 5023 [KSZ_DRIVER_STRENGTH_IO] = { 5024 .name = "microchip,io-drive-strength-microamp", 5025 .offset = 0, /* don't care */ 5026 .value = -1, 5027 }, 5028 }; 5029 struct device_node *np = dev->dev->of_node; 5030 bool have_any_prop = false; 5031 int i, ret; 5032 5033 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 5034 ret = of_property_read_u32(np, of_props[i].name, 5035 &of_props[i].value); 5036 if (ret && ret != -EINVAL) 5037 dev_warn(dev->dev, "Failed to read %s\n", 5038 of_props[i].name); 5039 if (ret) 5040 continue; 5041 5042 have_any_prop = true; 5043 } 5044 5045 if (!have_any_prop) 5046 return 0; 5047 5048 switch (dev->chip_id) { 5049 case KSZ88X3_CHIP_ID: 5050 return ksz88x3_drive_strength_write(dev, of_props, 5051 ARRAY_SIZE(of_props)); 5052 case KSZ8795_CHIP_ID: 5053 case KSZ8794_CHIP_ID: 5054 case KSZ8765_CHIP_ID: 5055 case KSZ8563_CHIP_ID: 5056 case KSZ8567_CHIP_ID: 5057 case KSZ9477_CHIP_ID: 5058 case KSZ9563_CHIP_ID: 5059 case KSZ9567_CHIP_ID: 5060 case KSZ9893_CHIP_ID: 5061 case KSZ9896_CHIP_ID: 5062 case KSZ9897_CHIP_ID: 5063 case LAN9646_CHIP_ID: 5064 return ksz9477_drive_strength_write(dev, of_props, 5065 ARRAY_SIZE(of_props)); 5066 default: 5067 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 5068 if (of_props[i].value == -1) 5069 continue; 5070 5071 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 5072 of_props[i].name); 5073 } 5074 } 5075 5076 return 0; 5077 } 5078 5079 int ksz_switch_register(struct ksz_device *dev) 5080 { 5081 const struct ksz_chip_data *info; 5082 struct device_node *ports; 5083 phy_interface_t interface; 5084 unsigned int port_num; 5085 int ret; 5086 int i; 5087 5088 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 5089 GPIOD_OUT_LOW); 5090 if (IS_ERR(dev->reset_gpio)) 5091 return PTR_ERR(dev->reset_gpio); 5092 5093 if (dev->reset_gpio) { 5094 gpiod_set_value_cansleep(dev->reset_gpio, 1); 5095 usleep_range(10000, 12000); 5096 gpiod_set_value_cansleep(dev->reset_gpio, 0); 5097 msleep(100); 5098 } 5099 5100 mutex_init(&dev->dev_mutex); 5101 mutex_init(&dev->regmap_mutex); 5102 mutex_init(&dev->alu_mutex); 5103 mutex_init(&dev->vlan_mutex); 5104 5105 ret = ksz_switch_detect(dev); 5106 if (ret) 5107 return ret; 5108 5109 info = ksz_lookup_info(dev->chip_id); 5110 if (!info) 5111 return -ENODEV; 5112 5113 /* Update the compatible info with the probed one */ 5114 dev->info = info; 5115 5116 dev_info(dev->dev, "found switch: %s, rev %i\n", 5117 dev->info->dev_name, dev->chip_rev); 5118 5119 ret = ksz_check_device_id(dev); 5120 if (ret) 5121 return ret; 5122 5123 dev->dev_ops = dev->info->ops; 5124 5125 ret = dev->dev_ops->init(dev); 5126 if (ret) 5127 return ret; 5128 5129 dev->ports = devm_kzalloc(dev->dev, 5130 dev->info->port_cnt * sizeof(struct ksz_port), 5131 GFP_KERNEL); 5132 if (!dev->ports) 5133 return -ENOMEM; 5134 5135 for (i = 0; i < dev->info->port_cnt; i++) { 5136 spin_lock_init(&dev->ports[i].mib.stats64_lock); 5137 mutex_init(&dev->ports[i].mib.cnt_mutex); 5138 dev->ports[i].mib.counters = 5139 devm_kzalloc(dev->dev, 5140 sizeof(u64) * (dev->info->mib_cnt + 1), 5141 GFP_KERNEL); 5142 if (!dev->ports[i].mib.counters) 5143 return -ENOMEM; 5144 5145 dev->ports[i].ksz_dev = dev; 5146 dev->ports[i].num = i; 5147 } 5148 5149 /* set the real number of ports */ 5150 dev->ds->num_ports = dev->info->port_cnt; 5151 5152 /* set the phylink ops */ 5153 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops; 5154 5155 /* Host port interface will be self detected, or specifically set in 5156 * device tree. 5157 */ 5158 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 5159 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 5160 if (dev->dev->of_node) { 5161 ret = of_get_phy_mode(dev->dev->of_node, &interface); 5162 if (ret == 0) 5163 dev->compat_interface = interface; 5164 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 5165 if (!ports) 5166 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 5167 if (ports) { 5168 for_each_available_child_of_node_scoped(ports, port) { 5169 if (of_property_read_u32(port, "reg", 5170 &port_num)) 5171 continue; 5172 if (!(dev->port_mask & BIT(port_num))) { 5173 of_node_put(ports); 5174 return -EINVAL; 5175 } 5176 of_get_phy_mode(port, 5177 &dev->ports[port_num].interface); 5178 5179 ksz_parse_rgmii_delay(dev, port_num, port); 5180 } 5181 of_node_put(ports); 5182 } 5183 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 5184 "microchip,synclko-125"); 5185 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 5186 "microchip,synclko-disable"); 5187 if (dev->synclko_125 && dev->synclko_disable) { 5188 dev_err(dev->dev, "inconsistent synclko settings\n"); 5189 return -EINVAL; 5190 } 5191 5192 dev->wakeup_source = of_property_read_bool(dev->dev->of_node, 5193 "wakeup-source"); 5194 dev->pme_active_high = of_property_read_bool(dev->dev->of_node, 5195 "microchip,pme-active-high"); 5196 } 5197 5198 ret = dsa_register_switch(dev->ds); 5199 if (ret) { 5200 dev->dev_ops->exit(dev); 5201 return ret; 5202 } 5203 5204 /* Read MIB counters every 30 seconds to avoid overflow. */ 5205 dev->mib_read_interval = msecs_to_jiffies(5000); 5206 5207 /* Start the MIB timer. */ 5208 schedule_delayed_work(&dev->mib_read, 0); 5209 5210 return ret; 5211 } 5212 EXPORT_SYMBOL(ksz_switch_register); 5213 5214 void ksz_switch_remove(struct ksz_device *dev) 5215 { 5216 /* timer started */ 5217 if (dev->mib_read_interval) { 5218 dev->mib_read_interval = 0; 5219 cancel_delayed_work_sync(&dev->mib_read); 5220 } 5221 5222 dev->dev_ops->exit(dev); 5223 dsa_unregister_switch(dev->ds); 5224 5225 if (dev->reset_gpio) 5226 gpiod_set_value_cansleep(dev->reset_gpio, 1); 5227 5228 } 5229 EXPORT_SYMBOL(ksz_switch_remove); 5230 5231 #ifdef CONFIG_PM_SLEEP 5232 int ksz_switch_suspend(struct device *dev) 5233 { 5234 struct ksz_device *priv = dev_get_drvdata(dev); 5235 5236 return dsa_switch_suspend(priv->ds); 5237 } 5238 EXPORT_SYMBOL(ksz_switch_suspend); 5239 5240 int ksz_switch_resume(struct device *dev) 5241 { 5242 struct ksz_device *priv = dev_get_drvdata(dev); 5243 5244 return dsa_switch_resume(priv->ds); 5245 } 5246 EXPORT_SYMBOL(ksz_switch_resume); 5247 #endif 5248 5249 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 5250 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 5251 MODULE_LICENSE("GPL"); 5252