1 /* 2 * Microchip switch driver main logic 3 * 4 * Copyright (C) 2017 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <linux/delay.h> 20 #include <linux/export.h> 21 #include <linux/gpio.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/platform_data/microchip-ksz.h> 25 #include <linux/phy.h> 26 #include <linux/etherdevice.h> 27 #include <linux/if_bridge.h> 28 #include <net/dsa.h> 29 #include <net/switchdev.h> 30 31 #include "ksz_priv.h" 32 33 static const struct { 34 int index; 35 char string[ETH_GSTRING_LEN]; 36 } mib_names[TOTAL_SWITCH_COUNTER_NUM] = { 37 { 0x00, "rx_hi" }, 38 { 0x01, "rx_undersize" }, 39 { 0x02, "rx_fragments" }, 40 { 0x03, "rx_oversize" }, 41 { 0x04, "rx_jabbers" }, 42 { 0x05, "rx_symbol_err" }, 43 { 0x06, "rx_crc_err" }, 44 { 0x07, "rx_align_err" }, 45 { 0x08, "rx_mac_ctrl" }, 46 { 0x09, "rx_pause" }, 47 { 0x0A, "rx_bcast" }, 48 { 0x0B, "rx_mcast" }, 49 { 0x0C, "rx_ucast" }, 50 { 0x0D, "rx_64_or_less" }, 51 { 0x0E, "rx_65_127" }, 52 { 0x0F, "rx_128_255" }, 53 { 0x10, "rx_256_511" }, 54 { 0x11, "rx_512_1023" }, 55 { 0x12, "rx_1024_1522" }, 56 { 0x13, "rx_1523_2000" }, 57 { 0x14, "rx_2001" }, 58 { 0x15, "tx_hi" }, 59 { 0x16, "tx_late_col" }, 60 { 0x17, "tx_pause" }, 61 { 0x18, "tx_bcast" }, 62 { 0x19, "tx_mcast" }, 63 { 0x1A, "tx_ucast" }, 64 { 0x1B, "tx_deferred" }, 65 { 0x1C, "tx_total_col" }, 66 { 0x1D, "tx_exc_col" }, 67 { 0x1E, "tx_single_col" }, 68 { 0x1F, "tx_mult_col" }, 69 { 0x80, "rx_total" }, 70 { 0x81, "tx_total" }, 71 { 0x82, "rx_discards" }, 72 { 0x83, "tx_discards" }, 73 }; 74 75 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 76 { 77 u8 data; 78 79 ksz_read8(dev, addr, &data); 80 if (set) 81 data |= bits; 82 else 83 data &= ~bits; 84 ksz_write8(dev, addr, data); 85 } 86 87 static void ksz_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 88 { 89 u32 data; 90 91 ksz_read32(dev, addr, &data); 92 if (set) 93 data |= bits; 94 else 95 data &= ~bits; 96 ksz_write32(dev, addr, data); 97 } 98 99 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 100 bool set) 101 { 102 u32 addr; 103 u8 data; 104 105 addr = PORT_CTRL_ADDR(port, offset); 106 ksz_read8(dev, addr, &data); 107 108 if (set) 109 data |= bits; 110 else 111 data &= ~bits; 112 113 ksz_write8(dev, addr, data); 114 } 115 116 static void ksz_port_cfg32(struct ksz_device *dev, int port, int offset, 117 u32 bits, bool set) 118 { 119 u32 addr; 120 u32 data; 121 122 addr = PORT_CTRL_ADDR(port, offset); 123 ksz_read32(dev, addr, &data); 124 125 if (set) 126 data |= bits; 127 else 128 data &= ~bits; 129 130 ksz_write32(dev, addr, data); 131 } 132 133 static int wait_vlan_ctrl_ready(struct ksz_device *dev, u32 waiton, int timeout) 134 { 135 u8 data; 136 137 do { 138 ksz_read8(dev, REG_SW_VLAN_CTRL, &data); 139 if (!(data & waiton)) 140 break; 141 usleep_range(1, 10); 142 } while (timeout-- > 0); 143 144 if (timeout <= 0) 145 return -ETIMEDOUT; 146 147 return 0; 148 } 149 150 static int get_vlan_table(struct dsa_switch *ds, u16 vid, u32 *vlan_table) 151 { 152 struct ksz_device *dev = ds->priv; 153 int ret; 154 155 mutex_lock(&dev->vlan_mutex); 156 157 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 158 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 159 160 /* wait to be cleared */ 161 ret = wait_vlan_ctrl_ready(dev, VLAN_START, 1000); 162 if (ret < 0) { 163 dev_dbg(dev->dev, "Failed to read vlan table\n"); 164 goto exit; 165 } 166 167 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 168 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 169 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 170 171 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 172 173 exit: 174 mutex_unlock(&dev->vlan_mutex); 175 176 return ret; 177 } 178 179 static int set_vlan_table(struct dsa_switch *ds, u16 vid, u32 *vlan_table) 180 { 181 struct ksz_device *dev = ds->priv; 182 int ret; 183 184 mutex_lock(&dev->vlan_mutex); 185 186 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 187 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 188 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 189 190 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 191 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 192 193 /* wait to be cleared */ 194 ret = wait_vlan_ctrl_ready(dev, VLAN_START, 1000); 195 if (ret < 0) { 196 dev_dbg(dev->dev, "Failed to write vlan table\n"); 197 goto exit; 198 } 199 200 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 201 202 /* update vlan cache table */ 203 dev->vlan_cache[vid].table[0] = vlan_table[0]; 204 dev->vlan_cache[vid].table[1] = vlan_table[1]; 205 dev->vlan_cache[vid].table[2] = vlan_table[2]; 206 207 exit: 208 mutex_unlock(&dev->vlan_mutex); 209 210 return ret; 211 } 212 213 static void read_table(struct dsa_switch *ds, u32 *table) 214 { 215 struct ksz_device *dev = ds->priv; 216 217 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 218 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 219 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 220 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 221 } 222 223 static void write_table(struct dsa_switch *ds, u32 *table) 224 { 225 struct ksz_device *dev = ds->priv; 226 227 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 228 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 229 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 230 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 231 } 232 233 static int wait_alu_ready(struct ksz_device *dev, u32 waiton, int timeout) 234 { 235 u32 data; 236 237 do { 238 ksz_read32(dev, REG_SW_ALU_CTRL__4, &data); 239 if (!(data & waiton)) 240 break; 241 usleep_range(1, 10); 242 } while (timeout-- > 0); 243 244 if (timeout <= 0) 245 return -ETIMEDOUT; 246 247 return 0; 248 } 249 250 static int wait_alu_sta_ready(struct ksz_device *dev, u32 waiton, int timeout) 251 { 252 u32 data; 253 254 do { 255 ksz_read32(dev, REG_SW_ALU_STAT_CTRL__4, &data); 256 if (!(data & waiton)) 257 break; 258 usleep_range(1, 10); 259 } while (timeout-- > 0); 260 261 if (timeout <= 0) 262 return -ETIMEDOUT; 263 264 return 0; 265 } 266 267 static int ksz_reset_switch(struct dsa_switch *ds) 268 { 269 struct ksz_device *dev = ds->priv; 270 u8 data8; 271 u16 data16; 272 u32 data32; 273 274 /* reset switch */ 275 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 276 277 /* turn off SPI DO Edge select */ 278 ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 279 data8 &= ~SPI_AUTO_EDGE_DETECTION; 280 ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 281 282 /* default configuration */ 283 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 284 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING | 285 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE; 286 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 287 288 /* disable interrupts */ 289 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 290 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 291 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 292 293 /* set broadcast storm protection 10% rate */ 294 ksz_read16(dev, REG_SW_MAC_CTRL_2, &data16); 295 data16 &= ~BROADCAST_STORM_RATE; 296 data16 |= (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100; 297 ksz_write16(dev, REG_SW_MAC_CTRL_2, data16); 298 299 return 0; 300 } 301 302 static void port_setup(struct ksz_device *dev, int port, bool cpu_port) 303 { 304 u8 data8; 305 u16 data16; 306 307 /* enable tag tail for host port */ 308 if (cpu_port) 309 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 310 true); 311 312 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 313 314 /* set back pressure */ 315 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 316 317 /* set flow control */ 318 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 319 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, true); 320 321 /* enable broadcast storm limit */ 322 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 323 324 /* disable DiffServ priority */ 325 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false); 326 327 /* replace priority */ 328 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 329 false); 330 ksz_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 331 MTI_PVID_REPLACE, false); 332 333 /* enable 802.1p priority */ 334 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 335 336 /* configure MAC to 1G & RGMII mode */ 337 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 338 data8 |= PORT_RGMII_ID_EG_ENABLE; 339 data8 &= ~PORT_MII_NOT_1GBIT; 340 data8 &= ~PORT_MII_SEL_M; 341 data8 |= PORT_RGMII_SEL; 342 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8); 343 344 /* clear pending interrupts */ 345 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 346 } 347 348 static void ksz_config_cpu_port(struct dsa_switch *ds) 349 { 350 struct ksz_device *dev = ds->priv; 351 int i; 352 353 ds->num_ports = dev->port_cnt; 354 355 for (i = 0; i < ds->num_ports; i++) { 356 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) { 357 dev->cpu_port = i; 358 359 /* enable cpu port */ 360 port_setup(dev, i, true); 361 } 362 } 363 } 364 365 static int ksz_setup(struct dsa_switch *ds) 366 { 367 struct ksz_device *dev = ds->priv; 368 int ret = 0; 369 370 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 371 dev->num_vlans, GFP_KERNEL); 372 if (!dev->vlan_cache) 373 return -ENOMEM; 374 375 ret = ksz_reset_switch(ds); 376 if (ret) { 377 dev_err(ds->dev, "failed to reset switch\n"); 378 return ret; 379 } 380 381 /* accept packet up to 2000bytes */ 382 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true); 383 384 ksz_config_cpu_port(ds); 385 386 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true); 387 388 /* queue based egress rate limit */ 389 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 390 391 /* start switch */ 392 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true); 393 394 return 0; 395 } 396 397 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds) 398 { 399 return DSA_TAG_PROTO_KSZ; 400 } 401 402 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 403 { 404 struct ksz_device *dev = ds->priv; 405 u16 val = 0; 406 407 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 408 409 return val; 410 } 411 412 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 413 { 414 struct ksz_device *dev = ds->priv; 415 416 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 417 418 return 0; 419 } 420 421 static int ksz_enable_port(struct dsa_switch *ds, int port, 422 struct phy_device *phy) 423 { 424 struct ksz_device *dev = ds->priv; 425 426 /* setup slave port */ 427 port_setup(dev, port, false); 428 429 return 0; 430 } 431 432 static void ksz_disable_port(struct dsa_switch *ds, int port, 433 struct phy_device *phy) 434 { 435 struct ksz_device *dev = ds->priv; 436 437 /* there is no port disable */ 438 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, true); 439 } 440 441 static int ksz_sset_count(struct dsa_switch *ds) 442 { 443 return TOTAL_SWITCH_COUNTER_NUM; 444 } 445 446 static void ksz_get_strings(struct dsa_switch *ds, int port, uint8_t *buf) 447 { 448 int i; 449 450 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) { 451 memcpy(buf + i * ETH_GSTRING_LEN, mib_names[i].string, 452 ETH_GSTRING_LEN); 453 } 454 } 455 456 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 457 uint64_t *buf) 458 { 459 struct ksz_device *dev = ds->priv; 460 int i; 461 u32 data; 462 int timeout; 463 464 mutex_lock(&dev->stats_mutex); 465 466 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) { 467 data = MIB_COUNTER_READ; 468 data |= ((mib_names[i].index & 0xFF) << MIB_COUNTER_INDEX_S); 469 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 470 471 timeout = 1000; 472 do { 473 ksz_pread32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 474 &data); 475 usleep_range(1, 10); 476 if (!(data & MIB_COUNTER_READ)) 477 break; 478 } while (timeout-- > 0); 479 480 /* failed to read MIB. get out of loop */ 481 if (!timeout) { 482 dev_dbg(dev->dev, "Failed to get MIB\n"); 483 break; 484 } 485 486 /* count resets upon read */ 487 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 488 489 dev->mib_value[i] += (uint64_t)data; 490 buf[i] = dev->mib_value[i]; 491 } 492 493 mutex_unlock(&dev->stats_mutex); 494 } 495 496 static void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 497 { 498 struct ksz_device *dev = ds->priv; 499 u8 data; 500 501 ksz_pread8(dev, port, P_STP_CTRL, &data); 502 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 503 504 switch (state) { 505 case BR_STATE_DISABLED: 506 data |= PORT_LEARN_DISABLE; 507 break; 508 case BR_STATE_LISTENING: 509 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 510 break; 511 case BR_STATE_LEARNING: 512 data |= PORT_RX_ENABLE; 513 break; 514 case BR_STATE_FORWARDING: 515 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 516 break; 517 case BR_STATE_BLOCKING: 518 data |= PORT_LEARN_DISABLE; 519 break; 520 default: 521 dev_err(ds->dev, "invalid STP state: %d\n", state); 522 return; 523 } 524 525 ksz_pwrite8(dev, port, P_STP_CTRL, data); 526 } 527 528 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 529 { 530 struct ksz_device *dev = ds->priv; 531 u8 data8; 532 533 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 534 data8 |= SW_FAST_AGING; 535 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 536 537 data8 &= ~SW_FAST_AGING; 538 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 539 } 540 541 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, bool flag) 542 { 543 struct ksz_device *dev = ds->priv; 544 545 if (flag) { 546 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 547 PORT_VLAN_LOOKUP_VID_0, true); 548 ksz_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, true); 549 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 550 } else { 551 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 552 ksz_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, false); 553 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 554 PORT_VLAN_LOOKUP_VID_0, false); 555 } 556 557 return 0; 558 } 559 560 static int ksz_port_vlan_prepare(struct dsa_switch *ds, int port, 561 const struct switchdev_obj_port_vlan *vlan, 562 struct switchdev_trans *trans) 563 { 564 /* nothing needed */ 565 566 return 0; 567 } 568 569 static void ksz_port_vlan_add(struct dsa_switch *ds, int port, 570 const struct switchdev_obj_port_vlan *vlan, 571 struct switchdev_trans *trans) 572 { 573 struct ksz_device *dev = ds->priv; 574 u32 vlan_table[3]; 575 u16 vid; 576 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 577 578 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 579 if (get_vlan_table(ds, vid, vlan_table)) { 580 dev_dbg(dev->dev, "Failed to get vlan table\n"); 581 return; 582 } 583 584 vlan_table[0] = VLAN_VALID | (vid & VLAN_FID_M); 585 if (untagged) 586 vlan_table[1] |= BIT(port); 587 else 588 vlan_table[1] &= ~BIT(port); 589 vlan_table[1] &= ~(BIT(dev->cpu_port)); 590 591 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 592 593 if (set_vlan_table(ds, vid, vlan_table)) { 594 dev_dbg(dev->dev, "Failed to set vlan table\n"); 595 return; 596 } 597 598 /* change PVID */ 599 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 600 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vid); 601 } 602 } 603 604 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 605 const struct switchdev_obj_port_vlan *vlan) 606 { 607 struct ksz_device *dev = ds->priv; 608 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 609 u32 vlan_table[3]; 610 u16 vid; 611 u16 pvid; 612 613 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 614 pvid = pvid & 0xFFF; 615 616 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 617 if (get_vlan_table(ds, vid, vlan_table)) { 618 dev_dbg(dev->dev, "Failed to get vlan table\n"); 619 return -ETIMEDOUT; 620 } 621 622 vlan_table[2] &= ~BIT(port); 623 624 if (pvid == vid) 625 pvid = 1; 626 627 if (untagged) 628 vlan_table[1] &= ~BIT(port); 629 630 if (set_vlan_table(ds, vid, vlan_table)) { 631 dev_dbg(dev->dev, "Failed to set vlan table\n"); 632 return -ETIMEDOUT; 633 } 634 } 635 636 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 637 638 return 0; 639 } 640 641 static int ksz_port_vlan_dump(struct dsa_switch *ds, int port, 642 struct switchdev_obj_port_vlan *vlan, 643 switchdev_obj_dump_cb_t *cb) 644 { 645 struct ksz_device *dev = ds->priv; 646 u16 vid; 647 u16 data; 648 struct vlan_table *vlan_cache; 649 int err = 0; 650 651 mutex_lock(&dev->vlan_mutex); 652 653 /* use dev->vlan_cache due to lack of searching valid vlan entry */ 654 for (vid = vlan->vid_begin; vid < dev->num_vlans; vid++) { 655 vlan_cache = &dev->vlan_cache[vid]; 656 657 if (!(vlan_cache->table[0] & VLAN_VALID)) 658 continue; 659 660 vlan->vid_begin = vid; 661 vlan->vid_end = vid; 662 vlan->flags = 0; 663 if (vlan_cache->table[2] & BIT(port)) { 664 if (vlan_cache->table[1] & BIT(port)) 665 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED; 666 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &data); 667 if (vid == (data & 0xFFFFF)) 668 vlan->flags |= BRIDGE_VLAN_INFO_PVID; 669 670 err = cb(&vlan->obj); 671 if (err) 672 break; 673 } 674 } 675 676 mutex_unlock(&dev->vlan_mutex); 677 678 return err; 679 } 680 681 static int ksz_port_fdb_prepare(struct dsa_switch *ds, int port, 682 const struct switchdev_obj_port_fdb *fdb, 683 struct switchdev_trans *trans) 684 { 685 /* nothing needed */ 686 687 return 0; 688 } 689 690 struct alu_struct { 691 /* entry 1 */ 692 u8 is_static:1; 693 u8 is_src_filter:1; 694 u8 is_dst_filter:1; 695 u8 prio_age:3; 696 u32 _reserv_0_1:23; 697 u8 mstp:3; 698 /* entry 2 */ 699 u8 is_override:1; 700 u8 is_use_fid:1; 701 u32 _reserv_1_1:23; 702 u8 port_forward:7; 703 /* entry 3 & 4*/ 704 u32 _reserv_2_1:9; 705 u8 fid:7; 706 u8 mac[ETH_ALEN]; 707 }; 708 709 static void ksz_port_fdb_add(struct dsa_switch *ds, int port, 710 const struct switchdev_obj_port_fdb *fdb, 711 struct switchdev_trans *trans) 712 { 713 struct ksz_device *dev = ds->priv; 714 u32 alu_table[4]; 715 u32 data; 716 717 mutex_lock(&dev->alu_mutex); 718 719 /* find any entry with mac & vid */ 720 data = fdb->vid << ALU_FID_INDEX_S; 721 data |= ((fdb->addr[0] << 8) | fdb->addr[1]); 722 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 723 724 data = ((fdb->addr[2] << 24) | (fdb->addr[3] << 16)); 725 data |= ((fdb->addr[4] << 8) | fdb->addr[5]); 726 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 727 728 /* start read operation */ 729 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 730 731 /* wait to be finished */ 732 if (wait_alu_ready(dev, ALU_START, 1000) < 0) { 733 dev_dbg(dev->dev, "Failed to read ALU\n"); 734 goto exit; 735 } 736 737 /* read ALU entry */ 738 read_table(ds, alu_table); 739 740 /* update ALU entry */ 741 alu_table[0] = ALU_V_STATIC_VALID; 742 alu_table[1] |= BIT(port); 743 if (fdb->vid) 744 alu_table[1] |= ALU_V_USE_FID; 745 alu_table[2] = (fdb->vid << ALU_V_FID_S); 746 alu_table[2] |= ((fdb->addr[0] << 8) | fdb->addr[1]); 747 alu_table[3] = ((fdb->addr[2] << 24) | (fdb->addr[3] << 16)); 748 alu_table[3] |= ((fdb->addr[4] << 8) | fdb->addr[5]); 749 750 write_table(ds, alu_table); 751 752 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 753 754 /* wait to be finished */ 755 if (wait_alu_ready(dev, ALU_START, 1000) < 0) 756 dev_dbg(dev->dev, "Failed to read ALU\n"); 757 758 exit: 759 mutex_unlock(&dev->alu_mutex); 760 } 761 762 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 763 const struct switchdev_obj_port_fdb *fdb) 764 { 765 struct ksz_device *dev = ds->priv; 766 u32 alu_table[4]; 767 u32 data; 768 int ret = 0; 769 770 mutex_lock(&dev->alu_mutex); 771 772 /* read any entry with mac & vid */ 773 data = fdb->vid << ALU_FID_INDEX_S; 774 data |= ((fdb->addr[0] << 8) | fdb->addr[1]); 775 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 776 777 data = ((fdb->addr[2] << 24) | (fdb->addr[3] << 16)); 778 data |= ((fdb->addr[4] << 8) | fdb->addr[5]); 779 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 780 781 /* start read operation */ 782 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 783 784 /* wait to be finished */ 785 ret = wait_alu_ready(dev, ALU_START, 1000); 786 if (ret < 0) { 787 dev_dbg(dev->dev, "Failed to read ALU\n"); 788 goto exit; 789 } 790 791 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 792 if (alu_table[0] & ALU_V_STATIC_VALID) { 793 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 794 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 795 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 796 797 /* clear forwarding port */ 798 alu_table[2] &= ~BIT(port); 799 800 /* if there is no port to forward, clear table */ 801 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) { 802 alu_table[0] = 0; 803 alu_table[1] = 0; 804 alu_table[2] = 0; 805 alu_table[3] = 0; 806 } 807 } else { 808 alu_table[0] = 0; 809 alu_table[1] = 0; 810 alu_table[2] = 0; 811 alu_table[3] = 0; 812 } 813 814 write_table(ds, alu_table); 815 816 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 817 818 /* wait to be finished */ 819 ret = wait_alu_ready(dev, ALU_START, 1000); 820 if (ret < 0) 821 dev_dbg(dev->dev, "Failed to write ALU\n"); 822 823 exit: 824 mutex_unlock(&dev->alu_mutex); 825 826 return ret; 827 } 828 829 static void convert_alu(struct alu_struct *alu, u32 *alu_table) 830 { 831 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 832 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 833 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 834 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 835 ALU_V_PRIO_AGE_CNT_M; 836 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 837 838 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 839 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 840 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 841 842 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 843 844 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 845 alu->mac[1] = alu_table[2] & 0xFF; 846 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 847 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 848 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 849 alu->mac[5] = alu_table[3] & 0xFF; 850 } 851 852 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 853 struct switchdev_obj_port_fdb *fdb, 854 switchdev_obj_dump_cb_t *cb) 855 { 856 struct ksz_device *dev = ds->priv; 857 int ret = 0; 858 u32 data; 859 u32 alu_table[4]; 860 struct alu_struct alu; 861 int timeout; 862 863 mutex_lock(&dev->alu_mutex); 864 865 /* start ALU search */ 866 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 867 868 do { 869 timeout = 1000; 870 do { 871 ksz_read32(dev, REG_SW_ALU_CTRL__4, &data); 872 if ((data & ALU_VALID) || !(data & ALU_START)) 873 break; 874 usleep_range(1, 10); 875 } while (timeout-- > 0); 876 877 if (!timeout) { 878 dev_dbg(dev->dev, "Failed to search ALU\n"); 879 ret = -ETIMEDOUT; 880 goto exit; 881 } 882 883 /* read ALU table */ 884 read_table(ds, alu_table); 885 886 convert_alu(&alu, alu_table); 887 888 if (alu.port_forward & BIT(port)) { 889 fdb->vid = alu.fid; 890 if (alu.is_static) 891 fdb->ndm_state = NUD_NOARP; 892 else 893 fdb->ndm_state = NUD_REACHABLE; 894 ether_addr_copy(fdb->addr, alu.mac); 895 896 ret = cb(&fdb->obj); 897 if (ret) 898 goto exit; 899 } 900 } while (data & ALU_START); 901 902 exit: 903 904 /* stop ALU search */ 905 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 906 907 mutex_unlock(&dev->alu_mutex); 908 909 return ret; 910 } 911 912 static int ksz_port_mdb_prepare(struct dsa_switch *ds, int port, 913 const struct switchdev_obj_port_mdb *mdb, 914 struct switchdev_trans *trans) 915 { 916 /* nothing to do */ 917 return 0; 918 } 919 920 static void ksz_port_mdb_add(struct dsa_switch *ds, int port, 921 const struct switchdev_obj_port_mdb *mdb, 922 struct switchdev_trans *trans) 923 { 924 struct ksz_device *dev = ds->priv; 925 u32 static_table[4]; 926 u32 data; 927 int index; 928 u32 mac_hi, mac_lo; 929 930 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 931 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 932 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 933 934 mutex_lock(&dev->alu_mutex); 935 936 for (index = 0; index < dev->num_statics; index++) { 937 /* find empty slot first */ 938 data = (index << ALU_STAT_INDEX_S) | 939 ALU_STAT_READ | ALU_STAT_START; 940 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 941 942 /* wait to be finished */ 943 if (wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0) { 944 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 945 goto exit; 946 } 947 948 /* read ALU static table */ 949 read_table(ds, static_table); 950 951 if (static_table[0] & ALU_V_STATIC_VALID) { 952 /* check this has same vid & mac address */ 953 if (((static_table[2] >> ALU_V_FID_S) == (mdb->vid)) && 954 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 955 (static_table[3] == mac_lo)) { 956 /* found matching one */ 957 break; 958 } 959 } else { 960 /* found empty one */ 961 break; 962 } 963 } 964 965 /* no available entry */ 966 if (index == dev->num_statics) 967 goto exit; 968 969 /* add entry */ 970 static_table[0] = ALU_V_STATIC_VALID; 971 static_table[1] |= BIT(port); 972 if (mdb->vid) 973 static_table[1] |= ALU_V_USE_FID; 974 static_table[2] = (mdb->vid << ALU_V_FID_S); 975 static_table[2] |= mac_hi; 976 static_table[3] = mac_lo; 977 978 write_table(ds, static_table); 979 980 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 981 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 982 983 /* wait to be finished */ 984 if (wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0) 985 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 986 987 exit: 988 mutex_unlock(&dev->alu_mutex); 989 } 990 991 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 992 const struct switchdev_obj_port_mdb *mdb) 993 { 994 struct ksz_device *dev = ds->priv; 995 u32 static_table[4]; 996 u32 data; 997 int index; 998 int ret = 0; 999 u32 mac_hi, mac_lo; 1000 1001 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 1002 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 1003 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 1004 1005 mutex_lock(&dev->alu_mutex); 1006 1007 for (index = 0; index < dev->num_statics; index++) { 1008 /* find empty slot first */ 1009 data = (index << ALU_STAT_INDEX_S) | 1010 ALU_STAT_READ | ALU_STAT_START; 1011 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1012 1013 /* wait to be finished */ 1014 ret = wait_alu_sta_ready(dev, ALU_STAT_START, 1000); 1015 if (ret < 0) { 1016 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 1017 goto exit; 1018 } 1019 1020 /* read ALU static table */ 1021 read_table(ds, static_table); 1022 1023 if (static_table[0] & ALU_V_STATIC_VALID) { 1024 /* check this has same vid & mac address */ 1025 1026 if (((static_table[2] >> ALU_V_FID_S) == (mdb->vid)) && 1027 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 1028 (static_table[3] == mac_lo)) { 1029 /* found matching one */ 1030 break; 1031 } 1032 } 1033 } 1034 1035 /* no available entry */ 1036 if (index == dev->num_statics) { 1037 ret = -EINVAL; 1038 goto exit; 1039 } 1040 1041 /* clear port */ 1042 static_table[1] &= ~BIT(port); 1043 1044 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 1045 /* delete entry */ 1046 static_table[0] = 0; 1047 static_table[1] = 0; 1048 static_table[2] = 0; 1049 static_table[3] = 0; 1050 } 1051 1052 write_table(ds, static_table); 1053 1054 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 1055 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1056 1057 /* wait to be finished */ 1058 ret = wait_alu_sta_ready(dev, ALU_STAT_START, 1000); 1059 if (ret < 0) 1060 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 1061 1062 exit: 1063 mutex_unlock(&dev->alu_mutex); 1064 1065 return ret; 1066 } 1067 1068 static int ksz_port_mdb_dump(struct dsa_switch *ds, int port, 1069 struct switchdev_obj_port_mdb *mdb, 1070 switchdev_obj_dump_cb_t *cb) 1071 { 1072 /* this is not called by switch layer */ 1073 return 0; 1074 } 1075 1076 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 1077 struct dsa_mall_mirror_tc_entry *mirror, 1078 bool ingress) 1079 { 1080 struct ksz_device *dev = ds->priv; 1081 1082 if (ingress) 1083 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 1084 else 1085 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 1086 1087 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); 1088 1089 /* configure mirror port */ 1090 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1091 PORT_MIRROR_SNIFFER, true); 1092 1093 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 1094 1095 return 0; 1096 } 1097 1098 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 1099 struct dsa_mall_mirror_tc_entry *mirror) 1100 { 1101 struct ksz_device *dev = ds->priv; 1102 u8 data; 1103 1104 if (mirror->ingress) 1105 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 1106 else 1107 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 1108 1109 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 1110 1111 if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) 1112 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1113 PORT_MIRROR_SNIFFER, false); 1114 } 1115 1116 static const struct dsa_switch_ops ksz_switch_ops = { 1117 .get_tag_protocol = ksz_get_tag_protocol, 1118 .setup = ksz_setup, 1119 .phy_read = ksz_phy_read16, 1120 .phy_write = ksz_phy_write16, 1121 .port_enable = ksz_enable_port, 1122 .port_disable = ksz_disable_port, 1123 .get_strings = ksz_get_strings, 1124 .get_ethtool_stats = ksz_get_ethtool_stats, 1125 .get_sset_count = ksz_sset_count, 1126 .port_stp_state_set = ksz_port_stp_state_set, 1127 .port_fast_age = ksz_port_fast_age, 1128 .port_vlan_filtering = ksz_port_vlan_filtering, 1129 .port_vlan_prepare = ksz_port_vlan_prepare, 1130 .port_vlan_add = ksz_port_vlan_add, 1131 .port_vlan_del = ksz_port_vlan_del, 1132 .port_vlan_dump = ksz_port_vlan_dump, 1133 .port_fdb_prepare = ksz_port_fdb_prepare, 1134 .port_fdb_dump = ksz_port_fdb_dump, 1135 .port_fdb_add = ksz_port_fdb_add, 1136 .port_fdb_del = ksz_port_fdb_del, 1137 .port_mdb_prepare = ksz_port_mdb_prepare, 1138 .port_mdb_add = ksz_port_mdb_add, 1139 .port_mdb_del = ksz_port_mdb_del, 1140 .port_mdb_dump = ksz_port_mdb_dump, 1141 .port_mirror_add = ksz_port_mirror_add, 1142 .port_mirror_del = ksz_port_mirror_del, 1143 }; 1144 1145 struct ksz_chip_data { 1146 u32 chip_id; 1147 const char *dev_name; 1148 int num_vlans; 1149 int num_alus; 1150 int num_statics; 1151 int cpu_ports; 1152 int port_cnt; 1153 }; 1154 1155 static const struct ksz_chip_data ksz_switch_chips[] = { 1156 { 1157 .chip_id = 0x00947700, 1158 .dev_name = "KSZ9477", 1159 .num_vlans = 4096, 1160 .num_alus = 4096, 1161 .num_statics = 16, 1162 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1163 .port_cnt = 7, /* total physical port count */ 1164 }, 1165 }; 1166 1167 static int ksz_switch_init(struct ksz_device *dev) 1168 { 1169 int i; 1170 1171 mutex_init(&dev->reg_mutex); 1172 mutex_init(&dev->stats_mutex); 1173 mutex_init(&dev->alu_mutex); 1174 mutex_init(&dev->vlan_mutex); 1175 1176 dev->ds->ops = &ksz_switch_ops; 1177 1178 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1179 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1180 1181 if (dev->chip_id == chip->chip_id) { 1182 dev->name = chip->dev_name; 1183 dev->num_vlans = chip->num_vlans; 1184 dev->num_alus = chip->num_alus; 1185 dev->num_statics = chip->num_statics; 1186 dev->port_cnt = chip->port_cnt; 1187 dev->cpu_ports = chip->cpu_ports; 1188 1189 break; 1190 } 1191 } 1192 1193 /* no switch found */ 1194 if (!dev->port_cnt) 1195 return -ENODEV; 1196 1197 return 0; 1198 } 1199 1200 struct ksz_device *ksz_switch_alloc(struct device *base, 1201 const struct ksz_io_ops *ops, 1202 void *priv) 1203 { 1204 struct dsa_switch *ds; 1205 struct ksz_device *swdev; 1206 1207 ds = dsa_switch_alloc(base, DSA_MAX_PORTS); 1208 if (!ds) 1209 return NULL; 1210 1211 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 1212 if (!swdev) 1213 return NULL; 1214 1215 ds->priv = swdev; 1216 swdev->dev = base; 1217 1218 swdev->ds = ds; 1219 swdev->priv = priv; 1220 swdev->ops = ops; 1221 1222 return swdev; 1223 } 1224 EXPORT_SYMBOL(ksz_switch_alloc); 1225 1226 int ksz_switch_detect(struct ksz_device *dev) 1227 { 1228 u8 data8; 1229 u32 id32; 1230 int ret; 1231 1232 /* turn off SPI DO Edge select */ 1233 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1234 if (ret) 1235 return ret; 1236 1237 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1238 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1239 if (ret) 1240 return ret; 1241 1242 /* read chip id */ 1243 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32); 1244 if (ret) 1245 return ret; 1246 1247 dev->chip_id = id32; 1248 1249 return 0; 1250 } 1251 EXPORT_SYMBOL(ksz_switch_detect); 1252 1253 int ksz_switch_register(struct ksz_device *dev) 1254 { 1255 int ret; 1256 1257 if (dev->pdata) 1258 dev->chip_id = dev->pdata->chip_id; 1259 1260 if (ksz_switch_detect(dev)) 1261 return -EINVAL; 1262 1263 ret = ksz_switch_init(dev); 1264 if (ret) 1265 return ret; 1266 1267 return dsa_register_switch(dev->ds); 1268 } 1269 EXPORT_SYMBOL(ksz_switch_register); 1270 1271 void ksz_switch_remove(struct ksz_device *dev) 1272 { 1273 dsa_unregister_switch(dev->ds); 1274 } 1275 EXPORT_SYMBOL(ksz_switch_remove); 1276 1277 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1278 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 1279 MODULE_LICENSE("GPL"); 1280