1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2025 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/of.h> 22 #include <linux/of_mdio.h> 23 #include <linux/of_net.h> 24 #include <linux/micrel_phy.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <net/dsa.h> 27 #include <net/ieee8021q.h> 28 #include <net/pkt_cls.h> 29 #include <net/switchdev.h> 30 31 #include "ksz_common.h" 32 #include "ksz_dcb.h" 33 #include "ksz_ptp.h" 34 #include "ksz8.h" 35 #include "ksz9477.h" 36 #include "lan937x.h" 37 38 #define MIB_COUNTER_NUM 0x20 39 40 static const struct ksz_mib_names ksz88xx_mib_names[] = { 41 { 0x00, "rx" }, 42 { 0x01, "rx_hi" }, 43 { 0x02, "rx_undersize" }, 44 { 0x03, "rx_fragments" }, 45 { 0x04, "rx_oversize" }, 46 { 0x05, "rx_jabbers" }, 47 { 0x06, "rx_symbol_err" }, 48 { 0x07, "rx_crc_err" }, 49 { 0x08, "rx_align_err" }, 50 { 0x09, "rx_mac_ctrl" }, 51 { 0x0a, "rx_pause" }, 52 { 0x0b, "rx_bcast" }, 53 { 0x0c, "rx_mcast" }, 54 { 0x0d, "rx_ucast" }, 55 { 0x0e, "rx_64_or_less" }, 56 { 0x0f, "rx_65_127" }, 57 { 0x10, "rx_128_255" }, 58 { 0x11, "rx_256_511" }, 59 { 0x12, "rx_512_1023" }, 60 { 0x13, "rx_1024_1522" }, 61 { 0x14, "tx" }, 62 { 0x15, "tx_hi" }, 63 { 0x16, "tx_late_col" }, 64 { 0x17, "tx_pause" }, 65 { 0x18, "tx_bcast" }, 66 { 0x19, "tx_mcast" }, 67 { 0x1a, "tx_ucast" }, 68 { 0x1b, "tx_deferred" }, 69 { 0x1c, "tx_total_col" }, 70 { 0x1d, "tx_exc_col" }, 71 { 0x1e, "tx_single_col" }, 72 { 0x1f, "tx_mult_col" }, 73 { 0x100, "rx_discards" }, 74 { 0x101, "tx_discards" }, 75 }; 76 77 static const struct ksz_mib_names ksz9477_mib_names[] = { 78 { 0x00, "rx_hi" }, 79 { 0x01, "rx_undersize" }, 80 { 0x02, "rx_fragments" }, 81 { 0x03, "rx_oversize" }, 82 { 0x04, "rx_jabbers" }, 83 { 0x05, "rx_symbol_err" }, 84 { 0x06, "rx_crc_err" }, 85 { 0x07, "rx_align_err" }, 86 { 0x08, "rx_mac_ctrl" }, 87 { 0x09, "rx_pause" }, 88 { 0x0A, "rx_bcast" }, 89 { 0x0B, "rx_mcast" }, 90 { 0x0C, "rx_ucast" }, 91 { 0x0D, "rx_64_or_less" }, 92 { 0x0E, "rx_65_127" }, 93 { 0x0F, "rx_128_255" }, 94 { 0x10, "rx_256_511" }, 95 { 0x11, "rx_512_1023" }, 96 { 0x12, "rx_1024_1522" }, 97 { 0x13, "rx_1523_2000" }, 98 { 0x14, "rx_2001" }, 99 { 0x15, "tx_hi" }, 100 { 0x16, "tx_late_col" }, 101 { 0x17, "tx_pause" }, 102 { 0x18, "tx_bcast" }, 103 { 0x19, "tx_mcast" }, 104 { 0x1A, "tx_ucast" }, 105 { 0x1B, "tx_deferred" }, 106 { 0x1C, "tx_total_col" }, 107 { 0x1D, "tx_exc_col" }, 108 { 0x1E, "tx_single_col" }, 109 { 0x1F, "tx_mult_col" }, 110 { 0x80, "rx_total" }, 111 { 0x81, "tx_total" }, 112 { 0x82, "rx_discards" }, 113 { 0x83, "tx_discards" }, 114 }; 115 116 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants 117 * 118 * This values are not documented in KSZ9477 variants but confirmed by 119 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893 120 * and KSZ8563 are using same register (drive strength) settings like KSZ8795. 121 * 122 * Documentation in KSZ8795CLX provides more information with some 123 * recommendations: 124 * - for high speed signals 125 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using 126 * 2.5V or 3.3V VDDIO. 127 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with 128 * using 1.8V VDDIO. 129 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V 130 * or 3.3V VDDIO. 131 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO. 132 * 5. In same interface, the heavy loading should use higher one of the 133 * drive current strength. 134 * - for low speed signals 135 * 1. 3.3V VDDIO, use either 4 mA or 8 mA. 136 * 2. 2.5V VDDIO, use either 8 mA or 12 mA. 137 * 3. 1.8V VDDIO, use either 12 mA or 16 mA. 138 * 4. If it is heavy loading, can use higher drive current strength. 139 */ 140 static const struct ksz_drive_strength ksz9477_drive_strengths[] = { 141 { SW_DRIVE_STRENGTH_2MA, 2000 }, 142 { SW_DRIVE_STRENGTH_4MA, 4000 }, 143 { SW_DRIVE_STRENGTH_8MA, 8000 }, 144 { SW_DRIVE_STRENGTH_12MA, 12000 }, 145 { SW_DRIVE_STRENGTH_16MA, 16000 }, 146 { SW_DRIVE_STRENGTH_20MA, 20000 }, 147 { SW_DRIVE_STRENGTH_24MA, 24000 }, 148 { SW_DRIVE_STRENGTH_28MA, 28000 }, 149 }; 150 151 /** 152 * ksz_phylink_mac_disable_tx_lpi() - Callback to signal LPI support (Dummy) 153 * @config: phylink config structure 154 * 155 * This function is a dummy handler. See ksz_phylink_mac_enable_tx_lpi() for 156 * a detailed explanation of EEE/LPI handling in KSZ switches. 157 */ 158 void ksz_phylink_mac_disable_tx_lpi(struct phylink_config *config) 159 { 160 } 161 162 /** 163 * ksz_phylink_mac_enable_tx_lpi() - Callback to signal LPI support (Dummy) 164 * @config: phylink config structure 165 * @timer: timer value before entering LPI (unused) 166 * @tx_clock_stop: whether to stop the TX clock in LPI mode (unused) 167 * 168 * This function signals to phylink that the driver architecture supports 169 * LPI management, enabling phylink to control EEE advertisement during 170 * negotiation according to IEEE Std 802.3 (Clause 78). 171 * 172 * Hardware Management of EEE/LPI State: 173 * For KSZ switch ports with integrated PHYs (e.g., KSZ9893R ports 1-2), 174 * observation and testing suggest that the actual EEE / Low Power Idle (LPI) 175 * state transitions are managed autonomously by the hardware based on 176 * the auto-negotiation results. (Note: While the datasheet describes EEE 177 * operation based on negotiation, it doesn't explicitly detail the internal 178 * MAC/PHY interaction, so autonomous hardware management of the MAC state 179 * for LPI is inferred from observed behavior). 180 * This hardware control, consistent with the switch's ability to operate 181 * autonomously via strapping, means MAC-level software intervention is not 182 * required or exposed for managing the LPI state once EEE is negotiated. 183 * (Ref: KSZ9893R Data Sheet DS00002420D, primarily Section 4.7.5 explaining 184 * EEE, also Sections 4.1.7 on Auto-Negotiation and 3.2.1 on Configuration 185 * Straps). 186 * 187 * Additionally, ports configured as MAC interfaces (e.g., KSZ9893R port 3) 188 * lack documented MAC-level LPI control. 189 * 190 * Therefore, this callback performs no action and serves primarily to inform 191 * phylink of LPI awareness and to document the inferred hardware behavior. 192 * 193 * Returns: 0 (Always success) 194 */ 195 int ksz_phylink_mac_enable_tx_lpi(struct phylink_config *config, 196 u32 timer, bool tx_clock_stop) 197 { 198 return 0; 199 } 200 201 static const u16 ksz8463_regs[] = { 202 [REG_SW_MAC_ADDR] = 0x10, 203 [REG_IND_CTRL_0] = 0x30, 204 [REG_IND_DATA_8] = 0x26, 205 [REG_IND_DATA_CHECK] = 0x26, 206 [REG_IND_DATA_HI] = 0x28, 207 [REG_IND_DATA_LO] = 0x2C, 208 [REG_IND_MIB_CHECK] = 0x2F, 209 [P_FORCE_CTRL] = 0x0C, 210 [P_LINK_STATUS] = 0x0E, 211 [P_LOCAL_CTRL] = 0x0C, 212 [P_NEG_RESTART_CTRL] = 0x0D, 213 [P_REMOTE_STATUS] = 0x0E, 214 [P_SPEED_STATUS] = 0x0F, 215 [S_TAIL_TAG_CTRL] = 0xAD, 216 [P_STP_CTRL] = 0x6F, 217 [S_START_CTRL] = 0x01, 218 [S_BROADCAST_CTRL] = 0x06, 219 [S_MULTICAST_CTRL] = 0x04, 220 [PTP_CLK_CTRL] = 0x0600, 221 [PTP_RTC_NANOSEC] = 0x0604, 222 [PTP_RTC_SEC] = 0x0608, 223 [PTP_RTC_SUB_NANOSEC] = 0x060C, 224 [PTP_SUBNANOSEC_RATE] = 0x0610, 225 [PTP_MSG_CONF1] = 0x0620, 226 }; 227 228 static const u32 ksz8463_masks[] = { 229 [PORT_802_1P_REMAPPING] = BIT(3), 230 [SW_TAIL_TAG_ENABLE] = BIT(0), 231 [MIB_COUNTER_OVERFLOW] = BIT(7), 232 [MIB_COUNTER_VALID] = BIT(6), 233 [VLAN_TABLE_FID] = GENMASK(15, 12), 234 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 235 [VLAN_TABLE_VALID] = BIT(19), 236 [STATIC_MAC_TABLE_VALID] = BIT(19), 237 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 238 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 239 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 240 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 241 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 242 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 243 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 244 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 245 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 246 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 247 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 248 }; 249 250 static u8 ksz8463_shifts[] = { 251 [VLAN_TABLE_MEMBERSHIP_S] = 16, 252 [STATIC_MAC_FWD_PORTS] = 16, 253 [STATIC_MAC_FID] = 22, 254 [DYNAMIC_MAC_ENTRIES_H] = 8, 255 [DYNAMIC_MAC_ENTRIES] = 24, 256 [DYNAMIC_MAC_FID] = 16, 257 [DYNAMIC_MAC_TIMESTAMP] = 22, 258 [DYNAMIC_MAC_SRC_PORT] = 20, 259 }; 260 261 static const u16 ksz8795_regs[] = { 262 [REG_SW_MAC_ADDR] = 0x68, 263 [REG_IND_CTRL_0] = 0x6E, 264 [REG_IND_DATA_8] = 0x70, 265 [REG_IND_DATA_CHECK] = 0x72, 266 [REG_IND_DATA_HI] = 0x71, 267 [REG_IND_DATA_LO] = 0x75, 268 [REG_IND_MIB_CHECK] = 0x74, 269 [REG_IND_BYTE] = 0xA0, 270 [P_FORCE_CTRL] = 0x0C, 271 [P_LINK_STATUS] = 0x0E, 272 [P_LOCAL_CTRL] = 0x07, 273 [P_NEG_RESTART_CTRL] = 0x0D, 274 [P_REMOTE_STATUS] = 0x08, 275 [P_SPEED_STATUS] = 0x09, 276 [S_TAIL_TAG_CTRL] = 0x0C, 277 [P_STP_CTRL] = 0x02, 278 [S_START_CTRL] = 0x01, 279 [S_BROADCAST_CTRL] = 0x06, 280 [S_MULTICAST_CTRL] = 0x04, 281 [P_XMII_CTRL_0] = 0x06, 282 [P_XMII_CTRL_1] = 0x06, 283 [REG_SW_PME_CTRL] = 0x8003, 284 [REG_PORT_PME_STATUS] = 0x8003, 285 [REG_PORT_PME_CTRL] = 0x8007, 286 }; 287 288 static const u32 ksz8795_masks[] = { 289 [PORT_802_1P_REMAPPING] = BIT(7), 290 [SW_TAIL_TAG_ENABLE] = BIT(1), 291 [MIB_COUNTER_OVERFLOW] = BIT(6), 292 [MIB_COUNTER_VALID] = BIT(5), 293 [VLAN_TABLE_FID] = GENMASK(6, 0), 294 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 295 [VLAN_TABLE_VALID] = BIT(12), 296 [STATIC_MAC_TABLE_VALID] = BIT(21), 297 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 298 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 299 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 300 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 301 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 302 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 303 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 304 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 305 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 306 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 307 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 308 [P_MII_TX_FLOW_CTRL] = BIT(5), 309 [P_MII_RX_FLOW_CTRL] = BIT(5), 310 }; 311 312 static const u8 ksz8795_xmii_ctrl0[] = { 313 [P_MII_100MBIT] = 0, 314 [P_MII_10MBIT] = 1, 315 [P_MII_FULL_DUPLEX] = 0, 316 [P_MII_HALF_DUPLEX] = 1, 317 }; 318 319 static const u8 ksz8795_xmii_ctrl1[] = { 320 [P_RGMII_SEL] = 3, 321 [P_GMII_SEL] = 2, 322 [P_RMII_SEL] = 1, 323 [P_MII_SEL] = 0, 324 [P_GMII_1GBIT] = 1, 325 [P_GMII_NOT_1GBIT] = 0, 326 }; 327 328 static const u8 ksz8795_shifts[] = { 329 [VLAN_TABLE_MEMBERSHIP_S] = 7, 330 [VLAN_TABLE] = 16, 331 [STATIC_MAC_FWD_PORTS] = 16, 332 [STATIC_MAC_FID] = 24, 333 [DYNAMIC_MAC_ENTRIES_H] = 3, 334 [DYNAMIC_MAC_ENTRIES] = 29, 335 [DYNAMIC_MAC_FID] = 16, 336 [DYNAMIC_MAC_TIMESTAMP] = 27, 337 [DYNAMIC_MAC_SRC_PORT] = 24, 338 }; 339 340 static const u16 ksz8863_regs[] = { 341 [REG_SW_MAC_ADDR] = 0x70, 342 [REG_IND_CTRL_0] = 0x79, 343 [REG_IND_DATA_8] = 0x7B, 344 [REG_IND_DATA_CHECK] = 0x7B, 345 [REG_IND_DATA_HI] = 0x7C, 346 [REG_IND_DATA_LO] = 0x80, 347 [REG_IND_MIB_CHECK] = 0x80, 348 [P_FORCE_CTRL] = 0x0C, 349 [P_LINK_STATUS] = 0x0E, 350 [P_LOCAL_CTRL] = 0x0C, 351 [P_NEG_RESTART_CTRL] = 0x0D, 352 [P_REMOTE_STATUS] = 0x0E, 353 [P_SPEED_STATUS] = 0x0F, 354 [S_TAIL_TAG_CTRL] = 0x03, 355 [P_STP_CTRL] = 0x02, 356 [S_START_CTRL] = 0x01, 357 [S_BROADCAST_CTRL] = 0x06, 358 [S_MULTICAST_CTRL] = 0x04, 359 }; 360 361 static const u32 ksz8863_masks[] = { 362 [PORT_802_1P_REMAPPING] = BIT(3), 363 [SW_TAIL_TAG_ENABLE] = BIT(6), 364 [MIB_COUNTER_OVERFLOW] = BIT(7), 365 [MIB_COUNTER_VALID] = BIT(6), 366 [VLAN_TABLE_FID] = GENMASK(15, 12), 367 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 368 [VLAN_TABLE_VALID] = BIT(19), 369 [STATIC_MAC_TABLE_VALID] = BIT(19), 370 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 371 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 372 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 373 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 374 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 375 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 376 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 377 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 378 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 379 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 380 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 381 }; 382 383 static u8 ksz8863_shifts[] = { 384 [VLAN_TABLE_MEMBERSHIP_S] = 16, 385 [STATIC_MAC_FWD_PORTS] = 16, 386 [STATIC_MAC_FID] = 22, 387 [DYNAMIC_MAC_ENTRIES_H] = 8, 388 [DYNAMIC_MAC_ENTRIES] = 24, 389 [DYNAMIC_MAC_FID] = 16, 390 [DYNAMIC_MAC_TIMESTAMP] = 22, 391 [DYNAMIC_MAC_SRC_PORT] = 20, 392 }; 393 394 static const u16 ksz8895_regs[] = { 395 [REG_SW_MAC_ADDR] = 0x68, 396 [REG_IND_CTRL_0] = 0x6E, 397 [REG_IND_DATA_8] = 0x70, 398 [REG_IND_DATA_CHECK] = 0x72, 399 [REG_IND_DATA_HI] = 0x71, 400 [REG_IND_DATA_LO] = 0x75, 401 [REG_IND_MIB_CHECK] = 0x75, 402 [P_FORCE_CTRL] = 0x0C, 403 [P_LINK_STATUS] = 0x0E, 404 [P_LOCAL_CTRL] = 0x0C, 405 [P_NEG_RESTART_CTRL] = 0x0D, 406 [P_REMOTE_STATUS] = 0x0E, 407 [P_SPEED_STATUS] = 0x09, 408 [S_TAIL_TAG_CTRL] = 0x0C, 409 [P_STP_CTRL] = 0x02, 410 [S_START_CTRL] = 0x01, 411 [S_BROADCAST_CTRL] = 0x06, 412 [S_MULTICAST_CTRL] = 0x04, 413 }; 414 415 static const u32 ksz8895_masks[] = { 416 [PORT_802_1P_REMAPPING] = BIT(7), 417 [SW_TAIL_TAG_ENABLE] = BIT(1), 418 [MIB_COUNTER_OVERFLOW] = BIT(7), 419 [MIB_COUNTER_VALID] = BIT(6), 420 [VLAN_TABLE_FID] = GENMASK(6, 0), 421 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 422 [VLAN_TABLE_VALID] = BIT(12), 423 [STATIC_MAC_TABLE_VALID] = BIT(21), 424 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 425 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 426 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 427 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 428 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 429 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 430 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 431 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 432 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 433 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 434 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 435 }; 436 437 static const u8 ksz8895_shifts[] = { 438 [VLAN_TABLE_MEMBERSHIP_S] = 7, 439 [VLAN_TABLE] = 13, 440 [STATIC_MAC_FWD_PORTS] = 16, 441 [STATIC_MAC_FID] = 24, 442 [DYNAMIC_MAC_ENTRIES_H] = 3, 443 [DYNAMIC_MAC_ENTRIES] = 29, 444 [DYNAMIC_MAC_FID] = 16, 445 [DYNAMIC_MAC_TIMESTAMP] = 27, 446 [DYNAMIC_MAC_SRC_PORT] = 24, 447 }; 448 449 static const u16 ksz8995xa_regs[] = { 450 [REG_SW_MAC_ADDR] = 0x68, 451 [P_FORCE_CTRL] = 0x0C, 452 [P_LINK_STATUS] = 0x0E, 453 [P_LOCAL_CTRL] = 0x0C, 454 [P_NEG_RESTART_CTRL] = 0x0D, 455 [P_REMOTE_STATUS] = 0x0E, 456 [P_SPEED_STATUS] = 0x09, 457 [P_STP_CTRL] = 0x02, 458 [S_START_CTRL] = 0x01, 459 [S_BROADCAST_CTRL] = 0x06, 460 [S_MULTICAST_CTRL] = 0x04, 461 }; 462 463 static const u16 ksz9477_regs[] = { 464 [REG_SW_MAC_ADDR] = 0x0302, 465 [P_STP_CTRL] = 0x0B04, 466 [S_START_CTRL] = 0x0300, 467 [S_BROADCAST_CTRL] = 0x0332, 468 [S_MULTICAST_CTRL] = 0x0331, 469 [P_XMII_CTRL_0] = 0x0300, 470 [P_XMII_CTRL_1] = 0x0301, 471 [REG_SW_PME_CTRL] = 0x0006, 472 [REG_PORT_PME_STATUS] = 0x0013, 473 [REG_PORT_PME_CTRL] = 0x0017, 474 [PTP_CLK_CTRL] = 0x0500, 475 [PTP_RTC_SUB_NANOSEC] = 0x0502, 476 [PTP_RTC_NANOSEC] = 0x0504, 477 [PTP_RTC_SEC] = 0x0508, 478 [PTP_SUBNANOSEC_RATE] = 0x050C, 479 [PTP_MSG_CONF1] = 0x0514, 480 }; 481 482 static const u32 ksz9477_masks[] = { 483 [ALU_STAT_WRITE] = 0, 484 [ALU_STAT_READ] = 1, 485 [ALU_STAT_DIRECT] = 0, 486 [ALU_RESV_MCAST_ADDR] = BIT(1), 487 [P_MII_TX_FLOW_CTRL] = BIT(5), 488 [P_MII_RX_FLOW_CTRL] = BIT(3), 489 }; 490 491 static const u8 ksz9477_shifts[] = { 492 [ALU_STAT_INDEX] = 16, 493 }; 494 495 static const u8 ksz9477_xmii_ctrl0[] = { 496 [P_MII_100MBIT] = 1, 497 [P_MII_10MBIT] = 0, 498 [P_MII_FULL_DUPLEX] = 1, 499 [P_MII_HALF_DUPLEX] = 0, 500 }; 501 502 static const u8 ksz9477_xmii_ctrl1[] = { 503 [P_RGMII_SEL] = 0, 504 [P_RMII_SEL] = 1, 505 [P_GMII_SEL] = 2, 506 [P_MII_SEL] = 3, 507 [P_GMII_1GBIT] = 0, 508 [P_GMII_NOT_1GBIT] = 1, 509 }; 510 511 static const u32 lan937x_masks[] = { 512 [ALU_STAT_WRITE] = 1, 513 [ALU_STAT_READ] = 2, 514 [ALU_STAT_DIRECT] = BIT(3), 515 [ALU_RESV_MCAST_ADDR] = BIT(2), 516 [P_MII_TX_FLOW_CTRL] = BIT(5), 517 [P_MII_RX_FLOW_CTRL] = BIT(3), 518 }; 519 520 static const u8 lan937x_shifts[] = { 521 [ALU_STAT_INDEX] = 8, 522 }; 523 524 static const struct regmap_range ksz8563_valid_regs[] = { 525 regmap_reg_range(0x0000, 0x0003), 526 regmap_reg_range(0x0006, 0x0006), 527 regmap_reg_range(0x000f, 0x001f), 528 regmap_reg_range(0x0100, 0x0100), 529 regmap_reg_range(0x0104, 0x0107), 530 regmap_reg_range(0x010d, 0x010d), 531 regmap_reg_range(0x0110, 0x0113), 532 regmap_reg_range(0x0120, 0x012b), 533 regmap_reg_range(0x0201, 0x0201), 534 regmap_reg_range(0x0210, 0x0213), 535 regmap_reg_range(0x0300, 0x0300), 536 regmap_reg_range(0x0302, 0x031b), 537 regmap_reg_range(0x0320, 0x032b), 538 regmap_reg_range(0x0330, 0x0336), 539 regmap_reg_range(0x0338, 0x033e), 540 regmap_reg_range(0x0340, 0x035f), 541 regmap_reg_range(0x0370, 0x0370), 542 regmap_reg_range(0x0378, 0x0378), 543 regmap_reg_range(0x037c, 0x037d), 544 regmap_reg_range(0x0390, 0x0393), 545 regmap_reg_range(0x0400, 0x040e), 546 regmap_reg_range(0x0410, 0x042f), 547 regmap_reg_range(0x0500, 0x0519), 548 regmap_reg_range(0x0520, 0x054b), 549 regmap_reg_range(0x0550, 0x05b3), 550 551 /* port 1 */ 552 regmap_reg_range(0x1000, 0x1001), 553 regmap_reg_range(0x1004, 0x100b), 554 regmap_reg_range(0x1013, 0x1013), 555 regmap_reg_range(0x1017, 0x1017), 556 regmap_reg_range(0x101b, 0x101b), 557 regmap_reg_range(0x101f, 0x1021), 558 regmap_reg_range(0x1030, 0x1030), 559 regmap_reg_range(0x1100, 0x1111), 560 regmap_reg_range(0x111a, 0x111d), 561 regmap_reg_range(0x1122, 0x1127), 562 regmap_reg_range(0x112a, 0x112b), 563 regmap_reg_range(0x1136, 0x1139), 564 regmap_reg_range(0x113e, 0x113f), 565 regmap_reg_range(0x1400, 0x1401), 566 regmap_reg_range(0x1403, 0x1403), 567 regmap_reg_range(0x1410, 0x1417), 568 regmap_reg_range(0x1420, 0x1423), 569 regmap_reg_range(0x1500, 0x1507), 570 regmap_reg_range(0x1600, 0x1612), 571 regmap_reg_range(0x1800, 0x180f), 572 regmap_reg_range(0x1900, 0x1907), 573 regmap_reg_range(0x1914, 0x191b), 574 regmap_reg_range(0x1a00, 0x1a03), 575 regmap_reg_range(0x1a04, 0x1a08), 576 regmap_reg_range(0x1b00, 0x1b01), 577 regmap_reg_range(0x1b04, 0x1b04), 578 regmap_reg_range(0x1c00, 0x1c05), 579 regmap_reg_range(0x1c08, 0x1c1b), 580 581 /* port 2 */ 582 regmap_reg_range(0x2000, 0x2001), 583 regmap_reg_range(0x2004, 0x200b), 584 regmap_reg_range(0x2013, 0x2013), 585 regmap_reg_range(0x2017, 0x2017), 586 regmap_reg_range(0x201b, 0x201b), 587 regmap_reg_range(0x201f, 0x2021), 588 regmap_reg_range(0x2030, 0x2030), 589 regmap_reg_range(0x2100, 0x2111), 590 regmap_reg_range(0x211a, 0x211d), 591 regmap_reg_range(0x2122, 0x2127), 592 regmap_reg_range(0x212a, 0x212b), 593 regmap_reg_range(0x2136, 0x2139), 594 regmap_reg_range(0x213e, 0x213f), 595 regmap_reg_range(0x2400, 0x2401), 596 regmap_reg_range(0x2403, 0x2403), 597 regmap_reg_range(0x2410, 0x2417), 598 regmap_reg_range(0x2420, 0x2423), 599 regmap_reg_range(0x2500, 0x2507), 600 regmap_reg_range(0x2600, 0x2612), 601 regmap_reg_range(0x2800, 0x280f), 602 regmap_reg_range(0x2900, 0x2907), 603 regmap_reg_range(0x2914, 0x291b), 604 regmap_reg_range(0x2a00, 0x2a03), 605 regmap_reg_range(0x2a04, 0x2a08), 606 regmap_reg_range(0x2b00, 0x2b01), 607 regmap_reg_range(0x2b04, 0x2b04), 608 regmap_reg_range(0x2c00, 0x2c05), 609 regmap_reg_range(0x2c08, 0x2c1b), 610 611 /* port 3 */ 612 regmap_reg_range(0x3000, 0x3001), 613 regmap_reg_range(0x3004, 0x300b), 614 regmap_reg_range(0x3013, 0x3013), 615 regmap_reg_range(0x3017, 0x3017), 616 regmap_reg_range(0x301b, 0x301b), 617 regmap_reg_range(0x301f, 0x3021), 618 regmap_reg_range(0x3030, 0x3030), 619 regmap_reg_range(0x3300, 0x3301), 620 regmap_reg_range(0x3303, 0x3303), 621 regmap_reg_range(0x3400, 0x3401), 622 regmap_reg_range(0x3403, 0x3403), 623 regmap_reg_range(0x3410, 0x3417), 624 regmap_reg_range(0x3420, 0x3423), 625 regmap_reg_range(0x3500, 0x3507), 626 regmap_reg_range(0x3600, 0x3612), 627 regmap_reg_range(0x3800, 0x380f), 628 regmap_reg_range(0x3900, 0x3907), 629 regmap_reg_range(0x3914, 0x391b), 630 regmap_reg_range(0x3a00, 0x3a03), 631 regmap_reg_range(0x3a04, 0x3a08), 632 regmap_reg_range(0x3b00, 0x3b01), 633 regmap_reg_range(0x3b04, 0x3b04), 634 regmap_reg_range(0x3c00, 0x3c05), 635 regmap_reg_range(0x3c08, 0x3c1b), 636 }; 637 638 static const struct regmap_access_table ksz8563_register_set = { 639 .yes_ranges = ksz8563_valid_regs, 640 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 641 }; 642 643 static const struct regmap_range ksz9477_valid_regs[] = { 644 regmap_reg_range(0x0000, 0x0003), 645 regmap_reg_range(0x0006, 0x0006), 646 regmap_reg_range(0x0010, 0x001f), 647 regmap_reg_range(0x0100, 0x0100), 648 regmap_reg_range(0x0103, 0x0107), 649 regmap_reg_range(0x010d, 0x010d), 650 regmap_reg_range(0x0110, 0x0113), 651 regmap_reg_range(0x0120, 0x012b), 652 regmap_reg_range(0x0201, 0x0201), 653 regmap_reg_range(0x0210, 0x0213), 654 regmap_reg_range(0x0300, 0x0300), 655 regmap_reg_range(0x0302, 0x031b), 656 regmap_reg_range(0x0320, 0x032b), 657 regmap_reg_range(0x0330, 0x0336), 658 regmap_reg_range(0x0338, 0x033b), 659 regmap_reg_range(0x033e, 0x033e), 660 regmap_reg_range(0x0340, 0x035f), 661 regmap_reg_range(0x0370, 0x0370), 662 regmap_reg_range(0x0378, 0x0378), 663 regmap_reg_range(0x037c, 0x037d), 664 regmap_reg_range(0x0390, 0x0393), 665 regmap_reg_range(0x0400, 0x040e), 666 regmap_reg_range(0x0410, 0x042f), 667 regmap_reg_range(0x0444, 0x044b), 668 regmap_reg_range(0x0450, 0x046f), 669 regmap_reg_range(0x0500, 0x0519), 670 regmap_reg_range(0x0520, 0x054b), 671 regmap_reg_range(0x0550, 0x05b3), 672 regmap_reg_range(0x0604, 0x060b), 673 regmap_reg_range(0x0610, 0x0612), 674 regmap_reg_range(0x0614, 0x062c), 675 regmap_reg_range(0x0640, 0x0645), 676 regmap_reg_range(0x0648, 0x064d), 677 678 /* port 1 */ 679 regmap_reg_range(0x1000, 0x1001), 680 regmap_reg_range(0x1013, 0x1013), 681 regmap_reg_range(0x1017, 0x1017), 682 regmap_reg_range(0x101b, 0x101b), 683 regmap_reg_range(0x101f, 0x1020), 684 regmap_reg_range(0x1030, 0x1030), 685 regmap_reg_range(0x1100, 0x1115), 686 regmap_reg_range(0x111a, 0x111f), 687 regmap_reg_range(0x1120, 0x112b), 688 regmap_reg_range(0x1134, 0x113b), 689 regmap_reg_range(0x113c, 0x113f), 690 regmap_reg_range(0x1400, 0x1401), 691 regmap_reg_range(0x1403, 0x1403), 692 regmap_reg_range(0x1410, 0x1417), 693 regmap_reg_range(0x1420, 0x1423), 694 regmap_reg_range(0x1500, 0x1507), 695 regmap_reg_range(0x1600, 0x1613), 696 regmap_reg_range(0x1800, 0x180f), 697 regmap_reg_range(0x1820, 0x1827), 698 regmap_reg_range(0x1830, 0x1837), 699 regmap_reg_range(0x1840, 0x184b), 700 regmap_reg_range(0x1900, 0x1907), 701 regmap_reg_range(0x1914, 0x191b), 702 regmap_reg_range(0x1920, 0x1920), 703 regmap_reg_range(0x1923, 0x1927), 704 regmap_reg_range(0x1a00, 0x1a03), 705 regmap_reg_range(0x1a04, 0x1a07), 706 regmap_reg_range(0x1b00, 0x1b01), 707 regmap_reg_range(0x1b04, 0x1b04), 708 regmap_reg_range(0x1c00, 0x1c05), 709 regmap_reg_range(0x1c08, 0x1c1b), 710 711 /* port 2 */ 712 regmap_reg_range(0x2000, 0x2001), 713 regmap_reg_range(0x2013, 0x2013), 714 regmap_reg_range(0x2017, 0x2017), 715 regmap_reg_range(0x201b, 0x201b), 716 regmap_reg_range(0x201f, 0x2020), 717 regmap_reg_range(0x2030, 0x2030), 718 regmap_reg_range(0x2100, 0x2115), 719 regmap_reg_range(0x211a, 0x211f), 720 regmap_reg_range(0x2120, 0x212b), 721 regmap_reg_range(0x2134, 0x213b), 722 regmap_reg_range(0x213c, 0x213f), 723 regmap_reg_range(0x2400, 0x2401), 724 regmap_reg_range(0x2403, 0x2403), 725 regmap_reg_range(0x2410, 0x2417), 726 regmap_reg_range(0x2420, 0x2423), 727 regmap_reg_range(0x2500, 0x2507), 728 regmap_reg_range(0x2600, 0x2613), 729 regmap_reg_range(0x2800, 0x280f), 730 regmap_reg_range(0x2820, 0x2827), 731 regmap_reg_range(0x2830, 0x2837), 732 regmap_reg_range(0x2840, 0x284b), 733 regmap_reg_range(0x2900, 0x2907), 734 regmap_reg_range(0x2914, 0x291b), 735 regmap_reg_range(0x2920, 0x2920), 736 regmap_reg_range(0x2923, 0x2927), 737 regmap_reg_range(0x2a00, 0x2a03), 738 regmap_reg_range(0x2a04, 0x2a07), 739 regmap_reg_range(0x2b00, 0x2b01), 740 regmap_reg_range(0x2b04, 0x2b04), 741 regmap_reg_range(0x2c00, 0x2c05), 742 regmap_reg_range(0x2c08, 0x2c1b), 743 744 /* port 3 */ 745 regmap_reg_range(0x3000, 0x3001), 746 regmap_reg_range(0x3013, 0x3013), 747 regmap_reg_range(0x3017, 0x3017), 748 regmap_reg_range(0x301b, 0x301b), 749 regmap_reg_range(0x301f, 0x3020), 750 regmap_reg_range(0x3030, 0x3030), 751 regmap_reg_range(0x3100, 0x3115), 752 regmap_reg_range(0x311a, 0x311f), 753 regmap_reg_range(0x3120, 0x312b), 754 regmap_reg_range(0x3134, 0x313b), 755 regmap_reg_range(0x313c, 0x313f), 756 regmap_reg_range(0x3400, 0x3401), 757 regmap_reg_range(0x3403, 0x3403), 758 regmap_reg_range(0x3410, 0x3417), 759 regmap_reg_range(0x3420, 0x3423), 760 regmap_reg_range(0x3500, 0x3507), 761 regmap_reg_range(0x3600, 0x3613), 762 regmap_reg_range(0x3800, 0x380f), 763 regmap_reg_range(0x3820, 0x3827), 764 regmap_reg_range(0x3830, 0x3837), 765 regmap_reg_range(0x3840, 0x384b), 766 regmap_reg_range(0x3900, 0x3907), 767 regmap_reg_range(0x3914, 0x391b), 768 regmap_reg_range(0x3920, 0x3920), 769 regmap_reg_range(0x3923, 0x3927), 770 regmap_reg_range(0x3a00, 0x3a03), 771 regmap_reg_range(0x3a04, 0x3a07), 772 regmap_reg_range(0x3b00, 0x3b01), 773 regmap_reg_range(0x3b04, 0x3b04), 774 regmap_reg_range(0x3c00, 0x3c05), 775 regmap_reg_range(0x3c08, 0x3c1b), 776 777 /* port 4 */ 778 regmap_reg_range(0x4000, 0x4001), 779 regmap_reg_range(0x4013, 0x4013), 780 regmap_reg_range(0x4017, 0x4017), 781 regmap_reg_range(0x401b, 0x401b), 782 regmap_reg_range(0x401f, 0x4020), 783 regmap_reg_range(0x4030, 0x4030), 784 regmap_reg_range(0x4100, 0x4115), 785 regmap_reg_range(0x411a, 0x411f), 786 regmap_reg_range(0x4120, 0x412b), 787 regmap_reg_range(0x4134, 0x413b), 788 regmap_reg_range(0x413c, 0x413f), 789 regmap_reg_range(0x4400, 0x4401), 790 regmap_reg_range(0x4403, 0x4403), 791 regmap_reg_range(0x4410, 0x4417), 792 regmap_reg_range(0x4420, 0x4423), 793 regmap_reg_range(0x4500, 0x4507), 794 regmap_reg_range(0x4600, 0x4613), 795 regmap_reg_range(0x4800, 0x480f), 796 regmap_reg_range(0x4820, 0x4827), 797 regmap_reg_range(0x4830, 0x4837), 798 regmap_reg_range(0x4840, 0x484b), 799 regmap_reg_range(0x4900, 0x4907), 800 regmap_reg_range(0x4914, 0x491b), 801 regmap_reg_range(0x4920, 0x4920), 802 regmap_reg_range(0x4923, 0x4927), 803 regmap_reg_range(0x4a00, 0x4a03), 804 regmap_reg_range(0x4a04, 0x4a07), 805 regmap_reg_range(0x4b00, 0x4b01), 806 regmap_reg_range(0x4b04, 0x4b04), 807 regmap_reg_range(0x4c00, 0x4c05), 808 regmap_reg_range(0x4c08, 0x4c1b), 809 810 /* port 5 */ 811 regmap_reg_range(0x5000, 0x5001), 812 regmap_reg_range(0x5013, 0x5013), 813 regmap_reg_range(0x5017, 0x5017), 814 regmap_reg_range(0x501b, 0x501b), 815 regmap_reg_range(0x501f, 0x5020), 816 regmap_reg_range(0x5030, 0x5030), 817 regmap_reg_range(0x5100, 0x5115), 818 regmap_reg_range(0x511a, 0x511f), 819 regmap_reg_range(0x5120, 0x512b), 820 regmap_reg_range(0x5134, 0x513b), 821 regmap_reg_range(0x513c, 0x513f), 822 regmap_reg_range(0x5400, 0x5401), 823 regmap_reg_range(0x5403, 0x5403), 824 regmap_reg_range(0x5410, 0x5417), 825 regmap_reg_range(0x5420, 0x5423), 826 regmap_reg_range(0x5500, 0x5507), 827 regmap_reg_range(0x5600, 0x5613), 828 regmap_reg_range(0x5800, 0x580f), 829 regmap_reg_range(0x5820, 0x5827), 830 regmap_reg_range(0x5830, 0x5837), 831 regmap_reg_range(0x5840, 0x584b), 832 regmap_reg_range(0x5900, 0x5907), 833 regmap_reg_range(0x5914, 0x591b), 834 regmap_reg_range(0x5920, 0x5920), 835 regmap_reg_range(0x5923, 0x5927), 836 regmap_reg_range(0x5a00, 0x5a03), 837 regmap_reg_range(0x5a04, 0x5a07), 838 regmap_reg_range(0x5b00, 0x5b01), 839 regmap_reg_range(0x5b04, 0x5b04), 840 regmap_reg_range(0x5c00, 0x5c05), 841 regmap_reg_range(0x5c08, 0x5c1b), 842 843 /* port 6 */ 844 regmap_reg_range(0x6000, 0x6001), 845 regmap_reg_range(0x6013, 0x6013), 846 regmap_reg_range(0x6017, 0x6017), 847 regmap_reg_range(0x601b, 0x601b), 848 regmap_reg_range(0x601f, 0x6020), 849 regmap_reg_range(0x6030, 0x6030), 850 regmap_reg_range(0x6300, 0x6301), 851 regmap_reg_range(0x6400, 0x6401), 852 regmap_reg_range(0x6403, 0x6403), 853 regmap_reg_range(0x6410, 0x6417), 854 regmap_reg_range(0x6420, 0x6423), 855 regmap_reg_range(0x6500, 0x6507), 856 regmap_reg_range(0x6600, 0x6613), 857 regmap_reg_range(0x6800, 0x680f), 858 regmap_reg_range(0x6820, 0x6827), 859 regmap_reg_range(0x6830, 0x6837), 860 regmap_reg_range(0x6840, 0x684b), 861 regmap_reg_range(0x6900, 0x6907), 862 regmap_reg_range(0x6914, 0x691b), 863 regmap_reg_range(0x6920, 0x6920), 864 regmap_reg_range(0x6923, 0x6927), 865 regmap_reg_range(0x6a00, 0x6a03), 866 regmap_reg_range(0x6a04, 0x6a07), 867 regmap_reg_range(0x6b00, 0x6b01), 868 regmap_reg_range(0x6b04, 0x6b04), 869 regmap_reg_range(0x6c00, 0x6c05), 870 regmap_reg_range(0x6c08, 0x6c1b), 871 872 /* port 7 */ 873 regmap_reg_range(0x7000, 0x7001), 874 regmap_reg_range(0x7013, 0x7013), 875 regmap_reg_range(0x7017, 0x7017), 876 regmap_reg_range(0x701b, 0x701b), 877 regmap_reg_range(0x701f, 0x7020), 878 regmap_reg_range(0x7030, 0x7030), 879 regmap_reg_range(0x7200, 0x7207), 880 regmap_reg_range(0x7300, 0x7301), 881 regmap_reg_range(0x7400, 0x7401), 882 regmap_reg_range(0x7403, 0x7403), 883 regmap_reg_range(0x7410, 0x7417), 884 regmap_reg_range(0x7420, 0x7423), 885 regmap_reg_range(0x7500, 0x7507), 886 regmap_reg_range(0x7600, 0x7613), 887 regmap_reg_range(0x7800, 0x780f), 888 regmap_reg_range(0x7820, 0x7827), 889 regmap_reg_range(0x7830, 0x7837), 890 regmap_reg_range(0x7840, 0x784b), 891 regmap_reg_range(0x7900, 0x7907), 892 regmap_reg_range(0x7914, 0x791b), 893 regmap_reg_range(0x7920, 0x7920), 894 regmap_reg_range(0x7923, 0x7927), 895 regmap_reg_range(0x7a00, 0x7a03), 896 regmap_reg_range(0x7a04, 0x7a07), 897 regmap_reg_range(0x7b00, 0x7b01), 898 regmap_reg_range(0x7b04, 0x7b04), 899 regmap_reg_range(0x7c00, 0x7c05), 900 regmap_reg_range(0x7c08, 0x7c1b), 901 }; 902 903 static const struct regmap_access_table ksz9477_register_set = { 904 .yes_ranges = ksz9477_valid_regs, 905 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 906 }; 907 908 static const struct regmap_range ksz9896_valid_regs[] = { 909 regmap_reg_range(0x0000, 0x0003), 910 regmap_reg_range(0x0006, 0x0006), 911 regmap_reg_range(0x0010, 0x001f), 912 regmap_reg_range(0x0100, 0x0100), 913 regmap_reg_range(0x0103, 0x0107), 914 regmap_reg_range(0x010d, 0x010d), 915 regmap_reg_range(0x0110, 0x0113), 916 regmap_reg_range(0x0120, 0x0127), 917 regmap_reg_range(0x0201, 0x0201), 918 regmap_reg_range(0x0210, 0x0213), 919 regmap_reg_range(0x0300, 0x0300), 920 regmap_reg_range(0x0302, 0x030b), 921 regmap_reg_range(0x0310, 0x031b), 922 regmap_reg_range(0x0320, 0x032b), 923 regmap_reg_range(0x0330, 0x0336), 924 regmap_reg_range(0x0338, 0x033b), 925 regmap_reg_range(0x033e, 0x033e), 926 regmap_reg_range(0x0340, 0x035f), 927 regmap_reg_range(0x0370, 0x0370), 928 regmap_reg_range(0x0378, 0x0378), 929 regmap_reg_range(0x037c, 0x037d), 930 regmap_reg_range(0x0390, 0x0393), 931 regmap_reg_range(0x0400, 0x040e), 932 regmap_reg_range(0x0410, 0x042f), 933 934 /* port 1 */ 935 regmap_reg_range(0x1000, 0x1001), 936 regmap_reg_range(0x1013, 0x1013), 937 regmap_reg_range(0x1017, 0x1017), 938 regmap_reg_range(0x101b, 0x101b), 939 regmap_reg_range(0x101f, 0x1020), 940 regmap_reg_range(0x1030, 0x1030), 941 regmap_reg_range(0x1100, 0x1115), 942 regmap_reg_range(0x111a, 0x111f), 943 regmap_reg_range(0x1120, 0x112b), 944 regmap_reg_range(0x1134, 0x113b), 945 regmap_reg_range(0x113c, 0x113f), 946 regmap_reg_range(0x1400, 0x1401), 947 regmap_reg_range(0x1403, 0x1403), 948 regmap_reg_range(0x1410, 0x1417), 949 regmap_reg_range(0x1420, 0x1423), 950 regmap_reg_range(0x1500, 0x1507), 951 regmap_reg_range(0x1600, 0x1612), 952 regmap_reg_range(0x1800, 0x180f), 953 regmap_reg_range(0x1820, 0x1827), 954 regmap_reg_range(0x1830, 0x1837), 955 regmap_reg_range(0x1840, 0x184b), 956 regmap_reg_range(0x1900, 0x1907), 957 regmap_reg_range(0x1914, 0x1915), 958 regmap_reg_range(0x1a00, 0x1a03), 959 regmap_reg_range(0x1a04, 0x1a07), 960 regmap_reg_range(0x1b00, 0x1b01), 961 regmap_reg_range(0x1b04, 0x1b04), 962 963 /* port 2 */ 964 regmap_reg_range(0x2000, 0x2001), 965 regmap_reg_range(0x2013, 0x2013), 966 regmap_reg_range(0x2017, 0x2017), 967 regmap_reg_range(0x201b, 0x201b), 968 regmap_reg_range(0x201f, 0x2020), 969 regmap_reg_range(0x2030, 0x2030), 970 regmap_reg_range(0x2100, 0x2115), 971 regmap_reg_range(0x211a, 0x211f), 972 regmap_reg_range(0x2120, 0x212b), 973 regmap_reg_range(0x2134, 0x213b), 974 regmap_reg_range(0x213c, 0x213f), 975 regmap_reg_range(0x2400, 0x2401), 976 regmap_reg_range(0x2403, 0x2403), 977 regmap_reg_range(0x2410, 0x2417), 978 regmap_reg_range(0x2420, 0x2423), 979 regmap_reg_range(0x2500, 0x2507), 980 regmap_reg_range(0x2600, 0x2612), 981 regmap_reg_range(0x2800, 0x280f), 982 regmap_reg_range(0x2820, 0x2827), 983 regmap_reg_range(0x2830, 0x2837), 984 regmap_reg_range(0x2840, 0x284b), 985 regmap_reg_range(0x2900, 0x2907), 986 regmap_reg_range(0x2914, 0x2915), 987 regmap_reg_range(0x2a00, 0x2a03), 988 regmap_reg_range(0x2a04, 0x2a07), 989 regmap_reg_range(0x2b00, 0x2b01), 990 regmap_reg_range(0x2b04, 0x2b04), 991 992 /* port 3 */ 993 regmap_reg_range(0x3000, 0x3001), 994 regmap_reg_range(0x3013, 0x3013), 995 regmap_reg_range(0x3017, 0x3017), 996 regmap_reg_range(0x301b, 0x301b), 997 regmap_reg_range(0x301f, 0x3020), 998 regmap_reg_range(0x3030, 0x3030), 999 regmap_reg_range(0x3100, 0x3115), 1000 regmap_reg_range(0x311a, 0x311f), 1001 regmap_reg_range(0x3120, 0x312b), 1002 regmap_reg_range(0x3134, 0x313b), 1003 regmap_reg_range(0x313c, 0x313f), 1004 regmap_reg_range(0x3400, 0x3401), 1005 regmap_reg_range(0x3403, 0x3403), 1006 regmap_reg_range(0x3410, 0x3417), 1007 regmap_reg_range(0x3420, 0x3423), 1008 regmap_reg_range(0x3500, 0x3507), 1009 regmap_reg_range(0x3600, 0x3612), 1010 regmap_reg_range(0x3800, 0x380f), 1011 regmap_reg_range(0x3820, 0x3827), 1012 regmap_reg_range(0x3830, 0x3837), 1013 regmap_reg_range(0x3840, 0x384b), 1014 regmap_reg_range(0x3900, 0x3907), 1015 regmap_reg_range(0x3914, 0x3915), 1016 regmap_reg_range(0x3a00, 0x3a03), 1017 regmap_reg_range(0x3a04, 0x3a07), 1018 regmap_reg_range(0x3b00, 0x3b01), 1019 regmap_reg_range(0x3b04, 0x3b04), 1020 1021 /* port 4 */ 1022 regmap_reg_range(0x4000, 0x4001), 1023 regmap_reg_range(0x4013, 0x4013), 1024 regmap_reg_range(0x4017, 0x4017), 1025 regmap_reg_range(0x401b, 0x401b), 1026 regmap_reg_range(0x401f, 0x4020), 1027 regmap_reg_range(0x4030, 0x4030), 1028 regmap_reg_range(0x4100, 0x4115), 1029 regmap_reg_range(0x411a, 0x411f), 1030 regmap_reg_range(0x4120, 0x412b), 1031 regmap_reg_range(0x4134, 0x413b), 1032 regmap_reg_range(0x413c, 0x413f), 1033 regmap_reg_range(0x4400, 0x4401), 1034 regmap_reg_range(0x4403, 0x4403), 1035 regmap_reg_range(0x4410, 0x4417), 1036 regmap_reg_range(0x4420, 0x4423), 1037 regmap_reg_range(0x4500, 0x4507), 1038 regmap_reg_range(0x4600, 0x4612), 1039 regmap_reg_range(0x4800, 0x480f), 1040 regmap_reg_range(0x4820, 0x4827), 1041 regmap_reg_range(0x4830, 0x4837), 1042 regmap_reg_range(0x4840, 0x484b), 1043 regmap_reg_range(0x4900, 0x4907), 1044 regmap_reg_range(0x4914, 0x4915), 1045 regmap_reg_range(0x4a00, 0x4a03), 1046 regmap_reg_range(0x4a04, 0x4a07), 1047 regmap_reg_range(0x4b00, 0x4b01), 1048 regmap_reg_range(0x4b04, 0x4b04), 1049 1050 /* port 5 */ 1051 regmap_reg_range(0x5000, 0x5001), 1052 regmap_reg_range(0x5013, 0x5013), 1053 regmap_reg_range(0x5017, 0x5017), 1054 regmap_reg_range(0x501b, 0x501b), 1055 regmap_reg_range(0x501f, 0x5020), 1056 regmap_reg_range(0x5030, 0x5030), 1057 regmap_reg_range(0x5100, 0x5115), 1058 regmap_reg_range(0x511a, 0x511f), 1059 regmap_reg_range(0x5120, 0x512b), 1060 regmap_reg_range(0x5134, 0x513b), 1061 regmap_reg_range(0x513c, 0x513f), 1062 regmap_reg_range(0x5400, 0x5401), 1063 regmap_reg_range(0x5403, 0x5403), 1064 regmap_reg_range(0x5410, 0x5417), 1065 regmap_reg_range(0x5420, 0x5423), 1066 regmap_reg_range(0x5500, 0x5507), 1067 regmap_reg_range(0x5600, 0x5612), 1068 regmap_reg_range(0x5800, 0x580f), 1069 regmap_reg_range(0x5820, 0x5827), 1070 regmap_reg_range(0x5830, 0x5837), 1071 regmap_reg_range(0x5840, 0x584b), 1072 regmap_reg_range(0x5900, 0x5907), 1073 regmap_reg_range(0x5914, 0x5915), 1074 regmap_reg_range(0x5a00, 0x5a03), 1075 regmap_reg_range(0x5a04, 0x5a07), 1076 regmap_reg_range(0x5b00, 0x5b01), 1077 regmap_reg_range(0x5b04, 0x5b04), 1078 1079 /* port 6 */ 1080 regmap_reg_range(0x6000, 0x6001), 1081 regmap_reg_range(0x6013, 0x6013), 1082 regmap_reg_range(0x6017, 0x6017), 1083 regmap_reg_range(0x601b, 0x601b), 1084 regmap_reg_range(0x601f, 0x6020), 1085 regmap_reg_range(0x6030, 0x6030), 1086 regmap_reg_range(0x6100, 0x6115), 1087 regmap_reg_range(0x611a, 0x611f), 1088 regmap_reg_range(0x6120, 0x612b), 1089 regmap_reg_range(0x6134, 0x613b), 1090 regmap_reg_range(0x613c, 0x613f), 1091 regmap_reg_range(0x6300, 0x6301), 1092 regmap_reg_range(0x6400, 0x6401), 1093 regmap_reg_range(0x6403, 0x6403), 1094 regmap_reg_range(0x6410, 0x6417), 1095 regmap_reg_range(0x6420, 0x6423), 1096 regmap_reg_range(0x6500, 0x6507), 1097 regmap_reg_range(0x6600, 0x6612), 1098 regmap_reg_range(0x6800, 0x680f), 1099 regmap_reg_range(0x6820, 0x6827), 1100 regmap_reg_range(0x6830, 0x6837), 1101 regmap_reg_range(0x6840, 0x684b), 1102 regmap_reg_range(0x6900, 0x6907), 1103 regmap_reg_range(0x6914, 0x6915), 1104 regmap_reg_range(0x6a00, 0x6a03), 1105 regmap_reg_range(0x6a04, 0x6a07), 1106 regmap_reg_range(0x6b00, 0x6b01), 1107 regmap_reg_range(0x6b04, 0x6b04), 1108 }; 1109 1110 static const struct regmap_access_table ksz9896_register_set = { 1111 .yes_ranges = ksz9896_valid_regs, 1112 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1113 }; 1114 1115 static const struct regmap_range ksz8873_valid_regs[] = { 1116 regmap_reg_range(0x00, 0x01), 1117 /* global control register */ 1118 regmap_reg_range(0x02, 0x0f), 1119 1120 /* port registers */ 1121 regmap_reg_range(0x10, 0x1d), 1122 regmap_reg_range(0x1e, 0x1f), 1123 regmap_reg_range(0x20, 0x2d), 1124 regmap_reg_range(0x2e, 0x2f), 1125 regmap_reg_range(0x30, 0x39), 1126 regmap_reg_range(0x3f, 0x3f), 1127 1128 /* advanced control registers */ 1129 regmap_reg_range(0x43, 0x43), 1130 regmap_reg_range(0x60, 0x6f), 1131 regmap_reg_range(0x70, 0x75), 1132 regmap_reg_range(0x76, 0x78), 1133 regmap_reg_range(0x79, 0x7a), 1134 regmap_reg_range(0x7b, 0x83), 1135 regmap_reg_range(0x8e, 0x99), 1136 regmap_reg_range(0x9a, 0xa5), 1137 regmap_reg_range(0xa6, 0xa6), 1138 regmap_reg_range(0xa7, 0xaa), 1139 regmap_reg_range(0xab, 0xae), 1140 regmap_reg_range(0xaf, 0xba), 1141 regmap_reg_range(0xbb, 0xbc), 1142 regmap_reg_range(0xbd, 0xbd), 1143 regmap_reg_range(0xc0, 0xc0), 1144 regmap_reg_range(0xc2, 0xc2), 1145 regmap_reg_range(0xc3, 0xc3), 1146 regmap_reg_range(0xc4, 0xc4), 1147 regmap_reg_range(0xc6, 0xc6), 1148 }; 1149 1150 static const struct regmap_access_table ksz8873_register_set = { 1151 .yes_ranges = ksz8873_valid_regs, 1152 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), 1153 }; 1154 1155 const struct ksz_chip_data ksz_switch_chips[] = { 1156 [KSZ8463] = { 1157 .chip_id = KSZ8463_CHIP_ID, 1158 .dev_name = "KSZ8463", 1159 .num_vlans = 16, 1160 .num_alus = 0, 1161 .num_statics = 8, 1162 .cpu_ports = 0x4, /* can be configured as cpu port */ 1163 .port_cnt = 3, 1164 .num_tx_queues = 4, 1165 .num_ipms = 4, 1166 .ops = &ksz8463_dev_ops, 1167 .switch_ops = &ksz8463_switch_ops, 1168 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1169 .mib_names = ksz88xx_mib_names, 1170 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1171 .reg_mib_cnt = MIB_COUNTER_NUM, 1172 .regs = ksz8463_regs, 1173 .masks = ksz8463_masks, 1174 .shifts = ksz8463_shifts, 1175 .supports_mii = {false, false, true}, 1176 .supports_rmii = {false, false, true}, 1177 .internal_phy = {true, true, false}, 1178 .n_pins = 12, 1179 .n_per_out = 12, 1180 }, 1181 1182 [KSZ8563] = { 1183 .chip_id = KSZ8563_CHIP_ID, 1184 .dev_name = "KSZ8563", 1185 .num_vlans = 4096, 1186 .num_alus = 4096, 1187 .num_statics = 16, 1188 .cpu_ports = 0x07, /* can be configured as cpu port */ 1189 .port_cnt = 3, /* total port count */ 1190 .port_nirqs = 3, 1191 .num_tx_queues = 4, 1192 .num_ipms = 8, 1193 .tc_cbs_supported = true, 1194 .ops = &ksz9477_dev_ops, 1195 .switch_ops = &ksz9477_switch_ops, 1196 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1197 .mib_names = ksz9477_mib_names, 1198 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1199 .reg_mib_cnt = MIB_COUNTER_NUM, 1200 .regs = ksz9477_regs, 1201 .masks = ksz9477_masks, 1202 .shifts = ksz9477_shifts, 1203 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1204 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1205 .supports_mii = {false, false, true}, 1206 .supports_rmii = {false, false, true}, 1207 .supports_rgmii = {false, false, true}, 1208 .internal_phy = {true, true, false}, 1209 .gbit_capable = {false, false, true}, 1210 .ptp_capable = true, 1211 .wr_table = &ksz8563_register_set, 1212 .rd_table = &ksz8563_register_set, 1213 .n_pins = 2, 1214 .n_per_out = 3, 1215 }, 1216 1217 [KSZ8795] = { 1218 .chip_id = KSZ8795_CHIP_ID, 1219 .dev_name = "KSZ8795", 1220 .num_vlans = 4096, 1221 .num_alus = 0, 1222 .num_statics = 32, 1223 .cpu_ports = 0x10, /* can be configured as cpu port */ 1224 .port_cnt = 5, /* total cpu and user ports */ 1225 .num_tx_queues = 4, 1226 .num_ipms = 4, 1227 .ops = &ksz87xx_dev_ops, 1228 .switch_ops = &ksz87xx_switch_ops, 1229 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1230 .ksz87xx_eee_link_erratum = true, 1231 .mib_names = ksz9477_mib_names, 1232 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1233 .reg_mib_cnt = MIB_COUNTER_NUM, 1234 .regs = ksz8795_regs, 1235 .masks = ksz8795_masks, 1236 .shifts = ksz8795_shifts, 1237 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1238 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1239 .supports_mii = {false, false, false, false, true}, 1240 .supports_rmii = {false, false, false, false, true}, 1241 .supports_rgmii = {false, false, false, false, true}, 1242 .internal_phy = {true, true, true, true, false}, 1243 }, 1244 1245 [KSZ8794] = { 1246 /* WARNING 1247 * ======= 1248 * KSZ8794 is similar to KSZ8795, except the port map 1249 * contains a gap between external and CPU ports, the 1250 * port map is NOT continuous. The per-port register 1251 * map is shifted accordingly too, i.e. registers at 1252 * offset 0x40 are NOT used on KSZ8794 and they ARE 1253 * used on KSZ8795 for external port 3. 1254 * external cpu 1255 * KSZ8794 0,1,2 4 1256 * KSZ8795 0,1,2,3 4 1257 * KSZ8765 0,1,2,3 4 1258 * port_cnt is configured as 5, even though it is 4 1259 */ 1260 .chip_id = KSZ8794_CHIP_ID, 1261 .dev_name = "KSZ8794", 1262 .num_vlans = 4096, 1263 .num_alus = 0, 1264 .num_statics = 32, 1265 .cpu_ports = 0x10, /* can be configured as cpu port */ 1266 .port_cnt = 5, /* total cpu and user ports */ 1267 .num_tx_queues = 4, 1268 .num_ipms = 4, 1269 .ops = &ksz87xx_dev_ops, 1270 .switch_ops = &ksz87xx_switch_ops, 1271 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1272 .ksz87xx_eee_link_erratum = true, 1273 .mib_names = ksz9477_mib_names, 1274 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1275 .reg_mib_cnt = MIB_COUNTER_NUM, 1276 .regs = ksz8795_regs, 1277 .masks = ksz8795_masks, 1278 .shifts = ksz8795_shifts, 1279 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1280 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1281 .supports_mii = {false, false, false, false, true}, 1282 .supports_rmii = {false, false, false, false, true}, 1283 .supports_rgmii = {false, false, false, false, true}, 1284 .internal_phy = {true, true, true, false, false}, 1285 }, 1286 1287 [KSZ8765] = { 1288 .chip_id = KSZ8765_CHIP_ID, 1289 .dev_name = "KSZ8765", 1290 .num_vlans = 4096, 1291 .num_alus = 0, 1292 .num_statics = 32, 1293 .cpu_ports = 0x10, /* can be configured as cpu port */ 1294 .port_cnt = 5, /* total cpu and user ports */ 1295 .num_tx_queues = 4, 1296 .num_ipms = 4, 1297 .ops = &ksz87xx_dev_ops, 1298 .switch_ops = &ksz87xx_switch_ops, 1299 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1300 .ksz87xx_eee_link_erratum = true, 1301 .mib_names = ksz9477_mib_names, 1302 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1303 .reg_mib_cnt = MIB_COUNTER_NUM, 1304 .regs = ksz8795_regs, 1305 .masks = ksz8795_masks, 1306 .shifts = ksz8795_shifts, 1307 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1308 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1309 .supports_mii = {false, false, false, false, true}, 1310 .supports_rmii = {false, false, false, false, true}, 1311 .supports_rgmii = {false, false, false, false, true}, 1312 .internal_phy = {true, true, true, true, false}, 1313 }, 1314 1315 [KSZ88X3] = { 1316 .chip_id = KSZ88X3_CHIP_ID, 1317 .dev_name = "KSZ8863/KSZ8873", 1318 .num_vlans = 16, 1319 .num_alus = 0, 1320 .num_statics = 8, 1321 .cpu_ports = 0x4, /* can be configured as cpu port */ 1322 .port_cnt = 3, 1323 .num_tx_queues = 4, 1324 .num_ipms = 4, 1325 .ops = &ksz88xx_dev_ops, 1326 .switch_ops = &ksz88xx_switch_ops, 1327 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1328 .mib_names = ksz88xx_mib_names, 1329 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1330 .reg_mib_cnt = MIB_COUNTER_NUM, 1331 .regs = ksz8863_regs, 1332 .masks = ksz8863_masks, 1333 .shifts = ksz8863_shifts, 1334 .supports_mii = {false, false, true}, 1335 .supports_rmii = {false, false, true}, 1336 .internal_phy = {true, true, false}, 1337 .wr_table = &ksz8873_register_set, 1338 .rd_table = &ksz8873_register_set, 1339 }, 1340 1341 [KSZ8864] = { 1342 /* WARNING 1343 * ======= 1344 * KSZ8864 is similar to KSZ8895, except the first port 1345 * does not exist. 1346 * external cpu 1347 * KSZ8864 1,2,3 4 1348 * KSZ8895 0,1,2,3 4 1349 * port_cnt is configured as 5, even though it is 4 1350 */ 1351 .chip_id = KSZ8864_CHIP_ID, 1352 .dev_name = "KSZ8864", 1353 .num_vlans = 4096, 1354 .num_alus = 0, 1355 .num_statics = 32, 1356 .cpu_ports = 0x10, /* can be configured as cpu port */ 1357 .port_cnt = 5, /* total cpu and user ports */ 1358 .num_tx_queues = 4, 1359 .num_ipms = 4, 1360 .ops = &ksz88xx_dev_ops, 1361 .switch_ops = &ksz88xx_switch_ops, 1362 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1363 .mib_names = ksz88xx_mib_names, 1364 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1365 .reg_mib_cnt = MIB_COUNTER_NUM, 1366 .regs = ksz8895_regs, 1367 .masks = ksz8895_masks, 1368 .shifts = ksz8895_shifts, 1369 .supports_mii = {false, false, false, false, true}, 1370 .supports_rmii = {false, false, false, false, true}, 1371 .internal_phy = {false, true, true, true, false}, 1372 }, 1373 1374 [KSZ8895] = { 1375 .chip_id = KSZ8895_CHIP_ID, 1376 .dev_name = "KSZ8895", 1377 .num_vlans = 4096, 1378 .num_alus = 0, 1379 .num_statics = 32, 1380 .cpu_ports = 0x10, /* can be configured as cpu port */ 1381 .port_cnt = 5, /* total cpu and user ports */ 1382 .num_tx_queues = 4, 1383 .num_ipms = 4, 1384 .ops = &ksz88xx_dev_ops, 1385 .switch_ops = &ksz88xx_switch_ops, 1386 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1387 .mib_names = ksz88xx_mib_names, 1388 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1389 .reg_mib_cnt = MIB_COUNTER_NUM, 1390 .regs = ksz8895_regs, 1391 .masks = ksz8895_masks, 1392 .shifts = ksz8895_shifts, 1393 .supports_mii = {false, false, false, false, true}, 1394 .supports_rmii = {false, false, false, false, true}, 1395 .internal_phy = {true, true, true, true, false}, 1396 }, 1397 1398 [KSZ8995XA] = { 1399 .chip_id = KSZ8995XA_CHIP_ID, /* Also known as KS8995XA */ 1400 .dev_name = "KSZ8995XA", 1401 .cpu_ports = 0x10, /* can be configured as cpu port */ 1402 .port_cnt = 5, /* total cpu and user ports */ 1403 .num_tx_queues = 2, /* low/hi priority queues, no more */ 1404 .num_ipms = 2, 1405 .ops = &ksz8995xa_dev_ops, 1406 .switch_ops = &ksz8995xa_switch_ops, 1407 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1408 .regs = ksz8995xa_regs, 1409 .supports_mii = {true, true, true, true, true}, 1410 .internal_phy = {true, true, true, true, false}, 1411 }, 1412 1413 [KSZ9477] = { 1414 .chip_id = KSZ9477_CHIP_ID, 1415 .dev_name = "KSZ9477", 1416 .num_vlans = 4096, 1417 .num_alus = 4096, 1418 .num_statics = 16, 1419 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1420 .port_cnt = 7, /* total physical port count */ 1421 .port_nirqs = 4, 1422 .num_tx_queues = 4, 1423 .num_ipms = 8, 1424 .tc_cbs_supported = true, 1425 .ops = &ksz9477_dev_ops, 1426 .switch_ops = &ksz9477_switch_ops, 1427 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1428 .phy_errata_9477 = true, 1429 .mib_names = ksz9477_mib_names, 1430 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1431 .reg_mib_cnt = MIB_COUNTER_NUM, 1432 .regs = ksz9477_regs, 1433 .masks = ksz9477_masks, 1434 .shifts = ksz9477_shifts, 1435 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1436 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1437 .supports_mii = {false, false, false, false, 1438 false, true, false}, 1439 .supports_rmii = {false, false, false, false, 1440 false, true, false}, 1441 .supports_rgmii = {false, false, false, false, 1442 false, true, false}, 1443 .internal_phy = {true, true, true, true, 1444 true, false, false}, 1445 .gbit_capable = {true, true, true, true, true, true, true}, 1446 .ptp_capable = true, 1447 .sgmii_port = 7, 1448 .wr_table = &ksz9477_register_set, 1449 .rd_table = &ksz9477_register_set, 1450 .n_pins = 2, 1451 .n_per_out = 3, 1452 }, 1453 1454 [KSZ9896] = { 1455 .chip_id = KSZ9896_CHIP_ID, 1456 .dev_name = "KSZ9896", 1457 .num_vlans = 4096, 1458 .num_alus = 4096, 1459 .num_statics = 16, 1460 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1461 .port_cnt = 6, /* total physical port count */ 1462 .port_nirqs = 2, 1463 .num_tx_queues = 4, 1464 .num_ipms = 8, 1465 .ops = &ksz9477_dev_ops, 1466 .switch_ops = &ksz9477_switch_ops, 1467 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1468 .phy_errata_9477 = true, 1469 .mib_names = ksz9477_mib_names, 1470 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1471 .reg_mib_cnt = MIB_COUNTER_NUM, 1472 .regs = ksz9477_regs, 1473 .masks = ksz9477_masks, 1474 .shifts = ksz9477_shifts, 1475 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1476 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1477 .supports_mii = {false, false, false, false, 1478 false, true}, 1479 .supports_rmii = {false, false, false, false, 1480 false, true}, 1481 .supports_rgmii = {false, false, false, false, 1482 false, true}, 1483 .internal_phy = {true, true, true, true, 1484 true, false}, 1485 .gbit_capable = {true, true, true, true, true, true}, 1486 .wr_table = &ksz9896_register_set, 1487 .rd_table = &ksz9896_register_set, 1488 }, 1489 1490 [KSZ9897] = { 1491 .chip_id = KSZ9897_CHIP_ID, 1492 .dev_name = "KSZ9897", 1493 .num_vlans = 4096, 1494 .num_alus = 4096, 1495 .num_statics = 16, 1496 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1497 .port_cnt = 7, /* total physical port count */ 1498 .port_nirqs = 2, 1499 .num_tx_queues = 4, 1500 .num_ipms = 8, 1501 .ops = &ksz9477_dev_ops, 1502 .switch_ops = &ksz9477_switch_ops, 1503 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1504 .phy_errata_9477 = true, 1505 .mib_names = ksz9477_mib_names, 1506 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1507 .reg_mib_cnt = MIB_COUNTER_NUM, 1508 .regs = ksz9477_regs, 1509 .masks = ksz9477_masks, 1510 .shifts = ksz9477_shifts, 1511 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1512 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1513 .supports_mii = {false, false, false, false, 1514 false, true, true}, 1515 .supports_rmii = {false, false, false, false, 1516 false, true, true}, 1517 .supports_rgmii = {false, false, false, false, 1518 false, true, true}, 1519 .internal_phy = {true, true, true, true, 1520 true, false, false}, 1521 .gbit_capable = {true, true, true, true, true, true, true}, 1522 }, 1523 1524 [KSZ9897S] = { 1525 .chip_id = KSZ9897S_CHIP_ID, 1526 .dev_name = "KSZ9897S", 1527 .num_vlans = 4096, 1528 .num_alus = 4096, 1529 .num_statics = 16, 1530 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1531 .port_cnt = 7, /* total physical port count */ 1532 .port_nirqs = 2, 1533 .num_tx_queues = 4, 1534 .num_ipms = 8, 1535 .ops = &ksz9477_dev_ops, 1536 .switch_ops = &ksz9477_switch_ops, 1537 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1538 .phy_errata_9477 = true, 1539 .mib_names = ksz9477_mib_names, 1540 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1541 .reg_mib_cnt = MIB_COUNTER_NUM, 1542 .regs = ksz9477_regs, 1543 .masks = ksz9477_masks, 1544 .shifts = ksz9477_shifts, 1545 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1546 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1547 .supports_mii = {false, false, false, false, 1548 false, true, false}, 1549 .supports_rmii = {false, false, false, false, 1550 false, true, false}, 1551 .supports_rgmii = {false, false, false, false, 1552 false, true, false}, 1553 .internal_phy = {true, true, true, true, 1554 true, false, false}, 1555 .gbit_capable = {true, true, true, true, true, true, true}, 1556 .sgmii_port = 7, 1557 }, 1558 1559 [KSZ9893] = { 1560 .chip_id = KSZ9893_CHIP_ID, 1561 .dev_name = "KSZ9893", 1562 .num_vlans = 4096, 1563 .num_alus = 4096, 1564 .num_statics = 16, 1565 .cpu_ports = 0x07, /* can be configured as cpu port */ 1566 .port_cnt = 3, /* total port count */ 1567 .port_nirqs = 2, 1568 .num_tx_queues = 4, 1569 .num_ipms = 8, 1570 .ops = &ksz9477_dev_ops, 1571 .switch_ops = &ksz9477_switch_ops, 1572 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1573 .mib_names = ksz9477_mib_names, 1574 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1575 .reg_mib_cnt = MIB_COUNTER_NUM, 1576 .regs = ksz9477_regs, 1577 .masks = ksz9477_masks, 1578 .shifts = ksz9477_shifts, 1579 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1580 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1581 .supports_mii = {false, false, true}, 1582 .supports_rmii = {false, false, true}, 1583 .supports_rgmii = {false, false, true}, 1584 .internal_phy = {true, true, false}, 1585 .gbit_capable = {true, true, true}, 1586 }, 1587 1588 [KSZ9563] = { 1589 .chip_id = KSZ9563_CHIP_ID, 1590 .dev_name = "KSZ9563", 1591 .num_vlans = 4096, 1592 .num_alus = 4096, 1593 .num_statics = 16, 1594 .cpu_ports = 0x07, /* can be configured as cpu port */ 1595 .port_cnt = 3, /* total port count */ 1596 .port_nirqs = 3, 1597 .num_tx_queues = 4, 1598 .num_ipms = 8, 1599 .tc_cbs_supported = true, 1600 .ops = &ksz9477_dev_ops, 1601 .switch_ops = &ksz9477_switch_ops, 1602 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1603 .mib_names = ksz9477_mib_names, 1604 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1605 .reg_mib_cnt = MIB_COUNTER_NUM, 1606 .regs = ksz9477_regs, 1607 .masks = ksz9477_masks, 1608 .shifts = ksz9477_shifts, 1609 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1610 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1611 .supports_mii = {false, false, true}, 1612 .supports_rmii = {false, false, true}, 1613 .supports_rgmii = {false, false, true}, 1614 .internal_phy = {true, true, false}, 1615 .gbit_capable = {true, true, true}, 1616 .ptp_capable = true, 1617 .n_pins = 2, 1618 .n_per_out = 3, 1619 }, 1620 1621 [KSZ8567] = { 1622 .chip_id = KSZ8567_CHIP_ID, 1623 .dev_name = "KSZ8567", 1624 .num_vlans = 4096, 1625 .num_alus = 4096, 1626 .num_statics = 16, 1627 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1628 .port_cnt = 7, /* total port count */ 1629 .port_nirqs = 3, 1630 .num_tx_queues = 4, 1631 .num_ipms = 8, 1632 .tc_cbs_supported = true, 1633 .ops = &ksz9477_dev_ops, 1634 .switch_ops = &ksz9477_switch_ops, 1635 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1636 .phy_errata_9477 = true, 1637 .mib_names = ksz9477_mib_names, 1638 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1639 .reg_mib_cnt = MIB_COUNTER_NUM, 1640 .regs = ksz9477_regs, 1641 .masks = ksz9477_masks, 1642 .shifts = ksz9477_shifts, 1643 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1644 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1645 .supports_mii = {false, false, false, false, 1646 false, true, true}, 1647 .supports_rmii = {false, false, false, false, 1648 false, true, true}, 1649 .supports_rgmii = {false, false, false, false, 1650 false, true, true}, 1651 .internal_phy = {true, true, true, true, 1652 true, false, false}, 1653 .gbit_capable = {false, false, false, false, false, 1654 true, true}, 1655 .ptp_capable = true, 1656 .n_pins = 2, 1657 .n_per_out = 3, 1658 }, 1659 1660 [KSZ9567] = { 1661 .chip_id = KSZ9567_CHIP_ID, 1662 .dev_name = "KSZ9567", 1663 .num_vlans = 4096, 1664 .num_alus = 4096, 1665 .num_statics = 16, 1666 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1667 .port_cnt = 7, /* total physical port count */ 1668 .port_nirqs = 3, 1669 .num_tx_queues = 4, 1670 .num_ipms = 8, 1671 .tc_cbs_supported = true, 1672 .ops = &ksz9477_dev_ops, 1673 .switch_ops = &ksz9477_switch_ops, 1674 .mib_names = ksz9477_mib_names, 1675 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1676 .reg_mib_cnt = MIB_COUNTER_NUM, 1677 .regs = ksz9477_regs, 1678 .masks = ksz9477_masks, 1679 .shifts = ksz9477_shifts, 1680 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1681 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1682 .supports_mii = {false, false, false, false, 1683 false, true, true}, 1684 .supports_rmii = {false, false, false, false, 1685 false, true, true}, 1686 .supports_rgmii = {false, false, false, false, 1687 false, true, true}, 1688 .internal_phy = {true, true, true, true, 1689 true, false, false}, 1690 .gbit_capable = {true, true, true, true, true, true, true}, 1691 .ptp_capable = true, 1692 .n_pins = 2, 1693 .n_per_out = 3, 1694 }, 1695 1696 [LAN9370] = { 1697 .chip_id = LAN9370_CHIP_ID, 1698 .dev_name = "LAN9370", 1699 .num_vlans = 4096, 1700 .num_alus = 1024, 1701 .num_statics = 256, 1702 .cpu_ports = 0x10, /* can be configured as cpu port */ 1703 .port_cnt = 5, /* total physical port count */ 1704 .port_nirqs = 6, 1705 .num_tx_queues = 8, 1706 .num_ipms = 8, 1707 .tc_cbs_supported = true, 1708 .phy_side_mdio_supported = true, 1709 .ops = &lan937x_dev_ops, 1710 .switch_ops = &lan937x_switch_ops, 1711 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1712 .mib_names = ksz9477_mib_names, 1713 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1714 .reg_mib_cnt = MIB_COUNTER_NUM, 1715 .regs = ksz9477_regs, 1716 .masks = lan937x_masks, 1717 .shifts = lan937x_shifts, 1718 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1719 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1720 .supports_mii = {false, false, false, false, true}, 1721 .supports_rmii = {false, false, false, false, true}, 1722 .supports_rgmii = {false, false, false, false, true}, 1723 .internal_phy = {true, true, true, true, false}, 1724 .ptp_capable = true, 1725 .n_pins = 2, 1726 .n_per_out = 3, 1727 }, 1728 1729 [LAN9371] = { 1730 .chip_id = LAN9371_CHIP_ID, 1731 .dev_name = "LAN9371", 1732 .num_vlans = 4096, 1733 .num_alus = 1024, 1734 .num_statics = 256, 1735 .cpu_ports = 0x30, /* can be configured as cpu port */ 1736 .port_cnt = 6, /* total physical port count */ 1737 .port_nirqs = 6, 1738 .num_tx_queues = 8, 1739 .num_ipms = 8, 1740 .tc_cbs_supported = true, 1741 .phy_side_mdio_supported = true, 1742 .ops = &lan937x_dev_ops, 1743 .switch_ops = &lan937x_switch_ops, 1744 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1745 .mib_names = ksz9477_mib_names, 1746 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1747 .reg_mib_cnt = MIB_COUNTER_NUM, 1748 .regs = ksz9477_regs, 1749 .masks = lan937x_masks, 1750 .shifts = lan937x_shifts, 1751 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1752 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1753 .supports_mii = {false, false, false, false, true, true}, 1754 .supports_rmii = {false, false, false, false, true, true}, 1755 .supports_rgmii = {false, false, false, false, true, true}, 1756 .internal_phy = {true, true, true, true, false, false}, 1757 .ptp_capable = true, 1758 .n_pins = 2, 1759 .n_per_out = 3, 1760 }, 1761 1762 [LAN9372] = { 1763 .chip_id = LAN9372_CHIP_ID, 1764 .dev_name = "LAN9372", 1765 .num_vlans = 4096, 1766 .num_alus = 1024, 1767 .num_statics = 256, 1768 .cpu_ports = 0x30, /* can be configured as cpu port */ 1769 .port_cnt = 8, /* total physical port count */ 1770 .port_nirqs = 6, 1771 .num_tx_queues = 8, 1772 .num_ipms = 8, 1773 .tc_cbs_supported = true, 1774 .phy_side_mdio_supported = true, 1775 .ops = &lan937x_dev_ops, 1776 .switch_ops = &lan937x_switch_ops, 1777 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1778 .mib_names = ksz9477_mib_names, 1779 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1780 .reg_mib_cnt = MIB_COUNTER_NUM, 1781 .regs = ksz9477_regs, 1782 .masks = lan937x_masks, 1783 .shifts = lan937x_shifts, 1784 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1785 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1786 .supports_mii = {false, false, false, false, 1787 true, true, false, false}, 1788 .supports_rmii = {false, false, false, false, 1789 true, true, false, false}, 1790 .supports_rgmii = {false, false, false, false, 1791 true, true, false, false}, 1792 .internal_phy = {true, true, true, true, 1793 false, false, true, true}, 1794 .ptp_capable = true, 1795 .n_pins = 2, 1796 .n_per_out = 3, 1797 }, 1798 1799 [LAN9373] = { 1800 .chip_id = LAN9373_CHIP_ID, 1801 .dev_name = "LAN9373", 1802 .num_vlans = 4096, 1803 .num_alus = 1024, 1804 .num_statics = 256, 1805 .cpu_ports = 0x38, /* can be configured as cpu port */ 1806 .port_cnt = 5, /* total physical port count */ 1807 .port_nirqs = 6, 1808 .num_tx_queues = 8, 1809 .num_ipms = 8, 1810 .tc_cbs_supported = true, 1811 .phy_side_mdio_supported = true, 1812 .ops = &lan937x_dev_ops, 1813 .switch_ops = &lan937x_switch_ops, 1814 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1815 .mib_names = ksz9477_mib_names, 1816 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1817 .reg_mib_cnt = MIB_COUNTER_NUM, 1818 .regs = ksz9477_regs, 1819 .masks = lan937x_masks, 1820 .shifts = lan937x_shifts, 1821 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1822 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1823 .supports_mii = {false, false, false, false, 1824 true, true, false, false}, 1825 .supports_rmii = {false, false, false, false, 1826 true, true, false, false}, 1827 .supports_rgmii = {false, false, false, false, 1828 true, true, false, false}, 1829 .internal_phy = {true, true, true, false, 1830 false, false, true, true}, 1831 .ptp_capable = true, 1832 .n_pins = 2, 1833 .n_per_out = 3, 1834 }, 1835 1836 [LAN9374] = { 1837 .chip_id = LAN9374_CHIP_ID, 1838 .dev_name = "LAN9374", 1839 .num_vlans = 4096, 1840 .num_alus = 1024, 1841 .num_statics = 256, 1842 .cpu_ports = 0x30, /* can be configured as cpu port */ 1843 .port_cnt = 8, /* total physical port count */ 1844 .port_nirqs = 6, 1845 .num_tx_queues = 8, 1846 .num_ipms = 8, 1847 .tc_cbs_supported = true, 1848 .phy_side_mdio_supported = true, 1849 .ops = &lan937x_dev_ops, 1850 .switch_ops = &lan937x_switch_ops, 1851 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1852 .mib_names = ksz9477_mib_names, 1853 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1854 .reg_mib_cnt = MIB_COUNTER_NUM, 1855 .regs = ksz9477_regs, 1856 .masks = lan937x_masks, 1857 .shifts = lan937x_shifts, 1858 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1859 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1860 .supports_mii = {false, false, false, false, 1861 true, true, false, false}, 1862 .supports_rmii = {false, false, false, false, 1863 true, true, false, false}, 1864 .supports_rgmii = {false, false, false, false, 1865 true, true, false, false}, 1866 .internal_phy = {true, true, true, true, 1867 false, false, true, true}, 1868 .ptp_capable = true, 1869 .n_pins = 2, 1870 .n_per_out = 3, 1871 }, 1872 1873 [LAN9646] = { 1874 .chip_id = LAN9646_CHIP_ID, 1875 .dev_name = "LAN9646", 1876 .num_vlans = 4096, 1877 .num_alus = 4096, 1878 .num_statics = 16, 1879 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1880 .port_cnt = 7, /* total physical port count */ 1881 .port_nirqs = 4, 1882 .num_tx_queues = 4, 1883 .num_ipms = 8, 1884 .ops = &ksz9477_dev_ops, 1885 .switch_ops = &ksz9477_switch_ops, 1886 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1887 .phy_errata_9477 = true, 1888 .mib_names = ksz9477_mib_names, 1889 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1890 .reg_mib_cnt = MIB_COUNTER_NUM, 1891 .regs = ksz9477_regs, 1892 .masks = ksz9477_masks, 1893 .shifts = ksz9477_shifts, 1894 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1895 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1896 .supports_mii = {false, false, false, false, 1897 false, true, true}, 1898 .supports_rmii = {false, false, false, false, 1899 false, true, true}, 1900 .supports_rgmii = {false, false, false, false, 1901 false, true, true}, 1902 .internal_phy = {true, true, true, true, 1903 true, false, false}, 1904 .gbit_capable = {true, true, true, true, true, true, true}, 1905 .sgmii_port = 7, 1906 .wr_table = &ksz9477_register_set, 1907 .rd_table = &ksz9477_register_set, 1908 }, 1909 }; 1910 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1911 1912 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1913 { 1914 int i; 1915 1916 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1917 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1918 1919 if (chip->chip_id == prod_num) 1920 return chip; 1921 } 1922 1923 return NULL; 1924 } 1925 1926 static int ksz_check_device_id(struct ksz_device *dev) 1927 { 1928 const struct ksz_chip_data *expected_chip_data; 1929 u32 expected_chip_id; 1930 1931 if (dev->pdata) { 1932 expected_chip_id = dev->pdata->chip_id; 1933 expected_chip_data = ksz_lookup_info(expected_chip_id); 1934 if (WARN_ON(!expected_chip_data)) 1935 return -ENODEV; 1936 } else { 1937 expected_chip_data = of_device_get_match_data(dev->dev); 1938 expected_chip_id = expected_chip_data->chip_id; 1939 } 1940 1941 if (expected_chip_id != dev->chip_id) { 1942 dev_err(dev->dev, 1943 "Device tree specifies chip %s but found %s, please fix it!\n", 1944 expected_chip_data->dev_name, dev->info->dev_name); 1945 return -ENODEV; 1946 } 1947 1948 return 0; 1949 } 1950 1951 void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1952 struct phylink_config *config) 1953 { 1954 struct ksz_device *dev = ds->priv; 1955 1956 if (dev->info->supports_mii[port]) 1957 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1958 1959 if (dev->info->supports_rmii[port]) 1960 __set_bit(PHY_INTERFACE_MODE_RMII, 1961 config->supported_interfaces); 1962 1963 if (dev->info->supports_rgmii[port]) 1964 phy_interface_set_rgmii(config->supported_interfaces); 1965 1966 if (dev->info->internal_phy[port]) { 1967 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1968 config->supported_interfaces); 1969 /* Compatibility for phylib's default interface type when the 1970 * phy-mode property is absent 1971 */ 1972 __set_bit(PHY_INTERFACE_MODE_GMII, 1973 config->supported_interfaces); 1974 } 1975 1976 if (ds->ops->support_eee && ds->ops->support_eee(ds, port)) { 1977 memcpy(config->lpi_interfaces, config->supported_interfaces, 1978 sizeof(config->lpi_interfaces)); 1979 1980 config->lpi_capabilities = MAC_100FD; 1981 if (dev->info->gbit_capable[port]) 1982 config->lpi_capabilities |= MAC_1000FD; 1983 1984 /* EEE is fully operational */ 1985 config->eee_enabled_default = true; 1986 } 1987 } 1988 1989 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 1990 { 1991 struct ethtool_pause_stats *pstats; 1992 struct rtnl_link_stats64 *stats; 1993 struct ksz_stats_raw *raw; 1994 struct ksz_port_mib *mib; 1995 1996 mib = &dev->ports[port].mib; 1997 stats = &mib->stats64; 1998 pstats = &mib->pause_stats; 1999 raw = (struct ksz_stats_raw *)mib->counters; 2000 2001 spin_lock(&mib->stats64_lock); 2002 2003 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 2004 raw->rx_pause; 2005 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2006 raw->tx_pause; 2007 2008 /* HW counters are counting bytes + FCS which is not acceptable 2009 * for rtnl_link_stats64 interface 2010 */ 2011 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 2012 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 2013 2014 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2015 raw->rx_oversize; 2016 2017 stats->rx_crc_errors = raw->rx_crc_err; 2018 stats->rx_frame_errors = raw->rx_align_err; 2019 stats->rx_dropped = raw->rx_discards; 2020 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2021 stats->rx_frame_errors + stats->rx_dropped; 2022 2023 stats->tx_window_errors = raw->tx_late_col; 2024 stats->tx_fifo_errors = raw->tx_discards; 2025 stats->tx_aborted_errors = raw->tx_exc_col; 2026 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2027 stats->tx_aborted_errors; 2028 2029 stats->multicast = raw->rx_mcast; 2030 stats->collisions = raw->tx_total_col; 2031 2032 pstats->tx_pause_frames = raw->tx_pause; 2033 pstats->rx_pause_frames = raw->rx_pause; 2034 2035 spin_unlock(&mib->stats64_lock); 2036 } 2037 2038 void ksz_get_stats64(struct dsa_switch *ds, int port, 2039 struct rtnl_link_stats64 *s) 2040 { 2041 struct ksz_device *dev = ds->priv; 2042 struct ksz_port_mib *mib; 2043 2044 mib = &dev->ports[port].mib; 2045 2046 spin_lock(&mib->stats64_lock); 2047 memcpy(s, &mib->stats64, sizeof(*s)); 2048 spin_unlock(&mib->stats64_lock); 2049 } 2050 2051 void ksz_get_pause_stats(struct dsa_switch *ds, int port, 2052 struct ethtool_pause_stats *pause_stats) 2053 { 2054 struct ksz_device *dev = ds->priv; 2055 struct ksz_port_mib *mib; 2056 2057 mib = &dev->ports[port].mib; 2058 2059 spin_lock(&mib->stats64_lock); 2060 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 2061 spin_unlock(&mib->stats64_lock); 2062 } 2063 2064 void ksz_get_strings(struct dsa_switch *ds, int port, 2065 u32 stringset, uint8_t *buf) 2066 { 2067 struct ksz_device *dev = ds->priv; 2068 int i; 2069 2070 if (stringset != ETH_SS_STATS) 2071 return; 2072 2073 for (i = 0; i < dev->info->mib_cnt; i++) 2074 ethtool_puts(&buf, dev->info->mib_names[i].string); 2075 } 2076 2077 /** 2078 * ksz_update_port_member - Adjust port forwarding rules based on STP state and 2079 * isolation settings. 2080 * @dev: A pointer to the struct ksz_device representing the device. 2081 * @port: The port number to adjust. 2082 * 2083 * This function dynamically adjusts the port membership configuration for a 2084 * specified port and other device ports, based on Spanning Tree Protocol (STP) 2085 * states and port isolation settings. Each port, including the CPU port, has a 2086 * membership register, represented as a bitfield, where each bit corresponds 2087 * to a port number. A set bit indicates permission to forward frames to that 2088 * port. This function iterates over all ports, updating the membership register 2089 * to reflect current forwarding permissions: 2090 * 2091 * 1. Forwards frames only to ports that are part of the same bridge group and 2092 * in the BR_STATE_FORWARDING state. 2093 * 2. Takes into account the isolation status of ports; ports in the 2094 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward 2095 * frames to each other, even if they are in the same bridge group. 2096 * 3. Ensures that the CPU port is included in the membership based on its 2097 * upstream port configuration, allowing for management and control traffic 2098 * to flow as required. 2099 */ 2100 static void ksz_update_port_member(struct ksz_device *dev, int port) 2101 { 2102 struct ksz_port *p = &dev->ports[port]; 2103 struct dsa_switch *ds = dev->ds; 2104 u8 port_member = 0, cpu_port; 2105 const struct dsa_port *dp; 2106 int i, j; 2107 2108 if (!dsa_is_user_port(ds, port)) 2109 return; 2110 2111 dp = dsa_to_port(ds, port); 2112 cpu_port = BIT(dsa_upstream_port(ds, port)); 2113 2114 for (i = 0; i < ds->num_ports; i++) { 2115 const struct dsa_port *other_dp = dsa_to_port(ds, i); 2116 struct ksz_port *other_p = &dev->ports[i]; 2117 u8 val = 0; 2118 2119 if (!dsa_is_user_port(ds, i)) 2120 continue; 2121 if (port == i) 2122 continue; 2123 if (!dsa_port_bridge_same(dp, other_dp)) 2124 continue; 2125 if (other_p->stp_state != BR_STATE_FORWARDING) 2126 continue; 2127 2128 /* At this point we know that "port" and "other" port [i] are in 2129 * the same bridge group and that "other" port [i] is in 2130 * forwarding stp state. If "port" is also in forwarding stp 2131 * state, we can allow forwarding from port [port] to port [i]. 2132 * Except if both ports are isolated. 2133 */ 2134 if (p->stp_state == BR_STATE_FORWARDING && 2135 !(p->isolated && other_p->isolated)) { 2136 val |= BIT(port); 2137 port_member |= BIT(i); 2138 } 2139 2140 /* Retain port [i]'s relationship to other ports than [port] */ 2141 for (j = 0; j < ds->num_ports; j++) { 2142 const struct dsa_port *third_dp; 2143 struct ksz_port *third_p; 2144 2145 if (j == i) 2146 continue; 2147 if (j == port) 2148 continue; 2149 if (!dsa_is_user_port(ds, j)) 2150 continue; 2151 third_p = &dev->ports[j]; 2152 if (third_p->stp_state != BR_STATE_FORWARDING) 2153 continue; 2154 2155 third_dp = dsa_to_port(ds, j); 2156 2157 /* Now we updating relation of the "other" port [i] to 2158 * the "third" port [j]. We already know that "other" 2159 * port [i] is in forwarding stp state and that "third" 2160 * port [j] is in forwarding stp state too. 2161 * We need to check if "other" port [i] and "third" port 2162 * [j] are in the same bridge group and not isolated 2163 * before allowing forwarding from port [i] to port [j]. 2164 */ 2165 if (dsa_port_bridge_same(other_dp, third_dp) && 2166 !(other_p->isolated && third_p->isolated)) 2167 val |= BIT(j); 2168 } 2169 2170 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 2171 } 2172 2173 /* HSR ports are setup once so need to use the assigned membership 2174 * when the port is enabled. 2175 */ 2176 if (!port_member && p->stp_state == BR_STATE_FORWARDING && 2177 (dev->hsr_ports & BIT(port))) 2178 port_member = dev->hsr_ports; 2179 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 2180 } 2181 2182 int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 2183 { 2184 struct ksz_device *dev = bus->priv; 2185 struct dsa_switch *ds = dev->ds; 2186 2187 return ds->ops->phy_read(ds, addr, regnum); 2188 } 2189 2190 int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val) 2191 { 2192 struct ksz_device *dev = bus->priv; 2193 struct dsa_switch *ds = dev->ds; 2194 2195 return ds->ops->phy_write(ds, addr, regnum, val); 2196 } 2197 2198 /** 2199 * ksz_parent_mdio_read - Read data from a PHY register on the parent MDIO bus. 2200 * @bus: MDIO bus structure. 2201 * @addr: PHY address on the parent MDIO bus. 2202 * @regnum: Register number to read. 2203 * 2204 * This function provides a direct read operation on the parent MDIO bus for 2205 * accessing PHY registers. By bypassing SPI or I2C, it uses the parent MDIO bus 2206 * to retrieve data from the PHY registers at the specified address and register 2207 * number. 2208 * 2209 * Return: Value of the PHY register, or a negative error code on failure. 2210 */ 2211 int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum) 2212 { 2213 struct ksz_device *dev = bus->priv; 2214 2215 return mdiobus_read_nested(dev->parent_mdio_bus, addr, regnum); 2216 } 2217 2218 /** 2219 * ksz_parent_mdio_write - Write data to a PHY register on the parent MDIO bus. 2220 * @bus: MDIO bus structure. 2221 * @addr: PHY address on the parent MDIO bus. 2222 * @regnum: Register number to write to. 2223 * @val: Value to write to the PHY register. 2224 * 2225 * This function provides a direct write operation on the parent MDIO bus for 2226 * accessing PHY registers. Bypassing SPI or I2C, it uses the parent MDIO bus 2227 * to modify the PHY register values at the specified address. 2228 * 2229 * Return: 0 on success, or a negative error code on failure. 2230 */ 2231 int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val) 2232 { 2233 struct ksz_device *dev = bus->priv; 2234 2235 return mdiobus_write_nested(dev->parent_mdio_bus, addr, regnum, val); 2236 } 2237 2238 /** 2239 * ksz_phy_addr_to_port - Map a PHY address to the corresponding switch port. 2240 * @dev: Pointer to device structure. 2241 * @addr: PHY address to map to a port. 2242 * 2243 * This function finds the corresponding switch port for a given PHY address by 2244 * iterating over all user ports on the device. It checks if a port's PHY 2245 * address in `phy_addr_map` matches the specified address and if the port 2246 * contains an internal PHY. If a match is found, the index of the port is 2247 * returned. 2248 * 2249 * Return: Port index on success, or -EINVAL if no matching port is found. 2250 */ 2251 static int ksz_phy_addr_to_port(struct ksz_device *dev, int addr) 2252 { 2253 struct dsa_switch *ds = dev->ds; 2254 struct dsa_port *dp; 2255 2256 dsa_switch_for_each_user_port(dp, ds) { 2257 if (dev->info->internal_phy[dp->index] && 2258 dev->phy_addr_map[dp->index] == addr) 2259 return dp->index; 2260 } 2261 2262 return -EINVAL; 2263 } 2264 2265 /** 2266 * ksz_irq_phy_setup - Configure IRQs for PHYs in the KSZ device. 2267 * @dev: Pointer to the KSZ device structure. 2268 * 2269 * Sets up IRQs for each active PHY connected to the KSZ switch by mapping the 2270 * appropriate IRQs for each PHY and assigning them to the `user_mii_bus` in 2271 * the DSA switch structure. Each IRQ is mapped based on the port's IRQ domain. 2272 * 2273 * Return: 0 on success, or a negative error code on failure. 2274 */ 2275 static int ksz_irq_phy_setup(struct ksz_device *dev) 2276 { 2277 struct dsa_switch *ds = dev->ds; 2278 int phy, port; 2279 int irq; 2280 int ret; 2281 2282 for (phy = 0; phy < PHY_MAX_ADDR; phy++) { 2283 if (BIT(phy) & ds->phys_mii_mask) { 2284 port = ksz_phy_addr_to_port(dev, phy); 2285 if (port < 0) { 2286 ret = port; 2287 goto out; 2288 } 2289 2290 irq = irq_find_mapping(dev->ports[port].pirq.domain, 2291 PORT_SRC_PHY_INT); 2292 if (!irq) { 2293 ret = -EINVAL; 2294 goto out; 2295 } 2296 ds->user_mii_bus->irq[phy] = irq; 2297 } 2298 } 2299 return 0; 2300 out: 2301 while (phy--) 2302 if (BIT(phy) & ds->phys_mii_mask) 2303 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2304 2305 return ret; 2306 } 2307 2308 /** 2309 * ksz_irq_phy_free - Release IRQ mappings for PHYs in the KSZ device. 2310 * @dev: Pointer to the KSZ device structure. 2311 * 2312 * Releases any IRQ mappings previously assigned to active PHYs in the KSZ 2313 * switch by disposing of each mapped IRQ in the `user_mii_bus` structure. 2314 */ 2315 static void ksz_irq_phy_free(struct ksz_device *dev) 2316 { 2317 struct dsa_switch *ds = dev->ds; 2318 int phy; 2319 2320 for (phy = 0; phy < PHY_MAX_ADDR; phy++) 2321 if (BIT(phy) & ds->phys_mii_mask) 2322 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2323 } 2324 2325 /** 2326 * ksz_parse_dt_phy_config - Parse and validate PHY configuration from DT 2327 * @dev: pointer to the KSZ device structure 2328 * @bus: pointer to the MII bus structure 2329 * @mdio_np: pointer to the MDIO node in the device tree 2330 * 2331 * This function parses and validates PHY configurations for each user port 2332 * defined in the device tree for a KSZ switch device. It verifies that the 2333 * `phy-handle` properties are correctly set and that the internal PHYs match 2334 * expected addresses and parent nodes. Sets up the PHY mask in the MII bus if 2335 * all validations pass. Logs error messages for any mismatches or missing data. 2336 * 2337 * Return: 0 on success, or a negative error code on failure. 2338 */ 2339 int ksz_parse_dt_phy_config(struct ksz_device *dev, struct mii_bus *bus, 2340 struct device_node *mdio_np) 2341 { 2342 struct device_node *phy_node, *phy_parent_node; 2343 bool phys_are_valid = true; 2344 struct dsa_port *dp; 2345 u32 phy_addr; 2346 int ret; 2347 2348 dsa_switch_for_each_user_port(dp, dev->ds) { 2349 if (!dev->info->internal_phy[dp->index]) 2350 continue; 2351 2352 phy_node = of_parse_phandle(dp->dn, "phy-handle", 0); 2353 if (!phy_node) { 2354 dev_err(dev->dev, "failed to parse phy-handle for port %d.\n", 2355 dp->index); 2356 phys_are_valid = false; 2357 continue; 2358 } 2359 2360 phy_parent_node = of_get_parent(phy_node); 2361 if (!phy_parent_node) { 2362 dev_err(dev->dev, "failed to get PHY-parent node for port %d\n", 2363 dp->index); 2364 phys_are_valid = false; 2365 } else if (phy_parent_node != mdio_np) { 2366 dev_err(dev->dev, "PHY-parent node mismatch for port %d, expected %pOF, got %pOF\n", 2367 dp->index, mdio_np, phy_parent_node); 2368 phys_are_valid = false; 2369 } else { 2370 ret = of_property_read_u32(phy_node, "reg", &phy_addr); 2371 if (ret < 0) { 2372 dev_err(dev->dev, "failed to read PHY address for port %d. Error %d\n", 2373 dp->index, ret); 2374 phys_are_valid = false; 2375 } else if (phy_addr != dev->phy_addr_map[dp->index]) { 2376 dev_err(dev->dev, "PHY address mismatch for port %d, expected 0x%x, got 0x%x\n", 2377 dp->index, dev->phy_addr_map[dp->index], 2378 phy_addr); 2379 phys_are_valid = false; 2380 } else { 2381 bus->phy_mask |= BIT(phy_addr); 2382 } 2383 } 2384 2385 of_node_put(phy_node); 2386 of_node_put(phy_parent_node); 2387 } 2388 2389 if (!phys_are_valid) 2390 return -EINVAL; 2391 2392 return 0; 2393 } 2394 2395 /** 2396 * ksz_mdio_register - Register and configure the MDIO bus for the KSZ device. 2397 * @dev: Pointer to the KSZ device structure. 2398 * 2399 * This function sets up and registers an MDIO bus for the KSZ switch device, 2400 * allowing access to its internal PHYs. If the device supports side MDIO, 2401 * the function will configure the external MDIO controller specified by the 2402 * "mdio-parent-bus" device tree property to directly manage internal PHYs. 2403 * Otherwise, SPI or I2C access is set up for PHY access. 2404 * 2405 * Return: 0 on success, or a negative error code on failure. 2406 */ 2407 int ksz_mdio_register(struct ksz_device *dev) 2408 { 2409 struct device_node *parent_bus_node; 2410 struct mii_bus *parent_bus = NULL; 2411 struct dsa_switch *ds = dev->ds; 2412 struct device_node *mdio_np; 2413 struct mii_bus *bus; 2414 int ret, i; 2415 2416 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 2417 if (!mdio_np) 2418 return 0; 2419 2420 parent_bus_node = of_parse_phandle(mdio_np, "mdio-parent-bus", 0); 2421 if (parent_bus_node && !dev->info->phy_side_mdio_supported) { 2422 dev_err(dev->dev, "Side MDIO bus is not supported for this HW, ignoring 'mdio-parent-bus' property.\n"); 2423 ret = -EINVAL; 2424 2425 goto put_mdio_node; 2426 } else if (parent_bus_node) { 2427 parent_bus = of_mdio_find_bus(parent_bus_node); 2428 if (!parent_bus) { 2429 ret = -EPROBE_DEFER; 2430 2431 goto put_mdio_node; 2432 } 2433 2434 dev->parent_mdio_bus = parent_bus; 2435 } 2436 2437 bus = devm_mdiobus_alloc(ds->dev); 2438 if (!bus) { 2439 ret = -ENOMEM; 2440 goto put_mdio_node; 2441 } 2442 2443 for (i = 0; i < dev->info->port_cnt; i++) 2444 dev->phy_addr_map[i] = i; 2445 2446 bus->priv = dev; 2447 if (parent_bus) { 2448 bus->read = ksz_parent_mdio_read; 2449 bus->write = ksz_parent_mdio_write; 2450 bus->name = "KSZ side MDIO"; 2451 snprintf(bus->id, MII_BUS_ID_SIZE, "ksz-side-mdio-%d", 2452 ds->index); 2453 } else { 2454 bus->read = ksz_sw_mdio_read; 2455 bus->write = ksz_sw_mdio_write; 2456 bus->name = "ksz user smi"; 2457 if (ds->dst->index != 0) { 2458 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d-%d", ds->dst->index, ds->index); 2459 } else { 2460 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 2461 } 2462 } 2463 2464 ret = ksz_parse_dt_phy_config(dev, bus, mdio_np); 2465 if (ret) 2466 goto put_mdio_node; 2467 2468 ds->phys_mii_mask = bus->phy_mask; 2469 bus->parent = ds->dev; 2470 2471 ds->user_mii_bus = bus; 2472 2473 if (dev->irq > 0) { 2474 ret = ksz_irq_phy_setup(dev); 2475 if (ret) 2476 goto put_mdio_node; 2477 } 2478 2479 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 2480 if (ret) { 2481 dev_err(ds->dev, "unable to register MDIO bus %s\n", 2482 bus->id); 2483 if (dev->irq > 0) 2484 ksz_irq_phy_free(dev); 2485 } 2486 2487 put_mdio_node: 2488 of_node_put(mdio_np); 2489 of_node_put(parent_bus_node); 2490 2491 return ret; 2492 } 2493 2494 static void ksz_irq_mask(struct irq_data *d) 2495 { 2496 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2497 2498 kirq->masked |= BIT(d->hwirq); 2499 } 2500 2501 static void ksz_irq_unmask(struct irq_data *d) 2502 { 2503 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2504 2505 kirq->masked &= ~BIT(d->hwirq); 2506 } 2507 2508 void ksz_irq_bus_lock(struct irq_data *d) 2509 { 2510 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2511 2512 mutex_lock(&kirq->dev->lock_irq); 2513 } 2514 2515 void ksz_irq_bus_sync_unlock(struct irq_data *d) 2516 { 2517 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2518 struct ksz_device *dev = kirq->dev; 2519 int ret; 2520 2521 ret = ksz_write8(dev, kirq->reg_mask, kirq->masked); 2522 if (ret) 2523 dev_err(dev->dev, "failed to change IRQ mask\n"); 2524 2525 mutex_unlock(&dev->lock_irq); 2526 } 2527 2528 static const struct irq_chip ksz_irq_chip = { 2529 .name = "ksz-irq", 2530 .irq_mask = ksz_irq_mask, 2531 .irq_unmask = ksz_irq_unmask, 2532 .irq_bus_lock = ksz_irq_bus_lock, 2533 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 2534 }; 2535 2536 static int ksz_irq_domain_map(struct irq_domain *d, 2537 unsigned int irq, irq_hw_number_t hwirq) 2538 { 2539 irq_set_chip_data(irq, d->host_data); 2540 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 2541 irq_set_noprobe(irq); 2542 2543 return 0; 2544 } 2545 2546 static const struct irq_domain_ops ksz_irq_domain_ops = { 2547 .map = ksz_irq_domain_map, 2548 .xlate = irq_domain_xlate_twocell, 2549 }; 2550 2551 void ksz_irq_free(struct ksz_irq *kirq) 2552 { 2553 int irq, virq; 2554 2555 free_irq(kirq->irq_num, kirq); 2556 2557 for (irq = 0; irq < kirq->nirqs; irq++) { 2558 virq = irq_find_mapping(kirq->domain, irq); 2559 irq_dispose_mapping(virq); 2560 } 2561 2562 irq_domain_remove(kirq->domain); 2563 } 2564 2565 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 2566 { 2567 struct ksz_irq *kirq = dev_id; 2568 unsigned int nhandled = 0; 2569 struct ksz_device *dev; 2570 unsigned int sub_irq; 2571 u8 data; 2572 int ret; 2573 u8 n; 2574 2575 dev = kirq->dev; 2576 2577 /* Read interrupt status register */ 2578 ret = ksz_read8(dev, kirq->reg_status, &data); 2579 if (ret) 2580 goto out; 2581 2582 for (n = 0; n < kirq->nirqs; ++n) { 2583 if (data & BIT(n)) { 2584 sub_irq = irq_find_mapping(kirq->domain, n); 2585 handle_nested_irq(sub_irq); 2586 ++nhandled; 2587 } 2588 } 2589 out: 2590 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2591 } 2592 2593 int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq, 2594 const struct irq_domain_ops *ops) 2595 { 2596 int ret, n; 2597 2598 kirq->dev = dev; 2599 2600 kirq->domain = irq_domain_create_simple(dev_fwnode(dev->dev), 2601 kirq->nirqs, 0, ops, kirq); 2602 if (!kirq->domain) 2603 return -ENOMEM; 2604 2605 for (n = 0; n < kirq->nirqs; n++) 2606 irq_create_mapping(kirq->domain, n); 2607 2608 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2609 IRQF_ONESHOT, kirq->name, kirq); 2610 if (ret) 2611 goto out; 2612 2613 return 0; 2614 2615 out: 2616 ksz_irq_free(kirq); 2617 2618 return ret; 2619 } 2620 2621 int ksz_girq_setup(struct ksz_device *dev) 2622 { 2623 struct ksz_irq *girq = &dev->girq; 2624 2625 girq->nirqs = dev->info->port_cnt; 2626 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2627 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2628 girq->masked = ~0; 2629 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2630 2631 girq->irq_num = dev->irq; 2632 2633 return ksz_irq_common_setup(dev, girq, &ksz_irq_domain_ops); 2634 } 2635 2636 int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2637 { 2638 struct ksz_irq *pirq = &dev->ports[p].pirq; 2639 2640 pirq->nirqs = dev->info->port_nirqs; 2641 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2642 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2643 pirq->masked = ~0; 2644 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2645 2646 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2647 if (!pirq->irq_num) 2648 return -EINVAL; 2649 2650 return ksz_irq_common_setup(dev, pirq, &ksz_irq_domain_ops); 2651 } 2652 2653 void ksz_teardown(struct dsa_switch *ds) 2654 { 2655 struct ksz_device *dev = ds->priv; 2656 struct dsa_port *dp; 2657 2658 if (dev->info->ptp_capable) 2659 ksz_ptp_clock_unregister(ds); 2660 2661 if (dev->irq > 0) { 2662 dsa_switch_for_each_user_port(dp, dev->ds) { 2663 if (dev->info->ptp_capable) 2664 ksz_ptp_irq_free(ds, dp->index); 2665 2666 ksz_irq_free(&dev->ports[dp->index].pirq); 2667 } 2668 2669 ksz_irq_free(&dev->girq); 2670 } 2671 } 2672 2673 static void port_r_cnt(struct ksz_device *dev, int port) 2674 { 2675 struct ksz_port_mib *mib = &dev->ports[port].mib; 2676 u64 *dropped; 2677 2678 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2679 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2680 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2681 &mib->counters[mib->cnt_ptr]); 2682 ++mib->cnt_ptr; 2683 } 2684 2685 /* last one in storage */ 2686 dropped = &mib->counters[dev->info->mib_cnt]; 2687 2688 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2689 while (mib->cnt_ptr < dev->info->mib_cnt) { 2690 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2691 dropped, &mib->counters[mib->cnt_ptr]); 2692 ++mib->cnt_ptr; 2693 } 2694 mib->cnt_ptr = 0; 2695 } 2696 2697 static void ksz_mib_read_work(struct work_struct *work) 2698 { 2699 struct ksz_device *dev = container_of(work, struct ksz_device, 2700 mib_read.work); 2701 struct ksz_port_mib *mib; 2702 struct ksz_port *p; 2703 int i; 2704 2705 for (i = 0; i < dev->info->port_cnt; i++) { 2706 if (dsa_is_unused_port(dev->ds, i)) 2707 continue; 2708 2709 p = &dev->ports[i]; 2710 mib = &p->mib; 2711 mutex_lock(&mib->cnt_mutex); 2712 2713 /* Only read MIB counters when the port is told to do. 2714 * If not, read only dropped counters when link is not up. 2715 */ 2716 if (!p->read) { 2717 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 2718 2719 if (!netif_carrier_ok(dp->user)) 2720 mib->cnt_ptr = dev->info->reg_mib_cnt; 2721 } 2722 port_r_cnt(dev, i); 2723 p->read = false; 2724 2725 if (dev->dev_ops->r_mib_stat64) 2726 dev->dev_ops->r_mib_stat64(dev, i); 2727 2728 mutex_unlock(&mib->cnt_mutex); 2729 } 2730 2731 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 2732 } 2733 2734 void ksz_init_mib_timer(struct ksz_device *dev) 2735 { 2736 int i; 2737 2738 /* KSZ8995XA lacks MiB features */ 2739 if (ksz_is_ksz8995xa(dev)) 2740 return; 2741 2742 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 2743 2744 for (i = 0; i < dev->info->port_cnt; i++) { 2745 struct ksz_port_mib *mib = &dev->ports[i].mib; 2746 2747 dev->dev_ops->port_init_cnt(dev, i); 2748 2749 mib->cnt_ptr = 0; 2750 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 2751 } 2752 } 2753 2754 void ksz_phylink_mac_link_down(struct phylink_config *config, 2755 unsigned int mode, 2756 phy_interface_t interface) 2757 { 2758 struct dsa_port *dp = dsa_phylink_to_port(config); 2759 struct ksz_device *dev = dp->ds->priv; 2760 2761 /* Read all MIB counters when the link is going down. */ 2762 dev->ports[dp->index].read = true; 2763 /* timer started */ 2764 if (dev->mib_read_interval) 2765 schedule_delayed_work(&dev->mib_read, 0); 2766 } 2767 2768 int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 2769 { 2770 struct ksz_device *dev = ds->priv; 2771 2772 if (sset != ETH_SS_STATS) 2773 return 0; 2774 2775 return dev->info->mib_cnt; 2776 } 2777 2778 void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 2779 uint64_t *buf) 2780 { 2781 const struct dsa_port *dp = dsa_to_port(ds, port); 2782 struct ksz_device *dev = ds->priv; 2783 struct ksz_port_mib *mib; 2784 2785 mib = &dev->ports[port].mib; 2786 mutex_lock(&mib->cnt_mutex); 2787 2788 /* Only read dropped counters if no link. */ 2789 if (!netif_carrier_ok(dp->user)) 2790 mib->cnt_ptr = dev->info->reg_mib_cnt; 2791 port_r_cnt(dev, port); 2792 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 2793 mutex_unlock(&mib->cnt_mutex); 2794 } 2795 2796 int ksz_port_bridge_join(struct dsa_switch *ds, int port, 2797 struct dsa_bridge bridge, 2798 bool *tx_fwd_offload, 2799 struct netlink_ext_ack *extack) 2800 { 2801 /* port_stp_state_set() will be called after to put the port in 2802 * appropriate state so there is no need to do anything. 2803 */ 2804 2805 return 0; 2806 } 2807 2808 void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 2809 struct dsa_bridge bridge) 2810 { 2811 /* port_stp_state_set() will be called after to put the port in 2812 * forwarding state so there is no need to do anything. 2813 */ 2814 } 2815 2816 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 2817 { 2818 struct ksz_device *dev = ds->priv; 2819 struct ksz_port *p; 2820 const u16 *regs; 2821 u8 data; 2822 2823 regs = dev->info->regs; 2824 2825 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 2826 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2827 2828 p = &dev->ports[port]; 2829 2830 switch (state) { 2831 case BR_STATE_DISABLED: 2832 data |= PORT_LEARN_DISABLE; 2833 break; 2834 case BR_STATE_LISTENING: 2835 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2836 break; 2837 case BR_STATE_LEARNING: 2838 data |= PORT_RX_ENABLE; 2839 if (!p->learning) 2840 data |= PORT_LEARN_DISABLE; 2841 break; 2842 case BR_STATE_FORWARDING: 2843 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 2844 if (!p->learning) 2845 data |= PORT_LEARN_DISABLE; 2846 break; 2847 case BR_STATE_BLOCKING: 2848 data |= PORT_LEARN_DISABLE; 2849 break; 2850 default: 2851 dev_err(ds->dev, "invalid STP state: %d\n", state); 2852 return; 2853 } 2854 2855 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 2856 2857 p->stp_state = state; 2858 2859 ksz_update_port_member(dev, port); 2860 } 2861 2862 int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 2863 struct switchdev_brport_flags flags, 2864 struct netlink_ext_ack *extack) 2865 { 2866 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED)) 2867 return -EINVAL; 2868 2869 return 0; 2870 } 2871 2872 int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 2873 struct switchdev_brport_flags flags, 2874 struct netlink_ext_ack *extack) 2875 { 2876 struct ksz_device *dev = ds->priv; 2877 struct ksz_port *p = &dev->ports[port]; 2878 2879 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) { 2880 if (flags.mask & BR_LEARNING) 2881 p->learning = !!(flags.val & BR_LEARNING); 2882 2883 if (flags.mask & BR_ISOLATED) 2884 p->isolated = !!(flags.val & BR_ISOLATED); 2885 2886 /* Make the change take effect immediately */ 2887 ksz_port_stp_state_set(ds, port, p->stp_state); 2888 } 2889 2890 return 0; 2891 } 2892 2893 int ksz_set_mac_eee(struct dsa_switch *ds, int port, 2894 struct ethtool_keee *e) 2895 { 2896 struct ksz_device *dev = ds->priv; 2897 2898 if (!e->tx_lpi_enabled) { 2899 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 2900 return -EINVAL; 2901 } 2902 2903 if (e->tx_lpi_timer) { 2904 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 2905 return -EINVAL; 2906 } 2907 2908 return 0; 2909 } 2910 2911 void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface) 2912 { 2913 const u8 *bitval = dev->info->xmii_ctrl1; 2914 struct ksz_port *p = &dev->ports[port]; 2915 const u16 *regs = dev->info->regs; 2916 u8 data8; 2917 2918 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2919 2920 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 2921 P_RGMII_ID_EG_ENABLE); 2922 2923 switch (interface) { 2924 case PHY_INTERFACE_MODE_MII: 2925 data8 |= bitval[P_MII_SEL]; 2926 break; 2927 case PHY_INTERFACE_MODE_RMII: 2928 data8 |= bitval[P_RMII_SEL]; 2929 break; 2930 case PHY_INTERFACE_MODE_GMII: 2931 data8 |= bitval[P_GMII_SEL]; 2932 break; 2933 case PHY_INTERFACE_MODE_RGMII: 2934 case PHY_INTERFACE_MODE_RGMII_ID: 2935 case PHY_INTERFACE_MODE_RGMII_TXID: 2936 case PHY_INTERFACE_MODE_RGMII_RXID: 2937 data8 |= bitval[P_RGMII_SEL]; 2938 /* On KSZ9893, disable RGMII in-band status support */ 2939 if (dev->chip_id == KSZ9893_CHIP_ID || 2940 dev->chip_id == KSZ8563_CHIP_ID || 2941 dev->chip_id == KSZ9563_CHIP_ID || 2942 is_lan937x(dev)) 2943 data8 &= ~P_MII_MAC_MODE; 2944 break; 2945 default: 2946 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 2947 phy_modes(interface), port); 2948 return; 2949 } 2950 2951 if (p->rgmii_tx_val) 2952 data8 |= P_RGMII_ID_EG_ENABLE; 2953 2954 if (p->rgmii_rx_val) 2955 data8 |= P_RGMII_ID_IG_ENABLE; 2956 2957 /* Write the updated value */ 2958 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2959 } 2960 2961 bool ksz_phylink_need_config(struct phylink_config *config, 2962 unsigned int mode) 2963 { 2964 struct dsa_port *dp = dsa_phylink_to_port(config); 2965 struct ksz_device *dev = dp->ds->priv; 2966 int port = dp->index; 2967 2968 /* Internal PHYs */ 2969 if (dev->info->internal_phy[port]) 2970 return false; 2971 2972 /* No need to configure XMII control register when using SGMII. */ 2973 if (ksz_is_sgmii_port(dev, port)) 2974 return false; 2975 2976 if (phylink_autoneg_inband(mode)) { 2977 dev_err(dev->dev, "In-band AN not supported!\n"); 2978 return false; 2979 } 2980 2981 return true; 2982 } 2983 2984 void ksz_phylink_mac_config(struct phylink_config *config, 2985 unsigned int mode, 2986 const struct phylink_link_state *state) 2987 { 2988 struct dsa_port *dp = dsa_phylink_to_port(config); 2989 struct ksz_device *dev = dp->ds->priv; 2990 int port = dp->index; 2991 2992 if (ksz_phylink_need_config(config, mode)) 2993 ksz_set_xmii(dev, port, state->interface); 2994 } 2995 2996 static int ksz_switch_detect(struct ksz_device *dev) 2997 { 2998 u8 id1, id2, id4; 2999 u16 id16; 3000 u32 id32; 3001 int ret; 3002 3003 /* read chip id */ 3004 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 3005 if (ret) 3006 return ret; 3007 3008 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 3009 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 3010 3011 switch (id1) { 3012 case KSZ84_FAMILY_ID: 3013 dev->chip_id = KSZ8463_CHIP_ID; 3014 break; 3015 case KSZ87_FAMILY_ID: 3016 if (id2 == KSZ87_CHIP_ID_95) { 3017 u8 val; 3018 3019 dev->chip_id = KSZ8795_CHIP_ID; 3020 3021 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 3022 if (val & KSZ8_PORT_FIBER_MODE) 3023 dev->chip_id = KSZ8765_CHIP_ID; 3024 } else if (id2 == KSZ87_CHIP_ID_94) { 3025 dev->chip_id = KSZ8794_CHIP_ID; 3026 } else { 3027 return -ENODEV; 3028 } 3029 break; 3030 case KSZ88_FAMILY_ID: 3031 if (id2 == KSZ88_CHIP_ID_63) 3032 dev->chip_id = KSZ88X3_CHIP_ID; 3033 else 3034 return -ENODEV; 3035 break; 3036 case KSZ8895_FAMILY_ID: 3037 if (id2 == KSZ8895_CHIP_ID_95XA) { 3038 dev->chip_id = KSZ8995XA_CHIP_ID; 3039 break; 3040 } else if (id2 == KSZ8895_CHIP_ID_95 || 3041 id2 == KSZ8895_CHIP_ID_95R) { 3042 dev->chip_id = KSZ8895_CHIP_ID; 3043 } else { 3044 return -ENODEV; 3045 } 3046 ret = ksz_read8(dev, REG_KSZ8864_CHIP_ID, &id4); 3047 if (ret) 3048 return ret; 3049 if (id4 & SW_KSZ8864) 3050 dev->chip_id = KSZ8864_CHIP_ID; 3051 break; 3052 default: 3053 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 3054 if (ret) 3055 return ret; 3056 3057 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 3058 id32 &= ~0xFF; 3059 3060 switch (id32) { 3061 case KSZ9477_CHIP_ID: 3062 case KSZ9896_CHIP_ID: 3063 case KSZ9897_CHIP_ID: 3064 case KSZ9567_CHIP_ID: 3065 case KSZ8567_CHIP_ID: 3066 case LAN9370_CHIP_ID: 3067 case LAN9371_CHIP_ID: 3068 case LAN9372_CHIP_ID: 3069 case LAN9373_CHIP_ID: 3070 case LAN9374_CHIP_ID: 3071 3072 /* LAN9646 does not have its own chip id. */ 3073 if (dev->chip_id != LAN9646_CHIP_ID) 3074 dev->chip_id = id32; 3075 break; 3076 case KSZ9893_CHIP_ID: 3077 ret = ksz_read8(dev, REG_CHIP_ID4, 3078 &id4); 3079 if (ret) 3080 return ret; 3081 3082 if (id4 == SKU_ID_KSZ8563) 3083 dev->chip_id = KSZ8563_CHIP_ID; 3084 else if (id4 == SKU_ID_KSZ9563) 3085 dev->chip_id = KSZ9563_CHIP_ID; 3086 else 3087 dev->chip_id = KSZ9893_CHIP_ID; 3088 3089 break; 3090 default: 3091 dev_err(dev->dev, 3092 "unsupported switch detected (0x%x)\n", id32); 3093 return -ENODEV; 3094 } 3095 } 3096 return 0; 3097 } 3098 3099 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 3100 * is converted to Hex-decimal using the successive multiplication method. On 3101 * every step, integer part is taken and decimal part is carry forwarded. 3102 */ 3103 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 3104 { 3105 u32 cinc = 0; 3106 u32 txrate; 3107 u32 rate; 3108 u8 temp; 3109 u8 i; 3110 3111 txrate = idle_slope - send_slope; 3112 3113 if (!txrate) 3114 return -EINVAL; 3115 3116 rate = idle_slope; 3117 3118 /* 24 bit register */ 3119 for (i = 0; i < 6; i++) { 3120 rate = rate * 16; 3121 3122 temp = rate / txrate; 3123 3124 rate %= txrate; 3125 3126 cinc = ((cinc << 4) | temp); 3127 } 3128 3129 *bw = cinc; 3130 3131 return 0; 3132 } 3133 3134 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 3135 u8 shaper) 3136 { 3137 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 3138 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 3139 FIELD_PREP(MTI_SHAPING_M, shaper)); 3140 } 3141 3142 int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 3143 struct tc_cbs_qopt_offload *qopt) 3144 { 3145 struct ksz_device *dev = ds->priv; 3146 int ret; 3147 u32 bw; 3148 3149 if (!dev->info->tc_cbs_supported) 3150 return -EOPNOTSUPP; 3151 3152 if (qopt->queue > dev->info->num_tx_queues) 3153 return -EINVAL; 3154 3155 /* Queue Selection */ 3156 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 3157 if (ret) 3158 return ret; 3159 3160 if (!qopt->enable) 3161 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3162 MTI_SHAPING_OFF); 3163 3164 /* High Credit */ 3165 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 3166 qopt->hicredit); 3167 if (ret) 3168 return ret; 3169 3170 /* Low Credit */ 3171 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 3172 qopt->locredit); 3173 if (ret) 3174 return ret; 3175 3176 /* Credit Increment Register */ 3177 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 3178 if (ret) 3179 return ret; 3180 3181 if (dev->dev_ops->tc_cbs_set_cinc) { 3182 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 3183 if (ret) 3184 return ret; 3185 } 3186 3187 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3188 MTI_SHAPING_SRP); 3189 } 3190 3191 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 3192 { 3193 int queue, ret; 3194 3195 /* Configuration will not take effect until the last Port Queue X 3196 * Egress Limit Control Register is written. 3197 */ 3198 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3199 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 3200 KSZ9477_OUT_RATE_NO_LIMIT); 3201 if (ret) 3202 return ret; 3203 } 3204 3205 return 0; 3206 } 3207 3208 int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 3209 int band) 3210 { 3211 /* Compared to queues, bands prioritize packets differently. In strict 3212 * priority mode, the lowest priority is assigned to Queue 0 while the 3213 * highest priority is given to Band 0. 3214 */ 3215 return p->bands - 1 - band; 3216 } 3217 3218 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 3219 { 3220 int ret; 3221 3222 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3223 if (ret) 3224 return ret; 3225 3226 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3227 MTI_SHAPING_OFF); 3228 } 3229 3230 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 3231 int weight) 3232 { 3233 int ret; 3234 3235 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3236 if (ret) 3237 return ret; 3238 3239 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3240 MTI_SHAPING_OFF); 3241 if (ret) 3242 return ret; 3243 3244 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 3245 } 3246 3247 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 3248 struct tc_ets_qopt_offload_replace_params *p) 3249 { 3250 int ret, band, tc_prio; 3251 u32 queue_map = 0; 3252 3253 /* In order to ensure proper prioritization, it is necessary to set the 3254 * rate limit for the related queue to zero. Otherwise strict priority 3255 * or WRR mode will not work. This is a hardware limitation. 3256 */ 3257 ret = ksz_disable_egress_rate_limit(dev, port); 3258 if (ret) 3259 return ret; 3260 3261 /* Configure queue scheduling mode for all bands. Currently only strict 3262 * prio mode is supported. 3263 */ 3264 for (band = 0; band < p->bands; band++) { 3265 int queue = ksz_ets_band_to_queue(p, band); 3266 3267 ret = ksz_queue_set_strict(dev, port, queue); 3268 if (ret) 3269 return ret; 3270 } 3271 3272 /* Configure the mapping between traffic classes and queues. Note: 3273 * priomap variable support 16 traffic classes, but the chip can handle 3274 * only 8 classes. 3275 */ 3276 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 3277 int queue; 3278 3279 if (tc_prio >= dev->info->num_ipms) 3280 break; 3281 3282 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 3283 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3284 } 3285 3286 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3287 } 3288 3289 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 3290 { 3291 int ret, queue; 3292 3293 /* To restore the default chip configuration, set all queues to use the 3294 * WRR scheduler with a weight of 1. 3295 */ 3296 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3297 ret = ksz_queue_set_wrr(dev, port, queue, 3298 KSZ9477_DEFAULT_WRR_WEIGHT); 3299 3300 if (ret) 3301 return ret; 3302 } 3303 3304 /* Revert the queue mapping for TC-priority to its default setting on 3305 * the chip. 3306 */ 3307 return ksz9477_set_default_prio_queue_mapping(dev, port); 3308 } 3309 3310 int ksz_tc_ets_validate(struct ksz_device *dev, int port, 3311 struct tc_ets_qopt_offload_replace_params *p) 3312 { 3313 int band; 3314 3315 /* Since it is not feasible to share one port among multiple qdisc, 3316 * the user must configure all available queues appropriately. 3317 */ 3318 if (p->bands != dev->info->num_tx_queues) { 3319 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 3320 dev->info->num_tx_queues); 3321 return -EOPNOTSUPP; 3322 } 3323 3324 for (band = 0; band < p->bands; ++band) { 3325 /* The KSZ switches utilize a weighted round robin configuration 3326 * where a certain number of packets can be transmitted from a 3327 * queue before the next queue is serviced. For more information 3328 * on this, refer to section 5.2.8.4 of the KSZ8565R 3329 * documentation on the Port Transmit Queue Control 1 Register. 3330 * However, the current ETS Qdisc implementation (as of February 3331 * 2023) assigns a weight to each queue based on the number of 3332 * bytes or extrapolated bandwidth in percentages. Since this 3333 * differs from the KSZ switches' method and we don't want to 3334 * fake support by converting bytes to packets, it is better to 3335 * return an error instead. 3336 */ 3337 if (p->quanta[band]) { 3338 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 3339 return -EOPNOTSUPP; 3340 } 3341 } 3342 3343 return 0; 3344 } 3345 3346 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 3347 struct tc_ets_qopt_offload *qopt) 3348 { 3349 struct ksz_device *dev = ds->priv; 3350 int ret; 3351 3352 if (qopt->parent != TC_H_ROOT) { 3353 dev_err(dev->dev, "Parent should be \"root\"\n"); 3354 return -EOPNOTSUPP; 3355 } 3356 3357 switch (qopt->command) { 3358 case TC_ETS_REPLACE: 3359 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 3360 if (ret) 3361 return ret; 3362 3363 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 3364 case TC_ETS_DESTROY: 3365 return ksz_tc_ets_del(dev, port); 3366 case TC_ETS_STATS: 3367 case TC_ETS_GRAFT: 3368 return -EOPNOTSUPP; 3369 } 3370 3371 return -EOPNOTSUPP; 3372 } 3373 3374 int ksz_setup_tc(struct dsa_switch *ds, int port, 3375 enum tc_setup_type type, void *type_data) 3376 { 3377 switch (type) { 3378 case TC_SETUP_QDISC_CBS: 3379 return ksz_setup_tc_cbs(ds, port, type_data); 3380 case TC_SETUP_QDISC_ETS: 3381 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 3382 default: 3383 return -EOPNOTSUPP; 3384 } 3385 } 3386 3387 /** 3388 * ksz_handle_wake_reason - Handle wake reason on a specified port. 3389 * @dev: The device structure. 3390 * @port: The port number. 3391 * 3392 * This function reads the PME (Power Management Event) status register of a 3393 * specified port to determine the wake reason. If there is no wake event, it 3394 * returns early. Otherwise, it logs the wake reason which could be due to a 3395 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register 3396 * is then cleared to acknowledge the handling of the wake event. 3397 * 3398 * Return: 0 on success, or an error code on failure. 3399 */ 3400 int ksz_handle_wake_reason(struct ksz_device *dev, int port) 3401 { 3402 const struct ksz_dev_ops *ops = dev->dev_ops; 3403 const u16 *regs = dev->info->regs; 3404 u8 pme_status; 3405 int ret; 3406 3407 ret = ops->pme_pread8(dev, port, regs[REG_PORT_PME_STATUS], 3408 &pme_status); 3409 if (ret) 3410 return ret; 3411 3412 if (!pme_status) 3413 return 0; 3414 3415 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port, 3416 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "", 3417 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "", 3418 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : ""); 3419 3420 return ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_STATUS], 3421 pme_status); 3422 } 3423 3424 /** 3425 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port 3426 * can be used as a global address. 3427 * @ds: Pointer to the DSA switch structure. 3428 * @port: The port number on which the MAC address is to be checked. 3429 * 3430 * This function examines the MAC address set on the specified port and 3431 * determines if it can be used as a global address for the switch. 3432 * 3433 * Return: true if the port's MAC address can be used as a global address, false 3434 * otherwise. 3435 */ 3436 static bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port) 3437 { 3438 struct net_device *user = dsa_to_port(ds, port)->user; 3439 const unsigned char *addr = user->dev_addr; 3440 struct ksz_switch_macaddr *switch_macaddr; 3441 struct ksz_device *dev = ds->priv; 3442 3443 ASSERT_RTNL(); 3444 3445 switch_macaddr = dev->switch_macaddr; 3446 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr)) 3447 return false; 3448 3449 return true; 3450 } 3451 3452 /** 3453 * ksz_get_wol - Get Wake-on-LAN settings for a specified port. 3454 * @ds: The dsa_switch structure. 3455 * @port: The port number. 3456 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 3457 * 3458 * This function checks the device PME wakeup_source flag and chip_id. 3459 * If enabled and supported, it sets the supported and active WoL 3460 * flags. 3461 */ 3462 void ksz_get_wol(struct dsa_switch *ds, int port, 3463 struct ethtool_wolinfo *wol) 3464 { 3465 struct ksz_device *dev = ds->priv; 3466 const u16 *regs = dev->info->regs; 3467 u8 pme_ctrl; 3468 int ret; 3469 3470 if (!dev->wakeup_source) 3471 return; 3472 3473 wol->supported = WAKE_PHY; 3474 3475 /* Check if the current MAC address on this port can be set 3476 * as global for WAKE_MAGIC support. The result may vary 3477 * dynamically based on other ports configurations. 3478 */ 3479 if (ksz_is_port_mac_global_usable(dev->ds, port)) 3480 wol->supported |= WAKE_MAGIC; 3481 3482 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 3483 &pme_ctrl); 3484 if (ret) 3485 return; 3486 3487 if (pme_ctrl & PME_WOL_MAGICPKT) 3488 wol->wolopts |= WAKE_MAGIC; 3489 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY)) 3490 wol->wolopts |= WAKE_PHY; 3491 } 3492 3493 /** 3494 * ksz_set_wol - Set Wake-on-LAN settings for a specified port. 3495 * @ds: The dsa_switch structure. 3496 * @port: The port number. 3497 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 3498 * 3499 * This function configures Wake-on-LAN (WoL) settings for a specified 3500 * port. It validates the provided WoL options, checks if PME is 3501 * enabled and supported, clears any previous wake reasons, and sets 3502 * the Magic Packet flag in the port's PME control register if 3503 * specified. 3504 * 3505 * Return: 0 on success, or other error codes on failure. 3506 */ 3507 int ksz_set_wol(struct dsa_switch *ds, int port, 3508 struct ethtool_wolinfo *wol) 3509 { 3510 u8 pme_ctrl = 0, pme_ctrl_old = 0; 3511 struct ksz_device *dev = ds->priv; 3512 const u16 *regs = dev->info->regs; 3513 bool magic_switched_off; 3514 bool magic_switched_on; 3515 int ret; 3516 3517 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC)) 3518 return -EINVAL; 3519 3520 if (!dev->wakeup_source) 3521 return -EOPNOTSUPP; 3522 3523 ret = ksz_handle_wake_reason(dev, port); 3524 if (ret) 3525 return ret; 3526 3527 if (wol->wolopts & WAKE_MAGIC) 3528 pme_ctrl |= PME_WOL_MAGICPKT; 3529 if (wol->wolopts & WAKE_PHY) 3530 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY; 3531 3532 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 3533 &pme_ctrl_old); 3534 if (ret) 3535 return ret; 3536 3537 if (pme_ctrl_old == pme_ctrl) 3538 return 0; 3539 3540 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) && 3541 !(pme_ctrl & PME_WOL_MAGICPKT); 3542 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) && 3543 (pme_ctrl & PME_WOL_MAGICPKT); 3544 3545 /* To keep reference count of MAC address, we should do this 3546 * operation only on change of WOL settings. 3547 */ 3548 if (magic_switched_on) { 3549 ret = ksz_switch_macaddr_get(dev->ds, port, NULL); 3550 if (ret) 3551 return ret; 3552 } else if (magic_switched_off) { 3553 ksz_switch_macaddr_put(dev->ds); 3554 } 3555 3556 ret = dev->dev_ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 3557 pme_ctrl); 3558 if (ret) { 3559 if (magic_switched_on) 3560 ksz_switch_macaddr_put(dev->ds); 3561 return ret; 3562 } 3563 3564 return 0; 3565 } 3566 3567 /** 3568 * ksz_wol_pre_shutdown - Prepares the switch device for shutdown while 3569 * considering Wake-on-LAN (WoL) settings. 3570 * @dev: The switch device structure. 3571 * 3572 * This function prepares the switch device for a safe shutdown while taking 3573 * into account the Wake-on-LAN (WoL) settings on the user ports. 3574 */ 3575 static void ksz_wol_pre_shutdown(struct ksz_device *dev) 3576 { 3577 const struct ksz_dev_ops *ops = dev->dev_ops; 3578 const u16 *regs = dev->info->regs; 3579 struct dsa_switch *ds = dev->ds; 3580 u8 pme_pin_en = PME_ENABLE; 3581 bool wol_enabled = false; 3582 struct dsa_port *dp; 3583 int ret; 3584 3585 if (!ds->ops->set_wol) 3586 return; 3587 3588 if (!dev->wakeup_source) 3589 return; 3590 3591 dsa_switch_for_each_user_port(dp, dev->ds) { 3592 u8 pme_ctrl = 0; 3593 3594 ret = ops->pme_pread8(dev, dp->index, 3595 regs[REG_PORT_PME_CTRL], &pme_ctrl); 3596 if (!ret && pme_ctrl) 3597 wol_enabled = true; 3598 3599 /* make sure there are no pending wake events which would 3600 * prevent the device from going to sleep/shutdown. 3601 */ 3602 ksz_handle_wake_reason(dev, dp->index); 3603 } 3604 3605 /* Now we are save to enable PME pin. */ 3606 if (wol_enabled) { 3607 if (dev->pme_active_high) 3608 pme_pin_en |= PME_POLARITY; 3609 ops->pme_write8(dev, regs[REG_SW_PME_CTRL], pme_pin_en); 3610 if (ksz_is_ksz87xx(dev)) 3611 ksz_write8(dev, KSZ87XX_REG_INT_EN, KSZ87XX_INT_PME_MASK); 3612 } 3613 } 3614 3615 int ksz_port_set_mac_address(struct dsa_switch *ds, int port, 3616 const unsigned char *addr) 3617 { 3618 struct dsa_port *dp = dsa_to_port(ds, port); 3619 struct ethtool_wolinfo wol; 3620 3621 if (dp->hsr_dev) { 3622 dev_err(ds->dev, 3623 "Cannot change MAC address on port %d with active HSR offload\n", 3624 port); 3625 return -EBUSY; 3626 } 3627 3628 /* Need to initialize variable as the code to fill in settings may 3629 * not be executed. 3630 */ 3631 wol.wolopts = 0; 3632 3633 if (ds->ops->get_wol) 3634 ds->ops->get_wol(ds, dp->index, &wol); 3635 if (wol.wolopts & WAKE_MAGIC) { 3636 dev_err(ds->dev, 3637 "Cannot change MAC address on port %d with active Wake on Magic Packet\n", 3638 port); 3639 return -EBUSY; 3640 } 3641 3642 return 0; 3643 } 3644 3645 /** 3646 * ksz_switch_macaddr_get - Program the switch's MAC address register. 3647 * @ds: DSA switch instance. 3648 * @port: Port number. 3649 * @extack: Netlink extended acknowledgment. 3650 * 3651 * This function programs the switch's MAC address register with the MAC address 3652 * of the requesting user port. This single address is used by the switch for 3653 * multiple features like HSR self-address filtering and WoL. Other user ports 3654 * can share ownership of this address as long as their MAC address is the same. 3655 * The MAC addresses of user ports must not change while they have ownership of 3656 * the switch MAC address. 3657 * 3658 * Return: 0 on success, or other error codes on failure. 3659 */ 3660 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 3661 struct netlink_ext_ack *extack) 3662 { 3663 struct net_device *user = dsa_to_port(ds, port)->user; 3664 const unsigned char *addr = user->dev_addr; 3665 struct ksz_switch_macaddr *switch_macaddr; 3666 struct ksz_device *dev = ds->priv; 3667 const u16 *regs = dev->info->regs; 3668 int i, ret; 3669 3670 /* Make sure concurrent MAC address changes are blocked */ 3671 ASSERT_RTNL(); 3672 3673 switch_macaddr = dev->switch_macaddr; 3674 if (switch_macaddr) { 3675 if (!ether_addr_equal(switch_macaddr->addr, addr)) { 3676 NL_SET_ERR_MSG_FMT_MOD(extack, 3677 "Switch already configured for MAC address %pM", 3678 switch_macaddr->addr); 3679 return -EBUSY; 3680 } 3681 3682 refcount_inc(&switch_macaddr->refcount); 3683 return 0; 3684 } 3685 3686 switch_macaddr = kzalloc_obj(*switch_macaddr); 3687 if (!switch_macaddr) 3688 return -ENOMEM; 3689 3690 ether_addr_copy(switch_macaddr->addr, addr); 3691 refcount_set(&switch_macaddr->refcount, 1); 3692 dev->switch_macaddr = switch_macaddr; 3693 3694 /* Program the switch MAC address to hardware */ 3695 for (i = 0; i < ETH_ALEN; i++) { 3696 if (ksz_is_ksz8463(dev)) { 3697 u16 addr16 = ((u16)addr[i] << 8) | addr[i + 1]; 3698 3699 ret = ksz_write16(dev, regs[REG_SW_MAC_ADDR] + i, 3700 addr16); 3701 i++; 3702 } else { 3703 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 3704 addr[i]); 3705 } 3706 if (ret) 3707 goto macaddr_drop; 3708 } 3709 3710 return 0; 3711 3712 macaddr_drop: 3713 dev->switch_macaddr = NULL; 3714 refcount_set(&switch_macaddr->refcount, 0); 3715 kfree(switch_macaddr); 3716 3717 return ret; 3718 } 3719 3720 void ksz_switch_macaddr_put(struct dsa_switch *ds) 3721 { 3722 struct ksz_switch_macaddr *switch_macaddr; 3723 struct ksz_device *dev = ds->priv; 3724 const u16 *regs = dev->info->regs; 3725 int i; 3726 3727 /* Make sure concurrent MAC address changes are blocked */ 3728 ASSERT_RTNL(); 3729 3730 switch_macaddr = dev->switch_macaddr; 3731 if (!refcount_dec_and_test(&switch_macaddr->refcount)) 3732 return; 3733 3734 for (i = 0; i < ETH_ALEN; i++) 3735 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0); 3736 3737 dev->switch_macaddr = NULL; 3738 kfree(switch_macaddr); 3739 } 3740 3741 int ksz_suspend(struct dsa_switch *ds) 3742 { 3743 struct ksz_device *dev = ds->priv; 3744 3745 cancel_delayed_work_sync(&dev->mib_read); 3746 return 0; 3747 } 3748 3749 int ksz_resume(struct dsa_switch *ds) 3750 { 3751 struct ksz_device *dev = ds->priv; 3752 3753 if (dev->mib_read_interval) 3754 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 3755 return 0; 3756 } 3757 3758 struct ksz_device *ksz_switch_alloc(struct device *base, 3759 const struct ksz_chip_data *chip, 3760 void *priv) 3761 { 3762 struct dsa_switch *ds; 3763 struct ksz_device *swdev; 3764 3765 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 3766 if (!ds) 3767 return NULL; 3768 3769 ds->dev = base; 3770 ds->num_ports = DSA_MAX_PORTS; 3771 ds->ops = chip->switch_ops; 3772 3773 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 3774 if (!swdev) 3775 return NULL; 3776 3777 ds->priv = swdev; 3778 swdev->dev = base; 3779 3780 swdev->ds = ds; 3781 swdev->priv = priv; 3782 3783 return swdev; 3784 } 3785 EXPORT_SYMBOL(ksz_switch_alloc); 3786 3787 /** 3788 * ksz_switch_shutdown - Shutdown routine for the switch device. 3789 * @dev: The switch device structure. 3790 * 3791 * This function is responsible for initiating a shutdown sequence for the 3792 * switch device. Subsequently, it calls the DSA framework's shutdown function 3793 * to ensure a proper shutdown of the DSA switch. 3794 */ 3795 void ksz_switch_shutdown(struct ksz_device *dev) 3796 { 3797 ksz_wol_pre_shutdown(dev); 3798 dsa_switch_shutdown(dev->ds); 3799 } 3800 EXPORT_SYMBOL(ksz_switch_shutdown); 3801 3802 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 3803 struct device_node *port_dn) 3804 { 3805 phy_interface_t phy_mode = dev->ports[port_num].interface; 3806 int rx_delay = -1, tx_delay = -1; 3807 3808 if (!phy_interface_mode_is_rgmii(phy_mode)) 3809 return; 3810 3811 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 3812 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 3813 3814 if (rx_delay == -1 && tx_delay == -1) { 3815 dev_warn(dev->dev, 3816 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 3817 "please update device tree to specify \"rx-internal-delay-ps\" and " 3818 "\"tx-internal-delay-ps\"", 3819 port_num); 3820 3821 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 3822 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 3823 rx_delay = 2000; 3824 3825 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 3826 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 3827 tx_delay = 2000; 3828 } 3829 3830 if (rx_delay < 0) 3831 rx_delay = 0; 3832 if (tx_delay < 0) 3833 tx_delay = 0; 3834 3835 dev->ports[port_num].rgmii_rx_val = rx_delay; 3836 dev->ports[port_num].rgmii_tx_val = tx_delay; 3837 } 3838 3839 /** 3840 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding 3841 * register value. 3842 * @array: The array of drive strength values to search. 3843 * @array_size: The size of the array. 3844 * @microamp: The drive strength value in microamp to be converted. 3845 * 3846 * This function searches the array of drive strength values for the given 3847 * microamp value and returns the corresponding register value for that drive. 3848 * 3849 * Returns: If found, the corresponding register value for that drive strength 3850 * is returned. Otherwise, -EINVAL is returned indicating an invalid value. 3851 */ 3852 int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array, 3853 size_t array_size, int microamp) 3854 { 3855 int i; 3856 3857 for (i = 0; i < array_size; i++) { 3858 if (array[i].microamp == microamp) 3859 return array[i].reg_val; 3860 } 3861 3862 return -EINVAL; 3863 } 3864 3865 /** 3866 * ksz_drive_strength_error() - Report invalid drive strength value 3867 * @dev: ksz device 3868 * @array: The array of drive strength values to search. 3869 * @array_size: The size of the array. 3870 * @microamp: Invalid drive strength value in microamp 3871 * 3872 * This function logs an error message when an unsupported drive strength value 3873 * is detected. It lists out all the supported drive strength values for 3874 * reference in the error message. 3875 */ 3876 void ksz_drive_strength_error(struct ksz_device *dev, 3877 const struct ksz_drive_strength *array, 3878 size_t array_size, int microamp) 3879 { 3880 char supported_values[100]; 3881 size_t remaining_size; 3882 int added_len; 3883 char *ptr; 3884 int i; 3885 3886 remaining_size = sizeof(supported_values); 3887 ptr = supported_values; 3888 3889 for (i = 0; i < array_size; i++) { 3890 added_len = snprintf(ptr, remaining_size, 3891 i == 0 ? "%d" : ", %d", array[i].microamp); 3892 3893 if (added_len >= remaining_size) 3894 break; 3895 3896 ptr += added_len; 3897 remaining_size -= added_len; 3898 } 3899 3900 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n", 3901 microamp, supported_values); 3902 } 3903 3904 /** 3905 * ksz_drive_strength_write() - Set the drive strength for specific KSZ9477 3906 * and the KSZ87xx chip variants. 3907 * @dev: ksz device 3908 * @props: Array of drive strength properties to be applied 3909 * @num_props: Number of properties in the array 3910 * 3911 * This function configures the drive strength for various KSZ9477 chip variants 3912 * based on the provided properties. It handles chip-specific nuances and 3913 * ensures only valid drive strengths are written to the respective chip. 3914 * 3915 * Return: 0 on successful configuration, a negative error code on failure. 3916 */ 3917 int ksz_drive_strength_write(struct ksz_device *dev, 3918 struct ksz_driver_strength_prop *props, 3919 int num_props) 3920 { 3921 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths); 3922 int i, ret, reg; 3923 u8 mask = 0; 3924 u8 val = 0; 3925 3926 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1) 3927 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 3928 props[KSZ_DRIVER_STRENGTH_IO].name); 3929 3930 if (dev->chip_id == KSZ8795_CHIP_ID || 3931 dev->chip_id == KSZ8794_CHIP_ID || 3932 dev->chip_id == KSZ8765_CHIP_ID) 3933 reg = KSZ8795_REG_SW_CTRL_20; 3934 else 3935 reg = KSZ9477_REG_SW_IO_STRENGTH; 3936 3937 for (i = 0; i < num_props; i++) { 3938 if (props[i].value == -1) 3939 continue; 3940 3941 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths, 3942 array_size, props[i].value); 3943 if (ret < 0) { 3944 ksz_drive_strength_error(dev, ksz9477_drive_strengths, 3945 array_size, props[i].value); 3946 return ret; 3947 } 3948 3949 mask |= SW_DRIVE_STRENGTH_M << props[i].offset; 3950 val |= ret << props[i].offset; 3951 } 3952 3953 return ksz_rmw8(dev, reg, mask, val); 3954 } 3955 3956 static int ksz8463_configure_straps_spi(struct ksz_device *dev) 3957 { 3958 struct pinctrl *pinctrl; 3959 struct gpio_desc *rxd0; 3960 struct gpio_desc *rxd1; 3961 3962 rxd0 = devm_gpiod_get_index_optional(dev->dev, "straps-rxd", 0, GPIOD_OUT_LOW); 3963 if (IS_ERR(rxd0)) 3964 return PTR_ERR(rxd0); 3965 3966 rxd1 = devm_gpiod_get_index_optional(dev->dev, "straps-rxd", 1, GPIOD_OUT_HIGH); 3967 if (IS_ERR(rxd1)) 3968 return PTR_ERR(rxd1); 3969 3970 if (!rxd0 && !rxd1) 3971 return 0; 3972 3973 if ((rxd0 && !rxd1) || (rxd1 && !rxd0)) 3974 return -EINVAL; 3975 3976 pinctrl = devm_pinctrl_get_select(dev->dev, "reset"); 3977 if (IS_ERR(pinctrl)) 3978 return PTR_ERR(pinctrl); 3979 3980 return 0; 3981 } 3982 3983 static int ksz8463_release_straps_spi(struct ksz_device *dev) 3984 { 3985 return pinctrl_select_default_state(dev->dev); 3986 } 3987 3988 int ksz_switch_register(struct ksz_device *dev) 3989 { 3990 const struct ksz_chip_data *info; 3991 struct device_node *ports; 3992 phy_interface_t interface; 3993 unsigned int port_num; 3994 u32 lookup_chip_id; 3995 int ret; 3996 int i; 3997 3998 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 3999 GPIOD_OUT_LOW); 4000 if (IS_ERR(dev->reset_gpio)) 4001 return PTR_ERR(dev->reset_gpio); 4002 4003 if (dev->reset_gpio) { 4004 if (of_device_is_compatible(dev->dev->of_node, "microchip,ksz8463")) { 4005 ret = ksz8463_configure_straps_spi(dev); 4006 if (ret) 4007 return ret; 4008 } 4009 4010 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4011 usleep_range(10000, 12000); 4012 gpiod_set_value_cansleep(dev->reset_gpio, 0); 4013 msleep(100); 4014 4015 if (of_device_is_compatible(dev->dev->of_node, "microchip,ksz8463")) { 4016 ret = ksz8463_release_straps_spi(dev); 4017 if (ret) 4018 return ret; 4019 } 4020 } 4021 4022 mutex_init(&dev->dev_mutex); 4023 mutex_init(&dev->regmap_mutex); 4024 mutex_init(&dev->alu_mutex); 4025 mutex_init(&dev->vlan_mutex); 4026 4027 ret = ksz_switch_detect(dev); 4028 if (ret) 4029 return ret; 4030 4031 lookup_chip_id = dev->chip_id; 4032 4033 /* The KSZ9897S and the KSZ9897R report the same chip ID and differ 4034 * only in chip_data: only the S has the SGMII port 7, the R has a 4035 * second RGMII port instead. Bit 7 of the port 7 XMII control 0 4036 * register is read-only and tells them apart; it reads one on the S. 4037 * Compare the KSZ9897S data sheet DS00002394C section 5.2.4.1 with 4038 * the KSZ9897R data sheet DS00002330D section 5.2.3.1. 4039 * 4040 * Only the chip_data entry differs, so dev->chip_id keeps the shared 4041 * chip ID and nothing else has to know about the variant. 4042 */ 4043 if (dev->chip_id == KSZ9897_CHIP_ID) { 4044 u8 val; 4045 4046 ret = ksz_read8(dev, KSZ9897_REG_PORT7_XMII_CTRL_0, &val); 4047 if (ret) 4048 return ret; 4049 4050 if (val & KSZ9897_PORT7_SGMII_SEL) 4051 lookup_chip_id = KSZ9897S_CHIP_ID; 4052 } 4053 4054 info = ksz_lookup_info(lookup_chip_id); 4055 if (!info) 4056 return -ENODEV; 4057 4058 /* Update the compatible info with the probed one */ 4059 dev->info = info; 4060 4061 dev_info(dev->dev, "found switch: %s, rev %i\n", 4062 dev->info->dev_name, dev->chip_rev); 4063 4064 ret = ksz_check_device_id(dev); 4065 if (ret) 4066 return ret; 4067 4068 dev->dev_ops = dev->info->ops; 4069 4070 ret = dev->dev_ops->init(dev); 4071 if (ret) 4072 return ret; 4073 4074 dev->ports = devm_kzalloc(dev->dev, 4075 dev->info->port_cnt * sizeof(struct ksz_port), 4076 GFP_KERNEL); 4077 if (!dev->ports) 4078 return -ENOMEM; 4079 4080 for (i = 0; i < dev->info->port_cnt; i++) { 4081 spin_lock_init(&dev->ports[i].mib.stats64_lock); 4082 mutex_init(&dev->ports[i].mib.cnt_mutex); 4083 dev->ports[i].mib.counters = 4084 devm_kzalloc(dev->dev, 4085 sizeof(u64) * (dev->info->mib_cnt + 1), 4086 GFP_KERNEL); 4087 if (!dev->ports[i].mib.counters) 4088 return -ENOMEM; 4089 4090 dev->ports[i].ksz_dev = dev; 4091 dev->ports[i].num = i; 4092 } 4093 4094 /* set the real number of ports */ 4095 dev->ds->num_ports = dev->info->port_cnt; 4096 4097 /* set the phylink ops */ 4098 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops; 4099 4100 /* Host port interface will be self detected, or specifically set in 4101 * device tree. 4102 */ 4103 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 4104 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 4105 if (dev->dev->of_node) { 4106 ret = of_get_phy_mode(dev->dev->of_node, &interface); 4107 if (ret == 0) 4108 dev->compat_interface = interface; 4109 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 4110 if (!ports) 4111 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 4112 if (ports) { 4113 for_each_available_child_of_node_scoped(ports, port) { 4114 if (of_property_read_u32(port, "reg", 4115 &port_num)) 4116 continue; 4117 if (!(dev->port_mask & BIT(port_num))) { 4118 of_node_put(ports); 4119 return -EINVAL; 4120 } 4121 of_get_phy_mode(port, 4122 &dev->ports[port_num].interface); 4123 4124 ksz_parse_rgmii_delay(dev, port_num, port); 4125 dev->ports[port_num].fiber = 4126 of_property_read_bool(port, 4127 "micrel,fiber-mode"); 4128 } 4129 of_node_put(ports); 4130 } 4131 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 4132 "microchip,synclko-125"); 4133 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 4134 "microchip,synclko-disable"); 4135 if (dev->synclko_125 && dev->synclko_disable) { 4136 dev_err(dev->dev, "inconsistent synclko settings\n"); 4137 return -EINVAL; 4138 } 4139 4140 dev->wakeup_source = of_property_read_bool(dev->dev->of_node, 4141 "wakeup-source"); 4142 dev->pme_active_high = of_property_read_bool(dev->dev->of_node, 4143 "microchip,pme-active-high"); 4144 } 4145 4146 ret = dsa_register_switch(dev->ds); 4147 if (ret) 4148 return ret; 4149 4150 if (!ksz_is_ksz8995xa(dev)) { 4151 /* Read MIB counters every 30 seconds to avoid overflow. */ 4152 dev->mib_read_interval = msecs_to_jiffies(5000); 4153 4154 /* Start the MIB timer. */ 4155 schedule_delayed_work(&dev->mib_read, 0); 4156 } 4157 4158 return ret; 4159 } 4160 EXPORT_SYMBOL(ksz_switch_register); 4161 4162 void ksz_switch_remove(struct ksz_device *dev) 4163 { 4164 /* timer started */ 4165 if (dev->mib_read_interval) { 4166 dev->mib_read_interval = 0; 4167 cancel_delayed_work_sync(&dev->mib_read); 4168 } 4169 4170 dsa_unregister_switch(dev->ds); 4171 } 4172 EXPORT_SYMBOL(ksz_switch_remove); 4173 4174 #ifdef CONFIG_PM_SLEEP 4175 int ksz_switch_suspend(struct device *dev) 4176 { 4177 struct ksz_device *priv = dev_get_drvdata(dev); 4178 4179 return dsa_switch_suspend(priv->ds); 4180 } 4181 EXPORT_SYMBOL(ksz_switch_suspend); 4182 4183 int ksz_switch_resume(struct device *dev) 4184 { 4185 struct ksz_device *priv = dev_get_drvdata(dev); 4186 4187 return dsa_switch_resume(priv->ds); 4188 } 4189 EXPORT_SYMBOL(ksz_switch_resume); 4190 #endif 4191 4192 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 4193 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 4194 MODULE_LICENSE("GPL"); 4195