1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2025 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/if_hsr.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/of.h> 23 #include <linux/of_mdio.h> 24 #include <linux/of_net.h> 25 #include <linux/micrel_phy.h> 26 #include <net/dsa.h> 27 #include <net/ieee8021q.h> 28 #include <net/pkt_cls.h> 29 #include <net/switchdev.h> 30 31 #include "ksz_common.h" 32 #include "ksz_dcb.h" 33 #include "ksz_ptp.h" 34 #include "ksz8.h" 35 #include "ksz9477.h" 36 #include "lan937x.h" 37 38 #define MIB_COUNTER_NUM 0x20 39 40 struct ksz_stats_raw { 41 u64 rx_hi; 42 u64 rx_undersize; 43 u64 rx_fragments; 44 u64 rx_oversize; 45 u64 rx_jabbers; 46 u64 rx_symbol_err; 47 u64 rx_crc_err; 48 u64 rx_align_err; 49 u64 rx_mac_ctrl; 50 u64 rx_pause; 51 u64 rx_bcast; 52 u64 rx_mcast; 53 u64 rx_ucast; 54 u64 rx_64_or_less; 55 u64 rx_65_127; 56 u64 rx_128_255; 57 u64 rx_256_511; 58 u64 rx_512_1023; 59 u64 rx_1024_1522; 60 u64 rx_1523_2000; 61 u64 rx_2001; 62 u64 tx_hi; 63 u64 tx_late_col; 64 u64 tx_pause; 65 u64 tx_bcast; 66 u64 tx_mcast; 67 u64 tx_ucast; 68 u64 tx_deferred; 69 u64 tx_total_col; 70 u64 tx_exc_col; 71 u64 tx_single_col; 72 u64 tx_mult_col; 73 u64 rx_total; 74 u64 tx_total; 75 u64 rx_discards; 76 u64 tx_discards; 77 }; 78 79 struct ksz88xx_stats_raw { 80 u64 rx; 81 u64 rx_hi; 82 u64 rx_undersize; 83 u64 rx_fragments; 84 u64 rx_oversize; 85 u64 rx_jabbers; 86 u64 rx_symbol_err; 87 u64 rx_crc_err; 88 u64 rx_align_err; 89 u64 rx_mac_ctrl; 90 u64 rx_pause; 91 u64 rx_bcast; 92 u64 rx_mcast; 93 u64 rx_ucast; 94 u64 rx_64_or_less; 95 u64 rx_65_127; 96 u64 rx_128_255; 97 u64 rx_256_511; 98 u64 rx_512_1023; 99 u64 rx_1024_1522; 100 u64 tx; 101 u64 tx_hi; 102 u64 tx_late_col; 103 u64 tx_pause; 104 u64 tx_bcast; 105 u64 tx_mcast; 106 u64 tx_ucast; 107 u64 tx_deferred; 108 u64 tx_total_col; 109 u64 tx_exc_col; 110 u64 tx_single_col; 111 u64 tx_mult_col; 112 u64 rx_discards; 113 u64 tx_discards; 114 }; 115 116 static const struct ksz_mib_names ksz88xx_mib_names[] = { 117 { 0x00, "rx" }, 118 { 0x01, "rx_hi" }, 119 { 0x02, "rx_undersize" }, 120 { 0x03, "rx_fragments" }, 121 { 0x04, "rx_oversize" }, 122 { 0x05, "rx_jabbers" }, 123 { 0x06, "rx_symbol_err" }, 124 { 0x07, "rx_crc_err" }, 125 { 0x08, "rx_align_err" }, 126 { 0x09, "rx_mac_ctrl" }, 127 { 0x0a, "rx_pause" }, 128 { 0x0b, "rx_bcast" }, 129 { 0x0c, "rx_mcast" }, 130 { 0x0d, "rx_ucast" }, 131 { 0x0e, "rx_64_or_less" }, 132 { 0x0f, "rx_65_127" }, 133 { 0x10, "rx_128_255" }, 134 { 0x11, "rx_256_511" }, 135 { 0x12, "rx_512_1023" }, 136 { 0x13, "rx_1024_1522" }, 137 { 0x14, "tx" }, 138 { 0x15, "tx_hi" }, 139 { 0x16, "tx_late_col" }, 140 { 0x17, "tx_pause" }, 141 { 0x18, "tx_bcast" }, 142 { 0x19, "tx_mcast" }, 143 { 0x1a, "tx_ucast" }, 144 { 0x1b, "tx_deferred" }, 145 { 0x1c, "tx_total_col" }, 146 { 0x1d, "tx_exc_col" }, 147 { 0x1e, "tx_single_col" }, 148 { 0x1f, "tx_mult_col" }, 149 { 0x100, "rx_discards" }, 150 { 0x101, "tx_discards" }, 151 }; 152 153 static const struct ksz_mib_names ksz9477_mib_names[] = { 154 { 0x00, "rx_hi" }, 155 { 0x01, "rx_undersize" }, 156 { 0x02, "rx_fragments" }, 157 { 0x03, "rx_oversize" }, 158 { 0x04, "rx_jabbers" }, 159 { 0x05, "rx_symbol_err" }, 160 { 0x06, "rx_crc_err" }, 161 { 0x07, "rx_align_err" }, 162 { 0x08, "rx_mac_ctrl" }, 163 { 0x09, "rx_pause" }, 164 { 0x0A, "rx_bcast" }, 165 { 0x0B, "rx_mcast" }, 166 { 0x0C, "rx_ucast" }, 167 { 0x0D, "rx_64_or_less" }, 168 { 0x0E, "rx_65_127" }, 169 { 0x0F, "rx_128_255" }, 170 { 0x10, "rx_256_511" }, 171 { 0x11, "rx_512_1023" }, 172 { 0x12, "rx_1024_1522" }, 173 { 0x13, "rx_1523_2000" }, 174 { 0x14, "rx_2001" }, 175 { 0x15, "tx_hi" }, 176 { 0x16, "tx_late_col" }, 177 { 0x17, "tx_pause" }, 178 { 0x18, "tx_bcast" }, 179 { 0x19, "tx_mcast" }, 180 { 0x1A, "tx_ucast" }, 181 { 0x1B, "tx_deferred" }, 182 { 0x1C, "tx_total_col" }, 183 { 0x1D, "tx_exc_col" }, 184 { 0x1E, "tx_single_col" }, 185 { 0x1F, "tx_mult_col" }, 186 { 0x80, "rx_total" }, 187 { 0x81, "tx_total" }, 188 { 0x82, "rx_discards" }, 189 { 0x83, "tx_discards" }, 190 }; 191 192 struct ksz_driver_strength_prop { 193 const char *name; 194 int offset; 195 int value; 196 }; 197 198 enum ksz_driver_strength_type { 199 KSZ_DRIVER_STRENGTH_HI, 200 KSZ_DRIVER_STRENGTH_LO, 201 KSZ_DRIVER_STRENGTH_IO, 202 }; 203 204 /** 205 * struct ksz_drive_strength - drive strength mapping 206 * @reg_val: register value 207 * @microamp: microamp value 208 */ 209 struct ksz_drive_strength { 210 u32 reg_val; 211 u32 microamp; 212 }; 213 214 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants 215 * 216 * This values are not documented in KSZ9477 variants but confirmed by 217 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893 218 * and KSZ8563 are using same register (drive strength) settings like KSZ8795. 219 * 220 * Documentation in KSZ8795CLX provides more information with some 221 * recommendations: 222 * - for high speed signals 223 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using 224 * 2.5V or 3.3V VDDIO. 225 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with 226 * using 1.8V VDDIO. 227 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V 228 * or 3.3V VDDIO. 229 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO. 230 * 5. In same interface, the heavy loading should use higher one of the 231 * drive current strength. 232 * - for low speed signals 233 * 1. 3.3V VDDIO, use either 4 mA or 8 mA. 234 * 2. 2.5V VDDIO, use either 8 mA or 12 mA. 235 * 3. 1.8V VDDIO, use either 12 mA or 16 mA. 236 * 4. If it is heavy loading, can use higher drive current strength. 237 */ 238 static const struct ksz_drive_strength ksz9477_drive_strengths[] = { 239 { SW_DRIVE_STRENGTH_2MA, 2000 }, 240 { SW_DRIVE_STRENGTH_4MA, 4000 }, 241 { SW_DRIVE_STRENGTH_8MA, 8000 }, 242 { SW_DRIVE_STRENGTH_12MA, 12000 }, 243 { SW_DRIVE_STRENGTH_16MA, 16000 }, 244 { SW_DRIVE_STRENGTH_20MA, 20000 }, 245 { SW_DRIVE_STRENGTH_24MA, 24000 }, 246 { SW_DRIVE_STRENGTH_28MA, 28000 }, 247 }; 248 249 /* ksz88x3_drive_strengths - Drive strength mapping for KSZ8863, KSZ8873, .. 250 * variants. 251 * This values are documented in KSZ8873 and KSZ8863 datasheets. 252 */ 253 static const struct ksz_drive_strength ksz88x3_drive_strengths[] = { 254 { 0, 8000 }, 255 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 }, 256 }; 257 258 static void ksz88x3_phylink_mac_config(struct phylink_config *config, 259 unsigned int mode, 260 const struct phylink_link_state *state); 261 static void ksz_phylink_mac_config(struct phylink_config *config, 262 unsigned int mode, 263 const struct phylink_link_state *state); 264 static void ksz_phylink_mac_link_down(struct phylink_config *config, 265 unsigned int mode, 266 phy_interface_t interface); 267 268 /** 269 * ksz_phylink_mac_disable_tx_lpi() - Callback to signal LPI support (Dummy) 270 * @config: phylink config structure 271 * 272 * This function is a dummy handler. See ksz_phylink_mac_enable_tx_lpi() for 273 * a detailed explanation of EEE/LPI handling in KSZ switches. 274 */ 275 static void ksz_phylink_mac_disable_tx_lpi(struct phylink_config *config) 276 { 277 } 278 279 /** 280 * ksz_phylink_mac_enable_tx_lpi() - Callback to signal LPI support (Dummy) 281 * @config: phylink config structure 282 * @timer: timer value before entering LPI (unused) 283 * @tx_clock_stop: whether to stop the TX clock in LPI mode (unused) 284 * 285 * This function signals to phylink that the driver architecture supports 286 * LPI management, enabling phylink to control EEE advertisement during 287 * negotiation according to IEEE Std 802.3 (Clause 78). 288 * 289 * Hardware Management of EEE/LPI State: 290 * For KSZ switch ports with integrated PHYs (e.g., KSZ9893R ports 1-2), 291 * observation and testing suggest that the actual EEE / Low Power Idle (LPI) 292 * state transitions are managed autonomously by the hardware based on 293 * the auto-negotiation results. (Note: While the datasheet describes EEE 294 * operation based on negotiation, it doesn't explicitly detail the internal 295 * MAC/PHY interaction, so autonomous hardware management of the MAC state 296 * for LPI is inferred from observed behavior). 297 * This hardware control, consistent with the switch's ability to operate 298 * autonomously via strapping, means MAC-level software intervention is not 299 * required or exposed for managing the LPI state once EEE is negotiated. 300 * (Ref: KSZ9893R Data Sheet DS00002420D, primarily Section 4.7.5 explaining 301 * EEE, also Sections 4.1.7 on Auto-Negotiation and 3.2.1 on Configuration 302 * Straps). 303 * 304 * Additionally, ports configured as MAC interfaces (e.g., KSZ9893R port 3) 305 * lack documented MAC-level LPI control. 306 * 307 * Therefore, this callback performs no action and serves primarily to inform 308 * phylink of LPI awareness and to document the inferred hardware behavior. 309 * 310 * Returns: 0 (Always success) 311 */ 312 static int ksz_phylink_mac_enable_tx_lpi(struct phylink_config *config, 313 u32 timer, bool tx_clock_stop) 314 { 315 return 0; 316 } 317 318 static const struct phylink_mac_ops ksz88x3_phylink_mac_ops = { 319 .mac_config = ksz88x3_phylink_mac_config, 320 .mac_link_down = ksz_phylink_mac_link_down, 321 .mac_link_up = ksz8_phylink_mac_link_up, 322 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 323 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 324 }; 325 326 static const struct phylink_mac_ops ksz8_phylink_mac_ops = { 327 .mac_config = ksz_phylink_mac_config, 328 .mac_link_down = ksz_phylink_mac_link_down, 329 .mac_link_up = ksz8_phylink_mac_link_up, 330 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 331 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 332 }; 333 334 static const struct ksz_dev_ops ksz8463_dev_ops = { 335 .setup = ksz8_setup, 336 .get_port_addr = ksz8463_get_port_addr, 337 .cfg_port_member = ksz8_cfg_port_member, 338 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 339 .port_setup = ksz8_port_setup, 340 .r_phy = ksz8463_r_phy, 341 .w_phy = ksz8463_w_phy, 342 .r_mib_cnt = ksz8_r_mib_cnt, 343 .r_mib_pkt = ksz8_r_mib_pkt, 344 .r_mib_stat64 = ksz88xx_r_mib_stats64, 345 .freeze_mib = ksz8_freeze_mib, 346 .port_init_cnt = ksz8_port_init_cnt, 347 .fdb_dump = ksz8_fdb_dump, 348 .fdb_add = ksz8_fdb_add, 349 .fdb_del = ksz8_fdb_del, 350 .mdb_add = ksz8_mdb_add, 351 .mdb_del = ksz8_mdb_del, 352 .vlan_filtering = ksz8_port_vlan_filtering, 353 .vlan_add = ksz8_port_vlan_add, 354 .vlan_del = ksz8_port_vlan_del, 355 .mirror_add = ksz8_port_mirror_add, 356 .mirror_del = ksz8_port_mirror_del, 357 .get_caps = ksz8_get_caps, 358 .config_cpu_port = ksz8_config_cpu_port, 359 .enable_stp_addr = ksz8_enable_stp_addr, 360 .reset = ksz8_reset_switch, 361 .init = ksz8_switch_init, 362 .exit = ksz8_switch_exit, 363 .change_mtu = ksz8_change_mtu, 364 }; 365 366 static const struct ksz_dev_ops ksz88xx_dev_ops = { 367 .setup = ksz8_setup, 368 .get_port_addr = ksz8_get_port_addr, 369 .cfg_port_member = ksz8_cfg_port_member, 370 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 371 .port_setup = ksz8_port_setup, 372 .r_phy = ksz8_r_phy, 373 .w_phy = ksz8_w_phy, 374 .r_mib_cnt = ksz8_r_mib_cnt, 375 .r_mib_pkt = ksz8_r_mib_pkt, 376 .r_mib_stat64 = ksz88xx_r_mib_stats64, 377 .freeze_mib = ksz8_freeze_mib, 378 .port_init_cnt = ksz8_port_init_cnt, 379 .fdb_dump = ksz8_fdb_dump, 380 .fdb_add = ksz8_fdb_add, 381 .fdb_del = ksz8_fdb_del, 382 .mdb_add = ksz8_mdb_add, 383 .mdb_del = ksz8_mdb_del, 384 .vlan_filtering = ksz8_port_vlan_filtering, 385 .vlan_add = ksz8_port_vlan_add, 386 .vlan_del = ksz8_port_vlan_del, 387 .mirror_add = ksz8_port_mirror_add, 388 .mirror_del = ksz8_port_mirror_del, 389 .get_caps = ksz8_get_caps, 390 .config_cpu_port = ksz8_config_cpu_port, 391 .enable_stp_addr = ksz8_enable_stp_addr, 392 .reset = ksz8_reset_switch, 393 .init = ksz8_switch_init, 394 .exit = ksz8_switch_exit, 395 .change_mtu = ksz8_change_mtu, 396 .pme_write8 = ksz8_pme_write8, 397 .pme_pread8 = ksz8_pme_pread8, 398 .pme_pwrite8 = ksz8_pme_pwrite8, 399 }; 400 401 static const struct ksz_dev_ops ksz87xx_dev_ops = { 402 .setup = ksz8_setup, 403 .get_port_addr = ksz8_get_port_addr, 404 .cfg_port_member = ksz8_cfg_port_member, 405 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 406 .port_setup = ksz8_port_setup, 407 .r_phy = ksz8_r_phy, 408 .w_phy = ksz8_w_phy, 409 .r_mib_cnt = ksz8_r_mib_cnt, 410 .r_mib_pkt = ksz8_r_mib_pkt, 411 .r_mib_stat64 = ksz_r_mib_stats64, 412 .freeze_mib = ksz8_freeze_mib, 413 .port_init_cnt = ksz8_port_init_cnt, 414 .fdb_dump = ksz8_fdb_dump, 415 .fdb_add = ksz8_fdb_add, 416 .fdb_del = ksz8_fdb_del, 417 .mdb_add = ksz8_mdb_add, 418 .mdb_del = ksz8_mdb_del, 419 .vlan_filtering = ksz8_port_vlan_filtering, 420 .vlan_add = ksz8_port_vlan_add, 421 .vlan_del = ksz8_port_vlan_del, 422 .mirror_add = ksz8_port_mirror_add, 423 .mirror_del = ksz8_port_mirror_del, 424 .get_caps = ksz8_get_caps, 425 .config_cpu_port = ksz8_config_cpu_port, 426 .enable_stp_addr = ksz8_enable_stp_addr, 427 .reset = ksz8_reset_switch, 428 .init = ksz8_switch_init, 429 .exit = ksz8_switch_exit, 430 .change_mtu = ksz8_change_mtu, 431 .pme_write8 = ksz8_pme_write8, 432 .pme_pread8 = ksz8_pme_pread8, 433 .pme_pwrite8 = ksz8_pme_pwrite8, 434 }; 435 436 static void ksz9477_phylink_mac_link_up(struct phylink_config *config, 437 struct phy_device *phydev, 438 unsigned int mode, 439 phy_interface_t interface, 440 int speed, int duplex, bool tx_pause, 441 bool rx_pause); 442 443 static struct phylink_pcs * 444 ksz_phylink_mac_select_pcs(struct phylink_config *config, 445 phy_interface_t interface) 446 { 447 struct dsa_port *dp = dsa_phylink_to_port(config); 448 struct ksz_device *dev = dp->ds->priv; 449 struct ksz_port *p = &dev->ports[dp->index]; 450 451 if (ksz_is_sgmii_port(dev, dp->index) && 452 (interface == PHY_INTERFACE_MODE_SGMII || 453 interface == PHY_INTERFACE_MODE_1000BASEX)) 454 return p->pcs; 455 456 return NULL; 457 } 458 459 static const struct phylink_mac_ops ksz9477_phylink_mac_ops = { 460 .mac_config = ksz_phylink_mac_config, 461 .mac_link_down = ksz_phylink_mac_link_down, 462 .mac_link_up = ksz9477_phylink_mac_link_up, 463 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 464 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 465 .mac_select_pcs = ksz_phylink_mac_select_pcs, 466 }; 467 468 static const struct ksz_dev_ops ksz9477_dev_ops = { 469 .setup = ksz9477_setup, 470 .get_port_addr = ksz9477_get_port_addr, 471 .cfg_port_member = ksz9477_cfg_port_member, 472 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 473 .port_setup = ksz9477_port_setup, 474 .set_ageing_time = ksz9477_set_ageing_time, 475 .r_phy = ksz9477_r_phy, 476 .w_phy = ksz9477_w_phy, 477 .r_mib_cnt = ksz9477_r_mib_cnt, 478 .r_mib_pkt = ksz9477_r_mib_pkt, 479 .r_mib_stat64 = ksz_r_mib_stats64, 480 .freeze_mib = ksz9477_freeze_mib, 481 .port_init_cnt = ksz9477_port_init_cnt, 482 .vlan_filtering = ksz9477_port_vlan_filtering, 483 .vlan_add = ksz9477_port_vlan_add, 484 .vlan_del = ksz9477_port_vlan_del, 485 .mirror_add = ksz9477_port_mirror_add, 486 .mirror_del = ksz9477_port_mirror_del, 487 .get_caps = ksz9477_get_caps, 488 .fdb_dump = ksz9477_fdb_dump, 489 .fdb_add = ksz9477_fdb_add, 490 .fdb_del = ksz9477_fdb_del, 491 .mdb_add = ksz9477_mdb_add, 492 .mdb_del = ksz9477_mdb_del, 493 .change_mtu = ksz9477_change_mtu, 494 .pme_write8 = ksz_write8, 495 .pme_pread8 = ksz_pread8, 496 .pme_pwrite8 = ksz_pwrite8, 497 .config_cpu_port = ksz9477_config_cpu_port, 498 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc, 499 .enable_stp_addr = ksz9477_enable_stp_addr, 500 .reset = ksz9477_reset_switch, 501 .init = ksz9477_switch_init, 502 .exit = ksz9477_switch_exit, 503 .pcs_create = ksz9477_pcs_create, 504 }; 505 506 static const struct phylink_mac_ops lan937x_phylink_mac_ops = { 507 .mac_config = ksz_phylink_mac_config, 508 .mac_link_down = ksz_phylink_mac_link_down, 509 .mac_link_up = ksz9477_phylink_mac_link_up, 510 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 511 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 512 }; 513 514 static const struct ksz_dev_ops lan937x_dev_ops = { 515 .setup = lan937x_setup, 516 .teardown = lan937x_teardown, 517 .get_port_addr = ksz9477_get_port_addr, 518 .cfg_port_member = ksz9477_cfg_port_member, 519 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 520 .port_setup = lan937x_port_setup, 521 .set_ageing_time = lan937x_set_ageing_time, 522 .mdio_bus_preinit = lan937x_mdio_bus_preinit, 523 .create_phy_addr_map = lan937x_create_phy_addr_map, 524 .r_phy = lan937x_r_phy, 525 .w_phy = lan937x_w_phy, 526 .r_mib_cnt = ksz9477_r_mib_cnt, 527 .r_mib_pkt = ksz9477_r_mib_pkt, 528 .r_mib_stat64 = ksz_r_mib_stats64, 529 .freeze_mib = ksz9477_freeze_mib, 530 .port_init_cnt = ksz9477_port_init_cnt, 531 .vlan_filtering = ksz9477_port_vlan_filtering, 532 .vlan_add = ksz9477_port_vlan_add, 533 .vlan_del = ksz9477_port_vlan_del, 534 .mirror_add = ksz9477_port_mirror_add, 535 .mirror_del = ksz9477_port_mirror_del, 536 .get_caps = lan937x_phylink_get_caps, 537 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 538 .fdb_dump = ksz9477_fdb_dump, 539 .fdb_add = ksz9477_fdb_add, 540 .fdb_del = ksz9477_fdb_del, 541 .mdb_add = ksz9477_mdb_add, 542 .mdb_del = ksz9477_mdb_del, 543 .change_mtu = lan937x_change_mtu, 544 .config_cpu_port = lan937x_config_cpu_port, 545 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 546 .enable_stp_addr = ksz9477_enable_stp_addr, 547 .reset = lan937x_reset_switch, 548 .init = lan937x_switch_init, 549 .exit = lan937x_switch_exit, 550 }; 551 552 static const u16 ksz8463_regs[] = { 553 [REG_SW_MAC_ADDR] = 0x10, 554 [REG_IND_CTRL_0] = 0x30, 555 [REG_IND_DATA_8] = 0x26, 556 [REG_IND_DATA_CHECK] = 0x26, 557 [REG_IND_DATA_HI] = 0x28, 558 [REG_IND_DATA_LO] = 0x2C, 559 [REG_IND_MIB_CHECK] = 0x2F, 560 [P_FORCE_CTRL] = 0x0C, 561 [P_LINK_STATUS] = 0x0E, 562 [P_LOCAL_CTRL] = 0x0C, 563 [P_NEG_RESTART_CTRL] = 0x0D, 564 [P_REMOTE_STATUS] = 0x0E, 565 [P_SPEED_STATUS] = 0x0F, 566 [S_TAIL_TAG_CTRL] = 0xAD, 567 [P_STP_CTRL] = 0x6F, 568 [S_START_CTRL] = 0x01, 569 [S_BROADCAST_CTRL] = 0x06, 570 [S_MULTICAST_CTRL] = 0x04, 571 }; 572 573 static const u32 ksz8463_masks[] = { 574 [PORT_802_1P_REMAPPING] = BIT(3), 575 [SW_TAIL_TAG_ENABLE] = BIT(0), 576 [MIB_COUNTER_OVERFLOW] = BIT(7), 577 [MIB_COUNTER_VALID] = BIT(6), 578 [VLAN_TABLE_FID] = GENMASK(15, 12), 579 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 580 [VLAN_TABLE_VALID] = BIT(19), 581 [STATIC_MAC_TABLE_VALID] = BIT(19), 582 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 583 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 584 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 585 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 586 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 587 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 588 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 589 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 590 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 591 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 592 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 593 }; 594 595 static u8 ksz8463_shifts[] = { 596 [VLAN_TABLE_MEMBERSHIP_S] = 16, 597 [STATIC_MAC_FWD_PORTS] = 16, 598 [STATIC_MAC_FID] = 22, 599 [DYNAMIC_MAC_ENTRIES_H] = 8, 600 [DYNAMIC_MAC_ENTRIES] = 24, 601 [DYNAMIC_MAC_FID] = 16, 602 [DYNAMIC_MAC_TIMESTAMP] = 22, 603 [DYNAMIC_MAC_SRC_PORT] = 20, 604 }; 605 606 static const u16 ksz8795_regs[] = { 607 [REG_SW_MAC_ADDR] = 0x68, 608 [REG_IND_CTRL_0] = 0x6E, 609 [REG_IND_DATA_8] = 0x70, 610 [REG_IND_DATA_CHECK] = 0x72, 611 [REG_IND_DATA_HI] = 0x71, 612 [REG_IND_DATA_LO] = 0x75, 613 [REG_IND_MIB_CHECK] = 0x74, 614 [REG_IND_BYTE] = 0xA0, 615 [P_FORCE_CTRL] = 0x0C, 616 [P_LINK_STATUS] = 0x0E, 617 [P_LOCAL_CTRL] = 0x07, 618 [P_NEG_RESTART_CTRL] = 0x0D, 619 [P_REMOTE_STATUS] = 0x08, 620 [P_SPEED_STATUS] = 0x09, 621 [S_TAIL_TAG_CTRL] = 0x0C, 622 [P_STP_CTRL] = 0x02, 623 [S_START_CTRL] = 0x01, 624 [S_BROADCAST_CTRL] = 0x06, 625 [S_MULTICAST_CTRL] = 0x04, 626 [P_XMII_CTRL_0] = 0x06, 627 [P_XMII_CTRL_1] = 0x06, 628 [REG_SW_PME_CTRL] = 0x8003, 629 [REG_PORT_PME_STATUS] = 0x8003, 630 [REG_PORT_PME_CTRL] = 0x8007, 631 }; 632 633 static const u32 ksz8795_masks[] = { 634 [PORT_802_1P_REMAPPING] = BIT(7), 635 [SW_TAIL_TAG_ENABLE] = BIT(1), 636 [MIB_COUNTER_OVERFLOW] = BIT(6), 637 [MIB_COUNTER_VALID] = BIT(5), 638 [VLAN_TABLE_FID] = GENMASK(6, 0), 639 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 640 [VLAN_TABLE_VALID] = BIT(12), 641 [STATIC_MAC_TABLE_VALID] = BIT(21), 642 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 643 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 644 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 645 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 646 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 647 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 648 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 649 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 650 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 651 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 652 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 653 [P_MII_TX_FLOW_CTRL] = BIT(5), 654 [P_MII_RX_FLOW_CTRL] = BIT(5), 655 }; 656 657 static const u8 ksz8795_xmii_ctrl0[] = { 658 [P_MII_100MBIT] = 0, 659 [P_MII_10MBIT] = 1, 660 [P_MII_FULL_DUPLEX] = 0, 661 [P_MII_HALF_DUPLEX] = 1, 662 }; 663 664 static const u8 ksz8795_xmii_ctrl1[] = { 665 [P_RGMII_SEL] = 3, 666 [P_GMII_SEL] = 2, 667 [P_RMII_SEL] = 1, 668 [P_MII_SEL] = 0, 669 [P_GMII_1GBIT] = 1, 670 [P_GMII_NOT_1GBIT] = 0, 671 }; 672 673 static const u8 ksz8795_shifts[] = { 674 [VLAN_TABLE_MEMBERSHIP_S] = 7, 675 [VLAN_TABLE] = 16, 676 [STATIC_MAC_FWD_PORTS] = 16, 677 [STATIC_MAC_FID] = 24, 678 [DYNAMIC_MAC_ENTRIES_H] = 3, 679 [DYNAMIC_MAC_ENTRIES] = 29, 680 [DYNAMIC_MAC_FID] = 16, 681 [DYNAMIC_MAC_TIMESTAMP] = 27, 682 [DYNAMIC_MAC_SRC_PORT] = 24, 683 }; 684 685 static const u16 ksz8863_regs[] = { 686 [REG_SW_MAC_ADDR] = 0x70, 687 [REG_IND_CTRL_0] = 0x79, 688 [REG_IND_DATA_8] = 0x7B, 689 [REG_IND_DATA_CHECK] = 0x7B, 690 [REG_IND_DATA_HI] = 0x7C, 691 [REG_IND_DATA_LO] = 0x80, 692 [REG_IND_MIB_CHECK] = 0x80, 693 [P_FORCE_CTRL] = 0x0C, 694 [P_LINK_STATUS] = 0x0E, 695 [P_LOCAL_CTRL] = 0x0C, 696 [P_NEG_RESTART_CTRL] = 0x0D, 697 [P_REMOTE_STATUS] = 0x0E, 698 [P_SPEED_STATUS] = 0x0F, 699 [S_TAIL_TAG_CTRL] = 0x03, 700 [P_STP_CTRL] = 0x02, 701 [S_START_CTRL] = 0x01, 702 [S_BROADCAST_CTRL] = 0x06, 703 [S_MULTICAST_CTRL] = 0x04, 704 }; 705 706 static const u32 ksz8863_masks[] = { 707 [PORT_802_1P_REMAPPING] = BIT(3), 708 [SW_TAIL_TAG_ENABLE] = BIT(6), 709 [MIB_COUNTER_OVERFLOW] = BIT(7), 710 [MIB_COUNTER_VALID] = BIT(6), 711 [VLAN_TABLE_FID] = GENMASK(15, 12), 712 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 713 [VLAN_TABLE_VALID] = BIT(19), 714 [STATIC_MAC_TABLE_VALID] = BIT(19), 715 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 716 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 717 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 718 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 719 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 720 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 721 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 722 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 723 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 724 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 725 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 726 }; 727 728 static u8 ksz8863_shifts[] = { 729 [VLAN_TABLE_MEMBERSHIP_S] = 16, 730 [STATIC_MAC_FWD_PORTS] = 16, 731 [STATIC_MAC_FID] = 22, 732 [DYNAMIC_MAC_ENTRIES_H] = 8, 733 [DYNAMIC_MAC_ENTRIES] = 24, 734 [DYNAMIC_MAC_FID] = 16, 735 [DYNAMIC_MAC_TIMESTAMP] = 22, 736 [DYNAMIC_MAC_SRC_PORT] = 20, 737 }; 738 739 static const u16 ksz8895_regs[] = { 740 [REG_SW_MAC_ADDR] = 0x68, 741 [REG_IND_CTRL_0] = 0x6E, 742 [REG_IND_DATA_8] = 0x70, 743 [REG_IND_DATA_CHECK] = 0x72, 744 [REG_IND_DATA_HI] = 0x71, 745 [REG_IND_DATA_LO] = 0x75, 746 [REG_IND_MIB_CHECK] = 0x75, 747 [P_FORCE_CTRL] = 0x0C, 748 [P_LINK_STATUS] = 0x0E, 749 [P_LOCAL_CTRL] = 0x0C, 750 [P_NEG_RESTART_CTRL] = 0x0D, 751 [P_REMOTE_STATUS] = 0x0E, 752 [P_SPEED_STATUS] = 0x09, 753 [S_TAIL_TAG_CTRL] = 0x0C, 754 [P_STP_CTRL] = 0x02, 755 [S_START_CTRL] = 0x01, 756 [S_BROADCAST_CTRL] = 0x06, 757 [S_MULTICAST_CTRL] = 0x04, 758 }; 759 760 static const u32 ksz8895_masks[] = { 761 [PORT_802_1P_REMAPPING] = BIT(7), 762 [SW_TAIL_TAG_ENABLE] = BIT(1), 763 [MIB_COUNTER_OVERFLOW] = BIT(7), 764 [MIB_COUNTER_VALID] = BIT(6), 765 [VLAN_TABLE_FID] = GENMASK(6, 0), 766 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 767 [VLAN_TABLE_VALID] = BIT(12), 768 [STATIC_MAC_TABLE_VALID] = BIT(21), 769 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 770 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 771 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 772 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 773 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 774 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 775 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 776 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 777 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 778 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 779 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 780 }; 781 782 static const u8 ksz8895_shifts[] = { 783 [VLAN_TABLE_MEMBERSHIP_S] = 7, 784 [VLAN_TABLE] = 13, 785 [STATIC_MAC_FWD_PORTS] = 16, 786 [STATIC_MAC_FID] = 24, 787 [DYNAMIC_MAC_ENTRIES_H] = 3, 788 [DYNAMIC_MAC_ENTRIES] = 29, 789 [DYNAMIC_MAC_FID] = 16, 790 [DYNAMIC_MAC_TIMESTAMP] = 27, 791 [DYNAMIC_MAC_SRC_PORT] = 24, 792 }; 793 794 static const u16 ksz9477_regs[] = { 795 [REG_SW_MAC_ADDR] = 0x0302, 796 [P_STP_CTRL] = 0x0B04, 797 [S_START_CTRL] = 0x0300, 798 [S_BROADCAST_CTRL] = 0x0332, 799 [S_MULTICAST_CTRL] = 0x0331, 800 [P_XMII_CTRL_0] = 0x0300, 801 [P_XMII_CTRL_1] = 0x0301, 802 [REG_SW_PME_CTRL] = 0x0006, 803 [REG_PORT_PME_STATUS] = 0x0013, 804 [REG_PORT_PME_CTRL] = 0x0017, 805 }; 806 807 static const u32 ksz9477_masks[] = { 808 [ALU_STAT_WRITE] = 0, 809 [ALU_STAT_READ] = 1, 810 [P_MII_TX_FLOW_CTRL] = BIT(5), 811 [P_MII_RX_FLOW_CTRL] = BIT(3), 812 }; 813 814 static const u8 ksz9477_shifts[] = { 815 [ALU_STAT_INDEX] = 16, 816 }; 817 818 static const u8 ksz9477_xmii_ctrl0[] = { 819 [P_MII_100MBIT] = 1, 820 [P_MII_10MBIT] = 0, 821 [P_MII_FULL_DUPLEX] = 1, 822 [P_MII_HALF_DUPLEX] = 0, 823 }; 824 825 static const u8 ksz9477_xmii_ctrl1[] = { 826 [P_RGMII_SEL] = 0, 827 [P_RMII_SEL] = 1, 828 [P_GMII_SEL] = 2, 829 [P_MII_SEL] = 3, 830 [P_GMII_1GBIT] = 0, 831 [P_GMII_NOT_1GBIT] = 1, 832 }; 833 834 static const u32 lan937x_masks[] = { 835 [ALU_STAT_WRITE] = 1, 836 [ALU_STAT_READ] = 2, 837 [P_MII_TX_FLOW_CTRL] = BIT(5), 838 [P_MII_RX_FLOW_CTRL] = BIT(3), 839 }; 840 841 static const u8 lan937x_shifts[] = { 842 [ALU_STAT_INDEX] = 8, 843 }; 844 845 static const struct regmap_range ksz8563_valid_regs[] = { 846 regmap_reg_range(0x0000, 0x0003), 847 regmap_reg_range(0x0006, 0x0006), 848 regmap_reg_range(0x000f, 0x001f), 849 regmap_reg_range(0x0100, 0x0100), 850 regmap_reg_range(0x0104, 0x0107), 851 regmap_reg_range(0x010d, 0x010d), 852 regmap_reg_range(0x0110, 0x0113), 853 regmap_reg_range(0x0120, 0x012b), 854 regmap_reg_range(0x0201, 0x0201), 855 regmap_reg_range(0x0210, 0x0213), 856 regmap_reg_range(0x0300, 0x0300), 857 regmap_reg_range(0x0302, 0x031b), 858 regmap_reg_range(0x0320, 0x032b), 859 regmap_reg_range(0x0330, 0x0336), 860 regmap_reg_range(0x0338, 0x033e), 861 regmap_reg_range(0x0340, 0x035f), 862 regmap_reg_range(0x0370, 0x0370), 863 regmap_reg_range(0x0378, 0x0378), 864 regmap_reg_range(0x037c, 0x037d), 865 regmap_reg_range(0x0390, 0x0393), 866 regmap_reg_range(0x0400, 0x040e), 867 regmap_reg_range(0x0410, 0x042f), 868 regmap_reg_range(0x0500, 0x0519), 869 regmap_reg_range(0x0520, 0x054b), 870 regmap_reg_range(0x0550, 0x05b3), 871 872 /* port 1 */ 873 regmap_reg_range(0x1000, 0x1001), 874 regmap_reg_range(0x1004, 0x100b), 875 regmap_reg_range(0x1013, 0x1013), 876 regmap_reg_range(0x1017, 0x1017), 877 regmap_reg_range(0x101b, 0x101b), 878 regmap_reg_range(0x101f, 0x1021), 879 regmap_reg_range(0x1030, 0x1030), 880 regmap_reg_range(0x1100, 0x1111), 881 regmap_reg_range(0x111a, 0x111d), 882 regmap_reg_range(0x1122, 0x1127), 883 regmap_reg_range(0x112a, 0x112b), 884 regmap_reg_range(0x1136, 0x1139), 885 regmap_reg_range(0x113e, 0x113f), 886 regmap_reg_range(0x1400, 0x1401), 887 regmap_reg_range(0x1403, 0x1403), 888 regmap_reg_range(0x1410, 0x1417), 889 regmap_reg_range(0x1420, 0x1423), 890 regmap_reg_range(0x1500, 0x1507), 891 regmap_reg_range(0x1600, 0x1612), 892 regmap_reg_range(0x1800, 0x180f), 893 regmap_reg_range(0x1900, 0x1907), 894 regmap_reg_range(0x1914, 0x191b), 895 regmap_reg_range(0x1a00, 0x1a03), 896 regmap_reg_range(0x1a04, 0x1a08), 897 regmap_reg_range(0x1b00, 0x1b01), 898 regmap_reg_range(0x1b04, 0x1b04), 899 regmap_reg_range(0x1c00, 0x1c05), 900 regmap_reg_range(0x1c08, 0x1c1b), 901 902 /* port 2 */ 903 regmap_reg_range(0x2000, 0x2001), 904 regmap_reg_range(0x2004, 0x200b), 905 regmap_reg_range(0x2013, 0x2013), 906 regmap_reg_range(0x2017, 0x2017), 907 regmap_reg_range(0x201b, 0x201b), 908 regmap_reg_range(0x201f, 0x2021), 909 regmap_reg_range(0x2030, 0x2030), 910 regmap_reg_range(0x2100, 0x2111), 911 regmap_reg_range(0x211a, 0x211d), 912 regmap_reg_range(0x2122, 0x2127), 913 regmap_reg_range(0x212a, 0x212b), 914 regmap_reg_range(0x2136, 0x2139), 915 regmap_reg_range(0x213e, 0x213f), 916 regmap_reg_range(0x2400, 0x2401), 917 regmap_reg_range(0x2403, 0x2403), 918 regmap_reg_range(0x2410, 0x2417), 919 regmap_reg_range(0x2420, 0x2423), 920 regmap_reg_range(0x2500, 0x2507), 921 regmap_reg_range(0x2600, 0x2612), 922 regmap_reg_range(0x2800, 0x280f), 923 regmap_reg_range(0x2900, 0x2907), 924 regmap_reg_range(0x2914, 0x291b), 925 regmap_reg_range(0x2a00, 0x2a03), 926 regmap_reg_range(0x2a04, 0x2a08), 927 regmap_reg_range(0x2b00, 0x2b01), 928 regmap_reg_range(0x2b04, 0x2b04), 929 regmap_reg_range(0x2c00, 0x2c05), 930 regmap_reg_range(0x2c08, 0x2c1b), 931 932 /* port 3 */ 933 regmap_reg_range(0x3000, 0x3001), 934 regmap_reg_range(0x3004, 0x300b), 935 regmap_reg_range(0x3013, 0x3013), 936 regmap_reg_range(0x3017, 0x3017), 937 regmap_reg_range(0x301b, 0x301b), 938 regmap_reg_range(0x301f, 0x3021), 939 regmap_reg_range(0x3030, 0x3030), 940 regmap_reg_range(0x3300, 0x3301), 941 regmap_reg_range(0x3303, 0x3303), 942 regmap_reg_range(0x3400, 0x3401), 943 regmap_reg_range(0x3403, 0x3403), 944 regmap_reg_range(0x3410, 0x3417), 945 regmap_reg_range(0x3420, 0x3423), 946 regmap_reg_range(0x3500, 0x3507), 947 regmap_reg_range(0x3600, 0x3612), 948 regmap_reg_range(0x3800, 0x380f), 949 regmap_reg_range(0x3900, 0x3907), 950 regmap_reg_range(0x3914, 0x391b), 951 regmap_reg_range(0x3a00, 0x3a03), 952 regmap_reg_range(0x3a04, 0x3a08), 953 regmap_reg_range(0x3b00, 0x3b01), 954 regmap_reg_range(0x3b04, 0x3b04), 955 regmap_reg_range(0x3c00, 0x3c05), 956 regmap_reg_range(0x3c08, 0x3c1b), 957 }; 958 959 static const struct regmap_access_table ksz8563_register_set = { 960 .yes_ranges = ksz8563_valid_regs, 961 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 962 }; 963 964 static const struct regmap_range ksz9477_valid_regs[] = { 965 regmap_reg_range(0x0000, 0x0003), 966 regmap_reg_range(0x0006, 0x0006), 967 regmap_reg_range(0x0010, 0x001f), 968 regmap_reg_range(0x0100, 0x0100), 969 regmap_reg_range(0x0103, 0x0107), 970 regmap_reg_range(0x010d, 0x010d), 971 regmap_reg_range(0x0110, 0x0113), 972 regmap_reg_range(0x0120, 0x012b), 973 regmap_reg_range(0x0201, 0x0201), 974 regmap_reg_range(0x0210, 0x0213), 975 regmap_reg_range(0x0300, 0x0300), 976 regmap_reg_range(0x0302, 0x031b), 977 regmap_reg_range(0x0320, 0x032b), 978 regmap_reg_range(0x0330, 0x0336), 979 regmap_reg_range(0x0338, 0x033b), 980 regmap_reg_range(0x033e, 0x033e), 981 regmap_reg_range(0x0340, 0x035f), 982 regmap_reg_range(0x0370, 0x0370), 983 regmap_reg_range(0x0378, 0x0378), 984 regmap_reg_range(0x037c, 0x037d), 985 regmap_reg_range(0x0390, 0x0393), 986 regmap_reg_range(0x0400, 0x040e), 987 regmap_reg_range(0x0410, 0x042f), 988 regmap_reg_range(0x0444, 0x044b), 989 regmap_reg_range(0x0450, 0x046f), 990 regmap_reg_range(0x0500, 0x0519), 991 regmap_reg_range(0x0520, 0x054b), 992 regmap_reg_range(0x0550, 0x05b3), 993 regmap_reg_range(0x0604, 0x060b), 994 regmap_reg_range(0x0610, 0x0612), 995 regmap_reg_range(0x0614, 0x062c), 996 regmap_reg_range(0x0640, 0x0645), 997 regmap_reg_range(0x0648, 0x064d), 998 999 /* port 1 */ 1000 regmap_reg_range(0x1000, 0x1001), 1001 regmap_reg_range(0x1013, 0x1013), 1002 regmap_reg_range(0x1017, 0x1017), 1003 regmap_reg_range(0x101b, 0x101b), 1004 regmap_reg_range(0x101f, 0x1020), 1005 regmap_reg_range(0x1030, 0x1030), 1006 regmap_reg_range(0x1100, 0x1115), 1007 regmap_reg_range(0x111a, 0x111f), 1008 regmap_reg_range(0x1120, 0x112b), 1009 regmap_reg_range(0x1134, 0x113b), 1010 regmap_reg_range(0x113c, 0x113f), 1011 regmap_reg_range(0x1400, 0x1401), 1012 regmap_reg_range(0x1403, 0x1403), 1013 regmap_reg_range(0x1410, 0x1417), 1014 regmap_reg_range(0x1420, 0x1423), 1015 regmap_reg_range(0x1500, 0x1507), 1016 regmap_reg_range(0x1600, 0x1613), 1017 regmap_reg_range(0x1800, 0x180f), 1018 regmap_reg_range(0x1820, 0x1827), 1019 regmap_reg_range(0x1830, 0x1837), 1020 regmap_reg_range(0x1840, 0x184b), 1021 regmap_reg_range(0x1900, 0x1907), 1022 regmap_reg_range(0x1914, 0x191b), 1023 regmap_reg_range(0x1920, 0x1920), 1024 regmap_reg_range(0x1923, 0x1927), 1025 regmap_reg_range(0x1a00, 0x1a03), 1026 regmap_reg_range(0x1a04, 0x1a07), 1027 regmap_reg_range(0x1b00, 0x1b01), 1028 regmap_reg_range(0x1b04, 0x1b04), 1029 regmap_reg_range(0x1c00, 0x1c05), 1030 regmap_reg_range(0x1c08, 0x1c1b), 1031 1032 /* port 2 */ 1033 regmap_reg_range(0x2000, 0x2001), 1034 regmap_reg_range(0x2013, 0x2013), 1035 regmap_reg_range(0x2017, 0x2017), 1036 regmap_reg_range(0x201b, 0x201b), 1037 regmap_reg_range(0x201f, 0x2020), 1038 regmap_reg_range(0x2030, 0x2030), 1039 regmap_reg_range(0x2100, 0x2115), 1040 regmap_reg_range(0x211a, 0x211f), 1041 regmap_reg_range(0x2120, 0x212b), 1042 regmap_reg_range(0x2134, 0x213b), 1043 regmap_reg_range(0x213c, 0x213f), 1044 regmap_reg_range(0x2400, 0x2401), 1045 regmap_reg_range(0x2403, 0x2403), 1046 regmap_reg_range(0x2410, 0x2417), 1047 regmap_reg_range(0x2420, 0x2423), 1048 regmap_reg_range(0x2500, 0x2507), 1049 regmap_reg_range(0x2600, 0x2613), 1050 regmap_reg_range(0x2800, 0x280f), 1051 regmap_reg_range(0x2820, 0x2827), 1052 regmap_reg_range(0x2830, 0x2837), 1053 regmap_reg_range(0x2840, 0x284b), 1054 regmap_reg_range(0x2900, 0x2907), 1055 regmap_reg_range(0x2914, 0x291b), 1056 regmap_reg_range(0x2920, 0x2920), 1057 regmap_reg_range(0x2923, 0x2927), 1058 regmap_reg_range(0x2a00, 0x2a03), 1059 regmap_reg_range(0x2a04, 0x2a07), 1060 regmap_reg_range(0x2b00, 0x2b01), 1061 regmap_reg_range(0x2b04, 0x2b04), 1062 regmap_reg_range(0x2c00, 0x2c05), 1063 regmap_reg_range(0x2c08, 0x2c1b), 1064 1065 /* port 3 */ 1066 regmap_reg_range(0x3000, 0x3001), 1067 regmap_reg_range(0x3013, 0x3013), 1068 regmap_reg_range(0x3017, 0x3017), 1069 regmap_reg_range(0x301b, 0x301b), 1070 regmap_reg_range(0x301f, 0x3020), 1071 regmap_reg_range(0x3030, 0x3030), 1072 regmap_reg_range(0x3100, 0x3115), 1073 regmap_reg_range(0x311a, 0x311f), 1074 regmap_reg_range(0x3120, 0x312b), 1075 regmap_reg_range(0x3134, 0x313b), 1076 regmap_reg_range(0x313c, 0x313f), 1077 regmap_reg_range(0x3400, 0x3401), 1078 regmap_reg_range(0x3403, 0x3403), 1079 regmap_reg_range(0x3410, 0x3417), 1080 regmap_reg_range(0x3420, 0x3423), 1081 regmap_reg_range(0x3500, 0x3507), 1082 regmap_reg_range(0x3600, 0x3613), 1083 regmap_reg_range(0x3800, 0x380f), 1084 regmap_reg_range(0x3820, 0x3827), 1085 regmap_reg_range(0x3830, 0x3837), 1086 regmap_reg_range(0x3840, 0x384b), 1087 regmap_reg_range(0x3900, 0x3907), 1088 regmap_reg_range(0x3914, 0x391b), 1089 regmap_reg_range(0x3920, 0x3920), 1090 regmap_reg_range(0x3923, 0x3927), 1091 regmap_reg_range(0x3a00, 0x3a03), 1092 regmap_reg_range(0x3a04, 0x3a07), 1093 regmap_reg_range(0x3b00, 0x3b01), 1094 regmap_reg_range(0x3b04, 0x3b04), 1095 regmap_reg_range(0x3c00, 0x3c05), 1096 regmap_reg_range(0x3c08, 0x3c1b), 1097 1098 /* port 4 */ 1099 regmap_reg_range(0x4000, 0x4001), 1100 regmap_reg_range(0x4013, 0x4013), 1101 regmap_reg_range(0x4017, 0x4017), 1102 regmap_reg_range(0x401b, 0x401b), 1103 regmap_reg_range(0x401f, 0x4020), 1104 regmap_reg_range(0x4030, 0x4030), 1105 regmap_reg_range(0x4100, 0x4115), 1106 regmap_reg_range(0x411a, 0x411f), 1107 regmap_reg_range(0x4120, 0x412b), 1108 regmap_reg_range(0x4134, 0x413b), 1109 regmap_reg_range(0x413c, 0x413f), 1110 regmap_reg_range(0x4400, 0x4401), 1111 regmap_reg_range(0x4403, 0x4403), 1112 regmap_reg_range(0x4410, 0x4417), 1113 regmap_reg_range(0x4420, 0x4423), 1114 regmap_reg_range(0x4500, 0x4507), 1115 regmap_reg_range(0x4600, 0x4613), 1116 regmap_reg_range(0x4800, 0x480f), 1117 regmap_reg_range(0x4820, 0x4827), 1118 regmap_reg_range(0x4830, 0x4837), 1119 regmap_reg_range(0x4840, 0x484b), 1120 regmap_reg_range(0x4900, 0x4907), 1121 regmap_reg_range(0x4914, 0x491b), 1122 regmap_reg_range(0x4920, 0x4920), 1123 regmap_reg_range(0x4923, 0x4927), 1124 regmap_reg_range(0x4a00, 0x4a03), 1125 regmap_reg_range(0x4a04, 0x4a07), 1126 regmap_reg_range(0x4b00, 0x4b01), 1127 regmap_reg_range(0x4b04, 0x4b04), 1128 regmap_reg_range(0x4c00, 0x4c05), 1129 regmap_reg_range(0x4c08, 0x4c1b), 1130 1131 /* port 5 */ 1132 regmap_reg_range(0x5000, 0x5001), 1133 regmap_reg_range(0x5013, 0x5013), 1134 regmap_reg_range(0x5017, 0x5017), 1135 regmap_reg_range(0x501b, 0x501b), 1136 regmap_reg_range(0x501f, 0x5020), 1137 regmap_reg_range(0x5030, 0x5030), 1138 regmap_reg_range(0x5100, 0x5115), 1139 regmap_reg_range(0x511a, 0x511f), 1140 regmap_reg_range(0x5120, 0x512b), 1141 regmap_reg_range(0x5134, 0x513b), 1142 regmap_reg_range(0x513c, 0x513f), 1143 regmap_reg_range(0x5400, 0x5401), 1144 regmap_reg_range(0x5403, 0x5403), 1145 regmap_reg_range(0x5410, 0x5417), 1146 regmap_reg_range(0x5420, 0x5423), 1147 regmap_reg_range(0x5500, 0x5507), 1148 regmap_reg_range(0x5600, 0x5613), 1149 regmap_reg_range(0x5800, 0x580f), 1150 regmap_reg_range(0x5820, 0x5827), 1151 regmap_reg_range(0x5830, 0x5837), 1152 regmap_reg_range(0x5840, 0x584b), 1153 regmap_reg_range(0x5900, 0x5907), 1154 regmap_reg_range(0x5914, 0x591b), 1155 regmap_reg_range(0x5920, 0x5920), 1156 regmap_reg_range(0x5923, 0x5927), 1157 regmap_reg_range(0x5a00, 0x5a03), 1158 regmap_reg_range(0x5a04, 0x5a07), 1159 regmap_reg_range(0x5b00, 0x5b01), 1160 regmap_reg_range(0x5b04, 0x5b04), 1161 regmap_reg_range(0x5c00, 0x5c05), 1162 regmap_reg_range(0x5c08, 0x5c1b), 1163 1164 /* port 6 */ 1165 regmap_reg_range(0x6000, 0x6001), 1166 regmap_reg_range(0x6013, 0x6013), 1167 regmap_reg_range(0x6017, 0x6017), 1168 regmap_reg_range(0x601b, 0x601b), 1169 regmap_reg_range(0x601f, 0x6020), 1170 regmap_reg_range(0x6030, 0x6030), 1171 regmap_reg_range(0x6300, 0x6301), 1172 regmap_reg_range(0x6400, 0x6401), 1173 regmap_reg_range(0x6403, 0x6403), 1174 regmap_reg_range(0x6410, 0x6417), 1175 regmap_reg_range(0x6420, 0x6423), 1176 regmap_reg_range(0x6500, 0x6507), 1177 regmap_reg_range(0x6600, 0x6613), 1178 regmap_reg_range(0x6800, 0x680f), 1179 regmap_reg_range(0x6820, 0x6827), 1180 regmap_reg_range(0x6830, 0x6837), 1181 regmap_reg_range(0x6840, 0x684b), 1182 regmap_reg_range(0x6900, 0x6907), 1183 regmap_reg_range(0x6914, 0x691b), 1184 regmap_reg_range(0x6920, 0x6920), 1185 regmap_reg_range(0x6923, 0x6927), 1186 regmap_reg_range(0x6a00, 0x6a03), 1187 regmap_reg_range(0x6a04, 0x6a07), 1188 regmap_reg_range(0x6b00, 0x6b01), 1189 regmap_reg_range(0x6b04, 0x6b04), 1190 regmap_reg_range(0x6c00, 0x6c05), 1191 regmap_reg_range(0x6c08, 0x6c1b), 1192 1193 /* port 7 */ 1194 regmap_reg_range(0x7000, 0x7001), 1195 regmap_reg_range(0x7013, 0x7013), 1196 regmap_reg_range(0x7017, 0x7017), 1197 regmap_reg_range(0x701b, 0x701b), 1198 regmap_reg_range(0x701f, 0x7020), 1199 regmap_reg_range(0x7030, 0x7030), 1200 regmap_reg_range(0x7200, 0x7207), 1201 regmap_reg_range(0x7300, 0x7301), 1202 regmap_reg_range(0x7400, 0x7401), 1203 regmap_reg_range(0x7403, 0x7403), 1204 regmap_reg_range(0x7410, 0x7417), 1205 regmap_reg_range(0x7420, 0x7423), 1206 regmap_reg_range(0x7500, 0x7507), 1207 regmap_reg_range(0x7600, 0x7613), 1208 regmap_reg_range(0x7800, 0x780f), 1209 regmap_reg_range(0x7820, 0x7827), 1210 regmap_reg_range(0x7830, 0x7837), 1211 regmap_reg_range(0x7840, 0x784b), 1212 regmap_reg_range(0x7900, 0x7907), 1213 regmap_reg_range(0x7914, 0x791b), 1214 regmap_reg_range(0x7920, 0x7920), 1215 regmap_reg_range(0x7923, 0x7927), 1216 regmap_reg_range(0x7a00, 0x7a03), 1217 regmap_reg_range(0x7a04, 0x7a07), 1218 regmap_reg_range(0x7b00, 0x7b01), 1219 regmap_reg_range(0x7b04, 0x7b04), 1220 regmap_reg_range(0x7c00, 0x7c05), 1221 regmap_reg_range(0x7c08, 0x7c1b), 1222 }; 1223 1224 static const struct regmap_access_table ksz9477_register_set = { 1225 .yes_ranges = ksz9477_valid_regs, 1226 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 1227 }; 1228 1229 static const struct regmap_range ksz9896_valid_regs[] = { 1230 regmap_reg_range(0x0000, 0x0003), 1231 regmap_reg_range(0x0006, 0x0006), 1232 regmap_reg_range(0x0010, 0x001f), 1233 regmap_reg_range(0x0100, 0x0100), 1234 regmap_reg_range(0x0103, 0x0107), 1235 regmap_reg_range(0x010d, 0x010d), 1236 regmap_reg_range(0x0110, 0x0113), 1237 regmap_reg_range(0x0120, 0x0127), 1238 regmap_reg_range(0x0201, 0x0201), 1239 regmap_reg_range(0x0210, 0x0213), 1240 regmap_reg_range(0x0300, 0x0300), 1241 regmap_reg_range(0x0302, 0x030b), 1242 regmap_reg_range(0x0310, 0x031b), 1243 regmap_reg_range(0x0320, 0x032b), 1244 regmap_reg_range(0x0330, 0x0336), 1245 regmap_reg_range(0x0338, 0x033b), 1246 regmap_reg_range(0x033e, 0x033e), 1247 regmap_reg_range(0x0340, 0x035f), 1248 regmap_reg_range(0x0370, 0x0370), 1249 regmap_reg_range(0x0378, 0x0378), 1250 regmap_reg_range(0x037c, 0x037d), 1251 regmap_reg_range(0x0390, 0x0393), 1252 regmap_reg_range(0x0400, 0x040e), 1253 regmap_reg_range(0x0410, 0x042f), 1254 1255 /* port 1 */ 1256 regmap_reg_range(0x1000, 0x1001), 1257 regmap_reg_range(0x1013, 0x1013), 1258 regmap_reg_range(0x1017, 0x1017), 1259 regmap_reg_range(0x101b, 0x101b), 1260 regmap_reg_range(0x101f, 0x1020), 1261 regmap_reg_range(0x1030, 0x1030), 1262 regmap_reg_range(0x1100, 0x1115), 1263 regmap_reg_range(0x111a, 0x111f), 1264 regmap_reg_range(0x1120, 0x112b), 1265 regmap_reg_range(0x1134, 0x113b), 1266 regmap_reg_range(0x113c, 0x113f), 1267 regmap_reg_range(0x1400, 0x1401), 1268 regmap_reg_range(0x1403, 0x1403), 1269 regmap_reg_range(0x1410, 0x1417), 1270 regmap_reg_range(0x1420, 0x1423), 1271 regmap_reg_range(0x1500, 0x1507), 1272 regmap_reg_range(0x1600, 0x1612), 1273 regmap_reg_range(0x1800, 0x180f), 1274 regmap_reg_range(0x1820, 0x1827), 1275 regmap_reg_range(0x1830, 0x1837), 1276 regmap_reg_range(0x1840, 0x184b), 1277 regmap_reg_range(0x1900, 0x1907), 1278 regmap_reg_range(0x1914, 0x1915), 1279 regmap_reg_range(0x1a00, 0x1a03), 1280 regmap_reg_range(0x1a04, 0x1a07), 1281 regmap_reg_range(0x1b00, 0x1b01), 1282 regmap_reg_range(0x1b04, 0x1b04), 1283 1284 /* port 2 */ 1285 regmap_reg_range(0x2000, 0x2001), 1286 regmap_reg_range(0x2013, 0x2013), 1287 regmap_reg_range(0x2017, 0x2017), 1288 regmap_reg_range(0x201b, 0x201b), 1289 regmap_reg_range(0x201f, 0x2020), 1290 regmap_reg_range(0x2030, 0x2030), 1291 regmap_reg_range(0x2100, 0x2115), 1292 regmap_reg_range(0x211a, 0x211f), 1293 regmap_reg_range(0x2120, 0x212b), 1294 regmap_reg_range(0x2134, 0x213b), 1295 regmap_reg_range(0x213c, 0x213f), 1296 regmap_reg_range(0x2400, 0x2401), 1297 regmap_reg_range(0x2403, 0x2403), 1298 regmap_reg_range(0x2410, 0x2417), 1299 regmap_reg_range(0x2420, 0x2423), 1300 regmap_reg_range(0x2500, 0x2507), 1301 regmap_reg_range(0x2600, 0x2612), 1302 regmap_reg_range(0x2800, 0x280f), 1303 regmap_reg_range(0x2820, 0x2827), 1304 regmap_reg_range(0x2830, 0x2837), 1305 regmap_reg_range(0x2840, 0x284b), 1306 regmap_reg_range(0x2900, 0x2907), 1307 regmap_reg_range(0x2914, 0x2915), 1308 regmap_reg_range(0x2a00, 0x2a03), 1309 regmap_reg_range(0x2a04, 0x2a07), 1310 regmap_reg_range(0x2b00, 0x2b01), 1311 regmap_reg_range(0x2b04, 0x2b04), 1312 1313 /* port 3 */ 1314 regmap_reg_range(0x3000, 0x3001), 1315 regmap_reg_range(0x3013, 0x3013), 1316 regmap_reg_range(0x3017, 0x3017), 1317 regmap_reg_range(0x301b, 0x301b), 1318 regmap_reg_range(0x301f, 0x3020), 1319 regmap_reg_range(0x3030, 0x3030), 1320 regmap_reg_range(0x3100, 0x3115), 1321 regmap_reg_range(0x311a, 0x311f), 1322 regmap_reg_range(0x3120, 0x312b), 1323 regmap_reg_range(0x3134, 0x313b), 1324 regmap_reg_range(0x313c, 0x313f), 1325 regmap_reg_range(0x3400, 0x3401), 1326 regmap_reg_range(0x3403, 0x3403), 1327 regmap_reg_range(0x3410, 0x3417), 1328 regmap_reg_range(0x3420, 0x3423), 1329 regmap_reg_range(0x3500, 0x3507), 1330 regmap_reg_range(0x3600, 0x3612), 1331 regmap_reg_range(0x3800, 0x380f), 1332 regmap_reg_range(0x3820, 0x3827), 1333 regmap_reg_range(0x3830, 0x3837), 1334 regmap_reg_range(0x3840, 0x384b), 1335 regmap_reg_range(0x3900, 0x3907), 1336 regmap_reg_range(0x3914, 0x3915), 1337 regmap_reg_range(0x3a00, 0x3a03), 1338 regmap_reg_range(0x3a04, 0x3a07), 1339 regmap_reg_range(0x3b00, 0x3b01), 1340 regmap_reg_range(0x3b04, 0x3b04), 1341 1342 /* port 4 */ 1343 regmap_reg_range(0x4000, 0x4001), 1344 regmap_reg_range(0x4013, 0x4013), 1345 regmap_reg_range(0x4017, 0x4017), 1346 regmap_reg_range(0x401b, 0x401b), 1347 regmap_reg_range(0x401f, 0x4020), 1348 regmap_reg_range(0x4030, 0x4030), 1349 regmap_reg_range(0x4100, 0x4115), 1350 regmap_reg_range(0x411a, 0x411f), 1351 regmap_reg_range(0x4120, 0x412b), 1352 regmap_reg_range(0x4134, 0x413b), 1353 regmap_reg_range(0x413c, 0x413f), 1354 regmap_reg_range(0x4400, 0x4401), 1355 regmap_reg_range(0x4403, 0x4403), 1356 regmap_reg_range(0x4410, 0x4417), 1357 regmap_reg_range(0x4420, 0x4423), 1358 regmap_reg_range(0x4500, 0x4507), 1359 regmap_reg_range(0x4600, 0x4612), 1360 regmap_reg_range(0x4800, 0x480f), 1361 regmap_reg_range(0x4820, 0x4827), 1362 regmap_reg_range(0x4830, 0x4837), 1363 regmap_reg_range(0x4840, 0x484b), 1364 regmap_reg_range(0x4900, 0x4907), 1365 regmap_reg_range(0x4914, 0x4915), 1366 regmap_reg_range(0x4a00, 0x4a03), 1367 regmap_reg_range(0x4a04, 0x4a07), 1368 regmap_reg_range(0x4b00, 0x4b01), 1369 regmap_reg_range(0x4b04, 0x4b04), 1370 1371 /* port 5 */ 1372 regmap_reg_range(0x5000, 0x5001), 1373 regmap_reg_range(0x5013, 0x5013), 1374 regmap_reg_range(0x5017, 0x5017), 1375 regmap_reg_range(0x501b, 0x501b), 1376 regmap_reg_range(0x501f, 0x5020), 1377 regmap_reg_range(0x5030, 0x5030), 1378 regmap_reg_range(0x5100, 0x5115), 1379 regmap_reg_range(0x511a, 0x511f), 1380 regmap_reg_range(0x5120, 0x512b), 1381 regmap_reg_range(0x5134, 0x513b), 1382 regmap_reg_range(0x513c, 0x513f), 1383 regmap_reg_range(0x5400, 0x5401), 1384 regmap_reg_range(0x5403, 0x5403), 1385 regmap_reg_range(0x5410, 0x5417), 1386 regmap_reg_range(0x5420, 0x5423), 1387 regmap_reg_range(0x5500, 0x5507), 1388 regmap_reg_range(0x5600, 0x5612), 1389 regmap_reg_range(0x5800, 0x580f), 1390 regmap_reg_range(0x5820, 0x5827), 1391 regmap_reg_range(0x5830, 0x5837), 1392 regmap_reg_range(0x5840, 0x584b), 1393 regmap_reg_range(0x5900, 0x5907), 1394 regmap_reg_range(0x5914, 0x5915), 1395 regmap_reg_range(0x5a00, 0x5a03), 1396 regmap_reg_range(0x5a04, 0x5a07), 1397 regmap_reg_range(0x5b00, 0x5b01), 1398 regmap_reg_range(0x5b04, 0x5b04), 1399 1400 /* port 6 */ 1401 regmap_reg_range(0x6000, 0x6001), 1402 regmap_reg_range(0x6013, 0x6013), 1403 regmap_reg_range(0x6017, 0x6017), 1404 regmap_reg_range(0x601b, 0x601b), 1405 regmap_reg_range(0x601f, 0x6020), 1406 regmap_reg_range(0x6030, 0x6030), 1407 regmap_reg_range(0x6100, 0x6115), 1408 regmap_reg_range(0x611a, 0x611f), 1409 regmap_reg_range(0x6120, 0x612b), 1410 regmap_reg_range(0x6134, 0x613b), 1411 regmap_reg_range(0x613c, 0x613f), 1412 regmap_reg_range(0x6300, 0x6301), 1413 regmap_reg_range(0x6400, 0x6401), 1414 regmap_reg_range(0x6403, 0x6403), 1415 regmap_reg_range(0x6410, 0x6417), 1416 regmap_reg_range(0x6420, 0x6423), 1417 regmap_reg_range(0x6500, 0x6507), 1418 regmap_reg_range(0x6600, 0x6612), 1419 regmap_reg_range(0x6800, 0x680f), 1420 regmap_reg_range(0x6820, 0x6827), 1421 regmap_reg_range(0x6830, 0x6837), 1422 regmap_reg_range(0x6840, 0x684b), 1423 regmap_reg_range(0x6900, 0x6907), 1424 regmap_reg_range(0x6914, 0x6915), 1425 regmap_reg_range(0x6a00, 0x6a03), 1426 regmap_reg_range(0x6a04, 0x6a07), 1427 regmap_reg_range(0x6b00, 0x6b01), 1428 regmap_reg_range(0x6b04, 0x6b04), 1429 }; 1430 1431 static const struct regmap_access_table ksz9896_register_set = { 1432 .yes_ranges = ksz9896_valid_regs, 1433 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1434 }; 1435 1436 static const struct regmap_range ksz8873_valid_regs[] = { 1437 regmap_reg_range(0x00, 0x01), 1438 /* global control register */ 1439 regmap_reg_range(0x02, 0x0f), 1440 1441 /* port registers */ 1442 regmap_reg_range(0x10, 0x1d), 1443 regmap_reg_range(0x1e, 0x1f), 1444 regmap_reg_range(0x20, 0x2d), 1445 regmap_reg_range(0x2e, 0x2f), 1446 regmap_reg_range(0x30, 0x39), 1447 regmap_reg_range(0x3f, 0x3f), 1448 1449 /* advanced control registers */ 1450 regmap_reg_range(0x60, 0x6f), 1451 regmap_reg_range(0x70, 0x75), 1452 regmap_reg_range(0x76, 0x78), 1453 regmap_reg_range(0x79, 0x7a), 1454 regmap_reg_range(0x7b, 0x83), 1455 regmap_reg_range(0x8e, 0x99), 1456 regmap_reg_range(0x9a, 0xa5), 1457 regmap_reg_range(0xa6, 0xa6), 1458 regmap_reg_range(0xa7, 0xaa), 1459 regmap_reg_range(0xab, 0xae), 1460 regmap_reg_range(0xaf, 0xba), 1461 regmap_reg_range(0xbb, 0xbc), 1462 regmap_reg_range(0xbd, 0xbd), 1463 regmap_reg_range(0xc0, 0xc0), 1464 regmap_reg_range(0xc2, 0xc2), 1465 regmap_reg_range(0xc3, 0xc3), 1466 regmap_reg_range(0xc4, 0xc4), 1467 regmap_reg_range(0xc6, 0xc6), 1468 }; 1469 1470 static const struct regmap_access_table ksz8873_register_set = { 1471 .yes_ranges = ksz8873_valid_regs, 1472 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), 1473 }; 1474 1475 const struct ksz_chip_data ksz_switch_chips[] = { 1476 [KSZ8463] = { 1477 .chip_id = KSZ8463_CHIP_ID, 1478 .dev_name = "KSZ8463", 1479 .num_vlans = 16, 1480 .num_alus = 0, 1481 .num_statics = 8, 1482 .cpu_ports = 0x4, /* can be configured as cpu port */ 1483 .port_cnt = 3, 1484 .num_tx_queues = 4, 1485 .num_ipms = 4, 1486 .ops = &ksz8463_dev_ops, 1487 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1488 .mib_names = ksz88xx_mib_names, 1489 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1490 .reg_mib_cnt = MIB_COUNTER_NUM, 1491 .regs = ksz8463_regs, 1492 .masks = ksz8463_masks, 1493 .shifts = ksz8463_shifts, 1494 .supports_mii = {false, false, true}, 1495 .supports_rmii = {false, false, true}, 1496 .internal_phy = {true, true, false}, 1497 }, 1498 1499 [KSZ8563] = { 1500 .chip_id = KSZ8563_CHIP_ID, 1501 .dev_name = "KSZ8563", 1502 .num_vlans = 4096, 1503 .num_alus = 4096, 1504 .num_statics = 16, 1505 .cpu_ports = 0x07, /* can be configured as cpu port */ 1506 .port_cnt = 3, /* total port count */ 1507 .port_nirqs = 3, 1508 .num_tx_queues = 4, 1509 .num_ipms = 8, 1510 .tc_cbs_supported = true, 1511 .ops = &ksz9477_dev_ops, 1512 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1513 .mib_names = ksz9477_mib_names, 1514 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1515 .reg_mib_cnt = MIB_COUNTER_NUM, 1516 .regs = ksz9477_regs, 1517 .masks = ksz9477_masks, 1518 .shifts = ksz9477_shifts, 1519 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1520 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1521 .supports_mii = {false, false, true}, 1522 .supports_rmii = {false, false, true}, 1523 .supports_rgmii = {false, false, true}, 1524 .internal_phy = {true, true, false}, 1525 .gbit_capable = {false, false, true}, 1526 .ptp_capable = true, 1527 .wr_table = &ksz8563_register_set, 1528 .rd_table = &ksz8563_register_set, 1529 }, 1530 1531 [KSZ8795] = { 1532 .chip_id = KSZ8795_CHIP_ID, 1533 .dev_name = "KSZ8795", 1534 .num_vlans = 4096, 1535 .num_alus = 0, 1536 .num_statics = 32, 1537 .cpu_ports = 0x10, /* can be configured as cpu port */ 1538 .port_cnt = 5, /* total cpu and user ports */ 1539 .num_tx_queues = 4, 1540 .num_ipms = 4, 1541 .ops = &ksz87xx_dev_ops, 1542 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1543 .ksz87xx_eee_link_erratum = true, 1544 .mib_names = ksz9477_mib_names, 1545 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1546 .reg_mib_cnt = MIB_COUNTER_NUM, 1547 .regs = ksz8795_regs, 1548 .masks = ksz8795_masks, 1549 .shifts = ksz8795_shifts, 1550 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1551 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1552 .supports_mii = {false, false, false, false, true}, 1553 .supports_rmii = {false, false, false, false, true}, 1554 .supports_rgmii = {false, false, false, false, true}, 1555 .internal_phy = {true, true, true, true, false}, 1556 }, 1557 1558 [KSZ8794] = { 1559 /* WARNING 1560 * ======= 1561 * KSZ8794 is similar to KSZ8795, except the port map 1562 * contains a gap between external and CPU ports, the 1563 * port map is NOT continuous. The per-port register 1564 * map is shifted accordingly too, i.e. registers at 1565 * offset 0x40 are NOT used on KSZ8794 and they ARE 1566 * used on KSZ8795 for external port 3. 1567 * external cpu 1568 * KSZ8794 0,1,2 4 1569 * KSZ8795 0,1,2,3 4 1570 * KSZ8765 0,1,2,3 4 1571 * port_cnt is configured as 5, even though it is 4 1572 */ 1573 .chip_id = KSZ8794_CHIP_ID, 1574 .dev_name = "KSZ8794", 1575 .num_vlans = 4096, 1576 .num_alus = 0, 1577 .num_statics = 32, 1578 .cpu_ports = 0x10, /* can be configured as cpu port */ 1579 .port_cnt = 5, /* total cpu and user ports */ 1580 .num_tx_queues = 4, 1581 .num_ipms = 4, 1582 .ops = &ksz87xx_dev_ops, 1583 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1584 .ksz87xx_eee_link_erratum = true, 1585 .mib_names = ksz9477_mib_names, 1586 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1587 .reg_mib_cnt = MIB_COUNTER_NUM, 1588 .regs = ksz8795_regs, 1589 .masks = ksz8795_masks, 1590 .shifts = ksz8795_shifts, 1591 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1592 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1593 .supports_mii = {false, false, false, false, true}, 1594 .supports_rmii = {false, false, false, false, true}, 1595 .supports_rgmii = {false, false, false, false, true}, 1596 .internal_phy = {true, true, true, false, false}, 1597 }, 1598 1599 [KSZ8765] = { 1600 .chip_id = KSZ8765_CHIP_ID, 1601 .dev_name = "KSZ8765", 1602 .num_vlans = 4096, 1603 .num_alus = 0, 1604 .num_statics = 32, 1605 .cpu_ports = 0x10, /* can be configured as cpu port */ 1606 .port_cnt = 5, /* total cpu and user ports */ 1607 .num_tx_queues = 4, 1608 .num_ipms = 4, 1609 .ops = &ksz87xx_dev_ops, 1610 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1611 .ksz87xx_eee_link_erratum = true, 1612 .mib_names = ksz9477_mib_names, 1613 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1614 .reg_mib_cnt = MIB_COUNTER_NUM, 1615 .regs = ksz8795_regs, 1616 .masks = ksz8795_masks, 1617 .shifts = ksz8795_shifts, 1618 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1619 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1620 .supports_mii = {false, false, false, false, true}, 1621 .supports_rmii = {false, false, false, false, true}, 1622 .supports_rgmii = {false, false, false, false, true}, 1623 .internal_phy = {true, true, true, true, false}, 1624 }, 1625 1626 [KSZ88X3] = { 1627 .chip_id = KSZ88X3_CHIP_ID, 1628 .dev_name = "KSZ8863/KSZ8873", 1629 .num_vlans = 16, 1630 .num_alus = 0, 1631 .num_statics = 8, 1632 .cpu_ports = 0x4, /* can be configured as cpu port */ 1633 .port_cnt = 3, 1634 .num_tx_queues = 4, 1635 .num_ipms = 4, 1636 .ops = &ksz88xx_dev_ops, 1637 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1638 .mib_names = ksz88xx_mib_names, 1639 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1640 .reg_mib_cnt = MIB_COUNTER_NUM, 1641 .regs = ksz8863_regs, 1642 .masks = ksz8863_masks, 1643 .shifts = ksz8863_shifts, 1644 .supports_mii = {false, false, true}, 1645 .supports_rmii = {false, false, true}, 1646 .internal_phy = {true, true, false}, 1647 .wr_table = &ksz8873_register_set, 1648 .rd_table = &ksz8873_register_set, 1649 }, 1650 1651 [KSZ8864] = { 1652 /* WARNING 1653 * ======= 1654 * KSZ8864 is similar to KSZ8895, except the first port 1655 * does not exist. 1656 * external cpu 1657 * KSZ8864 1,2,3 4 1658 * KSZ8895 0,1,2,3 4 1659 * port_cnt is configured as 5, even though it is 4 1660 */ 1661 .chip_id = KSZ8864_CHIP_ID, 1662 .dev_name = "KSZ8864", 1663 .num_vlans = 4096, 1664 .num_alus = 0, 1665 .num_statics = 32, 1666 .cpu_ports = 0x10, /* can be configured as cpu port */ 1667 .port_cnt = 5, /* total cpu and user ports */ 1668 .num_tx_queues = 4, 1669 .num_ipms = 4, 1670 .ops = &ksz88xx_dev_ops, 1671 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1672 .mib_names = ksz88xx_mib_names, 1673 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1674 .reg_mib_cnt = MIB_COUNTER_NUM, 1675 .regs = ksz8895_regs, 1676 .masks = ksz8895_masks, 1677 .shifts = ksz8895_shifts, 1678 .supports_mii = {false, false, false, false, true}, 1679 .supports_rmii = {false, false, false, false, true}, 1680 .internal_phy = {false, true, true, true, false}, 1681 }, 1682 1683 [KSZ8895] = { 1684 .chip_id = KSZ8895_CHIP_ID, 1685 .dev_name = "KSZ8895", 1686 .num_vlans = 4096, 1687 .num_alus = 0, 1688 .num_statics = 32, 1689 .cpu_ports = 0x10, /* can be configured as cpu port */ 1690 .port_cnt = 5, /* total cpu and user ports */ 1691 .num_tx_queues = 4, 1692 .num_ipms = 4, 1693 .ops = &ksz88xx_dev_ops, 1694 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1695 .mib_names = ksz88xx_mib_names, 1696 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1697 .reg_mib_cnt = MIB_COUNTER_NUM, 1698 .regs = ksz8895_regs, 1699 .masks = ksz8895_masks, 1700 .shifts = ksz8895_shifts, 1701 .supports_mii = {false, false, false, false, true}, 1702 .supports_rmii = {false, false, false, false, true}, 1703 .internal_phy = {true, true, true, true, false}, 1704 }, 1705 1706 [KSZ9477] = { 1707 .chip_id = KSZ9477_CHIP_ID, 1708 .dev_name = "KSZ9477", 1709 .num_vlans = 4096, 1710 .num_alus = 4096, 1711 .num_statics = 16, 1712 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1713 .port_cnt = 7, /* total physical port count */ 1714 .port_nirqs = 4, 1715 .num_tx_queues = 4, 1716 .num_ipms = 8, 1717 .tc_cbs_supported = true, 1718 .ops = &ksz9477_dev_ops, 1719 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1720 .phy_errata_9477 = true, 1721 .mib_names = ksz9477_mib_names, 1722 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1723 .reg_mib_cnt = MIB_COUNTER_NUM, 1724 .regs = ksz9477_regs, 1725 .masks = ksz9477_masks, 1726 .shifts = ksz9477_shifts, 1727 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1728 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1729 .supports_mii = {false, false, false, false, 1730 false, true, false}, 1731 .supports_rmii = {false, false, false, false, 1732 false, true, false}, 1733 .supports_rgmii = {false, false, false, false, 1734 false, true, false}, 1735 .internal_phy = {true, true, true, true, 1736 true, false, false}, 1737 .gbit_capable = {true, true, true, true, true, true, true}, 1738 .ptp_capable = true, 1739 .sgmii_port = 7, 1740 .wr_table = &ksz9477_register_set, 1741 .rd_table = &ksz9477_register_set, 1742 }, 1743 1744 [KSZ9896] = { 1745 .chip_id = KSZ9896_CHIP_ID, 1746 .dev_name = "KSZ9896", 1747 .num_vlans = 4096, 1748 .num_alus = 4096, 1749 .num_statics = 16, 1750 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1751 .port_cnt = 6, /* total physical port count */ 1752 .port_nirqs = 2, 1753 .num_tx_queues = 4, 1754 .num_ipms = 8, 1755 .ops = &ksz9477_dev_ops, 1756 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1757 .phy_errata_9477 = true, 1758 .mib_names = ksz9477_mib_names, 1759 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1760 .reg_mib_cnt = MIB_COUNTER_NUM, 1761 .regs = ksz9477_regs, 1762 .masks = ksz9477_masks, 1763 .shifts = ksz9477_shifts, 1764 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1765 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1766 .supports_mii = {false, false, false, false, 1767 false, true}, 1768 .supports_rmii = {false, false, false, false, 1769 false, true}, 1770 .supports_rgmii = {false, false, false, false, 1771 false, true}, 1772 .internal_phy = {true, true, true, true, 1773 true, false}, 1774 .gbit_capable = {true, true, true, true, true, true}, 1775 .wr_table = &ksz9896_register_set, 1776 .rd_table = &ksz9896_register_set, 1777 }, 1778 1779 [KSZ9897] = { 1780 .chip_id = KSZ9897_CHIP_ID, 1781 .dev_name = "KSZ9897", 1782 .num_vlans = 4096, 1783 .num_alus = 4096, 1784 .num_statics = 16, 1785 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1786 .port_cnt = 7, /* total physical port count */ 1787 .port_nirqs = 2, 1788 .num_tx_queues = 4, 1789 .num_ipms = 8, 1790 .ops = &ksz9477_dev_ops, 1791 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1792 .phy_errata_9477 = true, 1793 .mib_names = ksz9477_mib_names, 1794 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1795 .reg_mib_cnt = MIB_COUNTER_NUM, 1796 .regs = ksz9477_regs, 1797 .masks = ksz9477_masks, 1798 .shifts = ksz9477_shifts, 1799 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1800 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1801 .supports_mii = {false, false, false, false, 1802 false, true, true}, 1803 .supports_rmii = {false, false, false, false, 1804 false, true, true}, 1805 .supports_rgmii = {false, false, false, false, 1806 false, true, true}, 1807 .internal_phy = {true, true, true, true, 1808 true, false, false}, 1809 .gbit_capable = {true, true, true, true, true, true, true}, 1810 }, 1811 1812 [KSZ9893] = { 1813 .chip_id = KSZ9893_CHIP_ID, 1814 .dev_name = "KSZ9893", 1815 .num_vlans = 4096, 1816 .num_alus = 4096, 1817 .num_statics = 16, 1818 .cpu_ports = 0x07, /* can be configured as cpu port */ 1819 .port_cnt = 3, /* total port count */ 1820 .port_nirqs = 2, 1821 .num_tx_queues = 4, 1822 .num_ipms = 8, 1823 .ops = &ksz9477_dev_ops, 1824 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1825 .mib_names = ksz9477_mib_names, 1826 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1827 .reg_mib_cnt = MIB_COUNTER_NUM, 1828 .regs = ksz9477_regs, 1829 .masks = ksz9477_masks, 1830 .shifts = ksz9477_shifts, 1831 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1832 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1833 .supports_mii = {false, false, true}, 1834 .supports_rmii = {false, false, true}, 1835 .supports_rgmii = {false, false, true}, 1836 .internal_phy = {true, true, false}, 1837 .gbit_capable = {true, true, true}, 1838 }, 1839 1840 [KSZ9563] = { 1841 .chip_id = KSZ9563_CHIP_ID, 1842 .dev_name = "KSZ9563", 1843 .num_vlans = 4096, 1844 .num_alus = 4096, 1845 .num_statics = 16, 1846 .cpu_ports = 0x07, /* can be configured as cpu port */ 1847 .port_cnt = 3, /* total port count */ 1848 .port_nirqs = 3, 1849 .num_tx_queues = 4, 1850 .num_ipms = 8, 1851 .tc_cbs_supported = true, 1852 .ops = &ksz9477_dev_ops, 1853 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1854 .mib_names = ksz9477_mib_names, 1855 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1856 .reg_mib_cnt = MIB_COUNTER_NUM, 1857 .regs = ksz9477_regs, 1858 .masks = ksz9477_masks, 1859 .shifts = ksz9477_shifts, 1860 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1861 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1862 .supports_mii = {false, false, true}, 1863 .supports_rmii = {false, false, true}, 1864 .supports_rgmii = {false, false, true}, 1865 .internal_phy = {true, true, false}, 1866 .gbit_capable = {true, true, true}, 1867 .ptp_capable = true, 1868 }, 1869 1870 [KSZ8567] = { 1871 .chip_id = KSZ8567_CHIP_ID, 1872 .dev_name = "KSZ8567", 1873 .num_vlans = 4096, 1874 .num_alus = 4096, 1875 .num_statics = 16, 1876 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1877 .port_cnt = 7, /* total port count */ 1878 .port_nirqs = 3, 1879 .num_tx_queues = 4, 1880 .num_ipms = 8, 1881 .tc_cbs_supported = true, 1882 .ops = &ksz9477_dev_ops, 1883 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1884 .phy_errata_9477 = true, 1885 .mib_names = ksz9477_mib_names, 1886 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1887 .reg_mib_cnt = MIB_COUNTER_NUM, 1888 .regs = ksz9477_regs, 1889 .masks = ksz9477_masks, 1890 .shifts = ksz9477_shifts, 1891 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1892 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1893 .supports_mii = {false, false, false, false, 1894 false, true, true}, 1895 .supports_rmii = {false, false, false, false, 1896 false, true, true}, 1897 .supports_rgmii = {false, false, false, false, 1898 false, true, true}, 1899 .internal_phy = {true, true, true, true, 1900 true, false, false}, 1901 .gbit_capable = {false, false, false, false, false, 1902 true, true}, 1903 .ptp_capable = true, 1904 }, 1905 1906 [KSZ9567] = { 1907 .chip_id = KSZ9567_CHIP_ID, 1908 .dev_name = "KSZ9567", 1909 .num_vlans = 4096, 1910 .num_alus = 4096, 1911 .num_statics = 16, 1912 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1913 .port_cnt = 7, /* total physical port count */ 1914 .port_nirqs = 3, 1915 .num_tx_queues = 4, 1916 .num_ipms = 8, 1917 .tc_cbs_supported = true, 1918 .ops = &ksz9477_dev_ops, 1919 .mib_names = ksz9477_mib_names, 1920 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1921 .reg_mib_cnt = MIB_COUNTER_NUM, 1922 .regs = ksz9477_regs, 1923 .masks = ksz9477_masks, 1924 .shifts = ksz9477_shifts, 1925 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1926 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1927 .supports_mii = {false, false, false, false, 1928 false, true, true}, 1929 .supports_rmii = {false, false, false, false, 1930 false, true, true}, 1931 .supports_rgmii = {false, false, false, false, 1932 false, true, true}, 1933 .internal_phy = {true, true, true, true, 1934 true, false, false}, 1935 .gbit_capable = {true, true, true, true, true, true, true}, 1936 .ptp_capable = true, 1937 }, 1938 1939 [LAN9370] = { 1940 .chip_id = LAN9370_CHIP_ID, 1941 .dev_name = "LAN9370", 1942 .num_vlans = 4096, 1943 .num_alus = 1024, 1944 .num_statics = 256, 1945 .cpu_ports = 0x10, /* can be configured as cpu port */ 1946 .port_cnt = 5, /* total physical port count */ 1947 .port_nirqs = 6, 1948 .num_tx_queues = 8, 1949 .num_ipms = 8, 1950 .tc_cbs_supported = true, 1951 .phy_side_mdio_supported = true, 1952 .ops = &lan937x_dev_ops, 1953 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1954 .mib_names = ksz9477_mib_names, 1955 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1956 .reg_mib_cnt = MIB_COUNTER_NUM, 1957 .regs = ksz9477_regs, 1958 .masks = lan937x_masks, 1959 .shifts = lan937x_shifts, 1960 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1961 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1962 .supports_mii = {false, false, false, false, true}, 1963 .supports_rmii = {false, false, false, false, true}, 1964 .supports_rgmii = {false, false, false, false, true}, 1965 .internal_phy = {true, true, true, true, false}, 1966 .ptp_capable = true, 1967 }, 1968 1969 [LAN9371] = { 1970 .chip_id = LAN9371_CHIP_ID, 1971 .dev_name = "LAN9371", 1972 .num_vlans = 4096, 1973 .num_alus = 1024, 1974 .num_statics = 256, 1975 .cpu_ports = 0x30, /* can be configured as cpu port */ 1976 .port_cnt = 6, /* total physical port count */ 1977 .port_nirqs = 6, 1978 .num_tx_queues = 8, 1979 .num_ipms = 8, 1980 .tc_cbs_supported = true, 1981 .phy_side_mdio_supported = true, 1982 .ops = &lan937x_dev_ops, 1983 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1984 .mib_names = ksz9477_mib_names, 1985 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1986 .reg_mib_cnt = MIB_COUNTER_NUM, 1987 .regs = ksz9477_regs, 1988 .masks = lan937x_masks, 1989 .shifts = lan937x_shifts, 1990 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1991 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1992 .supports_mii = {false, false, false, false, true, true}, 1993 .supports_rmii = {false, false, false, false, true, true}, 1994 .supports_rgmii = {false, false, false, false, true, true}, 1995 .internal_phy = {true, true, true, true, false, false}, 1996 .ptp_capable = true, 1997 }, 1998 1999 [LAN9372] = { 2000 .chip_id = LAN9372_CHIP_ID, 2001 .dev_name = "LAN9372", 2002 .num_vlans = 4096, 2003 .num_alus = 1024, 2004 .num_statics = 256, 2005 .cpu_ports = 0x30, /* can be configured as cpu port */ 2006 .port_cnt = 8, /* total physical port count */ 2007 .port_nirqs = 6, 2008 .num_tx_queues = 8, 2009 .num_ipms = 8, 2010 .tc_cbs_supported = true, 2011 .phy_side_mdio_supported = true, 2012 .ops = &lan937x_dev_ops, 2013 .phylink_mac_ops = &lan937x_phylink_mac_ops, 2014 .mib_names = ksz9477_mib_names, 2015 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 2016 .reg_mib_cnt = MIB_COUNTER_NUM, 2017 .regs = ksz9477_regs, 2018 .masks = lan937x_masks, 2019 .shifts = lan937x_shifts, 2020 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 2021 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 2022 .supports_mii = {false, false, false, false, 2023 true, true, false, false}, 2024 .supports_rmii = {false, false, false, false, 2025 true, true, false, false}, 2026 .supports_rgmii = {false, false, false, false, 2027 true, true, false, false}, 2028 .internal_phy = {true, true, true, true, 2029 false, false, true, true}, 2030 .ptp_capable = true, 2031 }, 2032 2033 [LAN9373] = { 2034 .chip_id = LAN9373_CHIP_ID, 2035 .dev_name = "LAN9373", 2036 .num_vlans = 4096, 2037 .num_alus = 1024, 2038 .num_statics = 256, 2039 .cpu_ports = 0x38, /* can be configured as cpu port */ 2040 .port_cnt = 5, /* total physical port count */ 2041 .port_nirqs = 6, 2042 .num_tx_queues = 8, 2043 .num_ipms = 8, 2044 .tc_cbs_supported = true, 2045 .phy_side_mdio_supported = true, 2046 .ops = &lan937x_dev_ops, 2047 .phylink_mac_ops = &lan937x_phylink_mac_ops, 2048 .mib_names = ksz9477_mib_names, 2049 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 2050 .reg_mib_cnt = MIB_COUNTER_NUM, 2051 .regs = ksz9477_regs, 2052 .masks = lan937x_masks, 2053 .shifts = lan937x_shifts, 2054 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 2055 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 2056 .supports_mii = {false, false, false, false, 2057 true, true, false, false}, 2058 .supports_rmii = {false, false, false, false, 2059 true, true, false, false}, 2060 .supports_rgmii = {false, false, false, false, 2061 true, true, false, false}, 2062 .internal_phy = {true, true, true, false, 2063 false, false, true, true}, 2064 .ptp_capable = true, 2065 }, 2066 2067 [LAN9374] = { 2068 .chip_id = LAN9374_CHIP_ID, 2069 .dev_name = "LAN9374", 2070 .num_vlans = 4096, 2071 .num_alus = 1024, 2072 .num_statics = 256, 2073 .cpu_ports = 0x30, /* can be configured as cpu port */ 2074 .port_cnt = 8, /* total physical port count */ 2075 .port_nirqs = 6, 2076 .num_tx_queues = 8, 2077 .num_ipms = 8, 2078 .tc_cbs_supported = true, 2079 .phy_side_mdio_supported = true, 2080 .ops = &lan937x_dev_ops, 2081 .phylink_mac_ops = &lan937x_phylink_mac_ops, 2082 .mib_names = ksz9477_mib_names, 2083 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 2084 .reg_mib_cnt = MIB_COUNTER_NUM, 2085 .regs = ksz9477_regs, 2086 .masks = lan937x_masks, 2087 .shifts = lan937x_shifts, 2088 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 2089 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 2090 .supports_mii = {false, false, false, false, 2091 true, true, false, false}, 2092 .supports_rmii = {false, false, false, false, 2093 true, true, false, false}, 2094 .supports_rgmii = {false, false, false, false, 2095 true, true, false, false}, 2096 .internal_phy = {true, true, true, true, 2097 false, false, true, true}, 2098 .ptp_capable = true, 2099 }, 2100 2101 [LAN9646] = { 2102 .chip_id = LAN9646_CHIP_ID, 2103 .dev_name = "LAN9646", 2104 .num_vlans = 4096, 2105 .num_alus = 4096, 2106 .num_statics = 16, 2107 .cpu_ports = 0x7F, /* can be configured as cpu port */ 2108 .port_cnt = 7, /* total physical port count */ 2109 .port_nirqs = 4, 2110 .num_tx_queues = 4, 2111 .num_ipms = 8, 2112 .ops = &ksz9477_dev_ops, 2113 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 2114 .phy_errata_9477 = true, 2115 .mib_names = ksz9477_mib_names, 2116 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 2117 .reg_mib_cnt = MIB_COUNTER_NUM, 2118 .regs = ksz9477_regs, 2119 .masks = ksz9477_masks, 2120 .shifts = ksz9477_shifts, 2121 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 2122 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 2123 .supports_mii = {false, false, false, false, 2124 false, true, true}, 2125 .supports_rmii = {false, false, false, false, 2126 false, true, true}, 2127 .supports_rgmii = {false, false, false, false, 2128 false, true, true}, 2129 .internal_phy = {true, true, true, true, 2130 true, false, false}, 2131 .gbit_capable = {true, true, true, true, true, true, true}, 2132 .sgmii_port = 7, 2133 .wr_table = &ksz9477_register_set, 2134 .rd_table = &ksz9477_register_set, 2135 }, 2136 }; 2137 EXPORT_SYMBOL_GPL(ksz_switch_chips); 2138 2139 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 2140 { 2141 int i; 2142 2143 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 2144 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 2145 2146 if (chip->chip_id == prod_num) 2147 return chip; 2148 } 2149 2150 return NULL; 2151 } 2152 2153 static int ksz_check_device_id(struct ksz_device *dev) 2154 { 2155 const struct ksz_chip_data *expected_chip_data; 2156 u32 expected_chip_id; 2157 2158 if (dev->pdata) { 2159 expected_chip_id = dev->pdata->chip_id; 2160 expected_chip_data = ksz_lookup_info(expected_chip_id); 2161 if (WARN_ON(!expected_chip_data)) 2162 return -ENODEV; 2163 } else { 2164 expected_chip_data = of_device_get_match_data(dev->dev); 2165 expected_chip_id = expected_chip_data->chip_id; 2166 } 2167 2168 if (expected_chip_id != dev->chip_id) { 2169 dev_err(dev->dev, 2170 "Device tree specifies chip %s but found %s, please fix it!\n", 2171 expected_chip_data->dev_name, dev->info->dev_name); 2172 return -ENODEV; 2173 } 2174 2175 return 0; 2176 } 2177 2178 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 2179 struct phylink_config *config) 2180 { 2181 struct ksz_device *dev = ds->priv; 2182 2183 if (dev->info->supports_mii[port]) 2184 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 2185 2186 if (dev->info->supports_rmii[port]) 2187 __set_bit(PHY_INTERFACE_MODE_RMII, 2188 config->supported_interfaces); 2189 2190 if (dev->info->supports_rgmii[port]) 2191 phy_interface_set_rgmii(config->supported_interfaces); 2192 2193 if (dev->info->internal_phy[port]) { 2194 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2195 config->supported_interfaces); 2196 /* Compatibility for phylib's default interface type when the 2197 * phy-mode property is absent 2198 */ 2199 __set_bit(PHY_INTERFACE_MODE_GMII, 2200 config->supported_interfaces); 2201 } 2202 2203 if (dev->dev_ops->get_caps) 2204 dev->dev_ops->get_caps(dev, port, config); 2205 2206 if (ds->ops->support_eee && ds->ops->support_eee(ds, port)) { 2207 memcpy(config->lpi_interfaces, config->supported_interfaces, 2208 sizeof(config->lpi_interfaces)); 2209 2210 config->lpi_capabilities = MAC_100FD; 2211 if (dev->info->gbit_capable[port]) 2212 config->lpi_capabilities |= MAC_1000FD; 2213 2214 /* EEE is fully operational */ 2215 config->eee_enabled_default = true; 2216 } 2217 } 2218 2219 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 2220 { 2221 struct ethtool_pause_stats *pstats; 2222 struct rtnl_link_stats64 *stats; 2223 struct ksz_stats_raw *raw; 2224 struct ksz_port_mib *mib; 2225 int ret; 2226 2227 mib = &dev->ports[port].mib; 2228 stats = &mib->stats64; 2229 pstats = &mib->pause_stats; 2230 raw = (struct ksz_stats_raw *)mib->counters; 2231 2232 spin_lock(&mib->stats64_lock); 2233 2234 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 2235 raw->rx_pause; 2236 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2237 raw->tx_pause; 2238 2239 /* HW counters are counting bytes + FCS which is not acceptable 2240 * for rtnl_link_stats64 interface 2241 */ 2242 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 2243 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 2244 2245 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2246 raw->rx_oversize; 2247 2248 stats->rx_crc_errors = raw->rx_crc_err; 2249 stats->rx_frame_errors = raw->rx_align_err; 2250 stats->rx_dropped = raw->rx_discards; 2251 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2252 stats->rx_frame_errors + stats->rx_dropped; 2253 2254 stats->tx_window_errors = raw->tx_late_col; 2255 stats->tx_fifo_errors = raw->tx_discards; 2256 stats->tx_aborted_errors = raw->tx_exc_col; 2257 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2258 stats->tx_aborted_errors; 2259 2260 stats->multicast = raw->rx_mcast; 2261 stats->collisions = raw->tx_total_col; 2262 2263 pstats->tx_pause_frames = raw->tx_pause; 2264 pstats->rx_pause_frames = raw->rx_pause; 2265 2266 spin_unlock(&mib->stats64_lock); 2267 2268 if (dev->info->phy_errata_9477 && !ksz_is_sgmii_port(dev, port)) { 2269 ret = ksz9477_errata_monitor(dev, port, raw->tx_late_col); 2270 if (ret) 2271 dev_err(dev->dev, "Failed to monitor transmission halt\n"); 2272 } 2273 } 2274 2275 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 2276 { 2277 struct ethtool_pause_stats *pstats; 2278 struct rtnl_link_stats64 *stats; 2279 struct ksz88xx_stats_raw *raw; 2280 struct ksz_port_mib *mib; 2281 2282 mib = &dev->ports[port].mib; 2283 stats = &mib->stats64; 2284 pstats = &mib->pause_stats; 2285 raw = (struct ksz88xx_stats_raw *)mib->counters; 2286 2287 spin_lock(&mib->stats64_lock); 2288 2289 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 2290 raw->rx_pause; 2291 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2292 raw->tx_pause; 2293 2294 /* HW counters are counting bytes + FCS which is not acceptable 2295 * for rtnl_link_stats64 interface 2296 */ 2297 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 2298 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 2299 2300 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2301 raw->rx_oversize; 2302 2303 stats->rx_crc_errors = raw->rx_crc_err; 2304 stats->rx_frame_errors = raw->rx_align_err; 2305 stats->rx_dropped = raw->rx_discards; 2306 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2307 stats->rx_frame_errors + stats->rx_dropped; 2308 2309 stats->tx_window_errors = raw->tx_late_col; 2310 stats->tx_fifo_errors = raw->tx_discards; 2311 stats->tx_aborted_errors = raw->tx_exc_col; 2312 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2313 stats->tx_aborted_errors; 2314 2315 stats->multicast = raw->rx_mcast; 2316 stats->collisions = raw->tx_total_col; 2317 2318 pstats->tx_pause_frames = raw->tx_pause; 2319 pstats->rx_pause_frames = raw->rx_pause; 2320 2321 spin_unlock(&mib->stats64_lock); 2322 } 2323 2324 static void ksz_get_stats64(struct dsa_switch *ds, int port, 2325 struct rtnl_link_stats64 *s) 2326 { 2327 struct ksz_device *dev = ds->priv; 2328 struct ksz_port_mib *mib; 2329 2330 mib = &dev->ports[port].mib; 2331 2332 spin_lock(&mib->stats64_lock); 2333 memcpy(s, &mib->stats64, sizeof(*s)); 2334 spin_unlock(&mib->stats64_lock); 2335 } 2336 2337 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 2338 struct ethtool_pause_stats *pause_stats) 2339 { 2340 struct ksz_device *dev = ds->priv; 2341 struct ksz_port_mib *mib; 2342 2343 mib = &dev->ports[port].mib; 2344 2345 spin_lock(&mib->stats64_lock); 2346 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 2347 spin_unlock(&mib->stats64_lock); 2348 } 2349 2350 static void ksz_get_strings(struct dsa_switch *ds, int port, 2351 u32 stringset, uint8_t *buf) 2352 { 2353 struct ksz_device *dev = ds->priv; 2354 int i; 2355 2356 if (stringset != ETH_SS_STATS) 2357 return; 2358 2359 for (i = 0; i < dev->info->mib_cnt; i++) 2360 ethtool_puts(&buf, dev->info->mib_names[i].string); 2361 } 2362 2363 /** 2364 * ksz_update_port_member - Adjust port forwarding rules based on STP state and 2365 * isolation settings. 2366 * @dev: A pointer to the struct ksz_device representing the device. 2367 * @port: The port number to adjust. 2368 * 2369 * This function dynamically adjusts the port membership configuration for a 2370 * specified port and other device ports, based on Spanning Tree Protocol (STP) 2371 * states and port isolation settings. Each port, including the CPU port, has a 2372 * membership register, represented as a bitfield, where each bit corresponds 2373 * to a port number. A set bit indicates permission to forward frames to that 2374 * port. This function iterates over all ports, updating the membership register 2375 * to reflect current forwarding permissions: 2376 * 2377 * 1. Forwards frames only to ports that are part of the same bridge group and 2378 * in the BR_STATE_FORWARDING state. 2379 * 2. Takes into account the isolation status of ports; ports in the 2380 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward 2381 * frames to each other, even if they are in the same bridge group. 2382 * 3. Ensures that the CPU port is included in the membership based on its 2383 * upstream port configuration, allowing for management and control traffic 2384 * to flow as required. 2385 */ 2386 static void ksz_update_port_member(struct ksz_device *dev, int port) 2387 { 2388 struct ksz_port *p = &dev->ports[port]; 2389 struct dsa_switch *ds = dev->ds; 2390 u8 port_member = 0, cpu_port; 2391 const struct dsa_port *dp; 2392 int i, j; 2393 2394 if (!dsa_is_user_port(ds, port)) 2395 return; 2396 2397 dp = dsa_to_port(ds, port); 2398 cpu_port = BIT(dsa_upstream_port(ds, port)); 2399 2400 for (i = 0; i < ds->num_ports; i++) { 2401 const struct dsa_port *other_dp = dsa_to_port(ds, i); 2402 struct ksz_port *other_p = &dev->ports[i]; 2403 u8 val = 0; 2404 2405 if (!dsa_is_user_port(ds, i)) 2406 continue; 2407 if (port == i) 2408 continue; 2409 if (!dsa_port_bridge_same(dp, other_dp)) 2410 continue; 2411 if (other_p->stp_state != BR_STATE_FORWARDING) 2412 continue; 2413 2414 /* At this point we know that "port" and "other" port [i] are in 2415 * the same bridge group and that "other" port [i] is in 2416 * forwarding stp state. If "port" is also in forwarding stp 2417 * state, we can allow forwarding from port [port] to port [i]. 2418 * Except if both ports are isolated. 2419 */ 2420 if (p->stp_state == BR_STATE_FORWARDING && 2421 !(p->isolated && other_p->isolated)) { 2422 val |= BIT(port); 2423 port_member |= BIT(i); 2424 } 2425 2426 /* Retain port [i]'s relationship to other ports than [port] */ 2427 for (j = 0; j < ds->num_ports; j++) { 2428 const struct dsa_port *third_dp; 2429 struct ksz_port *third_p; 2430 2431 if (j == i) 2432 continue; 2433 if (j == port) 2434 continue; 2435 if (!dsa_is_user_port(ds, j)) 2436 continue; 2437 third_p = &dev->ports[j]; 2438 if (third_p->stp_state != BR_STATE_FORWARDING) 2439 continue; 2440 2441 third_dp = dsa_to_port(ds, j); 2442 2443 /* Now we updating relation of the "other" port [i] to 2444 * the "third" port [j]. We already know that "other" 2445 * port [i] is in forwarding stp state and that "third" 2446 * port [j] is in forwarding stp state too. 2447 * We need to check if "other" port [i] and "third" port 2448 * [j] are in the same bridge group and not isolated 2449 * before allowing forwarding from port [i] to port [j]. 2450 */ 2451 if (dsa_port_bridge_same(other_dp, third_dp) && 2452 !(other_p->isolated && third_p->isolated)) 2453 val |= BIT(j); 2454 } 2455 2456 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 2457 } 2458 2459 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 2460 } 2461 2462 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 2463 { 2464 struct ksz_device *dev = bus->priv; 2465 u16 val; 2466 int ret; 2467 2468 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 2469 if (ret < 0) 2470 return ret; 2471 2472 return val; 2473 } 2474 2475 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 2476 u16 val) 2477 { 2478 struct ksz_device *dev = bus->priv; 2479 2480 return dev->dev_ops->w_phy(dev, addr, regnum, val); 2481 } 2482 2483 /** 2484 * ksz_parent_mdio_read - Read data from a PHY register on the parent MDIO bus. 2485 * @bus: MDIO bus structure. 2486 * @addr: PHY address on the parent MDIO bus. 2487 * @regnum: Register number to read. 2488 * 2489 * This function provides a direct read operation on the parent MDIO bus for 2490 * accessing PHY registers. By bypassing SPI or I2C, it uses the parent MDIO bus 2491 * to retrieve data from the PHY registers at the specified address and register 2492 * number. 2493 * 2494 * Return: Value of the PHY register, or a negative error code on failure. 2495 */ 2496 static int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum) 2497 { 2498 struct ksz_device *dev = bus->priv; 2499 2500 return mdiobus_read_nested(dev->parent_mdio_bus, addr, regnum); 2501 } 2502 2503 /** 2504 * ksz_parent_mdio_write - Write data to a PHY register on the parent MDIO bus. 2505 * @bus: MDIO bus structure. 2506 * @addr: PHY address on the parent MDIO bus. 2507 * @regnum: Register number to write to. 2508 * @val: Value to write to the PHY register. 2509 * 2510 * This function provides a direct write operation on the parent MDIO bus for 2511 * accessing PHY registers. Bypassing SPI or I2C, it uses the parent MDIO bus 2512 * to modify the PHY register values at the specified address. 2513 * 2514 * Return: 0 on success, or a negative error code on failure. 2515 */ 2516 static int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum, 2517 u16 val) 2518 { 2519 struct ksz_device *dev = bus->priv; 2520 2521 return mdiobus_write_nested(dev->parent_mdio_bus, addr, regnum, val); 2522 } 2523 2524 /** 2525 * ksz_phy_addr_to_port - Map a PHY address to the corresponding switch port. 2526 * @dev: Pointer to device structure. 2527 * @addr: PHY address to map to a port. 2528 * 2529 * This function finds the corresponding switch port for a given PHY address by 2530 * iterating over all user ports on the device. It checks if a port's PHY 2531 * address in `phy_addr_map` matches the specified address and if the port 2532 * contains an internal PHY. If a match is found, the index of the port is 2533 * returned. 2534 * 2535 * Return: Port index on success, or -EINVAL if no matching port is found. 2536 */ 2537 static int ksz_phy_addr_to_port(struct ksz_device *dev, int addr) 2538 { 2539 struct dsa_switch *ds = dev->ds; 2540 struct dsa_port *dp; 2541 2542 dsa_switch_for_each_user_port(dp, ds) { 2543 if (dev->info->internal_phy[dp->index] && 2544 dev->phy_addr_map[dp->index] == addr) 2545 return dp->index; 2546 } 2547 2548 return -EINVAL; 2549 } 2550 2551 /** 2552 * ksz_irq_phy_setup - Configure IRQs for PHYs in the KSZ device. 2553 * @dev: Pointer to the KSZ device structure. 2554 * 2555 * Sets up IRQs for each active PHY connected to the KSZ switch by mapping the 2556 * appropriate IRQs for each PHY and assigning them to the `user_mii_bus` in 2557 * the DSA switch structure. Each IRQ is mapped based on the port's IRQ domain. 2558 * 2559 * Return: 0 on success, or a negative error code on failure. 2560 */ 2561 static int ksz_irq_phy_setup(struct ksz_device *dev) 2562 { 2563 struct dsa_switch *ds = dev->ds; 2564 int phy, port; 2565 int irq; 2566 int ret; 2567 2568 for (phy = 0; phy < PHY_MAX_ADDR; phy++) { 2569 if (BIT(phy) & ds->phys_mii_mask) { 2570 port = ksz_phy_addr_to_port(dev, phy); 2571 if (port < 0) { 2572 ret = port; 2573 goto out; 2574 } 2575 2576 irq = irq_find_mapping(dev->ports[port].pirq.domain, 2577 PORT_SRC_PHY_INT); 2578 if (irq < 0) { 2579 ret = irq; 2580 goto out; 2581 } 2582 ds->user_mii_bus->irq[phy] = irq; 2583 } 2584 } 2585 return 0; 2586 out: 2587 while (phy--) 2588 if (BIT(phy) & ds->phys_mii_mask) 2589 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2590 2591 return ret; 2592 } 2593 2594 /** 2595 * ksz_irq_phy_free - Release IRQ mappings for PHYs in the KSZ device. 2596 * @dev: Pointer to the KSZ device structure. 2597 * 2598 * Releases any IRQ mappings previously assigned to active PHYs in the KSZ 2599 * switch by disposing of each mapped IRQ in the `user_mii_bus` structure. 2600 */ 2601 static void ksz_irq_phy_free(struct ksz_device *dev) 2602 { 2603 struct dsa_switch *ds = dev->ds; 2604 int phy; 2605 2606 for (phy = 0; phy < PHY_MAX_ADDR; phy++) 2607 if (BIT(phy) & ds->phys_mii_mask) 2608 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2609 } 2610 2611 /** 2612 * ksz_parse_dt_phy_config - Parse and validate PHY configuration from DT 2613 * @dev: pointer to the KSZ device structure 2614 * @bus: pointer to the MII bus structure 2615 * @mdio_np: pointer to the MDIO node in the device tree 2616 * 2617 * This function parses and validates PHY configurations for each user port 2618 * defined in the device tree for a KSZ switch device. It verifies that the 2619 * `phy-handle` properties are correctly set and that the internal PHYs match 2620 * expected addresses and parent nodes. Sets up the PHY mask in the MII bus if 2621 * all validations pass. Logs error messages for any mismatches or missing data. 2622 * 2623 * Return: 0 on success, or a negative error code on failure. 2624 */ 2625 static int ksz_parse_dt_phy_config(struct ksz_device *dev, struct mii_bus *bus, 2626 struct device_node *mdio_np) 2627 { 2628 struct device_node *phy_node, *phy_parent_node; 2629 bool phys_are_valid = true; 2630 struct dsa_port *dp; 2631 u32 phy_addr; 2632 int ret; 2633 2634 dsa_switch_for_each_user_port(dp, dev->ds) { 2635 if (!dev->info->internal_phy[dp->index]) 2636 continue; 2637 2638 phy_node = of_parse_phandle(dp->dn, "phy-handle", 0); 2639 if (!phy_node) { 2640 dev_err(dev->dev, "failed to parse phy-handle for port %d.\n", 2641 dp->index); 2642 phys_are_valid = false; 2643 continue; 2644 } 2645 2646 phy_parent_node = of_get_parent(phy_node); 2647 if (!phy_parent_node) { 2648 dev_err(dev->dev, "failed to get PHY-parent node for port %d\n", 2649 dp->index); 2650 phys_are_valid = false; 2651 } else if (phy_parent_node != mdio_np) { 2652 dev_err(dev->dev, "PHY-parent node mismatch for port %d, expected %pOF, got %pOF\n", 2653 dp->index, mdio_np, phy_parent_node); 2654 phys_are_valid = false; 2655 } else { 2656 ret = of_property_read_u32(phy_node, "reg", &phy_addr); 2657 if (ret < 0) { 2658 dev_err(dev->dev, "failed to read PHY address for port %d. Error %d\n", 2659 dp->index, ret); 2660 phys_are_valid = false; 2661 } else if (phy_addr != dev->phy_addr_map[dp->index]) { 2662 dev_err(dev->dev, "PHY address mismatch for port %d, expected 0x%x, got 0x%x\n", 2663 dp->index, dev->phy_addr_map[dp->index], 2664 phy_addr); 2665 phys_are_valid = false; 2666 } else { 2667 bus->phy_mask |= BIT(phy_addr); 2668 } 2669 } 2670 2671 of_node_put(phy_node); 2672 of_node_put(phy_parent_node); 2673 } 2674 2675 if (!phys_are_valid) 2676 return -EINVAL; 2677 2678 return 0; 2679 } 2680 2681 /** 2682 * ksz_mdio_register - Register and configure the MDIO bus for the KSZ device. 2683 * @dev: Pointer to the KSZ device structure. 2684 * 2685 * This function sets up and registers an MDIO bus for the KSZ switch device, 2686 * allowing access to its internal PHYs. If the device supports side MDIO, 2687 * the function will configure the external MDIO controller specified by the 2688 * "mdio-parent-bus" device tree property to directly manage internal PHYs. 2689 * Otherwise, SPI or I2C access is set up for PHY access. 2690 * 2691 * Return: 0 on success, or a negative error code on failure. 2692 */ 2693 static int ksz_mdio_register(struct ksz_device *dev) 2694 { 2695 struct device_node *parent_bus_node; 2696 struct mii_bus *parent_bus = NULL; 2697 struct dsa_switch *ds = dev->ds; 2698 struct device_node *mdio_np; 2699 struct mii_bus *bus; 2700 int ret, i; 2701 2702 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 2703 if (!mdio_np) 2704 return 0; 2705 2706 parent_bus_node = of_parse_phandle(mdio_np, "mdio-parent-bus", 0); 2707 if (parent_bus_node && !dev->info->phy_side_mdio_supported) { 2708 dev_err(dev->dev, "Side MDIO bus is not supported for this HW, ignoring 'mdio-parent-bus' property.\n"); 2709 ret = -EINVAL; 2710 2711 goto put_mdio_node; 2712 } else if (parent_bus_node) { 2713 parent_bus = of_mdio_find_bus(parent_bus_node); 2714 if (!parent_bus) { 2715 ret = -EPROBE_DEFER; 2716 2717 goto put_mdio_node; 2718 } 2719 2720 dev->parent_mdio_bus = parent_bus; 2721 } 2722 2723 bus = devm_mdiobus_alloc(ds->dev); 2724 if (!bus) { 2725 ret = -ENOMEM; 2726 goto put_mdio_node; 2727 } 2728 2729 if (dev->dev_ops->mdio_bus_preinit) { 2730 ret = dev->dev_ops->mdio_bus_preinit(dev, !!parent_bus); 2731 if (ret) 2732 goto put_mdio_node; 2733 } 2734 2735 if (dev->dev_ops->create_phy_addr_map) { 2736 ret = dev->dev_ops->create_phy_addr_map(dev, !!parent_bus); 2737 if (ret) 2738 goto put_mdio_node; 2739 } else { 2740 for (i = 0; i < dev->info->port_cnt; i++) 2741 dev->phy_addr_map[i] = i; 2742 } 2743 2744 bus->priv = dev; 2745 if (parent_bus) { 2746 bus->read = ksz_parent_mdio_read; 2747 bus->write = ksz_parent_mdio_write; 2748 bus->name = "KSZ side MDIO"; 2749 snprintf(bus->id, MII_BUS_ID_SIZE, "ksz-side-mdio-%d", 2750 ds->index); 2751 } else { 2752 bus->read = ksz_sw_mdio_read; 2753 bus->write = ksz_sw_mdio_write; 2754 bus->name = "ksz user smi"; 2755 if (ds->dst->index != 0) { 2756 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d-%d", ds->dst->index, ds->index); 2757 } else { 2758 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 2759 } 2760 } 2761 2762 ret = ksz_parse_dt_phy_config(dev, bus, mdio_np); 2763 if (ret) 2764 goto put_mdio_node; 2765 2766 ds->phys_mii_mask = bus->phy_mask; 2767 bus->parent = ds->dev; 2768 2769 ds->user_mii_bus = bus; 2770 2771 if (dev->irq > 0) { 2772 ret = ksz_irq_phy_setup(dev); 2773 if (ret) 2774 goto put_mdio_node; 2775 } 2776 2777 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 2778 if (ret) { 2779 dev_err(ds->dev, "unable to register MDIO bus %s\n", 2780 bus->id); 2781 if (dev->irq > 0) 2782 ksz_irq_phy_free(dev); 2783 } 2784 2785 put_mdio_node: 2786 of_node_put(mdio_np); 2787 of_node_put(parent_bus_node); 2788 2789 return ret; 2790 } 2791 2792 static void ksz_irq_mask(struct irq_data *d) 2793 { 2794 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2795 2796 kirq->masked |= BIT(d->hwirq); 2797 } 2798 2799 static void ksz_irq_unmask(struct irq_data *d) 2800 { 2801 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2802 2803 kirq->masked &= ~BIT(d->hwirq); 2804 } 2805 2806 static void ksz_irq_bus_lock(struct irq_data *d) 2807 { 2808 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2809 2810 mutex_lock(&kirq->dev->lock_irq); 2811 } 2812 2813 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 2814 { 2815 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2816 struct ksz_device *dev = kirq->dev; 2817 int ret; 2818 2819 ret = ksz_write8(dev, kirq->reg_mask, kirq->masked); 2820 if (ret) 2821 dev_err(dev->dev, "failed to change IRQ mask\n"); 2822 2823 mutex_unlock(&dev->lock_irq); 2824 } 2825 2826 static const struct irq_chip ksz_irq_chip = { 2827 .name = "ksz-irq", 2828 .irq_mask = ksz_irq_mask, 2829 .irq_unmask = ksz_irq_unmask, 2830 .irq_bus_lock = ksz_irq_bus_lock, 2831 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 2832 }; 2833 2834 static int ksz_irq_domain_map(struct irq_domain *d, 2835 unsigned int irq, irq_hw_number_t hwirq) 2836 { 2837 irq_set_chip_data(irq, d->host_data); 2838 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 2839 irq_set_noprobe(irq); 2840 2841 return 0; 2842 } 2843 2844 static const struct irq_domain_ops ksz_irq_domain_ops = { 2845 .map = ksz_irq_domain_map, 2846 .xlate = irq_domain_xlate_twocell, 2847 }; 2848 2849 static void ksz_irq_free(struct ksz_irq *kirq) 2850 { 2851 int irq, virq; 2852 2853 free_irq(kirq->irq_num, kirq); 2854 2855 for (irq = 0; irq < kirq->nirqs; irq++) { 2856 virq = irq_find_mapping(kirq->domain, irq); 2857 irq_dispose_mapping(virq); 2858 } 2859 2860 irq_domain_remove(kirq->domain); 2861 } 2862 2863 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 2864 { 2865 struct ksz_irq *kirq = dev_id; 2866 unsigned int nhandled = 0; 2867 struct ksz_device *dev; 2868 unsigned int sub_irq; 2869 u8 data; 2870 int ret; 2871 u8 n; 2872 2873 dev = kirq->dev; 2874 2875 /* Read interrupt status register */ 2876 ret = ksz_read8(dev, kirq->reg_status, &data); 2877 if (ret) 2878 goto out; 2879 2880 for (n = 0; n < kirq->nirqs; ++n) { 2881 if (data & BIT(n)) { 2882 sub_irq = irq_find_mapping(kirq->domain, n); 2883 handle_nested_irq(sub_irq); 2884 ++nhandled; 2885 } 2886 } 2887 out: 2888 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2889 } 2890 2891 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 2892 { 2893 int ret, n; 2894 2895 kirq->dev = dev; 2896 kirq->masked = ~0; 2897 2898 kirq->domain = irq_domain_create_simple(dev_fwnode(dev->dev), kirq->nirqs, 0, 2899 &ksz_irq_domain_ops, kirq); 2900 if (!kirq->domain) 2901 return -ENOMEM; 2902 2903 for (n = 0; n < kirq->nirqs; n++) 2904 irq_create_mapping(kirq->domain, n); 2905 2906 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2907 IRQF_ONESHOT, kirq->name, kirq); 2908 if (ret) 2909 goto out; 2910 2911 return 0; 2912 2913 out: 2914 ksz_irq_free(kirq); 2915 2916 return ret; 2917 } 2918 2919 static int ksz_girq_setup(struct ksz_device *dev) 2920 { 2921 struct ksz_irq *girq = &dev->girq; 2922 2923 girq->nirqs = dev->info->port_cnt; 2924 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2925 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2926 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2927 2928 girq->irq_num = dev->irq; 2929 2930 return ksz_irq_common_setup(dev, girq); 2931 } 2932 2933 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2934 { 2935 struct ksz_irq *pirq = &dev->ports[p].pirq; 2936 2937 pirq->nirqs = dev->info->port_nirqs; 2938 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2939 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2940 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2941 2942 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2943 if (pirq->irq_num < 0) 2944 return pirq->irq_num; 2945 2946 return ksz_irq_common_setup(dev, pirq); 2947 } 2948 2949 static int ksz_parse_drive_strength(struct ksz_device *dev); 2950 2951 static int ksz_setup(struct dsa_switch *ds) 2952 { 2953 struct ksz_device *dev = ds->priv; 2954 u16 storm_mask, storm_rate; 2955 struct dsa_port *dp; 2956 struct ksz_port *p; 2957 const u16 *regs; 2958 int ret; 2959 2960 regs = dev->info->regs; 2961 2962 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2963 dev->info->num_vlans, GFP_KERNEL); 2964 if (!dev->vlan_cache) 2965 return -ENOMEM; 2966 2967 ret = dev->dev_ops->reset(dev); 2968 if (ret) { 2969 dev_err(ds->dev, "failed to reset switch\n"); 2970 return ret; 2971 } 2972 2973 ret = ksz_parse_drive_strength(dev); 2974 if (ret) 2975 return ret; 2976 2977 if (ksz_has_sgmii_port(dev) && dev->dev_ops->pcs_create) { 2978 ret = dev->dev_ops->pcs_create(dev); 2979 if (ret) 2980 return ret; 2981 } 2982 2983 /* set broadcast storm protection 10% rate */ 2984 storm_mask = BROADCAST_STORM_RATE; 2985 storm_rate = (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100; 2986 if (ksz_is_ksz8463(dev)) { 2987 storm_mask = swab16(storm_mask); 2988 storm_rate = swab16(storm_rate); 2989 } 2990 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2991 storm_mask, storm_rate); 2992 2993 dev->dev_ops->config_cpu_port(ds); 2994 2995 dev->dev_ops->enable_stp_addr(dev); 2996 2997 ds->num_tx_queues = dev->info->num_tx_queues; 2998 2999 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 3000 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 3001 3002 ksz_init_mib_timer(dev); 3003 3004 ds->configure_vlan_while_not_filtering = false; 3005 ds->dscp_prio_mapping_is_global = true; 3006 3007 if (dev->dev_ops->setup) { 3008 ret = dev->dev_ops->setup(ds); 3009 if (ret) 3010 return ret; 3011 } 3012 3013 /* Start with learning disabled on standalone user ports, and enabled 3014 * on the CPU port. In lack of other finer mechanisms, learning on the 3015 * CPU port will avoid flooding bridge local addresses on the network 3016 * in some cases. 3017 */ 3018 p = &dev->ports[dev->cpu_port]; 3019 p->learning = true; 3020 3021 if (dev->irq > 0) { 3022 ret = ksz_girq_setup(dev); 3023 if (ret) 3024 return ret; 3025 3026 dsa_switch_for_each_user_port(dp, dev->ds) { 3027 ret = ksz_pirq_setup(dev, dp->index); 3028 if (ret) 3029 goto out_girq; 3030 3031 if (dev->info->ptp_capable) { 3032 ret = ksz_ptp_irq_setup(ds, dp->index); 3033 if (ret) 3034 goto out_pirq; 3035 } 3036 } 3037 } 3038 3039 if (dev->info->ptp_capable) { 3040 ret = ksz_ptp_clock_register(ds); 3041 if (ret) { 3042 dev_err(dev->dev, "Failed to register PTP clock: %d\n", 3043 ret); 3044 goto out_ptpirq; 3045 } 3046 } 3047 3048 ret = ksz_mdio_register(dev); 3049 if (ret < 0) { 3050 dev_err(dev->dev, "failed to register the mdio"); 3051 goto out_ptp_clock_unregister; 3052 } 3053 3054 ret = ksz_dcb_init(dev); 3055 if (ret) 3056 goto out_ptp_clock_unregister; 3057 3058 /* start switch */ 3059 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 3060 SW_START, SW_START); 3061 3062 return 0; 3063 3064 out_ptp_clock_unregister: 3065 if (dev->info->ptp_capable) 3066 ksz_ptp_clock_unregister(ds); 3067 out_ptpirq: 3068 if (dev->irq > 0 && dev->info->ptp_capable) 3069 dsa_switch_for_each_user_port(dp, dev->ds) 3070 ksz_ptp_irq_free(ds, dp->index); 3071 out_pirq: 3072 if (dev->irq > 0) 3073 dsa_switch_for_each_user_port(dp, dev->ds) 3074 ksz_irq_free(&dev->ports[dp->index].pirq); 3075 out_girq: 3076 if (dev->irq > 0) 3077 ksz_irq_free(&dev->girq); 3078 3079 return ret; 3080 } 3081 3082 static void ksz_teardown(struct dsa_switch *ds) 3083 { 3084 struct ksz_device *dev = ds->priv; 3085 struct dsa_port *dp; 3086 3087 if (dev->info->ptp_capable) 3088 ksz_ptp_clock_unregister(ds); 3089 3090 if (dev->irq > 0) { 3091 dsa_switch_for_each_user_port(dp, dev->ds) { 3092 if (dev->info->ptp_capable) 3093 ksz_ptp_irq_free(ds, dp->index); 3094 3095 ksz_irq_free(&dev->ports[dp->index].pirq); 3096 } 3097 3098 ksz_irq_free(&dev->girq); 3099 } 3100 3101 if (dev->dev_ops->teardown) 3102 dev->dev_ops->teardown(ds); 3103 } 3104 3105 static void port_r_cnt(struct ksz_device *dev, int port) 3106 { 3107 struct ksz_port_mib *mib = &dev->ports[port].mib; 3108 u64 *dropped; 3109 3110 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 3111 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 3112 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 3113 &mib->counters[mib->cnt_ptr]); 3114 ++mib->cnt_ptr; 3115 } 3116 3117 /* last one in storage */ 3118 dropped = &mib->counters[dev->info->mib_cnt]; 3119 3120 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 3121 while (mib->cnt_ptr < dev->info->mib_cnt) { 3122 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 3123 dropped, &mib->counters[mib->cnt_ptr]); 3124 ++mib->cnt_ptr; 3125 } 3126 mib->cnt_ptr = 0; 3127 } 3128 3129 static void ksz_mib_read_work(struct work_struct *work) 3130 { 3131 struct ksz_device *dev = container_of(work, struct ksz_device, 3132 mib_read.work); 3133 struct ksz_port_mib *mib; 3134 struct ksz_port *p; 3135 int i; 3136 3137 for (i = 0; i < dev->info->port_cnt; i++) { 3138 if (dsa_is_unused_port(dev->ds, i)) 3139 continue; 3140 3141 p = &dev->ports[i]; 3142 mib = &p->mib; 3143 mutex_lock(&mib->cnt_mutex); 3144 3145 /* Only read MIB counters when the port is told to do. 3146 * If not, read only dropped counters when link is not up. 3147 */ 3148 if (!p->read) { 3149 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 3150 3151 if (!netif_carrier_ok(dp->user)) 3152 mib->cnt_ptr = dev->info->reg_mib_cnt; 3153 } 3154 port_r_cnt(dev, i); 3155 p->read = false; 3156 3157 if (dev->dev_ops->r_mib_stat64) 3158 dev->dev_ops->r_mib_stat64(dev, i); 3159 3160 mutex_unlock(&mib->cnt_mutex); 3161 } 3162 3163 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 3164 } 3165 3166 void ksz_init_mib_timer(struct ksz_device *dev) 3167 { 3168 int i; 3169 3170 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 3171 3172 for (i = 0; i < dev->info->port_cnt; i++) { 3173 struct ksz_port_mib *mib = &dev->ports[i].mib; 3174 3175 dev->dev_ops->port_init_cnt(dev, i); 3176 3177 mib->cnt_ptr = 0; 3178 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 3179 } 3180 } 3181 3182 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 3183 { 3184 struct ksz_device *dev = ds->priv; 3185 u16 val = 0xffff; 3186 int ret; 3187 3188 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 3189 if (ret) 3190 return ret; 3191 3192 return val; 3193 } 3194 3195 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 3196 { 3197 struct ksz_device *dev = ds->priv; 3198 int ret; 3199 3200 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 3201 if (ret) 3202 return ret; 3203 3204 return 0; 3205 } 3206 3207 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 3208 { 3209 struct ksz_device *dev = ds->priv; 3210 3211 switch (dev->chip_id) { 3212 case KSZ88X3_CHIP_ID: 3213 /* Silicon Errata Sheet (DS80000830A): 3214 * Port 1 does not work with LinkMD Cable-Testing. 3215 * Port 1 does not respond to received PAUSE control frames. 3216 */ 3217 if (!port) 3218 return MICREL_KSZ8_P1_ERRATA; 3219 break; 3220 } 3221 3222 return 0; 3223 } 3224 3225 static void ksz_phylink_mac_link_down(struct phylink_config *config, 3226 unsigned int mode, 3227 phy_interface_t interface) 3228 { 3229 struct dsa_port *dp = dsa_phylink_to_port(config); 3230 struct ksz_device *dev = dp->ds->priv; 3231 3232 /* Read all MIB counters when the link is going down. */ 3233 dev->ports[dp->index].read = true; 3234 /* timer started */ 3235 if (dev->mib_read_interval) 3236 schedule_delayed_work(&dev->mib_read, 0); 3237 } 3238 3239 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 3240 { 3241 struct ksz_device *dev = ds->priv; 3242 3243 if (sset != ETH_SS_STATS) 3244 return 0; 3245 3246 return dev->info->mib_cnt; 3247 } 3248 3249 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 3250 uint64_t *buf) 3251 { 3252 const struct dsa_port *dp = dsa_to_port(ds, port); 3253 struct ksz_device *dev = ds->priv; 3254 struct ksz_port_mib *mib; 3255 3256 mib = &dev->ports[port].mib; 3257 mutex_lock(&mib->cnt_mutex); 3258 3259 /* Only read dropped counters if no link. */ 3260 if (!netif_carrier_ok(dp->user)) 3261 mib->cnt_ptr = dev->info->reg_mib_cnt; 3262 port_r_cnt(dev, port); 3263 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 3264 mutex_unlock(&mib->cnt_mutex); 3265 } 3266 3267 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 3268 struct dsa_bridge bridge, 3269 bool *tx_fwd_offload, 3270 struct netlink_ext_ack *extack) 3271 { 3272 /* port_stp_state_set() will be called after to put the port in 3273 * appropriate state so there is no need to do anything. 3274 */ 3275 3276 return 0; 3277 } 3278 3279 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 3280 struct dsa_bridge bridge) 3281 { 3282 /* port_stp_state_set() will be called after to put the port in 3283 * forwarding state so there is no need to do anything. 3284 */ 3285 } 3286 3287 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 3288 { 3289 struct ksz_device *dev = ds->priv; 3290 3291 dev->dev_ops->flush_dyn_mac_table(dev, port); 3292 } 3293 3294 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 3295 { 3296 struct ksz_device *dev = ds->priv; 3297 3298 if (!dev->dev_ops->set_ageing_time) 3299 return -EOPNOTSUPP; 3300 3301 return dev->dev_ops->set_ageing_time(dev, msecs); 3302 } 3303 3304 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 3305 const unsigned char *addr, u16 vid, 3306 struct dsa_db db) 3307 { 3308 struct ksz_device *dev = ds->priv; 3309 3310 if (!dev->dev_ops->fdb_add) 3311 return -EOPNOTSUPP; 3312 3313 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 3314 } 3315 3316 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 3317 const unsigned char *addr, 3318 u16 vid, struct dsa_db db) 3319 { 3320 struct ksz_device *dev = ds->priv; 3321 3322 if (!dev->dev_ops->fdb_del) 3323 return -EOPNOTSUPP; 3324 3325 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 3326 } 3327 3328 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 3329 dsa_fdb_dump_cb_t *cb, void *data) 3330 { 3331 struct ksz_device *dev = ds->priv; 3332 3333 if (!dev->dev_ops->fdb_dump) 3334 return -EOPNOTSUPP; 3335 3336 return dev->dev_ops->fdb_dump(dev, port, cb, data); 3337 } 3338 3339 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 3340 const struct switchdev_obj_port_mdb *mdb, 3341 struct dsa_db db) 3342 { 3343 struct ksz_device *dev = ds->priv; 3344 3345 if (!dev->dev_ops->mdb_add) 3346 return -EOPNOTSUPP; 3347 3348 return dev->dev_ops->mdb_add(dev, port, mdb, db); 3349 } 3350 3351 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 3352 const struct switchdev_obj_port_mdb *mdb, 3353 struct dsa_db db) 3354 { 3355 struct ksz_device *dev = ds->priv; 3356 3357 if (!dev->dev_ops->mdb_del) 3358 return -EOPNOTSUPP; 3359 3360 return dev->dev_ops->mdb_del(dev, port, mdb, db); 3361 } 3362 3363 static int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev, 3364 int port) 3365 { 3366 u32 queue_map = 0; 3367 int ipm; 3368 3369 for (ipm = 0; ipm < dev->info->num_ipms; ipm++) { 3370 int queue; 3371 3372 /* Traffic Type (TT) is corresponding to the Internal Priority 3373 * Map (IPM) in the switch. Traffic Class (TC) is 3374 * corresponding to the queue in the switch. 3375 */ 3376 queue = ieee8021q_tt_to_tc(ipm, dev->info->num_tx_queues); 3377 if (queue < 0) 3378 return queue; 3379 3380 queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S); 3381 } 3382 3383 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3384 } 3385 3386 static int ksz_port_setup(struct dsa_switch *ds, int port) 3387 { 3388 struct ksz_device *dev = ds->priv; 3389 int ret; 3390 3391 if (!dsa_is_user_port(ds, port)) 3392 return 0; 3393 3394 /* setup user port */ 3395 dev->dev_ops->port_setup(dev, port, false); 3396 3397 if (!is_ksz8(dev)) { 3398 ret = ksz9477_set_default_prio_queue_mapping(dev, port); 3399 if (ret) 3400 return ret; 3401 } 3402 3403 /* port_stp_state_set() will be called after to enable the port so 3404 * there is no need to do anything. 3405 */ 3406 3407 return ksz_dcb_init_port(dev, port); 3408 } 3409 3410 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 3411 { 3412 struct ksz_device *dev = ds->priv; 3413 struct ksz_port *p; 3414 const u16 *regs; 3415 u8 data; 3416 3417 regs = dev->info->regs; 3418 3419 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 3420 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 3421 3422 p = &dev->ports[port]; 3423 3424 switch (state) { 3425 case BR_STATE_DISABLED: 3426 data |= PORT_LEARN_DISABLE; 3427 break; 3428 case BR_STATE_LISTENING: 3429 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 3430 break; 3431 case BR_STATE_LEARNING: 3432 data |= PORT_RX_ENABLE; 3433 if (!p->learning) 3434 data |= PORT_LEARN_DISABLE; 3435 break; 3436 case BR_STATE_FORWARDING: 3437 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 3438 if (!p->learning) 3439 data |= PORT_LEARN_DISABLE; 3440 break; 3441 case BR_STATE_BLOCKING: 3442 data |= PORT_LEARN_DISABLE; 3443 break; 3444 default: 3445 dev_err(ds->dev, "invalid STP state: %d\n", state); 3446 return; 3447 } 3448 3449 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 3450 3451 p->stp_state = state; 3452 3453 ksz_update_port_member(dev, port); 3454 } 3455 3456 static void ksz_port_teardown(struct dsa_switch *ds, int port) 3457 { 3458 struct ksz_device *dev = ds->priv; 3459 3460 switch (dev->chip_id) { 3461 case KSZ8563_CHIP_ID: 3462 case KSZ8567_CHIP_ID: 3463 case KSZ9477_CHIP_ID: 3464 case KSZ9563_CHIP_ID: 3465 case KSZ9567_CHIP_ID: 3466 case KSZ9893_CHIP_ID: 3467 case KSZ9896_CHIP_ID: 3468 case KSZ9897_CHIP_ID: 3469 case LAN9646_CHIP_ID: 3470 if (dsa_is_user_port(ds, port)) 3471 ksz9477_port_acl_free(dev, port); 3472 } 3473 } 3474 3475 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 3476 struct switchdev_brport_flags flags, 3477 struct netlink_ext_ack *extack) 3478 { 3479 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED)) 3480 return -EINVAL; 3481 3482 return 0; 3483 } 3484 3485 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 3486 struct switchdev_brport_flags flags, 3487 struct netlink_ext_ack *extack) 3488 { 3489 struct ksz_device *dev = ds->priv; 3490 struct ksz_port *p = &dev->ports[port]; 3491 3492 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) { 3493 if (flags.mask & BR_LEARNING) 3494 p->learning = !!(flags.val & BR_LEARNING); 3495 3496 if (flags.mask & BR_ISOLATED) 3497 p->isolated = !!(flags.val & BR_ISOLATED); 3498 3499 /* Make the change take effect immediately */ 3500 ksz_port_stp_state_set(ds, port, p->stp_state); 3501 } 3502 3503 return 0; 3504 } 3505 3506 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 3507 int port, 3508 enum dsa_tag_protocol mp) 3509 { 3510 struct ksz_device *dev = ds->priv; 3511 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 3512 3513 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev)) 3514 proto = DSA_TAG_PROTO_KSZ8795; 3515 3516 if (dev->chip_id == KSZ88X3_CHIP_ID || 3517 dev->chip_id == KSZ8463_CHIP_ID || 3518 dev->chip_id == KSZ8563_CHIP_ID || 3519 dev->chip_id == KSZ9893_CHIP_ID || 3520 dev->chip_id == KSZ9563_CHIP_ID) 3521 proto = DSA_TAG_PROTO_KSZ9893; 3522 3523 if (dev->chip_id == KSZ8567_CHIP_ID || 3524 dev->chip_id == KSZ9477_CHIP_ID || 3525 dev->chip_id == KSZ9896_CHIP_ID || 3526 dev->chip_id == KSZ9897_CHIP_ID || 3527 dev->chip_id == KSZ9567_CHIP_ID || 3528 dev->chip_id == LAN9646_CHIP_ID) 3529 proto = DSA_TAG_PROTO_KSZ9477; 3530 3531 if (is_lan937x(dev)) 3532 proto = DSA_TAG_PROTO_LAN937X; 3533 3534 return proto; 3535 } 3536 3537 static int ksz_connect_tag_protocol(struct dsa_switch *ds, 3538 enum dsa_tag_protocol proto) 3539 { 3540 struct ksz_tagger_data *tagger_data; 3541 3542 switch (proto) { 3543 case DSA_TAG_PROTO_KSZ8795: 3544 return 0; 3545 case DSA_TAG_PROTO_KSZ9893: 3546 case DSA_TAG_PROTO_KSZ9477: 3547 case DSA_TAG_PROTO_LAN937X: 3548 tagger_data = ksz_tagger_data(ds); 3549 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 3550 return 0; 3551 default: 3552 return -EPROTONOSUPPORT; 3553 } 3554 } 3555 3556 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 3557 bool flag, struct netlink_ext_ack *extack) 3558 { 3559 struct ksz_device *dev = ds->priv; 3560 3561 if (!dev->dev_ops->vlan_filtering) 3562 return -EOPNOTSUPP; 3563 3564 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 3565 } 3566 3567 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 3568 const struct switchdev_obj_port_vlan *vlan, 3569 struct netlink_ext_ack *extack) 3570 { 3571 struct ksz_device *dev = ds->priv; 3572 3573 if (!dev->dev_ops->vlan_add) 3574 return -EOPNOTSUPP; 3575 3576 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 3577 } 3578 3579 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 3580 const struct switchdev_obj_port_vlan *vlan) 3581 { 3582 struct ksz_device *dev = ds->priv; 3583 3584 if (!dev->dev_ops->vlan_del) 3585 return -EOPNOTSUPP; 3586 3587 return dev->dev_ops->vlan_del(dev, port, vlan); 3588 } 3589 3590 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 3591 struct dsa_mall_mirror_tc_entry *mirror, 3592 bool ingress, struct netlink_ext_ack *extack) 3593 { 3594 struct ksz_device *dev = ds->priv; 3595 3596 if (!dev->dev_ops->mirror_add) 3597 return -EOPNOTSUPP; 3598 3599 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 3600 } 3601 3602 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 3603 struct dsa_mall_mirror_tc_entry *mirror) 3604 { 3605 struct ksz_device *dev = ds->priv; 3606 3607 if (dev->dev_ops->mirror_del) 3608 dev->dev_ops->mirror_del(dev, port, mirror); 3609 } 3610 3611 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 3612 { 3613 struct ksz_device *dev = ds->priv; 3614 3615 if (!dev->dev_ops->change_mtu) 3616 return -EOPNOTSUPP; 3617 3618 return dev->dev_ops->change_mtu(dev, port, mtu); 3619 } 3620 3621 static int ksz_max_mtu(struct dsa_switch *ds, int port) 3622 { 3623 struct ksz_device *dev = ds->priv; 3624 3625 switch (dev->chip_id) { 3626 case KSZ8795_CHIP_ID: 3627 case KSZ8794_CHIP_ID: 3628 case KSZ8765_CHIP_ID: 3629 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3630 case KSZ8463_CHIP_ID: 3631 case KSZ88X3_CHIP_ID: 3632 case KSZ8864_CHIP_ID: 3633 case KSZ8895_CHIP_ID: 3634 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3635 case KSZ8563_CHIP_ID: 3636 case KSZ8567_CHIP_ID: 3637 case KSZ9477_CHIP_ID: 3638 case KSZ9563_CHIP_ID: 3639 case KSZ9567_CHIP_ID: 3640 case KSZ9893_CHIP_ID: 3641 case KSZ9896_CHIP_ID: 3642 case KSZ9897_CHIP_ID: 3643 case LAN9370_CHIP_ID: 3644 case LAN9371_CHIP_ID: 3645 case LAN9372_CHIP_ID: 3646 case LAN9373_CHIP_ID: 3647 case LAN9374_CHIP_ID: 3648 case LAN9646_CHIP_ID: 3649 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3650 } 3651 3652 return -EOPNOTSUPP; 3653 } 3654 3655 /** 3656 * ksz_support_eee - Determine Energy Efficient Ethernet (EEE) support for a 3657 * port 3658 * @ds: Pointer to the DSA switch structure 3659 * @port: Port number to check 3660 * 3661 * This function also documents devices where EEE was initially advertised but 3662 * later withdrawn due to reliability issues, as described in official errata 3663 * documents. These devices are explicitly listed to record known limitations, 3664 * even if there is no technical necessity for runtime checks. 3665 * 3666 * Returns: true if the internal PHY on the given port supports fully 3667 * operational EEE, false otherwise. 3668 */ 3669 static bool ksz_support_eee(struct dsa_switch *ds, int port) 3670 { 3671 struct ksz_device *dev = ds->priv; 3672 3673 if (!dev->info->internal_phy[port]) 3674 return false; 3675 3676 switch (dev->chip_id) { 3677 case KSZ8563_CHIP_ID: 3678 case KSZ9563_CHIP_ID: 3679 case KSZ9893_CHIP_ID: 3680 return true; 3681 case KSZ8567_CHIP_ID: 3682 /* KSZ8567R Errata DS80000752C Module 4 */ 3683 case KSZ8765_CHIP_ID: 3684 case KSZ8794_CHIP_ID: 3685 case KSZ8795_CHIP_ID: 3686 /* KSZ879x/KSZ877x/KSZ876x Errata DS80000687C Module 2 */ 3687 case KSZ9477_CHIP_ID: 3688 /* KSZ9477S Errata DS80000754A Module 4 */ 3689 case KSZ9567_CHIP_ID: 3690 /* KSZ9567S Errata DS80000756A Module 4 */ 3691 case KSZ9896_CHIP_ID: 3692 /* KSZ9896C Errata DS80000757A Module 3 */ 3693 case KSZ9897_CHIP_ID: 3694 case LAN9646_CHIP_ID: 3695 /* KSZ9897R Errata DS80000758C Module 4 */ 3696 /* Energy Efficient Ethernet (EEE) feature select must be 3697 * manually disabled 3698 * The EEE feature is enabled by default, but it is not fully 3699 * operational. It must be manually disabled through register 3700 * controls. If not disabled, the PHY ports can auto-negotiate 3701 * to enable EEE, and this feature can cause link drops when 3702 * linked to another device supporting EEE. 3703 * 3704 * The same item appears in the errata for all switches above. 3705 */ 3706 break; 3707 } 3708 3709 return false; 3710 } 3711 3712 static int ksz_set_mac_eee(struct dsa_switch *ds, int port, 3713 struct ethtool_keee *e) 3714 { 3715 struct ksz_device *dev = ds->priv; 3716 3717 if (!e->tx_lpi_enabled) { 3718 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 3719 return -EINVAL; 3720 } 3721 3722 if (e->tx_lpi_timer) { 3723 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 3724 return -EINVAL; 3725 } 3726 3727 return 0; 3728 } 3729 3730 static void ksz_set_xmii(struct ksz_device *dev, int port, 3731 phy_interface_t interface) 3732 { 3733 const u8 *bitval = dev->info->xmii_ctrl1; 3734 struct ksz_port *p = &dev->ports[port]; 3735 const u16 *regs = dev->info->regs; 3736 u8 data8; 3737 3738 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3739 3740 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 3741 P_RGMII_ID_EG_ENABLE); 3742 3743 switch (interface) { 3744 case PHY_INTERFACE_MODE_MII: 3745 data8 |= bitval[P_MII_SEL]; 3746 break; 3747 case PHY_INTERFACE_MODE_RMII: 3748 data8 |= bitval[P_RMII_SEL]; 3749 break; 3750 case PHY_INTERFACE_MODE_GMII: 3751 data8 |= bitval[P_GMII_SEL]; 3752 break; 3753 case PHY_INTERFACE_MODE_RGMII: 3754 case PHY_INTERFACE_MODE_RGMII_ID: 3755 case PHY_INTERFACE_MODE_RGMII_TXID: 3756 case PHY_INTERFACE_MODE_RGMII_RXID: 3757 data8 |= bitval[P_RGMII_SEL]; 3758 /* On KSZ9893, disable RGMII in-band status support */ 3759 if (dev->chip_id == KSZ9893_CHIP_ID || 3760 dev->chip_id == KSZ8563_CHIP_ID || 3761 dev->chip_id == KSZ9563_CHIP_ID || 3762 is_lan937x(dev)) 3763 data8 &= ~P_MII_MAC_MODE; 3764 break; 3765 default: 3766 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 3767 phy_modes(interface), port); 3768 return; 3769 } 3770 3771 if (p->rgmii_tx_val) 3772 data8 |= P_RGMII_ID_EG_ENABLE; 3773 3774 if (p->rgmii_rx_val) 3775 data8 |= P_RGMII_ID_IG_ENABLE; 3776 3777 /* Write the updated value */ 3778 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3779 } 3780 3781 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 3782 { 3783 const u8 *bitval = dev->info->xmii_ctrl1; 3784 const u16 *regs = dev->info->regs; 3785 phy_interface_t interface; 3786 u8 data8; 3787 u8 val; 3788 3789 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3790 3791 val = FIELD_GET(P_MII_SEL_M, data8); 3792 3793 if (val == bitval[P_MII_SEL]) { 3794 if (gbit) 3795 interface = PHY_INTERFACE_MODE_GMII; 3796 else 3797 interface = PHY_INTERFACE_MODE_MII; 3798 } else if (val == bitval[P_RMII_SEL]) { 3799 interface = PHY_INTERFACE_MODE_RMII; 3800 } else { 3801 interface = PHY_INTERFACE_MODE_RGMII; 3802 if (data8 & P_RGMII_ID_EG_ENABLE) 3803 interface = PHY_INTERFACE_MODE_RGMII_TXID; 3804 if (data8 & P_RGMII_ID_IG_ENABLE) { 3805 interface = PHY_INTERFACE_MODE_RGMII_RXID; 3806 if (data8 & P_RGMII_ID_EG_ENABLE) 3807 interface = PHY_INTERFACE_MODE_RGMII_ID; 3808 } 3809 } 3810 3811 return interface; 3812 } 3813 3814 static void ksz88x3_phylink_mac_config(struct phylink_config *config, 3815 unsigned int mode, 3816 const struct phylink_link_state *state) 3817 { 3818 struct dsa_port *dp = dsa_phylink_to_port(config); 3819 struct ksz_device *dev = dp->ds->priv; 3820 3821 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN); 3822 } 3823 3824 static void ksz_phylink_mac_config(struct phylink_config *config, 3825 unsigned int mode, 3826 const struct phylink_link_state *state) 3827 { 3828 struct dsa_port *dp = dsa_phylink_to_port(config); 3829 struct ksz_device *dev = dp->ds->priv; 3830 int port = dp->index; 3831 3832 /* Internal PHYs */ 3833 if (dev->info->internal_phy[port]) 3834 return; 3835 3836 /* No need to configure XMII control register when using SGMII. */ 3837 if (ksz_is_sgmii_port(dev, port)) 3838 return; 3839 3840 if (phylink_autoneg_inband(mode)) { 3841 dev_err(dev->dev, "In-band AN not supported!\n"); 3842 return; 3843 } 3844 3845 ksz_set_xmii(dev, port, state->interface); 3846 3847 if (dev->dev_ops->setup_rgmii_delay) 3848 dev->dev_ops->setup_rgmii_delay(dev, port); 3849 } 3850 3851 bool ksz_get_gbit(struct ksz_device *dev, int port) 3852 { 3853 const u8 *bitval = dev->info->xmii_ctrl1; 3854 const u16 *regs = dev->info->regs; 3855 bool gbit = false; 3856 u8 data8; 3857 bool val; 3858 3859 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3860 3861 val = FIELD_GET(P_GMII_1GBIT_M, data8); 3862 3863 if (val == bitval[P_GMII_1GBIT]) 3864 gbit = true; 3865 3866 return gbit; 3867 } 3868 3869 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 3870 { 3871 const u8 *bitval = dev->info->xmii_ctrl1; 3872 const u16 *regs = dev->info->regs; 3873 u8 data8; 3874 3875 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3876 3877 data8 &= ~P_GMII_1GBIT_M; 3878 3879 if (gbit) 3880 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 3881 else 3882 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 3883 3884 /* Write the updated value */ 3885 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3886 } 3887 3888 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 3889 { 3890 const u8 *bitval = dev->info->xmii_ctrl0; 3891 const u16 *regs = dev->info->regs; 3892 u8 data8; 3893 3894 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 3895 3896 data8 &= ~P_MII_100MBIT_M; 3897 3898 if (speed == SPEED_100) 3899 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 3900 else 3901 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 3902 3903 /* Write the updated value */ 3904 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 3905 } 3906 3907 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 3908 { 3909 if (speed == SPEED_1000) 3910 ksz_set_gbit(dev, port, true); 3911 else 3912 ksz_set_gbit(dev, port, false); 3913 3914 if (speed == SPEED_100 || speed == SPEED_10) 3915 ksz_set_100_10mbit(dev, port, speed); 3916 } 3917 3918 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 3919 bool tx_pause, bool rx_pause) 3920 { 3921 const u8 *bitval = dev->info->xmii_ctrl0; 3922 const u32 *masks = dev->info->masks; 3923 const u16 *regs = dev->info->regs; 3924 u8 mask; 3925 u8 val; 3926 3927 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 3928 masks[P_MII_RX_FLOW_CTRL]; 3929 3930 if (duplex == DUPLEX_FULL) 3931 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 3932 else 3933 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 3934 3935 if (tx_pause) 3936 val |= masks[P_MII_TX_FLOW_CTRL]; 3937 3938 if (rx_pause) 3939 val |= masks[P_MII_RX_FLOW_CTRL]; 3940 3941 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 3942 } 3943 3944 static void ksz9477_phylink_mac_link_up(struct phylink_config *config, 3945 struct phy_device *phydev, 3946 unsigned int mode, 3947 phy_interface_t interface, 3948 int speed, int duplex, bool tx_pause, 3949 bool rx_pause) 3950 { 3951 struct dsa_port *dp = dsa_phylink_to_port(config); 3952 struct ksz_device *dev = dp->ds->priv; 3953 int port = dp->index; 3954 struct ksz_port *p; 3955 3956 p = &dev->ports[port]; 3957 3958 /* Internal PHYs */ 3959 if (dev->info->internal_phy[port]) 3960 return; 3961 3962 p->phydev.speed = speed; 3963 3964 ksz_port_set_xmii_speed(dev, port, speed); 3965 3966 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 3967 } 3968 3969 static int ksz_switch_detect(struct ksz_device *dev) 3970 { 3971 u8 id1, id2, id4; 3972 u16 id16; 3973 u32 id32; 3974 int ret; 3975 3976 /* read chip id */ 3977 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 3978 if (ret) 3979 return ret; 3980 3981 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 3982 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 3983 3984 switch (id1) { 3985 case KSZ84_FAMILY_ID: 3986 dev->chip_id = KSZ8463_CHIP_ID; 3987 break; 3988 case KSZ87_FAMILY_ID: 3989 if (id2 == KSZ87_CHIP_ID_95) { 3990 u8 val; 3991 3992 dev->chip_id = KSZ8795_CHIP_ID; 3993 3994 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 3995 if (val & KSZ8_PORT_FIBER_MODE) 3996 dev->chip_id = KSZ8765_CHIP_ID; 3997 } else if (id2 == KSZ87_CHIP_ID_94) { 3998 dev->chip_id = KSZ8794_CHIP_ID; 3999 } else { 4000 return -ENODEV; 4001 } 4002 break; 4003 case KSZ88_FAMILY_ID: 4004 if (id2 == KSZ88_CHIP_ID_63) 4005 dev->chip_id = KSZ88X3_CHIP_ID; 4006 else 4007 return -ENODEV; 4008 break; 4009 case KSZ8895_FAMILY_ID: 4010 if (id2 == KSZ8895_CHIP_ID_95 || 4011 id2 == KSZ8895_CHIP_ID_95R) 4012 dev->chip_id = KSZ8895_CHIP_ID; 4013 else 4014 return -ENODEV; 4015 ret = ksz_read8(dev, REG_KSZ8864_CHIP_ID, &id4); 4016 if (ret) 4017 return ret; 4018 if (id4 & SW_KSZ8864) 4019 dev->chip_id = KSZ8864_CHIP_ID; 4020 break; 4021 default: 4022 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 4023 if (ret) 4024 return ret; 4025 4026 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 4027 id32 &= ~0xFF; 4028 4029 switch (id32) { 4030 case KSZ9477_CHIP_ID: 4031 case KSZ9896_CHIP_ID: 4032 case KSZ9897_CHIP_ID: 4033 case KSZ9567_CHIP_ID: 4034 case KSZ8567_CHIP_ID: 4035 case LAN9370_CHIP_ID: 4036 case LAN9371_CHIP_ID: 4037 case LAN9372_CHIP_ID: 4038 case LAN9373_CHIP_ID: 4039 case LAN9374_CHIP_ID: 4040 4041 /* LAN9646 does not have its own chip id. */ 4042 if (dev->chip_id != LAN9646_CHIP_ID) 4043 dev->chip_id = id32; 4044 break; 4045 case KSZ9893_CHIP_ID: 4046 ret = ksz_read8(dev, REG_CHIP_ID4, 4047 &id4); 4048 if (ret) 4049 return ret; 4050 4051 if (id4 == SKU_ID_KSZ8563) 4052 dev->chip_id = KSZ8563_CHIP_ID; 4053 else if (id4 == SKU_ID_KSZ9563) 4054 dev->chip_id = KSZ9563_CHIP_ID; 4055 else 4056 dev->chip_id = KSZ9893_CHIP_ID; 4057 4058 break; 4059 default: 4060 dev_err(dev->dev, 4061 "unsupported switch detected %x)\n", id32); 4062 return -ENODEV; 4063 } 4064 } 4065 return 0; 4066 } 4067 4068 static int ksz_cls_flower_add(struct dsa_switch *ds, int port, 4069 struct flow_cls_offload *cls, bool ingress) 4070 { 4071 struct ksz_device *dev = ds->priv; 4072 4073 switch (dev->chip_id) { 4074 case KSZ8563_CHIP_ID: 4075 case KSZ8567_CHIP_ID: 4076 case KSZ9477_CHIP_ID: 4077 case KSZ9563_CHIP_ID: 4078 case KSZ9567_CHIP_ID: 4079 case KSZ9893_CHIP_ID: 4080 case KSZ9896_CHIP_ID: 4081 case KSZ9897_CHIP_ID: 4082 case LAN9646_CHIP_ID: 4083 return ksz9477_cls_flower_add(ds, port, cls, ingress); 4084 } 4085 4086 return -EOPNOTSUPP; 4087 } 4088 4089 static int ksz_cls_flower_del(struct dsa_switch *ds, int port, 4090 struct flow_cls_offload *cls, bool ingress) 4091 { 4092 struct ksz_device *dev = ds->priv; 4093 4094 switch (dev->chip_id) { 4095 case KSZ8563_CHIP_ID: 4096 case KSZ8567_CHIP_ID: 4097 case KSZ9477_CHIP_ID: 4098 case KSZ9563_CHIP_ID: 4099 case KSZ9567_CHIP_ID: 4100 case KSZ9893_CHIP_ID: 4101 case KSZ9896_CHIP_ID: 4102 case KSZ9897_CHIP_ID: 4103 case LAN9646_CHIP_ID: 4104 return ksz9477_cls_flower_del(ds, port, cls, ingress); 4105 } 4106 4107 return -EOPNOTSUPP; 4108 } 4109 4110 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 4111 * is converted to Hex-decimal using the successive multiplication method. On 4112 * every step, integer part is taken and decimal part is carry forwarded. 4113 */ 4114 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 4115 { 4116 u32 cinc = 0; 4117 u32 txrate; 4118 u32 rate; 4119 u8 temp; 4120 u8 i; 4121 4122 txrate = idle_slope - send_slope; 4123 4124 if (!txrate) 4125 return -EINVAL; 4126 4127 rate = idle_slope; 4128 4129 /* 24 bit register */ 4130 for (i = 0; i < 6; i++) { 4131 rate = rate * 16; 4132 4133 temp = rate / txrate; 4134 4135 rate %= txrate; 4136 4137 cinc = ((cinc << 4) | temp); 4138 } 4139 4140 *bw = cinc; 4141 4142 return 0; 4143 } 4144 4145 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 4146 u8 shaper) 4147 { 4148 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 4149 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 4150 FIELD_PREP(MTI_SHAPING_M, shaper)); 4151 } 4152 4153 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 4154 struct tc_cbs_qopt_offload *qopt) 4155 { 4156 struct ksz_device *dev = ds->priv; 4157 int ret; 4158 u32 bw; 4159 4160 if (!dev->info->tc_cbs_supported) 4161 return -EOPNOTSUPP; 4162 4163 if (qopt->queue > dev->info->num_tx_queues) 4164 return -EINVAL; 4165 4166 /* Queue Selection */ 4167 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 4168 if (ret) 4169 return ret; 4170 4171 if (!qopt->enable) 4172 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 4173 MTI_SHAPING_OFF); 4174 4175 /* High Credit */ 4176 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 4177 qopt->hicredit); 4178 if (ret) 4179 return ret; 4180 4181 /* Low Credit */ 4182 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 4183 qopt->locredit); 4184 if (ret) 4185 return ret; 4186 4187 /* Credit Increment Register */ 4188 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 4189 if (ret) 4190 return ret; 4191 4192 if (dev->dev_ops->tc_cbs_set_cinc) { 4193 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 4194 if (ret) 4195 return ret; 4196 } 4197 4198 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 4199 MTI_SHAPING_SRP); 4200 } 4201 4202 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 4203 { 4204 int queue, ret; 4205 4206 /* Configuration will not take effect until the last Port Queue X 4207 * Egress Limit Control Register is written. 4208 */ 4209 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 4210 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 4211 KSZ9477_OUT_RATE_NO_LIMIT); 4212 if (ret) 4213 return ret; 4214 } 4215 4216 return 0; 4217 } 4218 4219 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 4220 int band) 4221 { 4222 /* Compared to queues, bands prioritize packets differently. In strict 4223 * priority mode, the lowest priority is assigned to Queue 0 while the 4224 * highest priority is given to Band 0. 4225 */ 4226 return p->bands - 1 - band; 4227 } 4228 4229 static u8 ksz8463_tc_ctrl(int port, int queue) 4230 { 4231 u8 reg; 4232 4233 reg = 0xC8 + port * 4; 4234 reg += ((3 - queue) / 2) * 2; 4235 reg++; 4236 reg -= (queue & 1); 4237 return reg; 4238 } 4239 4240 /** 4241 * ksz88x3_tc_ets_add - Configure ETS (Enhanced Transmission Selection) 4242 * for a port on KSZ88x3 switch 4243 * @dev: Pointer to the KSZ switch device structure 4244 * @port: Port number to configure 4245 * @p: Pointer to offload replace parameters describing ETS bands and mapping 4246 * 4247 * The KSZ88x3 supports two scheduling modes: Strict Priority and 4248 * Weighted Fair Queuing (WFQ). Both modes have fixed behavior: 4249 * - No configurable queue-to-priority mapping 4250 * - No weight adjustment in WFQ mode 4251 * 4252 * This function configures the switch to use strict priority mode by 4253 * clearing the WFQ enable bit for all queues associated with ETS bands. 4254 * If strict priority is not explicitly requested, the switch will default 4255 * to WFQ mode. 4256 * 4257 * Return: 0 on success, or a negative error code on failure 4258 */ 4259 static int ksz88x3_tc_ets_add(struct ksz_device *dev, int port, 4260 struct tc_ets_qopt_offload_replace_params *p) 4261 { 4262 int ret, band; 4263 4264 /* Only strict priority mode is supported for now. 4265 * WFQ is implicitly enabled when strict mode is disabled. 4266 */ 4267 for (band = 0; band < p->bands; band++) { 4268 int queue = ksz_ets_band_to_queue(p, band); 4269 u8 reg; 4270 4271 /* Calculate TXQ Split Control register address for this 4272 * port/queue 4273 */ 4274 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue); 4275 if (ksz_is_ksz8463(dev)) 4276 reg = ksz8463_tc_ctrl(port, queue); 4277 4278 /* Clear WFQ enable bit to select strict priority scheduling */ 4279 ret = ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE, 0); 4280 if (ret) 4281 return ret; 4282 } 4283 4284 return 0; 4285 } 4286 4287 /** 4288 * ksz88x3_tc_ets_del - Reset ETS (Enhanced Transmission Selection) config 4289 * for a port on KSZ88x3 switch 4290 * @dev: Pointer to the KSZ switch device structure 4291 * @port: Port number to reset 4292 * 4293 * The KSZ88x3 supports only fixed scheduling modes: Strict Priority or 4294 * Weighted Fair Queuing (WFQ), with no reconfiguration of weights or 4295 * queue mapping. This function resets the port’s scheduling mode to 4296 * the default, which is WFQ, by enabling the WFQ bit for all queues. 4297 * 4298 * Return: 0 on success, or a negative error code on failure 4299 */ 4300 static int ksz88x3_tc_ets_del(struct ksz_device *dev, int port) 4301 { 4302 int ret, queue; 4303 4304 /* Iterate over all transmit queues for this port */ 4305 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 4306 u8 reg; 4307 4308 /* Calculate TXQ Split Control register address for this 4309 * port/queue 4310 */ 4311 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue); 4312 if (ksz_is_ksz8463(dev)) 4313 reg = ksz8463_tc_ctrl(port, queue); 4314 4315 /* Set WFQ enable bit to revert back to default scheduling 4316 * mode 4317 */ 4318 ret = ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE, 4319 KSZ8873_TXQ_WFQ_ENABLE); 4320 if (ret) 4321 return ret; 4322 } 4323 4324 return 0; 4325 } 4326 4327 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 4328 { 4329 int ret; 4330 4331 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 4332 if (ret) 4333 return ret; 4334 4335 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 4336 MTI_SHAPING_OFF); 4337 } 4338 4339 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 4340 int weight) 4341 { 4342 int ret; 4343 4344 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 4345 if (ret) 4346 return ret; 4347 4348 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 4349 MTI_SHAPING_OFF); 4350 if (ret) 4351 return ret; 4352 4353 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 4354 } 4355 4356 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 4357 struct tc_ets_qopt_offload_replace_params *p) 4358 { 4359 int ret, band, tc_prio; 4360 u32 queue_map = 0; 4361 4362 /* In order to ensure proper prioritization, it is necessary to set the 4363 * rate limit for the related queue to zero. Otherwise strict priority 4364 * or WRR mode will not work. This is a hardware limitation. 4365 */ 4366 ret = ksz_disable_egress_rate_limit(dev, port); 4367 if (ret) 4368 return ret; 4369 4370 /* Configure queue scheduling mode for all bands. Currently only strict 4371 * prio mode is supported. 4372 */ 4373 for (band = 0; band < p->bands; band++) { 4374 int queue = ksz_ets_band_to_queue(p, band); 4375 4376 ret = ksz_queue_set_strict(dev, port, queue); 4377 if (ret) 4378 return ret; 4379 } 4380 4381 /* Configure the mapping between traffic classes and queues. Note: 4382 * priomap variable support 16 traffic classes, but the chip can handle 4383 * only 8 classes. 4384 */ 4385 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 4386 int queue; 4387 4388 if (tc_prio >= dev->info->num_ipms) 4389 break; 4390 4391 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 4392 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 4393 } 4394 4395 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 4396 } 4397 4398 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 4399 { 4400 int ret, queue; 4401 4402 /* To restore the default chip configuration, set all queues to use the 4403 * WRR scheduler with a weight of 1. 4404 */ 4405 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 4406 ret = ksz_queue_set_wrr(dev, port, queue, 4407 KSZ9477_DEFAULT_WRR_WEIGHT); 4408 4409 if (ret) 4410 return ret; 4411 } 4412 4413 /* Revert the queue mapping for TC-priority to its default setting on 4414 * the chip. 4415 */ 4416 return ksz9477_set_default_prio_queue_mapping(dev, port); 4417 } 4418 4419 static int ksz_tc_ets_validate(struct ksz_device *dev, int port, 4420 struct tc_ets_qopt_offload_replace_params *p) 4421 { 4422 int band; 4423 4424 /* Since it is not feasible to share one port among multiple qdisc, 4425 * the user must configure all available queues appropriately. 4426 */ 4427 if (p->bands != dev->info->num_tx_queues) { 4428 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 4429 dev->info->num_tx_queues); 4430 return -EOPNOTSUPP; 4431 } 4432 4433 for (band = 0; band < p->bands; ++band) { 4434 /* The KSZ switches utilize a weighted round robin configuration 4435 * where a certain number of packets can be transmitted from a 4436 * queue before the next queue is serviced. For more information 4437 * on this, refer to section 5.2.8.4 of the KSZ8565R 4438 * documentation on the Port Transmit Queue Control 1 Register. 4439 * However, the current ETS Qdisc implementation (as of February 4440 * 2023) assigns a weight to each queue based on the number of 4441 * bytes or extrapolated bandwidth in percentages. Since this 4442 * differs from the KSZ switches' method and we don't want to 4443 * fake support by converting bytes to packets, it is better to 4444 * return an error instead. 4445 */ 4446 if (p->quanta[band]) { 4447 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 4448 return -EOPNOTSUPP; 4449 } 4450 } 4451 4452 return 0; 4453 } 4454 4455 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 4456 struct tc_ets_qopt_offload *qopt) 4457 { 4458 struct ksz_device *dev = ds->priv; 4459 int ret; 4460 4461 if (is_ksz8(dev) && !(ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev))) 4462 return -EOPNOTSUPP; 4463 4464 if (qopt->parent != TC_H_ROOT) { 4465 dev_err(dev->dev, "Parent should be \"root\"\n"); 4466 return -EOPNOTSUPP; 4467 } 4468 4469 switch (qopt->command) { 4470 case TC_ETS_REPLACE: 4471 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 4472 if (ret) 4473 return ret; 4474 4475 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 4476 return ksz88x3_tc_ets_add(dev, port, 4477 &qopt->replace_params); 4478 else 4479 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 4480 case TC_ETS_DESTROY: 4481 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 4482 return ksz88x3_tc_ets_del(dev, port); 4483 else 4484 return ksz_tc_ets_del(dev, port); 4485 case TC_ETS_STATS: 4486 case TC_ETS_GRAFT: 4487 return -EOPNOTSUPP; 4488 } 4489 4490 return -EOPNOTSUPP; 4491 } 4492 4493 static int ksz_setup_tc(struct dsa_switch *ds, int port, 4494 enum tc_setup_type type, void *type_data) 4495 { 4496 switch (type) { 4497 case TC_SETUP_QDISC_CBS: 4498 return ksz_setup_tc_cbs(ds, port, type_data); 4499 case TC_SETUP_QDISC_ETS: 4500 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 4501 default: 4502 return -EOPNOTSUPP; 4503 } 4504 } 4505 4506 /** 4507 * ksz_handle_wake_reason - Handle wake reason on a specified port. 4508 * @dev: The device structure. 4509 * @port: The port number. 4510 * 4511 * This function reads the PME (Power Management Event) status register of a 4512 * specified port to determine the wake reason. If there is no wake event, it 4513 * returns early. Otherwise, it logs the wake reason which could be due to a 4514 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register 4515 * is then cleared to acknowledge the handling of the wake event. 4516 * 4517 * Return: 0 on success, or an error code on failure. 4518 */ 4519 int ksz_handle_wake_reason(struct ksz_device *dev, int port) 4520 { 4521 const struct ksz_dev_ops *ops = dev->dev_ops; 4522 const u16 *regs = dev->info->regs; 4523 u8 pme_status; 4524 int ret; 4525 4526 ret = ops->pme_pread8(dev, port, regs[REG_PORT_PME_STATUS], 4527 &pme_status); 4528 if (ret) 4529 return ret; 4530 4531 if (!pme_status) 4532 return 0; 4533 4534 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port, 4535 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "", 4536 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "", 4537 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : ""); 4538 4539 return ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_STATUS], 4540 pme_status); 4541 } 4542 4543 /** 4544 * ksz_get_wol - Get Wake-on-LAN settings for a specified port. 4545 * @ds: The dsa_switch structure. 4546 * @port: The port number. 4547 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 4548 * 4549 * This function checks the device PME wakeup_source flag and chip_id. 4550 * If enabled and supported, it sets the supported and active WoL 4551 * flags. 4552 */ 4553 static void ksz_get_wol(struct dsa_switch *ds, int port, 4554 struct ethtool_wolinfo *wol) 4555 { 4556 struct ksz_device *dev = ds->priv; 4557 const u16 *regs = dev->info->regs; 4558 u8 pme_ctrl; 4559 int ret; 4560 4561 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4562 return; 4563 4564 if (!dev->wakeup_source) 4565 return; 4566 4567 wol->supported = WAKE_PHY; 4568 4569 /* Check if the current MAC address on this port can be set 4570 * as global for WAKE_MAGIC support. The result may vary 4571 * dynamically based on other ports configurations. 4572 */ 4573 if (ksz_is_port_mac_global_usable(dev->ds, port)) 4574 wol->supported |= WAKE_MAGIC; 4575 4576 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 4577 &pme_ctrl); 4578 if (ret) 4579 return; 4580 4581 if (pme_ctrl & PME_WOL_MAGICPKT) 4582 wol->wolopts |= WAKE_MAGIC; 4583 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY)) 4584 wol->wolopts |= WAKE_PHY; 4585 } 4586 4587 /** 4588 * ksz_set_wol - Set Wake-on-LAN settings for a specified port. 4589 * @ds: The dsa_switch structure. 4590 * @port: The port number. 4591 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 4592 * 4593 * This function configures Wake-on-LAN (WoL) settings for a specified 4594 * port. It validates the provided WoL options, checks if PME is 4595 * enabled and supported, clears any previous wake reasons, and sets 4596 * the Magic Packet flag in the port's PME control register if 4597 * specified. 4598 * 4599 * Return: 0 on success, or other error codes on failure. 4600 */ 4601 static int ksz_set_wol(struct dsa_switch *ds, int port, 4602 struct ethtool_wolinfo *wol) 4603 { 4604 u8 pme_ctrl = 0, pme_ctrl_old = 0; 4605 struct ksz_device *dev = ds->priv; 4606 const u16 *regs = dev->info->regs; 4607 bool magic_switched_off; 4608 bool magic_switched_on; 4609 int ret; 4610 4611 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC)) 4612 return -EINVAL; 4613 4614 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4615 return -EOPNOTSUPP; 4616 4617 if (!dev->wakeup_source) 4618 return -EOPNOTSUPP; 4619 4620 ret = ksz_handle_wake_reason(dev, port); 4621 if (ret) 4622 return ret; 4623 4624 if (wol->wolopts & WAKE_MAGIC) 4625 pme_ctrl |= PME_WOL_MAGICPKT; 4626 if (wol->wolopts & WAKE_PHY) 4627 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY; 4628 4629 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 4630 &pme_ctrl_old); 4631 if (ret) 4632 return ret; 4633 4634 if (pme_ctrl_old == pme_ctrl) 4635 return 0; 4636 4637 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) && 4638 !(pme_ctrl & PME_WOL_MAGICPKT); 4639 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) && 4640 (pme_ctrl & PME_WOL_MAGICPKT); 4641 4642 /* To keep reference count of MAC address, we should do this 4643 * operation only on change of WOL settings. 4644 */ 4645 if (magic_switched_on) { 4646 ret = ksz_switch_macaddr_get(dev->ds, port, NULL); 4647 if (ret) 4648 return ret; 4649 } else if (magic_switched_off) { 4650 ksz_switch_macaddr_put(dev->ds); 4651 } 4652 4653 ret = dev->dev_ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 4654 pme_ctrl); 4655 if (ret) { 4656 if (magic_switched_on) 4657 ksz_switch_macaddr_put(dev->ds); 4658 return ret; 4659 } 4660 4661 return 0; 4662 } 4663 4664 /** 4665 * ksz_wol_pre_shutdown - Prepares the switch device for shutdown while 4666 * considering Wake-on-LAN (WoL) settings. 4667 * @dev: The switch device structure. 4668 * @wol_enabled: Pointer to a boolean which will be set to true if WoL is 4669 * enabled on any port. 4670 * 4671 * This function prepares the switch device for a safe shutdown while taking 4672 * into account the Wake-on-LAN (WoL) settings on the user ports. It updates 4673 * the wol_enabled flag accordingly to reflect whether WoL is active on any 4674 * port. 4675 */ 4676 static void ksz_wol_pre_shutdown(struct ksz_device *dev, bool *wol_enabled) 4677 { 4678 const struct ksz_dev_ops *ops = dev->dev_ops; 4679 const u16 *regs = dev->info->regs; 4680 u8 pme_pin_en = PME_ENABLE; 4681 struct dsa_port *dp; 4682 int ret; 4683 4684 *wol_enabled = false; 4685 4686 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4687 return; 4688 4689 if (!dev->wakeup_source) 4690 return; 4691 4692 dsa_switch_for_each_user_port(dp, dev->ds) { 4693 u8 pme_ctrl = 0; 4694 4695 ret = ops->pme_pread8(dev, dp->index, 4696 regs[REG_PORT_PME_CTRL], &pme_ctrl); 4697 if (!ret && pme_ctrl) 4698 *wol_enabled = true; 4699 4700 /* make sure there are no pending wake events which would 4701 * prevent the device from going to sleep/shutdown. 4702 */ 4703 ksz_handle_wake_reason(dev, dp->index); 4704 } 4705 4706 /* Now we are save to enable PME pin. */ 4707 if (*wol_enabled) { 4708 if (dev->pme_active_high) 4709 pme_pin_en |= PME_POLARITY; 4710 ops->pme_write8(dev, regs[REG_SW_PME_CTRL], pme_pin_en); 4711 if (ksz_is_ksz87xx(dev)) 4712 ksz_write8(dev, KSZ87XX_REG_INT_EN, KSZ87XX_INT_PME_MASK); 4713 } 4714 } 4715 4716 static int ksz_port_set_mac_address(struct dsa_switch *ds, int port, 4717 const unsigned char *addr) 4718 { 4719 struct dsa_port *dp = dsa_to_port(ds, port); 4720 struct ethtool_wolinfo wol; 4721 4722 if (dp->hsr_dev) { 4723 dev_err(ds->dev, 4724 "Cannot change MAC address on port %d with active HSR offload\n", 4725 port); 4726 return -EBUSY; 4727 } 4728 4729 /* Need to initialize variable as the code to fill in settings may 4730 * not be executed. 4731 */ 4732 wol.wolopts = 0; 4733 4734 ksz_get_wol(ds, dp->index, &wol); 4735 if (wol.wolopts & WAKE_MAGIC) { 4736 dev_err(ds->dev, 4737 "Cannot change MAC address on port %d with active Wake on Magic Packet\n", 4738 port); 4739 return -EBUSY; 4740 } 4741 4742 return 0; 4743 } 4744 4745 /** 4746 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port 4747 * can be used as a global address. 4748 * @ds: Pointer to the DSA switch structure. 4749 * @port: The port number on which the MAC address is to be checked. 4750 * 4751 * This function examines the MAC address set on the specified port and 4752 * determines if it can be used as a global address for the switch. 4753 * 4754 * Return: true if the port's MAC address can be used as a global address, false 4755 * otherwise. 4756 */ 4757 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port) 4758 { 4759 struct net_device *user = dsa_to_port(ds, port)->user; 4760 const unsigned char *addr = user->dev_addr; 4761 struct ksz_switch_macaddr *switch_macaddr; 4762 struct ksz_device *dev = ds->priv; 4763 4764 ASSERT_RTNL(); 4765 4766 switch_macaddr = dev->switch_macaddr; 4767 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr)) 4768 return false; 4769 4770 return true; 4771 } 4772 4773 /** 4774 * ksz_switch_macaddr_get - Program the switch's MAC address register. 4775 * @ds: DSA switch instance. 4776 * @port: Port number. 4777 * @extack: Netlink extended acknowledgment. 4778 * 4779 * This function programs the switch's MAC address register with the MAC address 4780 * of the requesting user port. This single address is used by the switch for 4781 * multiple features like HSR self-address filtering and WoL. Other user ports 4782 * can share ownership of this address as long as their MAC address is the same. 4783 * The MAC addresses of user ports must not change while they have ownership of 4784 * the switch MAC address. 4785 * 4786 * Return: 0 on success, or other error codes on failure. 4787 */ 4788 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 4789 struct netlink_ext_ack *extack) 4790 { 4791 struct net_device *user = dsa_to_port(ds, port)->user; 4792 const unsigned char *addr = user->dev_addr; 4793 struct ksz_switch_macaddr *switch_macaddr; 4794 struct ksz_device *dev = ds->priv; 4795 const u16 *regs = dev->info->regs; 4796 int i, ret; 4797 4798 /* Make sure concurrent MAC address changes are blocked */ 4799 ASSERT_RTNL(); 4800 4801 switch_macaddr = dev->switch_macaddr; 4802 if (switch_macaddr) { 4803 if (!ether_addr_equal(switch_macaddr->addr, addr)) { 4804 NL_SET_ERR_MSG_FMT_MOD(extack, 4805 "Switch already configured for MAC address %pM", 4806 switch_macaddr->addr); 4807 return -EBUSY; 4808 } 4809 4810 refcount_inc(&switch_macaddr->refcount); 4811 return 0; 4812 } 4813 4814 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL); 4815 if (!switch_macaddr) 4816 return -ENOMEM; 4817 4818 ether_addr_copy(switch_macaddr->addr, addr); 4819 refcount_set(&switch_macaddr->refcount, 1); 4820 dev->switch_macaddr = switch_macaddr; 4821 4822 /* Program the switch MAC address to hardware */ 4823 for (i = 0; i < ETH_ALEN; i++) { 4824 if (ksz_is_ksz8463(dev)) { 4825 u16 addr16 = ((u16)addr[i] << 8) | addr[i + 1]; 4826 4827 ret = ksz_write16(dev, regs[REG_SW_MAC_ADDR] + i, 4828 addr16); 4829 i++; 4830 } else { 4831 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 4832 addr[i]); 4833 } 4834 if (ret) 4835 goto macaddr_drop; 4836 } 4837 4838 return 0; 4839 4840 macaddr_drop: 4841 dev->switch_macaddr = NULL; 4842 refcount_set(&switch_macaddr->refcount, 0); 4843 kfree(switch_macaddr); 4844 4845 return ret; 4846 } 4847 4848 void ksz_switch_macaddr_put(struct dsa_switch *ds) 4849 { 4850 struct ksz_switch_macaddr *switch_macaddr; 4851 struct ksz_device *dev = ds->priv; 4852 const u16 *regs = dev->info->regs; 4853 int i; 4854 4855 /* Make sure concurrent MAC address changes are blocked */ 4856 ASSERT_RTNL(); 4857 4858 switch_macaddr = dev->switch_macaddr; 4859 if (!refcount_dec_and_test(&switch_macaddr->refcount)) 4860 return; 4861 4862 for (i = 0; i < ETH_ALEN; i++) 4863 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0); 4864 4865 dev->switch_macaddr = NULL; 4866 kfree(switch_macaddr); 4867 } 4868 4869 static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr, 4870 struct netlink_ext_ack *extack) 4871 { 4872 struct ksz_device *dev = ds->priv; 4873 enum hsr_version ver; 4874 int ret; 4875 4876 ret = hsr_get_version(hsr, &ver); 4877 if (ret) 4878 return ret; 4879 4880 if (dev->chip_id != KSZ9477_CHIP_ID) { 4881 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload"); 4882 return -EOPNOTSUPP; 4883 } 4884 4885 /* KSZ9477 can support HW offloading of only 1 HSR device */ 4886 if (dev->hsr_dev && hsr != dev->hsr_dev) { 4887 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR"); 4888 return -EOPNOTSUPP; 4889 } 4890 4891 /* KSZ9477 only supports HSR v0 and v1 */ 4892 if (!(ver == HSR_V0 || ver == HSR_V1)) { 4893 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported"); 4894 return -EOPNOTSUPP; 4895 } 4896 4897 /* KSZ9477 can only perform HSR offloading for up to two ports */ 4898 if (hweight8(dev->hsr_ports) >= 2) { 4899 NL_SET_ERR_MSG_MOD(extack, 4900 "Cannot offload more than two ports - using software HSR"); 4901 return -EOPNOTSUPP; 4902 } 4903 4904 /* Self MAC address filtering, to avoid frames traversing 4905 * the HSR ring more than once. 4906 */ 4907 ret = ksz_switch_macaddr_get(ds, port, extack); 4908 if (ret) 4909 return ret; 4910 4911 ksz9477_hsr_join(ds, port, hsr); 4912 dev->hsr_dev = hsr; 4913 dev->hsr_ports |= BIT(port); 4914 4915 return 0; 4916 } 4917 4918 static int ksz_hsr_leave(struct dsa_switch *ds, int port, 4919 struct net_device *hsr) 4920 { 4921 struct ksz_device *dev = ds->priv; 4922 4923 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID); 4924 4925 ksz9477_hsr_leave(ds, port, hsr); 4926 dev->hsr_ports &= ~BIT(port); 4927 if (!dev->hsr_ports) 4928 dev->hsr_dev = NULL; 4929 4930 ksz_switch_macaddr_put(ds); 4931 4932 return 0; 4933 } 4934 4935 static int ksz_suspend(struct dsa_switch *ds) 4936 { 4937 struct ksz_device *dev = ds->priv; 4938 4939 cancel_delayed_work_sync(&dev->mib_read); 4940 return 0; 4941 } 4942 4943 static int ksz_resume(struct dsa_switch *ds) 4944 { 4945 struct ksz_device *dev = ds->priv; 4946 4947 if (dev->mib_read_interval) 4948 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 4949 return 0; 4950 } 4951 4952 static const struct dsa_switch_ops ksz_switch_ops = { 4953 .get_tag_protocol = ksz_get_tag_protocol, 4954 .connect_tag_protocol = ksz_connect_tag_protocol, 4955 .get_phy_flags = ksz_get_phy_flags, 4956 .setup = ksz_setup, 4957 .teardown = ksz_teardown, 4958 .phy_read = ksz_phy_read16, 4959 .phy_write = ksz_phy_write16, 4960 .phylink_get_caps = ksz_phylink_get_caps, 4961 .port_setup = ksz_port_setup, 4962 .set_ageing_time = ksz_set_ageing_time, 4963 .get_strings = ksz_get_strings, 4964 .get_ethtool_stats = ksz_get_ethtool_stats, 4965 .get_sset_count = ksz_sset_count, 4966 .port_bridge_join = ksz_port_bridge_join, 4967 .port_bridge_leave = ksz_port_bridge_leave, 4968 .port_hsr_join = ksz_hsr_join, 4969 .port_hsr_leave = ksz_hsr_leave, 4970 .port_set_mac_address = ksz_port_set_mac_address, 4971 .port_stp_state_set = ksz_port_stp_state_set, 4972 .port_teardown = ksz_port_teardown, 4973 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 4974 .port_bridge_flags = ksz_port_bridge_flags, 4975 .port_fast_age = ksz_port_fast_age, 4976 .port_vlan_filtering = ksz_port_vlan_filtering, 4977 .port_vlan_add = ksz_port_vlan_add, 4978 .port_vlan_del = ksz_port_vlan_del, 4979 .port_fdb_dump = ksz_port_fdb_dump, 4980 .port_fdb_add = ksz_port_fdb_add, 4981 .port_fdb_del = ksz_port_fdb_del, 4982 .port_mdb_add = ksz_port_mdb_add, 4983 .port_mdb_del = ksz_port_mdb_del, 4984 .port_mirror_add = ksz_port_mirror_add, 4985 .port_mirror_del = ksz_port_mirror_del, 4986 .get_stats64 = ksz_get_stats64, 4987 .get_pause_stats = ksz_get_pause_stats, 4988 .port_change_mtu = ksz_change_mtu, 4989 .port_max_mtu = ksz_max_mtu, 4990 .get_wol = ksz_get_wol, 4991 .set_wol = ksz_set_wol, 4992 .suspend = ksz_suspend, 4993 .resume = ksz_resume, 4994 .get_ts_info = ksz_get_ts_info, 4995 .port_hwtstamp_get = ksz_hwtstamp_get, 4996 .port_hwtstamp_set = ksz_hwtstamp_set, 4997 .port_txtstamp = ksz_port_txtstamp, 4998 .port_rxtstamp = ksz_port_rxtstamp, 4999 .cls_flower_add = ksz_cls_flower_add, 5000 .cls_flower_del = ksz_cls_flower_del, 5001 .port_setup_tc = ksz_setup_tc, 5002 .support_eee = ksz_support_eee, 5003 .set_mac_eee = ksz_set_mac_eee, 5004 .port_get_default_prio = ksz_port_get_default_prio, 5005 .port_set_default_prio = ksz_port_set_default_prio, 5006 .port_get_dscp_prio = ksz_port_get_dscp_prio, 5007 .port_add_dscp_prio = ksz_port_add_dscp_prio, 5008 .port_del_dscp_prio = ksz_port_del_dscp_prio, 5009 .port_get_apptrust = ksz_port_get_apptrust, 5010 .port_set_apptrust = ksz_port_set_apptrust, 5011 }; 5012 5013 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 5014 { 5015 struct dsa_switch *ds; 5016 struct ksz_device *swdev; 5017 5018 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 5019 if (!ds) 5020 return NULL; 5021 5022 ds->dev = base; 5023 ds->num_ports = DSA_MAX_PORTS; 5024 ds->ops = &ksz_switch_ops; 5025 5026 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 5027 if (!swdev) 5028 return NULL; 5029 5030 ds->priv = swdev; 5031 swdev->dev = base; 5032 5033 swdev->ds = ds; 5034 swdev->priv = priv; 5035 5036 return swdev; 5037 } 5038 EXPORT_SYMBOL(ksz_switch_alloc); 5039 5040 /** 5041 * ksz_switch_shutdown - Shutdown routine for the switch device. 5042 * @dev: The switch device structure. 5043 * 5044 * This function is responsible for initiating a shutdown sequence for the 5045 * switch device. It invokes the reset operation defined in the device 5046 * operations, if available, to reset the switch. Subsequently, it calls the 5047 * DSA framework's shutdown function to ensure a proper shutdown of the DSA 5048 * switch. 5049 */ 5050 void ksz_switch_shutdown(struct ksz_device *dev) 5051 { 5052 bool wol_enabled = false; 5053 5054 ksz_wol_pre_shutdown(dev, &wol_enabled); 5055 5056 if (dev->dev_ops->reset && !wol_enabled) 5057 dev->dev_ops->reset(dev); 5058 5059 dsa_switch_shutdown(dev->ds); 5060 } 5061 EXPORT_SYMBOL(ksz_switch_shutdown); 5062 5063 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 5064 struct device_node *port_dn) 5065 { 5066 phy_interface_t phy_mode = dev->ports[port_num].interface; 5067 int rx_delay = -1, tx_delay = -1; 5068 5069 if (!phy_interface_mode_is_rgmii(phy_mode)) 5070 return; 5071 5072 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 5073 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 5074 5075 if (rx_delay == -1 && tx_delay == -1) { 5076 dev_warn(dev->dev, 5077 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 5078 "please update device tree to specify \"rx-internal-delay-ps\" and " 5079 "\"tx-internal-delay-ps\"", 5080 port_num); 5081 5082 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 5083 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 5084 rx_delay = 2000; 5085 5086 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 5087 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 5088 tx_delay = 2000; 5089 } 5090 5091 if (rx_delay < 0) 5092 rx_delay = 0; 5093 if (tx_delay < 0) 5094 tx_delay = 0; 5095 5096 dev->ports[port_num].rgmii_rx_val = rx_delay; 5097 dev->ports[port_num].rgmii_tx_val = tx_delay; 5098 } 5099 5100 /** 5101 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding 5102 * register value. 5103 * @array: The array of drive strength values to search. 5104 * @array_size: The size of the array. 5105 * @microamp: The drive strength value in microamp to be converted. 5106 * 5107 * This function searches the array of drive strength values for the given 5108 * microamp value and returns the corresponding register value for that drive. 5109 * 5110 * Returns: If found, the corresponding register value for that drive strength 5111 * is returned. Otherwise, -EINVAL is returned indicating an invalid value. 5112 */ 5113 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array, 5114 size_t array_size, int microamp) 5115 { 5116 int i; 5117 5118 for (i = 0; i < array_size; i++) { 5119 if (array[i].microamp == microamp) 5120 return array[i].reg_val; 5121 } 5122 5123 return -EINVAL; 5124 } 5125 5126 /** 5127 * ksz_drive_strength_error() - Report invalid drive strength value 5128 * @dev: ksz device 5129 * @array: The array of drive strength values to search. 5130 * @array_size: The size of the array. 5131 * @microamp: Invalid drive strength value in microamp 5132 * 5133 * This function logs an error message when an unsupported drive strength value 5134 * is detected. It lists out all the supported drive strength values for 5135 * reference in the error message. 5136 */ 5137 static void ksz_drive_strength_error(struct ksz_device *dev, 5138 const struct ksz_drive_strength *array, 5139 size_t array_size, int microamp) 5140 { 5141 char supported_values[100]; 5142 size_t remaining_size; 5143 int added_len; 5144 char *ptr; 5145 int i; 5146 5147 remaining_size = sizeof(supported_values); 5148 ptr = supported_values; 5149 5150 for (i = 0; i < array_size; i++) { 5151 added_len = snprintf(ptr, remaining_size, 5152 i == 0 ? "%d" : ", %d", array[i].microamp); 5153 5154 if (added_len >= remaining_size) 5155 break; 5156 5157 ptr += added_len; 5158 remaining_size -= added_len; 5159 } 5160 5161 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n", 5162 microamp, supported_values); 5163 } 5164 5165 /** 5166 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477 5167 * chip variants. 5168 * @dev: ksz device 5169 * @props: Array of drive strength properties to be applied 5170 * @num_props: Number of properties in the array 5171 * 5172 * This function configures the drive strength for various KSZ9477 chip variants 5173 * based on the provided properties. It handles chip-specific nuances and 5174 * ensures only valid drive strengths are written to the respective chip. 5175 * 5176 * Return: 0 on successful configuration, a negative error code on failure. 5177 */ 5178 static int ksz9477_drive_strength_write(struct ksz_device *dev, 5179 struct ksz_driver_strength_prop *props, 5180 int num_props) 5181 { 5182 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths); 5183 int i, ret, reg; 5184 u8 mask = 0; 5185 u8 val = 0; 5186 5187 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1) 5188 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 5189 props[KSZ_DRIVER_STRENGTH_IO].name); 5190 5191 if (dev->chip_id == KSZ8795_CHIP_ID || 5192 dev->chip_id == KSZ8794_CHIP_ID || 5193 dev->chip_id == KSZ8765_CHIP_ID) 5194 reg = KSZ8795_REG_SW_CTRL_20; 5195 else 5196 reg = KSZ9477_REG_SW_IO_STRENGTH; 5197 5198 for (i = 0; i < num_props; i++) { 5199 if (props[i].value == -1) 5200 continue; 5201 5202 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths, 5203 array_size, props[i].value); 5204 if (ret < 0) { 5205 ksz_drive_strength_error(dev, ksz9477_drive_strengths, 5206 array_size, props[i].value); 5207 return ret; 5208 } 5209 5210 mask |= SW_DRIVE_STRENGTH_M << props[i].offset; 5211 val |= ret << props[i].offset; 5212 } 5213 5214 return ksz_rmw8(dev, reg, mask, val); 5215 } 5216 5217 /** 5218 * ksz88x3_drive_strength_write() - Set the drive strength configuration for 5219 * KSZ8863 compatible chip variants. 5220 * @dev: ksz device 5221 * @props: Array of drive strength properties to be set 5222 * @num_props: Number of properties in the array 5223 * 5224 * This function applies the specified drive strength settings to KSZ88X3 chip 5225 * variants (KSZ8873, KSZ8863). 5226 * It ensures the configurations align with what the chip variant supports and 5227 * warns or errors out on unsupported settings. 5228 * 5229 * Return: 0 on success, error code otherwise 5230 */ 5231 static int ksz88x3_drive_strength_write(struct ksz_device *dev, 5232 struct ksz_driver_strength_prop *props, 5233 int num_props) 5234 { 5235 size_t array_size = ARRAY_SIZE(ksz88x3_drive_strengths); 5236 int microamp; 5237 int i, ret; 5238 5239 for (i = 0; i < num_props; i++) { 5240 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO) 5241 continue; 5242 5243 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 5244 props[i].name); 5245 } 5246 5247 microamp = props[KSZ_DRIVER_STRENGTH_IO].value; 5248 ret = ksz_drive_strength_to_reg(ksz88x3_drive_strengths, array_size, 5249 microamp); 5250 if (ret < 0) { 5251 ksz_drive_strength_error(dev, ksz88x3_drive_strengths, 5252 array_size, microamp); 5253 return ret; 5254 } 5255 5256 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12, 5257 KSZ8873_DRIVE_STRENGTH_16MA, ret); 5258 } 5259 5260 /** 5261 * ksz_parse_drive_strength() - Extract and apply drive strength configurations 5262 * from device tree properties. 5263 * @dev: ksz device 5264 * 5265 * This function reads the specified drive strength properties from the 5266 * device tree, validates against the supported chip variants, and sets 5267 * them accordingly. An error should be critical here, as the drive strength 5268 * settings are crucial for EMI compliance. 5269 * 5270 * Return: 0 on success, error code otherwise 5271 */ 5272 static int ksz_parse_drive_strength(struct ksz_device *dev) 5273 { 5274 struct ksz_driver_strength_prop of_props[] = { 5275 [KSZ_DRIVER_STRENGTH_HI] = { 5276 .name = "microchip,hi-drive-strength-microamp", 5277 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S, 5278 .value = -1, 5279 }, 5280 [KSZ_DRIVER_STRENGTH_LO] = { 5281 .name = "microchip,lo-drive-strength-microamp", 5282 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S, 5283 .value = -1, 5284 }, 5285 [KSZ_DRIVER_STRENGTH_IO] = { 5286 .name = "microchip,io-drive-strength-microamp", 5287 .offset = 0, /* don't care */ 5288 .value = -1, 5289 }, 5290 }; 5291 struct device_node *np = dev->dev->of_node; 5292 bool have_any_prop = false; 5293 int i, ret; 5294 5295 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 5296 ret = of_property_read_u32(np, of_props[i].name, 5297 &of_props[i].value); 5298 if (ret && ret != -EINVAL) 5299 dev_warn(dev->dev, "Failed to read %s\n", 5300 of_props[i].name); 5301 if (ret) 5302 continue; 5303 5304 have_any_prop = true; 5305 } 5306 5307 if (!have_any_prop) 5308 return 0; 5309 5310 switch (dev->chip_id) { 5311 case KSZ88X3_CHIP_ID: 5312 return ksz88x3_drive_strength_write(dev, of_props, 5313 ARRAY_SIZE(of_props)); 5314 case KSZ8795_CHIP_ID: 5315 case KSZ8794_CHIP_ID: 5316 case KSZ8765_CHIP_ID: 5317 case KSZ8563_CHIP_ID: 5318 case KSZ8567_CHIP_ID: 5319 case KSZ9477_CHIP_ID: 5320 case KSZ9563_CHIP_ID: 5321 case KSZ9567_CHIP_ID: 5322 case KSZ9893_CHIP_ID: 5323 case KSZ9896_CHIP_ID: 5324 case KSZ9897_CHIP_ID: 5325 case LAN9646_CHIP_ID: 5326 return ksz9477_drive_strength_write(dev, of_props, 5327 ARRAY_SIZE(of_props)); 5328 default: 5329 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 5330 if (of_props[i].value == -1) 5331 continue; 5332 5333 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 5334 of_props[i].name); 5335 } 5336 } 5337 5338 return 0; 5339 } 5340 5341 int ksz_switch_register(struct ksz_device *dev) 5342 { 5343 const struct ksz_chip_data *info; 5344 struct device_node *ports; 5345 phy_interface_t interface; 5346 unsigned int port_num; 5347 int ret; 5348 int i; 5349 5350 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 5351 GPIOD_OUT_LOW); 5352 if (IS_ERR(dev->reset_gpio)) 5353 return PTR_ERR(dev->reset_gpio); 5354 5355 if (dev->reset_gpio) { 5356 gpiod_set_value_cansleep(dev->reset_gpio, 1); 5357 usleep_range(10000, 12000); 5358 gpiod_set_value_cansleep(dev->reset_gpio, 0); 5359 msleep(100); 5360 } 5361 5362 mutex_init(&dev->dev_mutex); 5363 mutex_init(&dev->regmap_mutex); 5364 mutex_init(&dev->alu_mutex); 5365 mutex_init(&dev->vlan_mutex); 5366 5367 ret = ksz_switch_detect(dev); 5368 if (ret) 5369 return ret; 5370 5371 info = ksz_lookup_info(dev->chip_id); 5372 if (!info) 5373 return -ENODEV; 5374 5375 /* Update the compatible info with the probed one */ 5376 dev->info = info; 5377 5378 dev_info(dev->dev, "found switch: %s, rev %i\n", 5379 dev->info->dev_name, dev->chip_rev); 5380 5381 ret = ksz_check_device_id(dev); 5382 if (ret) 5383 return ret; 5384 5385 dev->dev_ops = dev->info->ops; 5386 5387 ret = dev->dev_ops->init(dev); 5388 if (ret) 5389 return ret; 5390 5391 dev->ports = devm_kzalloc(dev->dev, 5392 dev->info->port_cnt * sizeof(struct ksz_port), 5393 GFP_KERNEL); 5394 if (!dev->ports) 5395 return -ENOMEM; 5396 5397 for (i = 0; i < dev->info->port_cnt; i++) { 5398 spin_lock_init(&dev->ports[i].mib.stats64_lock); 5399 mutex_init(&dev->ports[i].mib.cnt_mutex); 5400 dev->ports[i].mib.counters = 5401 devm_kzalloc(dev->dev, 5402 sizeof(u64) * (dev->info->mib_cnt + 1), 5403 GFP_KERNEL); 5404 if (!dev->ports[i].mib.counters) 5405 return -ENOMEM; 5406 5407 dev->ports[i].ksz_dev = dev; 5408 dev->ports[i].num = i; 5409 } 5410 5411 /* set the real number of ports */ 5412 dev->ds->num_ports = dev->info->port_cnt; 5413 5414 /* set the phylink ops */ 5415 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops; 5416 5417 /* Host port interface will be self detected, or specifically set in 5418 * device tree. 5419 */ 5420 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 5421 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 5422 if (dev->dev->of_node) { 5423 ret = of_get_phy_mode(dev->dev->of_node, &interface); 5424 if (ret == 0) 5425 dev->compat_interface = interface; 5426 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 5427 if (!ports) 5428 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 5429 if (ports) { 5430 for_each_available_child_of_node_scoped(ports, port) { 5431 if (of_property_read_u32(port, "reg", 5432 &port_num)) 5433 continue; 5434 if (!(dev->port_mask & BIT(port_num))) { 5435 of_node_put(ports); 5436 return -EINVAL; 5437 } 5438 of_get_phy_mode(port, 5439 &dev->ports[port_num].interface); 5440 5441 ksz_parse_rgmii_delay(dev, port_num, port); 5442 dev->ports[port_num].fiber = 5443 of_property_read_bool(port, 5444 "micrel,fiber-mode"); 5445 } 5446 of_node_put(ports); 5447 } 5448 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 5449 "microchip,synclko-125"); 5450 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 5451 "microchip,synclko-disable"); 5452 if (dev->synclko_125 && dev->synclko_disable) { 5453 dev_err(dev->dev, "inconsistent synclko settings\n"); 5454 return -EINVAL; 5455 } 5456 5457 dev->wakeup_source = of_property_read_bool(dev->dev->of_node, 5458 "wakeup-source"); 5459 dev->pme_active_high = of_property_read_bool(dev->dev->of_node, 5460 "microchip,pme-active-high"); 5461 } 5462 5463 ret = dsa_register_switch(dev->ds); 5464 if (ret) { 5465 dev->dev_ops->exit(dev); 5466 return ret; 5467 } 5468 5469 /* Read MIB counters every 30 seconds to avoid overflow. */ 5470 dev->mib_read_interval = msecs_to_jiffies(5000); 5471 5472 /* Start the MIB timer. */ 5473 schedule_delayed_work(&dev->mib_read, 0); 5474 5475 return ret; 5476 } 5477 EXPORT_SYMBOL(ksz_switch_register); 5478 5479 void ksz_switch_remove(struct ksz_device *dev) 5480 { 5481 /* timer started */ 5482 if (dev->mib_read_interval) { 5483 dev->mib_read_interval = 0; 5484 cancel_delayed_work_sync(&dev->mib_read); 5485 } 5486 5487 dev->dev_ops->exit(dev); 5488 dsa_unregister_switch(dev->ds); 5489 5490 if (dev->reset_gpio) 5491 gpiod_set_value_cansleep(dev->reset_gpio, 1); 5492 5493 } 5494 EXPORT_SYMBOL(ksz_switch_remove); 5495 5496 #ifdef CONFIG_PM_SLEEP 5497 int ksz_switch_suspend(struct device *dev) 5498 { 5499 struct ksz_device *priv = dev_get_drvdata(dev); 5500 5501 return dsa_switch_suspend(priv->ds); 5502 } 5503 EXPORT_SYMBOL(ksz_switch_suspend); 5504 5505 int ksz_switch_resume(struct device *dev) 5506 { 5507 struct ksz_device *priv = dev_get_drvdata(dev); 5508 5509 return dsa_switch_resume(priv->ds); 5510 } 5511 EXPORT_SYMBOL(ksz_switch_resume); 5512 #endif 5513 5514 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 5515 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 5516 MODULE_LICENSE("GPL"); 5517