1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/export.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/platform_data/microchip-ksz.h> 14 #include <linux/phy.h> 15 #include <linux/etherdevice.h> 16 #include <linux/if_bridge.h> 17 #include <linux/of_device.h> 18 #include <linux/of_net.h> 19 #include <linux/micrel_phy.h> 20 #include <net/dsa.h> 21 #include <net/switchdev.h> 22 23 #include "ksz_common.h" 24 #include "ksz8.h" 25 #include "ksz9477.h" 26 #include "lan937x.h" 27 28 #define MIB_COUNTER_NUM 0x20 29 30 struct ksz_stats_raw { 31 u64 rx_hi; 32 u64 rx_undersize; 33 u64 rx_fragments; 34 u64 rx_oversize; 35 u64 rx_jabbers; 36 u64 rx_symbol_err; 37 u64 rx_crc_err; 38 u64 rx_align_err; 39 u64 rx_mac_ctrl; 40 u64 rx_pause; 41 u64 rx_bcast; 42 u64 rx_mcast; 43 u64 rx_ucast; 44 u64 rx_64_or_less; 45 u64 rx_65_127; 46 u64 rx_128_255; 47 u64 rx_256_511; 48 u64 rx_512_1023; 49 u64 rx_1024_1522; 50 u64 rx_1523_2000; 51 u64 rx_2001; 52 u64 tx_hi; 53 u64 tx_late_col; 54 u64 tx_pause; 55 u64 tx_bcast; 56 u64 tx_mcast; 57 u64 tx_ucast; 58 u64 tx_deferred; 59 u64 tx_total_col; 60 u64 tx_exc_col; 61 u64 tx_single_col; 62 u64 tx_mult_col; 63 u64 rx_total; 64 u64 tx_total; 65 u64 rx_discards; 66 u64 tx_discards; 67 }; 68 69 static const struct ksz_mib_names ksz88xx_mib_names[] = { 70 { 0x00, "rx" }, 71 { 0x01, "rx_hi" }, 72 { 0x02, "rx_undersize" }, 73 { 0x03, "rx_fragments" }, 74 { 0x04, "rx_oversize" }, 75 { 0x05, "rx_jabbers" }, 76 { 0x06, "rx_symbol_err" }, 77 { 0x07, "rx_crc_err" }, 78 { 0x08, "rx_align_err" }, 79 { 0x09, "rx_mac_ctrl" }, 80 { 0x0a, "rx_pause" }, 81 { 0x0b, "rx_bcast" }, 82 { 0x0c, "rx_mcast" }, 83 { 0x0d, "rx_ucast" }, 84 { 0x0e, "rx_64_or_less" }, 85 { 0x0f, "rx_65_127" }, 86 { 0x10, "rx_128_255" }, 87 { 0x11, "rx_256_511" }, 88 { 0x12, "rx_512_1023" }, 89 { 0x13, "rx_1024_1522" }, 90 { 0x14, "tx" }, 91 { 0x15, "tx_hi" }, 92 { 0x16, "tx_late_col" }, 93 { 0x17, "tx_pause" }, 94 { 0x18, "tx_bcast" }, 95 { 0x19, "tx_mcast" }, 96 { 0x1a, "tx_ucast" }, 97 { 0x1b, "tx_deferred" }, 98 { 0x1c, "tx_total_col" }, 99 { 0x1d, "tx_exc_col" }, 100 { 0x1e, "tx_single_col" }, 101 { 0x1f, "tx_mult_col" }, 102 { 0x100, "rx_discards" }, 103 { 0x101, "tx_discards" }, 104 }; 105 106 static const struct ksz_mib_names ksz9477_mib_names[] = { 107 { 0x00, "rx_hi" }, 108 { 0x01, "rx_undersize" }, 109 { 0x02, "rx_fragments" }, 110 { 0x03, "rx_oversize" }, 111 { 0x04, "rx_jabbers" }, 112 { 0x05, "rx_symbol_err" }, 113 { 0x06, "rx_crc_err" }, 114 { 0x07, "rx_align_err" }, 115 { 0x08, "rx_mac_ctrl" }, 116 { 0x09, "rx_pause" }, 117 { 0x0A, "rx_bcast" }, 118 { 0x0B, "rx_mcast" }, 119 { 0x0C, "rx_ucast" }, 120 { 0x0D, "rx_64_or_less" }, 121 { 0x0E, "rx_65_127" }, 122 { 0x0F, "rx_128_255" }, 123 { 0x10, "rx_256_511" }, 124 { 0x11, "rx_512_1023" }, 125 { 0x12, "rx_1024_1522" }, 126 { 0x13, "rx_1523_2000" }, 127 { 0x14, "rx_2001" }, 128 { 0x15, "tx_hi" }, 129 { 0x16, "tx_late_col" }, 130 { 0x17, "tx_pause" }, 131 { 0x18, "tx_bcast" }, 132 { 0x19, "tx_mcast" }, 133 { 0x1A, "tx_ucast" }, 134 { 0x1B, "tx_deferred" }, 135 { 0x1C, "tx_total_col" }, 136 { 0x1D, "tx_exc_col" }, 137 { 0x1E, "tx_single_col" }, 138 { 0x1F, "tx_mult_col" }, 139 { 0x80, "rx_total" }, 140 { 0x81, "tx_total" }, 141 { 0x82, "rx_discards" }, 142 { 0x83, "tx_discards" }, 143 }; 144 145 static const struct ksz_dev_ops ksz8_dev_ops = { 146 .setup = ksz8_setup, 147 .get_port_addr = ksz8_get_port_addr, 148 .cfg_port_member = ksz8_cfg_port_member, 149 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 150 .port_setup = ksz8_port_setup, 151 .r_phy = ksz8_r_phy, 152 .w_phy = ksz8_w_phy, 153 .r_mib_cnt = ksz8_r_mib_cnt, 154 .r_mib_pkt = ksz8_r_mib_pkt, 155 .freeze_mib = ksz8_freeze_mib, 156 .port_init_cnt = ksz8_port_init_cnt, 157 .fdb_dump = ksz8_fdb_dump, 158 .mdb_add = ksz8_mdb_add, 159 .mdb_del = ksz8_mdb_del, 160 .vlan_filtering = ksz8_port_vlan_filtering, 161 .vlan_add = ksz8_port_vlan_add, 162 .vlan_del = ksz8_port_vlan_del, 163 .mirror_add = ksz8_port_mirror_add, 164 .mirror_del = ksz8_port_mirror_del, 165 .get_caps = ksz8_get_caps, 166 .config_cpu_port = ksz8_config_cpu_port, 167 .enable_stp_addr = ksz8_enable_stp_addr, 168 .reset = ksz8_reset_switch, 169 .init = ksz8_switch_init, 170 .exit = ksz8_switch_exit, 171 }; 172 173 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 174 unsigned int mode, 175 phy_interface_t interface, 176 struct phy_device *phydev, int speed, 177 int duplex, bool tx_pause, 178 bool rx_pause); 179 180 static const struct ksz_dev_ops ksz9477_dev_ops = { 181 .setup = ksz9477_setup, 182 .get_port_addr = ksz9477_get_port_addr, 183 .cfg_port_member = ksz9477_cfg_port_member, 184 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 185 .port_setup = ksz9477_port_setup, 186 .set_ageing_time = ksz9477_set_ageing_time, 187 .r_phy = ksz9477_r_phy, 188 .w_phy = ksz9477_w_phy, 189 .r_mib_cnt = ksz9477_r_mib_cnt, 190 .r_mib_pkt = ksz9477_r_mib_pkt, 191 .r_mib_stat64 = ksz_r_mib_stats64, 192 .freeze_mib = ksz9477_freeze_mib, 193 .port_init_cnt = ksz9477_port_init_cnt, 194 .vlan_filtering = ksz9477_port_vlan_filtering, 195 .vlan_add = ksz9477_port_vlan_add, 196 .vlan_del = ksz9477_port_vlan_del, 197 .mirror_add = ksz9477_port_mirror_add, 198 .mirror_del = ksz9477_port_mirror_del, 199 .get_caps = ksz9477_get_caps, 200 .fdb_dump = ksz9477_fdb_dump, 201 .fdb_add = ksz9477_fdb_add, 202 .fdb_del = ksz9477_fdb_del, 203 .mdb_add = ksz9477_mdb_add, 204 .mdb_del = ksz9477_mdb_del, 205 .change_mtu = ksz9477_change_mtu, 206 .max_mtu = ksz9477_max_mtu, 207 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 208 .config_cpu_port = ksz9477_config_cpu_port, 209 .enable_stp_addr = ksz9477_enable_stp_addr, 210 .reset = ksz9477_reset_switch, 211 .init = ksz9477_switch_init, 212 .exit = ksz9477_switch_exit, 213 }; 214 215 static const struct ksz_dev_ops lan937x_dev_ops = { 216 .setup = lan937x_setup, 217 .teardown = lan937x_teardown, 218 .get_port_addr = ksz9477_get_port_addr, 219 .cfg_port_member = ksz9477_cfg_port_member, 220 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 221 .port_setup = lan937x_port_setup, 222 .set_ageing_time = lan937x_set_ageing_time, 223 .r_phy = lan937x_r_phy, 224 .w_phy = lan937x_w_phy, 225 .r_mib_cnt = ksz9477_r_mib_cnt, 226 .r_mib_pkt = ksz9477_r_mib_pkt, 227 .r_mib_stat64 = ksz_r_mib_stats64, 228 .freeze_mib = ksz9477_freeze_mib, 229 .port_init_cnt = ksz9477_port_init_cnt, 230 .vlan_filtering = ksz9477_port_vlan_filtering, 231 .vlan_add = ksz9477_port_vlan_add, 232 .vlan_del = ksz9477_port_vlan_del, 233 .mirror_add = ksz9477_port_mirror_add, 234 .mirror_del = ksz9477_port_mirror_del, 235 .get_caps = lan937x_phylink_get_caps, 236 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 237 .fdb_dump = ksz9477_fdb_dump, 238 .fdb_add = ksz9477_fdb_add, 239 .fdb_del = ksz9477_fdb_del, 240 .mdb_add = ksz9477_mdb_add, 241 .mdb_del = ksz9477_mdb_del, 242 .change_mtu = lan937x_change_mtu, 243 .max_mtu = ksz9477_max_mtu, 244 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 245 .config_cpu_port = lan937x_config_cpu_port, 246 .enable_stp_addr = ksz9477_enable_stp_addr, 247 .reset = lan937x_reset_switch, 248 .init = lan937x_switch_init, 249 .exit = lan937x_switch_exit, 250 }; 251 252 static const u16 ksz8795_regs[] = { 253 [REG_IND_CTRL_0] = 0x6E, 254 [REG_IND_DATA_8] = 0x70, 255 [REG_IND_DATA_CHECK] = 0x72, 256 [REG_IND_DATA_HI] = 0x71, 257 [REG_IND_DATA_LO] = 0x75, 258 [REG_IND_MIB_CHECK] = 0x74, 259 [REG_IND_BYTE] = 0xA0, 260 [P_FORCE_CTRL] = 0x0C, 261 [P_LINK_STATUS] = 0x0E, 262 [P_LOCAL_CTRL] = 0x07, 263 [P_NEG_RESTART_CTRL] = 0x0D, 264 [P_REMOTE_STATUS] = 0x08, 265 [P_SPEED_STATUS] = 0x09, 266 [S_TAIL_TAG_CTRL] = 0x0C, 267 [P_STP_CTRL] = 0x02, 268 [S_START_CTRL] = 0x01, 269 [S_BROADCAST_CTRL] = 0x06, 270 [S_MULTICAST_CTRL] = 0x04, 271 [P_XMII_CTRL_0] = 0x06, 272 [P_XMII_CTRL_1] = 0x56, 273 }; 274 275 static const u32 ksz8795_masks[] = { 276 [PORT_802_1P_REMAPPING] = BIT(7), 277 [SW_TAIL_TAG_ENABLE] = BIT(1), 278 [MIB_COUNTER_OVERFLOW] = BIT(6), 279 [MIB_COUNTER_VALID] = BIT(5), 280 [VLAN_TABLE_FID] = GENMASK(6, 0), 281 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 282 [VLAN_TABLE_VALID] = BIT(12), 283 [STATIC_MAC_TABLE_VALID] = BIT(21), 284 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 285 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 286 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26), 287 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20), 288 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 289 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8), 290 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 291 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 292 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20), 293 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 294 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 295 [P_MII_TX_FLOW_CTRL] = BIT(5), 296 [P_MII_RX_FLOW_CTRL] = BIT(5), 297 }; 298 299 static const u8 ksz8795_xmii_ctrl0[] = { 300 [P_MII_100MBIT] = 0, 301 [P_MII_10MBIT] = 1, 302 [P_MII_FULL_DUPLEX] = 0, 303 [P_MII_HALF_DUPLEX] = 1, 304 }; 305 306 static const u8 ksz8795_xmii_ctrl1[] = { 307 [P_RGMII_SEL] = 3, 308 [P_GMII_SEL] = 2, 309 [P_RMII_SEL] = 1, 310 [P_MII_SEL] = 0, 311 [P_GMII_1GBIT] = 1, 312 [P_GMII_NOT_1GBIT] = 0, 313 }; 314 315 static const u8 ksz8795_shifts[] = { 316 [VLAN_TABLE_MEMBERSHIP_S] = 7, 317 [VLAN_TABLE] = 16, 318 [STATIC_MAC_FWD_PORTS] = 16, 319 [STATIC_MAC_FID] = 24, 320 [DYNAMIC_MAC_ENTRIES_H] = 3, 321 [DYNAMIC_MAC_ENTRIES] = 29, 322 [DYNAMIC_MAC_FID] = 16, 323 [DYNAMIC_MAC_TIMESTAMP] = 27, 324 [DYNAMIC_MAC_SRC_PORT] = 24, 325 }; 326 327 static const u16 ksz8863_regs[] = { 328 [REG_IND_CTRL_0] = 0x79, 329 [REG_IND_DATA_8] = 0x7B, 330 [REG_IND_DATA_CHECK] = 0x7B, 331 [REG_IND_DATA_HI] = 0x7C, 332 [REG_IND_DATA_LO] = 0x80, 333 [REG_IND_MIB_CHECK] = 0x80, 334 [P_FORCE_CTRL] = 0x0C, 335 [P_LINK_STATUS] = 0x0E, 336 [P_LOCAL_CTRL] = 0x0C, 337 [P_NEG_RESTART_CTRL] = 0x0D, 338 [P_REMOTE_STATUS] = 0x0E, 339 [P_SPEED_STATUS] = 0x0F, 340 [S_TAIL_TAG_CTRL] = 0x03, 341 [P_STP_CTRL] = 0x02, 342 [S_START_CTRL] = 0x01, 343 [S_BROADCAST_CTRL] = 0x06, 344 [S_MULTICAST_CTRL] = 0x04, 345 }; 346 347 static const u32 ksz8863_masks[] = { 348 [PORT_802_1P_REMAPPING] = BIT(3), 349 [SW_TAIL_TAG_ENABLE] = BIT(6), 350 [MIB_COUNTER_OVERFLOW] = BIT(7), 351 [MIB_COUNTER_VALID] = BIT(6), 352 [VLAN_TABLE_FID] = GENMASK(15, 12), 353 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 354 [VLAN_TABLE_VALID] = BIT(19), 355 [STATIC_MAC_TABLE_VALID] = BIT(19), 356 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 357 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26), 358 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 359 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 360 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0), 361 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 362 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 363 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28), 364 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 365 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 366 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 367 }; 368 369 static u8 ksz8863_shifts[] = { 370 [VLAN_TABLE_MEMBERSHIP_S] = 16, 371 [STATIC_MAC_FWD_PORTS] = 16, 372 [STATIC_MAC_FID] = 22, 373 [DYNAMIC_MAC_ENTRIES_H] = 3, 374 [DYNAMIC_MAC_ENTRIES] = 24, 375 [DYNAMIC_MAC_FID] = 16, 376 [DYNAMIC_MAC_TIMESTAMP] = 24, 377 [DYNAMIC_MAC_SRC_PORT] = 20, 378 }; 379 380 static const u16 ksz9477_regs[] = { 381 [P_STP_CTRL] = 0x0B04, 382 [S_START_CTRL] = 0x0300, 383 [S_BROADCAST_CTRL] = 0x0332, 384 [S_MULTICAST_CTRL] = 0x0331, 385 [P_XMII_CTRL_0] = 0x0300, 386 [P_XMII_CTRL_1] = 0x0301, 387 }; 388 389 static const u32 ksz9477_masks[] = { 390 [ALU_STAT_WRITE] = 0, 391 [ALU_STAT_READ] = 1, 392 [P_MII_TX_FLOW_CTRL] = BIT(5), 393 [P_MII_RX_FLOW_CTRL] = BIT(3), 394 }; 395 396 static const u8 ksz9477_shifts[] = { 397 [ALU_STAT_INDEX] = 16, 398 }; 399 400 static const u8 ksz9477_xmii_ctrl0[] = { 401 [P_MII_100MBIT] = 1, 402 [P_MII_10MBIT] = 0, 403 [P_MII_FULL_DUPLEX] = 1, 404 [P_MII_HALF_DUPLEX] = 0, 405 }; 406 407 static const u8 ksz9477_xmii_ctrl1[] = { 408 [P_RGMII_SEL] = 0, 409 [P_RMII_SEL] = 1, 410 [P_GMII_SEL] = 2, 411 [P_MII_SEL] = 3, 412 [P_GMII_1GBIT] = 0, 413 [P_GMII_NOT_1GBIT] = 1, 414 }; 415 416 static const u32 lan937x_masks[] = { 417 [ALU_STAT_WRITE] = 1, 418 [ALU_STAT_READ] = 2, 419 [P_MII_TX_FLOW_CTRL] = BIT(5), 420 [P_MII_RX_FLOW_CTRL] = BIT(3), 421 }; 422 423 static const u8 lan937x_shifts[] = { 424 [ALU_STAT_INDEX] = 8, 425 }; 426 427 static const struct regmap_range ksz8563_valid_regs[] = { 428 regmap_reg_range(0x0000, 0x0003), 429 regmap_reg_range(0x0006, 0x0006), 430 regmap_reg_range(0x000f, 0x001f), 431 regmap_reg_range(0x0100, 0x0100), 432 regmap_reg_range(0x0104, 0x0107), 433 regmap_reg_range(0x010d, 0x010d), 434 regmap_reg_range(0x0110, 0x0113), 435 regmap_reg_range(0x0120, 0x012b), 436 regmap_reg_range(0x0201, 0x0201), 437 regmap_reg_range(0x0210, 0x0213), 438 regmap_reg_range(0x0300, 0x0300), 439 regmap_reg_range(0x0302, 0x031b), 440 regmap_reg_range(0x0320, 0x032b), 441 regmap_reg_range(0x0330, 0x0336), 442 regmap_reg_range(0x0338, 0x033e), 443 regmap_reg_range(0x0340, 0x035f), 444 regmap_reg_range(0x0370, 0x0370), 445 regmap_reg_range(0x0378, 0x0378), 446 regmap_reg_range(0x037c, 0x037d), 447 regmap_reg_range(0x0390, 0x0393), 448 regmap_reg_range(0x0400, 0x040e), 449 regmap_reg_range(0x0410, 0x042f), 450 regmap_reg_range(0x0500, 0x0519), 451 regmap_reg_range(0x0520, 0x054b), 452 regmap_reg_range(0x0550, 0x05b3), 453 454 /* port 1 */ 455 regmap_reg_range(0x1000, 0x1001), 456 regmap_reg_range(0x1004, 0x100b), 457 regmap_reg_range(0x1013, 0x1013), 458 regmap_reg_range(0x1017, 0x1017), 459 regmap_reg_range(0x101b, 0x101b), 460 regmap_reg_range(0x101f, 0x1021), 461 regmap_reg_range(0x1030, 0x1030), 462 regmap_reg_range(0x1100, 0x1111), 463 regmap_reg_range(0x111a, 0x111d), 464 regmap_reg_range(0x1122, 0x1127), 465 regmap_reg_range(0x112a, 0x112b), 466 regmap_reg_range(0x1136, 0x1139), 467 regmap_reg_range(0x113e, 0x113f), 468 regmap_reg_range(0x1400, 0x1401), 469 regmap_reg_range(0x1403, 0x1403), 470 regmap_reg_range(0x1410, 0x1417), 471 regmap_reg_range(0x1420, 0x1423), 472 regmap_reg_range(0x1500, 0x1507), 473 regmap_reg_range(0x1600, 0x1612), 474 regmap_reg_range(0x1800, 0x180f), 475 regmap_reg_range(0x1900, 0x1907), 476 regmap_reg_range(0x1914, 0x191b), 477 regmap_reg_range(0x1a00, 0x1a03), 478 regmap_reg_range(0x1a04, 0x1a08), 479 regmap_reg_range(0x1b00, 0x1b01), 480 regmap_reg_range(0x1b04, 0x1b04), 481 regmap_reg_range(0x1c00, 0x1c05), 482 regmap_reg_range(0x1c08, 0x1c1b), 483 484 /* port 2 */ 485 regmap_reg_range(0x2000, 0x2001), 486 regmap_reg_range(0x2004, 0x200b), 487 regmap_reg_range(0x2013, 0x2013), 488 regmap_reg_range(0x2017, 0x2017), 489 regmap_reg_range(0x201b, 0x201b), 490 regmap_reg_range(0x201f, 0x2021), 491 regmap_reg_range(0x2030, 0x2030), 492 regmap_reg_range(0x2100, 0x2111), 493 regmap_reg_range(0x211a, 0x211d), 494 regmap_reg_range(0x2122, 0x2127), 495 regmap_reg_range(0x212a, 0x212b), 496 regmap_reg_range(0x2136, 0x2139), 497 regmap_reg_range(0x213e, 0x213f), 498 regmap_reg_range(0x2400, 0x2401), 499 regmap_reg_range(0x2403, 0x2403), 500 regmap_reg_range(0x2410, 0x2417), 501 regmap_reg_range(0x2420, 0x2423), 502 regmap_reg_range(0x2500, 0x2507), 503 regmap_reg_range(0x2600, 0x2612), 504 regmap_reg_range(0x2800, 0x280f), 505 regmap_reg_range(0x2900, 0x2907), 506 regmap_reg_range(0x2914, 0x291b), 507 regmap_reg_range(0x2a00, 0x2a03), 508 regmap_reg_range(0x2a04, 0x2a08), 509 regmap_reg_range(0x2b00, 0x2b01), 510 regmap_reg_range(0x2b04, 0x2b04), 511 regmap_reg_range(0x2c00, 0x2c05), 512 regmap_reg_range(0x2c08, 0x2c1b), 513 514 /* port 3 */ 515 regmap_reg_range(0x3000, 0x3001), 516 regmap_reg_range(0x3004, 0x300b), 517 regmap_reg_range(0x3013, 0x3013), 518 regmap_reg_range(0x3017, 0x3017), 519 regmap_reg_range(0x301b, 0x301b), 520 regmap_reg_range(0x301f, 0x3021), 521 regmap_reg_range(0x3030, 0x3030), 522 regmap_reg_range(0x3300, 0x3301), 523 regmap_reg_range(0x3303, 0x3303), 524 regmap_reg_range(0x3400, 0x3401), 525 regmap_reg_range(0x3403, 0x3403), 526 regmap_reg_range(0x3410, 0x3417), 527 regmap_reg_range(0x3420, 0x3423), 528 regmap_reg_range(0x3500, 0x3507), 529 regmap_reg_range(0x3600, 0x3612), 530 regmap_reg_range(0x3800, 0x380f), 531 regmap_reg_range(0x3900, 0x3907), 532 regmap_reg_range(0x3914, 0x391b), 533 regmap_reg_range(0x3a00, 0x3a03), 534 regmap_reg_range(0x3a04, 0x3a08), 535 regmap_reg_range(0x3b00, 0x3b01), 536 regmap_reg_range(0x3b04, 0x3b04), 537 regmap_reg_range(0x3c00, 0x3c05), 538 regmap_reg_range(0x3c08, 0x3c1b), 539 }; 540 541 static const struct regmap_access_table ksz8563_register_set = { 542 .yes_ranges = ksz8563_valid_regs, 543 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 544 }; 545 546 static const struct regmap_range ksz9477_valid_regs[] = { 547 regmap_reg_range(0x0000, 0x0003), 548 regmap_reg_range(0x0006, 0x0006), 549 regmap_reg_range(0x0010, 0x001f), 550 regmap_reg_range(0x0100, 0x0100), 551 regmap_reg_range(0x0103, 0x0107), 552 regmap_reg_range(0x010d, 0x010d), 553 regmap_reg_range(0x0110, 0x0113), 554 regmap_reg_range(0x0120, 0x012b), 555 regmap_reg_range(0x0201, 0x0201), 556 regmap_reg_range(0x0210, 0x0213), 557 regmap_reg_range(0x0300, 0x0300), 558 regmap_reg_range(0x0302, 0x031b), 559 regmap_reg_range(0x0320, 0x032b), 560 regmap_reg_range(0x0330, 0x0336), 561 regmap_reg_range(0x0338, 0x033b), 562 regmap_reg_range(0x033e, 0x033e), 563 regmap_reg_range(0x0340, 0x035f), 564 regmap_reg_range(0x0370, 0x0370), 565 regmap_reg_range(0x0378, 0x0378), 566 regmap_reg_range(0x037c, 0x037d), 567 regmap_reg_range(0x0390, 0x0393), 568 regmap_reg_range(0x0400, 0x040e), 569 regmap_reg_range(0x0410, 0x042f), 570 regmap_reg_range(0x0444, 0x044b), 571 regmap_reg_range(0x0450, 0x046f), 572 regmap_reg_range(0x0500, 0x0519), 573 regmap_reg_range(0x0520, 0x054b), 574 regmap_reg_range(0x0550, 0x05b3), 575 regmap_reg_range(0x0604, 0x060b), 576 regmap_reg_range(0x0610, 0x0612), 577 regmap_reg_range(0x0614, 0x062c), 578 regmap_reg_range(0x0640, 0x0645), 579 regmap_reg_range(0x0648, 0x064d), 580 581 /* port 1 */ 582 regmap_reg_range(0x1000, 0x1001), 583 regmap_reg_range(0x1013, 0x1013), 584 regmap_reg_range(0x1017, 0x1017), 585 regmap_reg_range(0x101b, 0x101b), 586 regmap_reg_range(0x101f, 0x1020), 587 regmap_reg_range(0x1030, 0x1030), 588 regmap_reg_range(0x1100, 0x1115), 589 regmap_reg_range(0x111a, 0x111f), 590 regmap_reg_range(0x1122, 0x1127), 591 regmap_reg_range(0x112a, 0x112b), 592 regmap_reg_range(0x1136, 0x1139), 593 regmap_reg_range(0x113e, 0x113f), 594 regmap_reg_range(0x1400, 0x1401), 595 regmap_reg_range(0x1403, 0x1403), 596 regmap_reg_range(0x1410, 0x1417), 597 regmap_reg_range(0x1420, 0x1423), 598 regmap_reg_range(0x1500, 0x1507), 599 regmap_reg_range(0x1600, 0x1613), 600 regmap_reg_range(0x1800, 0x180f), 601 regmap_reg_range(0x1820, 0x1827), 602 regmap_reg_range(0x1830, 0x1837), 603 regmap_reg_range(0x1840, 0x184b), 604 regmap_reg_range(0x1900, 0x1907), 605 regmap_reg_range(0x1914, 0x191b), 606 regmap_reg_range(0x1920, 0x1920), 607 regmap_reg_range(0x1923, 0x1927), 608 regmap_reg_range(0x1a00, 0x1a03), 609 regmap_reg_range(0x1a04, 0x1a07), 610 regmap_reg_range(0x1b00, 0x1b01), 611 regmap_reg_range(0x1b04, 0x1b04), 612 regmap_reg_range(0x1c00, 0x1c05), 613 regmap_reg_range(0x1c08, 0x1c1b), 614 615 /* port 2 */ 616 regmap_reg_range(0x2000, 0x2001), 617 regmap_reg_range(0x2013, 0x2013), 618 regmap_reg_range(0x2017, 0x2017), 619 regmap_reg_range(0x201b, 0x201b), 620 regmap_reg_range(0x201f, 0x2020), 621 regmap_reg_range(0x2030, 0x2030), 622 regmap_reg_range(0x2100, 0x2115), 623 regmap_reg_range(0x211a, 0x211f), 624 regmap_reg_range(0x2122, 0x2127), 625 regmap_reg_range(0x212a, 0x212b), 626 regmap_reg_range(0x2136, 0x2139), 627 regmap_reg_range(0x213e, 0x213f), 628 regmap_reg_range(0x2400, 0x2401), 629 regmap_reg_range(0x2403, 0x2403), 630 regmap_reg_range(0x2410, 0x2417), 631 regmap_reg_range(0x2420, 0x2423), 632 regmap_reg_range(0x2500, 0x2507), 633 regmap_reg_range(0x2600, 0x2613), 634 regmap_reg_range(0x2800, 0x280f), 635 regmap_reg_range(0x2820, 0x2827), 636 regmap_reg_range(0x2830, 0x2837), 637 regmap_reg_range(0x2840, 0x284b), 638 regmap_reg_range(0x2900, 0x2907), 639 regmap_reg_range(0x2914, 0x291b), 640 regmap_reg_range(0x2920, 0x2920), 641 regmap_reg_range(0x2923, 0x2927), 642 regmap_reg_range(0x2a00, 0x2a03), 643 regmap_reg_range(0x2a04, 0x2a07), 644 regmap_reg_range(0x2b00, 0x2b01), 645 regmap_reg_range(0x2b04, 0x2b04), 646 regmap_reg_range(0x2c00, 0x2c05), 647 regmap_reg_range(0x2c08, 0x2c1b), 648 649 /* port 3 */ 650 regmap_reg_range(0x3000, 0x3001), 651 regmap_reg_range(0x3013, 0x3013), 652 regmap_reg_range(0x3017, 0x3017), 653 regmap_reg_range(0x301b, 0x301b), 654 regmap_reg_range(0x301f, 0x3020), 655 regmap_reg_range(0x3030, 0x3030), 656 regmap_reg_range(0x3100, 0x3115), 657 regmap_reg_range(0x311a, 0x311f), 658 regmap_reg_range(0x3122, 0x3127), 659 regmap_reg_range(0x312a, 0x312b), 660 regmap_reg_range(0x3136, 0x3139), 661 regmap_reg_range(0x313e, 0x313f), 662 regmap_reg_range(0x3400, 0x3401), 663 regmap_reg_range(0x3403, 0x3403), 664 regmap_reg_range(0x3410, 0x3417), 665 regmap_reg_range(0x3420, 0x3423), 666 regmap_reg_range(0x3500, 0x3507), 667 regmap_reg_range(0x3600, 0x3613), 668 regmap_reg_range(0x3800, 0x380f), 669 regmap_reg_range(0x3820, 0x3827), 670 regmap_reg_range(0x3830, 0x3837), 671 regmap_reg_range(0x3840, 0x384b), 672 regmap_reg_range(0x3900, 0x3907), 673 regmap_reg_range(0x3914, 0x391b), 674 regmap_reg_range(0x3920, 0x3920), 675 regmap_reg_range(0x3923, 0x3927), 676 regmap_reg_range(0x3a00, 0x3a03), 677 regmap_reg_range(0x3a04, 0x3a07), 678 regmap_reg_range(0x3b00, 0x3b01), 679 regmap_reg_range(0x3b04, 0x3b04), 680 regmap_reg_range(0x3c00, 0x3c05), 681 regmap_reg_range(0x3c08, 0x3c1b), 682 683 /* port 4 */ 684 regmap_reg_range(0x4000, 0x4001), 685 regmap_reg_range(0x4013, 0x4013), 686 regmap_reg_range(0x4017, 0x4017), 687 regmap_reg_range(0x401b, 0x401b), 688 regmap_reg_range(0x401f, 0x4020), 689 regmap_reg_range(0x4030, 0x4030), 690 regmap_reg_range(0x4100, 0x4115), 691 regmap_reg_range(0x411a, 0x411f), 692 regmap_reg_range(0x4122, 0x4127), 693 regmap_reg_range(0x412a, 0x412b), 694 regmap_reg_range(0x4136, 0x4139), 695 regmap_reg_range(0x413e, 0x413f), 696 regmap_reg_range(0x4400, 0x4401), 697 regmap_reg_range(0x4403, 0x4403), 698 regmap_reg_range(0x4410, 0x4417), 699 regmap_reg_range(0x4420, 0x4423), 700 regmap_reg_range(0x4500, 0x4507), 701 regmap_reg_range(0x4600, 0x4613), 702 regmap_reg_range(0x4800, 0x480f), 703 regmap_reg_range(0x4820, 0x4827), 704 regmap_reg_range(0x4830, 0x4837), 705 regmap_reg_range(0x4840, 0x484b), 706 regmap_reg_range(0x4900, 0x4907), 707 regmap_reg_range(0x4914, 0x491b), 708 regmap_reg_range(0x4920, 0x4920), 709 regmap_reg_range(0x4923, 0x4927), 710 regmap_reg_range(0x4a00, 0x4a03), 711 regmap_reg_range(0x4a04, 0x4a07), 712 regmap_reg_range(0x4b00, 0x4b01), 713 regmap_reg_range(0x4b04, 0x4b04), 714 regmap_reg_range(0x4c00, 0x4c05), 715 regmap_reg_range(0x4c08, 0x4c1b), 716 717 /* port 5 */ 718 regmap_reg_range(0x5000, 0x5001), 719 regmap_reg_range(0x5013, 0x5013), 720 regmap_reg_range(0x5017, 0x5017), 721 regmap_reg_range(0x501b, 0x501b), 722 regmap_reg_range(0x501f, 0x5020), 723 regmap_reg_range(0x5030, 0x5030), 724 regmap_reg_range(0x5100, 0x5115), 725 regmap_reg_range(0x511a, 0x511f), 726 regmap_reg_range(0x5122, 0x5127), 727 regmap_reg_range(0x512a, 0x512b), 728 regmap_reg_range(0x5136, 0x5139), 729 regmap_reg_range(0x513e, 0x513f), 730 regmap_reg_range(0x5400, 0x5401), 731 regmap_reg_range(0x5403, 0x5403), 732 regmap_reg_range(0x5410, 0x5417), 733 regmap_reg_range(0x5420, 0x5423), 734 regmap_reg_range(0x5500, 0x5507), 735 regmap_reg_range(0x5600, 0x5613), 736 regmap_reg_range(0x5800, 0x580f), 737 regmap_reg_range(0x5820, 0x5827), 738 regmap_reg_range(0x5830, 0x5837), 739 regmap_reg_range(0x5840, 0x584b), 740 regmap_reg_range(0x5900, 0x5907), 741 regmap_reg_range(0x5914, 0x591b), 742 regmap_reg_range(0x5920, 0x5920), 743 regmap_reg_range(0x5923, 0x5927), 744 regmap_reg_range(0x5a00, 0x5a03), 745 regmap_reg_range(0x5a04, 0x5a07), 746 regmap_reg_range(0x5b00, 0x5b01), 747 regmap_reg_range(0x5b04, 0x5b04), 748 regmap_reg_range(0x5c00, 0x5c05), 749 regmap_reg_range(0x5c08, 0x5c1b), 750 751 /* port 6 */ 752 regmap_reg_range(0x6000, 0x6001), 753 regmap_reg_range(0x6013, 0x6013), 754 regmap_reg_range(0x6017, 0x6017), 755 regmap_reg_range(0x601b, 0x601b), 756 regmap_reg_range(0x601f, 0x6020), 757 regmap_reg_range(0x6030, 0x6030), 758 regmap_reg_range(0x6300, 0x6301), 759 regmap_reg_range(0x6400, 0x6401), 760 regmap_reg_range(0x6403, 0x6403), 761 regmap_reg_range(0x6410, 0x6417), 762 regmap_reg_range(0x6420, 0x6423), 763 regmap_reg_range(0x6500, 0x6507), 764 regmap_reg_range(0x6600, 0x6613), 765 regmap_reg_range(0x6800, 0x680f), 766 regmap_reg_range(0x6820, 0x6827), 767 regmap_reg_range(0x6830, 0x6837), 768 regmap_reg_range(0x6840, 0x684b), 769 regmap_reg_range(0x6900, 0x6907), 770 regmap_reg_range(0x6914, 0x691b), 771 regmap_reg_range(0x6920, 0x6920), 772 regmap_reg_range(0x6923, 0x6927), 773 regmap_reg_range(0x6a00, 0x6a03), 774 regmap_reg_range(0x6a04, 0x6a07), 775 regmap_reg_range(0x6b00, 0x6b01), 776 regmap_reg_range(0x6b04, 0x6b04), 777 regmap_reg_range(0x6c00, 0x6c05), 778 regmap_reg_range(0x6c08, 0x6c1b), 779 780 /* port 7 */ 781 regmap_reg_range(0x7000, 0x7001), 782 regmap_reg_range(0x7013, 0x7013), 783 regmap_reg_range(0x7017, 0x7017), 784 regmap_reg_range(0x701b, 0x701b), 785 regmap_reg_range(0x701f, 0x7020), 786 regmap_reg_range(0x7030, 0x7030), 787 regmap_reg_range(0x7200, 0x7203), 788 regmap_reg_range(0x7206, 0x7207), 789 regmap_reg_range(0x7300, 0x7301), 790 regmap_reg_range(0x7400, 0x7401), 791 regmap_reg_range(0x7403, 0x7403), 792 regmap_reg_range(0x7410, 0x7417), 793 regmap_reg_range(0x7420, 0x7423), 794 regmap_reg_range(0x7500, 0x7507), 795 regmap_reg_range(0x7600, 0x7613), 796 regmap_reg_range(0x7800, 0x780f), 797 regmap_reg_range(0x7820, 0x7827), 798 regmap_reg_range(0x7830, 0x7837), 799 regmap_reg_range(0x7840, 0x784b), 800 regmap_reg_range(0x7900, 0x7907), 801 regmap_reg_range(0x7914, 0x791b), 802 regmap_reg_range(0x7920, 0x7920), 803 regmap_reg_range(0x7923, 0x7927), 804 regmap_reg_range(0x7a00, 0x7a03), 805 regmap_reg_range(0x7a04, 0x7a07), 806 regmap_reg_range(0x7b00, 0x7b01), 807 regmap_reg_range(0x7b04, 0x7b04), 808 regmap_reg_range(0x7c00, 0x7c05), 809 regmap_reg_range(0x7c08, 0x7c1b), 810 }; 811 812 static const struct regmap_access_table ksz9477_register_set = { 813 .yes_ranges = ksz9477_valid_regs, 814 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 815 }; 816 817 static const struct regmap_range ksz9896_valid_regs[] = { 818 regmap_reg_range(0x0000, 0x0003), 819 regmap_reg_range(0x0006, 0x0006), 820 regmap_reg_range(0x0010, 0x001f), 821 regmap_reg_range(0x0100, 0x0100), 822 regmap_reg_range(0x0103, 0x0107), 823 regmap_reg_range(0x010d, 0x010d), 824 regmap_reg_range(0x0110, 0x0113), 825 regmap_reg_range(0x0120, 0x0127), 826 regmap_reg_range(0x0201, 0x0201), 827 regmap_reg_range(0x0210, 0x0213), 828 regmap_reg_range(0x0300, 0x0300), 829 regmap_reg_range(0x0302, 0x030b), 830 regmap_reg_range(0x0310, 0x031b), 831 regmap_reg_range(0x0320, 0x032b), 832 regmap_reg_range(0x0330, 0x0336), 833 regmap_reg_range(0x0338, 0x033b), 834 regmap_reg_range(0x033e, 0x033e), 835 regmap_reg_range(0x0340, 0x035f), 836 regmap_reg_range(0x0370, 0x0370), 837 regmap_reg_range(0x0378, 0x0378), 838 regmap_reg_range(0x037c, 0x037d), 839 regmap_reg_range(0x0390, 0x0393), 840 regmap_reg_range(0x0400, 0x040e), 841 regmap_reg_range(0x0410, 0x042f), 842 843 /* port 1 */ 844 regmap_reg_range(0x1000, 0x1001), 845 regmap_reg_range(0x1013, 0x1013), 846 regmap_reg_range(0x1017, 0x1017), 847 regmap_reg_range(0x101b, 0x101b), 848 regmap_reg_range(0x101f, 0x1020), 849 regmap_reg_range(0x1030, 0x1030), 850 regmap_reg_range(0x1100, 0x1115), 851 regmap_reg_range(0x111a, 0x111f), 852 regmap_reg_range(0x1122, 0x1127), 853 regmap_reg_range(0x112a, 0x112b), 854 regmap_reg_range(0x1136, 0x1139), 855 regmap_reg_range(0x113e, 0x113f), 856 regmap_reg_range(0x1400, 0x1401), 857 regmap_reg_range(0x1403, 0x1403), 858 regmap_reg_range(0x1410, 0x1417), 859 regmap_reg_range(0x1420, 0x1423), 860 regmap_reg_range(0x1500, 0x1507), 861 regmap_reg_range(0x1600, 0x1612), 862 regmap_reg_range(0x1800, 0x180f), 863 regmap_reg_range(0x1820, 0x1827), 864 regmap_reg_range(0x1830, 0x1837), 865 regmap_reg_range(0x1840, 0x184b), 866 regmap_reg_range(0x1900, 0x1907), 867 regmap_reg_range(0x1914, 0x1915), 868 regmap_reg_range(0x1a00, 0x1a03), 869 regmap_reg_range(0x1a04, 0x1a07), 870 regmap_reg_range(0x1b00, 0x1b01), 871 regmap_reg_range(0x1b04, 0x1b04), 872 873 /* port 2 */ 874 regmap_reg_range(0x2000, 0x2001), 875 regmap_reg_range(0x2013, 0x2013), 876 regmap_reg_range(0x2017, 0x2017), 877 regmap_reg_range(0x201b, 0x201b), 878 regmap_reg_range(0x201f, 0x2020), 879 regmap_reg_range(0x2030, 0x2030), 880 regmap_reg_range(0x2100, 0x2115), 881 regmap_reg_range(0x211a, 0x211f), 882 regmap_reg_range(0x2122, 0x2127), 883 regmap_reg_range(0x212a, 0x212b), 884 regmap_reg_range(0x2136, 0x2139), 885 regmap_reg_range(0x213e, 0x213f), 886 regmap_reg_range(0x2400, 0x2401), 887 regmap_reg_range(0x2403, 0x2403), 888 regmap_reg_range(0x2410, 0x2417), 889 regmap_reg_range(0x2420, 0x2423), 890 regmap_reg_range(0x2500, 0x2507), 891 regmap_reg_range(0x2600, 0x2612), 892 regmap_reg_range(0x2800, 0x280f), 893 regmap_reg_range(0x2820, 0x2827), 894 regmap_reg_range(0x2830, 0x2837), 895 regmap_reg_range(0x2840, 0x284b), 896 regmap_reg_range(0x2900, 0x2907), 897 regmap_reg_range(0x2914, 0x2915), 898 regmap_reg_range(0x2a00, 0x2a03), 899 regmap_reg_range(0x2a04, 0x2a07), 900 regmap_reg_range(0x2b00, 0x2b01), 901 regmap_reg_range(0x2b04, 0x2b04), 902 903 /* port 3 */ 904 regmap_reg_range(0x3000, 0x3001), 905 regmap_reg_range(0x3013, 0x3013), 906 regmap_reg_range(0x3017, 0x3017), 907 regmap_reg_range(0x301b, 0x301b), 908 regmap_reg_range(0x301f, 0x3020), 909 regmap_reg_range(0x3030, 0x3030), 910 regmap_reg_range(0x3100, 0x3115), 911 regmap_reg_range(0x311a, 0x311f), 912 regmap_reg_range(0x3122, 0x3127), 913 regmap_reg_range(0x312a, 0x312b), 914 regmap_reg_range(0x3136, 0x3139), 915 regmap_reg_range(0x313e, 0x313f), 916 regmap_reg_range(0x3400, 0x3401), 917 regmap_reg_range(0x3403, 0x3403), 918 regmap_reg_range(0x3410, 0x3417), 919 regmap_reg_range(0x3420, 0x3423), 920 regmap_reg_range(0x3500, 0x3507), 921 regmap_reg_range(0x3600, 0x3612), 922 regmap_reg_range(0x3800, 0x380f), 923 regmap_reg_range(0x3820, 0x3827), 924 regmap_reg_range(0x3830, 0x3837), 925 regmap_reg_range(0x3840, 0x384b), 926 regmap_reg_range(0x3900, 0x3907), 927 regmap_reg_range(0x3914, 0x3915), 928 regmap_reg_range(0x3a00, 0x3a03), 929 regmap_reg_range(0x3a04, 0x3a07), 930 regmap_reg_range(0x3b00, 0x3b01), 931 regmap_reg_range(0x3b04, 0x3b04), 932 933 /* port 4 */ 934 regmap_reg_range(0x4000, 0x4001), 935 regmap_reg_range(0x4013, 0x4013), 936 regmap_reg_range(0x4017, 0x4017), 937 regmap_reg_range(0x401b, 0x401b), 938 regmap_reg_range(0x401f, 0x4020), 939 regmap_reg_range(0x4030, 0x4030), 940 regmap_reg_range(0x4100, 0x4115), 941 regmap_reg_range(0x411a, 0x411f), 942 regmap_reg_range(0x4122, 0x4127), 943 regmap_reg_range(0x412a, 0x412b), 944 regmap_reg_range(0x4136, 0x4139), 945 regmap_reg_range(0x413e, 0x413f), 946 regmap_reg_range(0x4400, 0x4401), 947 regmap_reg_range(0x4403, 0x4403), 948 regmap_reg_range(0x4410, 0x4417), 949 regmap_reg_range(0x4420, 0x4423), 950 regmap_reg_range(0x4500, 0x4507), 951 regmap_reg_range(0x4600, 0x4612), 952 regmap_reg_range(0x4800, 0x480f), 953 regmap_reg_range(0x4820, 0x4827), 954 regmap_reg_range(0x4830, 0x4837), 955 regmap_reg_range(0x4840, 0x484b), 956 regmap_reg_range(0x4900, 0x4907), 957 regmap_reg_range(0x4914, 0x4915), 958 regmap_reg_range(0x4a00, 0x4a03), 959 regmap_reg_range(0x4a04, 0x4a07), 960 regmap_reg_range(0x4b00, 0x4b01), 961 regmap_reg_range(0x4b04, 0x4b04), 962 963 /* port 5 */ 964 regmap_reg_range(0x5000, 0x5001), 965 regmap_reg_range(0x5013, 0x5013), 966 regmap_reg_range(0x5017, 0x5017), 967 regmap_reg_range(0x501b, 0x501b), 968 regmap_reg_range(0x501f, 0x5020), 969 regmap_reg_range(0x5030, 0x5030), 970 regmap_reg_range(0x5100, 0x5115), 971 regmap_reg_range(0x511a, 0x511f), 972 regmap_reg_range(0x5122, 0x5127), 973 regmap_reg_range(0x512a, 0x512b), 974 regmap_reg_range(0x5136, 0x5139), 975 regmap_reg_range(0x513e, 0x513f), 976 regmap_reg_range(0x5400, 0x5401), 977 regmap_reg_range(0x5403, 0x5403), 978 regmap_reg_range(0x5410, 0x5417), 979 regmap_reg_range(0x5420, 0x5423), 980 regmap_reg_range(0x5500, 0x5507), 981 regmap_reg_range(0x5600, 0x5612), 982 regmap_reg_range(0x5800, 0x580f), 983 regmap_reg_range(0x5820, 0x5827), 984 regmap_reg_range(0x5830, 0x5837), 985 regmap_reg_range(0x5840, 0x584b), 986 regmap_reg_range(0x5900, 0x5907), 987 regmap_reg_range(0x5914, 0x5915), 988 regmap_reg_range(0x5a00, 0x5a03), 989 regmap_reg_range(0x5a04, 0x5a07), 990 regmap_reg_range(0x5b00, 0x5b01), 991 regmap_reg_range(0x5b04, 0x5b04), 992 993 /* port 6 */ 994 regmap_reg_range(0x6000, 0x6001), 995 regmap_reg_range(0x6013, 0x6013), 996 regmap_reg_range(0x6017, 0x6017), 997 regmap_reg_range(0x601b, 0x601b), 998 regmap_reg_range(0x601f, 0x6020), 999 regmap_reg_range(0x6030, 0x6030), 1000 regmap_reg_range(0x6100, 0x6115), 1001 regmap_reg_range(0x611a, 0x611f), 1002 regmap_reg_range(0x6122, 0x6127), 1003 regmap_reg_range(0x612a, 0x612b), 1004 regmap_reg_range(0x6136, 0x6139), 1005 regmap_reg_range(0x613e, 0x613f), 1006 regmap_reg_range(0x6300, 0x6301), 1007 regmap_reg_range(0x6400, 0x6401), 1008 regmap_reg_range(0x6403, 0x6403), 1009 regmap_reg_range(0x6410, 0x6417), 1010 regmap_reg_range(0x6420, 0x6423), 1011 regmap_reg_range(0x6500, 0x6507), 1012 regmap_reg_range(0x6600, 0x6612), 1013 regmap_reg_range(0x6800, 0x680f), 1014 regmap_reg_range(0x6820, 0x6827), 1015 regmap_reg_range(0x6830, 0x6837), 1016 regmap_reg_range(0x6840, 0x684b), 1017 regmap_reg_range(0x6900, 0x6907), 1018 regmap_reg_range(0x6914, 0x6915), 1019 regmap_reg_range(0x6a00, 0x6a03), 1020 regmap_reg_range(0x6a04, 0x6a07), 1021 regmap_reg_range(0x6b00, 0x6b01), 1022 regmap_reg_range(0x6b04, 0x6b04), 1023 }; 1024 1025 static const struct regmap_access_table ksz9896_register_set = { 1026 .yes_ranges = ksz9896_valid_regs, 1027 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1028 }; 1029 1030 const struct ksz_chip_data ksz_switch_chips[] = { 1031 [KSZ8563] = { 1032 .chip_id = KSZ8563_CHIP_ID, 1033 .dev_name = "KSZ8563", 1034 .num_vlans = 4096, 1035 .num_alus = 4096, 1036 .num_statics = 16, 1037 .cpu_ports = 0x07, /* can be configured as cpu port */ 1038 .port_cnt = 3, /* total port count */ 1039 .ops = &ksz9477_dev_ops, 1040 .mib_names = ksz9477_mib_names, 1041 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1042 .reg_mib_cnt = MIB_COUNTER_NUM, 1043 .regs = ksz9477_regs, 1044 .masks = ksz9477_masks, 1045 .shifts = ksz9477_shifts, 1046 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1047 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1048 .supports_mii = {false, false, true}, 1049 .supports_rmii = {false, false, true}, 1050 .supports_rgmii = {false, false, true}, 1051 .internal_phy = {true, true, false}, 1052 .gbit_capable = {false, false, true}, 1053 .wr_table = &ksz8563_register_set, 1054 .rd_table = &ksz8563_register_set, 1055 }, 1056 1057 [KSZ8795] = { 1058 .chip_id = KSZ8795_CHIP_ID, 1059 .dev_name = "KSZ8795", 1060 .num_vlans = 4096, 1061 .num_alus = 0, 1062 .num_statics = 8, 1063 .cpu_ports = 0x10, /* can be configured as cpu port */ 1064 .port_cnt = 5, /* total cpu and user ports */ 1065 .ops = &ksz8_dev_ops, 1066 .ksz87xx_eee_link_erratum = true, 1067 .mib_names = ksz9477_mib_names, 1068 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1069 .reg_mib_cnt = MIB_COUNTER_NUM, 1070 .regs = ksz8795_regs, 1071 .masks = ksz8795_masks, 1072 .shifts = ksz8795_shifts, 1073 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1074 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1075 .supports_mii = {false, false, false, false, true}, 1076 .supports_rmii = {false, false, false, false, true}, 1077 .supports_rgmii = {false, false, false, false, true}, 1078 .internal_phy = {true, true, true, true, false}, 1079 }, 1080 1081 [KSZ8794] = { 1082 /* WARNING 1083 * ======= 1084 * KSZ8794 is similar to KSZ8795, except the port map 1085 * contains a gap between external and CPU ports, the 1086 * port map is NOT continuous. The per-port register 1087 * map is shifted accordingly too, i.e. registers at 1088 * offset 0x40 are NOT used on KSZ8794 and they ARE 1089 * used on KSZ8795 for external port 3. 1090 * external cpu 1091 * KSZ8794 0,1,2 4 1092 * KSZ8795 0,1,2,3 4 1093 * KSZ8765 0,1,2,3 4 1094 * port_cnt is configured as 5, even though it is 4 1095 */ 1096 .chip_id = KSZ8794_CHIP_ID, 1097 .dev_name = "KSZ8794", 1098 .num_vlans = 4096, 1099 .num_alus = 0, 1100 .num_statics = 8, 1101 .cpu_ports = 0x10, /* can be configured as cpu port */ 1102 .port_cnt = 5, /* total cpu and user ports */ 1103 .ops = &ksz8_dev_ops, 1104 .ksz87xx_eee_link_erratum = true, 1105 .mib_names = ksz9477_mib_names, 1106 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1107 .reg_mib_cnt = MIB_COUNTER_NUM, 1108 .regs = ksz8795_regs, 1109 .masks = ksz8795_masks, 1110 .shifts = ksz8795_shifts, 1111 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1112 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1113 .supports_mii = {false, false, false, false, true}, 1114 .supports_rmii = {false, false, false, false, true}, 1115 .supports_rgmii = {false, false, false, false, true}, 1116 .internal_phy = {true, true, true, false, false}, 1117 }, 1118 1119 [KSZ8765] = { 1120 .chip_id = KSZ8765_CHIP_ID, 1121 .dev_name = "KSZ8765", 1122 .num_vlans = 4096, 1123 .num_alus = 0, 1124 .num_statics = 8, 1125 .cpu_ports = 0x10, /* can be configured as cpu port */ 1126 .port_cnt = 5, /* total cpu and user ports */ 1127 .ops = &ksz8_dev_ops, 1128 .ksz87xx_eee_link_erratum = true, 1129 .mib_names = ksz9477_mib_names, 1130 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1131 .reg_mib_cnt = MIB_COUNTER_NUM, 1132 .regs = ksz8795_regs, 1133 .masks = ksz8795_masks, 1134 .shifts = ksz8795_shifts, 1135 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1136 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1137 .supports_mii = {false, false, false, false, true}, 1138 .supports_rmii = {false, false, false, false, true}, 1139 .supports_rgmii = {false, false, false, false, true}, 1140 .internal_phy = {true, true, true, true, false}, 1141 }, 1142 1143 [KSZ8830] = { 1144 .chip_id = KSZ8830_CHIP_ID, 1145 .dev_name = "KSZ8863/KSZ8873", 1146 .num_vlans = 16, 1147 .num_alus = 0, 1148 .num_statics = 8, 1149 .cpu_ports = 0x4, /* can be configured as cpu port */ 1150 .port_cnt = 3, 1151 .ops = &ksz8_dev_ops, 1152 .mib_names = ksz88xx_mib_names, 1153 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1154 .reg_mib_cnt = MIB_COUNTER_NUM, 1155 .regs = ksz8863_regs, 1156 .masks = ksz8863_masks, 1157 .shifts = ksz8863_shifts, 1158 .supports_mii = {false, false, true}, 1159 .supports_rmii = {false, false, true}, 1160 .internal_phy = {true, true, false}, 1161 }, 1162 1163 [KSZ9477] = { 1164 .chip_id = KSZ9477_CHIP_ID, 1165 .dev_name = "KSZ9477", 1166 .num_vlans = 4096, 1167 .num_alus = 4096, 1168 .num_statics = 16, 1169 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1170 .port_cnt = 7, /* total physical port count */ 1171 .ops = &ksz9477_dev_ops, 1172 .phy_errata_9477 = true, 1173 .mib_names = ksz9477_mib_names, 1174 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1175 .reg_mib_cnt = MIB_COUNTER_NUM, 1176 .regs = ksz9477_regs, 1177 .masks = ksz9477_masks, 1178 .shifts = ksz9477_shifts, 1179 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1180 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1181 .supports_mii = {false, false, false, false, 1182 false, true, false}, 1183 .supports_rmii = {false, false, false, false, 1184 false, true, false}, 1185 .supports_rgmii = {false, false, false, false, 1186 false, true, false}, 1187 .internal_phy = {true, true, true, true, 1188 true, false, false}, 1189 .gbit_capable = {true, true, true, true, true, true, true}, 1190 .wr_table = &ksz9477_register_set, 1191 .rd_table = &ksz9477_register_set, 1192 }, 1193 1194 [KSZ9896] = { 1195 .chip_id = KSZ9896_CHIP_ID, 1196 .dev_name = "KSZ9896", 1197 .num_vlans = 4096, 1198 .num_alus = 4096, 1199 .num_statics = 16, 1200 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1201 .port_cnt = 6, /* total physical port count */ 1202 .ops = &ksz9477_dev_ops, 1203 .phy_errata_9477 = true, 1204 .mib_names = ksz9477_mib_names, 1205 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1206 .reg_mib_cnt = MIB_COUNTER_NUM, 1207 .regs = ksz9477_regs, 1208 .masks = ksz9477_masks, 1209 .shifts = ksz9477_shifts, 1210 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1211 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1212 .supports_mii = {false, false, false, false, 1213 false, true}, 1214 .supports_rmii = {false, false, false, false, 1215 false, true}, 1216 .supports_rgmii = {false, false, false, false, 1217 false, true}, 1218 .internal_phy = {true, true, true, true, 1219 true, false}, 1220 .gbit_capable = {true, true, true, true, true, true}, 1221 .wr_table = &ksz9896_register_set, 1222 .rd_table = &ksz9896_register_set, 1223 }, 1224 1225 [KSZ9897] = { 1226 .chip_id = KSZ9897_CHIP_ID, 1227 .dev_name = "KSZ9897", 1228 .num_vlans = 4096, 1229 .num_alus = 4096, 1230 .num_statics = 16, 1231 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1232 .port_cnt = 7, /* total physical port count */ 1233 .ops = &ksz9477_dev_ops, 1234 .phy_errata_9477 = true, 1235 .mib_names = ksz9477_mib_names, 1236 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1237 .reg_mib_cnt = MIB_COUNTER_NUM, 1238 .regs = ksz9477_regs, 1239 .masks = ksz9477_masks, 1240 .shifts = ksz9477_shifts, 1241 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1242 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1243 .supports_mii = {false, false, false, false, 1244 false, true, true}, 1245 .supports_rmii = {false, false, false, false, 1246 false, true, true}, 1247 .supports_rgmii = {false, false, false, false, 1248 false, true, true}, 1249 .internal_phy = {true, true, true, true, 1250 true, false, false}, 1251 .gbit_capable = {true, true, true, true, true, true, true}, 1252 }, 1253 1254 [KSZ9893] = { 1255 .chip_id = KSZ9893_CHIP_ID, 1256 .dev_name = "KSZ9893", 1257 .num_vlans = 4096, 1258 .num_alus = 4096, 1259 .num_statics = 16, 1260 .cpu_ports = 0x07, /* can be configured as cpu port */ 1261 .port_cnt = 3, /* total port count */ 1262 .ops = &ksz9477_dev_ops, 1263 .mib_names = ksz9477_mib_names, 1264 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1265 .reg_mib_cnt = MIB_COUNTER_NUM, 1266 .regs = ksz9477_regs, 1267 .masks = ksz9477_masks, 1268 .shifts = ksz9477_shifts, 1269 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1270 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1271 .supports_mii = {false, false, true}, 1272 .supports_rmii = {false, false, true}, 1273 .supports_rgmii = {false, false, true}, 1274 .internal_phy = {true, true, false}, 1275 .gbit_capable = {true, true, true}, 1276 }, 1277 1278 [KSZ9567] = { 1279 .chip_id = KSZ9567_CHIP_ID, 1280 .dev_name = "KSZ9567", 1281 .num_vlans = 4096, 1282 .num_alus = 4096, 1283 .num_statics = 16, 1284 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1285 .port_cnt = 7, /* total physical port count */ 1286 .ops = &ksz9477_dev_ops, 1287 .phy_errata_9477 = true, 1288 .mib_names = ksz9477_mib_names, 1289 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1290 .reg_mib_cnt = MIB_COUNTER_NUM, 1291 .regs = ksz9477_regs, 1292 .masks = ksz9477_masks, 1293 .shifts = ksz9477_shifts, 1294 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1295 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1296 .supports_mii = {false, false, false, false, 1297 false, true, true}, 1298 .supports_rmii = {false, false, false, false, 1299 false, true, true}, 1300 .supports_rgmii = {false, false, false, false, 1301 false, true, true}, 1302 .internal_phy = {true, true, true, true, 1303 true, false, false}, 1304 .gbit_capable = {true, true, true, true, true, true, true}, 1305 }, 1306 1307 [LAN9370] = { 1308 .chip_id = LAN9370_CHIP_ID, 1309 .dev_name = "LAN9370", 1310 .num_vlans = 4096, 1311 .num_alus = 1024, 1312 .num_statics = 256, 1313 .cpu_ports = 0x10, /* can be configured as cpu port */ 1314 .port_cnt = 5, /* total physical port count */ 1315 .ops = &lan937x_dev_ops, 1316 .mib_names = ksz9477_mib_names, 1317 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1318 .reg_mib_cnt = MIB_COUNTER_NUM, 1319 .regs = ksz9477_regs, 1320 .masks = lan937x_masks, 1321 .shifts = lan937x_shifts, 1322 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1323 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1324 .supports_mii = {false, false, false, false, true}, 1325 .supports_rmii = {false, false, false, false, true}, 1326 .supports_rgmii = {false, false, false, false, true}, 1327 .internal_phy = {true, true, true, true, false}, 1328 }, 1329 1330 [LAN9371] = { 1331 .chip_id = LAN9371_CHIP_ID, 1332 .dev_name = "LAN9371", 1333 .num_vlans = 4096, 1334 .num_alus = 1024, 1335 .num_statics = 256, 1336 .cpu_ports = 0x30, /* can be configured as cpu port */ 1337 .port_cnt = 6, /* total physical port count */ 1338 .ops = &lan937x_dev_ops, 1339 .mib_names = ksz9477_mib_names, 1340 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1341 .reg_mib_cnt = MIB_COUNTER_NUM, 1342 .regs = ksz9477_regs, 1343 .masks = lan937x_masks, 1344 .shifts = lan937x_shifts, 1345 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1346 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1347 .supports_mii = {false, false, false, false, true, true}, 1348 .supports_rmii = {false, false, false, false, true, true}, 1349 .supports_rgmii = {false, false, false, false, true, true}, 1350 .internal_phy = {true, true, true, true, false, false}, 1351 }, 1352 1353 [LAN9372] = { 1354 .chip_id = LAN9372_CHIP_ID, 1355 .dev_name = "LAN9372", 1356 .num_vlans = 4096, 1357 .num_alus = 1024, 1358 .num_statics = 256, 1359 .cpu_ports = 0x30, /* can be configured as cpu port */ 1360 .port_cnt = 8, /* total physical port count */ 1361 .ops = &lan937x_dev_ops, 1362 .mib_names = ksz9477_mib_names, 1363 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1364 .reg_mib_cnt = MIB_COUNTER_NUM, 1365 .regs = ksz9477_regs, 1366 .masks = lan937x_masks, 1367 .shifts = lan937x_shifts, 1368 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1369 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1370 .supports_mii = {false, false, false, false, 1371 true, true, false, false}, 1372 .supports_rmii = {false, false, false, false, 1373 true, true, false, false}, 1374 .supports_rgmii = {false, false, false, false, 1375 true, true, false, false}, 1376 .internal_phy = {true, true, true, true, 1377 false, false, true, true}, 1378 }, 1379 1380 [LAN9373] = { 1381 .chip_id = LAN9373_CHIP_ID, 1382 .dev_name = "LAN9373", 1383 .num_vlans = 4096, 1384 .num_alus = 1024, 1385 .num_statics = 256, 1386 .cpu_ports = 0x38, /* can be configured as cpu port */ 1387 .port_cnt = 5, /* total physical port count */ 1388 .ops = &lan937x_dev_ops, 1389 .mib_names = ksz9477_mib_names, 1390 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1391 .reg_mib_cnt = MIB_COUNTER_NUM, 1392 .regs = ksz9477_regs, 1393 .masks = lan937x_masks, 1394 .shifts = lan937x_shifts, 1395 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1396 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1397 .supports_mii = {false, false, false, false, 1398 true, true, false, false}, 1399 .supports_rmii = {false, false, false, false, 1400 true, true, false, false}, 1401 .supports_rgmii = {false, false, false, false, 1402 true, true, false, false}, 1403 .internal_phy = {true, true, true, false, 1404 false, false, true, true}, 1405 }, 1406 1407 [LAN9374] = { 1408 .chip_id = LAN9374_CHIP_ID, 1409 .dev_name = "LAN9374", 1410 .num_vlans = 4096, 1411 .num_alus = 1024, 1412 .num_statics = 256, 1413 .cpu_ports = 0x30, /* can be configured as cpu port */ 1414 .port_cnt = 8, /* total physical port count */ 1415 .ops = &lan937x_dev_ops, 1416 .mib_names = ksz9477_mib_names, 1417 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1418 .reg_mib_cnt = MIB_COUNTER_NUM, 1419 .regs = ksz9477_regs, 1420 .masks = lan937x_masks, 1421 .shifts = lan937x_shifts, 1422 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1423 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1424 .supports_mii = {false, false, false, false, 1425 true, true, false, false}, 1426 .supports_rmii = {false, false, false, false, 1427 true, true, false, false}, 1428 .supports_rgmii = {false, false, false, false, 1429 true, true, false, false}, 1430 .internal_phy = {true, true, true, true, 1431 false, false, true, true}, 1432 }, 1433 }; 1434 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1435 1436 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1437 { 1438 int i; 1439 1440 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1441 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1442 1443 if (chip->chip_id == prod_num) 1444 return chip; 1445 } 1446 1447 return NULL; 1448 } 1449 1450 static int ksz_check_device_id(struct ksz_device *dev) 1451 { 1452 const struct ksz_chip_data *dt_chip_data; 1453 1454 dt_chip_data = of_device_get_match_data(dev->dev); 1455 1456 /* Check for Device Tree and Chip ID */ 1457 if (dt_chip_data->chip_id != dev->chip_id) { 1458 dev_err(dev->dev, 1459 "Device tree specifies chip %s but found %s, please fix it!\n", 1460 dt_chip_data->dev_name, dev->info->dev_name); 1461 return -ENODEV; 1462 } 1463 1464 return 0; 1465 } 1466 1467 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1468 struct phylink_config *config) 1469 { 1470 struct ksz_device *dev = ds->priv; 1471 1472 config->legacy_pre_march2020 = false; 1473 1474 if (dev->info->supports_mii[port]) 1475 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1476 1477 if (dev->info->supports_rmii[port]) 1478 __set_bit(PHY_INTERFACE_MODE_RMII, 1479 config->supported_interfaces); 1480 1481 if (dev->info->supports_rgmii[port]) 1482 phy_interface_set_rgmii(config->supported_interfaces); 1483 1484 if (dev->info->internal_phy[port]) { 1485 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1486 config->supported_interfaces); 1487 /* Compatibility for phylib's default interface type when the 1488 * phy-mode property is absent 1489 */ 1490 __set_bit(PHY_INTERFACE_MODE_GMII, 1491 config->supported_interfaces); 1492 } 1493 1494 if (dev->dev_ops->get_caps) 1495 dev->dev_ops->get_caps(dev, port, config); 1496 } 1497 1498 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 1499 { 1500 struct ethtool_pause_stats *pstats; 1501 struct rtnl_link_stats64 *stats; 1502 struct ksz_stats_raw *raw; 1503 struct ksz_port_mib *mib; 1504 1505 mib = &dev->ports[port].mib; 1506 stats = &mib->stats64; 1507 pstats = &mib->pause_stats; 1508 raw = (struct ksz_stats_raw *)mib->counters; 1509 1510 spin_lock(&mib->stats64_lock); 1511 1512 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1513 raw->rx_pause; 1514 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1515 raw->tx_pause; 1516 1517 /* HW counters are counting bytes + FCS which is not acceptable 1518 * for rtnl_link_stats64 interface 1519 */ 1520 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 1521 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 1522 1523 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1524 raw->rx_oversize; 1525 1526 stats->rx_crc_errors = raw->rx_crc_err; 1527 stats->rx_frame_errors = raw->rx_align_err; 1528 stats->rx_dropped = raw->rx_discards; 1529 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1530 stats->rx_frame_errors + stats->rx_dropped; 1531 1532 stats->tx_window_errors = raw->tx_late_col; 1533 stats->tx_fifo_errors = raw->tx_discards; 1534 stats->tx_aborted_errors = raw->tx_exc_col; 1535 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1536 stats->tx_aborted_errors; 1537 1538 stats->multicast = raw->rx_mcast; 1539 stats->collisions = raw->tx_total_col; 1540 1541 pstats->tx_pause_frames = raw->tx_pause; 1542 pstats->rx_pause_frames = raw->rx_pause; 1543 1544 spin_unlock(&mib->stats64_lock); 1545 } 1546 1547 static void ksz_get_stats64(struct dsa_switch *ds, int port, 1548 struct rtnl_link_stats64 *s) 1549 { 1550 struct ksz_device *dev = ds->priv; 1551 struct ksz_port_mib *mib; 1552 1553 mib = &dev->ports[port].mib; 1554 1555 spin_lock(&mib->stats64_lock); 1556 memcpy(s, &mib->stats64, sizeof(*s)); 1557 spin_unlock(&mib->stats64_lock); 1558 } 1559 1560 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 1561 struct ethtool_pause_stats *pause_stats) 1562 { 1563 struct ksz_device *dev = ds->priv; 1564 struct ksz_port_mib *mib; 1565 1566 mib = &dev->ports[port].mib; 1567 1568 spin_lock(&mib->stats64_lock); 1569 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 1570 spin_unlock(&mib->stats64_lock); 1571 } 1572 1573 static void ksz_get_strings(struct dsa_switch *ds, int port, 1574 u32 stringset, uint8_t *buf) 1575 { 1576 struct ksz_device *dev = ds->priv; 1577 int i; 1578 1579 if (stringset != ETH_SS_STATS) 1580 return; 1581 1582 for (i = 0; i < dev->info->mib_cnt; i++) { 1583 memcpy(buf + i * ETH_GSTRING_LEN, 1584 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 1585 } 1586 } 1587 1588 static void ksz_update_port_member(struct ksz_device *dev, int port) 1589 { 1590 struct ksz_port *p = &dev->ports[port]; 1591 struct dsa_switch *ds = dev->ds; 1592 u8 port_member = 0, cpu_port; 1593 const struct dsa_port *dp; 1594 int i, j; 1595 1596 if (!dsa_is_user_port(ds, port)) 1597 return; 1598 1599 dp = dsa_to_port(ds, port); 1600 cpu_port = BIT(dsa_upstream_port(ds, port)); 1601 1602 for (i = 0; i < ds->num_ports; i++) { 1603 const struct dsa_port *other_dp = dsa_to_port(ds, i); 1604 struct ksz_port *other_p = &dev->ports[i]; 1605 u8 val = 0; 1606 1607 if (!dsa_is_user_port(ds, i)) 1608 continue; 1609 if (port == i) 1610 continue; 1611 if (!dsa_port_bridge_same(dp, other_dp)) 1612 continue; 1613 if (other_p->stp_state != BR_STATE_FORWARDING) 1614 continue; 1615 1616 if (p->stp_state == BR_STATE_FORWARDING) { 1617 val |= BIT(port); 1618 port_member |= BIT(i); 1619 } 1620 1621 /* Retain port [i]'s relationship to other ports than [port] */ 1622 for (j = 0; j < ds->num_ports; j++) { 1623 const struct dsa_port *third_dp; 1624 struct ksz_port *third_p; 1625 1626 if (j == i) 1627 continue; 1628 if (j == port) 1629 continue; 1630 if (!dsa_is_user_port(ds, j)) 1631 continue; 1632 third_p = &dev->ports[j]; 1633 if (third_p->stp_state != BR_STATE_FORWARDING) 1634 continue; 1635 third_dp = dsa_to_port(ds, j); 1636 if (dsa_port_bridge_same(other_dp, third_dp)) 1637 val |= BIT(j); 1638 } 1639 1640 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 1641 } 1642 1643 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 1644 } 1645 1646 static int ksz_setup(struct dsa_switch *ds) 1647 { 1648 struct ksz_device *dev = ds->priv; 1649 struct ksz_port *p; 1650 const u16 *regs; 1651 int ret; 1652 1653 regs = dev->info->regs; 1654 1655 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1656 dev->info->num_vlans, GFP_KERNEL); 1657 if (!dev->vlan_cache) 1658 return -ENOMEM; 1659 1660 ret = dev->dev_ops->reset(dev); 1661 if (ret) { 1662 dev_err(ds->dev, "failed to reset switch\n"); 1663 return ret; 1664 } 1665 1666 /* set broadcast storm protection 10% rate */ 1667 regmap_update_bits(dev->regmap[1], regs[S_BROADCAST_CTRL], 1668 BROADCAST_STORM_RATE, 1669 (BROADCAST_STORM_VALUE * 1670 BROADCAST_STORM_PROT_RATE) / 100); 1671 1672 dev->dev_ops->config_cpu_port(ds); 1673 1674 dev->dev_ops->enable_stp_addr(dev); 1675 1676 regmap_update_bits(dev->regmap[0], regs[S_MULTICAST_CTRL], 1677 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 1678 1679 ksz_init_mib_timer(dev); 1680 1681 ds->configure_vlan_while_not_filtering = false; 1682 1683 if (dev->dev_ops->setup) { 1684 ret = dev->dev_ops->setup(ds); 1685 if (ret) 1686 return ret; 1687 } 1688 1689 /* Start with learning disabled on standalone user ports, and enabled 1690 * on the CPU port. In lack of other finer mechanisms, learning on the 1691 * CPU port will avoid flooding bridge local addresses on the network 1692 * in some cases. 1693 */ 1694 p = &dev->ports[dev->cpu_port]; 1695 p->learning = true; 1696 1697 /* start switch */ 1698 regmap_update_bits(dev->regmap[0], regs[S_START_CTRL], 1699 SW_START, SW_START); 1700 1701 return 0; 1702 } 1703 1704 static void ksz_teardown(struct dsa_switch *ds) 1705 { 1706 struct ksz_device *dev = ds->priv; 1707 1708 if (dev->dev_ops->teardown) 1709 dev->dev_ops->teardown(ds); 1710 } 1711 1712 static void port_r_cnt(struct ksz_device *dev, int port) 1713 { 1714 struct ksz_port_mib *mib = &dev->ports[port].mib; 1715 u64 *dropped; 1716 1717 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 1718 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 1719 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 1720 &mib->counters[mib->cnt_ptr]); 1721 ++mib->cnt_ptr; 1722 } 1723 1724 /* last one in storage */ 1725 dropped = &mib->counters[dev->info->mib_cnt]; 1726 1727 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 1728 while (mib->cnt_ptr < dev->info->mib_cnt) { 1729 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 1730 dropped, &mib->counters[mib->cnt_ptr]); 1731 ++mib->cnt_ptr; 1732 } 1733 mib->cnt_ptr = 0; 1734 } 1735 1736 static void ksz_mib_read_work(struct work_struct *work) 1737 { 1738 struct ksz_device *dev = container_of(work, struct ksz_device, 1739 mib_read.work); 1740 struct ksz_port_mib *mib; 1741 struct ksz_port *p; 1742 int i; 1743 1744 for (i = 0; i < dev->info->port_cnt; i++) { 1745 if (dsa_is_unused_port(dev->ds, i)) 1746 continue; 1747 1748 p = &dev->ports[i]; 1749 mib = &p->mib; 1750 mutex_lock(&mib->cnt_mutex); 1751 1752 /* Only read MIB counters when the port is told to do. 1753 * If not, read only dropped counters when link is not up. 1754 */ 1755 if (!p->read) { 1756 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 1757 1758 if (!netif_carrier_ok(dp->slave)) 1759 mib->cnt_ptr = dev->info->reg_mib_cnt; 1760 } 1761 port_r_cnt(dev, i); 1762 p->read = false; 1763 1764 if (dev->dev_ops->r_mib_stat64) 1765 dev->dev_ops->r_mib_stat64(dev, i); 1766 1767 mutex_unlock(&mib->cnt_mutex); 1768 } 1769 1770 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 1771 } 1772 1773 void ksz_init_mib_timer(struct ksz_device *dev) 1774 { 1775 int i; 1776 1777 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 1778 1779 for (i = 0; i < dev->info->port_cnt; i++) { 1780 struct ksz_port_mib *mib = &dev->ports[i].mib; 1781 1782 dev->dev_ops->port_init_cnt(dev, i); 1783 1784 mib->cnt_ptr = 0; 1785 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 1786 } 1787 } 1788 1789 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 1790 { 1791 struct ksz_device *dev = ds->priv; 1792 u16 val = 0xffff; 1793 int ret; 1794 1795 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 1796 if (ret) 1797 return ret; 1798 1799 return val; 1800 } 1801 1802 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 1803 { 1804 struct ksz_device *dev = ds->priv; 1805 int ret; 1806 1807 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 1808 if (ret) 1809 return ret; 1810 1811 return 0; 1812 } 1813 1814 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 1815 { 1816 struct ksz_device *dev = ds->priv; 1817 1818 if (dev->chip_id == KSZ8830_CHIP_ID) { 1819 /* Silicon Errata Sheet (DS80000830A): 1820 * Port 1 does not work with LinkMD Cable-Testing. 1821 * Port 1 does not respond to received PAUSE control frames. 1822 */ 1823 if (!port) 1824 return MICREL_KSZ8_P1_ERRATA; 1825 } 1826 1827 return 0; 1828 } 1829 1830 static void ksz_mac_link_down(struct dsa_switch *ds, int port, 1831 unsigned int mode, phy_interface_t interface) 1832 { 1833 struct ksz_device *dev = ds->priv; 1834 struct ksz_port *p = &dev->ports[port]; 1835 1836 /* Read all MIB counters when the link is going down. */ 1837 p->read = true; 1838 /* timer started */ 1839 if (dev->mib_read_interval) 1840 schedule_delayed_work(&dev->mib_read, 0); 1841 } 1842 1843 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 1844 { 1845 struct ksz_device *dev = ds->priv; 1846 1847 if (sset != ETH_SS_STATS) 1848 return 0; 1849 1850 return dev->info->mib_cnt; 1851 } 1852 1853 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 1854 uint64_t *buf) 1855 { 1856 const struct dsa_port *dp = dsa_to_port(ds, port); 1857 struct ksz_device *dev = ds->priv; 1858 struct ksz_port_mib *mib; 1859 1860 mib = &dev->ports[port].mib; 1861 mutex_lock(&mib->cnt_mutex); 1862 1863 /* Only read dropped counters if no link. */ 1864 if (!netif_carrier_ok(dp->slave)) 1865 mib->cnt_ptr = dev->info->reg_mib_cnt; 1866 port_r_cnt(dev, port); 1867 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 1868 mutex_unlock(&mib->cnt_mutex); 1869 } 1870 1871 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 1872 struct dsa_bridge bridge, 1873 bool *tx_fwd_offload, 1874 struct netlink_ext_ack *extack) 1875 { 1876 /* port_stp_state_set() will be called after to put the port in 1877 * appropriate state so there is no need to do anything. 1878 */ 1879 1880 return 0; 1881 } 1882 1883 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 1884 struct dsa_bridge bridge) 1885 { 1886 /* port_stp_state_set() will be called after to put the port in 1887 * forwarding state so there is no need to do anything. 1888 */ 1889 } 1890 1891 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 1892 { 1893 struct ksz_device *dev = ds->priv; 1894 1895 dev->dev_ops->flush_dyn_mac_table(dev, port); 1896 } 1897 1898 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 1899 { 1900 struct ksz_device *dev = ds->priv; 1901 1902 if (!dev->dev_ops->set_ageing_time) 1903 return -EOPNOTSUPP; 1904 1905 return dev->dev_ops->set_ageing_time(dev, msecs); 1906 } 1907 1908 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 1909 const unsigned char *addr, u16 vid, 1910 struct dsa_db db) 1911 { 1912 struct ksz_device *dev = ds->priv; 1913 1914 if (!dev->dev_ops->fdb_add) 1915 return -EOPNOTSUPP; 1916 1917 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 1918 } 1919 1920 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 1921 const unsigned char *addr, 1922 u16 vid, struct dsa_db db) 1923 { 1924 struct ksz_device *dev = ds->priv; 1925 1926 if (!dev->dev_ops->fdb_del) 1927 return -EOPNOTSUPP; 1928 1929 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 1930 } 1931 1932 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 1933 dsa_fdb_dump_cb_t *cb, void *data) 1934 { 1935 struct ksz_device *dev = ds->priv; 1936 1937 if (!dev->dev_ops->fdb_dump) 1938 return -EOPNOTSUPP; 1939 1940 return dev->dev_ops->fdb_dump(dev, port, cb, data); 1941 } 1942 1943 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 1944 const struct switchdev_obj_port_mdb *mdb, 1945 struct dsa_db db) 1946 { 1947 struct ksz_device *dev = ds->priv; 1948 1949 if (!dev->dev_ops->mdb_add) 1950 return -EOPNOTSUPP; 1951 1952 return dev->dev_ops->mdb_add(dev, port, mdb, db); 1953 } 1954 1955 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 1956 const struct switchdev_obj_port_mdb *mdb, 1957 struct dsa_db db) 1958 { 1959 struct ksz_device *dev = ds->priv; 1960 1961 if (!dev->dev_ops->mdb_del) 1962 return -EOPNOTSUPP; 1963 1964 return dev->dev_ops->mdb_del(dev, port, mdb, db); 1965 } 1966 1967 static int ksz_enable_port(struct dsa_switch *ds, int port, 1968 struct phy_device *phy) 1969 { 1970 struct ksz_device *dev = ds->priv; 1971 1972 if (!dsa_is_user_port(ds, port)) 1973 return 0; 1974 1975 /* setup slave port */ 1976 dev->dev_ops->port_setup(dev, port, false); 1977 1978 /* port_stp_state_set() will be called after to enable the port so 1979 * there is no need to do anything. 1980 */ 1981 1982 return 0; 1983 } 1984 1985 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1986 { 1987 struct ksz_device *dev = ds->priv; 1988 struct ksz_port *p; 1989 const u16 *regs; 1990 u8 data; 1991 1992 regs = dev->info->regs; 1993 1994 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 1995 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 1996 1997 p = &dev->ports[port]; 1998 1999 switch (state) { 2000 case BR_STATE_DISABLED: 2001 data |= PORT_LEARN_DISABLE; 2002 break; 2003 case BR_STATE_LISTENING: 2004 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2005 break; 2006 case BR_STATE_LEARNING: 2007 data |= PORT_RX_ENABLE; 2008 if (!p->learning) 2009 data |= PORT_LEARN_DISABLE; 2010 break; 2011 case BR_STATE_FORWARDING: 2012 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 2013 if (!p->learning) 2014 data |= PORT_LEARN_DISABLE; 2015 break; 2016 case BR_STATE_BLOCKING: 2017 data |= PORT_LEARN_DISABLE; 2018 break; 2019 default: 2020 dev_err(ds->dev, "invalid STP state: %d\n", state); 2021 return; 2022 } 2023 2024 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 2025 2026 p->stp_state = state; 2027 2028 ksz_update_port_member(dev, port); 2029 } 2030 2031 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 2032 struct switchdev_brport_flags flags, 2033 struct netlink_ext_ack *extack) 2034 { 2035 if (flags.mask & ~BR_LEARNING) 2036 return -EINVAL; 2037 2038 return 0; 2039 } 2040 2041 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 2042 struct switchdev_brport_flags flags, 2043 struct netlink_ext_ack *extack) 2044 { 2045 struct ksz_device *dev = ds->priv; 2046 struct ksz_port *p = &dev->ports[port]; 2047 2048 if (flags.mask & BR_LEARNING) { 2049 p->learning = !!(flags.val & BR_LEARNING); 2050 2051 /* Make the change take effect immediately */ 2052 ksz_port_stp_state_set(ds, port, p->stp_state); 2053 } 2054 2055 return 0; 2056 } 2057 2058 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 2059 int port, 2060 enum dsa_tag_protocol mp) 2061 { 2062 struct ksz_device *dev = ds->priv; 2063 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 2064 2065 if (dev->chip_id == KSZ8795_CHIP_ID || 2066 dev->chip_id == KSZ8794_CHIP_ID || 2067 dev->chip_id == KSZ8765_CHIP_ID) 2068 proto = DSA_TAG_PROTO_KSZ8795; 2069 2070 if (dev->chip_id == KSZ8830_CHIP_ID || 2071 dev->chip_id == KSZ8563_CHIP_ID || 2072 dev->chip_id == KSZ9893_CHIP_ID) 2073 proto = DSA_TAG_PROTO_KSZ9893; 2074 2075 if (dev->chip_id == KSZ9477_CHIP_ID || 2076 dev->chip_id == KSZ9896_CHIP_ID || 2077 dev->chip_id == KSZ9897_CHIP_ID || 2078 dev->chip_id == KSZ9567_CHIP_ID) 2079 proto = DSA_TAG_PROTO_KSZ9477; 2080 2081 if (is_lan937x(dev)) 2082 proto = DSA_TAG_PROTO_LAN937X_VALUE; 2083 2084 return proto; 2085 } 2086 2087 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 2088 bool flag, struct netlink_ext_ack *extack) 2089 { 2090 struct ksz_device *dev = ds->priv; 2091 2092 if (!dev->dev_ops->vlan_filtering) 2093 return -EOPNOTSUPP; 2094 2095 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 2096 } 2097 2098 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 2099 const struct switchdev_obj_port_vlan *vlan, 2100 struct netlink_ext_ack *extack) 2101 { 2102 struct ksz_device *dev = ds->priv; 2103 2104 if (!dev->dev_ops->vlan_add) 2105 return -EOPNOTSUPP; 2106 2107 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 2108 } 2109 2110 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 2111 const struct switchdev_obj_port_vlan *vlan) 2112 { 2113 struct ksz_device *dev = ds->priv; 2114 2115 if (!dev->dev_ops->vlan_del) 2116 return -EOPNOTSUPP; 2117 2118 return dev->dev_ops->vlan_del(dev, port, vlan); 2119 } 2120 2121 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 2122 struct dsa_mall_mirror_tc_entry *mirror, 2123 bool ingress, struct netlink_ext_ack *extack) 2124 { 2125 struct ksz_device *dev = ds->priv; 2126 2127 if (!dev->dev_ops->mirror_add) 2128 return -EOPNOTSUPP; 2129 2130 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 2131 } 2132 2133 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 2134 struct dsa_mall_mirror_tc_entry *mirror) 2135 { 2136 struct ksz_device *dev = ds->priv; 2137 2138 if (dev->dev_ops->mirror_del) 2139 dev->dev_ops->mirror_del(dev, port, mirror); 2140 } 2141 2142 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 2143 { 2144 struct ksz_device *dev = ds->priv; 2145 2146 if (!dev->dev_ops->change_mtu) 2147 return -EOPNOTSUPP; 2148 2149 return dev->dev_ops->change_mtu(dev, port, mtu); 2150 } 2151 2152 static int ksz_max_mtu(struct dsa_switch *ds, int port) 2153 { 2154 struct ksz_device *dev = ds->priv; 2155 2156 if (!dev->dev_ops->max_mtu) 2157 return -EOPNOTSUPP; 2158 2159 return dev->dev_ops->max_mtu(dev, port); 2160 } 2161 2162 static void ksz_set_xmii(struct ksz_device *dev, int port, 2163 phy_interface_t interface) 2164 { 2165 const u8 *bitval = dev->info->xmii_ctrl1; 2166 struct ksz_port *p = &dev->ports[port]; 2167 const u16 *regs = dev->info->regs; 2168 u8 data8; 2169 2170 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2171 2172 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 2173 P_RGMII_ID_EG_ENABLE); 2174 2175 switch (interface) { 2176 case PHY_INTERFACE_MODE_MII: 2177 data8 |= bitval[P_MII_SEL]; 2178 break; 2179 case PHY_INTERFACE_MODE_RMII: 2180 data8 |= bitval[P_RMII_SEL]; 2181 break; 2182 case PHY_INTERFACE_MODE_GMII: 2183 data8 |= bitval[P_GMII_SEL]; 2184 break; 2185 case PHY_INTERFACE_MODE_RGMII: 2186 case PHY_INTERFACE_MODE_RGMII_ID: 2187 case PHY_INTERFACE_MODE_RGMII_TXID: 2188 case PHY_INTERFACE_MODE_RGMII_RXID: 2189 data8 |= bitval[P_RGMII_SEL]; 2190 /* On KSZ9893, disable RGMII in-band status support */ 2191 if (dev->chip_id == KSZ9893_CHIP_ID || 2192 dev->chip_id == KSZ8563_CHIP_ID) 2193 data8 &= ~P_MII_MAC_MODE; 2194 break; 2195 default: 2196 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 2197 phy_modes(interface), port); 2198 return; 2199 } 2200 2201 if (p->rgmii_tx_val) 2202 data8 |= P_RGMII_ID_EG_ENABLE; 2203 2204 if (p->rgmii_rx_val) 2205 data8 |= P_RGMII_ID_IG_ENABLE; 2206 2207 /* Write the updated value */ 2208 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2209 } 2210 2211 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 2212 { 2213 const u8 *bitval = dev->info->xmii_ctrl1; 2214 const u16 *regs = dev->info->regs; 2215 phy_interface_t interface; 2216 u8 data8; 2217 u8 val; 2218 2219 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2220 2221 val = FIELD_GET(P_MII_SEL_M, data8); 2222 2223 if (val == bitval[P_MII_SEL]) { 2224 if (gbit) 2225 interface = PHY_INTERFACE_MODE_GMII; 2226 else 2227 interface = PHY_INTERFACE_MODE_MII; 2228 } else if (val == bitval[P_RMII_SEL]) { 2229 interface = PHY_INTERFACE_MODE_RGMII; 2230 } else { 2231 interface = PHY_INTERFACE_MODE_RGMII; 2232 if (data8 & P_RGMII_ID_EG_ENABLE) 2233 interface = PHY_INTERFACE_MODE_RGMII_TXID; 2234 if (data8 & P_RGMII_ID_IG_ENABLE) { 2235 interface = PHY_INTERFACE_MODE_RGMII_RXID; 2236 if (data8 & P_RGMII_ID_EG_ENABLE) 2237 interface = PHY_INTERFACE_MODE_RGMII_ID; 2238 } 2239 } 2240 2241 return interface; 2242 } 2243 2244 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, 2245 unsigned int mode, 2246 const struct phylink_link_state *state) 2247 { 2248 struct ksz_device *dev = ds->priv; 2249 2250 if (ksz_is_ksz88x3(dev)) 2251 return; 2252 2253 /* Internal PHYs */ 2254 if (dev->info->internal_phy[port]) 2255 return; 2256 2257 if (phylink_autoneg_inband(mode)) { 2258 dev_err(dev->dev, "In-band AN not supported!\n"); 2259 return; 2260 } 2261 2262 ksz_set_xmii(dev, port, state->interface); 2263 2264 if (dev->dev_ops->phylink_mac_config) 2265 dev->dev_ops->phylink_mac_config(dev, port, mode, state); 2266 2267 if (dev->dev_ops->setup_rgmii_delay) 2268 dev->dev_ops->setup_rgmii_delay(dev, port); 2269 } 2270 2271 bool ksz_get_gbit(struct ksz_device *dev, int port) 2272 { 2273 const u8 *bitval = dev->info->xmii_ctrl1; 2274 const u16 *regs = dev->info->regs; 2275 bool gbit = false; 2276 u8 data8; 2277 bool val; 2278 2279 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2280 2281 val = FIELD_GET(P_GMII_1GBIT_M, data8); 2282 2283 if (val == bitval[P_GMII_1GBIT]) 2284 gbit = true; 2285 2286 return gbit; 2287 } 2288 2289 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 2290 { 2291 const u8 *bitval = dev->info->xmii_ctrl1; 2292 const u16 *regs = dev->info->regs; 2293 u8 data8; 2294 2295 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2296 2297 data8 &= ~P_GMII_1GBIT_M; 2298 2299 if (gbit) 2300 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 2301 else 2302 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 2303 2304 /* Write the updated value */ 2305 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2306 } 2307 2308 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 2309 { 2310 const u8 *bitval = dev->info->xmii_ctrl0; 2311 const u16 *regs = dev->info->regs; 2312 u8 data8; 2313 2314 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 2315 2316 data8 &= ~P_MII_100MBIT_M; 2317 2318 if (speed == SPEED_100) 2319 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 2320 else 2321 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 2322 2323 /* Write the updated value */ 2324 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 2325 } 2326 2327 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 2328 { 2329 if (speed == SPEED_1000) 2330 ksz_set_gbit(dev, port, true); 2331 else 2332 ksz_set_gbit(dev, port, false); 2333 2334 if (speed == SPEED_100 || speed == SPEED_10) 2335 ksz_set_100_10mbit(dev, port, speed); 2336 } 2337 2338 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 2339 bool tx_pause, bool rx_pause) 2340 { 2341 const u8 *bitval = dev->info->xmii_ctrl0; 2342 const u32 *masks = dev->info->masks; 2343 const u16 *regs = dev->info->regs; 2344 u8 mask; 2345 u8 val; 2346 2347 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 2348 masks[P_MII_RX_FLOW_CTRL]; 2349 2350 if (duplex == DUPLEX_FULL) 2351 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 2352 else 2353 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 2354 2355 if (tx_pause) 2356 val |= masks[P_MII_TX_FLOW_CTRL]; 2357 2358 if (rx_pause) 2359 val |= masks[P_MII_RX_FLOW_CTRL]; 2360 2361 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 2362 } 2363 2364 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 2365 unsigned int mode, 2366 phy_interface_t interface, 2367 struct phy_device *phydev, int speed, 2368 int duplex, bool tx_pause, 2369 bool rx_pause) 2370 { 2371 struct ksz_port *p; 2372 2373 p = &dev->ports[port]; 2374 2375 /* Internal PHYs */ 2376 if (dev->info->internal_phy[port]) 2377 return; 2378 2379 p->phydev.speed = speed; 2380 2381 ksz_port_set_xmii_speed(dev, port, speed); 2382 2383 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 2384 } 2385 2386 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, 2387 unsigned int mode, 2388 phy_interface_t interface, 2389 struct phy_device *phydev, int speed, 2390 int duplex, bool tx_pause, bool rx_pause) 2391 { 2392 struct ksz_device *dev = ds->priv; 2393 2394 if (dev->dev_ops->phylink_mac_link_up) 2395 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface, 2396 phydev, speed, duplex, 2397 tx_pause, rx_pause); 2398 } 2399 2400 static int ksz_switch_detect(struct ksz_device *dev) 2401 { 2402 u8 id1, id2, id4; 2403 u16 id16; 2404 u32 id32; 2405 int ret; 2406 2407 /* read chip id */ 2408 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 2409 if (ret) 2410 return ret; 2411 2412 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 2413 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 2414 2415 switch (id1) { 2416 case KSZ87_FAMILY_ID: 2417 if (id2 == KSZ87_CHIP_ID_95) { 2418 u8 val; 2419 2420 dev->chip_id = KSZ8795_CHIP_ID; 2421 2422 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 2423 if (val & KSZ8_PORT_FIBER_MODE) 2424 dev->chip_id = KSZ8765_CHIP_ID; 2425 } else if (id2 == KSZ87_CHIP_ID_94) { 2426 dev->chip_id = KSZ8794_CHIP_ID; 2427 } else { 2428 return -ENODEV; 2429 } 2430 break; 2431 case KSZ88_FAMILY_ID: 2432 if (id2 == KSZ88_CHIP_ID_63) 2433 dev->chip_id = KSZ8830_CHIP_ID; 2434 else 2435 return -ENODEV; 2436 break; 2437 default: 2438 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 2439 if (ret) 2440 return ret; 2441 2442 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 2443 id32 &= ~0xFF; 2444 2445 switch (id32) { 2446 case KSZ9477_CHIP_ID: 2447 case KSZ9896_CHIP_ID: 2448 case KSZ9897_CHIP_ID: 2449 case KSZ9567_CHIP_ID: 2450 case LAN9370_CHIP_ID: 2451 case LAN9371_CHIP_ID: 2452 case LAN9372_CHIP_ID: 2453 case LAN9373_CHIP_ID: 2454 case LAN9374_CHIP_ID: 2455 dev->chip_id = id32; 2456 break; 2457 case KSZ9893_CHIP_ID: 2458 ret = ksz_read8(dev, REG_CHIP_ID4, 2459 &id4); 2460 if (ret) 2461 return ret; 2462 2463 if (id4 == SKU_ID_KSZ8563) 2464 dev->chip_id = KSZ8563_CHIP_ID; 2465 else 2466 dev->chip_id = KSZ9893_CHIP_ID; 2467 2468 break; 2469 default: 2470 dev_err(dev->dev, 2471 "unsupported switch detected %x)\n", id32); 2472 return -ENODEV; 2473 } 2474 } 2475 return 0; 2476 } 2477 2478 static const struct dsa_switch_ops ksz_switch_ops = { 2479 .get_tag_protocol = ksz_get_tag_protocol, 2480 .get_phy_flags = ksz_get_phy_flags, 2481 .setup = ksz_setup, 2482 .teardown = ksz_teardown, 2483 .phy_read = ksz_phy_read16, 2484 .phy_write = ksz_phy_write16, 2485 .phylink_get_caps = ksz_phylink_get_caps, 2486 .phylink_mac_config = ksz_phylink_mac_config, 2487 .phylink_mac_link_up = ksz_phylink_mac_link_up, 2488 .phylink_mac_link_down = ksz_mac_link_down, 2489 .port_enable = ksz_enable_port, 2490 .set_ageing_time = ksz_set_ageing_time, 2491 .get_strings = ksz_get_strings, 2492 .get_ethtool_stats = ksz_get_ethtool_stats, 2493 .get_sset_count = ksz_sset_count, 2494 .port_bridge_join = ksz_port_bridge_join, 2495 .port_bridge_leave = ksz_port_bridge_leave, 2496 .port_stp_state_set = ksz_port_stp_state_set, 2497 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 2498 .port_bridge_flags = ksz_port_bridge_flags, 2499 .port_fast_age = ksz_port_fast_age, 2500 .port_vlan_filtering = ksz_port_vlan_filtering, 2501 .port_vlan_add = ksz_port_vlan_add, 2502 .port_vlan_del = ksz_port_vlan_del, 2503 .port_fdb_dump = ksz_port_fdb_dump, 2504 .port_fdb_add = ksz_port_fdb_add, 2505 .port_fdb_del = ksz_port_fdb_del, 2506 .port_mdb_add = ksz_port_mdb_add, 2507 .port_mdb_del = ksz_port_mdb_del, 2508 .port_mirror_add = ksz_port_mirror_add, 2509 .port_mirror_del = ksz_port_mirror_del, 2510 .get_stats64 = ksz_get_stats64, 2511 .get_pause_stats = ksz_get_pause_stats, 2512 .port_change_mtu = ksz_change_mtu, 2513 .port_max_mtu = ksz_max_mtu, 2514 }; 2515 2516 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 2517 { 2518 struct dsa_switch *ds; 2519 struct ksz_device *swdev; 2520 2521 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2522 if (!ds) 2523 return NULL; 2524 2525 ds->dev = base; 2526 ds->num_ports = DSA_MAX_PORTS; 2527 ds->ops = &ksz_switch_ops; 2528 2529 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 2530 if (!swdev) 2531 return NULL; 2532 2533 ds->priv = swdev; 2534 swdev->dev = base; 2535 2536 swdev->ds = ds; 2537 swdev->priv = priv; 2538 2539 return swdev; 2540 } 2541 EXPORT_SYMBOL(ksz_switch_alloc); 2542 2543 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 2544 struct device_node *port_dn) 2545 { 2546 phy_interface_t phy_mode = dev->ports[port_num].interface; 2547 int rx_delay = -1, tx_delay = -1; 2548 2549 if (!phy_interface_mode_is_rgmii(phy_mode)) 2550 return; 2551 2552 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 2553 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 2554 2555 if (rx_delay == -1 && tx_delay == -1) { 2556 dev_warn(dev->dev, 2557 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 2558 "please update device tree to specify \"rx-internal-delay-ps\" and " 2559 "\"tx-internal-delay-ps\"", 2560 port_num); 2561 2562 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 2563 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 2564 rx_delay = 2000; 2565 2566 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 2567 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 2568 tx_delay = 2000; 2569 } 2570 2571 if (rx_delay < 0) 2572 rx_delay = 0; 2573 if (tx_delay < 0) 2574 tx_delay = 0; 2575 2576 dev->ports[port_num].rgmii_rx_val = rx_delay; 2577 dev->ports[port_num].rgmii_tx_val = tx_delay; 2578 } 2579 2580 int ksz_switch_register(struct ksz_device *dev) 2581 { 2582 const struct ksz_chip_data *info; 2583 struct device_node *port, *ports; 2584 phy_interface_t interface; 2585 unsigned int port_num; 2586 int ret; 2587 int i; 2588 2589 if (dev->pdata) 2590 dev->chip_id = dev->pdata->chip_id; 2591 2592 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 2593 GPIOD_OUT_LOW); 2594 if (IS_ERR(dev->reset_gpio)) 2595 return PTR_ERR(dev->reset_gpio); 2596 2597 if (dev->reset_gpio) { 2598 gpiod_set_value_cansleep(dev->reset_gpio, 1); 2599 usleep_range(10000, 12000); 2600 gpiod_set_value_cansleep(dev->reset_gpio, 0); 2601 msleep(100); 2602 } 2603 2604 mutex_init(&dev->dev_mutex); 2605 mutex_init(&dev->regmap_mutex); 2606 mutex_init(&dev->alu_mutex); 2607 mutex_init(&dev->vlan_mutex); 2608 2609 ret = ksz_switch_detect(dev); 2610 if (ret) 2611 return ret; 2612 2613 info = ksz_lookup_info(dev->chip_id); 2614 if (!info) 2615 return -ENODEV; 2616 2617 /* Update the compatible info with the probed one */ 2618 dev->info = info; 2619 2620 dev_info(dev->dev, "found switch: %s, rev %i\n", 2621 dev->info->dev_name, dev->chip_rev); 2622 2623 ret = ksz_check_device_id(dev); 2624 if (ret) 2625 return ret; 2626 2627 dev->dev_ops = dev->info->ops; 2628 2629 ret = dev->dev_ops->init(dev); 2630 if (ret) 2631 return ret; 2632 2633 dev->ports = devm_kzalloc(dev->dev, 2634 dev->info->port_cnt * sizeof(struct ksz_port), 2635 GFP_KERNEL); 2636 if (!dev->ports) 2637 return -ENOMEM; 2638 2639 for (i = 0; i < dev->info->port_cnt; i++) { 2640 spin_lock_init(&dev->ports[i].mib.stats64_lock); 2641 mutex_init(&dev->ports[i].mib.cnt_mutex); 2642 dev->ports[i].mib.counters = 2643 devm_kzalloc(dev->dev, 2644 sizeof(u64) * (dev->info->mib_cnt + 1), 2645 GFP_KERNEL); 2646 if (!dev->ports[i].mib.counters) 2647 return -ENOMEM; 2648 2649 dev->ports[i].ksz_dev = dev; 2650 dev->ports[i].num = i; 2651 } 2652 2653 /* set the real number of ports */ 2654 dev->ds->num_ports = dev->info->port_cnt; 2655 2656 /* Host port interface will be self detected, or specifically set in 2657 * device tree. 2658 */ 2659 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 2660 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 2661 if (dev->dev->of_node) { 2662 ret = of_get_phy_mode(dev->dev->of_node, &interface); 2663 if (ret == 0) 2664 dev->compat_interface = interface; 2665 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 2666 if (!ports) 2667 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 2668 if (ports) { 2669 for_each_available_child_of_node(ports, port) { 2670 if (of_property_read_u32(port, "reg", 2671 &port_num)) 2672 continue; 2673 if (!(dev->port_mask & BIT(port_num))) { 2674 of_node_put(port); 2675 of_node_put(ports); 2676 return -EINVAL; 2677 } 2678 of_get_phy_mode(port, 2679 &dev->ports[port_num].interface); 2680 2681 ksz_parse_rgmii_delay(dev, port_num, port); 2682 } 2683 of_node_put(ports); 2684 } 2685 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 2686 "microchip,synclko-125"); 2687 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 2688 "microchip,synclko-disable"); 2689 if (dev->synclko_125 && dev->synclko_disable) { 2690 dev_err(dev->dev, "inconsistent synclko settings\n"); 2691 return -EINVAL; 2692 } 2693 } 2694 2695 ret = dsa_register_switch(dev->ds); 2696 if (ret) { 2697 dev->dev_ops->exit(dev); 2698 return ret; 2699 } 2700 2701 /* Read MIB counters every 30 seconds to avoid overflow. */ 2702 dev->mib_read_interval = msecs_to_jiffies(5000); 2703 2704 /* Start the MIB timer. */ 2705 schedule_delayed_work(&dev->mib_read, 0); 2706 2707 return ret; 2708 } 2709 EXPORT_SYMBOL(ksz_switch_register); 2710 2711 void ksz_switch_remove(struct ksz_device *dev) 2712 { 2713 /* timer started */ 2714 if (dev->mib_read_interval) { 2715 dev->mib_read_interval = 0; 2716 cancel_delayed_work_sync(&dev->mib_read); 2717 } 2718 2719 dev->dev_ops->exit(dev); 2720 dsa_unregister_switch(dev->ds); 2721 2722 if (dev->reset_gpio) 2723 gpiod_set_value_cansleep(dev->reset_gpio, 1); 2724 2725 } 2726 EXPORT_SYMBOL(ksz_switch_remove); 2727 2728 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 2729 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 2730 MODULE_LICENSE("GPL"); 2731