1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2025 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/if_hsr.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/of.h> 23 #include <linux/of_mdio.h> 24 #include <linux/of_net.h> 25 #include <linux/micrel_phy.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <net/dsa.h> 28 #include <net/ieee8021q.h> 29 #include <net/pkt_cls.h> 30 #include <net/switchdev.h> 31 32 #include "ksz_common.h" 33 #include "ksz_dcb.h" 34 #include "ksz_ptp.h" 35 #include "ksz8.h" 36 #include "ksz9477.h" 37 #include "lan937x.h" 38 39 #define MIB_COUNTER_NUM 0x20 40 41 struct ksz_stats_raw { 42 u64 rx_hi; 43 u64 rx_undersize; 44 u64 rx_fragments; 45 u64 rx_oversize; 46 u64 rx_jabbers; 47 u64 rx_symbol_err; 48 u64 rx_crc_err; 49 u64 rx_align_err; 50 u64 rx_mac_ctrl; 51 u64 rx_pause; 52 u64 rx_bcast; 53 u64 rx_mcast; 54 u64 rx_ucast; 55 u64 rx_64_or_less; 56 u64 rx_65_127; 57 u64 rx_128_255; 58 u64 rx_256_511; 59 u64 rx_512_1023; 60 u64 rx_1024_1522; 61 u64 rx_1523_2000; 62 u64 rx_2001; 63 u64 tx_hi; 64 u64 tx_late_col; 65 u64 tx_pause; 66 u64 tx_bcast; 67 u64 tx_mcast; 68 u64 tx_ucast; 69 u64 tx_deferred; 70 u64 tx_total_col; 71 u64 tx_exc_col; 72 u64 tx_single_col; 73 u64 tx_mult_col; 74 u64 rx_total; 75 u64 tx_total; 76 u64 rx_discards; 77 u64 tx_discards; 78 }; 79 80 struct ksz88xx_stats_raw { 81 u64 rx; 82 u64 rx_hi; 83 u64 rx_undersize; 84 u64 rx_fragments; 85 u64 rx_oversize; 86 u64 rx_jabbers; 87 u64 rx_symbol_err; 88 u64 rx_crc_err; 89 u64 rx_align_err; 90 u64 rx_mac_ctrl; 91 u64 rx_pause; 92 u64 rx_bcast; 93 u64 rx_mcast; 94 u64 rx_ucast; 95 u64 rx_64_or_less; 96 u64 rx_65_127; 97 u64 rx_128_255; 98 u64 rx_256_511; 99 u64 rx_512_1023; 100 u64 rx_1024_1522; 101 u64 tx; 102 u64 tx_hi; 103 u64 tx_late_col; 104 u64 tx_pause; 105 u64 tx_bcast; 106 u64 tx_mcast; 107 u64 tx_ucast; 108 u64 tx_deferred; 109 u64 tx_total_col; 110 u64 tx_exc_col; 111 u64 tx_single_col; 112 u64 tx_mult_col; 113 u64 rx_discards; 114 u64 tx_discards; 115 }; 116 117 static const struct ksz_mib_names ksz88xx_mib_names[] = { 118 { 0x00, "rx" }, 119 { 0x01, "rx_hi" }, 120 { 0x02, "rx_undersize" }, 121 { 0x03, "rx_fragments" }, 122 { 0x04, "rx_oversize" }, 123 { 0x05, "rx_jabbers" }, 124 { 0x06, "rx_symbol_err" }, 125 { 0x07, "rx_crc_err" }, 126 { 0x08, "rx_align_err" }, 127 { 0x09, "rx_mac_ctrl" }, 128 { 0x0a, "rx_pause" }, 129 { 0x0b, "rx_bcast" }, 130 { 0x0c, "rx_mcast" }, 131 { 0x0d, "rx_ucast" }, 132 { 0x0e, "rx_64_or_less" }, 133 { 0x0f, "rx_65_127" }, 134 { 0x10, "rx_128_255" }, 135 { 0x11, "rx_256_511" }, 136 { 0x12, "rx_512_1023" }, 137 { 0x13, "rx_1024_1522" }, 138 { 0x14, "tx" }, 139 { 0x15, "tx_hi" }, 140 { 0x16, "tx_late_col" }, 141 { 0x17, "tx_pause" }, 142 { 0x18, "tx_bcast" }, 143 { 0x19, "tx_mcast" }, 144 { 0x1a, "tx_ucast" }, 145 { 0x1b, "tx_deferred" }, 146 { 0x1c, "tx_total_col" }, 147 { 0x1d, "tx_exc_col" }, 148 { 0x1e, "tx_single_col" }, 149 { 0x1f, "tx_mult_col" }, 150 { 0x100, "rx_discards" }, 151 { 0x101, "tx_discards" }, 152 }; 153 154 static const struct ksz_mib_names ksz9477_mib_names[] = { 155 { 0x00, "rx_hi" }, 156 { 0x01, "rx_undersize" }, 157 { 0x02, "rx_fragments" }, 158 { 0x03, "rx_oversize" }, 159 { 0x04, "rx_jabbers" }, 160 { 0x05, "rx_symbol_err" }, 161 { 0x06, "rx_crc_err" }, 162 { 0x07, "rx_align_err" }, 163 { 0x08, "rx_mac_ctrl" }, 164 { 0x09, "rx_pause" }, 165 { 0x0A, "rx_bcast" }, 166 { 0x0B, "rx_mcast" }, 167 { 0x0C, "rx_ucast" }, 168 { 0x0D, "rx_64_or_less" }, 169 { 0x0E, "rx_65_127" }, 170 { 0x0F, "rx_128_255" }, 171 { 0x10, "rx_256_511" }, 172 { 0x11, "rx_512_1023" }, 173 { 0x12, "rx_1024_1522" }, 174 { 0x13, "rx_1523_2000" }, 175 { 0x14, "rx_2001" }, 176 { 0x15, "tx_hi" }, 177 { 0x16, "tx_late_col" }, 178 { 0x17, "tx_pause" }, 179 { 0x18, "tx_bcast" }, 180 { 0x19, "tx_mcast" }, 181 { 0x1A, "tx_ucast" }, 182 { 0x1B, "tx_deferred" }, 183 { 0x1C, "tx_total_col" }, 184 { 0x1D, "tx_exc_col" }, 185 { 0x1E, "tx_single_col" }, 186 { 0x1F, "tx_mult_col" }, 187 { 0x80, "rx_total" }, 188 { 0x81, "tx_total" }, 189 { 0x82, "rx_discards" }, 190 { 0x83, "tx_discards" }, 191 }; 192 193 struct ksz_driver_strength_prop { 194 const char *name; 195 int offset; 196 int value; 197 }; 198 199 enum ksz_driver_strength_type { 200 KSZ_DRIVER_STRENGTH_HI, 201 KSZ_DRIVER_STRENGTH_LO, 202 KSZ_DRIVER_STRENGTH_IO, 203 }; 204 205 /** 206 * struct ksz_drive_strength - drive strength mapping 207 * @reg_val: register value 208 * @microamp: microamp value 209 */ 210 struct ksz_drive_strength { 211 u32 reg_val; 212 u32 microamp; 213 }; 214 215 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants 216 * 217 * This values are not documented in KSZ9477 variants but confirmed by 218 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893 219 * and KSZ8563 are using same register (drive strength) settings like KSZ8795. 220 * 221 * Documentation in KSZ8795CLX provides more information with some 222 * recommendations: 223 * - for high speed signals 224 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using 225 * 2.5V or 3.3V VDDIO. 226 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with 227 * using 1.8V VDDIO. 228 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V 229 * or 3.3V VDDIO. 230 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO. 231 * 5. In same interface, the heavy loading should use higher one of the 232 * drive current strength. 233 * - for low speed signals 234 * 1. 3.3V VDDIO, use either 4 mA or 8 mA. 235 * 2. 2.5V VDDIO, use either 8 mA or 12 mA. 236 * 3. 1.8V VDDIO, use either 12 mA or 16 mA. 237 * 4. If it is heavy loading, can use higher drive current strength. 238 */ 239 static const struct ksz_drive_strength ksz9477_drive_strengths[] = { 240 { SW_DRIVE_STRENGTH_2MA, 2000 }, 241 { SW_DRIVE_STRENGTH_4MA, 4000 }, 242 { SW_DRIVE_STRENGTH_8MA, 8000 }, 243 { SW_DRIVE_STRENGTH_12MA, 12000 }, 244 { SW_DRIVE_STRENGTH_16MA, 16000 }, 245 { SW_DRIVE_STRENGTH_20MA, 20000 }, 246 { SW_DRIVE_STRENGTH_24MA, 24000 }, 247 { SW_DRIVE_STRENGTH_28MA, 28000 }, 248 }; 249 250 /* ksz88x3_drive_strengths - Drive strength mapping for KSZ8863, KSZ8873, .. 251 * variants. 252 * This values are documented in KSZ8873 and KSZ8863 datasheets. 253 */ 254 static const struct ksz_drive_strength ksz88x3_drive_strengths[] = { 255 { 0, 8000 }, 256 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 }, 257 }; 258 259 /** 260 * ksz_phylink_mac_disable_tx_lpi() - Callback to signal LPI support (Dummy) 261 * @config: phylink config structure 262 * 263 * This function is a dummy handler. See ksz_phylink_mac_enable_tx_lpi() for 264 * a detailed explanation of EEE/LPI handling in KSZ switches. 265 */ 266 void ksz_phylink_mac_disable_tx_lpi(struct phylink_config *config) 267 { 268 } 269 270 /** 271 * ksz_phylink_mac_enable_tx_lpi() - Callback to signal LPI support (Dummy) 272 * @config: phylink config structure 273 * @timer: timer value before entering LPI (unused) 274 * @tx_clock_stop: whether to stop the TX clock in LPI mode (unused) 275 * 276 * This function signals to phylink that the driver architecture supports 277 * LPI management, enabling phylink to control EEE advertisement during 278 * negotiation according to IEEE Std 802.3 (Clause 78). 279 * 280 * Hardware Management of EEE/LPI State: 281 * For KSZ switch ports with integrated PHYs (e.g., KSZ9893R ports 1-2), 282 * observation and testing suggest that the actual EEE / Low Power Idle (LPI) 283 * state transitions are managed autonomously by the hardware based on 284 * the auto-negotiation results. (Note: While the datasheet describes EEE 285 * operation based on negotiation, it doesn't explicitly detail the internal 286 * MAC/PHY interaction, so autonomous hardware management of the MAC state 287 * for LPI is inferred from observed behavior). 288 * This hardware control, consistent with the switch's ability to operate 289 * autonomously via strapping, means MAC-level software intervention is not 290 * required or exposed for managing the LPI state once EEE is negotiated. 291 * (Ref: KSZ9893R Data Sheet DS00002420D, primarily Section 4.7.5 explaining 292 * EEE, also Sections 4.1.7 on Auto-Negotiation and 3.2.1 on Configuration 293 * Straps). 294 * 295 * Additionally, ports configured as MAC interfaces (e.g., KSZ9893R port 3) 296 * lack documented MAC-level LPI control. 297 * 298 * Therefore, this callback performs no action and serves primarily to inform 299 * phylink of LPI awareness and to document the inferred hardware behavior. 300 * 301 * Returns: 0 (Always success) 302 */ 303 int ksz_phylink_mac_enable_tx_lpi(struct phylink_config *config, 304 u32 timer, bool tx_clock_stop) 305 { 306 return 0; 307 } 308 309 static const u16 ksz8463_regs[] = { 310 [REG_SW_MAC_ADDR] = 0x10, 311 [REG_IND_CTRL_0] = 0x30, 312 [REG_IND_DATA_8] = 0x26, 313 [REG_IND_DATA_CHECK] = 0x26, 314 [REG_IND_DATA_HI] = 0x28, 315 [REG_IND_DATA_LO] = 0x2C, 316 [REG_IND_MIB_CHECK] = 0x2F, 317 [P_FORCE_CTRL] = 0x0C, 318 [P_LINK_STATUS] = 0x0E, 319 [P_LOCAL_CTRL] = 0x0C, 320 [P_NEG_RESTART_CTRL] = 0x0D, 321 [P_REMOTE_STATUS] = 0x0E, 322 [P_SPEED_STATUS] = 0x0F, 323 [S_TAIL_TAG_CTRL] = 0xAD, 324 [P_STP_CTRL] = 0x6F, 325 [S_START_CTRL] = 0x01, 326 [S_BROADCAST_CTRL] = 0x06, 327 [S_MULTICAST_CTRL] = 0x04, 328 [PTP_CLK_CTRL] = 0x0600, 329 [PTP_RTC_NANOSEC] = 0x0604, 330 [PTP_RTC_SEC] = 0x0608, 331 [PTP_RTC_SUB_NANOSEC] = 0x060C, 332 [PTP_SUBNANOSEC_RATE] = 0x0610, 333 [PTP_MSG_CONF1] = 0x0620, 334 }; 335 336 static const u32 ksz8463_masks[] = { 337 [PORT_802_1P_REMAPPING] = BIT(3), 338 [SW_TAIL_TAG_ENABLE] = BIT(0), 339 [MIB_COUNTER_OVERFLOW] = BIT(7), 340 [MIB_COUNTER_VALID] = BIT(6), 341 [VLAN_TABLE_FID] = GENMASK(15, 12), 342 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 343 [VLAN_TABLE_VALID] = BIT(19), 344 [STATIC_MAC_TABLE_VALID] = BIT(19), 345 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 346 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 347 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 348 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 349 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 350 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 351 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 352 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 353 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 354 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 355 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 356 }; 357 358 static u8 ksz8463_shifts[] = { 359 [VLAN_TABLE_MEMBERSHIP_S] = 16, 360 [STATIC_MAC_FWD_PORTS] = 16, 361 [STATIC_MAC_FID] = 22, 362 [DYNAMIC_MAC_ENTRIES_H] = 8, 363 [DYNAMIC_MAC_ENTRIES] = 24, 364 [DYNAMIC_MAC_FID] = 16, 365 [DYNAMIC_MAC_TIMESTAMP] = 22, 366 [DYNAMIC_MAC_SRC_PORT] = 20, 367 }; 368 369 static const u16 ksz8795_regs[] = { 370 [REG_SW_MAC_ADDR] = 0x68, 371 [REG_IND_CTRL_0] = 0x6E, 372 [REG_IND_DATA_8] = 0x70, 373 [REG_IND_DATA_CHECK] = 0x72, 374 [REG_IND_DATA_HI] = 0x71, 375 [REG_IND_DATA_LO] = 0x75, 376 [REG_IND_MIB_CHECK] = 0x74, 377 [REG_IND_BYTE] = 0xA0, 378 [P_FORCE_CTRL] = 0x0C, 379 [P_LINK_STATUS] = 0x0E, 380 [P_LOCAL_CTRL] = 0x07, 381 [P_NEG_RESTART_CTRL] = 0x0D, 382 [P_REMOTE_STATUS] = 0x08, 383 [P_SPEED_STATUS] = 0x09, 384 [S_TAIL_TAG_CTRL] = 0x0C, 385 [P_STP_CTRL] = 0x02, 386 [S_START_CTRL] = 0x01, 387 [S_BROADCAST_CTRL] = 0x06, 388 [S_MULTICAST_CTRL] = 0x04, 389 [P_XMII_CTRL_0] = 0x06, 390 [P_XMII_CTRL_1] = 0x06, 391 [REG_SW_PME_CTRL] = 0x8003, 392 [REG_PORT_PME_STATUS] = 0x8003, 393 [REG_PORT_PME_CTRL] = 0x8007, 394 }; 395 396 static const u32 ksz8795_masks[] = { 397 [PORT_802_1P_REMAPPING] = BIT(7), 398 [SW_TAIL_TAG_ENABLE] = BIT(1), 399 [MIB_COUNTER_OVERFLOW] = BIT(6), 400 [MIB_COUNTER_VALID] = BIT(5), 401 [VLAN_TABLE_FID] = GENMASK(6, 0), 402 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 403 [VLAN_TABLE_VALID] = BIT(12), 404 [STATIC_MAC_TABLE_VALID] = BIT(21), 405 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 406 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 407 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 408 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 409 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 410 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 411 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 412 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 413 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 414 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 415 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 416 [P_MII_TX_FLOW_CTRL] = BIT(5), 417 [P_MII_RX_FLOW_CTRL] = BIT(5), 418 }; 419 420 static const u8 ksz8795_xmii_ctrl0[] = { 421 [P_MII_100MBIT] = 0, 422 [P_MII_10MBIT] = 1, 423 [P_MII_FULL_DUPLEX] = 0, 424 [P_MII_HALF_DUPLEX] = 1, 425 }; 426 427 static const u8 ksz8795_xmii_ctrl1[] = { 428 [P_RGMII_SEL] = 3, 429 [P_GMII_SEL] = 2, 430 [P_RMII_SEL] = 1, 431 [P_MII_SEL] = 0, 432 [P_GMII_1GBIT] = 1, 433 [P_GMII_NOT_1GBIT] = 0, 434 }; 435 436 static const u8 ksz8795_shifts[] = { 437 [VLAN_TABLE_MEMBERSHIP_S] = 7, 438 [VLAN_TABLE] = 16, 439 [STATIC_MAC_FWD_PORTS] = 16, 440 [STATIC_MAC_FID] = 24, 441 [DYNAMIC_MAC_ENTRIES_H] = 3, 442 [DYNAMIC_MAC_ENTRIES] = 29, 443 [DYNAMIC_MAC_FID] = 16, 444 [DYNAMIC_MAC_TIMESTAMP] = 27, 445 [DYNAMIC_MAC_SRC_PORT] = 24, 446 }; 447 448 static const u16 ksz8863_regs[] = { 449 [REG_SW_MAC_ADDR] = 0x70, 450 [REG_IND_CTRL_0] = 0x79, 451 [REG_IND_DATA_8] = 0x7B, 452 [REG_IND_DATA_CHECK] = 0x7B, 453 [REG_IND_DATA_HI] = 0x7C, 454 [REG_IND_DATA_LO] = 0x80, 455 [REG_IND_MIB_CHECK] = 0x80, 456 [P_FORCE_CTRL] = 0x0C, 457 [P_LINK_STATUS] = 0x0E, 458 [P_LOCAL_CTRL] = 0x0C, 459 [P_NEG_RESTART_CTRL] = 0x0D, 460 [P_REMOTE_STATUS] = 0x0E, 461 [P_SPEED_STATUS] = 0x0F, 462 [S_TAIL_TAG_CTRL] = 0x03, 463 [P_STP_CTRL] = 0x02, 464 [S_START_CTRL] = 0x01, 465 [S_BROADCAST_CTRL] = 0x06, 466 [S_MULTICAST_CTRL] = 0x04, 467 }; 468 469 static const u32 ksz8863_masks[] = { 470 [PORT_802_1P_REMAPPING] = BIT(3), 471 [SW_TAIL_TAG_ENABLE] = BIT(6), 472 [MIB_COUNTER_OVERFLOW] = BIT(7), 473 [MIB_COUNTER_VALID] = BIT(6), 474 [VLAN_TABLE_FID] = GENMASK(15, 12), 475 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 476 [VLAN_TABLE_VALID] = BIT(19), 477 [STATIC_MAC_TABLE_VALID] = BIT(19), 478 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 479 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 480 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 481 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 482 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 483 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 484 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 485 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 486 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 487 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 488 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 489 }; 490 491 static u8 ksz8863_shifts[] = { 492 [VLAN_TABLE_MEMBERSHIP_S] = 16, 493 [STATIC_MAC_FWD_PORTS] = 16, 494 [STATIC_MAC_FID] = 22, 495 [DYNAMIC_MAC_ENTRIES_H] = 8, 496 [DYNAMIC_MAC_ENTRIES] = 24, 497 [DYNAMIC_MAC_FID] = 16, 498 [DYNAMIC_MAC_TIMESTAMP] = 22, 499 [DYNAMIC_MAC_SRC_PORT] = 20, 500 }; 501 502 static const u16 ksz8895_regs[] = { 503 [REG_SW_MAC_ADDR] = 0x68, 504 [REG_IND_CTRL_0] = 0x6E, 505 [REG_IND_DATA_8] = 0x70, 506 [REG_IND_DATA_CHECK] = 0x72, 507 [REG_IND_DATA_HI] = 0x71, 508 [REG_IND_DATA_LO] = 0x75, 509 [REG_IND_MIB_CHECK] = 0x75, 510 [P_FORCE_CTRL] = 0x0C, 511 [P_LINK_STATUS] = 0x0E, 512 [P_LOCAL_CTRL] = 0x0C, 513 [P_NEG_RESTART_CTRL] = 0x0D, 514 [P_REMOTE_STATUS] = 0x0E, 515 [P_SPEED_STATUS] = 0x09, 516 [S_TAIL_TAG_CTRL] = 0x0C, 517 [P_STP_CTRL] = 0x02, 518 [S_START_CTRL] = 0x01, 519 [S_BROADCAST_CTRL] = 0x06, 520 [S_MULTICAST_CTRL] = 0x04, 521 }; 522 523 static const u32 ksz8895_masks[] = { 524 [PORT_802_1P_REMAPPING] = BIT(7), 525 [SW_TAIL_TAG_ENABLE] = BIT(1), 526 [MIB_COUNTER_OVERFLOW] = BIT(7), 527 [MIB_COUNTER_VALID] = BIT(6), 528 [VLAN_TABLE_FID] = GENMASK(6, 0), 529 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 530 [VLAN_TABLE_VALID] = BIT(12), 531 [STATIC_MAC_TABLE_VALID] = BIT(21), 532 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 533 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 534 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 535 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 536 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 537 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 538 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 539 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 540 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 541 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 542 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 543 }; 544 545 static const u8 ksz8895_shifts[] = { 546 [VLAN_TABLE_MEMBERSHIP_S] = 7, 547 [VLAN_TABLE] = 13, 548 [STATIC_MAC_FWD_PORTS] = 16, 549 [STATIC_MAC_FID] = 24, 550 [DYNAMIC_MAC_ENTRIES_H] = 3, 551 [DYNAMIC_MAC_ENTRIES] = 29, 552 [DYNAMIC_MAC_FID] = 16, 553 [DYNAMIC_MAC_TIMESTAMP] = 27, 554 [DYNAMIC_MAC_SRC_PORT] = 24, 555 }; 556 557 static const u16 ksz9477_regs[] = { 558 [REG_SW_MAC_ADDR] = 0x0302, 559 [P_STP_CTRL] = 0x0B04, 560 [S_START_CTRL] = 0x0300, 561 [S_BROADCAST_CTRL] = 0x0332, 562 [S_MULTICAST_CTRL] = 0x0331, 563 [P_XMII_CTRL_0] = 0x0300, 564 [P_XMII_CTRL_1] = 0x0301, 565 [REG_SW_PME_CTRL] = 0x0006, 566 [REG_PORT_PME_STATUS] = 0x0013, 567 [REG_PORT_PME_CTRL] = 0x0017, 568 [PTP_CLK_CTRL] = 0x0500, 569 [PTP_RTC_SUB_NANOSEC] = 0x0502, 570 [PTP_RTC_NANOSEC] = 0x0504, 571 [PTP_RTC_SEC] = 0x0508, 572 [PTP_SUBNANOSEC_RATE] = 0x050C, 573 [PTP_MSG_CONF1] = 0x0514, 574 }; 575 576 static const u32 ksz9477_masks[] = { 577 [ALU_STAT_WRITE] = 0, 578 [ALU_STAT_READ] = 1, 579 [ALU_STAT_DIRECT] = 0, 580 [ALU_RESV_MCAST_ADDR] = BIT(1), 581 [P_MII_TX_FLOW_CTRL] = BIT(5), 582 [P_MII_RX_FLOW_CTRL] = BIT(3), 583 }; 584 585 static const u8 ksz9477_shifts[] = { 586 [ALU_STAT_INDEX] = 16, 587 }; 588 589 static const u8 ksz9477_xmii_ctrl0[] = { 590 [P_MII_100MBIT] = 1, 591 [P_MII_10MBIT] = 0, 592 [P_MII_FULL_DUPLEX] = 1, 593 [P_MII_HALF_DUPLEX] = 0, 594 }; 595 596 static const u8 ksz9477_xmii_ctrl1[] = { 597 [P_RGMII_SEL] = 0, 598 [P_RMII_SEL] = 1, 599 [P_GMII_SEL] = 2, 600 [P_MII_SEL] = 3, 601 [P_GMII_1GBIT] = 0, 602 [P_GMII_NOT_1GBIT] = 1, 603 }; 604 605 static const u32 lan937x_masks[] = { 606 [ALU_STAT_WRITE] = 1, 607 [ALU_STAT_READ] = 2, 608 [ALU_STAT_DIRECT] = BIT(3), 609 [ALU_RESV_MCAST_ADDR] = BIT(2), 610 [P_MII_TX_FLOW_CTRL] = BIT(5), 611 [P_MII_RX_FLOW_CTRL] = BIT(3), 612 }; 613 614 static const u8 lan937x_shifts[] = { 615 [ALU_STAT_INDEX] = 8, 616 }; 617 618 static const struct regmap_range ksz8563_valid_regs[] = { 619 regmap_reg_range(0x0000, 0x0003), 620 regmap_reg_range(0x0006, 0x0006), 621 regmap_reg_range(0x000f, 0x001f), 622 regmap_reg_range(0x0100, 0x0100), 623 regmap_reg_range(0x0104, 0x0107), 624 regmap_reg_range(0x010d, 0x010d), 625 regmap_reg_range(0x0110, 0x0113), 626 regmap_reg_range(0x0120, 0x012b), 627 regmap_reg_range(0x0201, 0x0201), 628 regmap_reg_range(0x0210, 0x0213), 629 regmap_reg_range(0x0300, 0x0300), 630 regmap_reg_range(0x0302, 0x031b), 631 regmap_reg_range(0x0320, 0x032b), 632 regmap_reg_range(0x0330, 0x0336), 633 regmap_reg_range(0x0338, 0x033e), 634 regmap_reg_range(0x0340, 0x035f), 635 regmap_reg_range(0x0370, 0x0370), 636 regmap_reg_range(0x0378, 0x0378), 637 regmap_reg_range(0x037c, 0x037d), 638 regmap_reg_range(0x0390, 0x0393), 639 regmap_reg_range(0x0400, 0x040e), 640 regmap_reg_range(0x0410, 0x042f), 641 regmap_reg_range(0x0500, 0x0519), 642 regmap_reg_range(0x0520, 0x054b), 643 regmap_reg_range(0x0550, 0x05b3), 644 645 /* port 1 */ 646 regmap_reg_range(0x1000, 0x1001), 647 regmap_reg_range(0x1004, 0x100b), 648 regmap_reg_range(0x1013, 0x1013), 649 regmap_reg_range(0x1017, 0x1017), 650 regmap_reg_range(0x101b, 0x101b), 651 regmap_reg_range(0x101f, 0x1021), 652 regmap_reg_range(0x1030, 0x1030), 653 regmap_reg_range(0x1100, 0x1111), 654 regmap_reg_range(0x111a, 0x111d), 655 regmap_reg_range(0x1122, 0x1127), 656 regmap_reg_range(0x112a, 0x112b), 657 regmap_reg_range(0x1136, 0x1139), 658 regmap_reg_range(0x113e, 0x113f), 659 regmap_reg_range(0x1400, 0x1401), 660 regmap_reg_range(0x1403, 0x1403), 661 regmap_reg_range(0x1410, 0x1417), 662 regmap_reg_range(0x1420, 0x1423), 663 regmap_reg_range(0x1500, 0x1507), 664 regmap_reg_range(0x1600, 0x1612), 665 regmap_reg_range(0x1800, 0x180f), 666 regmap_reg_range(0x1900, 0x1907), 667 regmap_reg_range(0x1914, 0x191b), 668 regmap_reg_range(0x1a00, 0x1a03), 669 regmap_reg_range(0x1a04, 0x1a08), 670 regmap_reg_range(0x1b00, 0x1b01), 671 regmap_reg_range(0x1b04, 0x1b04), 672 regmap_reg_range(0x1c00, 0x1c05), 673 regmap_reg_range(0x1c08, 0x1c1b), 674 675 /* port 2 */ 676 regmap_reg_range(0x2000, 0x2001), 677 regmap_reg_range(0x2004, 0x200b), 678 regmap_reg_range(0x2013, 0x2013), 679 regmap_reg_range(0x2017, 0x2017), 680 regmap_reg_range(0x201b, 0x201b), 681 regmap_reg_range(0x201f, 0x2021), 682 regmap_reg_range(0x2030, 0x2030), 683 regmap_reg_range(0x2100, 0x2111), 684 regmap_reg_range(0x211a, 0x211d), 685 regmap_reg_range(0x2122, 0x2127), 686 regmap_reg_range(0x212a, 0x212b), 687 regmap_reg_range(0x2136, 0x2139), 688 regmap_reg_range(0x213e, 0x213f), 689 regmap_reg_range(0x2400, 0x2401), 690 regmap_reg_range(0x2403, 0x2403), 691 regmap_reg_range(0x2410, 0x2417), 692 regmap_reg_range(0x2420, 0x2423), 693 regmap_reg_range(0x2500, 0x2507), 694 regmap_reg_range(0x2600, 0x2612), 695 regmap_reg_range(0x2800, 0x280f), 696 regmap_reg_range(0x2900, 0x2907), 697 regmap_reg_range(0x2914, 0x291b), 698 regmap_reg_range(0x2a00, 0x2a03), 699 regmap_reg_range(0x2a04, 0x2a08), 700 regmap_reg_range(0x2b00, 0x2b01), 701 regmap_reg_range(0x2b04, 0x2b04), 702 regmap_reg_range(0x2c00, 0x2c05), 703 regmap_reg_range(0x2c08, 0x2c1b), 704 705 /* port 3 */ 706 regmap_reg_range(0x3000, 0x3001), 707 regmap_reg_range(0x3004, 0x300b), 708 regmap_reg_range(0x3013, 0x3013), 709 regmap_reg_range(0x3017, 0x3017), 710 regmap_reg_range(0x301b, 0x301b), 711 regmap_reg_range(0x301f, 0x3021), 712 regmap_reg_range(0x3030, 0x3030), 713 regmap_reg_range(0x3300, 0x3301), 714 regmap_reg_range(0x3303, 0x3303), 715 regmap_reg_range(0x3400, 0x3401), 716 regmap_reg_range(0x3403, 0x3403), 717 regmap_reg_range(0x3410, 0x3417), 718 regmap_reg_range(0x3420, 0x3423), 719 regmap_reg_range(0x3500, 0x3507), 720 regmap_reg_range(0x3600, 0x3612), 721 regmap_reg_range(0x3800, 0x380f), 722 regmap_reg_range(0x3900, 0x3907), 723 regmap_reg_range(0x3914, 0x391b), 724 regmap_reg_range(0x3a00, 0x3a03), 725 regmap_reg_range(0x3a04, 0x3a08), 726 regmap_reg_range(0x3b00, 0x3b01), 727 regmap_reg_range(0x3b04, 0x3b04), 728 regmap_reg_range(0x3c00, 0x3c05), 729 regmap_reg_range(0x3c08, 0x3c1b), 730 }; 731 732 static const struct regmap_access_table ksz8563_register_set = { 733 .yes_ranges = ksz8563_valid_regs, 734 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 735 }; 736 737 static const struct regmap_range ksz9477_valid_regs[] = { 738 regmap_reg_range(0x0000, 0x0003), 739 regmap_reg_range(0x0006, 0x0006), 740 regmap_reg_range(0x0010, 0x001f), 741 regmap_reg_range(0x0100, 0x0100), 742 regmap_reg_range(0x0103, 0x0107), 743 regmap_reg_range(0x010d, 0x010d), 744 regmap_reg_range(0x0110, 0x0113), 745 regmap_reg_range(0x0120, 0x012b), 746 regmap_reg_range(0x0201, 0x0201), 747 regmap_reg_range(0x0210, 0x0213), 748 regmap_reg_range(0x0300, 0x0300), 749 regmap_reg_range(0x0302, 0x031b), 750 regmap_reg_range(0x0320, 0x032b), 751 regmap_reg_range(0x0330, 0x0336), 752 regmap_reg_range(0x0338, 0x033b), 753 regmap_reg_range(0x033e, 0x033e), 754 regmap_reg_range(0x0340, 0x035f), 755 regmap_reg_range(0x0370, 0x0370), 756 regmap_reg_range(0x0378, 0x0378), 757 regmap_reg_range(0x037c, 0x037d), 758 regmap_reg_range(0x0390, 0x0393), 759 regmap_reg_range(0x0400, 0x040e), 760 regmap_reg_range(0x0410, 0x042f), 761 regmap_reg_range(0x0444, 0x044b), 762 regmap_reg_range(0x0450, 0x046f), 763 regmap_reg_range(0x0500, 0x0519), 764 regmap_reg_range(0x0520, 0x054b), 765 regmap_reg_range(0x0550, 0x05b3), 766 regmap_reg_range(0x0604, 0x060b), 767 regmap_reg_range(0x0610, 0x0612), 768 regmap_reg_range(0x0614, 0x062c), 769 regmap_reg_range(0x0640, 0x0645), 770 regmap_reg_range(0x0648, 0x064d), 771 772 /* port 1 */ 773 regmap_reg_range(0x1000, 0x1001), 774 regmap_reg_range(0x1013, 0x1013), 775 regmap_reg_range(0x1017, 0x1017), 776 regmap_reg_range(0x101b, 0x101b), 777 regmap_reg_range(0x101f, 0x1020), 778 regmap_reg_range(0x1030, 0x1030), 779 regmap_reg_range(0x1100, 0x1115), 780 regmap_reg_range(0x111a, 0x111f), 781 regmap_reg_range(0x1120, 0x112b), 782 regmap_reg_range(0x1134, 0x113b), 783 regmap_reg_range(0x113c, 0x113f), 784 regmap_reg_range(0x1400, 0x1401), 785 regmap_reg_range(0x1403, 0x1403), 786 regmap_reg_range(0x1410, 0x1417), 787 regmap_reg_range(0x1420, 0x1423), 788 regmap_reg_range(0x1500, 0x1507), 789 regmap_reg_range(0x1600, 0x1613), 790 regmap_reg_range(0x1800, 0x180f), 791 regmap_reg_range(0x1820, 0x1827), 792 regmap_reg_range(0x1830, 0x1837), 793 regmap_reg_range(0x1840, 0x184b), 794 regmap_reg_range(0x1900, 0x1907), 795 regmap_reg_range(0x1914, 0x191b), 796 regmap_reg_range(0x1920, 0x1920), 797 regmap_reg_range(0x1923, 0x1927), 798 regmap_reg_range(0x1a00, 0x1a03), 799 regmap_reg_range(0x1a04, 0x1a07), 800 regmap_reg_range(0x1b00, 0x1b01), 801 regmap_reg_range(0x1b04, 0x1b04), 802 regmap_reg_range(0x1c00, 0x1c05), 803 regmap_reg_range(0x1c08, 0x1c1b), 804 805 /* port 2 */ 806 regmap_reg_range(0x2000, 0x2001), 807 regmap_reg_range(0x2013, 0x2013), 808 regmap_reg_range(0x2017, 0x2017), 809 regmap_reg_range(0x201b, 0x201b), 810 regmap_reg_range(0x201f, 0x2020), 811 regmap_reg_range(0x2030, 0x2030), 812 regmap_reg_range(0x2100, 0x2115), 813 regmap_reg_range(0x211a, 0x211f), 814 regmap_reg_range(0x2120, 0x212b), 815 regmap_reg_range(0x2134, 0x213b), 816 regmap_reg_range(0x213c, 0x213f), 817 regmap_reg_range(0x2400, 0x2401), 818 regmap_reg_range(0x2403, 0x2403), 819 regmap_reg_range(0x2410, 0x2417), 820 regmap_reg_range(0x2420, 0x2423), 821 regmap_reg_range(0x2500, 0x2507), 822 regmap_reg_range(0x2600, 0x2613), 823 regmap_reg_range(0x2800, 0x280f), 824 regmap_reg_range(0x2820, 0x2827), 825 regmap_reg_range(0x2830, 0x2837), 826 regmap_reg_range(0x2840, 0x284b), 827 regmap_reg_range(0x2900, 0x2907), 828 regmap_reg_range(0x2914, 0x291b), 829 regmap_reg_range(0x2920, 0x2920), 830 regmap_reg_range(0x2923, 0x2927), 831 regmap_reg_range(0x2a00, 0x2a03), 832 regmap_reg_range(0x2a04, 0x2a07), 833 regmap_reg_range(0x2b00, 0x2b01), 834 regmap_reg_range(0x2b04, 0x2b04), 835 regmap_reg_range(0x2c00, 0x2c05), 836 regmap_reg_range(0x2c08, 0x2c1b), 837 838 /* port 3 */ 839 regmap_reg_range(0x3000, 0x3001), 840 regmap_reg_range(0x3013, 0x3013), 841 regmap_reg_range(0x3017, 0x3017), 842 regmap_reg_range(0x301b, 0x301b), 843 regmap_reg_range(0x301f, 0x3020), 844 regmap_reg_range(0x3030, 0x3030), 845 regmap_reg_range(0x3100, 0x3115), 846 regmap_reg_range(0x311a, 0x311f), 847 regmap_reg_range(0x3120, 0x312b), 848 regmap_reg_range(0x3134, 0x313b), 849 regmap_reg_range(0x313c, 0x313f), 850 regmap_reg_range(0x3400, 0x3401), 851 regmap_reg_range(0x3403, 0x3403), 852 regmap_reg_range(0x3410, 0x3417), 853 regmap_reg_range(0x3420, 0x3423), 854 regmap_reg_range(0x3500, 0x3507), 855 regmap_reg_range(0x3600, 0x3613), 856 regmap_reg_range(0x3800, 0x380f), 857 regmap_reg_range(0x3820, 0x3827), 858 regmap_reg_range(0x3830, 0x3837), 859 regmap_reg_range(0x3840, 0x384b), 860 regmap_reg_range(0x3900, 0x3907), 861 regmap_reg_range(0x3914, 0x391b), 862 regmap_reg_range(0x3920, 0x3920), 863 regmap_reg_range(0x3923, 0x3927), 864 regmap_reg_range(0x3a00, 0x3a03), 865 regmap_reg_range(0x3a04, 0x3a07), 866 regmap_reg_range(0x3b00, 0x3b01), 867 regmap_reg_range(0x3b04, 0x3b04), 868 regmap_reg_range(0x3c00, 0x3c05), 869 regmap_reg_range(0x3c08, 0x3c1b), 870 871 /* port 4 */ 872 regmap_reg_range(0x4000, 0x4001), 873 regmap_reg_range(0x4013, 0x4013), 874 regmap_reg_range(0x4017, 0x4017), 875 regmap_reg_range(0x401b, 0x401b), 876 regmap_reg_range(0x401f, 0x4020), 877 regmap_reg_range(0x4030, 0x4030), 878 regmap_reg_range(0x4100, 0x4115), 879 regmap_reg_range(0x411a, 0x411f), 880 regmap_reg_range(0x4120, 0x412b), 881 regmap_reg_range(0x4134, 0x413b), 882 regmap_reg_range(0x413c, 0x413f), 883 regmap_reg_range(0x4400, 0x4401), 884 regmap_reg_range(0x4403, 0x4403), 885 regmap_reg_range(0x4410, 0x4417), 886 regmap_reg_range(0x4420, 0x4423), 887 regmap_reg_range(0x4500, 0x4507), 888 regmap_reg_range(0x4600, 0x4613), 889 regmap_reg_range(0x4800, 0x480f), 890 regmap_reg_range(0x4820, 0x4827), 891 regmap_reg_range(0x4830, 0x4837), 892 regmap_reg_range(0x4840, 0x484b), 893 regmap_reg_range(0x4900, 0x4907), 894 regmap_reg_range(0x4914, 0x491b), 895 regmap_reg_range(0x4920, 0x4920), 896 regmap_reg_range(0x4923, 0x4927), 897 regmap_reg_range(0x4a00, 0x4a03), 898 regmap_reg_range(0x4a04, 0x4a07), 899 regmap_reg_range(0x4b00, 0x4b01), 900 regmap_reg_range(0x4b04, 0x4b04), 901 regmap_reg_range(0x4c00, 0x4c05), 902 regmap_reg_range(0x4c08, 0x4c1b), 903 904 /* port 5 */ 905 regmap_reg_range(0x5000, 0x5001), 906 regmap_reg_range(0x5013, 0x5013), 907 regmap_reg_range(0x5017, 0x5017), 908 regmap_reg_range(0x501b, 0x501b), 909 regmap_reg_range(0x501f, 0x5020), 910 regmap_reg_range(0x5030, 0x5030), 911 regmap_reg_range(0x5100, 0x5115), 912 regmap_reg_range(0x511a, 0x511f), 913 regmap_reg_range(0x5120, 0x512b), 914 regmap_reg_range(0x5134, 0x513b), 915 regmap_reg_range(0x513c, 0x513f), 916 regmap_reg_range(0x5400, 0x5401), 917 regmap_reg_range(0x5403, 0x5403), 918 regmap_reg_range(0x5410, 0x5417), 919 regmap_reg_range(0x5420, 0x5423), 920 regmap_reg_range(0x5500, 0x5507), 921 regmap_reg_range(0x5600, 0x5613), 922 regmap_reg_range(0x5800, 0x580f), 923 regmap_reg_range(0x5820, 0x5827), 924 regmap_reg_range(0x5830, 0x5837), 925 regmap_reg_range(0x5840, 0x584b), 926 regmap_reg_range(0x5900, 0x5907), 927 regmap_reg_range(0x5914, 0x591b), 928 regmap_reg_range(0x5920, 0x5920), 929 regmap_reg_range(0x5923, 0x5927), 930 regmap_reg_range(0x5a00, 0x5a03), 931 regmap_reg_range(0x5a04, 0x5a07), 932 regmap_reg_range(0x5b00, 0x5b01), 933 regmap_reg_range(0x5b04, 0x5b04), 934 regmap_reg_range(0x5c00, 0x5c05), 935 regmap_reg_range(0x5c08, 0x5c1b), 936 937 /* port 6 */ 938 regmap_reg_range(0x6000, 0x6001), 939 regmap_reg_range(0x6013, 0x6013), 940 regmap_reg_range(0x6017, 0x6017), 941 regmap_reg_range(0x601b, 0x601b), 942 regmap_reg_range(0x601f, 0x6020), 943 regmap_reg_range(0x6030, 0x6030), 944 regmap_reg_range(0x6300, 0x6301), 945 regmap_reg_range(0x6400, 0x6401), 946 regmap_reg_range(0x6403, 0x6403), 947 regmap_reg_range(0x6410, 0x6417), 948 regmap_reg_range(0x6420, 0x6423), 949 regmap_reg_range(0x6500, 0x6507), 950 regmap_reg_range(0x6600, 0x6613), 951 regmap_reg_range(0x6800, 0x680f), 952 regmap_reg_range(0x6820, 0x6827), 953 regmap_reg_range(0x6830, 0x6837), 954 regmap_reg_range(0x6840, 0x684b), 955 regmap_reg_range(0x6900, 0x6907), 956 regmap_reg_range(0x6914, 0x691b), 957 regmap_reg_range(0x6920, 0x6920), 958 regmap_reg_range(0x6923, 0x6927), 959 regmap_reg_range(0x6a00, 0x6a03), 960 regmap_reg_range(0x6a04, 0x6a07), 961 regmap_reg_range(0x6b00, 0x6b01), 962 regmap_reg_range(0x6b04, 0x6b04), 963 regmap_reg_range(0x6c00, 0x6c05), 964 regmap_reg_range(0x6c08, 0x6c1b), 965 966 /* port 7 */ 967 regmap_reg_range(0x7000, 0x7001), 968 regmap_reg_range(0x7013, 0x7013), 969 regmap_reg_range(0x7017, 0x7017), 970 regmap_reg_range(0x701b, 0x701b), 971 regmap_reg_range(0x701f, 0x7020), 972 regmap_reg_range(0x7030, 0x7030), 973 regmap_reg_range(0x7200, 0x7207), 974 regmap_reg_range(0x7300, 0x7301), 975 regmap_reg_range(0x7400, 0x7401), 976 regmap_reg_range(0x7403, 0x7403), 977 regmap_reg_range(0x7410, 0x7417), 978 regmap_reg_range(0x7420, 0x7423), 979 regmap_reg_range(0x7500, 0x7507), 980 regmap_reg_range(0x7600, 0x7613), 981 regmap_reg_range(0x7800, 0x780f), 982 regmap_reg_range(0x7820, 0x7827), 983 regmap_reg_range(0x7830, 0x7837), 984 regmap_reg_range(0x7840, 0x784b), 985 regmap_reg_range(0x7900, 0x7907), 986 regmap_reg_range(0x7914, 0x791b), 987 regmap_reg_range(0x7920, 0x7920), 988 regmap_reg_range(0x7923, 0x7927), 989 regmap_reg_range(0x7a00, 0x7a03), 990 regmap_reg_range(0x7a04, 0x7a07), 991 regmap_reg_range(0x7b00, 0x7b01), 992 regmap_reg_range(0x7b04, 0x7b04), 993 regmap_reg_range(0x7c00, 0x7c05), 994 regmap_reg_range(0x7c08, 0x7c1b), 995 }; 996 997 static const struct regmap_access_table ksz9477_register_set = { 998 .yes_ranges = ksz9477_valid_regs, 999 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 1000 }; 1001 1002 static const struct regmap_range ksz9896_valid_regs[] = { 1003 regmap_reg_range(0x0000, 0x0003), 1004 regmap_reg_range(0x0006, 0x0006), 1005 regmap_reg_range(0x0010, 0x001f), 1006 regmap_reg_range(0x0100, 0x0100), 1007 regmap_reg_range(0x0103, 0x0107), 1008 regmap_reg_range(0x010d, 0x010d), 1009 regmap_reg_range(0x0110, 0x0113), 1010 regmap_reg_range(0x0120, 0x0127), 1011 regmap_reg_range(0x0201, 0x0201), 1012 regmap_reg_range(0x0210, 0x0213), 1013 regmap_reg_range(0x0300, 0x0300), 1014 regmap_reg_range(0x0302, 0x030b), 1015 regmap_reg_range(0x0310, 0x031b), 1016 regmap_reg_range(0x0320, 0x032b), 1017 regmap_reg_range(0x0330, 0x0336), 1018 regmap_reg_range(0x0338, 0x033b), 1019 regmap_reg_range(0x033e, 0x033e), 1020 regmap_reg_range(0x0340, 0x035f), 1021 regmap_reg_range(0x0370, 0x0370), 1022 regmap_reg_range(0x0378, 0x0378), 1023 regmap_reg_range(0x037c, 0x037d), 1024 regmap_reg_range(0x0390, 0x0393), 1025 regmap_reg_range(0x0400, 0x040e), 1026 regmap_reg_range(0x0410, 0x042f), 1027 1028 /* port 1 */ 1029 regmap_reg_range(0x1000, 0x1001), 1030 regmap_reg_range(0x1013, 0x1013), 1031 regmap_reg_range(0x1017, 0x1017), 1032 regmap_reg_range(0x101b, 0x101b), 1033 regmap_reg_range(0x101f, 0x1020), 1034 regmap_reg_range(0x1030, 0x1030), 1035 regmap_reg_range(0x1100, 0x1115), 1036 regmap_reg_range(0x111a, 0x111f), 1037 regmap_reg_range(0x1120, 0x112b), 1038 regmap_reg_range(0x1134, 0x113b), 1039 regmap_reg_range(0x113c, 0x113f), 1040 regmap_reg_range(0x1400, 0x1401), 1041 regmap_reg_range(0x1403, 0x1403), 1042 regmap_reg_range(0x1410, 0x1417), 1043 regmap_reg_range(0x1420, 0x1423), 1044 regmap_reg_range(0x1500, 0x1507), 1045 regmap_reg_range(0x1600, 0x1612), 1046 regmap_reg_range(0x1800, 0x180f), 1047 regmap_reg_range(0x1820, 0x1827), 1048 regmap_reg_range(0x1830, 0x1837), 1049 regmap_reg_range(0x1840, 0x184b), 1050 regmap_reg_range(0x1900, 0x1907), 1051 regmap_reg_range(0x1914, 0x1915), 1052 regmap_reg_range(0x1a00, 0x1a03), 1053 regmap_reg_range(0x1a04, 0x1a07), 1054 regmap_reg_range(0x1b00, 0x1b01), 1055 regmap_reg_range(0x1b04, 0x1b04), 1056 1057 /* port 2 */ 1058 regmap_reg_range(0x2000, 0x2001), 1059 regmap_reg_range(0x2013, 0x2013), 1060 regmap_reg_range(0x2017, 0x2017), 1061 regmap_reg_range(0x201b, 0x201b), 1062 regmap_reg_range(0x201f, 0x2020), 1063 regmap_reg_range(0x2030, 0x2030), 1064 regmap_reg_range(0x2100, 0x2115), 1065 regmap_reg_range(0x211a, 0x211f), 1066 regmap_reg_range(0x2120, 0x212b), 1067 regmap_reg_range(0x2134, 0x213b), 1068 regmap_reg_range(0x213c, 0x213f), 1069 regmap_reg_range(0x2400, 0x2401), 1070 regmap_reg_range(0x2403, 0x2403), 1071 regmap_reg_range(0x2410, 0x2417), 1072 regmap_reg_range(0x2420, 0x2423), 1073 regmap_reg_range(0x2500, 0x2507), 1074 regmap_reg_range(0x2600, 0x2612), 1075 regmap_reg_range(0x2800, 0x280f), 1076 regmap_reg_range(0x2820, 0x2827), 1077 regmap_reg_range(0x2830, 0x2837), 1078 regmap_reg_range(0x2840, 0x284b), 1079 regmap_reg_range(0x2900, 0x2907), 1080 regmap_reg_range(0x2914, 0x2915), 1081 regmap_reg_range(0x2a00, 0x2a03), 1082 regmap_reg_range(0x2a04, 0x2a07), 1083 regmap_reg_range(0x2b00, 0x2b01), 1084 regmap_reg_range(0x2b04, 0x2b04), 1085 1086 /* port 3 */ 1087 regmap_reg_range(0x3000, 0x3001), 1088 regmap_reg_range(0x3013, 0x3013), 1089 regmap_reg_range(0x3017, 0x3017), 1090 regmap_reg_range(0x301b, 0x301b), 1091 regmap_reg_range(0x301f, 0x3020), 1092 regmap_reg_range(0x3030, 0x3030), 1093 regmap_reg_range(0x3100, 0x3115), 1094 regmap_reg_range(0x311a, 0x311f), 1095 regmap_reg_range(0x3120, 0x312b), 1096 regmap_reg_range(0x3134, 0x313b), 1097 regmap_reg_range(0x313c, 0x313f), 1098 regmap_reg_range(0x3400, 0x3401), 1099 regmap_reg_range(0x3403, 0x3403), 1100 regmap_reg_range(0x3410, 0x3417), 1101 regmap_reg_range(0x3420, 0x3423), 1102 regmap_reg_range(0x3500, 0x3507), 1103 regmap_reg_range(0x3600, 0x3612), 1104 regmap_reg_range(0x3800, 0x380f), 1105 regmap_reg_range(0x3820, 0x3827), 1106 regmap_reg_range(0x3830, 0x3837), 1107 regmap_reg_range(0x3840, 0x384b), 1108 regmap_reg_range(0x3900, 0x3907), 1109 regmap_reg_range(0x3914, 0x3915), 1110 regmap_reg_range(0x3a00, 0x3a03), 1111 regmap_reg_range(0x3a04, 0x3a07), 1112 regmap_reg_range(0x3b00, 0x3b01), 1113 regmap_reg_range(0x3b04, 0x3b04), 1114 1115 /* port 4 */ 1116 regmap_reg_range(0x4000, 0x4001), 1117 regmap_reg_range(0x4013, 0x4013), 1118 regmap_reg_range(0x4017, 0x4017), 1119 regmap_reg_range(0x401b, 0x401b), 1120 regmap_reg_range(0x401f, 0x4020), 1121 regmap_reg_range(0x4030, 0x4030), 1122 regmap_reg_range(0x4100, 0x4115), 1123 regmap_reg_range(0x411a, 0x411f), 1124 regmap_reg_range(0x4120, 0x412b), 1125 regmap_reg_range(0x4134, 0x413b), 1126 regmap_reg_range(0x413c, 0x413f), 1127 regmap_reg_range(0x4400, 0x4401), 1128 regmap_reg_range(0x4403, 0x4403), 1129 regmap_reg_range(0x4410, 0x4417), 1130 regmap_reg_range(0x4420, 0x4423), 1131 regmap_reg_range(0x4500, 0x4507), 1132 regmap_reg_range(0x4600, 0x4612), 1133 regmap_reg_range(0x4800, 0x480f), 1134 regmap_reg_range(0x4820, 0x4827), 1135 regmap_reg_range(0x4830, 0x4837), 1136 regmap_reg_range(0x4840, 0x484b), 1137 regmap_reg_range(0x4900, 0x4907), 1138 regmap_reg_range(0x4914, 0x4915), 1139 regmap_reg_range(0x4a00, 0x4a03), 1140 regmap_reg_range(0x4a04, 0x4a07), 1141 regmap_reg_range(0x4b00, 0x4b01), 1142 regmap_reg_range(0x4b04, 0x4b04), 1143 1144 /* port 5 */ 1145 regmap_reg_range(0x5000, 0x5001), 1146 regmap_reg_range(0x5013, 0x5013), 1147 regmap_reg_range(0x5017, 0x5017), 1148 regmap_reg_range(0x501b, 0x501b), 1149 regmap_reg_range(0x501f, 0x5020), 1150 regmap_reg_range(0x5030, 0x5030), 1151 regmap_reg_range(0x5100, 0x5115), 1152 regmap_reg_range(0x511a, 0x511f), 1153 regmap_reg_range(0x5120, 0x512b), 1154 regmap_reg_range(0x5134, 0x513b), 1155 regmap_reg_range(0x513c, 0x513f), 1156 regmap_reg_range(0x5400, 0x5401), 1157 regmap_reg_range(0x5403, 0x5403), 1158 regmap_reg_range(0x5410, 0x5417), 1159 regmap_reg_range(0x5420, 0x5423), 1160 regmap_reg_range(0x5500, 0x5507), 1161 regmap_reg_range(0x5600, 0x5612), 1162 regmap_reg_range(0x5800, 0x580f), 1163 regmap_reg_range(0x5820, 0x5827), 1164 regmap_reg_range(0x5830, 0x5837), 1165 regmap_reg_range(0x5840, 0x584b), 1166 regmap_reg_range(0x5900, 0x5907), 1167 regmap_reg_range(0x5914, 0x5915), 1168 regmap_reg_range(0x5a00, 0x5a03), 1169 regmap_reg_range(0x5a04, 0x5a07), 1170 regmap_reg_range(0x5b00, 0x5b01), 1171 regmap_reg_range(0x5b04, 0x5b04), 1172 1173 /* port 6 */ 1174 regmap_reg_range(0x6000, 0x6001), 1175 regmap_reg_range(0x6013, 0x6013), 1176 regmap_reg_range(0x6017, 0x6017), 1177 regmap_reg_range(0x601b, 0x601b), 1178 regmap_reg_range(0x601f, 0x6020), 1179 regmap_reg_range(0x6030, 0x6030), 1180 regmap_reg_range(0x6100, 0x6115), 1181 regmap_reg_range(0x611a, 0x611f), 1182 regmap_reg_range(0x6120, 0x612b), 1183 regmap_reg_range(0x6134, 0x613b), 1184 regmap_reg_range(0x613c, 0x613f), 1185 regmap_reg_range(0x6300, 0x6301), 1186 regmap_reg_range(0x6400, 0x6401), 1187 regmap_reg_range(0x6403, 0x6403), 1188 regmap_reg_range(0x6410, 0x6417), 1189 regmap_reg_range(0x6420, 0x6423), 1190 regmap_reg_range(0x6500, 0x6507), 1191 regmap_reg_range(0x6600, 0x6612), 1192 regmap_reg_range(0x6800, 0x680f), 1193 regmap_reg_range(0x6820, 0x6827), 1194 regmap_reg_range(0x6830, 0x6837), 1195 regmap_reg_range(0x6840, 0x684b), 1196 regmap_reg_range(0x6900, 0x6907), 1197 regmap_reg_range(0x6914, 0x6915), 1198 regmap_reg_range(0x6a00, 0x6a03), 1199 regmap_reg_range(0x6a04, 0x6a07), 1200 regmap_reg_range(0x6b00, 0x6b01), 1201 regmap_reg_range(0x6b04, 0x6b04), 1202 }; 1203 1204 static const struct regmap_access_table ksz9896_register_set = { 1205 .yes_ranges = ksz9896_valid_regs, 1206 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1207 }; 1208 1209 static const struct regmap_range ksz8873_valid_regs[] = { 1210 regmap_reg_range(0x00, 0x01), 1211 /* global control register */ 1212 regmap_reg_range(0x02, 0x0f), 1213 1214 /* port registers */ 1215 regmap_reg_range(0x10, 0x1d), 1216 regmap_reg_range(0x1e, 0x1f), 1217 regmap_reg_range(0x20, 0x2d), 1218 regmap_reg_range(0x2e, 0x2f), 1219 regmap_reg_range(0x30, 0x39), 1220 regmap_reg_range(0x3f, 0x3f), 1221 1222 /* advanced control registers */ 1223 regmap_reg_range(0x43, 0x43), 1224 regmap_reg_range(0x60, 0x6f), 1225 regmap_reg_range(0x70, 0x75), 1226 regmap_reg_range(0x76, 0x78), 1227 regmap_reg_range(0x79, 0x7a), 1228 regmap_reg_range(0x7b, 0x83), 1229 regmap_reg_range(0x8e, 0x99), 1230 regmap_reg_range(0x9a, 0xa5), 1231 regmap_reg_range(0xa6, 0xa6), 1232 regmap_reg_range(0xa7, 0xaa), 1233 regmap_reg_range(0xab, 0xae), 1234 regmap_reg_range(0xaf, 0xba), 1235 regmap_reg_range(0xbb, 0xbc), 1236 regmap_reg_range(0xbd, 0xbd), 1237 regmap_reg_range(0xc0, 0xc0), 1238 regmap_reg_range(0xc2, 0xc2), 1239 regmap_reg_range(0xc3, 0xc3), 1240 regmap_reg_range(0xc4, 0xc4), 1241 regmap_reg_range(0xc6, 0xc6), 1242 }; 1243 1244 static const struct regmap_access_table ksz8873_register_set = { 1245 .yes_ranges = ksz8873_valid_regs, 1246 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), 1247 }; 1248 1249 const struct ksz_chip_data ksz_switch_chips[] = { 1250 [KSZ8463] = { 1251 .chip_id = KSZ8463_CHIP_ID, 1252 .dev_name = "KSZ8463", 1253 .num_vlans = 16, 1254 .num_alus = 0, 1255 .num_statics = 8, 1256 .cpu_ports = 0x4, /* can be configured as cpu port */ 1257 .port_cnt = 3, 1258 .num_tx_queues = 4, 1259 .num_ipms = 4, 1260 .ops = &ksz8463_dev_ops, 1261 .switch_ops = &ksz8463_switch_ops, 1262 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1263 .mib_names = ksz88xx_mib_names, 1264 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1265 .reg_mib_cnt = MIB_COUNTER_NUM, 1266 .regs = ksz8463_regs, 1267 .masks = ksz8463_masks, 1268 .shifts = ksz8463_shifts, 1269 .supports_mii = {false, false, true}, 1270 .supports_rmii = {false, false, true}, 1271 .internal_phy = {true, true, false}, 1272 }, 1273 1274 [KSZ8563] = { 1275 .chip_id = KSZ8563_CHIP_ID, 1276 .dev_name = "KSZ8563", 1277 .num_vlans = 4096, 1278 .num_alus = 4096, 1279 .num_statics = 16, 1280 .cpu_ports = 0x07, /* can be configured as cpu port */ 1281 .port_cnt = 3, /* total port count */ 1282 .port_nirqs = 3, 1283 .num_tx_queues = 4, 1284 .num_ipms = 8, 1285 .tc_cbs_supported = true, 1286 .ops = &ksz9477_dev_ops, 1287 .switch_ops = &ksz9477_switch_ops, 1288 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1289 .mib_names = ksz9477_mib_names, 1290 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1291 .reg_mib_cnt = MIB_COUNTER_NUM, 1292 .regs = ksz9477_regs, 1293 .masks = ksz9477_masks, 1294 .shifts = ksz9477_shifts, 1295 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1296 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1297 .supports_mii = {false, false, true}, 1298 .supports_rmii = {false, false, true}, 1299 .supports_rgmii = {false, false, true}, 1300 .internal_phy = {true, true, false}, 1301 .gbit_capable = {false, false, true}, 1302 .ptp_capable = true, 1303 .wr_table = &ksz8563_register_set, 1304 .rd_table = &ksz8563_register_set, 1305 }, 1306 1307 [KSZ8795] = { 1308 .chip_id = KSZ8795_CHIP_ID, 1309 .dev_name = "KSZ8795", 1310 .num_vlans = 4096, 1311 .num_alus = 0, 1312 .num_statics = 32, 1313 .cpu_ports = 0x10, /* can be configured as cpu port */ 1314 .port_cnt = 5, /* total cpu and user ports */ 1315 .num_tx_queues = 4, 1316 .num_ipms = 4, 1317 .ops = &ksz87xx_dev_ops, 1318 .switch_ops = &ksz87xx_switch_ops, 1319 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1320 .ksz87xx_eee_link_erratum = true, 1321 .mib_names = ksz9477_mib_names, 1322 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1323 .reg_mib_cnt = MIB_COUNTER_NUM, 1324 .regs = ksz8795_regs, 1325 .masks = ksz8795_masks, 1326 .shifts = ksz8795_shifts, 1327 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1328 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1329 .supports_mii = {false, false, false, false, true}, 1330 .supports_rmii = {false, false, false, false, true}, 1331 .supports_rgmii = {false, false, false, false, true}, 1332 .internal_phy = {true, true, true, true, false}, 1333 }, 1334 1335 [KSZ8794] = { 1336 /* WARNING 1337 * ======= 1338 * KSZ8794 is similar to KSZ8795, except the port map 1339 * contains a gap between external and CPU ports, the 1340 * port map is NOT continuous. The per-port register 1341 * map is shifted accordingly too, i.e. registers at 1342 * offset 0x40 are NOT used on KSZ8794 and they ARE 1343 * used on KSZ8795 for external port 3. 1344 * external cpu 1345 * KSZ8794 0,1,2 4 1346 * KSZ8795 0,1,2,3 4 1347 * KSZ8765 0,1,2,3 4 1348 * port_cnt is configured as 5, even though it is 4 1349 */ 1350 .chip_id = KSZ8794_CHIP_ID, 1351 .dev_name = "KSZ8794", 1352 .num_vlans = 4096, 1353 .num_alus = 0, 1354 .num_statics = 32, 1355 .cpu_ports = 0x10, /* can be configured as cpu port */ 1356 .port_cnt = 5, /* total cpu and user ports */ 1357 .num_tx_queues = 4, 1358 .num_ipms = 4, 1359 .ops = &ksz87xx_dev_ops, 1360 .switch_ops = &ksz87xx_switch_ops, 1361 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1362 .ksz87xx_eee_link_erratum = true, 1363 .mib_names = ksz9477_mib_names, 1364 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1365 .reg_mib_cnt = MIB_COUNTER_NUM, 1366 .regs = ksz8795_regs, 1367 .masks = ksz8795_masks, 1368 .shifts = ksz8795_shifts, 1369 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1370 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1371 .supports_mii = {false, false, false, false, true}, 1372 .supports_rmii = {false, false, false, false, true}, 1373 .supports_rgmii = {false, false, false, false, true}, 1374 .internal_phy = {true, true, true, false, false}, 1375 }, 1376 1377 [KSZ8765] = { 1378 .chip_id = KSZ8765_CHIP_ID, 1379 .dev_name = "KSZ8765", 1380 .num_vlans = 4096, 1381 .num_alus = 0, 1382 .num_statics = 32, 1383 .cpu_ports = 0x10, /* can be configured as cpu port */ 1384 .port_cnt = 5, /* total cpu and user ports */ 1385 .num_tx_queues = 4, 1386 .num_ipms = 4, 1387 .ops = &ksz87xx_dev_ops, 1388 .switch_ops = &ksz87xx_switch_ops, 1389 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1390 .ksz87xx_eee_link_erratum = true, 1391 .mib_names = ksz9477_mib_names, 1392 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1393 .reg_mib_cnt = MIB_COUNTER_NUM, 1394 .regs = ksz8795_regs, 1395 .masks = ksz8795_masks, 1396 .shifts = ksz8795_shifts, 1397 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1398 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1399 .supports_mii = {false, false, false, false, true}, 1400 .supports_rmii = {false, false, false, false, true}, 1401 .supports_rgmii = {false, false, false, false, true}, 1402 .internal_phy = {true, true, true, true, false}, 1403 }, 1404 1405 [KSZ88X3] = { 1406 .chip_id = KSZ88X3_CHIP_ID, 1407 .dev_name = "KSZ8863/KSZ8873", 1408 .num_vlans = 16, 1409 .num_alus = 0, 1410 .num_statics = 8, 1411 .cpu_ports = 0x4, /* can be configured as cpu port */ 1412 .port_cnt = 3, 1413 .num_tx_queues = 4, 1414 .num_ipms = 4, 1415 .ops = &ksz88xx_dev_ops, 1416 .switch_ops = &ksz88xx_switch_ops, 1417 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1418 .mib_names = ksz88xx_mib_names, 1419 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1420 .reg_mib_cnt = MIB_COUNTER_NUM, 1421 .regs = ksz8863_regs, 1422 .masks = ksz8863_masks, 1423 .shifts = ksz8863_shifts, 1424 .supports_mii = {false, false, true}, 1425 .supports_rmii = {false, false, true}, 1426 .internal_phy = {true, true, false}, 1427 .wr_table = &ksz8873_register_set, 1428 .rd_table = &ksz8873_register_set, 1429 }, 1430 1431 [KSZ8864] = { 1432 /* WARNING 1433 * ======= 1434 * KSZ8864 is similar to KSZ8895, except the first port 1435 * does not exist. 1436 * external cpu 1437 * KSZ8864 1,2,3 4 1438 * KSZ8895 0,1,2,3 4 1439 * port_cnt is configured as 5, even though it is 4 1440 */ 1441 .chip_id = KSZ8864_CHIP_ID, 1442 .dev_name = "KSZ8864", 1443 .num_vlans = 4096, 1444 .num_alus = 0, 1445 .num_statics = 32, 1446 .cpu_ports = 0x10, /* can be configured as cpu port */ 1447 .port_cnt = 5, /* total cpu and user ports */ 1448 .num_tx_queues = 4, 1449 .num_ipms = 4, 1450 .ops = &ksz88xx_dev_ops, 1451 .switch_ops = &ksz88xx_switch_ops, 1452 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1453 .mib_names = ksz88xx_mib_names, 1454 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1455 .reg_mib_cnt = MIB_COUNTER_NUM, 1456 .regs = ksz8895_regs, 1457 .masks = ksz8895_masks, 1458 .shifts = ksz8895_shifts, 1459 .supports_mii = {false, false, false, false, true}, 1460 .supports_rmii = {false, false, false, false, true}, 1461 .internal_phy = {false, true, true, true, false}, 1462 }, 1463 1464 [KSZ8895] = { 1465 .chip_id = KSZ8895_CHIP_ID, 1466 .dev_name = "KSZ8895", 1467 .num_vlans = 4096, 1468 .num_alus = 0, 1469 .num_statics = 32, 1470 .cpu_ports = 0x10, /* can be configured as cpu port */ 1471 .port_cnt = 5, /* total cpu and user ports */ 1472 .num_tx_queues = 4, 1473 .num_ipms = 4, 1474 .ops = &ksz88xx_dev_ops, 1475 .switch_ops = &ksz88xx_switch_ops, 1476 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1477 .mib_names = ksz88xx_mib_names, 1478 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1479 .reg_mib_cnt = MIB_COUNTER_NUM, 1480 .regs = ksz8895_regs, 1481 .masks = ksz8895_masks, 1482 .shifts = ksz8895_shifts, 1483 .supports_mii = {false, false, false, false, true}, 1484 .supports_rmii = {false, false, false, false, true}, 1485 .internal_phy = {true, true, true, true, false}, 1486 }, 1487 1488 [KSZ9477] = { 1489 .chip_id = KSZ9477_CHIP_ID, 1490 .dev_name = "KSZ9477", 1491 .num_vlans = 4096, 1492 .num_alus = 4096, 1493 .num_statics = 16, 1494 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1495 .port_cnt = 7, /* total physical port count */ 1496 .port_nirqs = 4, 1497 .num_tx_queues = 4, 1498 .num_ipms = 8, 1499 .tc_cbs_supported = true, 1500 .ops = &ksz9477_dev_ops, 1501 .switch_ops = &ksz9477_switch_ops, 1502 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1503 .phy_errata_9477 = true, 1504 .mib_names = ksz9477_mib_names, 1505 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1506 .reg_mib_cnt = MIB_COUNTER_NUM, 1507 .regs = ksz9477_regs, 1508 .masks = ksz9477_masks, 1509 .shifts = ksz9477_shifts, 1510 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1511 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1512 .supports_mii = {false, false, false, false, 1513 false, true, false}, 1514 .supports_rmii = {false, false, false, false, 1515 false, true, false}, 1516 .supports_rgmii = {false, false, false, false, 1517 false, true, false}, 1518 .internal_phy = {true, true, true, true, 1519 true, false, false}, 1520 .gbit_capable = {true, true, true, true, true, true, true}, 1521 .ptp_capable = true, 1522 .sgmii_port = 7, 1523 .wr_table = &ksz9477_register_set, 1524 .rd_table = &ksz9477_register_set, 1525 }, 1526 1527 [KSZ9896] = { 1528 .chip_id = KSZ9896_CHIP_ID, 1529 .dev_name = "KSZ9896", 1530 .num_vlans = 4096, 1531 .num_alus = 4096, 1532 .num_statics = 16, 1533 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1534 .port_cnt = 6, /* total physical port count */ 1535 .port_nirqs = 2, 1536 .num_tx_queues = 4, 1537 .num_ipms = 8, 1538 .ops = &ksz9477_dev_ops, 1539 .switch_ops = &ksz9477_switch_ops, 1540 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1541 .phy_errata_9477 = true, 1542 .mib_names = ksz9477_mib_names, 1543 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1544 .reg_mib_cnt = MIB_COUNTER_NUM, 1545 .regs = ksz9477_regs, 1546 .masks = ksz9477_masks, 1547 .shifts = ksz9477_shifts, 1548 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1549 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1550 .supports_mii = {false, false, false, false, 1551 false, true}, 1552 .supports_rmii = {false, false, false, false, 1553 false, true}, 1554 .supports_rgmii = {false, false, false, false, 1555 false, true}, 1556 .internal_phy = {true, true, true, true, 1557 true, false}, 1558 .gbit_capable = {true, true, true, true, true, true}, 1559 .wr_table = &ksz9896_register_set, 1560 .rd_table = &ksz9896_register_set, 1561 }, 1562 1563 [KSZ9897] = { 1564 .chip_id = KSZ9897_CHIP_ID, 1565 .dev_name = "KSZ9897", 1566 .num_vlans = 4096, 1567 .num_alus = 4096, 1568 .num_statics = 16, 1569 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1570 .port_cnt = 7, /* total physical port count */ 1571 .port_nirqs = 2, 1572 .num_tx_queues = 4, 1573 .num_ipms = 8, 1574 .ops = &ksz9477_dev_ops, 1575 .switch_ops = &ksz9477_switch_ops, 1576 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1577 .phy_errata_9477 = true, 1578 .mib_names = ksz9477_mib_names, 1579 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1580 .reg_mib_cnt = MIB_COUNTER_NUM, 1581 .regs = ksz9477_regs, 1582 .masks = ksz9477_masks, 1583 .shifts = ksz9477_shifts, 1584 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1585 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1586 .supports_mii = {false, false, false, false, 1587 false, true, true}, 1588 .supports_rmii = {false, false, false, false, 1589 false, true, true}, 1590 .supports_rgmii = {false, false, false, false, 1591 false, true, true}, 1592 .internal_phy = {true, true, true, true, 1593 true, false, false}, 1594 .gbit_capable = {true, true, true, true, true, true, true}, 1595 }, 1596 1597 [KSZ9893] = { 1598 .chip_id = KSZ9893_CHIP_ID, 1599 .dev_name = "KSZ9893", 1600 .num_vlans = 4096, 1601 .num_alus = 4096, 1602 .num_statics = 16, 1603 .cpu_ports = 0x07, /* can be configured as cpu port */ 1604 .port_cnt = 3, /* total port count */ 1605 .port_nirqs = 2, 1606 .num_tx_queues = 4, 1607 .num_ipms = 8, 1608 .ops = &ksz9477_dev_ops, 1609 .switch_ops = &ksz9477_switch_ops, 1610 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1611 .mib_names = ksz9477_mib_names, 1612 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1613 .reg_mib_cnt = MIB_COUNTER_NUM, 1614 .regs = ksz9477_regs, 1615 .masks = ksz9477_masks, 1616 .shifts = ksz9477_shifts, 1617 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1618 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1619 .supports_mii = {false, false, true}, 1620 .supports_rmii = {false, false, true}, 1621 .supports_rgmii = {false, false, true}, 1622 .internal_phy = {true, true, false}, 1623 .gbit_capable = {true, true, true}, 1624 }, 1625 1626 [KSZ9563] = { 1627 .chip_id = KSZ9563_CHIP_ID, 1628 .dev_name = "KSZ9563", 1629 .num_vlans = 4096, 1630 .num_alus = 4096, 1631 .num_statics = 16, 1632 .cpu_ports = 0x07, /* can be configured as cpu port */ 1633 .port_cnt = 3, /* total port count */ 1634 .port_nirqs = 3, 1635 .num_tx_queues = 4, 1636 .num_ipms = 8, 1637 .tc_cbs_supported = true, 1638 .ops = &ksz9477_dev_ops, 1639 .switch_ops = &ksz9477_switch_ops, 1640 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1641 .mib_names = ksz9477_mib_names, 1642 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1643 .reg_mib_cnt = MIB_COUNTER_NUM, 1644 .regs = ksz9477_regs, 1645 .masks = ksz9477_masks, 1646 .shifts = ksz9477_shifts, 1647 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1648 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1649 .supports_mii = {false, false, true}, 1650 .supports_rmii = {false, false, true}, 1651 .supports_rgmii = {false, false, true}, 1652 .internal_phy = {true, true, false}, 1653 .gbit_capable = {true, true, true}, 1654 .ptp_capable = true, 1655 }, 1656 1657 [KSZ8567] = { 1658 .chip_id = KSZ8567_CHIP_ID, 1659 .dev_name = "KSZ8567", 1660 .num_vlans = 4096, 1661 .num_alus = 4096, 1662 .num_statics = 16, 1663 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1664 .port_cnt = 7, /* total port count */ 1665 .port_nirqs = 3, 1666 .num_tx_queues = 4, 1667 .num_ipms = 8, 1668 .tc_cbs_supported = true, 1669 .ops = &ksz9477_dev_ops, 1670 .switch_ops = &ksz9477_switch_ops, 1671 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1672 .phy_errata_9477 = true, 1673 .mib_names = ksz9477_mib_names, 1674 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1675 .reg_mib_cnt = MIB_COUNTER_NUM, 1676 .regs = ksz9477_regs, 1677 .masks = ksz9477_masks, 1678 .shifts = ksz9477_shifts, 1679 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1680 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1681 .supports_mii = {false, false, false, false, 1682 false, true, true}, 1683 .supports_rmii = {false, false, false, false, 1684 false, true, true}, 1685 .supports_rgmii = {false, false, false, false, 1686 false, true, true}, 1687 .internal_phy = {true, true, true, true, 1688 true, false, false}, 1689 .gbit_capable = {false, false, false, false, false, 1690 true, true}, 1691 .ptp_capable = true, 1692 }, 1693 1694 [KSZ9567] = { 1695 .chip_id = KSZ9567_CHIP_ID, 1696 .dev_name = "KSZ9567", 1697 .num_vlans = 4096, 1698 .num_alus = 4096, 1699 .num_statics = 16, 1700 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1701 .port_cnt = 7, /* total physical port count */ 1702 .port_nirqs = 3, 1703 .num_tx_queues = 4, 1704 .num_ipms = 8, 1705 .tc_cbs_supported = true, 1706 .ops = &ksz9477_dev_ops, 1707 .switch_ops = &ksz9477_switch_ops, 1708 .mib_names = ksz9477_mib_names, 1709 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1710 .reg_mib_cnt = MIB_COUNTER_NUM, 1711 .regs = ksz9477_regs, 1712 .masks = ksz9477_masks, 1713 .shifts = ksz9477_shifts, 1714 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1715 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1716 .supports_mii = {false, false, false, false, 1717 false, true, true}, 1718 .supports_rmii = {false, false, false, false, 1719 false, true, true}, 1720 .supports_rgmii = {false, false, false, false, 1721 false, true, true}, 1722 .internal_phy = {true, true, true, true, 1723 true, false, false}, 1724 .gbit_capable = {true, true, true, true, true, true, true}, 1725 .ptp_capable = true, 1726 }, 1727 1728 [LAN9370] = { 1729 .chip_id = LAN9370_CHIP_ID, 1730 .dev_name = "LAN9370", 1731 .num_vlans = 4096, 1732 .num_alus = 1024, 1733 .num_statics = 256, 1734 .cpu_ports = 0x10, /* can be configured as cpu port */ 1735 .port_cnt = 5, /* total physical port count */ 1736 .port_nirqs = 6, 1737 .num_tx_queues = 8, 1738 .num_ipms = 8, 1739 .tc_cbs_supported = true, 1740 .phy_side_mdio_supported = true, 1741 .ops = &lan937x_dev_ops, 1742 .switch_ops = &lan937x_switch_ops, 1743 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1744 .mib_names = ksz9477_mib_names, 1745 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1746 .reg_mib_cnt = MIB_COUNTER_NUM, 1747 .regs = ksz9477_regs, 1748 .masks = lan937x_masks, 1749 .shifts = lan937x_shifts, 1750 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1751 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1752 .supports_mii = {false, false, false, false, true}, 1753 .supports_rmii = {false, false, false, false, true}, 1754 .supports_rgmii = {false, false, false, false, true}, 1755 .internal_phy = {true, true, true, true, false}, 1756 .ptp_capable = true, 1757 }, 1758 1759 [LAN9371] = { 1760 .chip_id = LAN9371_CHIP_ID, 1761 .dev_name = "LAN9371", 1762 .num_vlans = 4096, 1763 .num_alus = 1024, 1764 .num_statics = 256, 1765 .cpu_ports = 0x30, /* can be configured as cpu port */ 1766 .port_cnt = 6, /* total physical port count */ 1767 .port_nirqs = 6, 1768 .num_tx_queues = 8, 1769 .num_ipms = 8, 1770 .tc_cbs_supported = true, 1771 .phy_side_mdio_supported = true, 1772 .ops = &lan937x_dev_ops, 1773 .switch_ops = &lan937x_switch_ops, 1774 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1775 .mib_names = ksz9477_mib_names, 1776 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1777 .reg_mib_cnt = MIB_COUNTER_NUM, 1778 .regs = ksz9477_regs, 1779 .masks = lan937x_masks, 1780 .shifts = lan937x_shifts, 1781 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1782 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1783 .supports_mii = {false, false, false, false, true, true}, 1784 .supports_rmii = {false, false, false, false, true, true}, 1785 .supports_rgmii = {false, false, false, false, true, true}, 1786 .internal_phy = {true, true, true, true, false, false}, 1787 .ptp_capable = true, 1788 }, 1789 1790 [LAN9372] = { 1791 .chip_id = LAN9372_CHIP_ID, 1792 .dev_name = "LAN9372", 1793 .num_vlans = 4096, 1794 .num_alus = 1024, 1795 .num_statics = 256, 1796 .cpu_ports = 0x30, /* can be configured as cpu port */ 1797 .port_cnt = 8, /* total physical port count */ 1798 .port_nirqs = 6, 1799 .num_tx_queues = 8, 1800 .num_ipms = 8, 1801 .tc_cbs_supported = true, 1802 .phy_side_mdio_supported = true, 1803 .ops = &lan937x_dev_ops, 1804 .switch_ops = &lan937x_switch_ops, 1805 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1806 .mib_names = ksz9477_mib_names, 1807 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1808 .reg_mib_cnt = MIB_COUNTER_NUM, 1809 .regs = ksz9477_regs, 1810 .masks = lan937x_masks, 1811 .shifts = lan937x_shifts, 1812 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1813 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1814 .supports_mii = {false, false, false, false, 1815 true, true, false, false}, 1816 .supports_rmii = {false, false, false, false, 1817 true, true, false, false}, 1818 .supports_rgmii = {false, false, false, false, 1819 true, true, false, false}, 1820 .internal_phy = {true, true, true, true, 1821 false, false, true, true}, 1822 .ptp_capable = true, 1823 }, 1824 1825 [LAN9373] = { 1826 .chip_id = LAN9373_CHIP_ID, 1827 .dev_name = "LAN9373", 1828 .num_vlans = 4096, 1829 .num_alus = 1024, 1830 .num_statics = 256, 1831 .cpu_ports = 0x38, /* can be configured as cpu port */ 1832 .port_cnt = 5, /* total physical port count */ 1833 .port_nirqs = 6, 1834 .num_tx_queues = 8, 1835 .num_ipms = 8, 1836 .tc_cbs_supported = true, 1837 .phy_side_mdio_supported = true, 1838 .ops = &lan937x_dev_ops, 1839 .switch_ops = &lan937x_switch_ops, 1840 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1841 .mib_names = ksz9477_mib_names, 1842 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1843 .reg_mib_cnt = MIB_COUNTER_NUM, 1844 .regs = ksz9477_regs, 1845 .masks = lan937x_masks, 1846 .shifts = lan937x_shifts, 1847 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1848 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1849 .supports_mii = {false, false, false, false, 1850 true, true, false, false}, 1851 .supports_rmii = {false, false, false, false, 1852 true, true, false, false}, 1853 .supports_rgmii = {false, false, false, false, 1854 true, true, false, false}, 1855 .internal_phy = {true, true, true, false, 1856 false, false, true, true}, 1857 .ptp_capable = true, 1858 }, 1859 1860 [LAN9374] = { 1861 .chip_id = LAN9374_CHIP_ID, 1862 .dev_name = "LAN9374", 1863 .num_vlans = 4096, 1864 .num_alus = 1024, 1865 .num_statics = 256, 1866 .cpu_ports = 0x30, /* can be configured as cpu port */ 1867 .port_cnt = 8, /* total physical port count */ 1868 .port_nirqs = 6, 1869 .num_tx_queues = 8, 1870 .num_ipms = 8, 1871 .tc_cbs_supported = true, 1872 .phy_side_mdio_supported = true, 1873 .ops = &lan937x_dev_ops, 1874 .switch_ops = &lan937x_switch_ops, 1875 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1876 .mib_names = ksz9477_mib_names, 1877 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1878 .reg_mib_cnt = MIB_COUNTER_NUM, 1879 .regs = ksz9477_regs, 1880 .masks = lan937x_masks, 1881 .shifts = lan937x_shifts, 1882 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1883 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1884 .supports_mii = {false, false, false, false, 1885 true, true, false, false}, 1886 .supports_rmii = {false, false, false, false, 1887 true, true, false, false}, 1888 .supports_rgmii = {false, false, false, false, 1889 true, true, false, false}, 1890 .internal_phy = {true, true, true, true, 1891 false, false, true, true}, 1892 .ptp_capable = true, 1893 }, 1894 1895 [LAN9646] = { 1896 .chip_id = LAN9646_CHIP_ID, 1897 .dev_name = "LAN9646", 1898 .num_vlans = 4096, 1899 .num_alus = 4096, 1900 .num_statics = 16, 1901 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1902 .port_cnt = 7, /* total physical port count */ 1903 .port_nirqs = 4, 1904 .num_tx_queues = 4, 1905 .num_ipms = 8, 1906 .ops = &ksz9477_dev_ops, 1907 .switch_ops = &ksz9477_switch_ops, 1908 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1909 .phy_errata_9477 = true, 1910 .mib_names = ksz9477_mib_names, 1911 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1912 .reg_mib_cnt = MIB_COUNTER_NUM, 1913 .regs = ksz9477_regs, 1914 .masks = ksz9477_masks, 1915 .shifts = ksz9477_shifts, 1916 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1917 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1918 .supports_mii = {false, false, false, false, 1919 false, true, true}, 1920 .supports_rmii = {false, false, false, false, 1921 false, true, true}, 1922 .supports_rgmii = {false, false, false, false, 1923 false, true, true}, 1924 .internal_phy = {true, true, true, true, 1925 true, false, false}, 1926 .gbit_capable = {true, true, true, true, true, true, true}, 1927 .sgmii_port = 7, 1928 .wr_table = &ksz9477_register_set, 1929 .rd_table = &ksz9477_register_set, 1930 }, 1931 }; 1932 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1933 1934 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1935 { 1936 int i; 1937 1938 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1939 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1940 1941 if (chip->chip_id == prod_num) 1942 return chip; 1943 } 1944 1945 return NULL; 1946 } 1947 1948 static int ksz_check_device_id(struct ksz_device *dev) 1949 { 1950 const struct ksz_chip_data *expected_chip_data; 1951 u32 expected_chip_id; 1952 1953 if (dev->pdata) { 1954 expected_chip_id = dev->pdata->chip_id; 1955 expected_chip_data = ksz_lookup_info(expected_chip_id); 1956 if (WARN_ON(!expected_chip_data)) 1957 return -ENODEV; 1958 } else { 1959 expected_chip_data = of_device_get_match_data(dev->dev); 1960 expected_chip_id = expected_chip_data->chip_id; 1961 } 1962 1963 if (expected_chip_id != dev->chip_id) { 1964 dev_err(dev->dev, 1965 "Device tree specifies chip %s but found %s, please fix it!\n", 1966 expected_chip_data->dev_name, dev->info->dev_name); 1967 return -ENODEV; 1968 } 1969 1970 return 0; 1971 } 1972 1973 void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1974 struct phylink_config *config) 1975 { 1976 struct ksz_device *dev = ds->priv; 1977 1978 if (dev->info->supports_mii[port]) 1979 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1980 1981 if (dev->info->supports_rmii[port]) 1982 __set_bit(PHY_INTERFACE_MODE_RMII, 1983 config->supported_interfaces); 1984 1985 if (dev->info->supports_rgmii[port]) 1986 phy_interface_set_rgmii(config->supported_interfaces); 1987 1988 if (dev->info->internal_phy[port]) { 1989 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1990 config->supported_interfaces); 1991 /* Compatibility for phylib's default interface type when the 1992 * phy-mode property is absent 1993 */ 1994 __set_bit(PHY_INTERFACE_MODE_GMII, 1995 config->supported_interfaces); 1996 } 1997 1998 if (ds->ops->support_eee && ds->ops->support_eee(ds, port)) { 1999 memcpy(config->lpi_interfaces, config->supported_interfaces, 2000 sizeof(config->lpi_interfaces)); 2001 2002 config->lpi_capabilities = MAC_100FD; 2003 if (dev->info->gbit_capable[port]) 2004 config->lpi_capabilities |= MAC_1000FD; 2005 2006 /* EEE is fully operational */ 2007 config->eee_enabled_default = true; 2008 } 2009 } 2010 2011 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 2012 { 2013 struct ethtool_pause_stats *pstats; 2014 struct rtnl_link_stats64 *stats; 2015 struct ksz_stats_raw *raw; 2016 struct ksz_port_mib *mib; 2017 int ret; 2018 2019 mib = &dev->ports[port].mib; 2020 stats = &mib->stats64; 2021 pstats = &mib->pause_stats; 2022 raw = (struct ksz_stats_raw *)mib->counters; 2023 2024 spin_lock(&mib->stats64_lock); 2025 2026 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 2027 raw->rx_pause; 2028 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2029 raw->tx_pause; 2030 2031 /* HW counters are counting bytes + FCS which is not acceptable 2032 * for rtnl_link_stats64 interface 2033 */ 2034 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 2035 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 2036 2037 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2038 raw->rx_oversize; 2039 2040 stats->rx_crc_errors = raw->rx_crc_err; 2041 stats->rx_frame_errors = raw->rx_align_err; 2042 stats->rx_dropped = raw->rx_discards; 2043 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2044 stats->rx_frame_errors + stats->rx_dropped; 2045 2046 stats->tx_window_errors = raw->tx_late_col; 2047 stats->tx_fifo_errors = raw->tx_discards; 2048 stats->tx_aborted_errors = raw->tx_exc_col; 2049 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2050 stats->tx_aborted_errors; 2051 2052 stats->multicast = raw->rx_mcast; 2053 stats->collisions = raw->tx_total_col; 2054 2055 pstats->tx_pause_frames = raw->tx_pause; 2056 pstats->rx_pause_frames = raw->rx_pause; 2057 2058 spin_unlock(&mib->stats64_lock); 2059 2060 if (dev->info->phy_errata_9477 && !ksz_is_sgmii_port(dev, port)) { 2061 ret = ksz9477_errata_monitor(dev, port, raw->tx_late_col); 2062 if (ret) 2063 dev_err(dev->dev, "Failed to monitor transmission halt\n"); 2064 } 2065 } 2066 2067 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 2068 { 2069 struct ethtool_pause_stats *pstats; 2070 struct rtnl_link_stats64 *stats; 2071 struct ksz88xx_stats_raw *raw; 2072 struct ksz_port_mib *mib; 2073 2074 mib = &dev->ports[port].mib; 2075 stats = &mib->stats64; 2076 pstats = &mib->pause_stats; 2077 raw = (struct ksz88xx_stats_raw *)mib->counters; 2078 2079 spin_lock(&mib->stats64_lock); 2080 2081 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 2082 raw->rx_pause; 2083 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2084 raw->tx_pause; 2085 2086 /* HW counters are counting bytes + FCS which is not acceptable 2087 * for rtnl_link_stats64 interface 2088 */ 2089 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 2090 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 2091 2092 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2093 raw->rx_oversize; 2094 2095 stats->rx_crc_errors = raw->rx_crc_err; 2096 stats->rx_frame_errors = raw->rx_align_err; 2097 stats->rx_dropped = raw->rx_discards; 2098 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2099 stats->rx_frame_errors + stats->rx_dropped; 2100 2101 stats->tx_window_errors = raw->tx_late_col; 2102 stats->tx_fifo_errors = raw->tx_discards; 2103 stats->tx_aborted_errors = raw->tx_exc_col; 2104 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2105 stats->tx_aborted_errors; 2106 2107 stats->multicast = raw->rx_mcast; 2108 stats->collisions = raw->tx_total_col; 2109 2110 pstats->tx_pause_frames = raw->tx_pause; 2111 pstats->rx_pause_frames = raw->rx_pause; 2112 2113 spin_unlock(&mib->stats64_lock); 2114 } 2115 2116 void ksz_get_stats64(struct dsa_switch *ds, int port, 2117 struct rtnl_link_stats64 *s) 2118 { 2119 struct ksz_device *dev = ds->priv; 2120 struct ksz_port_mib *mib; 2121 2122 mib = &dev->ports[port].mib; 2123 2124 spin_lock(&mib->stats64_lock); 2125 memcpy(s, &mib->stats64, sizeof(*s)); 2126 spin_unlock(&mib->stats64_lock); 2127 } 2128 2129 void ksz_get_pause_stats(struct dsa_switch *ds, int port, 2130 struct ethtool_pause_stats *pause_stats) 2131 { 2132 struct ksz_device *dev = ds->priv; 2133 struct ksz_port_mib *mib; 2134 2135 mib = &dev->ports[port].mib; 2136 2137 spin_lock(&mib->stats64_lock); 2138 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 2139 spin_unlock(&mib->stats64_lock); 2140 } 2141 2142 void ksz_get_strings(struct dsa_switch *ds, int port, 2143 u32 stringset, uint8_t *buf) 2144 { 2145 struct ksz_device *dev = ds->priv; 2146 int i; 2147 2148 if (stringset != ETH_SS_STATS) 2149 return; 2150 2151 for (i = 0; i < dev->info->mib_cnt; i++) 2152 ethtool_puts(&buf, dev->info->mib_names[i].string); 2153 } 2154 2155 /** 2156 * ksz_update_port_member - Adjust port forwarding rules based on STP state and 2157 * isolation settings. 2158 * @dev: A pointer to the struct ksz_device representing the device. 2159 * @port: The port number to adjust. 2160 * 2161 * This function dynamically adjusts the port membership configuration for a 2162 * specified port and other device ports, based on Spanning Tree Protocol (STP) 2163 * states and port isolation settings. Each port, including the CPU port, has a 2164 * membership register, represented as a bitfield, where each bit corresponds 2165 * to a port number. A set bit indicates permission to forward frames to that 2166 * port. This function iterates over all ports, updating the membership register 2167 * to reflect current forwarding permissions: 2168 * 2169 * 1. Forwards frames only to ports that are part of the same bridge group and 2170 * in the BR_STATE_FORWARDING state. 2171 * 2. Takes into account the isolation status of ports; ports in the 2172 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward 2173 * frames to each other, even if they are in the same bridge group. 2174 * 3. Ensures that the CPU port is included in the membership based on its 2175 * upstream port configuration, allowing for management and control traffic 2176 * to flow as required. 2177 */ 2178 static void ksz_update_port_member(struct ksz_device *dev, int port) 2179 { 2180 struct ksz_port *p = &dev->ports[port]; 2181 struct dsa_switch *ds = dev->ds; 2182 u8 port_member = 0, cpu_port; 2183 const struct dsa_port *dp; 2184 int i, j; 2185 2186 if (!dsa_is_user_port(ds, port)) 2187 return; 2188 2189 dp = dsa_to_port(ds, port); 2190 cpu_port = BIT(dsa_upstream_port(ds, port)); 2191 2192 for (i = 0; i < ds->num_ports; i++) { 2193 const struct dsa_port *other_dp = dsa_to_port(ds, i); 2194 struct ksz_port *other_p = &dev->ports[i]; 2195 u8 val = 0; 2196 2197 if (!dsa_is_user_port(ds, i)) 2198 continue; 2199 if (port == i) 2200 continue; 2201 if (!dsa_port_bridge_same(dp, other_dp)) 2202 continue; 2203 if (other_p->stp_state != BR_STATE_FORWARDING) 2204 continue; 2205 2206 /* At this point we know that "port" and "other" port [i] are in 2207 * the same bridge group and that "other" port [i] is in 2208 * forwarding stp state. If "port" is also in forwarding stp 2209 * state, we can allow forwarding from port [port] to port [i]. 2210 * Except if both ports are isolated. 2211 */ 2212 if (p->stp_state == BR_STATE_FORWARDING && 2213 !(p->isolated && other_p->isolated)) { 2214 val |= BIT(port); 2215 port_member |= BIT(i); 2216 } 2217 2218 /* Retain port [i]'s relationship to other ports than [port] */ 2219 for (j = 0; j < ds->num_ports; j++) { 2220 const struct dsa_port *third_dp; 2221 struct ksz_port *third_p; 2222 2223 if (j == i) 2224 continue; 2225 if (j == port) 2226 continue; 2227 if (!dsa_is_user_port(ds, j)) 2228 continue; 2229 third_p = &dev->ports[j]; 2230 if (third_p->stp_state != BR_STATE_FORWARDING) 2231 continue; 2232 2233 third_dp = dsa_to_port(ds, j); 2234 2235 /* Now we updating relation of the "other" port [i] to 2236 * the "third" port [j]. We already know that "other" 2237 * port [i] is in forwarding stp state and that "third" 2238 * port [j] is in forwarding stp state too. 2239 * We need to check if "other" port [i] and "third" port 2240 * [j] are in the same bridge group and not isolated 2241 * before allowing forwarding from port [i] to port [j]. 2242 */ 2243 if (dsa_port_bridge_same(other_dp, third_dp) && 2244 !(other_p->isolated && third_p->isolated)) 2245 val |= BIT(j); 2246 } 2247 2248 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 2249 } 2250 2251 /* HSR ports are setup once so need to use the assigned membership 2252 * when the port is enabled. 2253 */ 2254 if (!port_member && p->stp_state == BR_STATE_FORWARDING && 2255 (dev->hsr_ports & BIT(port))) 2256 port_member = dev->hsr_ports; 2257 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 2258 } 2259 2260 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 2261 { 2262 struct ksz_device *dev = bus->priv; 2263 u16 val; 2264 int ret; 2265 2266 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 2267 if (ret < 0) 2268 return ret; 2269 2270 return val; 2271 } 2272 2273 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 2274 u16 val) 2275 { 2276 struct ksz_device *dev = bus->priv; 2277 2278 return dev->dev_ops->w_phy(dev, addr, regnum, val); 2279 } 2280 2281 /** 2282 * ksz_parent_mdio_read - Read data from a PHY register on the parent MDIO bus. 2283 * @bus: MDIO bus structure. 2284 * @addr: PHY address on the parent MDIO bus. 2285 * @regnum: Register number to read. 2286 * 2287 * This function provides a direct read operation on the parent MDIO bus for 2288 * accessing PHY registers. By bypassing SPI or I2C, it uses the parent MDIO bus 2289 * to retrieve data from the PHY registers at the specified address and register 2290 * number. 2291 * 2292 * Return: Value of the PHY register, or a negative error code on failure. 2293 */ 2294 static int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum) 2295 { 2296 struct ksz_device *dev = bus->priv; 2297 2298 return mdiobus_read_nested(dev->parent_mdio_bus, addr, regnum); 2299 } 2300 2301 /** 2302 * ksz_parent_mdio_write - Write data to a PHY register on the parent MDIO bus. 2303 * @bus: MDIO bus structure. 2304 * @addr: PHY address on the parent MDIO bus. 2305 * @regnum: Register number to write to. 2306 * @val: Value to write to the PHY register. 2307 * 2308 * This function provides a direct write operation on the parent MDIO bus for 2309 * accessing PHY registers. Bypassing SPI or I2C, it uses the parent MDIO bus 2310 * to modify the PHY register values at the specified address. 2311 * 2312 * Return: 0 on success, or a negative error code on failure. 2313 */ 2314 static int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum, 2315 u16 val) 2316 { 2317 struct ksz_device *dev = bus->priv; 2318 2319 return mdiobus_write_nested(dev->parent_mdio_bus, addr, regnum, val); 2320 } 2321 2322 /** 2323 * ksz_phy_addr_to_port - Map a PHY address to the corresponding switch port. 2324 * @dev: Pointer to device structure. 2325 * @addr: PHY address to map to a port. 2326 * 2327 * This function finds the corresponding switch port for a given PHY address by 2328 * iterating over all user ports on the device. It checks if a port's PHY 2329 * address in `phy_addr_map` matches the specified address and if the port 2330 * contains an internal PHY. If a match is found, the index of the port is 2331 * returned. 2332 * 2333 * Return: Port index on success, or -EINVAL if no matching port is found. 2334 */ 2335 static int ksz_phy_addr_to_port(struct ksz_device *dev, int addr) 2336 { 2337 struct dsa_switch *ds = dev->ds; 2338 struct dsa_port *dp; 2339 2340 dsa_switch_for_each_user_port(dp, ds) { 2341 if (dev->info->internal_phy[dp->index] && 2342 dev->phy_addr_map[dp->index] == addr) 2343 return dp->index; 2344 } 2345 2346 return -EINVAL; 2347 } 2348 2349 /** 2350 * ksz_irq_phy_setup - Configure IRQs for PHYs in the KSZ device. 2351 * @dev: Pointer to the KSZ device structure. 2352 * 2353 * Sets up IRQs for each active PHY connected to the KSZ switch by mapping the 2354 * appropriate IRQs for each PHY and assigning them to the `user_mii_bus` in 2355 * the DSA switch structure. Each IRQ is mapped based on the port's IRQ domain. 2356 * 2357 * Return: 0 on success, or a negative error code on failure. 2358 */ 2359 static int ksz_irq_phy_setup(struct ksz_device *dev) 2360 { 2361 struct dsa_switch *ds = dev->ds; 2362 int phy, port; 2363 int irq; 2364 int ret; 2365 2366 for (phy = 0; phy < PHY_MAX_ADDR; phy++) { 2367 if (BIT(phy) & ds->phys_mii_mask) { 2368 port = ksz_phy_addr_to_port(dev, phy); 2369 if (port < 0) { 2370 ret = port; 2371 goto out; 2372 } 2373 2374 irq = irq_find_mapping(dev->ports[port].pirq.domain, 2375 PORT_SRC_PHY_INT); 2376 if (!irq) { 2377 ret = -EINVAL; 2378 goto out; 2379 } 2380 ds->user_mii_bus->irq[phy] = irq; 2381 } 2382 } 2383 return 0; 2384 out: 2385 while (phy--) 2386 if (BIT(phy) & ds->phys_mii_mask) 2387 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2388 2389 return ret; 2390 } 2391 2392 /** 2393 * ksz_irq_phy_free - Release IRQ mappings for PHYs in the KSZ device. 2394 * @dev: Pointer to the KSZ device structure. 2395 * 2396 * Releases any IRQ mappings previously assigned to active PHYs in the KSZ 2397 * switch by disposing of each mapped IRQ in the `user_mii_bus` structure. 2398 */ 2399 static void ksz_irq_phy_free(struct ksz_device *dev) 2400 { 2401 struct dsa_switch *ds = dev->ds; 2402 int phy; 2403 2404 for (phy = 0; phy < PHY_MAX_ADDR; phy++) 2405 if (BIT(phy) & ds->phys_mii_mask) 2406 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2407 } 2408 2409 /** 2410 * ksz_parse_dt_phy_config - Parse and validate PHY configuration from DT 2411 * @dev: pointer to the KSZ device structure 2412 * @bus: pointer to the MII bus structure 2413 * @mdio_np: pointer to the MDIO node in the device tree 2414 * 2415 * This function parses and validates PHY configurations for each user port 2416 * defined in the device tree for a KSZ switch device. It verifies that the 2417 * `phy-handle` properties are correctly set and that the internal PHYs match 2418 * expected addresses and parent nodes. Sets up the PHY mask in the MII bus if 2419 * all validations pass. Logs error messages for any mismatches or missing data. 2420 * 2421 * Return: 0 on success, or a negative error code on failure. 2422 */ 2423 static int ksz_parse_dt_phy_config(struct ksz_device *dev, struct mii_bus *bus, 2424 struct device_node *mdio_np) 2425 { 2426 struct device_node *phy_node, *phy_parent_node; 2427 bool phys_are_valid = true; 2428 struct dsa_port *dp; 2429 u32 phy_addr; 2430 int ret; 2431 2432 dsa_switch_for_each_user_port(dp, dev->ds) { 2433 if (!dev->info->internal_phy[dp->index]) 2434 continue; 2435 2436 phy_node = of_parse_phandle(dp->dn, "phy-handle", 0); 2437 if (!phy_node) { 2438 dev_err(dev->dev, "failed to parse phy-handle for port %d.\n", 2439 dp->index); 2440 phys_are_valid = false; 2441 continue; 2442 } 2443 2444 phy_parent_node = of_get_parent(phy_node); 2445 if (!phy_parent_node) { 2446 dev_err(dev->dev, "failed to get PHY-parent node for port %d\n", 2447 dp->index); 2448 phys_are_valid = false; 2449 } else if (phy_parent_node != mdio_np) { 2450 dev_err(dev->dev, "PHY-parent node mismatch for port %d, expected %pOF, got %pOF\n", 2451 dp->index, mdio_np, phy_parent_node); 2452 phys_are_valid = false; 2453 } else { 2454 ret = of_property_read_u32(phy_node, "reg", &phy_addr); 2455 if (ret < 0) { 2456 dev_err(dev->dev, "failed to read PHY address for port %d. Error %d\n", 2457 dp->index, ret); 2458 phys_are_valid = false; 2459 } else if (phy_addr != dev->phy_addr_map[dp->index]) { 2460 dev_err(dev->dev, "PHY address mismatch for port %d, expected 0x%x, got 0x%x\n", 2461 dp->index, dev->phy_addr_map[dp->index], 2462 phy_addr); 2463 phys_are_valid = false; 2464 } else { 2465 bus->phy_mask |= BIT(phy_addr); 2466 } 2467 } 2468 2469 of_node_put(phy_node); 2470 of_node_put(phy_parent_node); 2471 } 2472 2473 if (!phys_are_valid) 2474 return -EINVAL; 2475 2476 return 0; 2477 } 2478 2479 /** 2480 * ksz_mdio_register - Register and configure the MDIO bus for the KSZ device. 2481 * @dev: Pointer to the KSZ device structure. 2482 * 2483 * This function sets up and registers an MDIO bus for the KSZ switch device, 2484 * allowing access to its internal PHYs. If the device supports side MDIO, 2485 * the function will configure the external MDIO controller specified by the 2486 * "mdio-parent-bus" device tree property to directly manage internal PHYs. 2487 * Otherwise, SPI or I2C access is set up for PHY access. 2488 * 2489 * Return: 0 on success, or a negative error code on failure. 2490 */ 2491 static int ksz_mdio_register(struct ksz_device *dev) 2492 { 2493 struct device_node *parent_bus_node; 2494 struct mii_bus *parent_bus = NULL; 2495 struct dsa_switch *ds = dev->ds; 2496 struct device_node *mdio_np; 2497 struct mii_bus *bus; 2498 int ret, i; 2499 2500 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 2501 if (!mdio_np) 2502 return 0; 2503 2504 parent_bus_node = of_parse_phandle(mdio_np, "mdio-parent-bus", 0); 2505 if (parent_bus_node && !dev->info->phy_side_mdio_supported) { 2506 dev_err(dev->dev, "Side MDIO bus is not supported for this HW, ignoring 'mdio-parent-bus' property.\n"); 2507 ret = -EINVAL; 2508 2509 goto put_mdio_node; 2510 } else if (parent_bus_node) { 2511 parent_bus = of_mdio_find_bus(parent_bus_node); 2512 if (!parent_bus) { 2513 ret = -EPROBE_DEFER; 2514 2515 goto put_mdio_node; 2516 } 2517 2518 dev->parent_mdio_bus = parent_bus; 2519 } 2520 2521 bus = devm_mdiobus_alloc(ds->dev); 2522 if (!bus) { 2523 ret = -ENOMEM; 2524 goto put_mdio_node; 2525 } 2526 2527 if (dev->dev_ops->mdio_bus_preinit) { 2528 ret = dev->dev_ops->mdio_bus_preinit(dev, !!parent_bus); 2529 if (ret) 2530 goto put_mdio_node; 2531 } 2532 2533 if (dev->dev_ops->create_phy_addr_map) { 2534 ret = dev->dev_ops->create_phy_addr_map(dev, !!parent_bus); 2535 if (ret) 2536 goto put_mdio_node; 2537 } else { 2538 for (i = 0; i < dev->info->port_cnt; i++) 2539 dev->phy_addr_map[i] = i; 2540 } 2541 2542 bus->priv = dev; 2543 if (parent_bus) { 2544 bus->read = ksz_parent_mdio_read; 2545 bus->write = ksz_parent_mdio_write; 2546 bus->name = "KSZ side MDIO"; 2547 snprintf(bus->id, MII_BUS_ID_SIZE, "ksz-side-mdio-%d", 2548 ds->index); 2549 } else { 2550 bus->read = ksz_sw_mdio_read; 2551 bus->write = ksz_sw_mdio_write; 2552 bus->name = "ksz user smi"; 2553 if (ds->dst->index != 0) { 2554 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d-%d", ds->dst->index, ds->index); 2555 } else { 2556 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 2557 } 2558 } 2559 2560 ret = ksz_parse_dt_phy_config(dev, bus, mdio_np); 2561 if (ret) 2562 goto put_mdio_node; 2563 2564 ds->phys_mii_mask = bus->phy_mask; 2565 bus->parent = ds->dev; 2566 2567 ds->user_mii_bus = bus; 2568 2569 if (dev->irq > 0) { 2570 ret = ksz_irq_phy_setup(dev); 2571 if (ret) 2572 goto put_mdio_node; 2573 } 2574 2575 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 2576 if (ret) { 2577 dev_err(ds->dev, "unable to register MDIO bus %s\n", 2578 bus->id); 2579 if (dev->irq > 0) 2580 ksz_irq_phy_free(dev); 2581 } 2582 2583 put_mdio_node: 2584 of_node_put(mdio_np); 2585 of_node_put(parent_bus_node); 2586 2587 return ret; 2588 } 2589 2590 static void ksz_irq_mask(struct irq_data *d) 2591 { 2592 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2593 2594 kirq->masked |= BIT(d->hwirq); 2595 } 2596 2597 static void ksz_irq_unmask(struct irq_data *d) 2598 { 2599 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2600 2601 kirq->masked &= ~BIT(d->hwirq); 2602 } 2603 2604 static void ksz_irq_bus_lock(struct irq_data *d) 2605 { 2606 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2607 2608 mutex_lock(&kirq->dev->lock_irq); 2609 } 2610 2611 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 2612 { 2613 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2614 struct ksz_device *dev = kirq->dev; 2615 int ret; 2616 2617 ret = ksz_write8(dev, kirq->reg_mask, kirq->masked); 2618 if (ret) 2619 dev_err(dev->dev, "failed to change IRQ mask\n"); 2620 2621 mutex_unlock(&dev->lock_irq); 2622 } 2623 2624 static const struct irq_chip ksz_irq_chip = { 2625 .name = "ksz-irq", 2626 .irq_mask = ksz_irq_mask, 2627 .irq_unmask = ksz_irq_unmask, 2628 .irq_bus_lock = ksz_irq_bus_lock, 2629 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 2630 }; 2631 2632 static int ksz_irq_domain_map(struct irq_domain *d, 2633 unsigned int irq, irq_hw_number_t hwirq) 2634 { 2635 irq_set_chip_data(irq, d->host_data); 2636 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 2637 irq_set_noprobe(irq); 2638 2639 return 0; 2640 } 2641 2642 static const struct irq_domain_ops ksz_irq_domain_ops = { 2643 .map = ksz_irq_domain_map, 2644 .xlate = irq_domain_xlate_twocell, 2645 }; 2646 2647 static void ksz_irq_free(struct ksz_irq *kirq) 2648 { 2649 int irq, virq; 2650 2651 free_irq(kirq->irq_num, kirq); 2652 2653 for (irq = 0; irq < kirq->nirqs; irq++) { 2654 virq = irq_find_mapping(kirq->domain, irq); 2655 irq_dispose_mapping(virq); 2656 } 2657 2658 irq_domain_remove(kirq->domain); 2659 } 2660 2661 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 2662 { 2663 struct ksz_irq *kirq = dev_id; 2664 unsigned int nhandled = 0; 2665 struct ksz_device *dev; 2666 unsigned int sub_irq; 2667 u8 data; 2668 int ret; 2669 u8 n; 2670 2671 dev = kirq->dev; 2672 2673 /* Read interrupt status register */ 2674 ret = ksz_read8(dev, kirq->reg_status, &data); 2675 if (ret) 2676 goto out; 2677 2678 for (n = 0; n < kirq->nirqs; ++n) { 2679 if (data & BIT(n)) { 2680 sub_irq = irq_find_mapping(kirq->domain, n); 2681 handle_nested_irq(sub_irq); 2682 ++nhandled; 2683 } 2684 } 2685 out: 2686 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2687 } 2688 2689 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 2690 { 2691 int ret, n; 2692 2693 kirq->dev = dev; 2694 2695 kirq->domain = irq_domain_create_simple(dev_fwnode(dev->dev), kirq->nirqs, 0, 2696 &ksz_irq_domain_ops, kirq); 2697 if (!kirq->domain) 2698 return -ENOMEM; 2699 2700 for (n = 0; n < kirq->nirqs; n++) 2701 irq_create_mapping(kirq->domain, n); 2702 2703 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2704 IRQF_ONESHOT, kirq->name, kirq); 2705 if (ret) 2706 goto out; 2707 2708 return 0; 2709 2710 out: 2711 ksz_irq_free(kirq); 2712 2713 return ret; 2714 } 2715 2716 static int ksz_girq_setup(struct ksz_device *dev) 2717 { 2718 struct ksz_irq *girq = &dev->girq; 2719 2720 girq->nirqs = dev->info->port_cnt; 2721 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2722 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2723 girq->masked = ~0; 2724 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2725 2726 girq->irq_num = dev->irq; 2727 2728 return ksz_irq_common_setup(dev, girq); 2729 } 2730 2731 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2732 { 2733 struct ksz_irq *pirq = &dev->ports[p].pirq; 2734 2735 pirq->nirqs = dev->info->port_nirqs; 2736 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2737 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2738 pirq->masked = ~0; 2739 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2740 2741 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2742 if (!pirq->irq_num) 2743 return -EINVAL; 2744 2745 return ksz_irq_common_setup(dev, pirq); 2746 } 2747 2748 static int ksz_parse_drive_strength(struct ksz_device *dev); 2749 2750 int ksz_setup(struct dsa_switch *ds) 2751 { 2752 struct ksz_device *dev = ds->priv; 2753 u16 storm_mask, storm_rate; 2754 struct dsa_port *dp; 2755 struct ksz_port *p; 2756 const u16 *regs; 2757 int ret; 2758 2759 regs = dev->info->regs; 2760 2761 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2762 dev->info->num_vlans, GFP_KERNEL); 2763 if (!dev->vlan_cache) 2764 return -ENOMEM; 2765 2766 ret = dev->dev_ops->reset(dev); 2767 if (ret) { 2768 dev_err(ds->dev, "failed to reset switch\n"); 2769 return ret; 2770 } 2771 2772 ret = ksz_parse_drive_strength(dev); 2773 if (ret) 2774 return ret; 2775 2776 if (ksz_has_sgmii_port(dev) && dev->dev_ops->pcs_create) { 2777 ret = dev->dev_ops->pcs_create(dev); 2778 if (ret) 2779 return ret; 2780 } 2781 2782 /* set broadcast storm protection 10% rate */ 2783 storm_mask = BROADCAST_STORM_RATE; 2784 storm_rate = (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100; 2785 if (ksz_is_ksz8463(dev)) { 2786 storm_mask = swab16(storm_mask); 2787 storm_rate = swab16(storm_rate); 2788 } 2789 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2790 storm_mask, storm_rate); 2791 2792 dev->dev_ops->config_cpu_port(ds); 2793 2794 dev->dev_ops->enable_stp_addr(dev); 2795 2796 ds->num_tx_queues = dev->info->num_tx_queues; 2797 2798 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 2799 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2800 2801 ksz_init_mib_timer(dev); 2802 2803 ds->configure_vlan_while_not_filtering = false; 2804 ds->dscp_prio_mapping_is_global = true; 2805 2806 if (dev->dev_ops->setup) { 2807 ret = dev->dev_ops->setup(ds); 2808 if (ret) 2809 return ret; 2810 } 2811 2812 /* Start with learning disabled on standalone user ports, and enabled 2813 * on the CPU port. In lack of other finer mechanisms, learning on the 2814 * CPU port will avoid flooding bridge local addresses on the network 2815 * in some cases. 2816 */ 2817 p = &dev->ports[dev->cpu_port]; 2818 p->learning = true; 2819 2820 if (dev->irq > 0) { 2821 ret = ksz_girq_setup(dev); 2822 if (ret) 2823 return ret; 2824 2825 dsa_switch_for_each_user_port(dp, dev->ds) { 2826 ret = ksz_pirq_setup(dev, dp->index); 2827 if (ret) 2828 goto port_release; 2829 2830 if (dev->info->ptp_capable) { 2831 ret = ksz_ptp_irq_setup(ds, dp->index); 2832 if (ret) 2833 goto pirq_release; 2834 } 2835 } 2836 } 2837 2838 if (dev->info->ptp_capable) { 2839 ret = ksz_ptp_clock_register(ds); 2840 if (ret) { 2841 dev_err(dev->dev, "Failed to register PTP clock: %d\n", 2842 ret); 2843 goto port_release; 2844 } 2845 } 2846 2847 ret = ksz_mdio_register(dev); 2848 if (ret < 0) { 2849 dev_err(dev->dev, "failed to register the mdio"); 2850 goto out_ptp_clock_unregister; 2851 } 2852 2853 ret = ksz_dcb_init(dev); 2854 if (ret) 2855 goto out_ptp_clock_unregister; 2856 2857 /* start switch */ 2858 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 2859 SW_START, SW_START); 2860 2861 return 0; 2862 2863 out_ptp_clock_unregister: 2864 if (dev->info->ptp_capable) 2865 ksz_ptp_clock_unregister(ds); 2866 port_release: 2867 if (dev->irq > 0) { 2868 dsa_switch_for_each_user_port_continue_reverse(dp, dev->ds) { 2869 if (dev->info->ptp_capable) 2870 ksz_ptp_irq_free(ds, dp->index); 2871 pirq_release: 2872 ksz_irq_free(&dev->ports[dp->index].pirq); 2873 } 2874 ksz_irq_free(&dev->girq); 2875 } 2876 2877 return ret; 2878 } 2879 2880 void ksz_teardown(struct dsa_switch *ds) 2881 { 2882 struct ksz_device *dev = ds->priv; 2883 struct dsa_port *dp; 2884 2885 if (dev->info->ptp_capable) 2886 ksz_ptp_clock_unregister(ds); 2887 2888 if (dev->irq > 0) { 2889 dsa_switch_for_each_user_port(dp, dev->ds) { 2890 if (dev->info->ptp_capable) 2891 ksz_ptp_irq_free(ds, dp->index); 2892 2893 ksz_irq_free(&dev->ports[dp->index].pirq); 2894 } 2895 2896 ksz_irq_free(&dev->girq); 2897 } 2898 2899 if (dev->dev_ops->teardown) 2900 dev->dev_ops->teardown(ds); 2901 } 2902 2903 static void port_r_cnt(struct ksz_device *dev, int port) 2904 { 2905 struct ksz_port_mib *mib = &dev->ports[port].mib; 2906 u64 *dropped; 2907 2908 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2909 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2910 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2911 &mib->counters[mib->cnt_ptr]); 2912 ++mib->cnt_ptr; 2913 } 2914 2915 /* last one in storage */ 2916 dropped = &mib->counters[dev->info->mib_cnt]; 2917 2918 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2919 while (mib->cnt_ptr < dev->info->mib_cnt) { 2920 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2921 dropped, &mib->counters[mib->cnt_ptr]); 2922 ++mib->cnt_ptr; 2923 } 2924 mib->cnt_ptr = 0; 2925 } 2926 2927 static void ksz_mib_read_work(struct work_struct *work) 2928 { 2929 struct ksz_device *dev = container_of(work, struct ksz_device, 2930 mib_read.work); 2931 struct ksz_port_mib *mib; 2932 struct ksz_port *p; 2933 int i; 2934 2935 for (i = 0; i < dev->info->port_cnt; i++) { 2936 if (dsa_is_unused_port(dev->ds, i)) 2937 continue; 2938 2939 p = &dev->ports[i]; 2940 mib = &p->mib; 2941 mutex_lock(&mib->cnt_mutex); 2942 2943 /* Only read MIB counters when the port is told to do. 2944 * If not, read only dropped counters when link is not up. 2945 */ 2946 if (!p->read) { 2947 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 2948 2949 if (!netif_carrier_ok(dp->user)) 2950 mib->cnt_ptr = dev->info->reg_mib_cnt; 2951 } 2952 port_r_cnt(dev, i); 2953 p->read = false; 2954 2955 if (dev->dev_ops->r_mib_stat64) 2956 dev->dev_ops->r_mib_stat64(dev, i); 2957 2958 mutex_unlock(&mib->cnt_mutex); 2959 } 2960 2961 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 2962 } 2963 2964 void ksz_init_mib_timer(struct ksz_device *dev) 2965 { 2966 int i; 2967 2968 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 2969 2970 for (i = 0; i < dev->info->port_cnt; i++) { 2971 struct ksz_port_mib *mib = &dev->ports[i].mib; 2972 2973 dev->dev_ops->port_init_cnt(dev, i); 2974 2975 mib->cnt_ptr = 0; 2976 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 2977 } 2978 } 2979 2980 int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 2981 { 2982 struct ksz_device *dev = ds->priv; 2983 u16 val = 0xffff; 2984 int ret; 2985 2986 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 2987 if (ret) 2988 return ret; 2989 2990 return val; 2991 } 2992 2993 int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 2994 { 2995 struct ksz_device *dev = ds->priv; 2996 int ret; 2997 2998 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 2999 if (ret) 3000 return ret; 3001 3002 return 0; 3003 } 3004 3005 u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 3006 { 3007 struct ksz_device *dev = ds->priv; 3008 3009 switch (dev->chip_id) { 3010 case KSZ88X3_CHIP_ID: 3011 /* Silicon Errata Sheet (DS80000830A): 3012 * Port 1 does not work with LinkMD Cable-Testing. 3013 * Port 1 does not respond to received PAUSE control frames. 3014 */ 3015 if (!port) 3016 return MICREL_KSZ8_P1_ERRATA; 3017 break; 3018 } 3019 3020 return 0; 3021 } 3022 3023 void ksz_phylink_mac_link_down(struct phylink_config *config, 3024 unsigned int mode, 3025 phy_interface_t interface) 3026 { 3027 struct dsa_port *dp = dsa_phylink_to_port(config); 3028 struct ksz_device *dev = dp->ds->priv; 3029 3030 /* Read all MIB counters when the link is going down. */ 3031 dev->ports[dp->index].read = true; 3032 /* timer started */ 3033 if (dev->mib_read_interval) 3034 schedule_delayed_work(&dev->mib_read, 0); 3035 } 3036 3037 int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 3038 { 3039 struct ksz_device *dev = ds->priv; 3040 3041 if (sset != ETH_SS_STATS) 3042 return 0; 3043 3044 return dev->info->mib_cnt; 3045 } 3046 3047 void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 3048 uint64_t *buf) 3049 { 3050 const struct dsa_port *dp = dsa_to_port(ds, port); 3051 struct ksz_device *dev = ds->priv; 3052 struct ksz_port_mib *mib; 3053 3054 mib = &dev->ports[port].mib; 3055 mutex_lock(&mib->cnt_mutex); 3056 3057 /* Only read dropped counters if no link. */ 3058 if (!netif_carrier_ok(dp->user)) 3059 mib->cnt_ptr = dev->info->reg_mib_cnt; 3060 port_r_cnt(dev, port); 3061 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 3062 mutex_unlock(&mib->cnt_mutex); 3063 } 3064 3065 int ksz_port_bridge_join(struct dsa_switch *ds, int port, 3066 struct dsa_bridge bridge, 3067 bool *tx_fwd_offload, 3068 struct netlink_ext_ack *extack) 3069 { 3070 /* port_stp_state_set() will be called after to put the port in 3071 * appropriate state so there is no need to do anything. 3072 */ 3073 3074 return 0; 3075 } 3076 3077 void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 3078 struct dsa_bridge bridge) 3079 { 3080 /* port_stp_state_set() will be called after to put the port in 3081 * forwarding state so there is no need to do anything. 3082 */ 3083 } 3084 3085 static int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev, 3086 int port) 3087 { 3088 u32 queue_map = 0; 3089 int ipm; 3090 3091 for (ipm = 0; ipm < dev->info->num_ipms; ipm++) { 3092 int queue; 3093 3094 /* Traffic Type (TT) is corresponding to the Internal Priority 3095 * Map (IPM) in the switch. Traffic Class (TC) is 3096 * corresponding to the queue in the switch. 3097 */ 3098 queue = ieee8021q_tt_to_tc(ipm, dev->info->num_tx_queues); 3099 if (queue < 0) 3100 return queue; 3101 3102 queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S); 3103 } 3104 3105 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3106 } 3107 3108 int ksz_port_setup(struct dsa_switch *ds, int port) 3109 { 3110 struct ksz_device *dev = ds->priv; 3111 int ret; 3112 3113 if (!dsa_is_user_port(ds, port)) 3114 return 0; 3115 3116 /* setup user port */ 3117 dev->dev_ops->port_setup(dev, port, false); 3118 3119 if (!is_ksz8(dev)) { 3120 ret = ksz9477_set_default_prio_queue_mapping(dev, port); 3121 if (ret) 3122 return ret; 3123 } 3124 3125 /* port_stp_state_set() will be called after to enable the port so 3126 * there is no need to do anything. 3127 */ 3128 3129 return ksz_dcb_init_port(dev, port); 3130 } 3131 3132 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 3133 { 3134 struct ksz_device *dev = ds->priv; 3135 struct ksz_port *p; 3136 const u16 *regs; 3137 u8 data; 3138 3139 regs = dev->info->regs; 3140 3141 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 3142 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 3143 3144 p = &dev->ports[port]; 3145 3146 switch (state) { 3147 case BR_STATE_DISABLED: 3148 data |= PORT_LEARN_DISABLE; 3149 break; 3150 case BR_STATE_LISTENING: 3151 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 3152 break; 3153 case BR_STATE_LEARNING: 3154 data |= PORT_RX_ENABLE; 3155 if (!p->learning) 3156 data |= PORT_LEARN_DISABLE; 3157 break; 3158 case BR_STATE_FORWARDING: 3159 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 3160 if (!p->learning) 3161 data |= PORT_LEARN_DISABLE; 3162 break; 3163 case BR_STATE_BLOCKING: 3164 data |= PORT_LEARN_DISABLE; 3165 break; 3166 default: 3167 dev_err(ds->dev, "invalid STP state: %d\n", state); 3168 return; 3169 } 3170 3171 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 3172 3173 p->stp_state = state; 3174 3175 ksz_update_port_member(dev, port); 3176 } 3177 3178 void ksz_port_teardown(struct dsa_switch *ds, int port) 3179 { 3180 struct ksz_device *dev = ds->priv; 3181 3182 switch (dev->chip_id) { 3183 case KSZ8563_CHIP_ID: 3184 case KSZ8567_CHIP_ID: 3185 case KSZ9477_CHIP_ID: 3186 case KSZ9563_CHIP_ID: 3187 case KSZ9567_CHIP_ID: 3188 case KSZ9893_CHIP_ID: 3189 case KSZ9896_CHIP_ID: 3190 case KSZ9897_CHIP_ID: 3191 case LAN9646_CHIP_ID: 3192 if (dsa_is_user_port(ds, port)) 3193 ksz9477_port_acl_free(dev, port); 3194 } 3195 } 3196 3197 int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 3198 struct switchdev_brport_flags flags, 3199 struct netlink_ext_ack *extack) 3200 { 3201 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED)) 3202 return -EINVAL; 3203 3204 return 0; 3205 } 3206 3207 int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 3208 struct switchdev_brport_flags flags, 3209 struct netlink_ext_ack *extack) 3210 { 3211 struct ksz_device *dev = ds->priv; 3212 struct ksz_port *p = &dev->ports[port]; 3213 3214 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) { 3215 if (flags.mask & BR_LEARNING) 3216 p->learning = !!(flags.val & BR_LEARNING); 3217 3218 if (flags.mask & BR_ISOLATED) 3219 p->isolated = !!(flags.val & BR_ISOLATED); 3220 3221 /* Make the change take effect immediately */ 3222 ksz_port_stp_state_set(ds, port, p->stp_state); 3223 } 3224 3225 return 0; 3226 } 3227 3228 int ksz_max_mtu(struct dsa_switch *ds, int port) 3229 { 3230 struct ksz_device *dev = ds->priv; 3231 3232 switch (dev->chip_id) { 3233 case KSZ8795_CHIP_ID: 3234 case KSZ8794_CHIP_ID: 3235 case KSZ8765_CHIP_ID: 3236 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3237 case KSZ8463_CHIP_ID: 3238 case KSZ88X3_CHIP_ID: 3239 case KSZ8864_CHIP_ID: 3240 case KSZ8895_CHIP_ID: 3241 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3242 case KSZ8563_CHIP_ID: 3243 case KSZ8567_CHIP_ID: 3244 case KSZ9477_CHIP_ID: 3245 case KSZ9563_CHIP_ID: 3246 case KSZ9567_CHIP_ID: 3247 case KSZ9893_CHIP_ID: 3248 case KSZ9896_CHIP_ID: 3249 case KSZ9897_CHIP_ID: 3250 case LAN9370_CHIP_ID: 3251 case LAN9371_CHIP_ID: 3252 case LAN9372_CHIP_ID: 3253 case LAN9373_CHIP_ID: 3254 case LAN9374_CHIP_ID: 3255 case LAN9646_CHIP_ID: 3256 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3257 } 3258 3259 return -EOPNOTSUPP; 3260 } 3261 3262 /** 3263 * ksz_support_eee - Determine Energy Efficient Ethernet (EEE) support for a 3264 * port 3265 * @ds: Pointer to the DSA switch structure 3266 * @port: Port number to check 3267 * 3268 * This function also documents devices where EEE was initially advertised but 3269 * later withdrawn due to reliability issues, as described in official errata 3270 * documents. These devices are explicitly listed to record known limitations, 3271 * even if there is no technical necessity for runtime checks. 3272 * 3273 * Returns: true if the internal PHY on the given port supports fully 3274 * operational EEE, false otherwise. 3275 */ 3276 bool ksz_support_eee(struct dsa_switch *ds, int port) 3277 { 3278 struct ksz_device *dev = ds->priv; 3279 3280 if (!dev->info->internal_phy[port]) 3281 return false; 3282 3283 switch (dev->chip_id) { 3284 case KSZ8563_CHIP_ID: 3285 case KSZ9563_CHIP_ID: 3286 case KSZ9893_CHIP_ID: 3287 return true; 3288 case KSZ8567_CHIP_ID: 3289 /* KSZ8567R Errata DS80000752C Module 4 */ 3290 case KSZ8765_CHIP_ID: 3291 case KSZ8794_CHIP_ID: 3292 case KSZ8795_CHIP_ID: 3293 /* KSZ879x/KSZ877x/KSZ876x Errata DS80000687C Module 2 */ 3294 case KSZ9477_CHIP_ID: 3295 /* KSZ9477S Errata DS80000754A Module 4 */ 3296 case KSZ9567_CHIP_ID: 3297 /* KSZ9567S Errata DS80000756A Module 4 */ 3298 case KSZ9896_CHIP_ID: 3299 /* KSZ9896C Errata DS80000757A Module 3 */ 3300 case KSZ9897_CHIP_ID: 3301 case LAN9646_CHIP_ID: 3302 /* KSZ9897R Errata DS80000758C Module 4 */ 3303 /* Energy Efficient Ethernet (EEE) feature select must be 3304 * manually disabled 3305 * The EEE feature is enabled by default, but it is not fully 3306 * operational. It must be manually disabled through register 3307 * controls. If not disabled, the PHY ports can auto-negotiate 3308 * to enable EEE, and this feature can cause link drops when 3309 * linked to another device supporting EEE. 3310 * 3311 * The same item appears in the errata for all switches above. 3312 */ 3313 break; 3314 } 3315 3316 return false; 3317 } 3318 3319 int ksz_set_mac_eee(struct dsa_switch *ds, int port, 3320 struct ethtool_keee *e) 3321 { 3322 struct ksz_device *dev = ds->priv; 3323 3324 if (!e->tx_lpi_enabled) { 3325 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 3326 return -EINVAL; 3327 } 3328 3329 if (e->tx_lpi_timer) { 3330 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 3331 return -EINVAL; 3332 } 3333 3334 return 0; 3335 } 3336 3337 static void ksz_set_xmii(struct ksz_device *dev, int port, 3338 phy_interface_t interface) 3339 { 3340 const u8 *bitval = dev->info->xmii_ctrl1; 3341 struct ksz_port *p = &dev->ports[port]; 3342 const u16 *regs = dev->info->regs; 3343 u8 data8; 3344 3345 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3346 3347 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 3348 P_RGMII_ID_EG_ENABLE); 3349 3350 switch (interface) { 3351 case PHY_INTERFACE_MODE_MII: 3352 data8 |= bitval[P_MII_SEL]; 3353 break; 3354 case PHY_INTERFACE_MODE_RMII: 3355 data8 |= bitval[P_RMII_SEL]; 3356 break; 3357 case PHY_INTERFACE_MODE_GMII: 3358 data8 |= bitval[P_GMII_SEL]; 3359 break; 3360 case PHY_INTERFACE_MODE_RGMII: 3361 case PHY_INTERFACE_MODE_RGMII_ID: 3362 case PHY_INTERFACE_MODE_RGMII_TXID: 3363 case PHY_INTERFACE_MODE_RGMII_RXID: 3364 data8 |= bitval[P_RGMII_SEL]; 3365 /* On KSZ9893, disable RGMII in-band status support */ 3366 if (dev->chip_id == KSZ9893_CHIP_ID || 3367 dev->chip_id == KSZ8563_CHIP_ID || 3368 dev->chip_id == KSZ9563_CHIP_ID || 3369 is_lan937x(dev)) 3370 data8 &= ~P_MII_MAC_MODE; 3371 break; 3372 default: 3373 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 3374 phy_modes(interface), port); 3375 return; 3376 } 3377 3378 if (p->rgmii_tx_val) 3379 data8 |= P_RGMII_ID_EG_ENABLE; 3380 3381 if (p->rgmii_rx_val) 3382 data8 |= P_RGMII_ID_IG_ENABLE; 3383 3384 /* Write the updated value */ 3385 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3386 } 3387 3388 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 3389 { 3390 const u8 *bitval = dev->info->xmii_ctrl1; 3391 const u16 *regs = dev->info->regs; 3392 phy_interface_t interface; 3393 u8 data8; 3394 u8 val; 3395 3396 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3397 3398 val = FIELD_GET(P_MII_SEL_M, data8); 3399 3400 if (val == bitval[P_MII_SEL]) { 3401 if (gbit) 3402 interface = PHY_INTERFACE_MODE_GMII; 3403 else 3404 interface = PHY_INTERFACE_MODE_MII; 3405 } else if (val == bitval[P_RMII_SEL]) { 3406 interface = PHY_INTERFACE_MODE_RMII; 3407 } else { 3408 interface = PHY_INTERFACE_MODE_RGMII; 3409 if (data8 & P_RGMII_ID_EG_ENABLE) 3410 interface = PHY_INTERFACE_MODE_RGMII_TXID; 3411 if (data8 & P_RGMII_ID_IG_ENABLE) { 3412 interface = PHY_INTERFACE_MODE_RGMII_RXID; 3413 if (data8 & P_RGMII_ID_EG_ENABLE) 3414 interface = PHY_INTERFACE_MODE_RGMII_ID; 3415 } 3416 } 3417 3418 return interface; 3419 } 3420 3421 void ksz_phylink_mac_config(struct phylink_config *config, 3422 unsigned int mode, 3423 const struct phylink_link_state *state) 3424 { 3425 struct dsa_port *dp = dsa_phylink_to_port(config); 3426 struct ksz_device *dev = dp->ds->priv; 3427 int port = dp->index; 3428 3429 /* Internal PHYs */ 3430 if (dev->info->internal_phy[port]) 3431 return; 3432 3433 /* No need to configure XMII control register when using SGMII. */ 3434 if (ksz_is_sgmii_port(dev, port)) 3435 return; 3436 3437 if (phylink_autoneg_inband(mode)) { 3438 dev_err(dev->dev, "In-band AN not supported!\n"); 3439 return; 3440 } 3441 3442 ksz_set_xmii(dev, port, state->interface); 3443 3444 if (dev->dev_ops->setup_rgmii_delay) 3445 dev->dev_ops->setup_rgmii_delay(dev, port); 3446 } 3447 3448 bool ksz_get_gbit(struct ksz_device *dev, int port) 3449 { 3450 const u8 *bitval = dev->info->xmii_ctrl1; 3451 const u16 *regs = dev->info->regs; 3452 bool gbit = false; 3453 u8 data8; 3454 bool val; 3455 3456 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3457 3458 val = FIELD_GET(P_GMII_1GBIT_M, data8); 3459 3460 if (val == bitval[P_GMII_1GBIT]) 3461 gbit = true; 3462 3463 return gbit; 3464 } 3465 3466 static int ksz_switch_detect(struct ksz_device *dev) 3467 { 3468 u8 id1, id2, id4; 3469 u16 id16; 3470 u32 id32; 3471 int ret; 3472 3473 /* read chip id */ 3474 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 3475 if (ret) 3476 return ret; 3477 3478 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 3479 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 3480 3481 switch (id1) { 3482 case KSZ84_FAMILY_ID: 3483 dev->chip_id = KSZ8463_CHIP_ID; 3484 break; 3485 case KSZ87_FAMILY_ID: 3486 if (id2 == KSZ87_CHIP_ID_95) { 3487 u8 val; 3488 3489 dev->chip_id = KSZ8795_CHIP_ID; 3490 3491 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 3492 if (val & KSZ8_PORT_FIBER_MODE) 3493 dev->chip_id = KSZ8765_CHIP_ID; 3494 } else if (id2 == KSZ87_CHIP_ID_94) { 3495 dev->chip_id = KSZ8794_CHIP_ID; 3496 } else { 3497 return -ENODEV; 3498 } 3499 break; 3500 case KSZ88_FAMILY_ID: 3501 if (id2 == KSZ88_CHIP_ID_63) 3502 dev->chip_id = KSZ88X3_CHIP_ID; 3503 else 3504 return -ENODEV; 3505 break; 3506 case KSZ8895_FAMILY_ID: 3507 if (id2 == KSZ8895_CHIP_ID_95 || 3508 id2 == KSZ8895_CHIP_ID_95R) 3509 dev->chip_id = KSZ8895_CHIP_ID; 3510 else 3511 return -ENODEV; 3512 ret = ksz_read8(dev, REG_KSZ8864_CHIP_ID, &id4); 3513 if (ret) 3514 return ret; 3515 if (id4 & SW_KSZ8864) 3516 dev->chip_id = KSZ8864_CHIP_ID; 3517 break; 3518 default: 3519 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 3520 if (ret) 3521 return ret; 3522 3523 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 3524 id32 &= ~0xFF; 3525 3526 switch (id32) { 3527 case KSZ9477_CHIP_ID: 3528 case KSZ9896_CHIP_ID: 3529 case KSZ9897_CHIP_ID: 3530 case KSZ9567_CHIP_ID: 3531 case KSZ8567_CHIP_ID: 3532 case LAN9370_CHIP_ID: 3533 case LAN9371_CHIP_ID: 3534 case LAN9372_CHIP_ID: 3535 case LAN9373_CHIP_ID: 3536 case LAN9374_CHIP_ID: 3537 3538 /* LAN9646 does not have its own chip id. */ 3539 if (dev->chip_id != LAN9646_CHIP_ID) 3540 dev->chip_id = id32; 3541 break; 3542 case KSZ9893_CHIP_ID: 3543 ret = ksz_read8(dev, REG_CHIP_ID4, 3544 &id4); 3545 if (ret) 3546 return ret; 3547 3548 if (id4 == SKU_ID_KSZ8563) 3549 dev->chip_id = KSZ8563_CHIP_ID; 3550 else if (id4 == SKU_ID_KSZ9563) 3551 dev->chip_id = KSZ9563_CHIP_ID; 3552 else 3553 dev->chip_id = KSZ9893_CHIP_ID; 3554 3555 break; 3556 default: 3557 dev_err(dev->dev, 3558 "unsupported switch detected %x)\n", id32); 3559 return -ENODEV; 3560 } 3561 } 3562 return 0; 3563 } 3564 3565 int ksz_cls_flower_add(struct dsa_switch *ds, int port, 3566 struct flow_cls_offload *cls, bool ingress) 3567 { 3568 struct ksz_device *dev = ds->priv; 3569 3570 switch (dev->chip_id) { 3571 case KSZ8563_CHIP_ID: 3572 case KSZ8567_CHIP_ID: 3573 case KSZ9477_CHIP_ID: 3574 case KSZ9563_CHIP_ID: 3575 case KSZ9567_CHIP_ID: 3576 case KSZ9893_CHIP_ID: 3577 case KSZ9896_CHIP_ID: 3578 case KSZ9897_CHIP_ID: 3579 case LAN9646_CHIP_ID: 3580 return ksz9477_cls_flower_add(ds, port, cls, ingress); 3581 } 3582 3583 return -EOPNOTSUPP; 3584 } 3585 3586 int ksz_cls_flower_del(struct dsa_switch *ds, int port, 3587 struct flow_cls_offload *cls, bool ingress) 3588 { 3589 struct ksz_device *dev = ds->priv; 3590 3591 switch (dev->chip_id) { 3592 case KSZ8563_CHIP_ID: 3593 case KSZ8567_CHIP_ID: 3594 case KSZ9477_CHIP_ID: 3595 case KSZ9563_CHIP_ID: 3596 case KSZ9567_CHIP_ID: 3597 case KSZ9893_CHIP_ID: 3598 case KSZ9896_CHIP_ID: 3599 case KSZ9897_CHIP_ID: 3600 case LAN9646_CHIP_ID: 3601 return ksz9477_cls_flower_del(ds, port, cls, ingress); 3602 } 3603 3604 return -EOPNOTSUPP; 3605 } 3606 3607 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 3608 * is converted to Hex-decimal using the successive multiplication method. On 3609 * every step, integer part is taken and decimal part is carry forwarded. 3610 */ 3611 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 3612 { 3613 u32 cinc = 0; 3614 u32 txrate; 3615 u32 rate; 3616 u8 temp; 3617 u8 i; 3618 3619 txrate = idle_slope - send_slope; 3620 3621 if (!txrate) 3622 return -EINVAL; 3623 3624 rate = idle_slope; 3625 3626 /* 24 bit register */ 3627 for (i = 0; i < 6; i++) { 3628 rate = rate * 16; 3629 3630 temp = rate / txrate; 3631 3632 rate %= txrate; 3633 3634 cinc = ((cinc << 4) | temp); 3635 } 3636 3637 *bw = cinc; 3638 3639 return 0; 3640 } 3641 3642 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 3643 u8 shaper) 3644 { 3645 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 3646 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 3647 FIELD_PREP(MTI_SHAPING_M, shaper)); 3648 } 3649 3650 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 3651 struct tc_cbs_qopt_offload *qopt) 3652 { 3653 struct ksz_device *dev = ds->priv; 3654 int ret; 3655 u32 bw; 3656 3657 if (!dev->info->tc_cbs_supported) 3658 return -EOPNOTSUPP; 3659 3660 if (qopt->queue > dev->info->num_tx_queues) 3661 return -EINVAL; 3662 3663 /* Queue Selection */ 3664 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 3665 if (ret) 3666 return ret; 3667 3668 if (!qopt->enable) 3669 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3670 MTI_SHAPING_OFF); 3671 3672 /* High Credit */ 3673 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 3674 qopt->hicredit); 3675 if (ret) 3676 return ret; 3677 3678 /* Low Credit */ 3679 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 3680 qopt->locredit); 3681 if (ret) 3682 return ret; 3683 3684 /* Credit Increment Register */ 3685 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 3686 if (ret) 3687 return ret; 3688 3689 if (dev->dev_ops->tc_cbs_set_cinc) { 3690 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 3691 if (ret) 3692 return ret; 3693 } 3694 3695 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3696 MTI_SHAPING_SRP); 3697 } 3698 3699 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 3700 { 3701 int queue, ret; 3702 3703 /* Configuration will not take effect until the last Port Queue X 3704 * Egress Limit Control Register is written. 3705 */ 3706 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3707 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 3708 KSZ9477_OUT_RATE_NO_LIMIT); 3709 if (ret) 3710 return ret; 3711 } 3712 3713 return 0; 3714 } 3715 3716 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 3717 int band) 3718 { 3719 /* Compared to queues, bands prioritize packets differently. In strict 3720 * priority mode, the lowest priority is assigned to Queue 0 while the 3721 * highest priority is given to Band 0. 3722 */ 3723 return p->bands - 1 - band; 3724 } 3725 3726 static u8 ksz8463_tc_ctrl(int port, int queue) 3727 { 3728 u8 reg; 3729 3730 reg = 0xC8 + port * 4; 3731 reg += ((3 - queue) / 2) * 2; 3732 reg++; 3733 reg -= (queue & 1); 3734 return reg; 3735 } 3736 3737 /** 3738 * ksz88x3_tc_ets_add - Configure ETS (Enhanced Transmission Selection) 3739 * for a port on KSZ88x3 switch 3740 * @dev: Pointer to the KSZ switch device structure 3741 * @port: Port number to configure 3742 * @p: Pointer to offload replace parameters describing ETS bands and mapping 3743 * 3744 * The KSZ88x3 supports two scheduling modes: Strict Priority and 3745 * Weighted Fair Queuing (WFQ). Both modes have fixed behavior: 3746 * - No configurable queue-to-priority mapping 3747 * - No weight adjustment in WFQ mode 3748 * 3749 * This function configures the switch to use strict priority mode by 3750 * clearing the WFQ enable bit for all queues associated with ETS bands. 3751 * If strict priority is not explicitly requested, the switch will default 3752 * to WFQ mode. 3753 * 3754 * Return: 0 on success, or a negative error code on failure 3755 */ 3756 static int ksz88x3_tc_ets_add(struct ksz_device *dev, int port, 3757 struct tc_ets_qopt_offload_replace_params *p) 3758 { 3759 int ret, band; 3760 3761 /* Only strict priority mode is supported for now. 3762 * WFQ is implicitly enabled when strict mode is disabled. 3763 */ 3764 for (band = 0; band < p->bands; band++) { 3765 int queue = ksz_ets_band_to_queue(p, band); 3766 u8 reg; 3767 3768 /* Calculate TXQ Split Control register address for this 3769 * port/queue 3770 */ 3771 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue); 3772 if (ksz_is_ksz8463(dev)) 3773 reg = ksz8463_tc_ctrl(port, queue); 3774 3775 /* Clear WFQ enable bit to select strict priority scheduling */ 3776 ret = ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE, 0); 3777 if (ret) 3778 return ret; 3779 } 3780 3781 return 0; 3782 } 3783 3784 /** 3785 * ksz88x3_tc_ets_del - Reset ETS (Enhanced Transmission Selection) config 3786 * for a port on KSZ88x3 switch 3787 * @dev: Pointer to the KSZ switch device structure 3788 * @port: Port number to reset 3789 * 3790 * The KSZ88x3 supports only fixed scheduling modes: Strict Priority or 3791 * Weighted Fair Queuing (WFQ), with no reconfiguration of weights or 3792 * queue mapping. This function resets the port’s scheduling mode to 3793 * the default, which is WFQ, by enabling the WFQ bit for all queues. 3794 * 3795 * Return: 0 on success, or a negative error code on failure 3796 */ 3797 static int ksz88x3_tc_ets_del(struct ksz_device *dev, int port) 3798 { 3799 int ret, queue; 3800 3801 /* Iterate over all transmit queues for this port */ 3802 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3803 u8 reg; 3804 3805 /* Calculate TXQ Split Control register address for this 3806 * port/queue 3807 */ 3808 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue); 3809 if (ksz_is_ksz8463(dev)) 3810 reg = ksz8463_tc_ctrl(port, queue); 3811 3812 /* Set WFQ enable bit to revert back to default scheduling 3813 * mode 3814 */ 3815 ret = ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE, 3816 KSZ8873_TXQ_WFQ_ENABLE); 3817 if (ret) 3818 return ret; 3819 } 3820 3821 return 0; 3822 } 3823 3824 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 3825 { 3826 int ret; 3827 3828 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3829 if (ret) 3830 return ret; 3831 3832 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3833 MTI_SHAPING_OFF); 3834 } 3835 3836 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 3837 int weight) 3838 { 3839 int ret; 3840 3841 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3842 if (ret) 3843 return ret; 3844 3845 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3846 MTI_SHAPING_OFF); 3847 if (ret) 3848 return ret; 3849 3850 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 3851 } 3852 3853 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 3854 struct tc_ets_qopt_offload_replace_params *p) 3855 { 3856 int ret, band, tc_prio; 3857 u32 queue_map = 0; 3858 3859 /* In order to ensure proper prioritization, it is necessary to set the 3860 * rate limit for the related queue to zero. Otherwise strict priority 3861 * or WRR mode will not work. This is a hardware limitation. 3862 */ 3863 ret = ksz_disable_egress_rate_limit(dev, port); 3864 if (ret) 3865 return ret; 3866 3867 /* Configure queue scheduling mode for all bands. Currently only strict 3868 * prio mode is supported. 3869 */ 3870 for (band = 0; band < p->bands; band++) { 3871 int queue = ksz_ets_band_to_queue(p, band); 3872 3873 ret = ksz_queue_set_strict(dev, port, queue); 3874 if (ret) 3875 return ret; 3876 } 3877 3878 /* Configure the mapping between traffic classes and queues. Note: 3879 * priomap variable support 16 traffic classes, but the chip can handle 3880 * only 8 classes. 3881 */ 3882 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 3883 int queue; 3884 3885 if (tc_prio >= dev->info->num_ipms) 3886 break; 3887 3888 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 3889 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3890 } 3891 3892 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3893 } 3894 3895 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 3896 { 3897 int ret, queue; 3898 3899 /* To restore the default chip configuration, set all queues to use the 3900 * WRR scheduler with a weight of 1. 3901 */ 3902 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3903 ret = ksz_queue_set_wrr(dev, port, queue, 3904 KSZ9477_DEFAULT_WRR_WEIGHT); 3905 3906 if (ret) 3907 return ret; 3908 } 3909 3910 /* Revert the queue mapping for TC-priority to its default setting on 3911 * the chip. 3912 */ 3913 return ksz9477_set_default_prio_queue_mapping(dev, port); 3914 } 3915 3916 static int ksz_tc_ets_validate(struct ksz_device *dev, int port, 3917 struct tc_ets_qopt_offload_replace_params *p) 3918 { 3919 int band; 3920 3921 /* Since it is not feasible to share one port among multiple qdisc, 3922 * the user must configure all available queues appropriately. 3923 */ 3924 if (p->bands != dev->info->num_tx_queues) { 3925 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 3926 dev->info->num_tx_queues); 3927 return -EOPNOTSUPP; 3928 } 3929 3930 for (band = 0; band < p->bands; ++band) { 3931 /* The KSZ switches utilize a weighted round robin configuration 3932 * where a certain number of packets can be transmitted from a 3933 * queue before the next queue is serviced. For more information 3934 * on this, refer to section 5.2.8.4 of the KSZ8565R 3935 * documentation on the Port Transmit Queue Control 1 Register. 3936 * However, the current ETS Qdisc implementation (as of February 3937 * 2023) assigns a weight to each queue based on the number of 3938 * bytes or extrapolated bandwidth in percentages. Since this 3939 * differs from the KSZ switches' method and we don't want to 3940 * fake support by converting bytes to packets, it is better to 3941 * return an error instead. 3942 */ 3943 if (p->quanta[band]) { 3944 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 3945 return -EOPNOTSUPP; 3946 } 3947 } 3948 3949 return 0; 3950 } 3951 3952 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 3953 struct tc_ets_qopt_offload *qopt) 3954 { 3955 struct ksz_device *dev = ds->priv; 3956 int ret; 3957 3958 if (is_ksz8(dev) && !(ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev))) 3959 return -EOPNOTSUPP; 3960 3961 if (qopt->parent != TC_H_ROOT) { 3962 dev_err(dev->dev, "Parent should be \"root\"\n"); 3963 return -EOPNOTSUPP; 3964 } 3965 3966 switch (qopt->command) { 3967 case TC_ETS_REPLACE: 3968 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 3969 if (ret) 3970 return ret; 3971 3972 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 3973 return ksz88x3_tc_ets_add(dev, port, 3974 &qopt->replace_params); 3975 else 3976 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 3977 case TC_ETS_DESTROY: 3978 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 3979 return ksz88x3_tc_ets_del(dev, port); 3980 else 3981 return ksz_tc_ets_del(dev, port); 3982 case TC_ETS_STATS: 3983 case TC_ETS_GRAFT: 3984 return -EOPNOTSUPP; 3985 } 3986 3987 return -EOPNOTSUPP; 3988 } 3989 3990 int ksz_setup_tc(struct dsa_switch *ds, int port, 3991 enum tc_setup_type type, void *type_data) 3992 { 3993 switch (type) { 3994 case TC_SETUP_QDISC_CBS: 3995 return ksz_setup_tc_cbs(ds, port, type_data); 3996 case TC_SETUP_QDISC_ETS: 3997 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 3998 default: 3999 return -EOPNOTSUPP; 4000 } 4001 } 4002 4003 /** 4004 * ksz_handle_wake_reason - Handle wake reason on a specified port. 4005 * @dev: The device structure. 4006 * @port: The port number. 4007 * 4008 * This function reads the PME (Power Management Event) status register of a 4009 * specified port to determine the wake reason. If there is no wake event, it 4010 * returns early. Otherwise, it logs the wake reason which could be due to a 4011 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register 4012 * is then cleared to acknowledge the handling of the wake event. 4013 * 4014 * Return: 0 on success, or an error code on failure. 4015 */ 4016 int ksz_handle_wake_reason(struct ksz_device *dev, int port) 4017 { 4018 const struct ksz_dev_ops *ops = dev->dev_ops; 4019 const u16 *regs = dev->info->regs; 4020 u8 pme_status; 4021 int ret; 4022 4023 ret = ops->pme_pread8(dev, port, regs[REG_PORT_PME_STATUS], 4024 &pme_status); 4025 if (ret) 4026 return ret; 4027 4028 if (!pme_status) 4029 return 0; 4030 4031 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port, 4032 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "", 4033 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "", 4034 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : ""); 4035 4036 return ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_STATUS], 4037 pme_status); 4038 } 4039 4040 /** 4041 * ksz_get_wol - Get Wake-on-LAN settings for a specified port. 4042 * @ds: The dsa_switch structure. 4043 * @port: The port number. 4044 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 4045 * 4046 * This function checks the device PME wakeup_source flag and chip_id. 4047 * If enabled and supported, it sets the supported and active WoL 4048 * flags. 4049 */ 4050 void ksz_get_wol(struct dsa_switch *ds, int port, 4051 struct ethtool_wolinfo *wol) 4052 { 4053 struct ksz_device *dev = ds->priv; 4054 const u16 *regs = dev->info->regs; 4055 u8 pme_ctrl; 4056 int ret; 4057 4058 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4059 return; 4060 4061 if (!dev->wakeup_source) 4062 return; 4063 4064 wol->supported = WAKE_PHY; 4065 4066 /* Check if the current MAC address on this port can be set 4067 * as global for WAKE_MAGIC support. The result may vary 4068 * dynamically based on other ports configurations. 4069 */ 4070 if (ksz_is_port_mac_global_usable(dev->ds, port)) 4071 wol->supported |= WAKE_MAGIC; 4072 4073 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 4074 &pme_ctrl); 4075 if (ret) 4076 return; 4077 4078 if (pme_ctrl & PME_WOL_MAGICPKT) 4079 wol->wolopts |= WAKE_MAGIC; 4080 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY)) 4081 wol->wolopts |= WAKE_PHY; 4082 } 4083 4084 /** 4085 * ksz_set_wol - Set Wake-on-LAN settings for a specified port. 4086 * @ds: The dsa_switch structure. 4087 * @port: The port number. 4088 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 4089 * 4090 * This function configures Wake-on-LAN (WoL) settings for a specified 4091 * port. It validates the provided WoL options, checks if PME is 4092 * enabled and supported, clears any previous wake reasons, and sets 4093 * the Magic Packet flag in the port's PME control register if 4094 * specified. 4095 * 4096 * Return: 0 on success, or other error codes on failure. 4097 */ 4098 int ksz_set_wol(struct dsa_switch *ds, int port, 4099 struct ethtool_wolinfo *wol) 4100 { 4101 u8 pme_ctrl = 0, pme_ctrl_old = 0; 4102 struct ksz_device *dev = ds->priv; 4103 const u16 *regs = dev->info->regs; 4104 bool magic_switched_off; 4105 bool magic_switched_on; 4106 int ret; 4107 4108 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC)) 4109 return -EINVAL; 4110 4111 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4112 return -EOPNOTSUPP; 4113 4114 if (!dev->wakeup_source) 4115 return -EOPNOTSUPP; 4116 4117 ret = ksz_handle_wake_reason(dev, port); 4118 if (ret) 4119 return ret; 4120 4121 if (wol->wolopts & WAKE_MAGIC) 4122 pme_ctrl |= PME_WOL_MAGICPKT; 4123 if (wol->wolopts & WAKE_PHY) 4124 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY; 4125 4126 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 4127 &pme_ctrl_old); 4128 if (ret) 4129 return ret; 4130 4131 if (pme_ctrl_old == pme_ctrl) 4132 return 0; 4133 4134 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) && 4135 !(pme_ctrl & PME_WOL_MAGICPKT); 4136 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) && 4137 (pme_ctrl & PME_WOL_MAGICPKT); 4138 4139 /* To keep reference count of MAC address, we should do this 4140 * operation only on change of WOL settings. 4141 */ 4142 if (magic_switched_on) { 4143 ret = ksz_switch_macaddr_get(dev->ds, port, NULL); 4144 if (ret) 4145 return ret; 4146 } else if (magic_switched_off) { 4147 ksz_switch_macaddr_put(dev->ds); 4148 } 4149 4150 ret = dev->dev_ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 4151 pme_ctrl); 4152 if (ret) { 4153 if (magic_switched_on) 4154 ksz_switch_macaddr_put(dev->ds); 4155 return ret; 4156 } 4157 4158 return 0; 4159 } 4160 4161 /** 4162 * ksz_wol_pre_shutdown - Prepares the switch device for shutdown while 4163 * considering Wake-on-LAN (WoL) settings. 4164 * @dev: The switch device structure. 4165 * @wol_enabled: Pointer to a boolean which will be set to true if WoL is 4166 * enabled on any port. 4167 * 4168 * This function prepares the switch device for a safe shutdown while taking 4169 * into account the Wake-on-LAN (WoL) settings on the user ports. It updates 4170 * the wol_enabled flag accordingly to reflect whether WoL is active on any 4171 * port. 4172 */ 4173 static void ksz_wol_pre_shutdown(struct ksz_device *dev, bool *wol_enabled) 4174 { 4175 const struct ksz_dev_ops *ops = dev->dev_ops; 4176 const u16 *regs = dev->info->regs; 4177 u8 pme_pin_en = PME_ENABLE; 4178 struct dsa_port *dp; 4179 int ret; 4180 4181 *wol_enabled = false; 4182 4183 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4184 return; 4185 4186 if (!dev->wakeup_source) 4187 return; 4188 4189 dsa_switch_for_each_user_port(dp, dev->ds) { 4190 u8 pme_ctrl = 0; 4191 4192 ret = ops->pme_pread8(dev, dp->index, 4193 regs[REG_PORT_PME_CTRL], &pme_ctrl); 4194 if (!ret && pme_ctrl) 4195 *wol_enabled = true; 4196 4197 /* make sure there are no pending wake events which would 4198 * prevent the device from going to sleep/shutdown. 4199 */ 4200 ksz_handle_wake_reason(dev, dp->index); 4201 } 4202 4203 /* Now we are save to enable PME pin. */ 4204 if (*wol_enabled) { 4205 if (dev->pme_active_high) 4206 pme_pin_en |= PME_POLARITY; 4207 ops->pme_write8(dev, regs[REG_SW_PME_CTRL], pme_pin_en); 4208 if (ksz_is_ksz87xx(dev)) 4209 ksz_write8(dev, KSZ87XX_REG_INT_EN, KSZ87XX_INT_PME_MASK); 4210 } 4211 } 4212 4213 int ksz_port_set_mac_address(struct dsa_switch *ds, int port, 4214 const unsigned char *addr) 4215 { 4216 struct dsa_port *dp = dsa_to_port(ds, port); 4217 struct ethtool_wolinfo wol; 4218 4219 if (dp->hsr_dev) { 4220 dev_err(ds->dev, 4221 "Cannot change MAC address on port %d with active HSR offload\n", 4222 port); 4223 return -EBUSY; 4224 } 4225 4226 /* Need to initialize variable as the code to fill in settings may 4227 * not be executed. 4228 */ 4229 wol.wolopts = 0; 4230 4231 ksz_get_wol(ds, dp->index, &wol); 4232 if (wol.wolopts & WAKE_MAGIC) { 4233 dev_err(ds->dev, 4234 "Cannot change MAC address on port %d with active Wake on Magic Packet\n", 4235 port); 4236 return -EBUSY; 4237 } 4238 4239 return 0; 4240 } 4241 4242 /** 4243 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port 4244 * can be used as a global address. 4245 * @ds: Pointer to the DSA switch structure. 4246 * @port: The port number on which the MAC address is to be checked. 4247 * 4248 * This function examines the MAC address set on the specified port and 4249 * determines if it can be used as a global address for the switch. 4250 * 4251 * Return: true if the port's MAC address can be used as a global address, false 4252 * otherwise. 4253 */ 4254 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port) 4255 { 4256 struct net_device *user = dsa_to_port(ds, port)->user; 4257 const unsigned char *addr = user->dev_addr; 4258 struct ksz_switch_macaddr *switch_macaddr; 4259 struct ksz_device *dev = ds->priv; 4260 4261 ASSERT_RTNL(); 4262 4263 switch_macaddr = dev->switch_macaddr; 4264 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr)) 4265 return false; 4266 4267 return true; 4268 } 4269 4270 /** 4271 * ksz_switch_macaddr_get - Program the switch's MAC address register. 4272 * @ds: DSA switch instance. 4273 * @port: Port number. 4274 * @extack: Netlink extended acknowledgment. 4275 * 4276 * This function programs the switch's MAC address register with the MAC address 4277 * of the requesting user port. This single address is used by the switch for 4278 * multiple features like HSR self-address filtering and WoL. Other user ports 4279 * can share ownership of this address as long as their MAC address is the same. 4280 * The MAC addresses of user ports must not change while they have ownership of 4281 * the switch MAC address. 4282 * 4283 * Return: 0 on success, or other error codes on failure. 4284 */ 4285 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 4286 struct netlink_ext_ack *extack) 4287 { 4288 struct net_device *user = dsa_to_port(ds, port)->user; 4289 const unsigned char *addr = user->dev_addr; 4290 struct ksz_switch_macaddr *switch_macaddr; 4291 struct ksz_device *dev = ds->priv; 4292 const u16 *regs = dev->info->regs; 4293 int i, ret; 4294 4295 /* Make sure concurrent MAC address changes are blocked */ 4296 ASSERT_RTNL(); 4297 4298 switch_macaddr = dev->switch_macaddr; 4299 if (switch_macaddr) { 4300 if (!ether_addr_equal(switch_macaddr->addr, addr)) { 4301 NL_SET_ERR_MSG_FMT_MOD(extack, 4302 "Switch already configured for MAC address %pM", 4303 switch_macaddr->addr); 4304 return -EBUSY; 4305 } 4306 4307 refcount_inc(&switch_macaddr->refcount); 4308 return 0; 4309 } 4310 4311 switch_macaddr = kzalloc_obj(*switch_macaddr); 4312 if (!switch_macaddr) 4313 return -ENOMEM; 4314 4315 ether_addr_copy(switch_macaddr->addr, addr); 4316 refcount_set(&switch_macaddr->refcount, 1); 4317 dev->switch_macaddr = switch_macaddr; 4318 4319 /* Program the switch MAC address to hardware */ 4320 for (i = 0; i < ETH_ALEN; i++) { 4321 if (ksz_is_ksz8463(dev)) { 4322 u16 addr16 = ((u16)addr[i] << 8) | addr[i + 1]; 4323 4324 ret = ksz_write16(dev, regs[REG_SW_MAC_ADDR] + i, 4325 addr16); 4326 i++; 4327 } else { 4328 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 4329 addr[i]); 4330 } 4331 if (ret) 4332 goto macaddr_drop; 4333 } 4334 4335 return 0; 4336 4337 macaddr_drop: 4338 dev->switch_macaddr = NULL; 4339 refcount_set(&switch_macaddr->refcount, 0); 4340 kfree(switch_macaddr); 4341 4342 return ret; 4343 } 4344 4345 void ksz_switch_macaddr_put(struct dsa_switch *ds) 4346 { 4347 struct ksz_switch_macaddr *switch_macaddr; 4348 struct ksz_device *dev = ds->priv; 4349 const u16 *regs = dev->info->regs; 4350 int i; 4351 4352 /* Make sure concurrent MAC address changes are blocked */ 4353 ASSERT_RTNL(); 4354 4355 switch_macaddr = dev->switch_macaddr; 4356 if (!refcount_dec_and_test(&switch_macaddr->refcount)) 4357 return; 4358 4359 for (i = 0; i < ETH_ALEN; i++) 4360 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0); 4361 4362 dev->switch_macaddr = NULL; 4363 kfree(switch_macaddr); 4364 } 4365 4366 int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr, 4367 struct netlink_ext_ack *extack) 4368 { 4369 struct ksz_device *dev = ds->priv; 4370 enum hsr_version ver; 4371 int ret; 4372 4373 ret = hsr_get_version(hsr, &ver); 4374 if (ret) 4375 return ret; 4376 4377 if (dev->chip_id != KSZ9477_CHIP_ID) { 4378 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload"); 4379 return -EOPNOTSUPP; 4380 } 4381 4382 /* KSZ9477 can support HW offloading of only 1 HSR device */ 4383 if (dev->hsr_dev && hsr != dev->hsr_dev) { 4384 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR"); 4385 return -EOPNOTSUPP; 4386 } 4387 4388 /* KSZ9477 only supports HSR v0 and v1 */ 4389 if (!(ver == HSR_V0 || ver == HSR_V1)) { 4390 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported"); 4391 return -EOPNOTSUPP; 4392 } 4393 4394 /* KSZ9477 can only perform HSR offloading for up to two ports */ 4395 if (hweight8(dev->hsr_ports) >= 2) { 4396 NL_SET_ERR_MSG_MOD(extack, 4397 "Cannot offload more than two ports - using software HSR"); 4398 return -EOPNOTSUPP; 4399 } 4400 4401 /* Self MAC address filtering, to avoid frames traversing 4402 * the HSR ring more than once. 4403 */ 4404 ret = ksz_switch_macaddr_get(ds, port, extack); 4405 if (ret) 4406 return ret; 4407 4408 ksz9477_hsr_join(ds, port, hsr); 4409 dev->hsr_dev = hsr; 4410 dev->hsr_ports |= BIT(port); 4411 4412 return 0; 4413 } 4414 4415 int ksz_hsr_leave(struct dsa_switch *ds, int port, 4416 struct net_device *hsr) 4417 { 4418 struct ksz_device *dev = ds->priv; 4419 4420 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID); 4421 4422 ksz9477_hsr_leave(ds, port, hsr); 4423 dev->hsr_ports &= ~BIT(port); 4424 if (!dev->hsr_ports) 4425 dev->hsr_dev = NULL; 4426 4427 ksz_switch_macaddr_put(ds); 4428 4429 return 0; 4430 } 4431 4432 int ksz_suspend(struct dsa_switch *ds) 4433 { 4434 struct ksz_device *dev = ds->priv; 4435 4436 cancel_delayed_work_sync(&dev->mib_read); 4437 return 0; 4438 } 4439 4440 int ksz_resume(struct dsa_switch *ds) 4441 { 4442 struct ksz_device *dev = ds->priv; 4443 4444 if (dev->mib_read_interval) 4445 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 4446 return 0; 4447 } 4448 4449 struct ksz_device *ksz_switch_alloc(struct device *base, 4450 const struct ksz_chip_data *chip, 4451 void *priv) 4452 { 4453 struct dsa_switch *ds; 4454 struct ksz_device *swdev; 4455 4456 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 4457 if (!ds) 4458 return NULL; 4459 4460 ds->dev = base; 4461 ds->num_ports = DSA_MAX_PORTS; 4462 ds->ops = chip->switch_ops; 4463 4464 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 4465 if (!swdev) 4466 return NULL; 4467 4468 ds->priv = swdev; 4469 swdev->dev = base; 4470 4471 swdev->ds = ds; 4472 swdev->priv = priv; 4473 4474 return swdev; 4475 } 4476 EXPORT_SYMBOL(ksz_switch_alloc); 4477 4478 /** 4479 * ksz_switch_shutdown - Shutdown routine for the switch device. 4480 * @dev: The switch device structure. 4481 * 4482 * This function is responsible for initiating a shutdown sequence for the 4483 * switch device. It invokes the reset operation defined in the device 4484 * operations, if available, to reset the switch. Subsequently, it calls the 4485 * DSA framework's shutdown function to ensure a proper shutdown of the DSA 4486 * switch. 4487 */ 4488 void ksz_switch_shutdown(struct ksz_device *dev) 4489 { 4490 bool wol_enabled = false; 4491 4492 ksz_wol_pre_shutdown(dev, &wol_enabled); 4493 4494 if (dev->dev_ops->reset && !wol_enabled) 4495 dev->dev_ops->reset(dev); 4496 4497 dsa_switch_shutdown(dev->ds); 4498 } 4499 EXPORT_SYMBOL(ksz_switch_shutdown); 4500 4501 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 4502 struct device_node *port_dn) 4503 { 4504 phy_interface_t phy_mode = dev->ports[port_num].interface; 4505 int rx_delay = -1, tx_delay = -1; 4506 4507 if (!phy_interface_mode_is_rgmii(phy_mode)) 4508 return; 4509 4510 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 4511 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 4512 4513 if (rx_delay == -1 && tx_delay == -1) { 4514 dev_warn(dev->dev, 4515 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 4516 "please update device tree to specify \"rx-internal-delay-ps\" and " 4517 "\"tx-internal-delay-ps\"", 4518 port_num); 4519 4520 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 4521 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 4522 rx_delay = 2000; 4523 4524 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 4525 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 4526 tx_delay = 2000; 4527 } 4528 4529 if (rx_delay < 0) 4530 rx_delay = 0; 4531 if (tx_delay < 0) 4532 tx_delay = 0; 4533 4534 dev->ports[port_num].rgmii_rx_val = rx_delay; 4535 dev->ports[port_num].rgmii_tx_val = tx_delay; 4536 } 4537 4538 /** 4539 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding 4540 * register value. 4541 * @array: The array of drive strength values to search. 4542 * @array_size: The size of the array. 4543 * @microamp: The drive strength value in microamp to be converted. 4544 * 4545 * This function searches the array of drive strength values for the given 4546 * microamp value and returns the corresponding register value for that drive. 4547 * 4548 * Returns: If found, the corresponding register value for that drive strength 4549 * is returned. Otherwise, -EINVAL is returned indicating an invalid value. 4550 */ 4551 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array, 4552 size_t array_size, int microamp) 4553 { 4554 int i; 4555 4556 for (i = 0; i < array_size; i++) { 4557 if (array[i].microamp == microamp) 4558 return array[i].reg_val; 4559 } 4560 4561 return -EINVAL; 4562 } 4563 4564 /** 4565 * ksz_drive_strength_error() - Report invalid drive strength value 4566 * @dev: ksz device 4567 * @array: The array of drive strength values to search. 4568 * @array_size: The size of the array. 4569 * @microamp: Invalid drive strength value in microamp 4570 * 4571 * This function logs an error message when an unsupported drive strength value 4572 * is detected. It lists out all the supported drive strength values for 4573 * reference in the error message. 4574 */ 4575 static void ksz_drive_strength_error(struct ksz_device *dev, 4576 const struct ksz_drive_strength *array, 4577 size_t array_size, int microamp) 4578 { 4579 char supported_values[100]; 4580 size_t remaining_size; 4581 int added_len; 4582 char *ptr; 4583 int i; 4584 4585 remaining_size = sizeof(supported_values); 4586 ptr = supported_values; 4587 4588 for (i = 0; i < array_size; i++) { 4589 added_len = snprintf(ptr, remaining_size, 4590 i == 0 ? "%d" : ", %d", array[i].microamp); 4591 4592 if (added_len >= remaining_size) 4593 break; 4594 4595 ptr += added_len; 4596 remaining_size -= added_len; 4597 } 4598 4599 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n", 4600 microamp, supported_values); 4601 } 4602 4603 /** 4604 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477 4605 * chip variants. 4606 * @dev: ksz device 4607 * @props: Array of drive strength properties to be applied 4608 * @num_props: Number of properties in the array 4609 * 4610 * This function configures the drive strength for various KSZ9477 chip variants 4611 * based on the provided properties. It handles chip-specific nuances and 4612 * ensures only valid drive strengths are written to the respective chip. 4613 * 4614 * Return: 0 on successful configuration, a negative error code on failure. 4615 */ 4616 static int ksz9477_drive_strength_write(struct ksz_device *dev, 4617 struct ksz_driver_strength_prop *props, 4618 int num_props) 4619 { 4620 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths); 4621 int i, ret, reg; 4622 u8 mask = 0; 4623 u8 val = 0; 4624 4625 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1) 4626 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4627 props[KSZ_DRIVER_STRENGTH_IO].name); 4628 4629 if (dev->chip_id == KSZ8795_CHIP_ID || 4630 dev->chip_id == KSZ8794_CHIP_ID || 4631 dev->chip_id == KSZ8765_CHIP_ID) 4632 reg = KSZ8795_REG_SW_CTRL_20; 4633 else 4634 reg = KSZ9477_REG_SW_IO_STRENGTH; 4635 4636 for (i = 0; i < num_props; i++) { 4637 if (props[i].value == -1) 4638 continue; 4639 4640 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths, 4641 array_size, props[i].value); 4642 if (ret < 0) { 4643 ksz_drive_strength_error(dev, ksz9477_drive_strengths, 4644 array_size, props[i].value); 4645 return ret; 4646 } 4647 4648 mask |= SW_DRIVE_STRENGTH_M << props[i].offset; 4649 val |= ret << props[i].offset; 4650 } 4651 4652 return ksz_rmw8(dev, reg, mask, val); 4653 } 4654 4655 /** 4656 * ksz88x3_drive_strength_write() - Set the drive strength configuration for 4657 * KSZ8863 compatible chip variants. 4658 * @dev: ksz device 4659 * @props: Array of drive strength properties to be set 4660 * @num_props: Number of properties in the array 4661 * 4662 * This function applies the specified drive strength settings to KSZ88X3 chip 4663 * variants (KSZ8873, KSZ8863). 4664 * It ensures the configurations align with what the chip variant supports and 4665 * warns or errors out on unsupported settings. 4666 * 4667 * Return: 0 on success, error code otherwise 4668 */ 4669 static int ksz88x3_drive_strength_write(struct ksz_device *dev, 4670 struct ksz_driver_strength_prop *props, 4671 int num_props) 4672 { 4673 size_t array_size = ARRAY_SIZE(ksz88x3_drive_strengths); 4674 int microamp; 4675 int i, ret; 4676 4677 for (i = 0; i < num_props; i++) { 4678 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO) 4679 continue; 4680 4681 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4682 props[i].name); 4683 } 4684 4685 microamp = props[KSZ_DRIVER_STRENGTH_IO].value; 4686 ret = ksz_drive_strength_to_reg(ksz88x3_drive_strengths, array_size, 4687 microamp); 4688 if (ret < 0) { 4689 ksz_drive_strength_error(dev, ksz88x3_drive_strengths, 4690 array_size, microamp); 4691 return ret; 4692 } 4693 4694 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12, 4695 KSZ8873_DRIVE_STRENGTH_16MA, ret); 4696 } 4697 4698 /** 4699 * ksz_parse_drive_strength() - Extract and apply drive strength configurations 4700 * from device tree properties. 4701 * @dev: ksz device 4702 * 4703 * This function reads the specified drive strength properties from the 4704 * device tree, validates against the supported chip variants, and sets 4705 * them accordingly. An error should be critical here, as the drive strength 4706 * settings are crucial for EMI compliance. 4707 * 4708 * Return: 0 on success, error code otherwise 4709 */ 4710 static int ksz_parse_drive_strength(struct ksz_device *dev) 4711 { 4712 struct ksz_driver_strength_prop of_props[] = { 4713 [KSZ_DRIVER_STRENGTH_HI] = { 4714 .name = "microchip,hi-drive-strength-microamp", 4715 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S, 4716 .value = -1, 4717 }, 4718 [KSZ_DRIVER_STRENGTH_LO] = { 4719 .name = "microchip,lo-drive-strength-microamp", 4720 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S, 4721 .value = -1, 4722 }, 4723 [KSZ_DRIVER_STRENGTH_IO] = { 4724 .name = "microchip,io-drive-strength-microamp", 4725 .offset = 0, /* don't care */ 4726 .value = -1, 4727 }, 4728 }; 4729 struct device_node *np = dev->dev->of_node; 4730 bool have_any_prop = false; 4731 int i, ret; 4732 4733 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4734 ret = of_property_read_u32(np, of_props[i].name, 4735 &of_props[i].value); 4736 if (ret && ret != -EINVAL) 4737 dev_warn(dev->dev, "Failed to read %s\n", 4738 of_props[i].name); 4739 if (ret) 4740 continue; 4741 4742 have_any_prop = true; 4743 } 4744 4745 if (!have_any_prop) 4746 return 0; 4747 4748 switch (dev->chip_id) { 4749 case KSZ88X3_CHIP_ID: 4750 return ksz88x3_drive_strength_write(dev, of_props, 4751 ARRAY_SIZE(of_props)); 4752 case KSZ8795_CHIP_ID: 4753 case KSZ8794_CHIP_ID: 4754 case KSZ8765_CHIP_ID: 4755 case KSZ8563_CHIP_ID: 4756 case KSZ8567_CHIP_ID: 4757 case KSZ9477_CHIP_ID: 4758 case KSZ9563_CHIP_ID: 4759 case KSZ9567_CHIP_ID: 4760 case KSZ9893_CHIP_ID: 4761 case KSZ9896_CHIP_ID: 4762 case KSZ9897_CHIP_ID: 4763 case LAN9646_CHIP_ID: 4764 return ksz9477_drive_strength_write(dev, of_props, 4765 ARRAY_SIZE(of_props)); 4766 default: 4767 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4768 if (of_props[i].value == -1) 4769 continue; 4770 4771 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4772 of_props[i].name); 4773 } 4774 } 4775 4776 return 0; 4777 } 4778 4779 static int ksz8463_configure_straps_spi(struct ksz_device *dev) 4780 { 4781 struct pinctrl *pinctrl; 4782 struct gpio_desc *rxd0; 4783 struct gpio_desc *rxd1; 4784 4785 rxd0 = devm_gpiod_get_index_optional(dev->dev, "straps-rxd", 0, GPIOD_OUT_LOW); 4786 if (IS_ERR(rxd0)) 4787 return PTR_ERR(rxd0); 4788 4789 rxd1 = devm_gpiod_get_index_optional(dev->dev, "straps-rxd", 1, GPIOD_OUT_HIGH); 4790 if (IS_ERR(rxd1)) 4791 return PTR_ERR(rxd1); 4792 4793 if (!rxd0 && !rxd1) 4794 return 0; 4795 4796 if ((rxd0 && !rxd1) || (rxd1 && !rxd0)) 4797 return -EINVAL; 4798 4799 pinctrl = devm_pinctrl_get_select(dev->dev, "reset"); 4800 if (IS_ERR(pinctrl)) 4801 return PTR_ERR(pinctrl); 4802 4803 return 0; 4804 } 4805 4806 static int ksz8463_release_straps_spi(struct ksz_device *dev) 4807 { 4808 return pinctrl_select_default_state(dev->dev); 4809 } 4810 4811 int ksz_switch_register(struct ksz_device *dev) 4812 { 4813 const struct ksz_chip_data *info; 4814 struct device_node *ports; 4815 phy_interface_t interface; 4816 unsigned int port_num; 4817 int ret; 4818 int i; 4819 4820 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 4821 GPIOD_OUT_LOW); 4822 if (IS_ERR(dev->reset_gpio)) 4823 return PTR_ERR(dev->reset_gpio); 4824 4825 if (dev->reset_gpio) { 4826 if (of_device_is_compatible(dev->dev->of_node, "microchip,ksz8463")) { 4827 ret = ksz8463_configure_straps_spi(dev); 4828 if (ret) 4829 return ret; 4830 } 4831 4832 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4833 usleep_range(10000, 12000); 4834 gpiod_set_value_cansleep(dev->reset_gpio, 0); 4835 msleep(100); 4836 4837 if (of_device_is_compatible(dev->dev->of_node, "microchip,ksz8463")) { 4838 ret = ksz8463_release_straps_spi(dev); 4839 if (ret) 4840 return ret; 4841 } 4842 } 4843 4844 mutex_init(&dev->dev_mutex); 4845 mutex_init(&dev->regmap_mutex); 4846 mutex_init(&dev->alu_mutex); 4847 mutex_init(&dev->vlan_mutex); 4848 4849 ret = ksz_switch_detect(dev); 4850 if (ret) 4851 return ret; 4852 4853 info = ksz_lookup_info(dev->chip_id); 4854 if (!info) 4855 return -ENODEV; 4856 4857 /* Update the compatible info with the probed one */ 4858 dev->info = info; 4859 4860 dev_info(dev->dev, "found switch: %s, rev %i\n", 4861 dev->info->dev_name, dev->chip_rev); 4862 4863 ret = ksz_check_device_id(dev); 4864 if (ret) 4865 return ret; 4866 4867 dev->dev_ops = dev->info->ops; 4868 4869 ret = dev->dev_ops->init(dev); 4870 if (ret) 4871 return ret; 4872 4873 dev->ports = devm_kzalloc(dev->dev, 4874 dev->info->port_cnt * sizeof(struct ksz_port), 4875 GFP_KERNEL); 4876 if (!dev->ports) 4877 return -ENOMEM; 4878 4879 for (i = 0; i < dev->info->port_cnt; i++) { 4880 spin_lock_init(&dev->ports[i].mib.stats64_lock); 4881 mutex_init(&dev->ports[i].mib.cnt_mutex); 4882 dev->ports[i].mib.counters = 4883 devm_kzalloc(dev->dev, 4884 sizeof(u64) * (dev->info->mib_cnt + 1), 4885 GFP_KERNEL); 4886 if (!dev->ports[i].mib.counters) 4887 return -ENOMEM; 4888 4889 dev->ports[i].ksz_dev = dev; 4890 dev->ports[i].num = i; 4891 } 4892 4893 /* set the real number of ports */ 4894 dev->ds->num_ports = dev->info->port_cnt; 4895 4896 /* set the phylink ops */ 4897 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops; 4898 4899 /* Host port interface will be self detected, or specifically set in 4900 * device tree. 4901 */ 4902 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 4903 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 4904 if (dev->dev->of_node) { 4905 ret = of_get_phy_mode(dev->dev->of_node, &interface); 4906 if (ret == 0) 4907 dev->compat_interface = interface; 4908 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 4909 if (!ports) 4910 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 4911 if (ports) { 4912 for_each_available_child_of_node_scoped(ports, port) { 4913 if (of_property_read_u32(port, "reg", 4914 &port_num)) 4915 continue; 4916 if (!(dev->port_mask & BIT(port_num))) { 4917 of_node_put(ports); 4918 return -EINVAL; 4919 } 4920 of_get_phy_mode(port, 4921 &dev->ports[port_num].interface); 4922 4923 ksz_parse_rgmii_delay(dev, port_num, port); 4924 dev->ports[port_num].fiber = 4925 of_property_read_bool(port, 4926 "micrel,fiber-mode"); 4927 } 4928 of_node_put(ports); 4929 } 4930 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 4931 "microchip,synclko-125"); 4932 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 4933 "microchip,synclko-disable"); 4934 if (dev->synclko_125 && dev->synclko_disable) { 4935 dev_err(dev->dev, "inconsistent synclko settings\n"); 4936 return -EINVAL; 4937 } 4938 4939 dev->wakeup_source = of_property_read_bool(dev->dev->of_node, 4940 "wakeup-source"); 4941 dev->pme_active_high = of_property_read_bool(dev->dev->of_node, 4942 "microchip,pme-active-high"); 4943 } 4944 4945 ret = dsa_register_switch(dev->ds); 4946 if (ret) { 4947 dev->dev_ops->exit(dev); 4948 return ret; 4949 } 4950 4951 /* Read MIB counters every 30 seconds to avoid overflow. */ 4952 dev->mib_read_interval = msecs_to_jiffies(5000); 4953 4954 /* Start the MIB timer. */ 4955 schedule_delayed_work(&dev->mib_read, 0); 4956 4957 return ret; 4958 } 4959 EXPORT_SYMBOL(ksz_switch_register); 4960 4961 void ksz_switch_remove(struct ksz_device *dev) 4962 { 4963 /* timer started */ 4964 if (dev->mib_read_interval) { 4965 dev->mib_read_interval = 0; 4966 cancel_delayed_work_sync(&dev->mib_read); 4967 } 4968 4969 dev->dev_ops->exit(dev); 4970 dsa_unregister_switch(dev->ds); 4971 4972 if (dev->reset_gpio) 4973 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4974 4975 } 4976 EXPORT_SYMBOL(ksz_switch_remove); 4977 4978 #ifdef CONFIG_PM_SLEEP 4979 int ksz_switch_suspend(struct device *dev) 4980 { 4981 struct ksz_device *priv = dev_get_drvdata(dev); 4982 4983 return dsa_switch_suspend(priv->ds); 4984 } 4985 EXPORT_SYMBOL(ksz_switch_suspend); 4986 4987 int ksz_switch_resume(struct device *dev) 4988 { 4989 struct ksz_device *priv = dev_get_drvdata(dev); 4990 4991 return dsa_switch_resume(priv->ds); 4992 } 4993 EXPORT_SYMBOL(ksz_switch_resume); 4994 #endif 4995 4996 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 4997 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 4998 MODULE_LICENSE("GPL"); 4999