1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2025 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/if_hsr.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/of.h> 23 #include <linux/of_mdio.h> 24 #include <linux/of_net.h> 25 #include <linux/micrel_phy.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <net/dsa.h> 28 #include <net/ieee8021q.h> 29 #include <net/pkt_cls.h> 30 #include <net/switchdev.h> 31 32 #include "ksz_common.h" 33 #include "ksz_dcb.h" 34 #include "ksz_ptp.h" 35 #include "ksz8.h" 36 #include "ksz9477.h" 37 #include "lan937x.h" 38 39 #define MIB_COUNTER_NUM 0x20 40 41 struct ksz_stats_raw { 42 u64 rx_hi; 43 u64 rx_undersize; 44 u64 rx_fragments; 45 u64 rx_oversize; 46 u64 rx_jabbers; 47 u64 rx_symbol_err; 48 u64 rx_crc_err; 49 u64 rx_align_err; 50 u64 rx_mac_ctrl; 51 u64 rx_pause; 52 u64 rx_bcast; 53 u64 rx_mcast; 54 u64 rx_ucast; 55 u64 rx_64_or_less; 56 u64 rx_65_127; 57 u64 rx_128_255; 58 u64 rx_256_511; 59 u64 rx_512_1023; 60 u64 rx_1024_1522; 61 u64 rx_1523_2000; 62 u64 rx_2001; 63 u64 tx_hi; 64 u64 tx_late_col; 65 u64 tx_pause; 66 u64 tx_bcast; 67 u64 tx_mcast; 68 u64 tx_ucast; 69 u64 tx_deferred; 70 u64 tx_total_col; 71 u64 tx_exc_col; 72 u64 tx_single_col; 73 u64 tx_mult_col; 74 u64 rx_total; 75 u64 tx_total; 76 u64 rx_discards; 77 u64 tx_discards; 78 }; 79 80 struct ksz88xx_stats_raw { 81 u64 rx; 82 u64 rx_hi; 83 u64 rx_undersize; 84 u64 rx_fragments; 85 u64 rx_oversize; 86 u64 rx_jabbers; 87 u64 rx_symbol_err; 88 u64 rx_crc_err; 89 u64 rx_align_err; 90 u64 rx_mac_ctrl; 91 u64 rx_pause; 92 u64 rx_bcast; 93 u64 rx_mcast; 94 u64 rx_ucast; 95 u64 rx_64_or_less; 96 u64 rx_65_127; 97 u64 rx_128_255; 98 u64 rx_256_511; 99 u64 rx_512_1023; 100 u64 rx_1024_1522; 101 u64 tx; 102 u64 tx_hi; 103 u64 tx_late_col; 104 u64 tx_pause; 105 u64 tx_bcast; 106 u64 tx_mcast; 107 u64 tx_ucast; 108 u64 tx_deferred; 109 u64 tx_total_col; 110 u64 tx_exc_col; 111 u64 tx_single_col; 112 u64 tx_mult_col; 113 u64 rx_discards; 114 u64 tx_discards; 115 }; 116 117 static const struct ksz_mib_names ksz88xx_mib_names[] = { 118 { 0x00, "rx" }, 119 { 0x01, "rx_hi" }, 120 { 0x02, "rx_undersize" }, 121 { 0x03, "rx_fragments" }, 122 { 0x04, "rx_oversize" }, 123 { 0x05, "rx_jabbers" }, 124 { 0x06, "rx_symbol_err" }, 125 { 0x07, "rx_crc_err" }, 126 { 0x08, "rx_align_err" }, 127 { 0x09, "rx_mac_ctrl" }, 128 { 0x0a, "rx_pause" }, 129 { 0x0b, "rx_bcast" }, 130 { 0x0c, "rx_mcast" }, 131 { 0x0d, "rx_ucast" }, 132 { 0x0e, "rx_64_or_less" }, 133 { 0x0f, "rx_65_127" }, 134 { 0x10, "rx_128_255" }, 135 { 0x11, "rx_256_511" }, 136 { 0x12, "rx_512_1023" }, 137 { 0x13, "rx_1024_1522" }, 138 { 0x14, "tx" }, 139 { 0x15, "tx_hi" }, 140 { 0x16, "tx_late_col" }, 141 { 0x17, "tx_pause" }, 142 { 0x18, "tx_bcast" }, 143 { 0x19, "tx_mcast" }, 144 { 0x1a, "tx_ucast" }, 145 { 0x1b, "tx_deferred" }, 146 { 0x1c, "tx_total_col" }, 147 { 0x1d, "tx_exc_col" }, 148 { 0x1e, "tx_single_col" }, 149 { 0x1f, "tx_mult_col" }, 150 { 0x100, "rx_discards" }, 151 { 0x101, "tx_discards" }, 152 }; 153 154 static const struct ksz_mib_names ksz9477_mib_names[] = { 155 { 0x00, "rx_hi" }, 156 { 0x01, "rx_undersize" }, 157 { 0x02, "rx_fragments" }, 158 { 0x03, "rx_oversize" }, 159 { 0x04, "rx_jabbers" }, 160 { 0x05, "rx_symbol_err" }, 161 { 0x06, "rx_crc_err" }, 162 { 0x07, "rx_align_err" }, 163 { 0x08, "rx_mac_ctrl" }, 164 { 0x09, "rx_pause" }, 165 { 0x0A, "rx_bcast" }, 166 { 0x0B, "rx_mcast" }, 167 { 0x0C, "rx_ucast" }, 168 { 0x0D, "rx_64_or_less" }, 169 { 0x0E, "rx_65_127" }, 170 { 0x0F, "rx_128_255" }, 171 { 0x10, "rx_256_511" }, 172 { 0x11, "rx_512_1023" }, 173 { 0x12, "rx_1024_1522" }, 174 { 0x13, "rx_1523_2000" }, 175 { 0x14, "rx_2001" }, 176 { 0x15, "tx_hi" }, 177 { 0x16, "tx_late_col" }, 178 { 0x17, "tx_pause" }, 179 { 0x18, "tx_bcast" }, 180 { 0x19, "tx_mcast" }, 181 { 0x1A, "tx_ucast" }, 182 { 0x1B, "tx_deferred" }, 183 { 0x1C, "tx_total_col" }, 184 { 0x1D, "tx_exc_col" }, 185 { 0x1E, "tx_single_col" }, 186 { 0x1F, "tx_mult_col" }, 187 { 0x80, "rx_total" }, 188 { 0x81, "tx_total" }, 189 { 0x82, "rx_discards" }, 190 { 0x83, "tx_discards" }, 191 }; 192 193 struct ksz_driver_strength_prop { 194 const char *name; 195 int offset; 196 int value; 197 }; 198 199 enum ksz_driver_strength_type { 200 KSZ_DRIVER_STRENGTH_HI, 201 KSZ_DRIVER_STRENGTH_LO, 202 KSZ_DRIVER_STRENGTH_IO, 203 }; 204 205 /** 206 * struct ksz_drive_strength - drive strength mapping 207 * @reg_val: register value 208 * @microamp: microamp value 209 */ 210 struct ksz_drive_strength { 211 u32 reg_val; 212 u32 microamp; 213 }; 214 215 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants 216 * 217 * This values are not documented in KSZ9477 variants but confirmed by 218 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893 219 * and KSZ8563 are using same register (drive strength) settings like KSZ8795. 220 * 221 * Documentation in KSZ8795CLX provides more information with some 222 * recommendations: 223 * - for high speed signals 224 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using 225 * 2.5V or 3.3V VDDIO. 226 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with 227 * using 1.8V VDDIO. 228 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V 229 * or 3.3V VDDIO. 230 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO. 231 * 5. In same interface, the heavy loading should use higher one of the 232 * drive current strength. 233 * - for low speed signals 234 * 1. 3.3V VDDIO, use either 4 mA or 8 mA. 235 * 2. 2.5V VDDIO, use either 8 mA or 12 mA. 236 * 3. 1.8V VDDIO, use either 12 mA or 16 mA. 237 * 4. If it is heavy loading, can use higher drive current strength. 238 */ 239 static const struct ksz_drive_strength ksz9477_drive_strengths[] = { 240 { SW_DRIVE_STRENGTH_2MA, 2000 }, 241 { SW_DRIVE_STRENGTH_4MA, 4000 }, 242 { SW_DRIVE_STRENGTH_8MA, 8000 }, 243 { SW_DRIVE_STRENGTH_12MA, 12000 }, 244 { SW_DRIVE_STRENGTH_16MA, 16000 }, 245 { SW_DRIVE_STRENGTH_20MA, 20000 }, 246 { SW_DRIVE_STRENGTH_24MA, 24000 }, 247 { SW_DRIVE_STRENGTH_28MA, 28000 }, 248 }; 249 250 /* ksz88x3_drive_strengths - Drive strength mapping for KSZ8863, KSZ8873, .. 251 * variants. 252 * This values are documented in KSZ8873 and KSZ8863 datasheets. 253 */ 254 static const struct ksz_drive_strength ksz88x3_drive_strengths[] = { 255 { 0, 8000 }, 256 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 }, 257 }; 258 259 static void ksz88x3_phylink_mac_config(struct phylink_config *config, 260 unsigned int mode, 261 const struct phylink_link_state *state); 262 static void ksz_phylink_mac_config(struct phylink_config *config, 263 unsigned int mode, 264 const struct phylink_link_state *state); 265 static void ksz_phylink_mac_link_down(struct phylink_config *config, 266 unsigned int mode, 267 phy_interface_t interface); 268 269 /** 270 * ksz_phylink_mac_disable_tx_lpi() - Callback to signal LPI support (Dummy) 271 * @config: phylink config structure 272 * 273 * This function is a dummy handler. See ksz_phylink_mac_enable_tx_lpi() for 274 * a detailed explanation of EEE/LPI handling in KSZ switches. 275 */ 276 static void ksz_phylink_mac_disable_tx_lpi(struct phylink_config *config) 277 { 278 } 279 280 /** 281 * ksz_phylink_mac_enable_tx_lpi() - Callback to signal LPI support (Dummy) 282 * @config: phylink config structure 283 * @timer: timer value before entering LPI (unused) 284 * @tx_clock_stop: whether to stop the TX clock in LPI mode (unused) 285 * 286 * This function signals to phylink that the driver architecture supports 287 * LPI management, enabling phylink to control EEE advertisement during 288 * negotiation according to IEEE Std 802.3 (Clause 78). 289 * 290 * Hardware Management of EEE/LPI State: 291 * For KSZ switch ports with integrated PHYs (e.g., KSZ9893R ports 1-2), 292 * observation and testing suggest that the actual EEE / Low Power Idle (LPI) 293 * state transitions are managed autonomously by the hardware based on 294 * the auto-negotiation results. (Note: While the datasheet describes EEE 295 * operation based on negotiation, it doesn't explicitly detail the internal 296 * MAC/PHY interaction, so autonomous hardware management of the MAC state 297 * for LPI is inferred from observed behavior). 298 * This hardware control, consistent with the switch's ability to operate 299 * autonomously via strapping, means MAC-level software intervention is not 300 * required or exposed for managing the LPI state once EEE is negotiated. 301 * (Ref: KSZ9893R Data Sheet DS00002420D, primarily Section 4.7.5 explaining 302 * EEE, also Sections 4.1.7 on Auto-Negotiation and 3.2.1 on Configuration 303 * Straps). 304 * 305 * Additionally, ports configured as MAC interfaces (e.g., KSZ9893R port 3) 306 * lack documented MAC-level LPI control. 307 * 308 * Therefore, this callback performs no action and serves primarily to inform 309 * phylink of LPI awareness and to document the inferred hardware behavior. 310 * 311 * Returns: 0 (Always success) 312 */ 313 static int ksz_phylink_mac_enable_tx_lpi(struct phylink_config *config, 314 u32 timer, bool tx_clock_stop) 315 { 316 return 0; 317 } 318 319 static const struct phylink_mac_ops ksz88x3_phylink_mac_ops = { 320 .mac_config = ksz88x3_phylink_mac_config, 321 .mac_link_down = ksz_phylink_mac_link_down, 322 .mac_link_up = ksz8_phylink_mac_link_up, 323 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 324 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 325 }; 326 327 static const struct phylink_mac_ops ksz8_phylink_mac_ops = { 328 .mac_config = ksz_phylink_mac_config, 329 .mac_link_down = ksz_phylink_mac_link_down, 330 .mac_link_up = ksz8_phylink_mac_link_up, 331 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 332 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 333 }; 334 335 static const struct ksz_dev_ops ksz8463_dev_ops = { 336 .setup = ksz8_setup, 337 .get_port_addr = ksz8463_get_port_addr, 338 .cfg_port_member = ksz8_cfg_port_member, 339 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 340 .port_setup = ksz8_port_setup, 341 .r_phy = ksz8463_r_phy, 342 .w_phy = ksz8463_w_phy, 343 .r_mib_cnt = ksz8_r_mib_cnt, 344 .r_mib_pkt = ksz8_r_mib_pkt, 345 .r_mib_stat64 = ksz88xx_r_mib_stats64, 346 .freeze_mib = ksz8_freeze_mib, 347 .port_init_cnt = ksz8_port_init_cnt, 348 .fdb_dump = ksz8_fdb_dump, 349 .fdb_add = ksz8_fdb_add, 350 .fdb_del = ksz8_fdb_del, 351 .mdb_add = ksz8_mdb_add, 352 .mdb_del = ksz8_mdb_del, 353 .vlan_filtering = ksz8_port_vlan_filtering, 354 .vlan_add = ksz8_port_vlan_add, 355 .vlan_del = ksz8_port_vlan_del, 356 .mirror_add = ksz8_port_mirror_add, 357 .mirror_del = ksz8_port_mirror_del, 358 .get_caps = ksz8_get_caps, 359 .config_cpu_port = ksz8_config_cpu_port, 360 .enable_stp_addr = ksz8_enable_stp_addr, 361 .reset = ksz8_reset_switch, 362 .init = ksz8_switch_init, 363 .exit = ksz8_switch_exit, 364 .change_mtu = ksz8_change_mtu, 365 }; 366 367 static const struct ksz_dev_ops ksz88xx_dev_ops = { 368 .setup = ksz8_setup, 369 .get_port_addr = ksz8_get_port_addr, 370 .cfg_port_member = ksz8_cfg_port_member, 371 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 372 .port_setup = ksz8_port_setup, 373 .r_phy = ksz8_r_phy, 374 .w_phy = ksz8_w_phy, 375 .r_mib_cnt = ksz8_r_mib_cnt, 376 .r_mib_pkt = ksz8_r_mib_pkt, 377 .r_mib_stat64 = ksz88xx_r_mib_stats64, 378 .freeze_mib = ksz8_freeze_mib, 379 .port_init_cnt = ksz8_port_init_cnt, 380 .fdb_dump = ksz8_fdb_dump, 381 .fdb_add = ksz8_fdb_add, 382 .fdb_del = ksz8_fdb_del, 383 .mdb_add = ksz8_mdb_add, 384 .mdb_del = ksz8_mdb_del, 385 .vlan_filtering = ksz8_port_vlan_filtering, 386 .vlan_add = ksz8_port_vlan_add, 387 .vlan_del = ksz8_port_vlan_del, 388 .mirror_add = ksz8_port_mirror_add, 389 .mirror_del = ksz8_port_mirror_del, 390 .get_caps = ksz8_get_caps, 391 .config_cpu_port = ksz8_config_cpu_port, 392 .enable_stp_addr = ksz8_enable_stp_addr, 393 .reset = ksz8_reset_switch, 394 .init = ksz8_switch_init, 395 .exit = ksz8_switch_exit, 396 .change_mtu = ksz8_change_mtu, 397 .pme_write8 = ksz8_pme_write8, 398 .pme_pread8 = ksz8_pme_pread8, 399 .pme_pwrite8 = ksz8_pme_pwrite8, 400 }; 401 402 static const struct ksz_dev_ops ksz87xx_dev_ops = { 403 .setup = ksz8_setup, 404 .get_port_addr = ksz8_get_port_addr, 405 .cfg_port_member = ksz8_cfg_port_member, 406 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 407 .port_setup = ksz8_port_setup, 408 .r_phy = ksz8_r_phy, 409 .w_phy = ksz8_w_phy, 410 .r_mib_cnt = ksz8_r_mib_cnt, 411 .r_mib_pkt = ksz8_r_mib_pkt, 412 .r_mib_stat64 = ksz_r_mib_stats64, 413 .freeze_mib = ksz8_freeze_mib, 414 .port_init_cnt = ksz8_port_init_cnt, 415 .fdb_dump = ksz8_fdb_dump, 416 .fdb_add = ksz8_fdb_add, 417 .fdb_del = ksz8_fdb_del, 418 .mdb_add = ksz8_mdb_add, 419 .mdb_del = ksz8_mdb_del, 420 .vlan_filtering = ksz8_port_vlan_filtering, 421 .vlan_add = ksz8_port_vlan_add, 422 .vlan_del = ksz8_port_vlan_del, 423 .mirror_add = ksz8_port_mirror_add, 424 .mirror_del = ksz8_port_mirror_del, 425 .get_caps = ksz8_get_caps, 426 .config_cpu_port = ksz8_config_cpu_port, 427 .enable_stp_addr = ksz8_enable_stp_addr, 428 .reset = ksz8_reset_switch, 429 .init = ksz8_switch_init, 430 .exit = ksz8_switch_exit, 431 .change_mtu = ksz8_change_mtu, 432 .pme_write8 = ksz8_pme_write8, 433 .pme_pread8 = ksz8_pme_pread8, 434 .pme_pwrite8 = ksz8_pme_pwrite8, 435 }; 436 437 static void ksz9477_phylink_mac_link_up(struct phylink_config *config, 438 struct phy_device *phydev, 439 unsigned int mode, 440 phy_interface_t interface, 441 int speed, int duplex, bool tx_pause, 442 bool rx_pause); 443 444 static struct phylink_pcs * 445 ksz_phylink_mac_select_pcs(struct phylink_config *config, 446 phy_interface_t interface) 447 { 448 struct dsa_port *dp = dsa_phylink_to_port(config); 449 struct ksz_device *dev = dp->ds->priv; 450 struct ksz_port *p = &dev->ports[dp->index]; 451 452 if (ksz_is_sgmii_port(dev, dp->index) && 453 (interface == PHY_INTERFACE_MODE_SGMII || 454 interface == PHY_INTERFACE_MODE_1000BASEX)) 455 return p->pcs; 456 457 return NULL; 458 } 459 460 static const struct phylink_mac_ops ksz9477_phylink_mac_ops = { 461 .mac_config = ksz_phylink_mac_config, 462 .mac_link_down = ksz_phylink_mac_link_down, 463 .mac_link_up = ksz9477_phylink_mac_link_up, 464 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 465 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 466 .mac_select_pcs = ksz_phylink_mac_select_pcs, 467 }; 468 469 static const struct ksz_dev_ops ksz9477_dev_ops = { 470 .setup = ksz9477_setup, 471 .get_port_addr = ksz9477_get_port_addr, 472 .cfg_port_member = ksz9477_cfg_port_member, 473 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 474 .port_setup = ksz9477_port_setup, 475 .set_ageing_time = ksz9477_set_ageing_time, 476 .r_phy = ksz9477_r_phy, 477 .w_phy = ksz9477_w_phy, 478 .r_mib_cnt = ksz9477_r_mib_cnt, 479 .r_mib_pkt = ksz9477_r_mib_pkt, 480 .r_mib_stat64 = ksz_r_mib_stats64, 481 .freeze_mib = ksz9477_freeze_mib, 482 .port_init_cnt = ksz9477_port_init_cnt, 483 .vlan_filtering = ksz9477_port_vlan_filtering, 484 .vlan_add = ksz9477_port_vlan_add, 485 .vlan_del = ksz9477_port_vlan_del, 486 .mirror_add = ksz9477_port_mirror_add, 487 .mirror_del = ksz9477_port_mirror_del, 488 .get_caps = ksz9477_get_caps, 489 .fdb_dump = ksz9477_fdb_dump, 490 .fdb_add = ksz9477_fdb_add, 491 .fdb_del = ksz9477_fdb_del, 492 .mdb_add = ksz9477_mdb_add, 493 .mdb_del = ksz9477_mdb_del, 494 .change_mtu = ksz9477_change_mtu, 495 .pme_write8 = ksz_write8, 496 .pme_pread8 = ksz_pread8, 497 .pme_pwrite8 = ksz_pwrite8, 498 .config_cpu_port = ksz9477_config_cpu_port, 499 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc, 500 .enable_stp_addr = ksz9477_enable_stp_addr, 501 .reset = ksz9477_reset_switch, 502 .init = ksz9477_switch_init, 503 .exit = ksz9477_switch_exit, 504 .pcs_create = ksz9477_pcs_create, 505 }; 506 507 static const struct phylink_mac_ops lan937x_phylink_mac_ops = { 508 .mac_config = ksz_phylink_mac_config, 509 .mac_link_down = ksz_phylink_mac_link_down, 510 .mac_link_up = ksz9477_phylink_mac_link_up, 511 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 512 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 513 }; 514 515 static const struct ksz_dev_ops lan937x_dev_ops = { 516 .setup = lan937x_setup, 517 .teardown = lan937x_teardown, 518 .get_port_addr = ksz9477_get_port_addr, 519 .cfg_port_member = ksz9477_cfg_port_member, 520 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 521 .port_setup = lan937x_port_setup, 522 .set_ageing_time = lan937x_set_ageing_time, 523 .mdio_bus_preinit = lan937x_mdio_bus_preinit, 524 .create_phy_addr_map = lan937x_create_phy_addr_map, 525 .r_phy = lan937x_r_phy, 526 .w_phy = lan937x_w_phy, 527 .r_mib_cnt = ksz9477_r_mib_cnt, 528 .r_mib_pkt = ksz9477_r_mib_pkt, 529 .r_mib_stat64 = ksz_r_mib_stats64, 530 .freeze_mib = ksz9477_freeze_mib, 531 .port_init_cnt = ksz9477_port_init_cnt, 532 .vlan_filtering = ksz9477_port_vlan_filtering, 533 .vlan_add = ksz9477_port_vlan_add, 534 .vlan_del = ksz9477_port_vlan_del, 535 .mirror_add = ksz9477_port_mirror_add, 536 .mirror_del = ksz9477_port_mirror_del, 537 .get_caps = lan937x_phylink_get_caps, 538 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 539 .fdb_dump = ksz9477_fdb_dump, 540 .fdb_add = ksz9477_fdb_add, 541 .fdb_del = ksz9477_fdb_del, 542 .mdb_add = ksz9477_mdb_add, 543 .mdb_del = ksz9477_mdb_del, 544 .change_mtu = lan937x_change_mtu, 545 .config_cpu_port = lan937x_config_cpu_port, 546 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 547 .enable_stp_addr = ksz9477_enable_stp_addr, 548 .reset = lan937x_reset_switch, 549 .init = lan937x_switch_init, 550 .exit = lan937x_switch_exit, 551 }; 552 553 static const u16 ksz8463_regs[] = { 554 [REG_SW_MAC_ADDR] = 0x10, 555 [REG_IND_CTRL_0] = 0x30, 556 [REG_IND_DATA_8] = 0x26, 557 [REG_IND_DATA_CHECK] = 0x26, 558 [REG_IND_DATA_HI] = 0x28, 559 [REG_IND_DATA_LO] = 0x2C, 560 [REG_IND_MIB_CHECK] = 0x2F, 561 [P_FORCE_CTRL] = 0x0C, 562 [P_LINK_STATUS] = 0x0E, 563 [P_LOCAL_CTRL] = 0x0C, 564 [P_NEG_RESTART_CTRL] = 0x0D, 565 [P_REMOTE_STATUS] = 0x0E, 566 [P_SPEED_STATUS] = 0x0F, 567 [S_TAIL_TAG_CTRL] = 0xAD, 568 [P_STP_CTRL] = 0x6F, 569 [S_START_CTRL] = 0x01, 570 [S_BROADCAST_CTRL] = 0x06, 571 [S_MULTICAST_CTRL] = 0x04, 572 }; 573 574 static const u32 ksz8463_masks[] = { 575 [PORT_802_1P_REMAPPING] = BIT(3), 576 [SW_TAIL_TAG_ENABLE] = BIT(0), 577 [MIB_COUNTER_OVERFLOW] = BIT(7), 578 [MIB_COUNTER_VALID] = BIT(6), 579 [VLAN_TABLE_FID] = GENMASK(15, 12), 580 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 581 [VLAN_TABLE_VALID] = BIT(19), 582 [STATIC_MAC_TABLE_VALID] = BIT(19), 583 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 584 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 585 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 586 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 587 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 588 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 589 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 590 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 591 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 592 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 593 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 594 }; 595 596 static u8 ksz8463_shifts[] = { 597 [VLAN_TABLE_MEMBERSHIP_S] = 16, 598 [STATIC_MAC_FWD_PORTS] = 16, 599 [STATIC_MAC_FID] = 22, 600 [DYNAMIC_MAC_ENTRIES_H] = 8, 601 [DYNAMIC_MAC_ENTRIES] = 24, 602 [DYNAMIC_MAC_FID] = 16, 603 [DYNAMIC_MAC_TIMESTAMP] = 22, 604 [DYNAMIC_MAC_SRC_PORT] = 20, 605 }; 606 607 static const u16 ksz8795_regs[] = { 608 [REG_SW_MAC_ADDR] = 0x68, 609 [REG_IND_CTRL_0] = 0x6E, 610 [REG_IND_DATA_8] = 0x70, 611 [REG_IND_DATA_CHECK] = 0x72, 612 [REG_IND_DATA_HI] = 0x71, 613 [REG_IND_DATA_LO] = 0x75, 614 [REG_IND_MIB_CHECK] = 0x74, 615 [REG_IND_BYTE] = 0xA0, 616 [P_FORCE_CTRL] = 0x0C, 617 [P_LINK_STATUS] = 0x0E, 618 [P_LOCAL_CTRL] = 0x07, 619 [P_NEG_RESTART_CTRL] = 0x0D, 620 [P_REMOTE_STATUS] = 0x08, 621 [P_SPEED_STATUS] = 0x09, 622 [S_TAIL_TAG_CTRL] = 0x0C, 623 [P_STP_CTRL] = 0x02, 624 [S_START_CTRL] = 0x01, 625 [S_BROADCAST_CTRL] = 0x06, 626 [S_MULTICAST_CTRL] = 0x04, 627 [P_XMII_CTRL_0] = 0x06, 628 [P_XMII_CTRL_1] = 0x06, 629 [REG_SW_PME_CTRL] = 0x8003, 630 [REG_PORT_PME_STATUS] = 0x8003, 631 [REG_PORT_PME_CTRL] = 0x8007, 632 }; 633 634 static const u32 ksz8795_masks[] = { 635 [PORT_802_1P_REMAPPING] = BIT(7), 636 [SW_TAIL_TAG_ENABLE] = BIT(1), 637 [MIB_COUNTER_OVERFLOW] = BIT(6), 638 [MIB_COUNTER_VALID] = BIT(5), 639 [VLAN_TABLE_FID] = GENMASK(6, 0), 640 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 641 [VLAN_TABLE_VALID] = BIT(12), 642 [STATIC_MAC_TABLE_VALID] = BIT(21), 643 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 644 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 645 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 646 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 647 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 648 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 649 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 650 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 651 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 652 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 653 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 654 [P_MII_TX_FLOW_CTRL] = BIT(5), 655 [P_MII_RX_FLOW_CTRL] = BIT(5), 656 }; 657 658 static const u8 ksz8795_xmii_ctrl0[] = { 659 [P_MII_100MBIT] = 0, 660 [P_MII_10MBIT] = 1, 661 [P_MII_FULL_DUPLEX] = 0, 662 [P_MII_HALF_DUPLEX] = 1, 663 }; 664 665 static const u8 ksz8795_xmii_ctrl1[] = { 666 [P_RGMII_SEL] = 3, 667 [P_GMII_SEL] = 2, 668 [P_RMII_SEL] = 1, 669 [P_MII_SEL] = 0, 670 [P_GMII_1GBIT] = 1, 671 [P_GMII_NOT_1GBIT] = 0, 672 }; 673 674 static const u8 ksz8795_shifts[] = { 675 [VLAN_TABLE_MEMBERSHIP_S] = 7, 676 [VLAN_TABLE] = 16, 677 [STATIC_MAC_FWD_PORTS] = 16, 678 [STATIC_MAC_FID] = 24, 679 [DYNAMIC_MAC_ENTRIES_H] = 3, 680 [DYNAMIC_MAC_ENTRIES] = 29, 681 [DYNAMIC_MAC_FID] = 16, 682 [DYNAMIC_MAC_TIMESTAMP] = 27, 683 [DYNAMIC_MAC_SRC_PORT] = 24, 684 }; 685 686 static const u16 ksz8863_regs[] = { 687 [REG_SW_MAC_ADDR] = 0x70, 688 [REG_IND_CTRL_0] = 0x79, 689 [REG_IND_DATA_8] = 0x7B, 690 [REG_IND_DATA_CHECK] = 0x7B, 691 [REG_IND_DATA_HI] = 0x7C, 692 [REG_IND_DATA_LO] = 0x80, 693 [REG_IND_MIB_CHECK] = 0x80, 694 [P_FORCE_CTRL] = 0x0C, 695 [P_LINK_STATUS] = 0x0E, 696 [P_LOCAL_CTRL] = 0x0C, 697 [P_NEG_RESTART_CTRL] = 0x0D, 698 [P_REMOTE_STATUS] = 0x0E, 699 [P_SPEED_STATUS] = 0x0F, 700 [S_TAIL_TAG_CTRL] = 0x03, 701 [P_STP_CTRL] = 0x02, 702 [S_START_CTRL] = 0x01, 703 [S_BROADCAST_CTRL] = 0x06, 704 [S_MULTICAST_CTRL] = 0x04, 705 }; 706 707 static const u32 ksz8863_masks[] = { 708 [PORT_802_1P_REMAPPING] = BIT(3), 709 [SW_TAIL_TAG_ENABLE] = BIT(6), 710 [MIB_COUNTER_OVERFLOW] = BIT(7), 711 [MIB_COUNTER_VALID] = BIT(6), 712 [VLAN_TABLE_FID] = GENMASK(15, 12), 713 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 714 [VLAN_TABLE_VALID] = BIT(19), 715 [STATIC_MAC_TABLE_VALID] = BIT(19), 716 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 717 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 718 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 719 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 720 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 721 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 722 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 723 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 724 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 725 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 726 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 727 }; 728 729 static u8 ksz8863_shifts[] = { 730 [VLAN_TABLE_MEMBERSHIP_S] = 16, 731 [STATIC_MAC_FWD_PORTS] = 16, 732 [STATIC_MAC_FID] = 22, 733 [DYNAMIC_MAC_ENTRIES_H] = 8, 734 [DYNAMIC_MAC_ENTRIES] = 24, 735 [DYNAMIC_MAC_FID] = 16, 736 [DYNAMIC_MAC_TIMESTAMP] = 22, 737 [DYNAMIC_MAC_SRC_PORT] = 20, 738 }; 739 740 static const u16 ksz8895_regs[] = { 741 [REG_SW_MAC_ADDR] = 0x68, 742 [REG_IND_CTRL_0] = 0x6E, 743 [REG_IND_DATA_8] = 0x70, 744 [REG_IND_DATA_CHECK] = 0x72, 745 [REG_IND_DATA_HI] = 0x71, 746 [REG_IND_DATA_LO] = 0x75, 747 [REG_IND_MIB_CHECK] = 0x75, 748 [P_FORCE_CTRL] = 0x0C, 749 [P_LINK_STATUS] = 0x0E, 750 [P_LOCAL_CTRL] = 0x0C, 751 [P_NEG_RESTART_CTRL] = 0x0D, 752 [P_REMOTE_STATUS] = 0x0E, 753 [P_SPEED_STATUS] = 0x09, 754 [S_TAIL_TAG_CTRL] = 0x0C, 755 [P_STP_CTRL] = 0x02, 756 [S_START_CTRL] = 0x01, 757 [S_BROADCAST_CTRL] = 0x06, 758 [S_MULTICAST_CTRL] = 0x04, 759 }; 760 761 static const u32 ksz8895_masks[] = { 762 [PORT_802_1P_REMAPPING] = BIT(7), 763 [SW_TAIL_TAG_ENABLE] = BIT(1), 764 [MIB_COUNTER_OVERFLOW] = BIT(7), 765 [MIB_COUNTER_VALID] = BIT(6), 766 [VLAN_TABLE_FID] = GENMASK(6, 0), 767 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 768 [VLAN_TABLE_VALID] = BIT(12), 769 [STATIC_MAC_TABLE_VALID] = BIT(21), 770 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 771 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 772 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 773 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 774 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 775 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 776 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 777 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 778 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 779 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 780 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 781 }; 782 783 static const u8 ksz8895_shifts[] = { 784 [VLAN_TABLE_MEMBERSHIP_S] = 7, 785 [VLAN_TABLE] = 13, 786 [STATIC_MAC_FWD_PORTS] = 16, 787 [STATIC_MAC_FID] = 24, 788 [DYNAMIC_MAC_ENTRIES_H] = 3, 789 [DYNAMIC_MAC_ENTRIES] = 29, 790 [DYNAMIC_MAC_FID] = 16, 791 [DYNAMIC_MAC_TIMESTAMP] = 27, 792 [DYNAMIC_MAC_SRC_PORT] = 24, 793 }; 794 795 static const u16 ksz9477_regs[] = { 796 [REG_SW_MAC_ADDR] = 0x0302, 797 [P_STP_CTRL] = 0x0B04, 798 [S_START_CTRL] = 0x0300, 799 [S_BROADCAST_CTRL] = 0x0332, 800 [S_MULTICAST_CTRL] = 0x0331, 801 [P_XMII_CTRL_0] = 0x0300, 802 [P_XMII_CTRL_1] = 0x0301, 803 [REG_SW_PME_CTRL] = 0x0006, 804 [REG_PORT_PME_STATUS] = 0x0013, 805 [REG_PORT_PME_CTRL] = 0x0017, 806 }; 807 808 static const u32 ksz9477_masks[] = { 809 [ALU_STAT_WRITE] = 0, 810 [ALU_STAT_READ] = 1, 811 [P_MII_TX_FLOW_CTRL] = BIT(5), 812 [P_MII_RX_FLOW_CTRL] = BIT(3), 813 }; 814 815 static const u8 ksz9477_shifts[] = { 816 [ALU_STAT_INDEX] = 16, 817 }; 818 819 static const u8 ksz9477_xmii_ctrl0[] = { 820 [P_MII_100MBIT] = 1, 821 [P_MII_10MBIT] = 0, 822 [P_MII_FULL_DUPLEX] = 1, 823 [P_MII_HALF_DUPLEX] = 0, 824 }; 825 826 static const u8 ksz9477_xmii_ctrl1[] = { 827 [P_RGMII_SEL] = 0, 828 [P_RMII_SEL] = 1, 829 [P_GMII_SEL] = 2, 830 [P_MII_SEL] = 3, 831 [P_GMII_1GBIT] = 0, 832 [P_GMII_NOT_1GBIT] = 1, 833 }; 834 835 static const u32 lan937x_masks[] = { 836 [ALU_STAT_WRITE] = 1, 837 [ALU_STAT_READ] = 2, 838 [P_MII_TX_FLOW_CTRL] = BIT(5), 839 [P_MII_RX_FLOW_CTRL] = BIT(3), 840 }; 841 842 static const u8 lan937x_shifts[] = { 843 [ALU_STAT_INDEX] = 8, 844 }; 845 846 static const struct regmap_range ksz8563_valid_regs[] = { 847 regmap_reg_range(0x0000, 0x0003), 848 regmap_reg_range(0x0006, 0x0006), 849 regmap_reg_range(0x000f, 0x001f), 850 regmap_reg_range(0x0100, 0x0100), 851 regmap_reg_range(0x0104, 0x0107), 852 regmap_reg_range(0x010d, 0x010d), 853 regmap_reg_range(0x0110, 0x0113), 854 regmap_reg_range(0x0120, 0x012b), 855 regmap_reg_range(0x0201, 0x0201), 856 regmap_reg_range(0x0210, 0x0213), 857 regmap_reg_range(0x0300, 0x0300), 858 regmap_reg_range(0x0302, 0x031b), 859 regmap_reg_range(0x0320, 0x032b), 860 regmap_reg_range(0x0330, 0x0336), 861 regmap_reg_range(0x0338, 0x033e), 862 regmap_reg_range(0x0340, 0x035f), 863 regmap_reg_range(0x0370, 0x0370), 864 regmap_reg_range(0x0378, 0x0378), 865 regmap_reg_range(0x037c, 0x037d), 866 regmap_reg_range(0x0390, 0x0393), 867 regmap_reg_range(0x0400, 0x040e), 868 regmap_reg_range(0x0410, 0x042f), 869 regmap_reg_range(0x0500, 0x0519), 870 regmap_reg_range(0x0520, 0x054b), 871 regmap_reg_range(0x0550, 0x05b3), 872 873 /* port 1 */ 874 regmap_reg_range(0x1000, 0x1001), 875 regmap_reg_range(0x1004, 0x100b), 876 regmap_reg_range(0x1013, 0x1013), 877 regmap_reg_range(0x1017, 0x1017), 878 regmap_reg_range(0x101b, 0x101b), 879 regmap_reg_range(0x101f, 0x1021), 880 regmap_reg_range(0x1030, 0x1030), 881 regmap_reg_range(0x1100, 0x1111), 882 regmap_reg_range(0x111a, 0x111d), 883 regmap_reg_range(0x1122, 0x1127), 884 regmap_reg_range(0x112a, 0x112b), 885 regmap_reg_range(0x1136, 0x1139), 886 regmap_reg_range(0x113e, 0x113f), 887 regmap_reg_range(0x1400, 0x1401), 888 regmap_reg_range(0x1403, 0x1403), 889 regmap_reg_range(0x1410, 0x1417), 890 regmap_reg_range(0x1420, 0x1423), 891 regmap_reg_range(0x1500, 0x1507), 892 regmap_reg_range(0x1600, 0x1612), 893 regmap_reg_range(0x1800, 0x180f), 894 regmap_reg_range(0x1900, 0x1907), 895 regmap_reg_range(0x1914, 0x191b), 896 regmap_reg_range(0x1a00, 0x1a03), 897 regmap_reg_range(0x1a04, 0x1a08), 898 regmap_reg_range(0x1b00, 0x1b01), 899 regmap_reg_range(0x1b04, 0x1b04), 900 regmap_reg_range(0x1c00, 0x1c05), 901 regmap_reg_range(0x1c08, 0x1c1b), 902 903 /* port 2 */ 904 regmap_reg_range(0x2000, 0x2001), 905 regmap_reg_range(0x2004, 0x200b), 906 regmap_reg_range(0x2013, 0x2013), 907 regmap_reg_range(0x2017, 0x2017), 908 regmap_reg_range(0x201b, 0x201b), 909 regmap_reg_range(0x201f, 0x2021), 910 regmap_reg_range(0x2030, 0x2030), 911 regmap_reg_range(0x2100, 0x2111), 912 regmap_reg_range(0x211a, 0x211d), 913 regmap_reg_range(0x2122, 0x2127), 914 regmap_reg_range(0x212a, 0x212b), 915 regmap_reg_range(0x2136, 0x2139), 916 regmap_reg_range(0x213e, 0x213f), 917 regmap_reg_range(0x2400, 0x2401), 918 regmap_reg_range(0x2403, 0x2403), 919 regmap_reg_range(0x2410, 0x2417), 920 regmap_reg_range(0x2420, 0x2423), 921 regmap_reg_range(0x2500, 0x2507), 922 regmap_reg_range(0x2600, 0x2612), 923 regmap_reg_range(0x2800, 0x280f), 924 regmap_reg_range(0x2900, 0x2907), 925 regmap_reg_range(0x2914, 0x291b), 926 regmap_reg_range(0x2a00, 0x2a03), 927 regmap_reg_range(0x2a04, 0x2a08), 928 regmap_reg_range(0x2b00, 0x2b01), 929 regmap_reg_range(0x2b04, 0x2b04), 930 regmap_reg_range(0x2c00, 0x2c05), 931 regmap_reg_range(0x2c08, 0x2c1b), 932 933 /* port 3 */ 934 regmap_reg_range(0x3000, 0x3001), 935 regmap_reg_range(0x3004, 0x300b), 936 regmap_reg_range(0x3013, 0x3013), 937 regmap_reg_range(0x3017, 0x3017), 938 regmap_reg_range(0x301b, 0x301b), 939 regmap_reg_range(0x301f, 0x3021), 940 regmap_reg_range(0x3030, 0x3030), 941 regmap_reg_range(0x3300, 0x3301), 942 regmap_reg_range(0x3303, 0x3303), 943 regmap_reg_range(0x3400, 0x3401), 944 regmap_reg_range(0x3403, 0x3403), 945 regmap_reg_range(0x3410, 0x3417), 946 regmap_reg_range(0x3420, 0x3423), 947 regmap_reg_range(0x3500, 0x3507), 948 regmap_reg_range(0x3600, 0x3612), 949 regmap_reg_range(0x3800, 0x380f), 950 regmap_reg_range(0x3900, 0x3907), 951 regmap_reg_range(0x3914, 0x391b), 952 regmap_reg_range(0x3a00, 0x3a03), 953 regmap_reg_range(0x3a04, 0x3a08), 954 regmap_reg_range(0x3b00, 0x3b01), 955 regmap_reg_range(0x3b04, 0x3b04), 956 regmap_reg_range(0x3c00, 0x3c05), 957 regmap_reg_range(0x3c08, 0x3c1b), 958 }; 959 960 static const struct regmap_access_table ksz8563_register_set = { 961 .yes_ranges = ksz8563_valid_regs, 962 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 963 }; 964 965 static const struct regmap_range ksz9477_valid_regs[] = { 966 regmap_reg_range(0x0000, 0x0003), 967 regmap_reg_range(0x0006, 0x0006), 968 regmap_reg_range(0x0010, 0x001f), 969 regmap_reg_range(0x0100, 0x0100), 970 regmap_reg_range(0x0103, 0x0107), 971 regmap_reg_range(0x010d, 0x010d), 972 regmap_reg_range(0x0110, 0x0113), 973 regmap_reg_range(0x0120, 0x012b), 974 regmap_reg_range(0x0201, 0x0201), 975 regmap_reg_range(0x0210, 0x0213), 976 regmap_reg_range(0x0300, 0x0300), 977 regmap_reg_range(0x0302, 0x031b), 978 regmap_reg_range(0x0320, 0x032b), 979 regmap_reg_range(0x0330, 0x0336), 980 regmap_reg_range(0x0338, 0x033b), 981 regmap_reg_range(0x033e, 0x033e), 982 regmap_reg_range(0x0340, 0x035f), 983 regmap_reg_range(0x0370, 0x0370), 984 regmap_reg_range(0x0378, 0x0378), 985 regmap_reg_range(0x037c, 0x037d), 986 regmap_reg_range(0x0390, 0x0393), 987 regmap_reg_range(0x0400, 0x040e), 988 regmap_reg_range(0x0410, 0x042f), 989 regmap_reg_range(0x0444, 0x044b), 990 regmap_reg_range(0x0450, 0x046f), 991 regmap_reg_range(0x0500, 0x0519), 992 regmap_reg_range(0x0520, 0x054b), 993 regmap_reg_range(0x0550, 0x05b3), 994 regmap_reg_range(0x0604, 0x060b), 995 regmap_reg_range(0x0610, 0x0612), 996 regmap_reg_range(0x0614, 0x062c), 997 regmap_reg_range(0x0640, 0x0645), 998 regmap_reg_range(0x0648, 0x064d), 999 1000 /* port 1 */ 1001 regmap_reg_range(0x1000, 0x1001), 1002 regmap_reg_range(0x1013, 0x1013), 1003 regmap_reg_range(0x1017, 0x1017), 1004 regmap_reg_range(0x101b, 0x101b), 1005 regmap_reg_range(0x101f, 0x1020), 1006 regmap_reg_range(0x1030, 0x1030), 1007 regmap_reg_range(0x1100, 0x1115), 1008 regmap_reg_range(0x111a, 0x111f), 1009 regmap_reg_range(0x1120, 0x112b), 1010 regmap_reg_range(0x1134, 0x113b), 1011 regmap_reg_range(0x113c, 0x113f), 1012 regmap_reg_range(0x1400, 0x1401), 1013 regmap_reg_range(0x1403, 0x1403), 1014 regmap_reg_range(0x1410, 0x1417), 1015 regmap_reg_range(0x1420, 0x1423), 1016 regmap_reg_range(0x1500, 0x1507), 1017 regmap_reg_range(0x1600, 0x1613), 1018 regmap_reg_range(0x1800, 0x180f), 1019 regmap_reg_range(0x1820, 0x1827), 1020 regmap_reg_range(0x1830, 0x1837), 1021 regmap_reg_range(0x1840, 0x184b), 1022 regmap_reg_range(0x1900, 0x1907), 1023 regmap_reg_range(0x1914, 0x191b), 1024 regmap_reg_range(0x1920, 0x1920), 1025 regmap_reg_range(0x1923, 0x1927), 1026 regmap_reg_range(0x1a00, 0x1a03), 1027 regmap_reg_range(0x1a04, 0x1a07), 1028 regmap_reg_range(0x1b00, 0x1b01), 1029 regmap_reg_range(0x1b04, 0x1b04), 1030 regmap_reg_range(0x1c00, 0x1c05), 1031 regmap_reg_range(0x1c08, 0x1c1b), 1032 1033 /* port 2 */ 1034 regmap_reg_range(0x2000, 0x2001), 1035 regmap_reg_range(0x2013, 0x2013), 1036 regmap_reg_range(0x2017, 0x2017), 1037 regmap_reg_range(0x201b, 0x201b), 1038 regmap_reg_range(0x201f, 0x2020), 1039 regmap_reg_range(0x2030, 0x2030), 1040 regmap_reg_range(0x2100, 0x2115), 1041 regmap_reg_range(0x211a, 0x211f), 1042 regmap_reg_range(0x2120, 0x212b), 1043 regmap_reg_range(0x2134, 0x213b), 1044 regmap_reg_range(0x213c, 0x213f), 1045 regmap_reg_range(0x2400, 0x2401), 1046 regmap_reg_range(0x2403, 0x2403), 1047 regmap_reg_range(0x2410, 0x2417), 1048 regmap_reg_range(0x2420, 0x2423), 1049 regmap_reg_range(0x2500, 0x2507), 1050 regmap_reg_range(0x2600, 0x2613), 1051 regmap_reg_range(0x2800, 0x280f), 1052 regmap_reg_range(0x2820, 0x2827), 1053 regmap_reg_range(0x2830, 0x2837), 1054 regmap_reg_range(0x2840, 0x284b), 1055 regmap_reg_range(0x2900, 0x2907), 1056 regmap_reg_range(0x2914, 0x291b), 1057 regmap_reg_range(0x2920, 0x2920), 1058 regmap_reg_range(0x2923, 0x2927), 1059 regmap_reg_range(0x2a00, 0x2a03), 1060 regmap_reg_range(0x2a04, 0x2a07), 1061 regmap_reg_range(0x2b00, 0x2b01), 1062 regmap_reg_range(0x2b04, 0x2b04), 1063 regmap_reg_range(0x2c00, 0x2c05), 1064 regmap_reg_range(0x2c08, 0x2c1b), 1065 1066 /* port 3 */ 1067 regmap_reg_range(0x3000, 0x3001), 1068 regmap_reg_range(0x3013, 0x3013), 1069 regmap_reg_range(0x3017, 0x3017), 1070 regmap_reg_range(0x301b, 0x301b), 1071 regmap_reg_range(0x301f, 0x3020), 1072 regmap_reg_range(0x3030, 0x3030), 1073 regmap_reg_range(0x3100, 0x3115), 1074 regmap_reg_range(0x311a, 0x311f), 1075 regmap_reg_range(0x3120, 0x312b), 1076 regmap_reg_range(0x3134, 0x313b), 1077 regmap_reg_range(0x313c, 0x313f), 1078 regmap_reg_range(0x3400, 0x3401), 1079 regmap_reg_range(0x3403, 0x3403), 1080 regmap_reg_range(0x3410, 0x3417), 1081 regmap_reg_range(0x3420, 0x3423), 1082 regmap_reg_range(0x3500, 0x3507), 1083 regmap_reg_range(0x3600, 0x3613), 1084 regmap_reg_range(0x3800, 0x380f), 1085 regmap_reg_range(0x3820, 0x3827), 1086 regmap_reg_range(0x3830, 0x3837), 1087 regmap_reg_range(0x3840, 0x384b), 1088 regmap_reg_range(0x3900, 0x3907), 1089 regmap_reg_range(0x3914, 0x391b), 1090 regmap_reg_range(0x3920, 0x3920), 1091 regmap_reg_range(0x3923, 0x3927), 1092 regmap_reg_range(0x3a00, 0x3a03), 1093 regmap_reg_range(0x3a04, 0x3a07), 1094 regmap_reg_range(0x3b00, 0x3b01), 1095 regmap_reg_range(0x3b04, 0x3b04), 1096 regmap_reg_range(0x3c00, 0x3c05), 1097 regmap_reg_range(0x3c08, 0x3c1b), 1098 1099 /* port 4 */ 1100 regmap_reg_range(0x4000, 0x4001), 1101 regmap_reg_range(0x4013, 0x4013), 1102 regmap_reg_range(0x4017, 0x4017), 1103 regmap_reg_range(0x401b, 0x401b), 1104 regmap_reg_range(0x401f, 0x4020), 1105 regmap_reg_range(0x4030, 0x4030), 1106 regmap_reg_range(0x4100, 0x4115), 1107 regmap_reg_range(0x411a, 0x411f), 1108 regmap_reg_range(0x4120, 0x412b), 1109 regmap_reg_range(0x4134, 0x413b), 1110 regmap_reg_range(0x413c, 0x413f), 1111 regmap_reg_range(0x4400, 0x4401), 1112 regmap_reg_range(0x4403, 0x4403), 1113 regmap_reg_range(0x4410, 0x4417), 1114 regmap_reg_range(0x4420, 0x4423), 1115 regmap_reg_range(0x4500, 0x4507), 1116 regmap_reg_range(0x4600, 0x4613), 1117 regmap_reg_range(0x4800, 0x480f), 1118 regmap_reg_range(0x4820, 0x4827), 1119 regmap_reg_range(0x4830, 0x4837), 1120 regmap_reg_range(0x4840, 0x484b), 1121 regmap_reg_range(0x4900, 0x4907), 1122 regmap_reg_range(0x4914, 0x491b), 1123 regmap_reg_range(0x4920, 0x4920), 1124 regmap_reg_range(0x4923, 0x4927), 1125 regmap_reg_range(0x4a00, 0x4a03), 1126 regmap_reg_range(0x4a04, 0x4a07), 1127 regmap_reg_range(0x4b00, 0x4b01), 1128 regmap_reg_range(0x4b04, 0x4b04), 1129 regmap_reg_range(0x4c00, 0x4c05), 1130 regmap_reg_range(0x4c08, 0x4c1b), 1131 1132 /* port 5 */ 1133 regmap_reg_range(0x5000, 0x5001), 1134 regmap_reg_range(0x5013, 0x5013), 1135 regmap_reg_range(0x5017, 0x5017), 1136 regmap_reg_range(0x501b, 0x501b), 1137 regmap_reg_range(0x501f, 0x5020), 1138 regmap_reg_range(0x5030, 0x5030), 1139 regmap_reg_range(0x5100, 0x5115), 1140 regmap_reg_range(0x511a, 0x511f), 1141 regmap_reg_range(0x5120, 0x512b), 1142 regmap_reg_range(0x5134, 0x513b), 1143 regmap_reg_range(0x513c, 0x513f), 1144 regmap_reg_range(0x5400, 0x5401), 1145 regmap_reg_range(0x5403, 0x5403), 1146 regmap_reg_range(0x5410, 0x5417), 1147 regmap_reg_range(0x5420, 0x5423), 1148 regmap_reg_range(0x5500, 0x5507), 1149 regmap_reg_range(0x5600, 0x5613), 1150 regmap_reg_range(0x5800, 0x580f), 1151 regmap_reg_range(0x5820, 0x5827), 1152 regmap_reg_range(0x5830, 0x5837), 1153 regmap_reg_range(0x5840, 0x584b), 1154 regmap_reg_range(0x5900, 0x5907), 1155 regmap_reg_range(0x5914, 0x591b), 1156 regmap_reg_range(0x5920, 0x5920), 1157 regmap_reg_range(0x5923, 0x5927), 1158 regmap_reg_range(0x5a00, 0x5a03), 1159 regmap_reg_range(0x5a04, 0x5a07), 1160 regmap_reg_range(0x5b00, 0x5b01), 1161 regmap_reg_range(0x5b04, 0x5b04), 1162 regmap_reg_range(0x5c00, 0x5c05), 1163 regmap_reg_range(0x5c08, 0x5c1b), 1164 1165 /* port 6 */ 1166 regmap_reg_range(0x6000, 0x6001), 1167 regmap_reg_range(0x6013, 0x6013), 1168 regmap_reg_range(0x6017, 0x6017), 1169 regmap_reg_range(0x601b, 0x601b), 1170 regmap_reg_range(0x601f, 0x6020), 1171 regmap_reg_range(0x6030, 0x6030), 1172 regmap_reg_range(0x6300, 0x6301), 1173 regmap_reg_range(0x6400, 0x6401), 1174 regmap_reg_range(0x6403, 0x6403), 1175 regmap_reg_range(0x6410, 0x6417), 1176 regmap_reg_range(0x6420, 0x6423), 1177 regmap_reg_range(0x6500, 0x6507), 1178 regmap_reg_range(0x6600, 0x6613), 1179 regmap_reg_range(0x6800, 0x680f), 1180 regmap_reg_range(0x6820, 0x6827), 1181 regmap_reg_range(0x6830, 0x6837), 1182 regmap_reg_range(0x6840, 0x684b), 1183 regmap_reg_range(0x6900, 0x6907), 1184 regmap_reg_range(0x6914, 0x691b), 1185 regmap_reg_range(0x6920, 0x6920), 1186 regmap_reg_range(0x6923, 0x6927), 1187 regmap_reg_range(0x6a00, 0x6a03), 1188 regmap_reg_range(0x6a04, 0x6a07), 1189 regmap_reg_range(0x6b00, 0x6b01), 1190 regmap_reg_range(0x6b04, 0x6b04), 1191 regmap_reg_range(0x6c00, 0x6c05), 1192 regmap_reg_range(0x6c08, 0x6c1b), 1193 1194 /* port 7 */ 1195 regmap_reg_range(0x7000, 0x7001), 1196 regmap_reg_range(0x7013, 0x7013), 1197 regmap_reg_range(0x7017, 0x7017), 1198 regmap_reg_range(0x701b, 0x701b), 1199 regmap_reg_range(0x701f, 0x7020), 1200 regmap_reg_range(0x7030, 0x7030), 1201 regmap_reg_range(0x7200, 0x7207), 1202 regmap_reg_range(0x7300, 0x7301), 1203 regmap_reg_range(0x7400, 0x7401), 1204 regmap_reg_range(0x7403, 0x7403), 1205 regmap_reg_range(0x7410, 0x7417), 1206 regmap_reg_range(0x7420, 0x7423), 1207 regmap_reg_range(0x7500, 0x7507), 1208 regmap_reg_range(0x7600, 0x7613), 1209 regmap_reg_range(0x7800, 0x780f), 1210 regmap_reg_range(0x7820, 0x7827), 1211 regmap_reg_range(0x7830, 0x7837), 1212 regmap_reg_range(0x7840, 0x784b), 1213 regmap_reg_range(0x7900, 0x7907), 1214 regmap_reg_range(0x7914, 0x791b), 1215 regmap_reg_range(0x7920, 0x7920), 1216 regmap_reg_range(0x7923, 0x7927), 1217 regmap_reg_range(0x7a00, 0x7a03), 1218 regmap_reg_range(0x7a04, 0x7a07), 1219 regmap_reg_range(0x7b00, 0x7b01), 1220 regmap_reg_range(0x7b04, 0x7b04), 1221 regmap_reg_range(0x7c00, 0x7c05), 1222 regmap_reg_range(0x7c08, 0x7c1b), 1223 }; 1224 1225 static const struct regmap_access_table ksz9477_register_set = { 1226 .yes_ranges = ksz9477_valid_regs, 1227 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 1228 }; 1229 1230 static const struct regmap_range ksz9896_valid_regs[] = { 1231 regmap_reg_range(0x0000, 0x0003), 1232 regmap_reg_range(0x0006, 0x0006), 1233 regmap_reg_range(0x0010, 0x001f), 1234 regmap_reg_range(0x0100, 0x0100), 1235 regmap_reg_range(0x0103, 0x0107), 1236 regmap_reg_range(0x010d, 0x010d), 1237 regmap_reg_range(0x0110, 0x0113), 1238 regmap_reg_range(0x0120, 0x0127), 1239 regmap_reg_range(0x0201, 0x0201), 1240 regmap_reg_range(0x0210, 0x0213), 1241 regmap_reg_range(0x0300, 0x0300), 1242 regmap_reg_range(0x0302, 0x030b), 1243 regmap_reg_range(0x0310, 0x031b), 1244 regmap_reg_range(0x0320, 0x032b), 1245 regmap_reg_range(0x0330, 0x0336), 1246 regmap_reg_range(0x0338, 0x033b), 1247 regmap_reg_range(0x033e, 0x033e), 1248 regmap_reg_range(0x0340, 0x035f), 1249 regmap_reg_range(0x0370, 0x0370), 1250 regmap_reg_range(0x0378, 0x0378), 1251 regmap_reg_range(0x037c, 0x037d), 1252 regmap_reg_range(0x0390, 0x0393), 1253 regmap_reg_range(0x0400, 0x040e), 1254 regmap_reg_range(0x0410, 0x042f), 1255 1256 /* port 1 */ 1257 regmap_reg_range(0x1000, 0x1001), 1258 regmap_reg_range(0x1013, 0x1013), 1259 regmap_reg_range(0x1017, 0x1017), 1260 regmap_reg_range(0x101b, 0x101b), 1261 regmap_reg_range(0x101f, 0x1020), 1262 regmap_reg_range(0x1030, 0x1030), 1263 regmap_reg_range(0x1100, 0x1115), 1264 regmap_reg_range(0x111a, 0x111f), 1265 regmap_reg_range(0x1120, 0x112b), 1266 regmap_reg_range(0x1134, 0x113b), 1267 regmap_reg_range(0x113c, 0x113f), 1268 regmap_reg_range(0x1400, 0x1401), 1269 regmap_reg_range(0x1403, 0x1403), 1270 regmap_reg_range(0x1410, 0x1417), 1271 regmap_reg_range(0x1420, 0x1423), 1272 regmap_reg_range(0x1500, 0x1507), 1273 regmap_reg_range(0x1600, 0x1612), 1274 regmap_reg_range(0x1800, 0x180f), 1275 regmap_reg_range(0x1820, 0x1827), 1276 regmap_reg_range(0x1830, 0x1837), 1277 regmap_reg_range(0x1840, 0x184b), 1278 regmap_reg_range(0x1900, 0x1907), 1279 regmap_reg_range(0x1914, 0x1915), 1280 regmap_reg_range(0x1a00, 0x1a03), 1281 regmap_reg_range(0x1a04, 0x1a07), 1282 regmap_reg_range(0x1b00, 0x1b01), 1283 regmap_reg_range(0x1b04, 0x1b04), 1284 1285 /* port 2 */ 1286 regmap_reg_range(0x2000, 0x2001), 1287 regmap_reg_range(0x2013, 0x2013), 1288 regmap_reg_range(0x2017, 0x2017), 1289 regmap_reg_range(0x201b, 0x201b), 1290 regmap_reg_range(0x201f, 0x2020), 1291 regmap_reg_range(0x2030, 0x2030), 1292 regmap_reg_range(0x2100, 0x2115), 1293 regmap_reg_range(0x211a, 0x211f), 1294 regmap_reg_range(0x2120, 0x212b), 1295 regmap_reg_range(0x2134, 0x213b), 1296 regmap_reg_range(0x213c, 0x213f), 1297 regmap_reg_range(0x2400, 0x2401), 1298 regmap_reg_range(0x2403, 0x2403), 1299 regmap_reg_range(0x2410, 0x2417), 1300 regmap_reg_range(0x2420, 0x2423), 1301 regmap_reg_range(0x2500, 0x2507), 1302 regmap_reg_range(0x2600, 0x2612), 1303 regmap_reg_range(0x2800, 0x280f), 1304 regmap_reg_range(0x2820, 0x2827), 1305 regmap_reg_range(0x2830, 0x2837), 1306 regmap_reg_range(0x2840, 0x284b), 1307 regmap_reg_range(0x2900, 0x2907), 1308 regmap_reg_range(0x2914, 0x2915), 1309 regmap_reg_range(0x2a00, 0x2a03), 1310 regmap_reg_range(0x2a04, 0x2a07), 1311 regmap_reg_range(0x2b00, 0x2b01), 1312 regmap_reg_range(0x2b04, 0x2b04), 1313 1314 /* port 3 */ 1315 regmap_reg_range(0x3000, 0x3001), 1316 regmap_reg_range(0x3013, 0x3013), 1317 regmap_reg_range(0x3017, 0x3017), 1318 regmap_reg_range(0x301b, 0x301b), 1319 regmap_reg_range(0x301f, 0x3020), 1320 regmap_reg_range(0x3030, 0x3030), 1321 regmap_reg_range(0x3100, 0x3115), 1322 regmap_reg_range(0x311a, 0x311f), 1323 regmap_reg_range(0x3120, 0x312b), 1324 regmap_reg_range(0x3134, 0x313b), 1325 regmap_reg_range(0x313c, 0x313f), 1326 regmap_reg_range(0x3400, 0x3401), 1327 regmap_reg_range(0x3403, 0x3403), 1328 regmap_reg_range(0x3410, 0x3417), 1329 regmap_reg_range(0x3420, 0x3423), 1330 regmap_reg_range(0x3500, 0x3507), 1331 regmap_reg_range(0x3600, 0x3612), 1332 regmap_reg_range(0x3800, 0x380f), 1333 regmap_reg_range(0x3820, 0x3827), 1334 regmap_reg_range(0x3830, 0x3837), 1335 regmap_reg_range(0x3840, 0x384b), 1336 regmap_reg_range(0x3900, 0x3907), 1337 regmap_reg_range(0x3914, 0x3915), 1338 regmap_reg_range(0x3a00, 0x3a03), 1339 regmap_reg_range(0x3a04, 0x3a07), 1340 regmap_reg_range(0x3b00, 0x3b01), 1341 regmap_reg_range(0x3b04, 0x3b04), 1342 1343 /* port 4 */ 1344 regmap_reg_range(0x4000, 0x4001), 1345 regmap_reg_range(0x4013, 0x4013), 1346 regmap_reg_range(0x4017, 0x4017), 1347 regmap_reg_range(0x401b, 0x401b), 1348 regmap_reg_range(0x401f, 0x4020), 1349 regmap_reg_range(0x4030, 0x4030), 1350 regmap_reg_range(0x4100, 0x4115), 1351 regmap_reg_range(0x411a, 0x411f), 1352 regmap_reg_range(0x4120, 0x412b), 1353 regmap_reg_range(0x4134, 0x413b), 1354 regmap_reg_range(0x413c, 0x413f), 1355 regmap_reg_range(0x4400, 0x4401), 1356 regmap_reg_range(0x4403, 0x4403), 1357 regmap_reg_range(0x4410, 0x4417), 1358 regmap_reg_range(0x4420, 0x4423), 1359 regmap_reg_range(0x4500, 0x4507), 1360 regmap_reg_range(0x4600, 0x4612), 1361 regmap_reg_range(0x4800, 0x480f), 1362 regmap_reg_range(0x4820, 0x4827), 1363 regmap_reg_range(0x4830, 0x4837), 1364 regmap_reg_range(0x4840, 0x484b), 1365 regmap_reg_range(0x4900, 0x4907), 1366 regmap_reg_range(0x4914, 0x4915), 1367 regmap_reg_range(0x4a00, 0x4a03), 1368 regmap_reg_range(0x4a04, 0x4a07), 1369 regmap_reg_range(0x4b00, 0x4b01), 1370 regmap_reg_range(0x4b04, 0x4b04), 1371 1372 /* port 5 */ 1373 regmap_reg_range(0x5000, 0x5001), 1374 regmap_reg_range(0x5013, 0x5013), 1375 regmap_reg_range(0x5017, 0x5017), 1376 regmap_reg_range(0x501b, 0x501b), 1377 regmap_reg_range(0x501f, 0x5020), 1378 regmap_reg_range(0x5030, 0x5030), 1379 regmap_reg_range(0x5100, 0x5115), 1380 regmap_reg_range(0x511a, 0x511f), 1381 regmap_reg_range(0x5120, 0x512b), 1382 regmap_reg_range(0x5134, 0x513b), 1383 regmap_reg_range(0x513c, 0x513f), 1384 regmap_reg_range(0x5400, 0x5401), 1385 regmap_reg_range(0x5403, 0x5403), 1386 regmap_reg_range(0x5410, 0x5417), 1387 regmap_reg_range(0x5420, 0x5423), 1388 regmap_reg_range(0x5500, 0x5507), 1389 regmap_reg_range(0x5600, 0x5612), 1390 regmap_reg_range(0x5800, 0x580f), 1391 regmap_reg_range(0x5820, 0x5827), 1392 regmap_reg_range(0x5830, 0x5837), 1393 regmap_reg_range(0x5840, 0x584b), 1394 regmap_reg_range(0x5900, 0x5907), 1395 regmap_reg_range(0x5914, 0x5915), 1396 regmap_reg_range(0x5a00, 0x5a03), 1397 regmap_reg_range(0x5a04, 0x5a07), 1398 regmap_reg_range(0x5b00, 0x5b01), 1399 regmap_reg_range(0x5b04, 0x5b04), 1400 1401 /* port 6 */ 1402 regmap_reg_range(0x6000, 0x6001), 1403 regmap_reg_range(0x6013, 0x6013), 1404 regmap_reg_range(0x6017, 0x6017), 1405 regmap_reg_range(0x601b, 0x601b), 1406 regmap_reg_range(0x601f, 0x6020), 1407 regmap_reg_range(0x6030, 0x6030), 1408 regmap_reg_range(0x6100, 0x6115), 1409 regmap_reg_range(0x611a, 0x611f), 1410 regmap_reg_range(0x6120, 0x612b), 1411 regmap_reg_range(0x6134, 0x613b), 1412 regmap_reg_range(0x613c, 0x613f), 1413 regmap_reg_range(0x6300, 0x6301), 1414 regmap_reg_range(0x6400, 0x6401), 1415 regmap_reg_range(0x6403, 0x6403), 1416 regmap_reg_range(0x6410, 0x6417), 1417 regmap_reg_range(0x6420, 0x6423), 1418 regmap_reg_range(0x6500, 0x6507), 1419 regmap_reg_range(0x6600, 0x6612), 1420 regmap_reg_range(0x6800, 0x680f), 1421 regmap_reg_range(0x6820, 0x6827), 1422 regmap_reg_range(0x6830, 0x6837), 1423 regmap_reg_range(0x6840, 0x684b), 1424 regmap_reg_range(0x6900, 0x6907), 1425 regmap_reg_range(0x6914, 0x6915), 1426 regmap_reg_range(0x6a00, 0x6a03), 1427 regmap_reg_range(0x6a04, 0x6a07), 1428 regmap_reg_range(0x6b00, 0x6b01), 1429 regmap_reg_range(0x6b04, 0x6b04), 1430 }; 1431 1432 static const struct regmap_access_table ksz9896_register_set = { 1433 .yes_ranges = ksz9896_valid_regs, 1434 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1435 }; 1436 1437 static const struct regmap_range ksz8873_valid_regs[] = { 1438 regmap_reg_range(0x00, 0x01), 1439 /* global control register */ 1440 regmap_reg_range(0x02, 0x0f), 1441 1442 /* port registers */ 1443 regmap_reg_range(0x10, 0x1d), 1444 regmap_reg_range(0x1e, 0x1f), 1445 regmap_reg_range(0x20, 0x2d), 1446 regmap_reg_range(0x2e, 0x2f), 1447 regmap_reg_range(0x30, 0x39), 1448 regmap_reg_range(0x3f, 0x3f), 1449 1450 /* advanced control registers */ 1451 regmap_reg_range(0x43, 0x43), 1452 regmap_reg_range(0x60, 0x6f), 1453 regmap_reg_range(0x70, 0x75), 1454 regmap_reg_range(0x76, 0x78), 1455 regmap_reg_range(0x79, 0x7a), 1456 regmap_reg_range(0x7b, 0x83), 1457 regmap_reg_range(0x8e, 0x99), 1458 regmap_reg_range(0x9a, 0xa5), 1459 regmap_reg_range(0xa6, 0xa6), 1460 regmap_reg_range(0xa7, 0xaa), 1461 regmap_reg_range(0xab, 0xae), 1462 regmap_reg_range(0xaf, 0xba), 1463 regmap_reg_range(0xbb, 0xbc), 1464 regmap_reg_range(0xbd, 0xbd), 1465 regmap_reg_range(0xc0, 0xc0), 1466 regmap_reg_range(0xc2, 0xc2), 1467 regmap_reg_range(0xc3, 0xc3), 1468 regmap_reg_range(0xc4, 0xc4), 1469 regmap_reg_range(0xc6, 0xc6), 1470 }; 1471 1472 static const struct regmap_access_table ksz8873_register_set = { 1473 .yes_ranges = ksz8873_valid_regs, 1474 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), 1475 }; 1476 1477 const struct ksz_chip_data ksz_switch_chips[] = { 1478 [KSZ8463] = { 1479 .chip_id = KSZ8463_CHIP_ID, 1480 .dev_name = "KSZ8463", 1481 .num_vlans = 16, 1482 .num_alus = 0, 1483 .num_statics = 8, 1484 .cpu_ports = 0x4, /* can be configured as cpu port */ 1485 .port_cnt = 3, 1486 .num_tx_queues = 4, 1487 .num_ipms = 4, 1488 .ops = &ksz8463_dev_ops, 1489 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1490 .mib_names = ksz88xx_mib_names, 1491 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1492 .reg_mib_cnt = MIB_COUNTER_NUM, 1493 .regs = ksz8463_regs, 1494 .masks = ksz8463_masks, 1495 .shifts = ksz8463_shifts, 1496 .supports_mii = {false, false, true}, 1497 .supports_rmii = {false, false, true}, 1498 .internal_phy = {true, true, false}, 1499 }, 1500 1501 [KSZ8563] = { 1502 .chip_id = KSZ8563_CHIP_ID, 1503 .dev_name = "KSZ8563", 1504 .num_vlans = 4096, 1505 .num_alus = 4096, 1506 .num_statics = 16, 1507 .cpu_ports = 0x07, /* can be configured as cpu port */ 1508 .port_cnt = 3, /* total port count */ 1509 .port_nirqs = 3, 1510 .num_tx_queues = 4, 1511 .num_ipms = 8, 1512 .tc_cbs_supported = true, 1513 .ops = &ksz9477_dev_ops, 1514 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1515 .mib_names = ksz9477_mib_names, 1516 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1517 .reg_mib_cnt = MIB_COUNTER_NUM, 1518 .regs = ksz9477_regs, 1519 .masks = ksz9477_masks, 1520 .shifts = ksz9477_shifts, 1521 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1522 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1523 .supports_mii = {false, false, true}, 1524 .supports_rmii = {false, false, true}, 1525 .supports_rgmii = {false, false, true}, 1526 .internal_phy = {true, true, false}, 1527 .gbit_capable = {false, false, true}, 1528 .ptp_capable = true, 1529 .wr_table = &ksz8563_register_set, 1530 .rd_table = &ksz8563_register_set, 1531 }, 1532 1533 [KSZ8795] = { 1534 .chip_id = KSZ8795_CHIP_ID, 1535 .dev_name = "KSZ8795", 1536 .num_vlans = 4096, 1537 .num_alus = 0, 1538 .num_statics = 32, 1539 .cpu_ports = 0x10, /* can be configured as cpu port */ 1540 .port_cnt = 5, /* total cpu and user ports */ 1541 .num_tx_queues = 4, 1542 .num_ipms = 4, 1543 .ops = &ksz87xx_dev_ops, 1544 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1545 .ksz87xx_eee_link_erratum = true, 1546 .mib_names = ksz9477_mib_names, 1547 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1548 .reg_mib_cnt = MIB_COUNTER_NUM, 1549 .regs = ksz8795_regs, 1550 .masks = ksz8795_masks, 1551 .shifts = ksz8795_shifts, 1552 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1553 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1554 .supports_mii = {false, false, false, false, true}, 1555 .supports_rmii = {false, false, false, false, true}, 1556 .supports_rgmii = {false, false, false, false, true}, 1557 .internal_phy = {true, true, true, true, false}, 1558 }, 1559 1560 [KSZ8794] = { 1561 /* WARNING 1562 * ======= 1563 * KSZ8794 is similar to KSZ8795, except the port map 1564 * contains a gap between external and CPU ports, the 1565 * port map is NOT continuous. The per-port register 1566 * map is shifted accordingly too, i.e. registers at 1567 * offset 0x40 are NOT used on KSZ8794 and they ARE 1568 * used on KSZ8795 for external port 3. 1569 * external cpu 1570 * KSZ8794 0,1,2 4 1571 * KSZ8795 0,1,2,3 4 1572 * KSZ8765 0,1,2,3 4 1573 * port_cnt is configured as 5, even though it is 4 1574 */ 1575 .chip_id = KSZ8794_CHIP_ID, 1576 .dev_name = "KSZ8794", 1577 .num_vlans = 4096, 1578 .num_alus = 0, 1579 .num_statics = 32, 1580 .cpu_ports = 0x10, /* can be configured as cpu port */ 1581 .port_cnt = 5, /* total cpu and user ports */ 1582 .num_tx_queues = 4, 1583 .num_ipms = 4, 1584 .ops = &ksz87xx_dev_ops, 1585 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1586 .ksz87xx_eee_link_erratum = true, 1587 .mib_names = ksz9477_mib_names, 1588 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1589 .reg_mib_cnt = MIB_COUNTER_NUM, 1590 .regs = ksz8795_regs, 1591 .masks = ksz8795_masks, 1592 .shifts = ksz8795_shifts, 1593 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1594 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1595 .supports_mii = {false, false, false, false, true}, 1596 .supports_rmii = {false, false, false, false, true}, 1597 .supports_rgmii = {false, false, false, false, true}, 1598 .internal_phy = {true, true, true, false, false}, 1599 }, 1600 1601 [KSZ8765] = { 1602 .chip_id = KSZ8765_CHIP_ID, 1603 .dev_name = "KSZ8765", 1604 .num_vlans = 4096, 1605 .num_alus = 0, 1606 .num_statics = 32, 1607 .cpu_ports = 0x10, /* can be configured as cpu port */ 1608 .port_cnt = 5, /* total cpu and user ports */ 1609 .num_tx_queues = 4, 1610 .num_ipms = 4, 1611 .ops = &ksz87xx_dev_ops, 1612 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1613 .ksz87xx_eee_link_erratum = true, 1614 .mib_names = ksz9477_mib_names, 1615 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1616 .reg_mib_cnt = MIB_COUNTER_NUM, 1617 .regs = ksz8795_regs, 1618 .masks = ksz8795_masks, 1619 .shifts = ksz8795_shifts, 1620 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1621 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1622 .supports_mii = {false, false, false, false, true}, 1623 .supports_rmii = {false, false, false, false, true}, 1624 .supports_rgmii = {false, false, false, false, true}, 1625 .internal_phy = {true, true, true, true, false}, 1626 }, 1627 1628 [KSZ88X3] = { 1629 .chip_id = KSZ88X3_CHIP_ID, 1630 .dev_name = "KSZ8863/KSZ8873", 1631 .num_vlans = 16, 1632 .num_alus = 0, 1633 .num_statics = 8, 1634 .cpu_ports = 0x4, /* can be configured as cpu port */ 1635 .port_cnt = 3, 1636 .num_tx_queues = 4, 1637 .num_ipms = 4, 1638 .ops = &ksz88xx_dev_ops, 1639 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1640 .mib_names = ksz88xx_mib_names, 1641 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1642 .reg_mib_cnt = MIB_COUNTER_NUM, 1643 .regs = ksz8863_regs, 1644 .masks = ksz8863_masks, 1645 .shifts = ksz8863_shifts, 1646 .supports_mii = {false, false, true}, 1647 .supports_rmii = {false, false, true}, 1648 .internal_phy = {true, true, false}, 1649 .wr_table = &ksz8873_register_set, 1650 .rd_table = &ksz8873_register_set, 1651 }, 1652 1653 [KSZ8864] = { 1654 /* WARNING 1655 * ======= 1656 * KSZ8864 is similar to KSZ8895, except the first port 1657 * does not exist. 1658 * external cpu 1659 * KSZ8864 1,2,3 4 1660 * KSZ8895 0,1,2,3 4 1661 * port_cnt is configured as 5, even though it is 4 1662 */ 1663 .chip_id = KSZ8864_CHIP_ID, 1664 .dev_name = "KSZ8864", 1665 .num_vlans = 4096, 1666 .num_alus = 0, 1667 .num_statics = 32, 1668 .cpu_ports = 0x10, /* can be configured as cpu port */ 1669 .port_cnt = 5, /* total cpu and user ports */ 1670 .num_tx_queues = 4, 1671 .num_ipms = 4, 1672 .ops = &ksz88xx_dev_ops, 1673 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1674 .mib_names = ksz88xx_mib_names, 1675 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1676 .reg_mib_cnt = MIB_COUNTER_NUM, 1677 .regs = ksz8895_regs, 1678 .masks = ksz8895_masks, 1679 .shifts = ksz8895_shifts, 1680 .supports_mii = {false, false, false, false, true}, 1681 .supports_rmii = {false, false, false, false, true}, 1682 .internal_phy = {false, true, true, true, false}, 1683 }, 1684 1685 [KSZ8895] = { 1686 .chip_id = KSZ8895_CHIP_ID, 1687 .dev_name = "KSZ8895", 1688 .num_vlans = 4096, 1689 .num_alus = 0, 1690 .num_statics = 32, 1691 .cpu_ports = 0x10, /* can be configured as cpu port */ 1692 .port_cnt = 5, /* total cpu and user ports */ 1693 .num_tx_queues = 4, 1694 .num_ipms = 4, 1695 .ops = &ksz88xx_dev_ops, 1696 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1697 .mib_names = ksz88xx_mib_names, 1698 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1699 .reg_mib_cnt = MIB_COUNTER_NUM, 1700 .regs = ksz8895_regs, 1701 .masks = ksz8895_masks, 1702 .shifts = ksz8895_shifts, 1703 .supports_mii = {false, false, false, false, true}, 1704 .supports_rmii = {false, false, false, false, true}, 1705 .internal_phy = {true, true, true, true, false}, 1706 }, 1707 1708 [KSZ9477] = { 1709 .chip_id = KSZ9477_CHIP_ID, 1710 .dev_name = "KSZ9477", 1711 .num_vlans = 4096, 1712 .num_alus = 4096, 1713 .num_statics = 16, 1714 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1715 .port_cnt = 7, /* total physical port count */ 1716 .port_nirqs = 4, 1717 .num_tx_queues = 4, 1718 .num_ipms = 8, 1719 .tc_cbs_supported = true, 1720 .ops = &ksz9477_dev_ops, 1721 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1722 .phy_errata_9477 = true, 1723 .mib_names = ksz9477_mib_names, 1724 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1725 .reg_mib_cnt = MIB_COUNTER_NUM, 1726 .regs = ksz9477_regs, 1727 .masks = ksz9477_masks, 1728 .shifts = ksz9477_shifts, 1729 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1730 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1731 .supports_mii = {false, false, false, false, 1732 false, true, false}, 1733 .supports_rmii = {false, false, false, false, 1734 false, true, false}, 1735 .supports_rgmii = {false, false, false, false, 1736 false, true, false}, 1737 .internal_phy = {true, true, true, true, 1738 true, false, false}, 1739 .gbit_capable = {true, true, true, true, true, true, true}, 1740 .ptp_capable = true, 1741 .sgmii_port = 7, 1742 .wr_table = &ksz9477_register_set, 1743 .rd_table = &ksz9477_register_set, 1744 }, 1745 1746 [KSZ9896] = { 1747 .chip_id = KSZ9896_CHIP_ID, 1748 .dev_name = "KSZ9896", 1749 .num_vlans = 4096, 1750 .num_alus = 4096, 1751 .num_statics = 16, 1752 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1753 .port_cnt = 6, /* total physical port count */ 1754 .port_nirqs = 2, 1755 .num_tx_queues = 4, 1756 .num_ipms = 8, 1757 .ops = &ksz9477_dev_ops, 1758 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1759 .phy_errata_9477 = true, 1760 .mib_names = ksz9477_mib_names, 1761 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1762 .reg_mib_cnt = MIB_COUNTER_NUM, 1763 .regs = ksz9477_regs, 1764 .masks = ksz9477_masks, 1765 .shifts = ksz9477_shifts, 1766 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1767 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1768 .supports_mii = {false, false, false, false, 1769 false, true}, 1770 .supports_rmii = {false, false, false, false, 1771 false, true}, 1772 .supports_rgmii = {false, false, false, false, 1773 false, true}, 1774 .internal_phy = {true, true, true, true, 1775 true, false}, 1776 .gbit_capable = {true, true, true, true, true, true}, 1777 .wr_table = &ksz9896_register_set, 1778 .rd_table = &ksz9896_register_set, 1779 }, 1780 1781 [KSZ9897] = { 1782 .chip_id = KSZ9897_CHIP_ID, 1783 .dev_name = "KSZ9897", 1784 .num_vlans = 4096, 1785 .num_alus = 4096, 1786 .num_statics = 16, 1787 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1788 .port_cnt = 7, /* total physical port count */ 1789 .port_nirqs = 2, 1790 .num_tx_queues = 4, 1791 .num_ipms = 8, 1792 .ops = &ksz9477_dev_ops, 1793 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1794 .phy_errata_9477 = true, 1795 .mib_names = ksz9477_mib_names, 1796 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1797 .reg_mib_cnt = MIB_COUNTER_NUM, 1798 .regs = ksz9477_regs, 1799 .masks = ksz9477_masks, 1800 .shifts = ksz9477_shifts, 1801 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1802 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1803 .supports_mii = {false, false, false, false, 1804 false, true, true}, 1805 .supports_rmii = {false, false, false, false, 1806 false, true, true}, 1807 .supports_rgmii = {false, false, false, false, 1808 false, true, true}, 1809 .internal_phy = {true, true, true, true, 1810 true, false, false}, 1811 .gbit_capable = {true, true, true, true, true, true, true}, 1812 }, 1813 1814 [KSZ9893] = { 1815 .chip_id = KSZ9893_CHIP_ID, 1816 .dev_name = "KSZ9893", 1817 .num_vlans = 4096, 1818 .num_alus = 4096, 1819 .num_statics = 16, 1820 .cpu_ports = 0x07, /* can be configured as cpu port */ 1821 .port_cnt = 3, /* total port count */ 1822 .port_nirqs = 2, 1823 .num_tx_queues = 4, 1824 .num_ipms = 8, 1825 .ops = &ksz9477_dev_ops, 1826 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1827 .mib_names = ksz9477_mib_names, 1828 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1829 .reg_mib_cnt = MIB_COUNTER_NUM, 1830 .regs = ksz9477_regs, 1831 .masks = ksz9477_masks, 1832 .shifts = ksz9477_shifts, 1833 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1834 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1835 .supports_mii = {false, false, true}, 1836 .supports_rmii = {false, false, true}, 1837 .supports_rgmii = {false, false, true}, 1838 .internal_phy = {true, true, false}, 1839 .gbit_capable = {true, true, true}, 1840 }, 1841 1842 [KSZ9563] = { 1843 .chip_id = KSZ9563_CHIP_ID, 1844 .dev_name = "KSZ9563", 1845 .num_vlans = 4096, 1846 .num_alus = 4096, 1847 .num_statics = 16, 1848 .cpu_ports = 0x07, /* can be configured as cpu port */ 1849 .port_cnt = 3, /* total port count */ 1850 .port_nirqs = 3, 1851 .num_tx_queues = 4, 1852 .num_ipms = 8, 1853 .tc_cbs_supported = true, 1854 .ops = &ksz9477_dev_ops, 1855 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1856 .mib_names = ksz9477_mib_names, 1857 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1858 .reg_mib_cnt = MIB_COUNTER_NUM, 1859 .regs = ksz9477_regs, 1860 .masks = ksz9477_masks, 1861 .shifts = ksz9477_shifts, 1862 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1863 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1864 .supports_mii = {false, false, true}, 1865 .supports_rmii = {false, false, true}, 1866 .supports_rgmii = {false, false, true}, 1867 .internal_phy = {true, true, false}, 1868 .gbit_capable = {true, true, true}, 1869 .ptp_capable = true, 1870 }, 1871 1872 [KSZ8567] = { 1873 .chip_id = KSZ8567_CHIP_ID, 1874 .dev_name = "KSZ8567", 1875 .num_vlans = 4096, 1876 .num_alus = 4096, 1877 .num_statics = 16, 1878 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1879 .port_cnt = 7, /* total port count */ 1880 .port_nirqs = 3, 1881 .num_tx_queues = 4, 1882 .num_ipms = 8, 1883 .tc_cbs_supported = true, 1884 .ops = &ksz9477_dev_ops, 1885 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1886 .phy_errata_9477 = true, 1887 .mib_names = ksz9477_mib_names, 1888 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1889 .reg_mib_cnt = MIB_COUNTER_NUM, 1890 .regs = ksz9477_regs, 1891 .masks = ksz9477_masks, 1892 .shifts = ksz9477_shifts, 1893 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1894 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1895 .supports_mii = {false, false, false, false, 1896 false, true, true}, 1897 .supports_rmii = {false, false, false, false, 1898 false, true, true}, 1899 .supports_rgmii = {false, false, false, false, 1900 false, true, true}, 1901 .internal_phy = {true, true, true, true, 1902 true, false, false}, 1903 .gbit_capable = {false, false, false, false, false, 1904 true, true}, 1905 .ptp_capable = true, 1906 }, 1907 1908 [KSZ9567] = { 1909 .chip_id = KSZ9567_CHIP_ID, 1910 .dev_name = "KSZ9567", 1911 .num_vlans = 4096, 1912 .num_alus = 4096, 1913 .num_statics = 16, 1914 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1915 .port_cnt = 7, /* total physical port count */ 1916 .port_nirqs = 3, 1917 .num_tx_queues = 4, 1918 .num_ipms = 8, 1919 .tc_cbs_supported = true, 1920 .ops = &ksz9477_dev_ops, 1921 .mib_names = ksz9477_mib_names, 1922 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1923 .reg_mib_cnt = MIB_COUNTER_NUM, 1924 .regs = ksz9477_regs, 1925 .masks = ksz9477_masks, 1926 .shifts = ksz9477_shifts, 1927 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1928 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1929 .supports_mii = {false, false, false, false, 1930 false, true, true}, 1931 .supports_rmii = {false, false, false, false, 1932 false, true, true}, 1933 .supports_rgmii = {false, false, false, false, 1934 false, true, true}, 1935 .internal_phy = {true, true, true, true, 1936 true, false, false}, 1937 .gbit_capable = {true, true, true, true, true, true, true}, 1938 .ptp_capable = true, 1939 }, 1940 1941 [LAN9370] = { 1942 .chip_id = LAN9370_CHIP_ID, 1943 .dev_name = "LAN9370", 1944 .num_vlans = 4096, 1945 .num_alus = 1024, 1946 .num_statics = 256, 1947 .cpu_ports = 0x10, /* can be configured as cpu port */ 1948 .port_cnt = 5, /* total physical port count */ 1949 .port_nirqs = 6, 1950 .num_tx_queues = 8, 1951 .num_ipms = 8, 1952 .tc_cbs_supported = true, 1953 .phy_side_mdio_supported = true, 1954 .ops = &lan937x_dev_ops, 1955 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1956 .mib_names = ksz9477_mib_names, 1957 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1958 .reg_mib_cnt = MIB_COUNTER_NUM, 1959 .regs = ksz9477_regs, 1960 .masks = lan937x_masks, 1961 .shifts = lan937x_shifts, 1962 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1963 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1964 .supports_mii = {false, false, false, false, true}, 1965 .supports_rmii = {false, false, false, false, true}, 1966 .supports_rgmii = {false, false, false, false, true}, 1967 .internal_phy = {true, true, true, true, false}, 1968 .ptp_capable = true, 1969 }, 1970 1971 [LAN9371] = { 1972 .chip_id = LAN9371_CHIP_ID, 1973 .dev_name = "LAN9371", 1974 .num_vlans = 4096, 1975 .num_alus = 1024, 1976 .num_statics = 256, 1977 .cpu_ports = 0x30, /* can be configured as cpu port */ 1978 .port_cnt = 6, /* total physical port count */ 1979 .port_nirqs = 6, 1980 .num_tx_queues = 8, 1981 .num_ipms = 8, 1982 .tc_cbs_supported = true, 1983 .phy_side_mdio_supported = true, 1984 .ops = &lan937x_dev_ops, 1985 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1986 .mib_names = ksz9477_mib_names, 1987 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1988 .reg_mib_cnt = MIB_COUNTER_NUM, 1989 .regs = ksz9477_regs, 1990 .masks = lan937x_masks, 1991 .shifts = lan937x_shifts, 1992 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1993 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1994 .supports_mii = {false, false, false, false, true, true}, 1995 .supports_rmii = {false, false, false, false, true, true}, 1996 .supports_rgmii = {false, false, false, false, true, true}, 1997 .internal_phy = {true, true, true, true, false, false}, 1998 .ptp_capable = true, 1999 }, 2000 2001 [LAN9372] = { 2002 .chip_id = LAN9372_CHIP_ID, 2003 .dev_name = "LAN9372", 2004 .num_vlans = 4096, 2005 .num_alus = 1024, 2006 .num_statics = 256, 2007 .cpu_ports = 0x30, /* can be configured as cpu port */ 2008 .port_cnt = 8, /* total physical port count */ 2009 .port_nirqs = 6, 2010 .num_tx_queues = 8, 2011 .num_ipms = 8, 2012 .tc_cbs_supported = true, 2013 .phy_side_mdio_supported = true, 2014 .ops = &lan937x_dev_ops, 2015 .phylink_mac_ops = &lan937x_phylink_mac_ops, 2016 .mib_names = ksz9477_mib_names, 2017 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 2018 .reg_mib_cnt = MIB_COUNTER_NUM, 2019 .regs = ksz9477_regs, 2020 .masks = lan937x_masks, 2021 .shifts = lan937x_shifts, 2022 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 2023 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 2024 .supports_mii = {false, false, false, false, 2025 true, true, false, false}, 2026 .supports_rmii = {false, false, false, false, 2027 true, true, false, false}, 2028 .supports_rgmii = {false, false, false, false, 2029 true, true, false, false}, 2030 .internal_phy = {true, true, true, true, 2031 false, false, true, true}, 2032 .ptp_capable = true, 2033 }, 2034 2035 [LAN9373] = { 2036 .chip_id = LAN9373_CHIP_ID, 2037 .dev_name = "LAN9373", 2038 .num_vlans = 4096, 2039 .num_alus = 1024, 2040 .num_statics = 256, 2041 .cpu_ports = 0x38, /* can be configured as cpu port */ 2042 .port_cnt = 5, /* total physical port count */ 2043 .port_nirqs = 6, 2044 .num_tx_queues = 8, 2045 .num_ipms = 8, 2046 .tc_cbs_supported = true, 2047 .phy_side_mdio_supported = true, 2048 .ops = &lan937x_dev_ops, 2049 .phylink_mac_ops = &lan937x_phylink_mac_ops, 2050 .mib_names = ksz9477_mib_names, 2051 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 2052 .reg_mib_cnt = MIB_COUNTER_NUM, 2053 .regs = ksz9477_regs, 2054 .masks = lan937x_masks, 2055 .shifts = lan937x_shifts, 2056 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 2057 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 2058 .supports_mii = {false, false, false, false, 2059 true, true, false, false}, 2060 .supports_rmii = {false, false, false, false, 2061 true, true, false, false}, 2062 .supports_rgmii = {false, false, false, false, 2063 true, true, false, false}, 2064 .internal_phy = {true, true, true, false, 2065 false, false, true, true}, 2066 .ptp_capable = true, 2067 }, 2068 2069 [LAN9374] = { 2070 .chip_id = LAN9374_CHIP_ID, 2071 .dev_name = "LAN9374", 2072 .num_vlans = 4096, 2073 .num_alus = 1024, 2074 .num_statics = 256, 2075 .cpu_ports = 0x30, /* can be configured as cpu port */ 2076 .port_cnt = 8, /* total physical port count */ 2077 .port_nirqs = 6, 2078 .num_tx_queues = 8, 2079 .num_ipms = 8, 2080 .tc_cbs_supported = true, 2081 .phy_side_mdio_supported = true, 2082 .ops = &lan937x_dev_ops, 2083 .phylink_mac_ops = &lan937x_phylink_mac_ops, 2084 .mib_names = ksz9477_mib_names, 2085 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 2086 .reg_mib_cnt = MIB_COUNTER_NUM, 2087 .regs = ksz9477_regs, 2088 .masks = lan937x_masks, 2089 .shifts = lan937x_shifts, 2090 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 2091 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 2092 .supports_mii = {false, false, false, false, 2093 true, true, false, false}, 2094 .supports_rmii = {false, false, false, false, 2095 true, true, false, false}, 2096 .supports_rgmii = {false, false, false, false, 2097 true, true, false, false}, 2098 .internal_phy = {true, true, true, true, 2099 false, false, true, true}, 2100 .ptp_capable = true, 2101 }, 2102 2103 [LAN9646] = { 2104 .chip_id = LAN9646_CHIP_ID, 2105 .dev_name = "LAN9646", 2106 .num_vlans = 4096, 2107 .num_alus = 4096, 2108 .num_statics = 16, 2109 .cpu_ports = 0x7F, /* can be configured as cpu port */ 2110 .port_cnt = 7, /* total physical port count */ 2111 .port_nirqs = 4, 2112 .num_tx_queues = 4, 2113 .num_ipms = 8, 2114 .ops = &ksz9477_dev_ops, 2115 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 2116 .phy_errata_9477 = true, 2117 .mib_names = ksz9477_mib_names, 2118 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 2119 .reg_mib_cnt = MIB_COUNTER_NUM, 2120 .regs = ksz9477_regs, 2121 .masks = ksz9477_masks, 2122 .shifts = ksz9477_shifts, 2123 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 2124 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 2125 .supports_mii = {false, false, false, false, 2126 false, true, true}, 2127 .supports_rmii = {false, false, false, false, 2128 false, true, true}, 2129 .supports_rgmii = {false, false, false, false, 2130 false, true, true}, 2131 .internal_phy = {true, true, true, true, 2132 true, false, false}, 2133 .gbit_capable = {true, true, true, true, true, true, true}, 2134 .sgmii_port = 7, 2135 .wr_table = &ksz9477_register_set, 2136 .rd_table = &ksz9477_register_set, 2137 }, 2138 }; 2139 EXPORT_SYMBOL_GPL(ksz_switch_chips); 2140 2141 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 2142 { 2143 int i; 2144 2145 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 2146 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 2147 2148 if (chip->chip_id == prod_num) 2149 return chip; 2150 } 2151 2152 return NULL; 2153 } 2154 2155 static int ksz_check_device_id(struct ksz_device *dev) 2156 { 2157 const struct ksz_chip_data *expected_chip_data; 2158 u32 expected_chip_id; 2159 2160 if (dev->pdata) { 2161 expected_chip_id = dev->pdata->chip_id; 2162 expected_chip_data = ksz_lookup_info(expected_chip_id); 2163 if (WARN_ON(!expected_chip_data)) 2164 return -ENODEV; 2165 } else { 2166 expected_chip_data = of_device_get_match_data(dev->dev); 2167 expected_chip_id = expected_chip_data->chip_id; 2168 } 2169 2170 if (expected_chip_id != dev->chip_id) { 2171 dev_err(dev->dev, 2172 "Device tree specifies chip %s but found %s, please fix it!\n", 2173 expected_chip_data->dev_name, dev->info->dev_name); 2174 return -ENODEV; 2175 } 2176 2177 return 0; 2178 } 2179 2180 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 2181 struct phylink_config *config) 2182 { 2183 struct ksz_device *dev = ds->priv; 2184 2185 if (dev->info->supports_mii[port]) 2186 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 2187 2188 if (dev->info->supports_rmii[port]) 2189 __set_bit(PHY_INTERFACE_MODE_RMII, 2190 config->supported_interfaces); 2191 2192 if (dev->info->supports_rgmii[port]) 2193 phy_interface_set_rgmii(config->supported_interfaces); 2194 2195 if (dev->info->internal_phy[port]) { 2196 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2197 config->supported_interfaces); 2198 /* Compatibility for phylib's default interface type when the 2199 * phy-mode property is absent 2200 */ 2201 __set_bit(PHY_INTERFACE_MODE_GMII, 2202 config->supported_interfaces); 2203 } 2204 2205 if (dev->dev_ops->get_caps) 2206 dev->dev_ops->get_caps(dev, port, config); 2207 2208 if (ds->ops->support_eee && ds->ops->support_eee(ds, port)) { 2209 memcpy(config->lpi_interfaces, config->supported_interfaces, 2210 sizeof(config->lpi_interfaces)); 2211 2212 config->lpi_capabilities = MAC_100FD; 2213 if (dev->info->gbit_capable[port]) 2214 config->lpi_capabilities |= MAC_1000FD; 2215 2216 /* EEE is fully operational */ 2217 config->eee_enabled_default = true; 2218 } 2219 } 2220 2221 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 2222 { 2223 struct ethtool_pause_stats *pstats; 2224 struct rtnl_link_stats64 *stats; 2225 struct ksz_stats_raw *raw; 2226 struct ksz_port_mib *mib; 2227 int ret; 2228 2229 mib = &dev->ports[port].mib; 2230 stats = &mib->stats64; 2231 pstats = &mib->pause_stats; 2232 raw = (struct ksz_stats_raw *)mib->counters; 2233 2234 spin_lock(&mib->stats64_lock); 2235 2236 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 2237 raw->rx_pause; 2238 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2239 raw->tx_pause; 2240 2241 /* HW counters are counting bytes + FCS which is not acceptable 2242 * for rtnl_link_stats64 interface 2243 */ 2244 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 2245 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 2246 2247 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2248 raw->rx_oversize; 2249 2250 stats->rx_crc_errors = raw->rx_crc_err; 2251 stats->rx_frame_errors = raw->rx_align_err; 2252 stats->rx_dropped = raw->rx_discards; 2253 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2254 stats->rx_frame_errors + stats->rx_dropped; 2255 2256 stats->tx_window_errors = raw->tx_late_col; 2257 stats->tx_fifo_errors = raw->tx_discards; 2258 stats->tx_aborted_errors = raw->tx_exc_col; 2259 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2260 stats->tx_aborted_errors; 2261 2262 stats->multicast = raw->rx_mcast; 2263 stats->collisions = raw->tx_total_col; 2264 2265 pstats->tx_pause_frames = raw->tx_pause; 2266 pstats->rx_pause_frames = raw->rx_pause; 2267 2268 spin_unlock(&mib->stats64_lock); 2269 2270 if (dev->info->phy_errata_9477 && !ksz_is_sgmii_port(dev, port)) { 2271 ret = ksz9477_errata_monitor(dev, port, raw->tx_late_col); 2272 if (ret) 2273 dev_err(dev->dev, "Failed to monitor transmission halt\n"); 2274 } 2275 } 2276 2277 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 2278 { 2279 struct ethtool_pause_stats *pstats; 2280 struct rtnl_link_stats64 *stats; 2281 struct ksz88xx_stats_raw *raw; 2282 struct ksz_port_mib *mib; 2283 2284 mib = &dev->ports[port].mib; 2285 stats = &mib->stats64; 2286 pstats = &mib->pause_stats; 2287 raw = (struct ksz88xx_stats_raw *)mib->counters; 2288 2289 spin_lock(&mib->stats64_lock); 2290 2291 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 2292 raw->rx_pause; 2293 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2294 raw->tx_pause; 2295 2296 /* HW counters are counting bytes + FCS which is not acceptable 2297 * for rtnl_link_stats64 interface 2298 */ 2299 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 2300 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 2301 2302 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2303 raw->rx_oversize; 2304 2305 stats->rx_crc_errors = raw->rx_crc_err; 2306 stats->rx_frame_errors = raw->rx_align_err; 2307 stats->rx_dropped = raw->rx_discards; 2308 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2309 stats->rx_frame_errors + stats->rx_dropped; 2310 2311 stats->tx_window_errors = raw->tx_late_col; 2312 stats->tx_fifo_errors = raw->tx_discards; 2313 stats->tx_aborted_errors = raw->tx_exc_col; 2314 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2315 stats->tx_aborted_errors; 2316 2317 stats->multicast = raw->rx_mcast; 2318 stats->collisions = raw->tx_total_col; 2319 2320 pstats->tx_pause_frames = raw->tx_pause; 2321 pstats->rx_pause_frames = raw->rx_pause; 2322 2323 spin_unlock(&mib->stats64_lock); 2324 } 2325 2326 static void ksz_get_stats64(struct dsa_switch *ds, int port, 2327 struct rtnl_link_stats64 *s) 2328 { 2329 struct ksz_device *dev = ds->priv; 2330 struct ksz_port_mib *mib; 2331 2332 mib = &dev->ports[port].mib; 2333 2334 spin_lock(&mib->stats64_lock); 2335 memcpy(s, &mib->stats64, sizeof(*s)); 2336 spin_unlock(&mib->stats64_lock); 2337 } 2338 2339 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 2340 struct ethtool_pause_stats *pause_stats) 2341 { 2342 struct ksz_device *dev = ds->priv; 2343 struct ksz_port_mib *mib; 2344 2345 mib = &dev->ports[port].mib; 2346 2347 spin_lock(&mib->stats64_lock); 2348 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 2349 spin_unlock(&mib->stats64_lock); 2350 } 2351 2352 static void ksz_get_strings(struct dsa_switch *ds, int port, 2353 u32 stringset, uint8_t *buf) 2354 { 2355 struct ksz_device *dev = ds->priv; 2356 int i; 2357 2358 if (stringset != ETH_SS_STATS) 2359 return; 2360 2361 for (i = 0; i < dev->info->mib_cnt; i++) 2362 ethtool_puts(&buf, dev->info->mib_names[i].string); 2363 } 2364 2365 /** 2366 * ksz_update_port_member - Adjust port forwarding rules based on STP state and 2367 * isolation settings. 2368 * @dev: A pointer to the struct ksz_device representing the device. 2369 * @port: The port number to adjust. 2370 * 2371 * This function dynamically adjusts the port membership configuration for a 2372 * specified port and other device ports, based on Spanning Tree Protocol (STP) 2373 * states and port isolation settings. Each port, including the CPU port, has a 2374 * membership register, represented as a bitfield, where each bit corresponds 2375 * to a port number. A set bit indicates permission to forward frames to that 2376 * port. This function iterates over all ports, updating the membership register 2377 * to reflect current forwarding permissions: 2378 * 2379 * 1. Forwards frames only to ports that are part of the same bridge group and 2380 * in the BR_STATE_FORWARDING state. 2381 * 2. Takes into account the isolation status of ports; ports in the 2382 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward 2383 * frames to each other, even if they are in the same bridge group. 2384 * 3. Ensures that the CPU port is included in the membership based on its 2385 * upstream port configuration, allowing for management and control traffic 2386 * to flow as required. 2387 */ 2388 static void ksz_update_port_member(struct ksz_device *dev, int port) 2389 { 2390 struct ksz_port *p = &dev->ports[port]; 2391 struct dsa_switch *ds = dev->ds; 2392 u8 port_member = 0, cpu_port; 2393 const struct dsa_port *dp; 2394 int i, j; 2395 2396 if (!dsa_is_user_port(ds, port)) 2397 return; 2398 2399 dp = dsa_to_port(ds, port); 2400 cpu_port = BIT(dsa_upstream_port(ds, port)); 2401 2402 for (i = 0; i < ds->num_ports; i++) { 2403 const struct dsa_port *other_dp = dsa_to_port(ds, i); 2404 struct ksz_port *other_p = &dev->ports[i]; 2405 u8 val = 0; 2406 2407 if (!dsa_is_user_port(ds, i)) 2408 continue; 2409 if (port == i) 2410 continue; 2411 if (!dsa_port_bridge_same(dp, other_dp)) 2412 continue; 2413 if (other_p->stp_state != BR_STATE_FORWARDING) 2414 continue; 2415 2416 /* At this point we know that "port" and "other" port [i] are in 2417 * the same bridge group and that "other" port [i] is in 2418 * forwarding stp state. If "port" is also in forwarding stp 2419 * state, we can allow forwarding from port [port] to port [i]. 2420 * Except if both ports are isolated. 2421 */ 2422 if (p->stp_state == BR_STATE_FORWARDING && 2423 !(p->isolated && other_p->isolated)) { 2424 val |= BIT(port); 2425 port_member |= BIT(i); 2426 } 2427 2428 /* Retain port [i]'s relationship to other ports than [port] */ 2429 for (j = 0; j < ds->num_ports; j++) { 2430 const struct dsa_port *third_dp; 2431 struct ksz_port *third_p; 2432 2433 if (j == i) 2434 continue; 2435 if (j == port) 2436 continue; 2437 if (!dsa_is_user_port(ds, j)) 2438 continue; 2439 third_p = &dev->ports[j]; 2440 if (third_p->stp_state != BR_STATE_FORWARDING) 2441 continue; 2442 2443 third_dp = dsa_to_port(ds, j); 2444 2445 /* Now we updating relation of the "other" port [i] to 2446 * the "third" port [j]. We already know that "other" 2447 * port [i] is in forwarding stp state and that "third" 2448 * port [j] is in forwarding stp state too. 2449 * We need to check if "other" port [i] and "third" port 2450 * [j] are in the same bridge group and not isolated 2451 * before allowing forwarding from port [i] to port [j]. 2452 */ 2453 if (dsa_port_bridge_same(other_dp, third_dp) && 2454 !(other_p->isolated && third_p->isolated)) 2455 val |= BIT(j); 2456 } 2457 2458 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 2459 } 2460 2461 /* HSR ports are setup once so need to use the assigned membership 2462 * when the port is enabled. 2463 */ 2464 if (!port_member && p->stp_state == BR_STATE_FORWARDING && 2465 (dev->hsr_ports & BIT(port))) 2466 port_member = dev->hsr_ports; 2467 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 2468 } 2469 2470 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 2471 { 2472 struct ksz_device *dev = bus->priv; 2473 u16 val; 2474 int ret; 2475 2476 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 2477 if (ret < 0) 2478 return ret; 2479 2480 return val; 2481 } 2482 2483 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 2484 u16 val) 2485 { 2486 struct ksz_device *dev = bus->priv; 2487 2488 return dev->dev_ops->w_phy(dev, addr, regnum, val); 2489 } 2490 2491 /** 2492 * ksz_parent_mdio_read - Read data from a PHY register on the parent MDIO bus. 2493 * @bus: MDIO bus structure. 2494 * @addr: PHY address on the parent MDIO bus. 2495 * @regnum: Register number to read. 2496 * 2497 * This function provides a direct read operation on the parent MDIO bus for 2498 * accessing PHY registers. By bypassing SPI or I2C, it uses the parent MDIO bus 2499 * to retrieve data from the PHY registers at the specified address and register 2500 * number. 2501 * 2502 * Return: Value of the PHY register, or a negative error code on failure. 2503 */ 2504 static int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum) 2505 { 2506 struct ksz_device *dev = bus->priv; 2507 2508 return mdiobus_read_nested(dev->parent_mdio_bus, addr, regnum); 2509 } 2510 2511 /** 2512 * ksz_parent_mdio_write - Write data to a PHY register on the parent MDIO bus. 2513 * @bus: MDIO bus structure. 2514 * @addr: PHY address on the parent MDIO bus. 2515 * @regnum: Register number to write to. 2516 * @val: Value to write to the PHY register. 2517 * 2518 * This function provides a direct write operation on the parent MDIO bus for 2519 * accessing PHY registers. Bypassing SPI or I2C, it uses the parent MDIO bus 2520 * to modify the PHY register values at the specified address. 2521 * 2522 * Return: 0 on success, or a negative error code on failure. 2523 */ 2524 static int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum, 2525 u16 val) 2526 { 2527 struct ksz_device *dev = bus->priv; 2528 2529 return mdiobus_write_nested(dev->parent_mdio_bus, addr, regnum, val); 2530 } 2531 2532 /** 2533 * ksz_phy_addr_to_port - Map a PHY address to the corresponding switch port. 2534 * @dev: Pointer to device structure. 2535 * @addr: PHY address to map to a port. 2536 * 2537 * This function finds the corresponding switch port for a given PHY address by 2538 * iterating over all user ports on the device. It checks if a port's PHY 2539 * address in `phy_addr_map` matches the specified address and if the port 2540 * contains an internal PHY. If a match is found, the index of the port is 2541 * returned. 2542 * 2543 * Return: Port index on success, or -EINVAL if no matching port is found. 2544 */ 2545 static int ksz_phy_addr_to_port(struct ksz_device *dev, int addr) 2546 { 2547 struct dsa_switch *ds = dev->ds; 2548 struct dsa_port *dp; 2549 2550 dsa_switch_for_each_user_port(dp, ds) { 2551 if (dev->info->internal_phy[dp->index] && 2552 dev->phy_addr_map[dp->index] == addr) 2553 return dp->index; 2554 } 2555 2556 return -EINVAL; 2557 } 2558 2559 /** 2560 * ksz_irq_phy_setup - Configure IRQs for PHYs in the KSZ device. 2561 * @dev: Pointer to the KSZ device structure. 2562 * 2563 * Sets up IRQs for each active PHY connected to the KSZ switch by mapping the 2564 * appropriate IRQs for each PHY and assigning them to the `user_mii_bus` in 2565 * the DSA switch structure. Each IRQ is mapped based on the port's IRQ domain. 2566 * 2567 * Return: 0 on success, or a negative error code on failure. 2568 */ 2569 static int ksz_irq_phy_setup(struct ksz_device *dev) 2570 { 2571 struct dsa_switch *ds = dev->ds; 2572 int phy, port; 2573 int irq; 2574 int ret; 2575 2576 for (phy = 0; phy < PHY_MAX_ADDR; phy++) { 2577 if (BIT(phy) & ds->phys_mii_mask) { 2578 port = ksz_phy_addr_to_port(dev, phy); 2579 if (port < 0) { 2580 ret = port; 2581 goto out; 2582 } 2583 2584 irq = irq_find_mapping(dev->ports[port].pirq.domain, 2585 PORT_SRC_PHY_INT); 2586 if (irq < 0) { 2587 ret = irq; 2588 goto out; 2589 } 2590 ds->user_mii_bus->irq[phy] = irq; 2591 } 2592 } 2593 return 0; 2594 out: 2595 while (phy--) 2596 if (BIT(phy) & ds->phys_mii_mask) 2597 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2598 2599 return ret; 2600 } 2601 2602 /** 2603 * ksz_irq_phy_free - Release IRQ mappings for PHYs in the KSZ device. 2604 * @dev: Pointer to the KSZ device structure. 2605 * 2606 * Releases any IRQ mappings previously assigned to active PHYs in the KSZ 2607 * switch by disposing of each mapped IRQ in the `user_mii_bus` structure. 2608 */ 2609 static void ksz_irq_phy_free(struct ksz_device *dev) 2610 { 2611 struct dsa_switch *ds = dev->ds; 2612 int phy; 2613 2614 for (phy = 0; phy < PHY_MAX_ADDR; phy++) 2615 if (BIT(phy) & ds->phys_mii_mask) 2616 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2617 } 2618 2619 /** 2620 * ksz_parse_dt_phy_config - Parse and validate PHY configuration from DT 2621 * @dev: pointer to the KSZ device structure 2622 * @bus: pointer to the MII bus structure 2623 * @mdio_np: pointer to the MDIO node in the device tree 2624 * 2625 * This function parses and validates PHY configurations for each user port 2626 * defined in the device tree for a KSZ switch device. It verifies that the 2627 * `phy-handle` properties are correctly set and that the internal PHYs match 2628 * expected addresses and parent nodes. Sets up the PHY mask in the MII bus if 2629 * all validations pass. Logs error messages for any mismatches or missing data. 2630 * 2631 * Return: 0 on success, or a negative error code on failure. 2632 */ 2633 static int ksz_parse_dt_phy_config(struct ksz_device *dev, struct mii_bus *bus, 2634 struct device_node *mdio_np) 2635 { 2636 struct device_node *phy_node, *phy_parent_node; 2637 bool phys_are_valid = true; 2638 struct dsa_port *dp; 2639 u32 phy_addr; 2640 int ret; 2641 2642 dsa_switch_for_each_user_port(dp, dev->ds) { 2643 if (!dev->info->internal_phy[dp->index]) 2644 continue; 2645 2646 phy_node = of_parse_phandle(dp->dn, "phy-handle", 0); 2647 if (!phy_node) { 2648 dev_err(dev->dev, "failed to parse phy-handle for port %d.\n", 2649 dp->index); 2650 phys_are_valid = false; 2651 continue; 2652 } 2653 2654 phy_parent_node = of_get_parent(phy_node); 2655 if (!phy_parent_node) { 2656 dev_err(dev->dev, "failed to get PHY-parent node for port %d\n", 2657 dp->index); 2658 phys_are_valid = false; 2659 } else if (phy_parent_node != mdio_np) { 2660 dev_err(dev->dev, "PHY-parent node mismatch for port %d, expected %pOF, got %pOF\n", 2661 dp->index, mdio_np, phy_parent_node); 2662 phys_are_valid = false; 2663 } else { 2664 ret = of_property_read_u32(phy_node, "reg", &phy_addr); 2665 if (ret < 0) { 2666 dev_err(dev->dev, "failed to read PHY address for port %d. Error %d\n", 2667 dp->index, ret); 2668 phys_are_valid = false; 2669 } else if (phy_addr != dev->phy_addr_map[dp->index]) { 2670 dev_err(dev->dev, "PHY address mismatch for port %d, expected 0x%x, got 0x%x\n", 2671 dp->index, dev->phy_addr_map[dp->index], 2672 phy_addr); 2673 phys_are_valid = false; 2674 } else { 2675 bus->phy_mask |= BIT(phy_addr); 2676 } 2677 } 2678 2679 of_node_put(phy_node); 2680 of_node_put(phy_parent_node); 2681 } 2682 2683 if (!phys_are_valid) 2684 return -EINVAL; 2685 2686 return 0; 2687 } 2688 2689 /** 2690 * ksz_mdio_register - Register and configure the MDIO bus for the KSZ device. 2691 * @dev: Pointer to the KSZ device structure. 2692 * 2693 * This function sets up and registers an MDIO bus for the KSZ switch device, 2694 * allowing access to its internal PHYs. If the device supports side MDIO, 2695 * the function will configure the external MDIO controller specified by the 2696 * "mdio-parent-bus" device tree property to directly manage internal PHYs. 2697 * Otherwise, SPI or I2C access is set up for PHY access. 2698 * 2699 * Return: 0 on success, or a negative error code on failure. 2700 */ 2701 static int ksz_mdio_register(struct ksz_device *dev) 2702 { 2703 struct device_node *parent_bus_node; 2704 struct mii_bus *parent_bus = NULL; 2705 struct dsa_switch *ds = dev->ds; 2706 struct device_node *mdio_np; 2707 struct mii_bus *bus; 2708 int ret, i; 2709 2710 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 2711 if (!mdio_np) 2712 return 0; 2713 2714 parent_bus_node = of_parse_phandle(mdio_np, "mdio-parent-bus", 0); 2715 if (parent_bus_node && !dev->info->phy_side_mdio_supported) { 2716 dev_err(dev->dev, "Side MDIO bus is not supported for this HW, ignoring 'mdio-parent-bus' property.\n"); 2717 ret = -EINVAL; 2718 2719 goto put_mdio_node; 2720 } else if (parent_bus_node) { 2721 parent_bus = of_mdio_find_bus(parent_bus_node); 2722 if (!parent_bus) { 2723 ret = -EPROBE_DEFER; 2724 2725 goto put_mdio_node; 2726 } 2727 2728 dev->parent_mdio_bus = parent_bus; 2729 } 2730 2731 bus = devm_mdiobus_alloc(ds->dev); 2732 if (!bus) { 2733 ret = -ENOMEM; 2734 goto put_mdio_node; 2735 } 2736 2737 if (dev->dev_ops->mdio_bus_preinit) { 2738 ret = dev->dev_ops->mdio_bus_preinit(dev, !!parent_bus); 2739 if (ret) 2740 goto put_mdio_node; 2741 } 2742 2743 if (dev->dev_ops->create_phy_addr_map) { 2744 ret = dev->dev_ops->create_phy_addr_map(dev, !!parent_bus); 2745 if (ret) 2746 goto put_mdio_node; 2747 } else { 2748 for (i = 0; i < dev->info->port_cnt; i++) 2749 dev->phy_addr_map[i] = i; 2750 } 2751 2752 bus->priv = dev; 2753 if (parent_bus) { 2754 bus->read = ksz_parent_mdio_read; 2755 bus->write = ksz_parent_mdio_write; 2756 bus->name = "KSZ side MDIO"; 2757 snprintf(bus->id, MII_BUS_ID_SIZE, "ksz-side-mdio-%d", 2758 ds->index); 2759 } else { 2760 bus->read = ksz_sw_mdio_read; 2761 bus->write = ksz_sw_mdio_write; 2762 bus->name = "ksz user smi"; 2763 if (ds->dst->index != 0) { 2764 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d-%d", ds->dst->index, ds->index); 2765 } else { 2766 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 2767 } 2768 } 2769 2770 ret = ksz_parse_dt_phy_config(dev, bus, mdio_np); 2771 if (ret) 2772 goto put_mdio_node; 2773 2774 ds->phys_mii_mask = bus->phy_mask; 2775 bus->parent = ds->dev; 2776 2777 ds->user_mii_bus = bus; 2778 2779 if (dev->irq > 0) { 2780 ret = ksz_irq_phy_setup(dev); 2781 if (ret) 2782 goto put_mdio_node; 2783 } 2784 2785 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 2786 if (ret) { 2787 dev_err(ds->dev, "unable to register MDIO bus %s\n", 2788 bus->id); 2789 if (dev->irq > 0) 2790 ksz_irq_phy_free(dev); 2791 } 2792 2793 put_mdio_node: 2794 of_node_put(mdio_np); 2795 of_node_put(parent_bus_node); 2796 2797 return ret; 2798 } 2799 2800 static void ksz_irq_mask(struct irq_data *d) 2801 { 2802 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2803 2804 kirq->masked |= BIT(d->hwirq); 2805 } 2806 2807 static void ksz_irq_unmask(struct irq_data *d) 2808 { 2809 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2810 2811 kirq->masked &= ~BIT(d->hwirq); 2812 } 2813 2814 static void ksz_irq_bus_lock(struct irq_data *d) 2815 { 2816 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2817 2818 mutex_lock(&kirq->dev->lock_irq); 2819 } 2820 2821 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 2822 { 2823 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2824 struct ksz_device *dev = kirq->dev; 2825 int ret; 2826 2827 ret = ksz_write8(dev, kirq->reg_mask, kirq->masked); 2828 if (ret) 2829 dev_err(dev->dev, "failed to change IRQ mask\n"); 2830 2831 mutex_unlock(&dev->lock_irq); 2832 } 2833 2834 static const struct irq_chip ksz_irq_chip = { 2835 .name = "ksz-irq", 2836 .irq_mask = ksz_irq_mask, 2837 .irq_unmask = ksz_irq_unmask, 2838 .irq_bus_lock = ksz_irq_bus_lock, 2839 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 2840 }; 2841 2842 static int ksz_irq_domain_map(struct irq_domain *d, 2843 unsigned int irq, irq_hw_number_t hwirq) 2844 { 2845 irq_set_chip_data(irq, d->host_data); 2846 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 2847 irq_set_noprobe(irq); 2848 2849 return 0; 2850 } 2851 2852 static const struct irq_domain_ops ksz_irq_domain_ops = { 2853 .map = ksz_irq_domain_map, 2854 .xlate = irq_domain_xlate_twocell, 2855 }; 2856 2857 static void ksz_irq_free(struct ksz_irq *kirq) 2858 { 2859 int irq, virq; 2860 2861 free_irq(kirq->irq_num, kirq); 2862 2863 for (irq = 0; irq < kirq->nirqs; irq++) { 2864 virq = irq_find_mapping(kirq->domain, irq); 2865 irq_dispose_mapping(virq); 2866 } 2867 2868 irq_domain_remove(kirq->domain); 2869 } 2870 2871 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 2872 { 2873 struct ksz_irq *kirq = dev_id; 2874 unsigned int nhandled = 0; 2875 struct ksz_device *dev; 2876 unsigned int sub_irq; 2877 u8 data; 2878 int ret; 2879 u8 n; 2880 2881 dev = kirq->dev; 2882 2883 /* Read interrupt status register */ 2884 ret = ksz_read8(dev, kirq->reg_status, &data); 2885 if (ret) 2886 goto out; 2887 2888 for (n = 0; n < kirq->nirqs; ++n) { 2889 if (data & BIT(n)) { 2890 sub_irq = irq_find_mapping(kirq->domain, n); 2891 handle_nested_irq(sub_irq); 2892 ++nhandled; 2893 } 2894 } 2895 out: 2896 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2897 } 2898 2899 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 2900 { 2901 int ret, n; 2902 2903 kirq->dev = dev; 2904 kirq->masked = ~0; 2905 2906 kirq->domain = irq_domain_create_simple(dev_fwnode(dev->dev), kirq->nirqs, 0, 2907 &ksz_irq_domain_ops, kirq); 2908 if (!kirq->domain) 2909 return -ENOMEM; 2910 2911 for (n = 0; n < kirq->nirqs; n++) 2912 irq_create_mapping(kirq->domain, n); 2913 2914 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2915 IRQF_ONESHOT, kirq->name, kirq); 2916 if (ret) 2917 goto out; 2918 2919 return 0; 2920 2921 out: 2922 ksz_irq_free(kirq); 2923 2924 return ret; 2925 } 2926 2927 static int ksz_girq_setup(struct ksz_device *dev) 2928 { 2929 struct ksz_irq *girq = &dev->girq; 2930 2931 girq->nirqs = dev->info->port_cnt; 2932 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2933 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2934 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2935 2936 girq->irq_num = dev->irq; 2937 2938 return ksz_irq_common_setup(dev, girq); 2939 } 2940 2941 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2942 { 2943 struct ksz_irq *pirq = &dev->ports[p].pirq; 2944 2945 pirq->nirqs = dev->info->port_nirqs; 2946 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2947 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2948 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2949 2950 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2951 if (pirq->irq_num < 0) 2952 return pirq->irq_num; 2953 2954 return ksz_irq_common_setup(dev, pirq); 2955 } 2956 2957 static int ksz_parse_drive_strength(struct ksz_device *dev); 2958 2959 static int ksz_setup(struct dsa_switch *ds) 2960 { 2961 struct ksz_device *dev = ds->priv; 2962 u16 storm_mask, storm_rate; 2963 struct dsa_port *dp; 2964 struct ksz_port *p; 2965 const u16 *regs; 2966 int ret; 2967 2968 regs = dev->info->regs; 2969 2970 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2971 dev->info->num_vlans, GFP_KERNEL); 2972 if (!dev->vlan_cache) 2973 return -ENOMEM; 2974 2975 ret = dev->dev_ops->reset(dev); 2976 if (ret) { 2977 dev_err(ds->dev, "failed to reset switch\n"); 2978 return ret; 2979 } 2980 2981 ret = ksz_parse_drive_strength(dev); 2982 if (ret) 2983 return ret; 2984 2985 if (ksz_has_sgmii_port(dev) && dev->dev_ops->pcs_create) { 2986 ret = dev->dev_ops->pcs_create(dev); 2987 if (ret) 2988 return ret; 2989 } 2990 2991 /* set broadcast storm protection 10% rate */ 2992 storm_mask = BROADCAST_STORM_RATE; 2993 storm_rate = (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100; 2994 if (ksz_is_ksz8463(dev)) { 2995 storm_mask = swab16(storm_mask); 2996 storm_rate = swab16(storm_rate); 2997 } 2998 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2999 storm_mask, storm_rate); 3000 3001 dev->dev_ops->config_cpu_port(ds); 3002 3003 dev->dev_ops->enable_stp_addr(dev); 3004 3005 ds->num_tx_queues = dev->info->num_tx_queues; 3006 3007 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 3008 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 3009 3010 ksz_init_mib_timer(dev); 3011 3012 ds->configure_vlan_while_not_filtering = false; 3013 ds->dscp_prio_mapping_is_global = true; 3014 3015 if (dev->dev_ops->setup) { 3016 ret = dev->dev_ops->setup(ds); 3017 if (ret) 3018 return ret; 3019 } 3020 3021 /* Start with learning disabled on standalone user ports, and enabled 3022 * on the CPU port. In lack of other finer mechanisms, learning on the 3023 * CPU port will avoid flooding bridge local addresses on the network 3024 * in some cases. 3025 */ 3026 p = &dev->ports[dev->cpu_port]; 3027 p->learning = true; 3028 3029 if (dev->irq > 0) { 3030 ret = ksz_girq_setup(dev); 3031 if (ret) 3032 return ret; 3033 3034 dsa_switch_for_each_user_port(dp, dev->ds) { 3035 ret = ksz_pirq_setup(dev, dp->index); 3036 if (ret) 3037 goto out_girq; 3038 3039 if (dev->info->ptp_capable) { 3040 ret = ksz_ptp_irq_setup(ds, dp->index); 3041 if (ret) 3042 goto out_pirq; 3043 } 3044 } 3045 } 3046 3047 if (dev->info->ptp_capable) { 3048 ret = ksz_ptp_clock_register(ds); 3049 if (ret) { 3050 dev_err(dev->dev, "Failed to register PTP clock: %d\n", 3051 ret); 3052 goto out_ptpirq; 3053 } 3054 } 3055 3056 ret = ksz_mdio_register(dev); 3057 if (ret < 0) { 3058 dev_err(dev->dev, "failed to register the mdio"); 3059 goto out_ptp_clock_unregister; 3060 } 3061 3062 ret = ksz_dcb_init(dev); 3063 if (ret) 3064 goto out_ptp_clock_unregister; 3065 3066 /* start switch */ 3067 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 3068 SW_START, SW_START); 3069 3070 return 0; 3071 3072 out_ptp_clock_unregister: 3073 if (dev->info->ptp_capable) 3074 ksz_ptp_clock_unregister(ds); 3075 out_ptpirq: 3076 if (dev->irq > 0 && dev->info->ptp_capable) 3077 dsa_switch_for_each_user_port(dp, dev->ds) 3078 ksz_ptp_irq_free(ds, dp->index); 3079 out_pirq: 3080 if (dev->irq > 0) 3081 dsa_switch_for_each_user_port(dp, dev->ds) 3082 ksz_irq_free(&dev->ports[dp->index].pirq); 3083 out_girq: 3084 if (dev->irq > 0) 3085 ksz_irq_free(&dev->girq); 3086 3087 return ret; 3088 } 3089 3090 static void ksz_teardown(struct dsa_switch *ds) 3091 { 3092 struct ksz_device *dev = ds->priv; 3093 struct dsa_port *dp; 3094 3095 if (dev->info->ptp_capable) 3096 ksz_ptp_clock_unregister(ds); 3097 3098 if (dev->irq > 0) { 3099 dsa_switch_for_each_user_port(dp, dev->ds) { 3100 if (dev->info->ptp_capable) 3101 ksz_ptp_irq_free(ds, dp->index); 3102 3103 ksz_irq_free(&dev->ports[dp->index].pirq); 3104 } 3105 3106 ksz_irq_free(&dev->girq); 3107 } 3108 3109 if (dev->dev_ops->teardown) 3110 dev->dev_ops->teardown(ds); 3111 } 3112 3113 static void port_r_cnt(struct ksz_device *dev, int port) 3114 { 3115 struct ksz_port_mib *mib = &dev->ports[port].mib; 3116 u64 *dropped; 3117 3118 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 3119 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 3120 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 3121 &mib->counters[mib->cnt_ptr]); 3122 ++mib->cnt_ptr; 3123 } 3124 3125 /* last one in storage */ 3126 dropped = &mib->counters[dev->info->mib_cnt]; 3127 3128 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 3129 while (mib->cnt_ptr < dev->info->mib_cnt) { 3130 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 3131 dropped, &mib->counters[mib->cnt_ptr]); 3132 ++mib->cnt_ptr; 3133 } 3134 mib->cnt_ptr = 0; 3135 } 3136 3137 static void ksz_mib_read_work(struct work_struct *work) 3138 { 3139 struct ksz_device *dev = container_of(work, struct ksz_device, 3140 mib_read.work); 3141 struct ksz_port_mib *mib; 3142 struct ksz_port *p; 3143 int i; 3144 3145 for (i = 0; i < dev->info->port_cnt; i++) { 3146 if (dsa_is_unused_port(dev->ds, i)) 3147 continue; 3148 3149 p = &dev->ports[i]; 3150 mib = &p->mib; 3151 mutex_lock(&mib->cnt_mutex); 3152 3153 /* Only read MIB counters when the port is told to do. 3154 * If not, read only dropped counters when link is not up. 3155 */ 3156 if (!p->read) { 3157 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 3158 3159 if (!netif_carrier_ok(dp->user)) 3160 mib->cnt_ptr = dev->info->reg_mib_cnt; 3161 } 3162 port_r_cnt(dev, i); 3163 p->read = false; 3164 3165 if (dev->dev_ops->r_mib_stat64) 3166 dev->dev_ops->r_mib_stat64(dev, i); 3167 3168 mutex_unlock(&mib->cnt_mutex); 3169 } 3170 3171 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 3172 } 3173 3174 void ksz_init_mib_timer(struct ksz_device *dev) 3175 { 3176 int i; 3177 3178 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 3179 3180 for (i = 0; i < dev->info->port_cnt; i++) { 3181 struct ksz_port_mib *mib = &dev->ports[i].mib; 3182 3183 dev->dev_ops->port_init_cnt(dev, i); 3184 3185 mib->cnt_ptr = 0; 3186 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 3187 } 3188 } 3189 3190 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 3191 { 3192 struct ksz_device *dev = ds->priv; 3193 u16 val = 0xffff; 3194 int ret; 3195 3196 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 3197 if (ret) 3198 return ret; 3199 3200 return val; 3201 } 3202 3203 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 3204 { 3205 struct ksz_device *dev = ds->priv; 3206 int ret; 3207 3208 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 3209 if (ret) 3210 return ret; 3211 3212 return 0; 3213 } 3214 3215 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 3216 { 3217 struct ksz_device *dev = ds->priv; 3218 3219 switch (dev->chip_id) { 3220 case KSZ88X3_CHIP_ID: 3221 /* Silicon Errata Sheet (DS80000830A): 3222 * Port 1 does not work with LinkMD Cable-Testing. 3223 * Port 1 does not respond to received PAUSE control frames. 3224 */ 3225 if (!port) 3226 return MICREL_KSZ8_P1_ERRATA; 3227 break; 3228 } 3229 3230 return 0; 3231 } 3232 3233 static void ksz_phylink_mac_link_down(struct phylink_config *config, 3234 unsigned int mode, 3235 phy_interface_t interface) 3236 { 3237 struct dsa_port *dp = dsa_phylink_to_port(config); 3238 struct ksz_device *dev = dp->ds->priv; 3239 3240 /* Read all MIB counters when the link is going down. */ 3241 dev->ports[dp->index].read = true; 3242 /* timer started */ 3243 if (dev->mib_read_interval) 3244 schedule_delayed_work(&dev->mib_read, 0); 3245 } 3246 3247 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 3248 { 3249 struct ksz_device *dev = ds->priv; 3250 3251 if (sset != ETH_SS_STATS) 3252 return 0; 3253 3254 return dev->info->mib_cnt; 3255 } 3256 3257 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 3258 uint64_t *buf) 3259 { 3260 const struct dsa_port *dp = dsa_to_port(ds, port); 3261 struct ksz_device *dev = ds->priv; 3262 struct ksz_port_mib *mib; 3263 3264 mib = &dev->ports[port].mib; 3265 mutex_lock(&mib->cnt_mutex); 3266 3267 /* Only read dropped counters if no link. */ 3268 if (!netif_carrier_ok(dp->user)) 3269 mib->cnt_ptr = dev->info->reg_mib_cnt; 3270 port_r_cnt(dev, port); 3271 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 3272 mutex_unlock(&mib->cnt_mutex); 3273 } 3274 3275 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 3276 struct dsa_bridge bridge, 3277 bool *tx_fwd_offload, 3278 struct netlink_ext_ack *extack) 3279 { 3280 /* port_stp_state_set() will be called after to put the port in 3281 * appropriate state so there is no need to do anything. 3282 */ 3283 3284 return 0; 3285 } 3286 3287 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 3288 struct dsa_bridge bridge) 3289 { 3290 /* port_stp_state_set() will be called after to put the port in 3291 * forwarding state so there is no need to do anything. 3292 */ 3293 } 3294 3295 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 3296 { 3297 struct ksz_device *dev = ds->priv; 3298 3299 dev->dev_ops->flush_dyn_mac_table(dev, port); 3300 } 3301 3302 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 3303 { 3304 struct ksz_device *dev = ds->priv; 3305 3306 if (!dev->dev_ops->set_ageing_time) 3307 return -EOPNOTSUPP; 3308 3309 return dev->dev_ops->set_ageing_time(dev, msecs); 3310 } 3311 3312 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 3313 const unsigned char *addr, u16 vid, 3314 struct dsa_db db) 3315 { 3316 struct ksz_device *dev = ds->priv; 3317 3318 if (!dev->dev_ops->fdb_add) 3319 return -EOPNOTSUPP; 3320 3321 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 3322 } 3323 3324 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 3325 const unsigned char *addr, 3326 u16 vid, struct dsa_db db) 3327 { 3328 struct ksz_device *dev = ds->priv; 3329 3330 if (!dev->dev_ops->fdb_del) 3331 return -EOPNOTSUPP; 3332 3333 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 3334 } 3335 3336 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 3337 dsa_fdb_dump_cb_t *cb, void *data) 3338 { 3339 struct ksz_device *dev = ds->priv; 3340 3341 if (!dev->dev_ops->fdb_dump) 3342 return -EOPNOTSUPP; 3343 3344 return dev->dev_ops->fdb_dump(dev, port, cb, data); 3345 } 3346 3347 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 3348 const struct switchdev_obj_port_mdb *mdb, 3349 struct dsa_db db) 3350 { 3351 struct ksz_device *dev = ds->priv; 3352 3353 if (!dev->dev_ops->mdb_add) 3354 return -EOPNOTSUPP; 3355 3356 return dev->dev_ops->mdb_add(dev, port, mdb, db); 3357 } 3358 3359 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 3360 const struct switchdev_obj_port_mdb *mdb, 3361 struct dsa_db db) 3362 { 3363 struct ksz_device *dev = ds->priv; 3364 3365 if (!dev->dev_ops->mdb_del) 3366 return -EOPNOTSUPP; 3367 3368 return dev->dev_ops->mdb_del(dev, port, mdb, db); 3369 } 3370 3371 static int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev, 3372 int port) 3373 { 3374 u32 queue_map = 0; 3375 int ipm; 3376 3377 for (ipm = 0; ipm < dev->info->num_ipms; ipm++) { 3378 int queue; 3379 3380 /* Traffic Type (TT) is corresponding to the Internal Priority 3381 * Map (IPM) in the switch. Traffic Class (TC) is 3382 * corresponding to the queue in the switch. 3383 */ 3384 queue = ieee8021q_tt_to_tc(ipm, dev->info->num_tx_queues); 3385 if (queue < 0) 3386 return queue; 3387 3388 queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S); 3389 } 3390 3391 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3392 } 3393 3394 static int ksz_port_setup(struct dsa_switch *ds, int port) 3395 { 3396 struct ksz_device *dev = ds->priv; 3397 int ret; 3398 3399 if (!dsa_is_user_port(ds, port)) 3400 return 0; 3401 3402 /* setup user port */ 3403 dev->dev_ops->port_setup(dev, port, false); 3404 3405 if (!is_ksz8(dev)) { 3406 ret = ksz9477_set_default_prio_queue_mapping(dev, port); 3407 if (ret) 3408 return ret; 3409 } 3410 3411 /* port_stp_state_set() will be called after to enable the port so 3412 * there is no need to do anything. 3413 */ 3414 3415 return ksz_dcb_init_port(dev, port); 3416 } 3417 3418 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 3419 { 3420 struct ksz_device *dev = ds->priv; 3421 struct ksz_port *p; 3422 const u16 *regs; 3423 u8 data; 3424 3425 regs = dev->info->regs; 3426 3427 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 3428 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 3429 3430 p = &dev->ports[port]; 3431 3432 switch (state) { 3433 case BR_STATE_DISABLED: 3434 data |= PORT_LEARN_DISABLE; 3435 break; 3436 case BR_STATE_LISTENING: 3437 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 3438 break; 3439 case BR_STATE_LEARNING: 3440 data |= PORT_RX_ENABLE; 3441 if (!p->learning) 3442 data |= PORT_LEARN_DISABLE; 3443 break; 3444 case BR_STATE_FORWARDING: 3445 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 3446 if (!p->learning) 3447 data |= PORT_LEARN_DISABLE; 3448 break; 3449 case BR_STATE_BLOCKING: 3450 data |= PORT_LEARN_DISABLE; 3451 break; 3452 default: 3453 dev_err(ds->dev, "invalid STP state: %d\n", state); 3454 return; 3455 } 3456 3457 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 3458 3459 p->stp_state = state; 3460 3461 ksz_update_port_member(dev, port); 3462 } 3463 3464 static void ksz_port_teardown(struct dsa_switch *ds, int port) 3465 { 3466 struct ksz_device *dev = ds->priv; 3467 3468 switch (dev->chip_id) { 3469 case KSZ8563_CHIP_ID: 3470 case KSZ8567_CHIP_ID: 3471 case KSZ9477_CHIP_ID: 3472 case KSZ9563_CHIP_ID: 3473 case KSZ9567_CHIP_ID: 3474 case KSZ9893_CHIP_ID: 3475 case KSZ9896_CHIP_ID: 3476 case KSZ9897_CHIP_ID: 3477 case LAN9646_CHIP_ID: 3478 if (dsa_is_user_port(ds, port)) 3479 ksz9477_port_acl_free(dev, port); 3480 } 3481 } 3482 3483 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 3484 struct switchdev_brport_flags flags, 3485 struct netlink_ext_ack *extack) 3486 { 3487 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED)) 3488 return -EINVAL; 3489 3490 return 0; 3491 } 3492 3493 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 3494 struct switchdev_brport_flags flags, 3495 struct netlink_ext_ack *extack) 3496 { 3497 struct ksz_device *dev = ds->priv; 3498 struct ksz_port *p = &dev->ports[port]; 3499 3500 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) { 3501 if (flags.mask & BR_LEARNING) 3502 p->learning = !!(flags.val & BR_LEARNING); 3503 3504 if (flags.mask & BR_ISOLATED) 3505 p->isolated = !!(flags.val & BR_ISOLATED); 3506 3507 /* Make the change take effect immediately */ 3508 ksz_port_stp_state_set(ds, port, p->stp_state); 3509 } 3510 3511 return 0; 3512 } 3513 3514 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 3515 int port, 3516 enum dsa_tag_protocol mp) 3517 { 3518 struct ksz_device *dev = ds->priv; 3519 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 3520 3521 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev)) 3522 proto = DSA_TAG_PROTO_KSZ8795; 3523 3524 if (dev->chip_id == KSZ88X3_CHIP_ID || 3525 dev->chip_id == KSZ8463_CHIP_ID || 3526 dev->chip_id == KSZ8563_CHIP_ID || 3527 dev->chip_id == KSZ9893_CHIP_ID || 3528 dev->chip_id == KSZ9563_CHIP_ID) 3529 proto = DSA_TAG_PROTO_KSZ9893; 3530 3531 if (dev->chip_id == KSZ8567_CHIP_ID || 3532 dev->chip_id == KSZ9477_CHIP_ID || 3533 dev->chip_id == KSZ9896_CHIP_ID || 3534 dev->chip_id == KSZ9897_CHIP_ID || 3535 dev->chip_id == KSZ9567_CHIP_ID || 3536 dev->chip_id == LAN9646_CHIP_ID) 3537 proto = DSA_TAG_PROTO_KSZ9477; 3538 3539 if (is_lan937x(dev)) 3540 proto = DSA_TAG_PROTO_LAN937X; 3541 3542 return proto; 3543 } 3544 3545 static int ksz_connect_tag_protocol(struct dsa_switch *ds, 3546 enum dsa_tag_protocol proto) 3547 { 3548 struct ksz_tagger_data *tagger_data; 3549 3550 switch (proto) { 3551 case DSA_TAG_PROTO_KSZ8795: 3552 return 0; 3553 case DSA_TAG_PROTO_KSZ9893: 3554 case DSA_TAG_PROTO_KSZ9477: 3555 case DSA_TAG_PROTO_LAN937X: 3556 tagger_data = ksz_tagger_data(ds); 3557 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 3558 return 0; 3559 default: 3560 return -EPROTONOSUPPORT; 3561 } 3562 } 3563 3564 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 3565 bool flag, struct netlink_ext_ack *extack) 3566 { 3567 struct ksz_device *dev = ds->priv; 3568 3569 if (!dev->dev_ops->vlan_filtering) 3570 return -EOPNOTSUPP; 3571 3572 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 3573 } 3574 3575 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 3576 const struct switchdev_obj_port_vlan *vlan, 3577 struct netlink_ext_ack *extack) 3578 { 3579 struct ksz_device *dev = ds->priv; 3580 3581 if (!dev->dev_ops->vlan_add) 3582 return -EOPNOTSUPP; 3583 3584 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 3585 } 3586 3587 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 3588 const struct switchdev_obj_port_vlan *vlan) 3589 { 3590 struct ksz_device *dev = ds->priv; 3591 3592 if (!dev->dev_ops->vlan_del) 3593 return -EOPNOTSUPP; 3594 3595 return dev->dev_ops->vlan_del(dev, port, vlan); 3596 } 3597 3598 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 3599 struct dsa_mall_mirror_tc_entry *mirror, 3600 bool ingress, struct netlink_ext_ack *extack) 3601 { 3602 struct ksz_device *dev = ds->priv; 3603 3604 if (!dev->dev_ops->mirror_add) 3605 return -EOPNOTSUPP; 3606 3607 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 3608 } 3609 3610 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 3611 struct dsa_mall_mirror_tc_entry *mirror) 3612 { 3613 struct ksz_device *dev = ds->priv; 3614 3615 if (dev->dev_ops->mirror_del) 3616 dev->dev_ops->mirror_del(dev, port, mirror); 3617 } 3618 3619 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 3620 { 3621 struct ksz_device *dev = ds->priv; 3622 3623 if (!dev->dev_ops->change_mtu) 3624 return -EOPNOTSUPP; 3625 3626 return dev->dev_ops->change_mtu(dev, port, mtu); 3627 } 3628 3629 static int ksz_max_mtu(struct dsa_switch *ds, int port) 3630 { 3631 struct ksz_device *dev = ds->priv; 3632 3633 switch (dev->chip_id) { 3634 case KSZ8795_CHIP_ID: 3635 case KSZ8794_CHIP_ID: 3636 case KSZ8765_CHIP_ID: 3637 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3638 case KSZ8463_CHIP_ID: 3639 case KSZ88X3_CHIP_ID: 3640 case KSZ8864_CHIP_ID: 3641 case KSZ8895_CHIP_ID: 3642 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3643 case KSZ8563_CHIP_ID: 3644 case KSZ8567_CHIP_ID: 3645 case KSZ9477_CHIP_ID: 3646 case KSZ9563_CHIP_ID: 3647 case KSZ9567_CHIP_ID: 3648 case KSZ9893_CHIP_ID: 3649 case KSZ9896_CHIP_ID: 3650 case KSZ9897_CHIP_ID: 3651 case LAN9370_CHIP_ID: 3652 case LAN9371_CHIP_ID: 3653 case LAN9372_CHIP_ID: 3654 case LAN9373_CHIP_ID: 3655 case LAN9374_CHIP_ID: 3656 case LAN9646_CHIP_ID: 3657 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3658 } 3659 3660 return -EOPNOTSUPP; 3661 } 3662 3663 /** 3664 * ksz_support_eee - Determine Energy Efficient Ethernet (EEE) support for a 3665 * port 3666 * @ds: Pointer to the DSA switch structure 3667 * @port: Port number to check 3668 * 3669 * This function also documents devices where EEE was initially advertised but 3670 * later withdrawn due to reliability issues, as described in official errata 3671 * documents. These devices are explicitly listed to record known limitations, 3672 * even if there is no technical necessity for runtime checks. 3673 * 3674 * Returns: true if the internal PHY on the given port supports fully 3675 * operational EEE, false otherwise. 3676 */ 3677 static bool ksz_support_eee(struct dsa_switch *ds, int port) 3678 { 3679 struct ksz_device *dev = ds->priv; 3680 3681 if (!dev->info->internal_phy[port]) 3682 return false; 3683 3684 switch (dev->chip_id) { 3685 case KSZ8563_CHIP_ID: 3686 case KSZ9563_CHIP_ID: 3687 case KSZ9893_CHIP_ID: 3688 return true; 3689 case KSZ8567_CHIP_ID: 3690 /* KSZ8567R Errata DS80000752C Module 4 */ 3691 case KSZ8765_CHIP_ID: 3692 case KSZ8794_CHIP_ID: 3693 case KSZ8795_CHIP_ID: 3694 /* KSZ879x/KSZ877x/KSZ876x Errata DS80000687C Module 2 */ 3695 case KSZ9477_CHIP_ID: 3696 /* KSZ9477S Errata DS80000754A Module 4 */ 3697 case KSZ9567_CHIP_ID: 3698 /* KSZ9567S Errata DS80000756A Module 4 */ 3699 case KSZ9896_CHIP_ID: 3700 /* KSZ9896C Errata DS80000757A Module 3 */ 3701 case KSZ9897_CHIP_ID: 3702 case LAN9646_CHIP_ID: 3703 /* KSZ9897R Errata DS80000758C Module 4 */ 3704 /* Energy Efficient Ethernet (EEE) feature select must be 3705 * manually disabled 3706 * The EEE feature is enabled by default, but it is not fully 3707 * operational. It must be manually disabled through register 3708 * controls. If not disabled, the PHY ports can auto-negotiate 3709 * to enable EEE, and this feature can cause link drops when 3710 * linked to another device supporting EEE. 3711 * 3712 * The same item appears in the errata for all switches above. 3713 */ 3714 break; 3715 } 3716 3717 return false; 3718 } 3719 3720 static int ksz_set_mac_eee(struct dsa_switch *ds, int port, 3721 struct ethtool_keee *e) 3722 { 3723 struct ksz_device *dev = ds->priv; 3724 3725 if (!e->tx_lpi_enabled) { 3726 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 3727 return -EINVAL; 3728 } 3729 3730 if (e->tx_lpi_timer) { 3731 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 3732 return -EINVAL; 3733 } 3734 3735 return 0; 3736 } 3737 3738 static void ksz_set_xmii(struct ksz_device *dev, int port, 3739 phy_interface_t interface) 3740 { 3741 const u8 *bitval = dev->info->xmii_ctrl1; 3742 struct ksz_port *p = &dev->ports[port]; 3743 const u16 *regs = dev->info->regs; 3744 u8 data8; 3745 3746 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3747 3748 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 3749 P_RGMII_ID_EG_ENABLE); 3750 3751 switch (interface) { 3752 case PHY_INTERFACE_MODE_MII: 3753 data8 |= bitval[P_MII_SEL]; 3754 break; 3755 case PHY_INTERFACE_MODE_RMII: 3756 data8 |= bitval[P_RMII_SEL]; 3757 break; 3758 case PHY_INTERFACE_MODE_GMII: 3759 data8 |= bitval[P_GMII_SEL]; 3760 break; 3761 case PHY_INTERFACE_MODE_RGMII: 3762 case PHY_INTERFACE_MODE_RGMII_ID: 3763 case PHY_INTERFACE_MODE_RGMII_TXID: 3764 case PHY_INTERFACE_MODE_RGMII_RXID: 3765 data8 |= bitval[P_RGMII_SEL]; 3766 /* On KSZ9893, disable RGMII in-band status support */ 3767 if (dev->chip_id == KSZ9893_CHIP_ID || 3768 dev->chip_id == KSZ8563_CHIP_ID || 3769 dev->chip_id == KSZ9563_CHIP_ID || 3770 is_lan937x(dev)) 3771 data8 &= ~P_MII_MAC_MODE; 3772 break; 3773 default: 3774 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 3775 phy_modes(interface), port); 3776 return; 3777 } 3778 3779 if (p->rgmii_tx_val) 3780 data8 |= P_RGMII_ID_EG_ENABLE; 3781 3782 if (p->rgmii_rx_val) 3783 data8 |= P_RGMII_ID_IG_ENABLE; 3784 3785 /* Write the updated value */ 3786 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3787 } 3788 3789 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 3790 { 3791 const u8 *bitval = dev->info->xmii_ctrl1; 3792 const u16 *regs = dev->info->regs; 3793 phy_interface_t interface; 3794 u8 data8; 3795 u8 val; 3796 3797 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3798 3799 val = FIELD_GET(P_MII_SEL_M, data8); 3800 3801 if (val == bitval[P_MII_SEL]) { 3802 if (gbit) 3803 interface = PHY_INTERFACE_MODE_GMII; 3804 else 3805 interface = PHY_INTERFACE_MODE_MII; 3806 } else if (val == bitval[P_RMII_SEL]) { 3807 interface = PHY_INTERFACE_MODE_RMII; 3808 } else { 3809 interface = PHY_INTERFACE_MODE_RGMII; 3810 if (data8 & P_RGMII_ID_EG_ENABLE) 3811 interface = PHY_INTERFACE_MODE_RGMII_TXID; 3812 if (data8 & P_RGMII_ID_IG_ENABLE) { 3813 interface = PHY_INTERFACE_MODE_RGMII_RXID; 3814 if (data8 & P_RGMII_ID_EG_ENABLE) 3815 interface = PHY_INTERFACE_MODE_RGMII_ID; 3816 } 3817 } 3818 3819 return interface; 3820 } 3821 3822 static void ksz88x3_phylink_mac_config(struct phylink_config *config, 3823 unsigned int mode, 3824 const struct phylink_link_state *state) 3825 { 3826 struct dsa_port *dp = dsa_phylink_to_port(config); 3827 struct ksz_device *dev = dp->ds->priv; 3828 3829 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN); 3830 } 3831 3832 static void ksz_phylink_mac_config(struct phylink_config *config, 3833 unsigned int mode, 3834 const struct phylink_link_state *state) 3835 { 3836 struct dsa_port *dp = dsa_phylink_to_port(config); 3837 struct ksz_device *dev = dp->ds->priv; 3838 int port = dp->index; 3839 3840 /* Internal PHYs */ 3841 if (dev->info->internal_phy[port]) 3842 return; 3843 3844 /* No need to configure XMII control register when using SGMII. */ 3845 if (ksz_is_sgmii_port(dev, port)) 3846 return; 3847 3848 if (phylink_autoneg_inband(mode)) { 3849 dev_err(dev->dev, "In-band AN not supported!\n"); 3850 return; 3851 } 3852 3853 ksz_set_xmii(dev, port, state->interface); 3854 3855 if (dev->dev_ops->setup_rgmii_delay) 3856 dev->dev_ops->setup_rgmii_delay(dev, port); 3857 } 3858 3859 bool ksz_get_gbit(struct ksz_device *dev, int port) 3860 { 3861 const u8 *bitval = dev->info->xmii_ctrl1; 3862 const u16 *regs = dev->info->regs; 3863 bool gbit = false; 3864 u8 data8; 3865 bool val; 3866 3867 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3868 3869 val = FIELD_GET(P_GMII_1GBIT_M, data8); 3870 3871 if (val == bitval[P_GMII_1GBIT]) 3872 gbit = true; 3873 3874 return gbit; 3875 } 3876 3877 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 3878 { 3879 const u8 *bitval = dev->info->xmii_ctrl1; 3880 const u16 *regs = dev->info->regs; 3881 u8 data8; 3882 3883 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3884 3885 data8 &= ~P_GMII_1GBIT_M; 3886 3887 if (gbit) 3888 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 3889 else 3890 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 3891 3892 /* Write the updated value */ 3893 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3894 } 3895 3896 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 3897 { 3898 const u8 *bitval = dev->info->xmii_ctrl0; 3899 const u16 *regs = dev->info->regs; 3900 u8 data8; 3901 3902 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 3903 3904 data8 &= ~P_MII_100MBIT_M; 3905 3906 if (speed == SPEED_100) 3907 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 3908 else 3909 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 3910 3911 /* Write the updated value */ 3912 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 3913 } 3914 3915 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 3916 { 3917 if (speed == SPEED_1000) 3918 ksz_set_gbit(dev, port, true); 3919 else 3920 ksz_set_gbit(dev, port, false); 3921 3922 if (speed == SPEED_100 || speed == SPEED_10) 3923 ksz_set_100_10mbit(dev, port, speed); 3924 } 3925 3926 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 3927 bool tx_pause, bool rx_pause) 3928 { 3929 const u8 *bitval = dev->info->xmii_ctrl0; 3930 const u32 *masks = dev->info->masks; 3931 const u16 *regs = dev->info->regs; 3932 u8 mask; 3933 u8 val; 3934 3935 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 3936 masks[P_MII_RX_FLOW_CTRL]; 3937 3938 if (duplex == DUPLEX_FULL) 3939 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 3940 else 3941 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 3942 3943 if (tx_pause) 3944 val |= masks[P_MII_TX_FLOW_CTRL]; 3945 3946 if (rx_pause) 3947 val |= masks[P_MII_RX_FLOW_CTRL]; 3948 3949 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 3950 } 3951 3952 static void ksz9477_phylink_mac_link_up(struct phylink_config *config, 3953 struct phy_device *phydev, 3954 unsigned int mode, 3955 phy_interface_t interface, 3956 int speed, int duplex, bool tx_pause, 3957 bool rx_pause) 3958 { 3959 struct dsa_port *dp = dsa_phylink_to_port(config); 3960 struct ksz_device *dev = dp->ds->priv; 3961 int port = dp->index; 3962 struct ksz_port *p; 3963 3964 p = &dev->ports[port]; 3965 3966 /* Internal PHYs */ 3967 if (dev->info->internal_phy[port]) 3968 return; 3969 3970 p->phydev.speed = speed; 3971 3972 ksz_port_set_xmii_speed(dev, port, speed); 3973 3974 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 3975 } 3976 3977 static int ksz_switch_detect(struct ksz_device *dev) 3978 { 3979 u8 id1, id2, id4; 3980 u16 id16; 3981 u32 id32; 3982 int ret; 3983 3984 /* read chip id */ 3985 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 3986 if (ret) 3987 return ret; 3988 3989 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 3990 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 3991 3992 switch (id1) { 3993 case KSZ84_FAMILY_ID: 3994 dev->chip_id = KSZ8463_CHIP_ID; 3995 break; 3996 case KSZ87_FAMILY_ID: 3997 if (id2 == KSZ87_CHIP_ID_95) { 3998 u8 val; 3999 4000 dev->chip_id = KSZ8795_CHIP_ID; 4001 4002 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 4003 if (val & KSZ8_PORT_FIBER_MODE) 4004 dev->chip_id = KSZ8765_CHIP_ID; 4005 } else if (id2 == KSZ87_CHIP_ID_94) { 4006 dev->chip_id = KSZ8794_CHIP_ID; 4007 } else { 4008 return -ENODEV; 4009 } 4010 break; 4011 case KSZ88_FAMILY_ID: 4012 if (id2 == KSZ88_CHIP_ID_63) 4013 dev->chip_id = KSZ88X3_CHIP_ID; 4014 else 4015 return -ENODEV; 4016 break; 4017 case KSZ8895_FAMILY_ID: 4018 if (id2 == KSZ8895_CHIP_ID_95 || 4019 id2 == KSZ8895_CHIP_ID_95R) 4020 dev->chip_id = KSZ8895_CHIP_ID; 4021 else 4022 return -ENODEV; 4023 ret = ksz_read8(dev, REG_KSZ8864_CHIP_ID, &id4); 4024 if (ret) 4025 return ret; 4026 if (id4 & SW_KSZ8864) 4027 dev->chip_id = KSZ8864_CHIP_ID; 4028 break; 4029 default: 4030 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 4031 if (ret) 4032 return ret; 4033 4034 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 4035 id32 &= ~0xFF; 4036 4037 switch (id32) { 4038 case KSZ9477_CHIP_ID: 4039 case KSZ9896_CHIP_ID: 4040 case KSZ9897_CHIP_ID: 4041 case KSZ9567_CHIP_ID: 4042 case KSZ8567_CHIP_ID: 4043 case LAN9370_CHIP_ID: 4044 case LAN9371_CHIP_ID: 4045 case LAN9372_CHIP_ID: 4046 case LAN9373_CHIP_ID: 4047 case LAN9374_CHIP_ID: 4048 4049 /* LAN9646 does not have its own chip id. */ 4050 if (dev->chip_id != LAN9646_CHIP_ID) 4051 dev->chip_id = id32; 4052 break; 4053 case KSZ9893_CHIP_ID: 4054 ret = ksz_read8(dev, REG_CHIP_ID4, 4055 &id4); 4056 if (ret) 4057 return ret; 4058 4059 if (id4 == SKU_ID_KSZ8563) 4060 dev->chip_id = KSZ8563_CHIP_ID; 4061 else if (id4 == SKU_ID_KSZ9563) 4062 dev->chip_id = KSZ9563_CHIP_ID; 4063 else 4064 dev->chip_id = KSZ9893_CHIP_ID; 4065 4066 break; 4067 default: 4068 dev_err(dev->dev, 4069 "unsupported switch detected %x)\n", id32); 4070 return -ENODEV; 4071 } 4072 } 4073 return 0; 4074 } 4075 4076 static int ksz_cls_flower_add(struct dsa_switch *ds, int port, 4077 struct flow_cls_offload *cls, bool ingress) 4078 { 4079 struct ksz_device *dev = ds->priv; 4080 4081 switch (dev->chip_id) { 4082 case KSZ8563_CHIP_ID: 4083 case KSZ8567_CHIP_ID: 4084 case KSZ9477_CHIP_ID: 4085 case KSZ9563_CHIP_ID: 4086 case KSZ9567_CHIP_ID: 4087 case KSZ9893_CHIP_ID: 4088 case KSZ9896_CHIP_ID: 4089 case KSZ9897_CHIP_ID: 4090 case LAN9646_CHIP_ID: 4091 return ksz9477_cls_flower_add(ds, port, cls, ingress); 4092 } 4093 4094 return -EOPNOTSUPP; 4095 } 4096 4097 static int ksz_cls_flower_del(struct dsa_switch *ds, int port, 4098 struct flow_cls_offload *cls, bool ingress) 4099 { 4100 struct ksz_device *dev = ds->priv; 4101 4102 switch (dev->chip_id) { 4103 case KSZ8563_CHIP_ID: 4104 case KSZ8567_CHIP_ID: 4105 case KSZ9477_CHIP_ID: 4106 case KSZ9563_CHIP_ID: 4107 case KSZ9567_CHIP_ID: 4108 case KSZ9893_CHIP_ID: 4109 case KSZ9896_CHIP_ID: 4110 case KSZ9897_CHIP_ID: 4111 case LAN9646_CHIP_ID: 4112 return ksz9477_cls_flower_del(ds, port, cls, ingress); 4113 } 4114 4115 return -EOPNOTSUPP; 4116 } 4117 4118 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 4119 * is converted to Hex-decimal using the successive multiplication method. On 4120 * every step, integer part is taken and decimal part is carry forwarded. 4121 */ 4122 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 4123 { 4124 u32 cinc = 0; 4125 u32 txrate; 4126 u32 rate; 4127 u8 temp; 4128 u8 i; 4129 4130 txrate = idle_slope - send_slope; 4131 4132 if (!txrate) 4133 return -EINVAL; 4134 4135 rate = idle_slope; 4136 4137 /* 24 bit register */ 4138 for (i = 0; i < 6; i++) { 4139 rate = rate * 16; 4140 4141 temp = rate / txrate; 4142 4143 rate %= txrate; 4144 4145 cinc = ((cinc << 4) | temp); 4146 } 4147 4148 *bw = cinc; 4149 4150 return 0; 4151 } 4152 4153 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 4154 u8 shaper) 4155 { 4156 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 4157 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 4158 FIELD_PREP(MTI_SHAPING_M, shaper)); 4159 } 4160 4161 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 4162 struct tc_cbs_qopt_offload *qopt) 4163 { 4164 struct ksz_device *dev = ds->priv; 4165 int ret; 4166 u32 bw; 4167 4168 if (!dev->info->tc_cbs_supported) 4169 return -EOPNOTSUPP; 4170 4171 if (qopt->queue > dev->info->num_tx_queues) 4172 return -EINVAL; 4173 4174 /* Queue Selection */ 4175 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 4176 if (ret) 4177 return ret; 4178 4179 if (!qopt->enable) 4180 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 4181 MTI_SHAPING_OFF); 4182 4183 /* High Credit */ 4184 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 4185 qopt->hicredit); 4186 if (ret) 4187 return ret; 4188 4189 /* Low Credit */ 4190 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 4191 qopt->locredit); 4192 if (ret) 4193 return ret; 4194 4195 /* Credit Increment Register */ 4196 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 4197 if (ret) 4198 return ret; 4199 4200 if (dev->dev_ops->tc_cbs_set_cinc) { 4201 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 4202 if (ret) 4203 return ret; 4204 } 4205 4206 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 4207 MTI_SHAPING_SRP); 4208 } 4209 4210 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 4211 { 4212 int queue, ret; 4213 4214 /* Configuration will not take effect until the last Port Queue X 4215 * Egress Limit Control Register is written. 4216 */ 4217 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 4218 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 4219 KSZ9477_OUT_RATE_NO_LIMIT); 4220 if (ret) 4221 return ret; 4222 } 4223 4224 return 0; 4225 } 4226 4227 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 4228 int band) 4229 { 4230 /* Compared to queues, bands prioritize packets differently. In strict 4231 * priority mode, the lowest priority is assigned to Queue 0 while the 4232 * highest priority is given to Band 0. 4233 */ 4234 return p->bands - 1 - band; 4235 } 4236 4237 static u8 ksz8463_tc_ctrl(int port, int queue) 4238 { 4239 u8 reg; 4240 4241 reg = 0xC8 + port * 4; 4242 reg += ((3 - queue) / 2) * 2; 4243 reg++; 4244 reg -= (queue & 1); 4245 return reg; 4246 } 4247 4248 /** 4249 * ksz88x3_tc_ets_add - Configure ETS (Enhanced Transmission Selection) 4250 * for a port on KSZ88x3 switch 4251 * @dev: Pointer to the KSZ switch device structure 4252 * @port: Port number to configure 4253 * @p: Pointer to offload replace parameters describing ETS bands and mapping 4254 * 4255 * The KSZ88x3 supports two scheduling modes: Strict Priority and 4256 * Weighted Fair Queuing (WFQ). Both modes have fixed behavior: 4257 * - No configurable queue-to-priority mapping 4258 * - No weight adjustment in WFQ mode 4259 * 4260 * This function configures the switch to use strict priority mode by 4261 * clearing the WFQ enable bit for all queues associated with ETS bands. 4262 * If strict priority is not explicitly requested, the switch will default 4263 * to WFQ mode. 4264 * 4265 * Return: 0 on success, or a negative error code on failure 4266 */ 4267 static int ksz88x3_tc_ets_add(struct ksz_device *dev, int port, 4268 struct tc_ets_qopt_offload_replace_params *p) 4269 { 4270 int ret, band; 4271 4272 /* Only strict priority mode is supported for now. 4273 * WFQ is implicitly enabled when strict mode is disabled. 4274 */ 4275 for (band = 0; band < p->bands; band++) { 4276 int queue = ksz_ets_band_to_queue(p, band); 4277 u8 reg; 4278 4279 /* Calculate TXQ Split Control register address for this 4280 * port/queue 4281 */ 4282 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue); 4283 if (ksz_is_ksz8463(dev)) 4284 reg = ksz8463_tc_ctrl(port, queue); 4285 4286 /* Clear WFQ enable bit to select strict priority scheduling */ 4287 ret = ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE, 0); 4288 if (ret) 4289 return ret; 4290 } 4291 4292 return 0; 4293 } 4294 4295 /** 4296 * ksz88x3_tc_ets_del - Reset ETS (Enhanced Transmission Selection) config 4297 * for a port on KSZ88x3 switch 4298 * @dev: Pointer to the KSZ switch device structure 4299 * @port: Port number to reset 4300 * 4301 * The KSZ88x3 supports only fixed scheduling modes: Strict Priority or 4302 * Weighted Fair Queuing (WFQ), with no reconfiguration of weights or 4303 * queue mapping. This function resets the port’s scheduling mode to 4304 * the default, which is WFQ, by enabling the WFQ bit for all queues. 4305 * 4306 * Return: 0 on success, or a negative error code on failure 4307 */ 4308 static int ksz88x3_tc_ets_del(struct ksz_device *dev, int port) 4309 { 4310 int ret, queue; 4311 4312 /* Iterate over all transmit queues for this port */ 4313 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 4314 u8 reg; 4315 4316 /* Calculate TXQ Split Control register address for this 4317 * port/queue 4318 */ 4319 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue); 4320 if (ksz_is_ksz8463(dev)) 4321 reg = ksz8463_tc_ctrl(port, queue); 4322 4323 /* Set WFQ enable bit to revert back to default scheduling 4324 * mode 4325 */ 4326 ret = ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE, 4327 KSZ8873_TXQ_WFQ_ENABLE); 4328 if (ret) 4329 return ret; 4330 } 4331 4332 return 0; 4333 } 4334 4335 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 4336 { 4337 int ret; 4338 4339 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 4340 if (ret) 4341 return ret; 4342 4343 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 4344 MTI_SHAPING_OFF); 4345 } 4346 4347 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 4348 int weight) 4349 { 4350 int ret; 4351 4352 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 4353 if (ret) 4354 return ret; 4355 4356 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 4357 MTI_SHAPING_OFF); 4358 if (ret) 4359 return ret; 4360 4361 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 4362 } 4363 4364 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 4365 struct tc_ets_qopt_offload_replace_params *p) 4366 { 4367 int ret, band, tc_prio; 4368 u32 queue_map = 0; 4369 4370 /* In order to ensure proper prioritization, it is necessary to set the 4371 * rate limit for the related queue to zero. Otherwise strict priority 4372 * or WRR mode will not work. This is a hardware limitation. 4373 */ 4374 ret = ksz_disable_egress_rate_limit(dev, port); 4375 if (ret) 4376 return ret; 4377 4378 /* Configure queue scheduling mode for all bands. Currently only strict 4379 * prio mode is supported. 4380 */ 4381 for (band = 0; band < p->bands; band++) { 4382 int queue = ksz_ets_band_to_queue(p, band); 4383 4384 ret = ksz_queue_set_strict(dev, port, queue); 4385 if (ret) 4386 return ret; 4387 } 4388 4389 /* Configure the mapping between traffic classes and queues. Note: 4390 * priomap variable support 16 traffic classes, but the chip can handle 4391 * only 8 classes. 4392 */ 4393 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 4394 int queue; 4395 4396 if (tc_prio >= dev->info->num_ipms) 4397 break; 4398 4399 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 4400 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 4401 } 4402 4403 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 4404 } 4405 4406 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 4407 { 4408 int ret, queue; 4409 4410 /* To restore the default chip configuration, set all queues to use the 4411 * WRR scheduler with a weight of 1. 4412 */ 4413 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 4414 ret = ksz_queue_set_wrr(dev, port, queue, 4415 KSZ9477_DEFAULT_WRR_WEIGHT); 4416 4417 if (ret) 4418 return ret; 4419 } 4420 4421 /* Revert the queue mapping for TC-priority to its default setting on 4422 * the chip. 4423 */ 4424 return ksz9477_set_default_prio_queue_mapping(dev, port); 4425 } 4426 4427 static int ksz_tc_ets_validate(struct ksz_device *dev, int port, 4428 struct tc_ets_qopt_offload_replace_params *p) 4429 { 4430 int band; 4431 4432 /* Since it is not feasible to share one port among multiple qdisc, 4433 * the user must configure all available queues appropriately. 4434 */ 4435 if (p->bands != dev->info->num_tx_queues) { 4436 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 4437 dev->info->num_tx_queues); 4438 return -EOPNOTSUPP; 4439 } 4440 4441 for (band = 0; band < p->bands; ++band) { 4442 /* The KSZ switches utilize a weighted round robin configuration 4443 * where a certain number of packets can be transmitted from a 4444 * queue before the next queue is serviced. For more information 4445 * on this, refer to section 5.2.8.4 of the KSZ8565R 4446 * documentation on the Port Transmit Queue Control 1 Register. 4447 * However, the current ETS Qdisc implementation (as of February 4448 * 2023) assigns a weight to each queue based on the number of 4449 * bytes or extrapolated bandwidth in percentages. Since this 4450 * differs from the KSZ switches' method and we don't want to 4451 * fake support by converting bytes to packets, it is better to 4452 * return an error instead. 4453 */ 4454 if (p->quanta[band]) { 4455 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 4456 return -EOPNOTSUPP; 4457 } 4458 } 4459 4460 return 0; 4461 } 4462 4463 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 4464 struct tc_ets_qopt_offload *qopt) 4465 { 4466 struct ksz_device *dev = ds->priv; 4467 int ret; 4468 4469 if (is_ksz8(dev) && !(ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev))) 4470 return -EOPNOTSUPP; 4471 4472 if (qopt->parent != TC_H_ROOT) { 4473 dev_err(dev->dev, "Parent should be \"root\"\n"); 4474 return -EOPNOTSUPP; 4475 } 4476 4477 switch (qopt->command) { 4478 case TC_ETS_REPLACE: 4479 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 4480 if (ret) 4481 return ret; 4482 4483 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 4484 return ksz88x3_tc_ets_add(dev, port, 4485 &qopt->replace_params); 4486 else 4487 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 4488 case TC_ETS_DESTROY: 4489 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 4490 return ksz88x3_tc_ets_del(dev, port); 4491 else 4492 return ksz_tc_ets_del(dev, port); 4493 case TC_ETS_STATS: 4494 case TC_ETS_GRAFT: 4495 return -EOPNOTSUPP; 4496 } 4497 4498 return -EOPNOTSUPP; 4499 } 4500 4501 static int ksz_setup_tc(struct dsa_switch *ds, int port, 4502 enum tc_setup_type type, void *type_data) 4503 { 4504 switch (type) { 4505 case TC_SETUP_QDISC_CBS: 4506 return ksz_setup_tc_cbs(ds, port, type_data); 4507 case TC_SETUP_QDISC_ETS: 4508 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 4509 default: 4510 return -EOPNOTSUPP; 4511 } 4512 } 4513 4514 /** 4515 * ksz_handle_wake_reason - Handle wake reason on a specified port. 4516 * @dev: The device structure. 4517 * @port: The port number. 4518 * 4519 * This function reads the PME (Power Management Event) status register of a 4520 * specified port to determine the wake reason. If there is no wake event, it 4521 * returns early. Otherwise, it logs the wake reason which could be due to a 4522 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register 4523 * is then cleared to acknowledge the handling of the wake event. 4524 * 4525 * Return: 0 on success, or an error code on failure. 4526 */ 4527 int ksz_handle_wake_reason(struct ksz_device *dev, int port) 4528 { 4529 const struct ksz_dev_ops *ops = dev->dev_ops; 4530 const u16 *regs = dev->info->regs; 4531 u8 pme_status; 4532 int ret; 4533 4534 ret = ops->pme_pread8(dev, port, regs[REG_PORT_PME_STATUS], 4535 &pme_status); 4536 if (ret) 4537 return ret; 4538 4539 if (!pme_status) 4540 return 0; 4541 4542 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port, 4543 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "", 4544 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "", 4545 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : ""); 4546 4547 return ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_STATUS], 4548 pme_status); 4549 } 4550 4551 /** 4552 * ksz_get_wol - Get Wake-on-LAN settings for a specified port. 4553 * @ds: The dsa_switch structure. 4554 * @port: The port number. 4555 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 4556 * 4557 * This function checks the device PME wakeup_source flag and chip_id. 4558 * If enabled and supported, it sets the supported and active WoL 4559 * flags. 4560 */ 4561 static void ksz_get_wol(struct dsa_switch *ds, int port, 4562 struct ethtool_wolinfo *wol) 4563 { 4564 struct ksz_device *dev = ds->priv; 4565 const u16 *regs = dev->info->regs; 4566 u8 pme_ctrl; 4567 int ret; 4568 4569 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4570 return; 4571 4572 if (!dev->wakeup_source) 4573 return; 4574 4575 wol->supported = WAKE_PHY; 4576 4577 /* Check if the current MAC address on this port can be set 4578 * as global for WAKE_MAGIC support. The result may vary 4579 * dynamically based on other ports configurations. 4580 */ 4581 if (ksz_is_port_mac_global_usable(dev->ds, port)) 4582 wol->supported |= WAKE_MAGIC; 4583 4584 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 4585 &pme_ctrl); 4586 if (ret) 4587 return; 4588 4589 if (pme_ctrl & PME_WOL_MAGICPKT) 4590 wol->wolopts |= WAKE_MAGIC; 4591 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY)) 4592 wol->wolopts |= WAKE_PHY; 4593 } 4594 4595 /** 4596 * ksz_set_wol - Set Wake-on-LAN settings for a specified port. 4597 * @ds: The dsa_switch structure. 4598 * @port: The port number. 4599 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 4600 * 4601 * This function configures Wake-on-LAN (WoL) settings for a specified 4602 * port. It validates the provided WoL options, checks if PME is 4603 * enabled and supported, clears any previous wake reasons, and sets 4604 * the Magic Packet flag in the port's PME control register if 4605 * specified. 4606 * 4607 * Return: 0 on success, or other error codes on failure. 4608 */ 4609 static int ksz_set_wol(struct dsa_switch *ds, int port, 4610 struct ethtool_wolinfo *wol) 4611 { 4612 u8 pme_ctrl = 0, pme_ctrl_old = 0; 4613 struct ksz_device *dev = ds->priv; 4614 const u16 *regs = dev->info->regs; 4615 bool magic_switched_off; 4616 bool magic_switched_on; 4617 int ret; 4618 4619 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC)) 4620 return -EINVAL; 4621 4622 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4623 return -EOPNOTSUPP; 4624 4625 if (!dev->wakeup_source) 4626 return -EOPNOTSUPP; 4627 4628 ret = ksz_handle_wake_reason(dev, port); 4629 if (ret) 4630 return ret; 4631 4632 if (wol->wolopts & WAKE_MAGIC) 4633 pme_ctrl |= PME_WOL_MAGICPKT; 4634 if (wol->wolopts & WAKE_PHY) 4635 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY; 4636 4637 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 4638 &pme_ctrl_old); 4639 if (ret) 4640 return ret; 4641 4642 if (pme_ctrl_old == pme_ctrl) 4643 return 0; 4644 4645 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) && 4646 !(pme_ctrl & PME_WOL_MAGICPKT); 4647 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) && 4648 (pme_ctrl & PME_WOL_MAGICPKT); 4649 4650 /* To keep reference count of MAC address, we should do this 4651 * operation only on change of WOL settings. 4652 */ 4653 if (magic_switched_on) { 4654 ret = ksz_switch_macaddr_get(dev->ds, port, NULL); 4655 if (ret) 4656 return ret; 4657 } else if (magic_switched_off) { 4658 ksz_switch_macaddr_put(dev->ds); 4659 } 4660 4661 ret = dev->dev_ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 4662 pme_ctrl); 4663 if (ret) { 4664 if (magic_switched_on) 4665 ksz_switch_macaddr_put(dev->ds); 4666 return ret; 4667 } 4668 4669 return 0; 4670 } 4671 4672 /** 4673 * ksz_wol_pre_shutdown - Prepares the switch device for shutdown while 4674 * considering Wake-on-LAN (WoL) settings. 4675 * @dev: The switch device structure. 4676 * @wol_enabled: Pointer to a boolean which will be set to true if WoL is 4677 * enabled on any port. 4678 * 4679 * This function prepares the switch device for a safe shutdown while taking 4680 * into account the Wake-on-LAN (WoL) settings on the user ports. It updates 4681 * the wol_enabled flag accordingly to reflect whether WoL is active on any 4682 * port. 4683 */ 4684 static void ksz_wol_pre_shutdown(struct ksz_device *dev, bool *wol_enabled) 4685 { 4686 const struct ksz_dev_ops *ops = dev->dev_ops; 4687 const u16 *regs = dev->info->regs; 4688 u8 pme_pin_en = PME_ENABLE; 4689 struct dsa_port *dp; 4690 int ret; 4691 4692 *wol_enabled = false; 4693 4694 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4695 return; 4696 4697 if (!dev->wakeup_source) 4698 return; 4699 4700 dsa_switch_for_each_user_port(dp, dev->ds) { 4701 u8 pme_ctrl = 0; 4702 4703 ret = ops->pme_pread8(dev, dp->index, 4704 regs[REG_PORT_PME_CTRL], &pme_ctrl); 4705 if (!ret && pme_ctrl) 4706 *wol_enabled = true; 4707 4708 /* make sure there are no pending wake events which would 4709 * prevent the device from going to sleep/shutdown. 4710 */ 4711 ksz_handle_wake_reason(dev, dp->index); 4712 } 4713 4714 /* Now we are save to enable PME pin. */ 4715 if (*wol_enabled) { 4716 if (dev->pme_active_high) 4717 pme_pin_en |= PME_POLARITY; 4718 ops->pme_write8(dev, regs[REG_SW_PME_CTRL], pme_pin_en); 4719 if (ksz_is_ksz87xx(dev)) 4720 ksz_write8(dev, KSZ87XX_REG_INT_EN, KSZ87XX_INT_PME_MASK); 4721 } 4722 } 4723 4724 static int ksz_port_set_mac_address(struct dsa_switch *ds, int port, 4725 const unsigned char *addr) 4726 { 4727 struct dsa_port *dp = dsa_to_port(ds, port); 4728 struct ethtool_wolinfo wol; 4729 4730 if (dp->hsr_dev) { 4731 dev_err(ds->dev, 4732 "Cannot change MAC address on port %d with active HSR offload\n", 4733 port); 4734 return -EBUSY; 4735 } 4736 4737 /* Need to initialize variable as the code to fill in settings may 4738 * not be executed. 4739 */ 4740 wol.wolopts = 0; 4741 4742 ksz_get_wol(ds, dp->index, &wol); 4743 if (wol.wolopts & WAKE_MAGIC) { 4744 dev_err(ds->dev, 4745 "Cannot change MAC address on port %d with active Wake on Magic Packet\n", 4746 port); 4747 return -EBUSY; 4748 } 4749 4750 return 0; 4751 } 4752 4753 /** 4754 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port 4755 * can be used as a global address. 4756 * @ds: Pointer to the DSA switch structure. 4757 * @port: The port number on which the MAC address is to be checked. 4758 * 4759 * This function examines the MAC address set on the specified port and 4760 * determines if it can be used as a global address for the switch. 4761 * 4762 * Return: true if the port's MAC address can be used as a global address, false 4763 * otherwise. 4764 */ 4765 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port) 4766 { 4767 struct net_device *user = dsa_to_port(ds, port)->user; 4768 const unsigned char *addr = user->dev_addr; 4769 struct ksz_switch_macaddr *switch_macaddr; 4770 struct ksz_device *dev = ds->priv; 4771 4772 ASSERT_RTNL(); 4773 4774 switch_macaddr = dev->switch_macaddr; 4775 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr)) 4776 return false; 4777 4778 return true; 4779 } 4780 4781 /** 4782 * ksz_switch_macaddr_get - Program the switch's MAC address register. 4783 * @ds: DSA switch instance. 4784 * @port: Port number. 4785 * @extack: Netlink extended acknowledgment. 4786 * 4787 * This function programs the switch's MAC address register with the MAC address 4788 * of the requesting user port. This single address is used by the switch for 4789 * multiple features like HSR self-address filtering and WoL. Other user ports 4790 * can share ownership of this address as long as their MAC address is the same. 4791 * The MAC addresses of user ports must not change while they have ownership of 4792 * the switch MAC address. 4793 * 4794 * Return: 0 on success, or other error codes on failure. 4795 */ 4796 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 4797 struct netlink_ext_ack *extack) 4798 { 4799 struct net_device *user = dsa_to_port(ds, port)->user; 4800 const unsigned char *addr = user->dev_addr; 4801 struct ksz_switch_macaddr *switch_macaddr; 4802 struct ksz_device *dev = ds->priv; 4803 const u16 *regs = dev->info->regs; 4804 int i, ret; 4805 4806 /* Make sure concurrent MAC address changes are blocked */ 4807 ASSERT_RTNL(); 4808 4809 switch_macaddr = dev->switch_macaddr; 4810 if (switch_macaddr) { 4811 if (!ether_addr_equal(switch_macaddr->addr, addr)) { 4812 NL_SET_ERR_MSG_FMT_MOD(extack, 4813 "Switch already configured for MAC address %pM", 4814 switch_macaddr->addr); 4815 return -EBUSY; 4816 } 4817 4818 refcount_inc(&switch_macaddr->refcount); 4819 return 0; 4820 } 4821 4822 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL); 4823 if (!switch_macaddr) 4824 return -ENOMEM; 4825 4826 ether_addr_copy(switch_macaddr->addr, addr); 4827 refcount_set(&switch_macaddr->refcount, 1); 4828 dev->switch_macaddr = switch_macaddr; 4829 4830 /* Program the switch MAC address to hardware */ 4831 for (i = 0; i < ETH_ALEN; i++) { 4832 if (ksz_is_ksz8463(dev)) { 4833 u16 addr16 = ((u16)addr[i] << 8) | addr[i + 1]; 4834 4835 ret = ksz_write16(dev, regs[REG_SW_MAC_ADDR] + i, 4836 addr16); 4837 i++; 4838 } else { 4839 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 4840 addr[i]); 4841 } 4842 if (ret) 4843 goto macaddr_drop; 4844 } 4845 4846 return 0; 4847 4848 macaddr_drop: 4849 dev->switch_macaddr = NULL; 4850 refcount_set(&switch_macaddr->refcount, 0); 4851 kfree(switch_macaddr); 4852 4853 return ret; 4854 } 4855 4856 void ksz_switch_macaddr_put(struct dsa_switch *ds) 4857 { 4858 struct ksz_switch_macaddr *switch_macaddr; 4859 struct ksz_device *dev = ds->priv; 4860 const u16 *regs = dev->info->regs; 4861 int i; 4862 4863 /* Make sure concurrent MAC address changes are blocked */ 4864 ASSERT_RTNL(); 4865 4866 switch_macaddr = dev->switch_macaddr; 4867 if (!refcount_dec_and_test(&switch_macaddr->refcount)) 4868 return; 4869 4870 for (i = 0; i < ETH_ALEN; i++) 4871 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0); 4872 4873 dev->switch_macaddr = NULL; 4874 kfree(switch_macaddr); 4875 } 4876 4877 static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr, 4878 struct netlink_ext_ack *extack) 4879 { 4880 struct ksz_device *dev = ds->priv; 4881 enum hsr_version ver; 4882 int ret; 4883 4884 ret = hsr_get_version(hsr, &ver); 4885 if (ret) 4886 return ret; 4887 4888 if (dev->chip_id != KSZ9477_CHIP_ID) { 4889 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload"); 4890 return -EOPNOTSUPP; 4891 } 4892 4893 /* KSZ9477 can support HW offloading of only 1 HSR device */ 4894 if (dev->hsr_dev && hsr != dev->hsr_dev) { 4895 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR"); 4896 return -EOPNOTSUPP; 4897 } 4898 4899 /* KSZ9477 only supports HSR v0 and v1 */ 4900 if (!(ver == HSR_V0 || ver == HSR_V1)) { 4901 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported"); 4902 return -EOPNOTSUPP; 4903 } 4904 4905 /* KSZ9477 can only perform HSR offloading for up to two ports */ 4906 if (hweight8(dev->hsr_ports) >= 2) { 4907 NL_SET_ERR_MSG_MOD(extack, 4908 "Cannot offload more than two ports - using software HSR"); 4909 return -EOPNOTSUPP; 4910 } 4911 4912 /* Self MAC address filtering, to avoid frames traversing 4913 * the HSR ring more than once. 4914 */ 4915 ret = ksz_switch_macaddr_get(ds, port, extack); 4916 if (ret) 4917 return ret; 4918 4919 ksz9477_hsr_join(ds, port, hsr); 4920 dev->hsr_dev = hsr; 4921 dev->hsr_ports |= BIT(port); 4922 4923 return 0; 4924 } 4925 4926 static int ksz_hsr_leave(struct dsa_switch *ds, int port, 4927 struct net_device *hsr) 4928 { 4929 struct ksz_device *dev = ds->priv; 4930 4931 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID); 4932 4933 ksz9477_hsr_leave(ds, port, hsr); 4934 dev->hsr_ports &= ~BIT(port); 4935 if (!dev->hsr_ports) 4936 dev->hsr_dev = NULL; 4937 4938 ksz_switch_macaddr_put(ds); 4939 4940 return 0; 4941 } 4942 4943 static int ksz_suspend(struct dsa_switch *ds) 4944 { 4945 struct ksz_device *dev = ds->priv; 4946 4947 cancel_delayed_work_sync(&dev->mib_read); 4948 return 0; 4949 } 4950 4951 static int ksz_resume(struct dsa_switch *ds) 4952 { 4953 struct ksz_device *dev = ds->priv; 4954 4955 if (dev->mib_read_interval) 4956 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 4957 return 0; 4958 } 4959 4960 static const struct dsa_switch_ops ksz_switch_ops = { 4961 .get_tag_protocol = ksz_get_tag_protocol, 4962 .connect_tag_protocol = ksz_connect_tag_protocol, 4963 .get_phy_flags = ksz_get_phy_flags, 4964 .setup = ksz_setup, 4965 .teardown = ksz_teardown, 4966 .phy_read = ksz_phy_read16, 4967 .phy_write = ksz_phy_write16, 4968 .phylink_get_caps = ksz_phylink_get_caps, 4969 .port_setup = ksz_port_setup, 4970 .set_ageing_time = ksz_set_ageing_time, 4971 .get_strings = ksz_get_strings, 4972 .get_ethtool_stats = ksz_get_ethtool_stats, 4973 .get_sset_count = ksz_sset_count, 4974 .port_bridge_join = ksz_port_bridge_join, 4975 .port_bridge_leave = ksz_port_bridge_leave, 4976 .port_hsr_join = ksz_hsr_join, 4977 .port_hsr_leave = ksz_hsr_leave, 4978 .port_set_mac_address = ksz_port_set_mac_address, 4979 .port_stp_state_set = ksz_port_stp_state_set, 4980 .port_teardown = ksz_port_teardown, 4981 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 4982 .port_bridge_flags = ksz_port_bridge_flags, 4983 .port_fast_age = ksz_port_fast_age, 4984 .port_vlan_filtering = ksz_port_vlan_filtering, 4985 .port_vlan_add = ksz_port_vlan_add, 4986 .port_vlan_del = ksz_port_vlan_del, 4987 .port_fdb_dump = ksz_port_fdb_dump, 4988 .port_fdb_add = ksz_port_fdb_add, 4989 .port_fdb_del = ksz_port_fdb_del, 4990 .port_mdb_add = ksz_port_mdb_add, 4991 .port_mdb_del = ksz_port_mdb_del, 4992 .port_mirror_add = ksz_port_mirror_add, 4993 .port_mirror_del = ksz_port_mirror_del, 4994 .get_stats64 = ksz_get_stats64, 4995 .get_pause_stats = ksz_get_pause_stats, 4996 .port_change_mtu = ksz_change_mtu, 4997 .port_max_mtu = ksz_max_mtu, 4998 .get_wol = ksz_get_wol, 4999 .set_wol = ksz_set_wol, 5000 .suspend = ksz_suspend, 5001 .resume = ksz_resume, 5002 .get_ts_info = ksz_get_ts_info, 5003 .port_hwtstamp_get = ksz_hwtstamp_get, 5004 .port_hwtstamp_set = ksz_hwtstamp_set, 5005 .port_txtstamp = ksz_port_txtstamp, 5006 .port_rxtstamp = ksz_port_rxtstamp, 5007 .cls_flower_add = ksz_cls_flower_add, 5008 .cls_flower_del = ksz_cls_flower_del, 5009 .port_setup_tc = ksz_setup_tc, 5010 .support_eee = ksz_support_eee, 5011 .set_mac_eee = ksz_set_mac_eee, 5012 .port_get_default_prio = ksz_port_get_default_prio, 5013 .port_set_default_prio = ksz_port_set_default_prio, 5014 .port_get_dscp_prio = ksz_port_get_dscp_prio, 5015 .port_add_dscp_prio = ksz_port_add_dscp_prio, 5016 .port_del_dscp_prio = ksz_port_del_dscp_prio, 5017 .port_get_apptrust = ksz_port_get_apptrust, 5018 .port_set_apptrust = ksz_port_set_apptrust, 5019 }; 5020 5021 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 5022 { 5023 struct dsa_switch *ds; 5024 struct ksz_device *swdev; 5025 5026 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 5027 if (!ds) 5028 return NULL; 5029 5030 ds->dev = base; 5031 ds->num_ports = DSA_MAX_PORTS; 5032 ds->ops = &ksz_switch_ops; 5033 5034 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 5035 if (!swdev) 5036 return NULL; 5037 5038 ds->priv = swdev; 5039 swdev->dev = base; 5040 5041 swdev->ds = ds; 5042 swdev->priv = priv; 5043 5044 return swdev; 5045 } 5046 EXPORT_SYMBOL(ksz_switch_alloc); 5047 5048 /** 5049 * ksz_switch_shutdown - Shutdown routine for the switch device. 5050 * @dev: The switch device structure. 5051 * 5052 * This function is responsible for initiating a shutdown sequence for the 5053 * switch device. It invokes the reset operation defined in the device 5054 * operations, if available, to reset the switch. Subsequently, it calls the 5055 * DSA framework's shutdown function to ensure a proper shutdown of the DSA 5056 * switch. 5057 */ 5058 void ksz_switch_shutdown(struct ksz_device *dev) 5059 { 5060 bool wol_enabled = false; 5061 5062 ksz_wol_pre_shutdown(dev, &wol_enabled); 5063 5064 if (dev->dev_ops->reset && !wol_enabled) 5065 dev->dev_ops->reset(dev); 5066 5067 dsa_switch_shutdown(dev->ds); 5068 } 5069 EXPORT_SYMBOL(ksz_switch_shutdown); 5070 5071 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 5072 struct device_node *port_dn) 5073 { 5074 phy_interface_t phy_mode = dev->ports[port_num].interface; 5075 int rx_delay = -1, tx_delay = -1; 5076 5077 if (!phy_interface_mode_is_rgmii(phy_mode)) 5078 return; 5079 5080 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 5081 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 5082 5083 if (rx_delay == -1 && tx_delay == -1) { 5084 dev_warn(dev->dev, 5085 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 5086 "please update device tree to specify \"rx-internal-delay-ps\" and " 5087 "\"tx-internal-delay-ps\"", 5088 port_num); 5089 5090 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 5091 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 5092 rx_delay = 2000; 5093 5094 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 5095 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 5096 tx_delay = 2000; 5097 } 5098 5099 if (rx_delay < 0) 5100 rx_delay = 0; 5101 if (tx_delay < 0) 5102 tx_delay = 0; 5103 5104 dev->ports[port_num].rgmii_rx_val = rx_delay; 5105 dev->ports[port_num].rgmii_tx_val = tx_delay; 5106 } 5107 5108 /** 5109 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding 5110 * register value. 5111 * @array: The array of drive strength values to search. 5112 * @array_size: The size of the array. 5113 * @microamp: The drive strength value in microamp to be converted. 5114 * 5115 * This function searches the array of drive strength values for the given 5116 * microamp value and returns the corresponding register value for that drive. 5117 * 5118 * Returns: If found, the corresponding register value for that drive strength 5119 * is returned. Otherwise, -EINVAL is returned indicating an invalid value. 5120 */ 5121 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array, 5122 size_t array_size, int microamp) 5123 { 5124 int i; 5125 5126 for (i = 0; i < array_size; i++) { 5127 if (array[i].microamp == microamp) 5128 return array[i].reg_val; 5129 } 5130 5131 return -EINVAL; 5132 } 5133 5134 /** 5135 * ksz_drive_strength_error() - Report invalid drive strength value 5136 * @dev: ksz device 5137 * @array: The array of drive strength values to search. 5138 * @array_size: The size of the array. 5139 * @microamp: Invalid drive strength value in microamp 5140 * 5141 * This function logs an error message when an unsupported drive strength value 5142 * is detected. It lists out all the supported drive strength values for 5143 * reference in the error message. 5144 */ 5145 static void ksz_drive_strength_error(struct ksz_device *dev, 5146 const struct ksz_drive_strength *array, 5147 size_t array_size, int microamp) 5148 { 5149 char supported_values[100]; 5150 size_t remaining_size; 5151 int added_len; 5152 char *ptr; 5153 int i; 5154 5155 remaining_size = sizeof(supported_values); 5156 ptr = supported_values; 5157 5158 for (i = 0; i < array_size; i++) { 5159 added_len = snprintf(ptr, remaining_size, 5160 i == 0 ? "%d" : ", %d", array[i].microamp); 5161 5162 if (added_len >= remaining_size) 5163 break; 5164 5165 ptr += added_len; 5166 remaining_size -= added_len; 5167 } 5168 5169 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n", 5170 microamp, supported_values); 5171 } 5172 5173 /** 5174 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477 5175 * chip variants. 5176 * @dev: ksz device 5177 * @props: Array of drive strength properties to be applied 5178 * @num_props: Number of properties in the array 5179 * 5180 * This function configures the drive strength for various KSZ9477 chip variants 5181 * based on the provided properties. It handles chip-specific nuances and 5182 * ensures only valid drive strengths are written to the respective chip. 5183 * 5184 * Return: 0 on successful configuration, a negative error code on failure. 5185 */ 5186 static int ksz9477_drive_strength_write(struct ksz_device *dev, 5187 struct ksz_driver_strength_prop *props, 5188 int num_props) 5189 { 5190 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths); 5191 int i, ret, reg; 5192 u8 mask = 0; 5193 u8 val = 0; 5194 5195 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1) 5196 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 5197 props[KSZ_DRIVER_STRENGTH_IO].name); 5198 5199 if (dev->chip_id == KSZ8795_CHIP_ID || 5200 dev->chip_id == KSZ8794_CHIP_ID || 5201 dev->chip_id == KSZ8765_CHIP_ID) 5202 reg = KSZ8795_REG_SW_CTRL_20; 5203 else 5204 reg = KSZ9477_REG_SW_IO_STRENGTH; 5205 5206 for (i = 0; i < num_props; i++) { 5207 if (props[i].value == -1) 5208 continue; 5209 5210 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths, 5211 array_size, props[i].value); 5212 if (ret < 0) { 5213 ksz_drive_strength_error(dev, ksz9477_drive_strengths, 5214 array_size, props[i].value); 5215 return ret; 5216 } 5217 5218 mask |= SW_DRIVE_STRENGTH_M << props[i].offset; 5219 val |= ret << props[i].offset; 5220 } 5221 5222 return ksz_rmw8(dev, reg, mask, val); 5223 } 5224 5225 /** 5226 * ksz88x3_drive_strength_write() - Set the drive strength configuration for 5227 * KSZ8863 compatible chip variants. 5228 * @dev: ksz device 5229 * @props: Array of drive strength properties to be set 5230 * @num_props: Number of properties in the array 5231 * 5232 * This function applies the specified drive strength settings to KSZ88X3 chip 5233 * variants (KSZ8873, KSZ8863). 5234 * It ensures the configurations align with what the chip variant supports and 5235 * warns or errors out on unsupported settings. 5236 * 5237 * Return: 0 on success, error code otherwise 5238 */ 5239 static int ksz88x3_drive_strength_write(struct ksz_device *dev, 5240 struct ksz_driver_strength_prop *props, 5241 int num_props) 5242 { 5243 size_t array_size = ARRAY_SIZE(ksz88x3_drive_strengths); 5244 int microamp; 5245 int i, ret; 5246 5247 for (i = 0; i < num_props; i++) { 5248 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO) 5249 continue; 5250 5251 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 5252 props[i].name); 5253 } 5254 5255 microamp = props[KSZ_DRIVER_STRENGTH_IO].value; 5256 ret = ksz_drive_strength_to_reg(ksz88x3_drive_strengths, array_size, 5257 microamp); 5258 if (ret < 0) { 5259 ksz_drive_strength_error(dev, ksz88x3_drive_strengths, 5260 array_size, microamp); 5261 return ret; 5262 } 5263 5264 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12, 5265 KSZ8873_DRIVE_STRENGTH_16MA, ret); 5266 } 5267 5268 /** 5269 * ksz_parse_drive_strength() - Extract and apply drive strength configurations 5270 * from device tree properties. 5271 * @dev: ksz device 5272 * 5273 * This function reads the specified drive strength properties from the 5274 * device tree, validates against the supported chip variants, and sets 5275 * them accordingly. An error should be critical here, as the drive strength 5276 * settings are crucial for EMI compliance. 5277 * 5278 * Return: 0 on success, error code otherwise 5279 */ 5280 static int ksz_parse_drive_strength(struct ksz_device *dev) 5281 { 5282 struct ksz_driver_strength_prop of_props[] = { 5283 [KSZ_DRIVER_STRENGTH_HI] = { 5284 .name = "microchip,hi-drive-strength-microamp", 5285 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S, 5286 .value = -1, 5287 }, 5288 [KSZ_DRIVER_STRENGTH_LO] = { 5289 .name = "microchip,lo-drive-strength-microamp", 5290 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S, 5291 .value = -1, 5292 }, 5293 [KSZ_DRIVER_STRENGTH_IO] = { 5294 .name = "microchip,io-drive-strength-microamp", 5295 .offset = 0, /* don't care */ 5296 .value = -1, 5297 }, 5298 }; 5299 struct device_node *np = dev->dev->of_node; 5300 bool have_any_prop = false; 5301 int i, ret; 5302 5303 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 5304 ret = of_property_read_u32(np, of_props[i].name, 5305 &of_props[i].value); 5306 if (ret && ret != -EINVAL) 5307 dev_warn(dev->dev, "Failed to read %s\n", 5308 of_props[i].name); 5309 if (ret) 5310 continue; 5311 5312 have_any_prop = true; 5313 } 5314 5315 if (!have_any_prop) 5316 return 0; 5317 5318 switch (dev->chip_id) { 5319 case KSZ88X3_CHIP_ID: 5320 return ksz88x3_drive_strength_write(dev, of_props, 5321 ARRAY_SIZE(of_props)); 5322 case KSZ8795_CHIP_ID: 5323 case KSZ8794_CHIP_ID: 5324 case KSZ8765_CHIP_ID: 5325 case KSZ8563_CHIP_ID: 5326 case KSZ8567_CHIP_ID: 5327 case KSZ9477_CHIP_ID: 5328 case KSZ9563_CHIP_ID: 5329 case KSZ9567_CHIP_ID: 5330 case KSZ9893_CHIP_ID: 5331 case KSZ9896_CHIP_ID: 5332 case KSZ9897_CHIP_ID: 5333 case LAN9646_CHIP_ID: 5334 return ksz9477_drive_strength_write(dev, of_props, 5335 ARRAY_SIZE(of_props)); 5336 default: 5337 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 5338 if (of_props[i].value == -1) 5339 continue; 5340 5341 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 5342 of_props[i].name); 5343 } 5344 } 5345 5346 return 0; 5347 } 5348 5349 static int ksz8463_configure_straps_spi(struct ksz_device *dev) 5350 { 5351 struct pinctrl *pinctrl; 5352 struct gpio_desc *rxd0; 5353 struct gpio_desc *rxd1; 5354 5355 rxd0 = devm_gpiod_get_index_optional(dev->dev, "straps-rxd", 0, GPIOD_OUT_LOW); 5356 if (IS_ERR(rxd0)) 5357 return PTR_ERR(rxd0); 5358 5359 rxd1 = devm_gpiod_get_index_optional(dev->dev, "straps-rxd", 1, GPIOD_OUT_HIGH); 5360 if (IS_ERR(rxd1)) 5361 return PTR_ERR(rxd1); 5362 5363 if (!rxd0 && !rxd1) 5364 return 0; 5365 5366 if ((rxd0 && !rxd1) || (rxd1 && !rxd0)) 5367 return -EINVAL; 5368 5369 pinctrl = devm_pinctrl_get_select(dev->dev, "reset"); 5370 if (IS_ERR(pinctrl)) 5371 return PTR_ERR(pinctrl); 5372 5373 return 0; 5374 } 5375 5376 static int ksz8463_release_straps_spi(struct ksz_device *dev) 5377 { 5378 return pinctrl_select_default_state(dev->dev); 5379 } 5380 5381 int ksz_switch_register(struct ksz_device *dev) 5382 { 5383 const struct ksz_chip_data *info; 5384 struct device_node *ports; 5385 phy_interface_t interface; 5386 unsigned int port_num; 5387 int ret; 5388 int i; 5389 5390 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 5391 GPIOD_OUT_LOW); 5392 if (IS_ERR(dev->reset_gpio)) 5393 return PTR_ERR(dev->reset_gpio); 5394 5395 if (dev->reset_gpio) { 5396 if (of_device_is_compatible(dev->dev->of_node, "microchip,ksz8463")) { 5397 ret = ksz8463_configure_straps_spi(dev); 5398 if (ret) 5399 return ret; 5400 } 5401 5402 gpiod_set_value_cansleep(dev->reset_gpio, 1); 5403 usleep_range(10000, 12000); 5404 gpiod_set_value_cansleep(dev->reset_gpio, 0); 5405 msleep(100); 5406 5407 if (of_device_is_compatible(dev->dev->of_node, "microchip,ksz8463")) { 5408 ret = ksz8463_release_straps_spi(dev); 5409 if (ret) 5410 return ret; 5411 } 5412 } 5413 5414 mutex_init(&dev->dev_mutex); 5415 mutex_init(&dev->regmap_mutex); 5416 mutex_init(&dev->alu_mutex); 5417 mutex_init(&dev->vlan_mutex); 5418 5419 ret = ksz_switch_detect(dev); 5420 if (ret) 5421 return ret; 5422 5423 info = ksz_lookup_info(dev->chip_id); 5424 if (!info) 5425 return -ENODEV; 5426 5427 /* Update the compatible info with the probed one */ 5428 dev->info = info; 5429 5430 dev_info(dev->dev, "found switch: %s, rev %i\n", 5431 dev->info->dev_name, dev->chip_rev); 5432 5433 ret = ksz_check_device_id(dev); 5434 if (ret) 5435 return ret; 5436 5437 dev->dev_ops = dev->info->ops; 5438 5439 ret = dev->dev_ops->init(dev); 5440 if (ret) 5441 return ret; 5442 5443 dev->ports = devm_kzalloc(dev->dev, 5444 dev->info->port_cnt * sizeof(struct ksz_port), 5445 GFP_KERNEL); 5446 if (!dev->ports) 5447 return -ENOMEM; 5448 5449 for (i = 0; i < dev->info->port_cnt; i++) { 5450 spin_lock_init(&dev->ports[i].mib.stats64_lock); 5451 mutex_init(&dev->ports[i].mib.cnt_mutex); 5452 dev->ports[i].mib.counters = 5453 devm_kzalloc(dev->dev, 5454 sizeof(u64) * (dev->info->mib_cnt + 1), 5455 GFP_KERNEL); 5456 if (!dev->ports[i].mib.counters) 5457 return -ENOMEM; 5458 5459 dev->ports[i].ksz_dev = dev; 5460 dev->ports[i].num = i; 5461 } 5462 5463 /* set the real number of ports */ 5464 dev->ds->num_ports = dev->info->port_cnt; 5465 5466 /* set the phylink ops */ 5467 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops; 5468 5469 /* Host port interface will be self detected, or specifically set in 5470 * device tree. 5471 */ 5472 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 5473 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 5474 if (dev->dev->of_node) { 5475 ret = of_get_phy_mode(dev->dev->of_node, &interface); 5476 if (ret == 0) 5477 dev->compat_interface = interface; 5478 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 5479 if (!ports) 5480 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 5481 if (ports) { 5482 for_each_available_child_of_node_scoped(ports, port) { 5483 if (of_property_read_u32(port, "reg", 5484 &port_num)) 5485 continue; 5486 if (!(dev->port_mask & BIT(port_num))) { 5487 of_node_put(ports); 5488 return -EINVAL; 5489 } 5490 of_get_phy_mode(port, 5491 &dev->ports[port_num].interface); 5492 5493 ksz_parse_rgmii_delay(dev, port_num, port); 5494 dev->ports[port_num].fiber = 5495 of_property_read_bool(port, 5496 "micrel,fiber-mode"); 5497 } 5498 of_node_put(ports); 5499 } 5500 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 5501 "microchip,synclko-125"); 5502 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 5503 "microchip,synclko-disable"); 5504 if (dev->synclko_125 && dev->synclko_disable) { 5505 dev_err(dev->dev, "inconsistent synclko settings\n"); 5506 return -EINVAL; 5507 } 5508 5509 dev->wakeup_source = of_property_read_bool(dev->dev->of_node, 5510 "wakeup-source"); 5511 dev->pme_active_high = of_property_read_bool(dev->dev->of_node, 5512 "microchip,pme-active-high"); 5513 } 5514 5515 ret = dsa_register_switch(dev->ds); 5516 if (ret) { 5517 dev->dev_ops->exit(dev); 5518 return ret; 5519 } 5520 5521 /* Read MIB counters every 30 seconds to avoid overflow. */ 5522 dev->mib_read_interval = msecs_to_jiffies(5000); 5523 5524 /* Start the MIB timer. */ 5525 schedule_delayed_work(&dev->mib_read, 0); 5526 5527 return ret; 5528 } 5529 EXPORT_SYMBOL(ksz_switch_register); 5530 5531 void ksz_switch_remove(struct ksz_device *dev) 5532 { 5533 /* timer started */ 5534 if (dev->mib_read_interval) { 5535 dev->mib_read_interval = 0; 5536 cancel_delayed_work_sync(&dev->mib_read); 5537 } 5538 5539 dev->dev_ops->exit(dev); 5540 dsa_unregister_switch(dev->ds); 5541 5542 if (dev->reset_gpio) 5543 gpiod_set_value_cansleep(dev->reset_gpio, 1); 5544 5545 } 5546 EXPORT_SYMBOL(ksz_switch_remove); 5547 5548 #ifdef CONFIG_PM_SLEEP 5549 int ksz_switch_suspend(struct device *dev) 5550 { 5551 struct ksz_device *priv = dev_get_drvdata(dev); 5552 5553 return dsa_switch_suspend(priv->ds); 5554 } 5555 EXPORT_SYMBOL(ksz_switch_suspend); 5556 5557 int ksz_switch_resume(struct device *dev) 5558 { 5559 struct ksz_device *priv = dev_get_drvdata(dev); 5560 5561 return dsa_switch_resume(priv->ds); 5562 } 5563 EXPORT_SYMBOL(ksz_switch_resume); 5564 #endif 5565 5566 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 5567 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 5568 MODULE_LICENSE("GPL"); 5569