1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/export.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/platform_data/microchip-ksz.h> 14 #include <linux/phy.h> 15 #include <linux/etherdevice.h> 16 #include <linux/if_bridge.h> 17 #include <linux/of_device.h> 18 #include <linux/of_net.h> 19 #include <linux/micrel_phy.h> 20 #include <net/dsa.h> 21 #include <net/switchdev.h> 22 23 #include "ksz_common.h" 24 #include "ksz8.h" 25 #include "ksz9477.h" 26 #include "lan937x.h" 27 28 #define MIB_COUNTER_NUM 0x20 29 30 struct ksz_stats_raw { 31 u64 rx_hi; 32 u64 rx_undersize; 33 u64 rx_fragments; 34 u64 rx_oversize; 35 u64 rx_jabbers; 36 u64 rx_symbol_err; 37 u64 rx_crc_err; 38 u64 rx_align_err; 39 u64 rx_mac_ctrl; 40 u64 rx_pause; 41 u64 rx_bcast; 42 u64 rx_mcast; 43 u64 rx_ucast; 44 u64 rx_64_or_less; 45 u64 rx_65_127; 46 u64 rx_128_255; 47 u64 rx_256_511; 48 u64 rx_512_1023; 49 u64 rx_1024_1522; 50 u64 rx_1523_2000; 51 u64 rx_2001; 52 u64 tx_hi; 53 u64 tx_late_col; 54 u64 tx_pause; 55 u64 tx_bcast; 56 u64 tx_mcast; 57 u64 tx_ucast; 58 u64 tx_deferred; 59 u64 tx_total_col; 60 u64 tx_exc_col; 61 u64 tx_single_col; 62 u64 tx_mult_col; 63 u64 rx_total; 64 u64 tx_total; 65 u64 rx_discards; 66 u64 tx_discards; 67 }; 68 69 static const struct ksz_mib_names ksz88xx_mib_names[] = { 70 { 0x00, "rx" }, 71 { 0x01, "rx_hi" }, 72 { 0x02, "rx_undersize" }, 73 { 0x03, "rx_fragments" }, 74 { 0x04, "rx_oversize" }, 75 { 0x05, "rx_jabbers" }, 76 { 0x06, "rx_symbol_err" }, 77 { 0x07, "rx_crc_err" }, 78 { 0x08, "rx_align_err" }, 79 { 0x09, "rx_mac_ctrl" }, 80 { 0x0a, "rx_pause" }, 81 { 0x0b, "rx_bcast" }, 82 { 0x0c, "rx_mcast" }, 83 { 0x0d, "rx_ucast" }, 84 { 0x0e, "rx_64_or_less" }, 85 { 0x0f, "rx_65_127" }, 86 { 0x10, "rx_128_255" }, 87 { 0x11, "rx_256_511" }, 88 { 0x12, "rx_512_1023" }, 89 { 0x13, "rx_1024_1522" }, 90 { 0x14, "tx" }, 91 { 0x15, "tx_hi" }, 92 { 0x16, "tx_late_col" }, 93 { 0x17, "tx_pause" }, 94 { 0x18, "tx_bcast" }, 95 { 0x19, "tx_mcast" }, 96 { 0x1a, "tx_ucast" }, 97 { 0x1b, "tx_deferred" }, 98 { 0x1c, "tx_total_col" }, 99 { 0x1d, "tx_exc_col" }, 100 { 0x1e, "tx_single_col" }, 101 { 0x1f, "tx_mult_col" }, 102 { 0x100, "rx_discards" }, 103 { 0x101, "tx_discards" }, 104 }; 105 106 static const struct ksz_mib_names ksz9477_mib_names[] = { 107 { 0x00, "rx_hi" }, 108 { 0x01, "rx_undersize" }, 109 { 0x02, "rx_fragments" }, 110 { 0x03, "rx_oversize" }, 111 { 0x04, "rx_jabbers" }, 112 { 0x05, "rx_symbol_err" }, 113 { 0x06, "rx_crc_err" }, 114 { 0x07, "rx_align_err" }, 115 { 0x08, "rx_mac_ctrl" }, 116 { 0x09, "rx_pause" }, 117 { 0x0A, "rx_bcast" }, 118 { 0x0B, "rx_mcast" }, 119 { 0x0C, "rx_ucast" }, 120 { 0x0D, "rx_64_or_less" }, 121 { 0x0E, "rx_65_127" }, 122 { 0x0F, "rx_128_255" }, 123 { 0x10, "rx_256_511" }, 124 { 0x11, "rx_512_1023" }, 125 { 0x12, "rx_1024_1522" }, 126 { 0x13, "rx_1523_2000" }, 127 { 0x14, "rx_2001" }, 128 { 0x15, "tx_hi" }, 129 { 0x16, "tx_late_col" }, 130 { 0x17, "tx_pause" }, 131 { 0x18, "tx_bcast" }, 132 { 0x19, "tx_mcast" }, 133 { 0x1A, "tx_ucast" }, 134 { 0x1B, "tx_deferred" }, 135 { 0x1C, "tx_total_col" }, 136 { 0x1D, "tx_exc_col" }, 137 { 0x1E, "tx_single_col" }, 138 { 0x1F, "tx_mult_col" }, 139 { 0x80, "rx_total" }, 140 { 0x81, "tx_total" }, 141 { 0x82, "rx_discards" }, 142 { 0x83, "tx_discards" }, 143 }; 144 145 static const struct ksz_dev_ops ksz8_dev_ops = { 146 .setup = ksz8_setup, 147 .get_port_addr = ksz8_get_port_addr, 148 .cfg_port_member = ksz8_cfg_port_member, 149 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 150 .port_setup = ksz8_port_setup, 151 .r_phy = ksz8_r_phy, 152 .w_phy = ksz8_w_phy, 153 .r_mib_cnt = ksz8_r_mib_cnt, 154 .r_mib_pkt = ksz8_r_mib_pkt, 155 .freeze_mib = ksz8_freeze_mib, 156 .port_init_cnt = ksz8_port_init_cnt, 157 .fdb_dump = ksz8_fdb_dump, 158 .mdb_add = ksz8_mdb_add, 159 .mdb_del = ksz8_mdb_del, 160 .vlan_filtering = ksz8_port_vlan_filtering, 161 .vlan_add = ksz8_port_vlan_add, 162 .vlan_del = ksz8_port_vlan_del, 163 .mirror_add = ksz8_port_mirror_add, 164 .mirror_del = ksz8_port_mirror_del, 165 .get_caps = ksz8_get_caps, 166 .config_cpu_port = ksz8_config_cpu_port, 167 .enable_stp_addr = ksz8_enable_stp_addr, 168 .reset = ksz8_reset_switch, 169 .init = ksz8_switch_init, 170 .exit = ksz8_switch_exit, 171 }; 172 173 static const struct ksz_dev_ops ksz9477_dev_ops = { 174 .setup = ksz9477_setup, 175 .get_port_addr = ksz9477_get_port_addr, 176 .cfg_port_member = ksz9477_cfg_port_member, 177 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 178 .port_setup = ksz9477_port_setup, 179 .r_phy = ksz9477_r_phy, 180 .w_phy = ksz9477_w_phy, 181 .r_mib_cnt = ksz9477_r_mib_cnt, 182 .r_mib_pkt = ksz9477_r_mib_pkt, 183 .r_mib_stat64 = ksz_r_mib_stats64, 184 .freeze_mib = ksz9477_freeze_mib, 185 .port_init_cnt = ksz9477_port_init_cnt, 186 .vlan_filtering = ksz9477_port_vlan_filtering, 187 .vlan_add = ksz9477_port_vlan_add, 188 .vlan_del = ksz9477_port_vlan_del, 189 .mirror_add = ksz9477_port_mirror_add, 190 .mirror_del = ksz9477_port_mirror_del, 191 .get_caps = ksz9477_get_caps, 192 .fdb_dump = ksz9477_fdb_dump, 193 .fdb_add = ksz9477_fdb_add, 194 .fdb_del = ksz9477_fdb_del, 195 .mdb_add = ksz9477_mdb_add, 196 .mdb_del = ksz9477_mdb_del, 197 .change_mtu = ksz9477_change_mtu, 198 .max_mtu = ksz9477_max_mtu, 199 .config_cpu_port = ksz9477_config_cpu_port, 200 .enable_stp_addr = ksz9477_enable_stp_addr, 201 .reset = ksz9477_reset_switch, 202 .init = ksz9477_switch_init, 203 .exit = ksz9477_switch_exit, 204 }; 205 206 static const struct ksz_dev_ops lan937x_dev_ops = { 207 .setup = lan937x_setup, 208 .teardown = lan937x_teardown, 209 .get_port_addr = ksz9477_get_port_addr, 210 .cfg_port_member = ksz9477_cfg_port_member, 211 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 212 .port_setup = lan937x_port_setup, 213 .r_phy = lan937x_r_phy, 214 .w_phy = lan937x_w_phy, 215 .r_mib_cnt = ksz9477_r_mib_cnt, 216 .r_mib_pkt = ksz9477_r_mib_pkt, 217 .r_mib_stat64 = ksz_r_mib_stats64, 218 .freeze_mib = ksz9477_freeze_mib, 219 .port_init_cnt = ksz9477_port_init_cnt, 220 .vlan_filtering = ksz9477_port_vlan_filtering, 221 .vlan_add = ksz9477_port_vlan_add, 222 .vlan_del = ksz9477_port_vlan_del, 223 .mirror_add = ksz9477_port_mirror_add, 224 .mirror_del = ksz9477_port_mirror_del, 225 .get_caps = lan937x_phylink_get_caps, 226 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 227 .fdb_dump = ksz9477_fdb_dump, 228 .fdb_add = ksz9477_fdb_add, 229 .fdb_del = ksz9477_fdb_del, 230 .mdb_add = ksz9477_mdb_add, 231 .mdb_del = ksz9477_mdb_del, 232 .change_mtu = lan937x_change_mtu, 233 .max_mtu = ksz9477_max_mtu, 234 .config_cpu_port = lan937x_config_cpu_port, 235 .enable_stp_addr = ksz9477_enable_stp_addr, 236 .reset = lan937x_reset_switch, 237 .init = lan937x_switch_init, 238 .exit = lan937x_switch_exit, 239 }; 240 241 static const u16 ksz8795_regs[] = { 242 [REG_IND_CTRL_0] = 0x6E, 243 [REG_IND_DATA_8] = 0x70, 244 [REG_IND_DATA_CHECK] = 0x72, 245 [REG_IND_DATA_HI] = 0x71, 246 [REG_IND_DATA_LO] = 0x75, 247 [REG_IND_MIB_CHECK] = 0x74, 248 [REG_IND_BYTE] = 0xA0, 249 [P_FORCE_CTRL] = 0x0C, 250 [P_LINK_STATUS] = 0x0E, 251 [P_LOCAL_CTRL] = 0x07, 252 [P_NEG_RESTART_CTRL] = 0x0D, 253 [P_REMOTE_STATUS] = 0x08, 254 [P_SPEED_STATUS] = 0x09, 255 [S_TAIL_TAG_CTRL] = 0x0C, 256 [P_STP_CTRL] = 0x02, 257 [S_START_CTRL] = 0x01, 258 [S_BROADCAST_CTRL] = 0x06, 259 [S_MULTICAST_CTRL] = 0x04, 260 [P_XMII_CTRL_0] = 0x06, 261 [P_XMII_CTRL_1] = 0x56, 262 }; 263 264 static const u32 ksz8795_masks[] = { 265 [PORT_802_1P_REMAPPING] = BIT(7), 266 [SW_TAIL_TAG_ENABLE] = BIT(1), 267 [MIB_COUNTER_OVERFLOW] = BIT(6), 268 [MIB_COUNTER_VALID] = BIT(5), 269 [VLAN_TABLE_FID] = GENMASK(6, 0), 270 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 271 [VLAN_TABLE_VALID] = BIT(12), 272 [STATIC_MAC_TABLE_VALID] = BIT(21), 273 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 274 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 275 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26), 276 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20), 277 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 278 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8), 279 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 280 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 281 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20), 282 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 283 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 284 [P_MII_TX_FLOW_CTRL] = BIT(5), 285 [P_MII_RX_FLOW_CTRL] = BIT(5), 286 }; 287 288 static const u8 ksz8795_xmii_ctrl0[] = { 289 [P_MII_100MBIT] = 0, 290 [P_MII_10MBIT] = 1, 291 [P_MII_FULL_DUPLEX] = 0, 292 [P_MII_HALF_DUPLEX] = 1, 293 }; 294 295 static const u8 ksz8795_xmii_ctrl1[] = { 296 [P_RGMII_SEL] = 3, 297 [P_GMII_SEL] = 2, 298 [P_RMII_SEL] = 1, 299 [P_MII_SEL] = 0, 300 [P_GMII_1GBIT] = 1, 301 [P_GMII_NOT_1GBIT] = 0, 302 }; 303 304 static const u8 ksz8795_shifts[] = { 305 [VLAN_TABLE_MEMBERSHIP_S] = 7, 306 [VLAN_TABLE] = 16, 307 [STATIC_MAC_FWD_PORTS] = 16, 308 [STATIC_MAC_FID] = 24, 309 [DYNAMIC_MAC_ENTRIES_H] = 3, 310 [DYNAMIC_MAC_ENTRIES] = 29, 311 [DYNAMIC_MAC_FID] = 16, 312 [DYNAMIC_MAC_TIMESTAMP] = 27, 313 [DYNAMIC_MAC_SRC_PORT] = 24, 314 }; 315 316 static const u16 ksz8863_regs[] = { 317 [REG_IND_CTRL_0] = 0x79, 318 [REG_IND_DATA_8] = 0x7B, 319 [REG_IND_DATA_CHECK] = 0x7B, 320 [REG_IND_DATA_HI] = 0x7C, 321 [REG_IND_DATA_LO] = 0x80, 322 [REG_IND_MIB_CHECK] = 0x80, 323 [P_FORCE_CTRL] = 0x0C, 324 [P_LINK_STATUS] = 0x0E, 325 [P_LOCAL_CTRL] = 0x0C, 326 [P_NEG_RESTART_CTRL] = 0x0D, 327 [P_REMOTE_STATUS] = 0x0E, 328 [P_SPEED_STATUS] = 0x0F, 329 [S_TAIL_TAG_CTRL] = 0x03, 330 [P_STP_CTRL] = 0x02, 331 [S_START_CTRL] = 0x01, 332 [S_BROADCAST_CTRL] = 0x06, 333 [S_MULTICAST_CTRL] = 0x04, 334 }; 335 336 static const u32 ksz8863_masks[] = { 337 [PORT_802_1P_REMAPPING] = BIT(3), 338 [SW_TAIL_TAG_ENABLE] = BIT(6), 339 [MIB_COUNTER_OVERFLOW] = BIT(7), 340 [MIB_COUNTER_VALID] = BIT(6), 341 [VLAN_TABLE_FID] = GENMASK(15, 12), 342 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 343 [VLAN_TABLE_VALID] = BIT(19), 344 [STATIC_MAC_TABLE_VALID] = BIT(19), 345 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 346 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26), 347 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 348 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 349 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0), 350 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 351 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 352 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28), 353 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 354 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 355 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 356 }; 357 358 static u8 ksz8863_shifts[] = { 359 [VLAN_TABLE_MEMBERSHIP_S] = 16, 360 [STATIC_MAC_FWD_PORTS] = 16, 361 [STATIC_MAC_FID] = 22, 362 [DYNAMIC_MAC_ENTRIES_H] = 3, 363 [DYNAMIC_MAC_ENTRIES] = 24, 364 [DYNAMIC_MAC_FID] = 16, 365 [DYNAMIC_MAC_TIMESTAMP] = 24, 366 [DYNAMIC_MAC_SRC_PORT] = 20, 367 }; 368 369 static const u16 ksz9477_regs[] = { 370 [P_STP_CTRL] = 0x0B04, 371 [S_START_CTRL] = 0x0300, 372 [S_BROADCAST_CTRL] = 0x0332, 373 [S_MULTICAST_CTRL] = 0x0331, 374 [P_XMII_CTRL_0] = 0x0300, 375 [P_XMII_CTRL_1] = 0x0301, 376 }; 377 378 static const u32 ksz9477_masks[] = { 379 [ALU_STAT_WRITE] = 0, 380 [ALU_STAT_READ] = 1, 381 [P_MII_TX_FLOW_CTRL] = BIT(5), 382 [P_MII_RX_FLOW_CTRL] = BIT(3), 383 }; 384 385 static const u8 ksz9477_shifts[] = { 386 [ALU_STAT_INDEX] = 16, 387 }; 388 389 static const u8 ksz9477_xmii_ctrl0[] = { 390 [P_MII_100MBIT] = 1, 391 [P_MII_10MBIT] = 0, 392 [P_MII_FULL_DUPLEX] = 1, 393 [P_MII_HALF_DUPLEX] = 0, 394 }; 395 396 static const u8 ksz9477_xmii_ctrl1[] = { 397 [P_RGMII_SEL] = 0, 398 [P_RMII_SEL] = 1, 399 [P_GMII_SEL] = 2, 400 [P_MII_SEL] = 3, 401 [P_GMII_1GBIT] = 0, 402 [P_GMII_NOT_1GBIT] = 1, 403 }; 404 405 static const u32 lan937x_masks[] = { 406 [ALU_STAT_WRITE] = 1, 407 [ALU_STAT_READ] = 2, 408 [P_MII_TX_FLOW_CTRL] = BIT(5), 409 [P_MII_RX_FLOW_CTRL] = BIT(3), 410 }; 411 412 static const u8 lan937x_shifts[] = { 413 [ALU_STAT_INDEX] = 8, 414 }; 415 416 static const struct regmap_range ksz8563_valid_regs[] = { 417 regmap_reg_range(0x0000, 0x0003), 418 regmap_reg_range(0x0006, 0x0006), 419 regmap_reg_range(0x000f, 0x001f), 420 regmap_reg_range(0x0100, 0x0100), 421 regmap_reg_range(0x0104, 0x0107), 422 regmap_reg_range(0x010d, 0x010d), 423 regmap_reg_range(0x0110, 0x0113), 424 regmap_reg_range(0x0120, 0x012b), 425 regmap_reg_range(0x0201, 0x0201), 426 regmap_reg_range(0x0210, 0x0213), 427 regmap_reg_range(0x0300, 0x0300), 428 regmap_reg_range(0x0302, 0x031b), 429 regmap_reg_range(0x0320, 0x032b), 430 regmap_reg_range(0x0330, 0x0336), 431 regmap_reg_range(0x0338, 0x033e), 432 regmap_reg_range(0x0340, 0x035f), 433 regmap_reg_range(0x0370, 0x0370), 434 regmap_reg_range(0x0378, 0x0378), 435 regmap_reg_range(0x037c, 0x037d), 436 regmap_reg_range(0x0390, 0x0393), 437 regmap_reg_range(0x0400, 0x040e), 438 regmap_reg_range(0x0410, 0x042f), 439 regmap_reg_range(0x0500, 0x0519), 440 regmap_reg_range(0x0520, 0x054b), 441 regmap_reg_range(0x0550, 0x05b3), 442 443 /* port 1 */ 444 regmap_reg_range(0x1000, 0x1001), 445 regmap_reg_range(0x1004, 0x100b), 446 regmap_reg_range(0x1013, 0x1013), 447 regmap_reg_range(0x1017, 0x1017), 448 regmap_reg_range(0x101b, 0x101b), 449 regmap_reg_range(0x101f, 0x1021), 450 regmap_reg_range(0x1030, 0x1030), 451 regmap_reg_range(0x1100, 0x1111), 452 regmap_reg_range(0x111a, 0x111d), 453 regmap_reg_range(0x1122, 0x1127), 454 regmap_reg_range(0x112a, 0x112b), 455 regmap_reg_range(0x1136, 0x1139), 456 regmap_reg_range(0x113e, 0x113f), 457 regmap_reg_range(0x1400, 0x1401), 458 regmap_reg_range(0x1403, 0x1403), 459 regmap_reg_range(0x1410, 0x1417), 460 regmap_reg_range(0x1420, 0x1423), 461 regmap_reg_range(0x1500, 0x1507), 462 regmap_reg_range(0x1600, 0x1612), 463 regmap_reg_range(0x1800, 0x180f), 464 regmap_reg_range(0x1900, 0x1907), 465 regmap_reg_range(0x1914, 0x191b), 466 regmap_reg_range(0x1a00, 0x1a03), 467 regmap_reg_range(0x1a04, 0x1a08), 468 regmap_reg_range(0x1b00, 0x1b01), 469 regmap_reg_range(0x1b04, 0x1b04), 470 regmap_reg_range(0x1c00, 0x1c05), 471 regmap_reg_range(0x1c08, 0x1c1b), 472 473 /* port 2 */ 474 regmap_reg_range(0x2000, 0x2001), 475 regmap_reg_range(0x2004, 0x200b), 476 regmap_reg_range(0x2013, 0x2013), 477 regmap_reg_range(0x2017, 0x2017), 478 regmap_reg_range(0x201b, 0x201b), 479 regmap_reg_range(0x201f, 0x2021), 480 regmap_reg_range(0x2030, 0x2030), 481 regmap_reg_range(0x2100, 0x2111), 482 regmap_reg_range(0x211a, 0x211d), 483 regmap_reg_range(0x2122, 0x2127), 484 regmap_reg_range(0x212a, 0x212b), 485 regmap_reg_range(0x2136, 0x2139), 486 regmap_reg_range(0x213e, 0x213f), 487 regmap_reg_range(0x2400, 0x2401), 488 regmap_reg_range(0x2403, 0x2403), 489 regmap_reg_range(0x2410, 0x2417), 490 regmap_reg_range(0x2420, 0x2423), 491 regmap_reg_range(0x2500, 0x2507), 492 regmap_reg_range(0x2600, 0x2612), 493 regmap_reg_range(0x2800, 0x280f), 494 regmap_reg_range(0x2900, 0x2907), 495 regmap_reg_range(0x2914, 0x291b), 496 regmap_reg_range(0x2a00, 0x2a03), 497 regmap_reg_range(0x2a04, 0x2a08), 498 regmap_reg_range(0x2b00, 0x2b01), 499 regmap_reg_range(0x2b04, 0x2b04), 500 regmap_reg_range(0x2c00, 0x2c05), 501 regmap_reg_range(0x2c08, 0x2c1b), 502 503 /* port 3 */ 504 regmap_reg_range(0x3000, 0x3001), 505 regmap_reg_range(0x3004, 0x300b), 506 regmap_reg_range(0x3013, 0x3013), 507 regmap_reg_range(0x3017, 0x3017), 508 regmap_reg_range(0x301b, 0x301b), 509 regmap_reg_range(0x301f, 0x3021), 510 regmap_reg_range(0x3030, 0x3030), 511 regmap_reg_range(0x3300, 0x3301), 512 regmap_reg_range(0x3303, 0x3303), 513 regmap_reg_range(0x3400, 0x3401), 514 regmap_reg_range(0x3403, 0x3403), 515 regmap_reg_range(0x3410, 0x3417), 516 regmap_reg_range(0x3420, 0x3423), 517 regmap_reg_range(0x3500, 0x3507), 518 regmap_reg_range(0x3600, 0x3612), 519 regmap_reg_range(0x3800, 0x380f), 520 regmap_reg_range(0x3900, 0x3907), 521 regmap_reg_range(0x3914, 0x391b), 522 regmap_reg_range(0x3a00, 0x3a03), 523 regmap_reg_range(0x3a04, 0x3a08), 524 regmap_reg_range(0x3b00, 0x3b01), 525 regmap_reg_range(0x3b04, 0x3b04), 526 regmap_reg_range(0x3c00, 0x3c05), 527 regmap_reg_range(0x3c08, 0x3c1b), 528 }; 529 530 static const struct regmap_access_table ksz8563_register_set = { 531 .yes_ranges = ksz8563_valid_regs, 532 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 533 }; 534 535 static const struct regmap_range ksz9477_valid_regs[] = { 536 regmap_reg_range(0x0000, 0x0003), 537 regmap_reg_range(0x0006, 0x0006), 538 regmap_reg_range(0x0010, 0x001f), 539 regmap_reg_range(0x0100, 0x0100), 540 regmap_reg_range(0x0103, 0x0107), 541 regmap_reg_range(0x010d, 0x010d), 542 regmap_reg_range(0x0110, 0x0113), 543 regmap_reg_range(0x0120, 0x012b), 544 regmap_reg_range(0x0201, 0x0201), 545 regmap_reg_range(0x0210, 0x0213), 546 regmap_reg_range(0x0300, 0x0300), 547 regmap_reg_range(0x0302, 0x031b), 548 regmap_reg_range(0x0320, 0x032b), 549 regmap_reg_range(0x0330, 0x0336), 550 regmap_reg_range(0x0338, 0x033e), 551 regmap_reg_range(0x0340, 0x035f), 552 regmap_reg_range(0x0370, 0x0370), 553 regmap_reg_range(0x0378, 0x0378), 554 regmap_reg_range(0x037c, 0x037d), 555 regmap_reg_range(0x0390, 0x0393), 556 regmap_reg_range(0x0400, 0x040e), 557 regmap_reg_range(0x0410, 0x042f), 558 regmap_reg_range(0x0444, 0x044b), 559 regmap_reg_range(0x0450, 0x046f), 560 regmap_reg_range(0x0500, 0x0519), 561 regmap_reg_range(0x0520, 0x054b), 562 regmap_reg_range(0x0550, 0x05b3), 563 regmap_reg_range(0x0604, 0x060b), 564 regmap_reg_range(0x0610, 0x0612), 565 regmap_reg_range(0x0614, 0x062c), 566 regmap_reg_range(0x0640, 0x0645), 567 regmap_reg_range(0x0648, 0x064d), 568 569 /* port 1 */ 570 regmap_reg_range(0x1000, 0x1001), 571 regmap_reg_range(0x1013, 0x1013), 572 regmap_reg_range(0x1017, 0x1017), 573 regmap_reg_range(0x101b, 0x101b), 574 regmap_reg_range(0x101f, 0x1020), 575 regmap_reg_range(0x1030, 0x1030), 576 regmap_reg_range(0x1100, 0x1115), 577 regmap_reg_range(0x111a, 0x111f), 578 regmap_reg_range(0x1122, 0x1127), 579 regmap_reg_range(0x112a, 0x112b), 580 regmap_reg_range(0x1136, 0x1139), 581 regmap_reg_range(0x113e, 0x113f), 582 regmap_reg_range(0x1400, 0x1401), 583 regmap_reg_range(0x1403, 0x1403), 584 regmap_reg_range(0x1410, 0x1417), 585 regmap_reg_range(0x1420, 0x1423), 586 regmap_reg_range(0x1500, 0x1507), 587 regmap_reg_range(0x1600, 0x1613), 588 regmap_reg_range(0x1800, 0x180f), 589 regmap_reg_range(0x1820, 0x1827), 590 regmap_reg_range(0x1830, 0x1837), 591 regmap_reg_range(0x1840, 0x184b), 592 regmap_reg_range(0x1900, 0x1907), 593 regmap_reg_range(0x1914, 0x191b), 594 regmap_reg_range(0x1920, 0x1920), 595 regmap_reg_range(0x1923, 0x1927), 596 regmap_reg_range(0x1a00, 0x1a03), 597 regmap_reg_range(0x1a04, 0x1a07), 598 regmap_reg_range(0x1b00, 0x1b01), 599 regmap_reg_range(0x1b04, 0x1b04), 600 regmap_reg_range(0x1c00, 0x1c05), 601 regmap_reg_range(0x1c08, 0x1c1b), 602 603 /* port 2 */ 604 regmap_reg_range(0x2000, 0x2001), 605 regmap_reg_range(0x2013, 0x2013), 606 regmap_reg_range(0x2017, 0x2017), 607 regmap_reg_range(0x201b, 0x201b), 608 regmap_reg_range(0x201f, 0x2020), 609 regmap_reg_range(0x2030, 0x2030), 610 regmap_reg_range(0x2100, 0x2115), 611 regmap_reg_range(0x211a, 0x211f), 612 regmap_reg_range(0x2122, 0x2127), 613 regmap_reg_range(0x212a, 0x212b), 614 regmap_reg_range(0x2136, 0x2139), 615 regmap_reg_range(0x213e, 0x213f), 616 regmap_reg_range(0x2400, 0x2401), 617 regmap_reg_range(0x2403, 0x2403), 618 regmap_reg_range(0x2410, 0x2417), 619 regmap_reg_range(0x2420, 0x2423), 620 regmap_reg_range(0x2500, 0x2507), 621 regmap_reg_range(0x2600, 0x2613), 622 regmap_reg_range(0x2800, 0x280f), 623 regmap_reg_range(0x2820, 0x2827), 624 regmap_reg_range(0x2830, 0x2837), 625 regmap_reg_range(0x2840, 0x284b), 626 regmap_reg_range(0x2900, 0x2907), 627 regmap_reg_range(0x2914, 0x291b), 628 regmap_reg_range(0x2920, 0x2920), 629 regmap_reg_range(0x2923, 0x2927), 630 regmap_reg_range(0x2a00, 0x2a03), 631 regmap_reg_range(0x2a04, 0x2a07), 632 regmap_reg_range(0x2b00, 0x2b01), 633 regmap_reg_range(0x2b04, 0x2b04), 634 regmap_reg_range(0x2c00, 0x2c05), 635 regmap_reg_range(0x2c08, 0x2c1b), 636 637 /* port 3 */ 638 regmap_reg_range(0x3000, 0x3001), 639 regmap_reg_range(0x3013, 0x3013), 640 regmap_reg_range(0x3017, 0x3017), 641 regmap_reg_range(0x301b, 0x301b), 642 regmap_reg_range(0x301f, 0x3020), 643 regmap_reg_range(0x3030, 0x3030), 644 regmap_reg_range(0x3100, 0x3115), 645 regmap_reg_range(0x311a, 0x311f), 646 regmap_reg_range(0x3122, 0x3127), 647 regmap_reg_range(0x312a, 0x312b), 648 regmap_reg_range(0x3136, 0x3139), 649 regmap_reg_range(0x313e, 0x313f), 650 regmap_reg_range(0x3400, 0x3401), 651 regmap_reg_range(0x3403, 0x3403), 652 regmap_reg_range(0x3410, 0x3417), 653 regmap_reg_range(0x3420, 0x3423), 654 regmap_reg_range(0x3500, 0x3507), 655 regmap_reg_range(0x3600, 0x3613), 656 regmap_reg_range(0x3800, 0x380f), 657 regmap_reg_range(0x3820, 0x3827), 658 regmap_reg_range(0x3830, 0x3837), 659 regmap_reg_range(0x3840, 0x384b), 660 regmap_reg_range(0x3900, 0x3907), 661 regmap_reg_range(0x3914, 0x391b), 662 regmap_reg_range(0x3920, 0x3920), 663 regmap_reg_range(0x3923, 0x3927), 664 regmap_reg_range(0x3a00, 0x3a03), 665 regmap_reg_range(0x3a04, 0x3a07), 666 regmap_reg_range(0x3b00, 0x3b01), 667 regmap_reg_range(0x3b04, 0x3b04), 668 regmap_reg_range(0x3c00, 0x3c05), 669 regmap_reg_range(0x3c08, 0x3c1b), 670 671 /* port 4 */ 672 regmap_reg_range(0x4000, 0x4001), 673 regmap_reg_range(0x4013, 0x4013), 674 regmap_reg_range(0x4017, 0x4017), 675 regmap_reg_range(0x401b, 0x401b), 676 regmap_reg_range(0x401f, 0x4020), 677 regmap_reg_range(0x4030, 0x4030), 678 regmap_reg_range(0x4100, 0x4115), 679 regmap_reg_range(0x411a, 0x411f), 680 regmap_reg_range(0x4122, 0x4127), 681 regmap_reg_range(0x412a, 0x412b), 682 regmap_reg_range(0x4136, 0x4139), 683 regmap_reg_range(0x413e, 0x413f), 684 regmap_reg_range(0x4400, 0x4401), 685 regmap_reg_range(0x4403, 0x4403), 686 regmap_reg_range(0x4410, 0x4417), 687 regmap_reg_range(0x4420, 0x4423), 688 regmap_reg_range(0x4500, 0x4507), 689 regmap_reg_range(0x4600, 0x4613), 690 regmap_reg_range(0x4800, 0x480f), 691 regmap_reg_range(0x4820, 0x4827), 692 regmap_reg_range(0x4830, 0x4837), 693 regmap_reg_range(0x4840, 0x484b), 694 regmap_reg_range(0x4900, 0x4907), 695 regmap_reg_range(0x4914, 0x491b), 696 regmap_reg_range(0x4920, 0x4920), 697 regmap_reg_range(0x4923, 0x4927), 698 regmap_reg_range(0x4a00, 0x4a03), 699 regmap_reg_range(0x4a04, 0x4a07), 700 regmap_reg_range(0x4b00, 0x4b01), 701 regmap_reg_range(0x4b04, 0x4b04), 702 regmap_reg_range(0x4c00, 0x4c05), 703 regmap_reg_range(0x4c08, 0x4c1b), 704 705 /* port 5 */ 706 regmap_reg_range(0x5000, 0x5001), 707 regmap_reg_range(0x5013, 0x5013), 708 regmap_reg_range(0x5017, 0x5017), 709 regmap_reg_range(0x501b, 0x501b), 710 regmap_reg_range(0x501f, 0x5020), 711 regmap_reg_range(0x5030, 0x5030), 712 regmap_reg_range(0x5100, 0x5115), 713 regmap_reg_range(0x511a, 0x511f), 714 regmap_reg_range(0x5122, 0x5127), 715 regmap_reg_range(0x512a, 0x512b), 716 regmap_reg_range(0x5136, 0x5139), 717 regmap_reg_range(0x513e, 0x513f), 718 regmap_reg_range(0x5400, 0x5401), 719 regmap_reg_range(0x5403, 0x5403), 720 regmap_reg_range(0x5410, 0x5417), 721 regmap_reg_range(0x5420, 0x5423), 722 regmap_reg_range(0x5500, 0x5507), 723 regmap_reg_range(0x5600, 0x5613), 724 regmap_reg_range(0x5800, 0x580f), 725 regmap_reg_range(0x5820, 0x5827), 726 regmap_reg_range(0x5830, 0x5837), 727 regmap_reg_range(0x5840, 0x584b), 728 regmap_reg_range(0x5900, 0x5907), 729 regmap_reg_range(0x5914, 0x591b), 730 regmap_reg_range(0x5920, 0x5920), 731 regmap_reg_range(0x5923, 0x5927), 732 regmap_reg_range(0x5a00, 0x5a03), 733 regmap_reg_range(0x5a04, 0x5a07), 734 regmap_reg_range(0x5b00, 0x5b01), 735 regmap_reg_range(0x5b04, 0x5b04), 736 regmap_reg_range(0x5c00, 0x5c05), 737 regmap_reg_range(0x5c08, 0x5c1b), 738 739 /* port 6 */ 740 regmap_reg_range(0x6000, 0x6001), 741 regmap_reg_range(0x6013, 0x6013), 742 regmap_reg_range(0x6017, 0x6017), 743 regmap_reg_range(0x601b, 0x601b), 744 regmap_reg_range(0x601f, 0x6020), 745 regmap_reg_range(0x6030, 0x6030), 746 regmap_reg_range(0x6300, 0x6301), 747 regmap_reg_range(0x6400, 0x6401), 748 regmap_reg_range(0x6403, 0x6403), 749 regmap_reg_range(0x6410, 0x6417), 750 regmap_reg_range(0x6420, 0x6423), 751 regmap_reg_range(0x6500, 0x6507), 752 regmap_reg_range(0x6600, 0x6613), 753 regmap_reg_range(0x6800, 0x680f), 754 regmap_reg_range(0x6820, 0x6827), 755 regmap_reg_range(0x6830, 0x6837), 756 regmap_reg_range(0x6840, 0x684b), 757 regmap_reg_range(0x6900, 0x6907), 758 regmap_reg_range(0x6914, 0x691b), 759 regmap_reg_range(0x6920, 0x6920), 760 regmap_reg_range(0x6923, 0x6927), 761 regmap_reg_range(0x6a00, 0x6a03), 762 regmap_reg_range(0x6a04, 0x6a07), 763 regmap_reg_range(0x6b00, 0x6b01), 764 regmap_reg_range(0x6b04, 0x6b04), 765 regmap_reg_range(0x6c00, 0x6c05), 766 regmap_reg_range(0x6c08, 0x6c1b), 767 768 /* port 7 */ 769 regmap_reg_range(0x7000, 0x7001), 770 regmap_reg_range(0x7013, 0x7013), 771 regmap_reg_range(0x7017, 0x7017), 772 regmap_reg_range(0x701b, 0x701b), 773 regmap_reg_range(0x701f, 0x7020), 774 regmap_reg_range(0x7030, 0x7030), 775 regmap_reg_range(0x7200, 0x7203), 776 regmap_reg_range(0x7206, 0x7207), 777 regmap_reg_range(0x7300, 0x7301), 778 regmap_reg_range(0x7400, 0x7401), 779 regmap_reg_range(0x7403, 0x7403), 780 regmap_reg_range(0x7410, 0x7417), 781 regmap_reg_range(0x7420, 0x7423), 782 regmap_reg_range(0x7500, 0x7507), 783 regmap_reg_range(0x7600, 0x7613), 784 regmap_reg_range(0x7800, 0x780f), 785 regmap_reg_range(0x7820, 0x7827), 786 regmap_reg_range(0x7830, 0x7837), 787 regmap_reg_range(0x7840, 0x784b), 788 regmap_reg_range(0x7900, 0x7907), 789 regmap_reg_range(0x7914, 0x791b), 790 regmap_reg_range(0x7920, 0x7920), 791 regmap_reg_range(0x7923, 0x7927), 792 regmap_reg_range(0x7a00, 0x7a03), 793 regmap_reg_range(0x7a04, 0x7a07), 794 regmap_reg_range(0x7b00, 0x7b01), 795 regmap_reg_range(0x7b04, 0x7b04), 796 regmap_reg_range(0x7c00, 0x7c05), 797 regmap_reg_range(0x7c08, 0x7c1b), 798 }; 799 800 static const struct regmap_access_table ksz9477_register_set = { 801 .yes_ranges = ksz9477_valid_regs, 802 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 803 }; 804 805 const struct ksz_chip_data ksz_switch_chips[] = { 806 [KSZ8563] = { 807 .chip_id = KSZ8563_CHIP_ID, 808 .dev_name = "KSZ8563", 809 .num_vlans = 4096, 810 .num_alus = 4096, 811 .num_statics = 16, 812 .cpu_ports = 0x07, /* can be configured as cpu port */ 813 .port_cnt = 3, /* total port count */ 814 .ops = &ksz9477_dev_ops, 815 .mib_names = ksz9477_mib_names, 816 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 817 .reg_mib_cnt = MIB_COUNTER_NUM, 818 .regs = ksz9477_regs, 819 .masks = ksz9477_masks, 820 .shifts = ksz9477_shifts, 821 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 822 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 823 .supports_mii = {false, false, true}, 824 .supports_rmii = {false, false, true}, 825 .supports_rgmii = {false, false, true}, 826 .internal_phy = {true, true, false}, 827 .gbit_capable = {false, false, true}, 828 .wr_table = &ksz8563_register_set, 829 .rd_table = &ksz8563_register_set, 830 }, 831 832 [KSZ8795] = { 833 .chip_id = KSZ8795_CHIP_ID, 834 .dev_name = "KSZ8795", 835 .num_vlans = 4096, 836 .num_alus = 0, 837 .num_statics = 8, 838 .cpu_ports = 0x10, /* can be configured as cpu port */ 839 .port_cnt = 5, /* total cpu and user ports */ 840 .ops = &ksz8_dev_ops, 841 .ksz87xx_eee_link_erratum = true, 842 .mib_names = ksz9477_mib_names, 843 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 844 .reg_mib_cnt = MIB_COUNTER_NUM, 845 .regs = ksz8795_regs, 846 .masks = ksz8795_masks, 847 .shifts = ksz8795_shifts, 848 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 849 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 850 .supports_mii = {false, false, false, false, true}, 851 .supports_rmii = {false, false, false, false, true}, 852 .supports_rgmii = {false, false, false, false, true}, 853 .internal_phy = {true, true, true, true, false}, 854 }, 855 856 [KSZ8794] = { 857 /* WARNING 858 * ======= 859 * KSZ8794 is similar to KSZ8795, except the port map 860 * contains a gap between external and CPU ports, the 861 * port map is NOT continuous. The per-port register 862 * map is shifted accordingly too, i.e. registers at 863 * offset 0x40 are NOT used on KSZ8794 and they ARE 864 * used on KSZ8795 for external port 3. 865 * external cpu 866 * KSZ8794 0,1,2 4 867 * KSZ8795 0,1,2,3 4 868 * KSZ8765 0,1,2,3 4 869 * port_cnt is configured as 5, even though it is 4 870 */ 871 .chip_id = KSZ8794_CHIP_ID, 872 .dev_name = "KSZ8794", 873 .num_vlans = 4096, 874 .num_alus = 0, 875 .num_statics = 8, 876 .cpu_ports = 0x10, /* can be configured as cpu port */ 877 .port_cnt = 5, /* total cpu and user ports */ 878 .ops = &ksz8_dev_ops, 879 .ksz87xx_eee_link_erratum = true, 880 .mib_names = ksz9477_mib_names, 881 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 882 .reg_mib_cnt = MIB_COUNTER_NUM, 883 .regs = ksz8795_regs, 884 .masks = ksz8795_masks, 885 .shifts = ksz8795_shifts, 886 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 887 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 888 .supports_mii = {false, false, false, false, true}, 889 .supports_rmii = {false, false, false, false, true}, 890 .supports_rgmii = {false, false, false, false, true}, 891 .internal_phy = {true, true, true, false, false}, 892 }, 893 894 [KSZ8765] = { 895 .chip_id = KSZ8765_CHIP_ID, 896 .dev_name = "KSZ8765", 897 .num_vlans = 4096, 898 .num_alus = 0, 899 .num_statics = 8, 900 .cpu_ports = 0x10, /* can be configured as cpu port */ 901 .port_cnt = 5, /* total cpu and user ports */ 902 .ops = &ksz8_dev_ops, 903 .ksz87xx_eee_link_erratum = true, 904 .mib_names = ksz9477_mib_names, 905 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 906 .reg_mib_cnt = MIB_COUNTER_NUM, 907 .regs = ksz8795_regs, 908 .masks = ksz8795_masks, 909 .shifts = ksz8795_shifts, 910 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 911 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 912 .supports_mii = {false, false, false, false, true}, 913 .supports_rmii = {false, false, false, false, true}, 914 .supports_rgmii = {false, false, false, false, true}, 915 .internal_phy = {true, true, true, true, false}, 916 }, 917 918 [KSZ8830] = { 919 .chip_id = KSZ8830_CHIP_ID, 920 .dev_name = "KSZ8863/KSZ8873", 921 .num_vlans = 16, 922 .num_alus = 0, 923 .num_statics = 8, 924 .cpu_ports = 0x4, /* can be configured as cpu port */ 925 .port_cnt = 3, 926 .ops = &ksz8_dev_ops, 927 .mib_names = ksz88xx_mib_names, 928 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 929 .reg_mib_cnt = MIB_COUNTER_NUM, 930 .regs = ksz8863_regs, 931 .masks = ksz8863_masks, 932 .shifts = ksz8863_shifts, 933 .supports_mii = {false, false, true}, 934 .supports_rmii = {false, false, true}, 935 .internal_phy = {true, true, false}, 936 }, 937 938 [KSZ9477] = { 939 .chip_id = KSZ9477_CHIP_ID, 940 .dev_name = "KSZ9477", 941 .num_vlans = 4096, 942 .num_alus = 4096, 943 .num_statics = 16, 944 .cpu_ports = 0x7F, /* can be configured as cpu port */ 945 .port_cnt = 7, /* total physical port count */ 946 .ops = &ksz9477_dev_ops, 947 .phy_errata_9477 = true, 948 .mib_names = ksz9477_mib_names, 949 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 950 .reg_mib_cnt = MIB_COUNTER_NUM, 951 .regs = ksz9477_regs, 952 .masks = ksz9477_masks, 953 .shifts = ksz9477_shifts, 954 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 955 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 956 .supports_mii = {false, false, false, false, 957 false, true, false}, 958 .supports_rmii = {false, false, false, false, 959 false, true, false}, 960 .supports_rgmii = {false, false, false, false, 961 false, true, false}, 962 .internal_phy = {true, true, true, true, 963 true, false, false}, 964 .gbit_capable = {true, true, true, true, true, true, true}, 965 .wr_table = &ksz9477_register_set, 966 .rd_table = &ksz9477_register_set, 967 }, 968 969 [KSZ9897] = { 970 .chip_id = KSZ9897_CHIP_ID, 971 .dev_name = "KSZ9897", 972 .num_vlans = 4096, 973 .num_alus = 4096, 974 .num_statics = 16, 975 .cpu_ports = 0x7F, /* can be configured as cpu port */ 976 .port_cnt = 7, /* total physical port count */ 977 .ops = &ksz9477_dev_ops, 978 .phy_errata_9477 = true, 979 .mib_names = ksz9477_mib_names, 980 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 981 .reg_mib_cnt = MIB_COUNTER_NUM, 982 .regs = ksz9477_regs, 983 .masks = ksz9477_masks, 984 .shifts = ksz9477_shifts, 985 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 986 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 987 .supports_mii = {false, false, false, false, 988 false, true, true}, 989 .supports_rmii = {false, false, false, false, 990 false, true, true}, 991 .supports_rgmii = {false, false, false, false, 992 false, true, true}, 993 .internal_phy = {true, true, true, true, 994 true, false, false}, 995 .gbit_capable = {true, true, true, true, true, true, true}, 996 }, 997 998 [KSZ9893] = { 999 .chip_id = KSZ9893_CHIP_ID, 1000 .dev_name = "KSZ9893", 1001 .num_vlans = 4096, 1002 .num_alus = 4096, 1003 .num_statics = 16, 1004 .cpu_ports = 0x07, /* can be configured as cpu port */ 1005 .port_cnt = 3, /* total port count */ 1006 .ops = &ksz9477_dev_ops, 1007 .mib_names = ksz9477_mib_names, 1008 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1009 .reg_mib_cnt = MIB_COUNTER_NUM, 1010 .regs = ksz9477_regs, 1011 .masks = ksz9477_masks, 1012 .shifts = ksz9477_shifts, 1013 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1014 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1015 .supports_mii = {false, false, true}, 1016 .supports_rmii = {false, false, true}, 1017 .supports_rgmii = {false, false, true}, 1018 .internal_phy = {true, true, false}, 1019 .gbit_capable = {true, true, true}, 1020 }, 1021 1022 [KSZ9567] = { 1023 .chip_id = KSZ9567_CHIP_ID, 1024 .dev_name = "KSZ9567", 1025 .num_vlans = 4096, 1026 .num_alus = 4096, 1027 .num_statics = 16, 1028 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1029 .port_cnt = 7, /* total physical port count */ 1030 .ops = &ksz9477_dev_ops, 1031 .phy_errata_9477 = true, 1032 .mib_names = ksz9477_mib_names, 1033 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1034 .reg_mib_cnt = MIB_COUNTER_NUM, 1035 .regs = ksz9477_regs, 1036 .masks = ksz9477_masks, 1037 .shifts = ksz9477_shifts, 1038 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1039 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1040 .supports_mii = {false, false, false, false, 1041 false, true, true}, 1042 .supports_rmii = {false, false, false, false, 1043 false, true, true}, 1044 .supports_rgmii = {false, false, false, false, 1045 false, true, true}, 1046 .internal_phy = {true, true, true, true, 1047 true, false, false}, 1048 .gbit_capable = {true, true, true, true, true, true, true}, 1049 }, 1050 1051 [LAN9370] = { 1052 .chip_id = LAN9370_CHIP_ID, 1053 .dev_name = "LAN9370", 1054 .num_vlans = 4096, 1055 .num_alus = 1024, 1056 .num_statics = 256, 1057 .cpu_ports = 0x10, /* can be configured as cpu port */ 1058 .port_cnt = 5, /* total physical port count */ 1059 .ops = &lan937x_dev_ops, 1060 .mib_names = ksz9477_mib_names, 1061 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1062 .reg_mib_cnt = MIB_COUNTER_NUM, 1063 .regs = ksz9477_regs, 1064 .masks = lan937x_masks, 1065 .shifts = lan937x_shifts, 1066 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1067 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1068 .supports_mii = {false, false, false, false, true}, 1069 .supports_rmii = {false, false, false, false, true}, 1070 .supports_rgmii = {false, false, false, false, true}, 1071 .internal_phy = {true, true, true, true, false}, 1072 }, 1073 1074 [LAN9371] = { 1075 .chip_id = LAN9371_CHIP_ID, 1076 .dev_name = "LAN9371", 1077 .num_vlans = 4096, 1078 .num_alus = 1024, 1079 .num_statics = 256, 1080 .cpu_ports = 0x30, /* can be configured as cpu port */ 1081 .port_cnt = 6, /* total physical port count */ 1082 .ops = &lan937x_dev_ops, 1083 .mib_names = ksz9477_mib_names, 1084 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1085 .reg_mib_cnt = MIB_COUNTER_NUM, 1086 .regs = ksz9477_regs, 1087 .masks = lan937x_masks, 1088 .shifts = lan937x_shifts, 1089 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1090 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1091 .supports_mii = {false, false, false, false, true, true}, 1092 .supports_rmii = {false, false, false, false, true, true}, 1093 .supports_rgmii = {false, false, false, false, true, true}, 1094 .internal_phy = {true, true, true, true, false, false}, 1095 }, 1096 1097 [LAN9372] = { 1098 .chip_id = LAN9372_CHIP_ID, 1099 .dev_name = "LAN9372", 1100 .num_vlans = 4096, 1101 .num_alus = 1024, 1102 .num_statics = 256, 1103 .cpu_ports = 0x30, /* can be configured as cpu port */ 1104 .port_cnt = 8, /* total physical port count */ 1105 .ops = &lan937x_dev_ops, 1106 .mib_names = ksz9477_mib_names, 1107 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1108 .reg_mib_cnt = MIB_COUNTER_NUM, 1109 .regs = ksz9477_regs, 1110 .masks = lan937x_masks, 1111 .shifts = lan937x_shifts, 1112 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1113 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1114 .supports_mii = {false, false, false, false, 1115 true, true, false, false}, 1116 .supports_rmii = {false, false, false, false, 1117 true, true, false, false}, 1118 .supports_rgmii = {false, false, false, false, 1119 true, true, false, false}, 1120 .internal_phy = {true, true, true, true, 1121 false, false, true, true}, 1122 }, 1123 1124 [LAN9373] = { 1125 .chip_id = LAN9373_CHIP_ID, 1126 .dev_name = "LAN9373", 1127 .num_vlans = 4096, 1128 .num_alus = 1024, 1129 .num_statics = 256, 1130 .cpu_ports = 0x38, /* can be configured as cpu port */ 1131 .port_cnt = 5, /* total physical port count */ 1132 .ops = &lan937x_dev_ops, 1133 .mib_names = ksz9477_mib_names, 1134 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1135 .reg_mib_cnt = MIB_COUNTER_NUM, 1136 .regs = ksz9477_regs, 1137 .masks = lan937x_masks, 1138 .shifts = lan937x_shifts, 1139 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1140 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1141 .supports_mii = {false, false, false, false, 1142 true, true, false, false}, 1143 .supports_rmii = {false, false, false, false, 1144 true, true, false, false}, 1145 .supports_rgmii = {false, false, false, false, 1146 true, true, false, false}, 1147 .internal_phy = {true, true, true, false, 1148 false, false, true, true}, 1149 }, 1150 1151 [LAN9374] = { 1152 .chip_id = LAN9374_CHIP_ID, 1153 .dev_name = "LAN9374", 1154 .num_vlans = 4096, 1155 .num_alus = 1024, 1156 .num_statics = 256, 1157 .cpu_ports = 0x30, /* can be configured as cpu port */ 1158 .port_cnt = 8, /* total physical port count */ 1159 .ops = &lan937x_dev_ops, 1160 .mib_names = ksz9477_mib_names, 1161 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1162 .reg_mib_cnt = MIB_COUNTER_NUM, 1163 .regs = ksz9477_regs, 1164 .masks = lan937x_masks, 1165 .shifts = lan937x_shifts, 1166 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1167 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1168 .supports_mii = {false, false, false, false, 1169 true, true, false, false}, 1170 .supports_rmii = {false, false, false, false, 1171 true, true, false, false}, 1172 .supports_rgmii = {false, false, false, false, 1173 true, true, false, false}, 1174 .internal_phy = {true, true, true, true, 1175 false, false, true, true}, 1176 }, 1177 }; 1178 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1179 1180 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1181 { 1182 int i; 1183 1184 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1185 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1186 1187 if (chip->chip_id == prod_num) 1188 return chip; 1189 } 1190 1191 return NULL; 1192 } 1193 1194 static int ksz_check_device_id(struct ksz_device *dev) 1195 { 1196 const struct ksz_chip_data *dt_chip_data; 1197 1198 dt_chip_data = of_device_get_match_data(dev->dev); 1199 1200 /* Check for Device Tree and Chip ID */ 1201 if (dt_chip_data->chip_id != dev->chip_id) { 1202 dev_err(dev->dev, 1203 "Device tree specifies chip %s but found %s, please fix it!\n", 1204 dt_chip_data->dev_name, dev->info->dev_name); 1205 return -ENODEV; 1206 } 1207 1208 return 0; 1209 } 1210 1211 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1212 struct phylink_config *config) 1213 { 1214 struct ksz_device *dev = ds->priv; 1215 1216 config->legacy_pre_march2020 = false; 1217 1218 if (dev->info->supports_mii[port]) 1219 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1220 1221 if (dev->info->supports_rmii[port]) 1222 __set_bit(PHY_INTERFACE_MODE_RMII, 1223 config->supported_interfaces); 1224 1225 if (dev->info->supports_rgmii[port]) 1226 phy_interface_set_rgmii(config->supported_interfaces); 1227 1228 if (dev->info->internal_phy[port]) { 1229 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1230 config->supported_interfaces); 1231 /* Compatibility for phylib's default interface type when the 1232 * phy-mode property is absent 1233 */ 1234 __set_bit(PHY_INTERFACE_MODE_GMII, 1235 config->supported_interfaces); 1236 } 1237 1238 if (dev->dev_ops->get_caps) 1239 dev->dev_ops->get_caps(dev, port, config); 1240 } 1241 1242 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 1243 { 1244 struct ethtool_pause_stats *pstats; 1245 struct rtnl_link_stats64 *stats; 1246 struct ksz_stats_raw *raw; 1247 struct ksz_port_mib *mib; 1248 1249 mib = &dev->ports[port].mib; 1250 stats = &mib->stats64; 1251 pstats = &mib->pause_stats; 1252 raw = (struct ksz_stats_raw *)mib->counters; 1253 1254 spin_lock(&mib->stats64_lock); 1255 1256 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1257 raw->rx_pause; 1258 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1259 raw->tx_pause; 1260 1261 /* HW counters are counting bytes + FCS which is not acceptable 1262 * for rtnl_link_stats64 interface 1263 */ 1264 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 1265 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 1266 1267 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1268 raw->rx_oversize; 1269 1270 stats->rx_crc_errors = raw->rx_crc_err; 1271 stats->rx_frame_errors = raw->rx_align_err; 1272 stats->rx_dropped = raw->rx_discards; 1273 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1274 stats->rx_frame_errors + stats->rx_dropped; 1275 1276 stats->tx_window_errors = raw->tx_late_col; 1277 stats->tx_fifo_errors = raw->tx_discards; 1278 stats->tx_aborted_errors = raw->tx_exc_col; 1279 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1280 stats->tx_aborted_errors; 1281 1282 stats->multicast = raw->rx_mcast; 1283 stats->collisions = raw->tx_total_col; 1284 1285 pstats->tx_pause_frames = raw->tx_pause; 1286 pstats->rx_pause_frames = raw->rx_pause; 1287 1288 spin_unlock(&mib->stats64_lock); 1289 } 1290 1291 static void ksz_get_stats64(struct dsa_switch *ds, int port, 1292 struct rtnl_link_stats64 *s) 1293 { 1294 struct ksz_device *dev = ds->priv; 1295 struct ksz_port_mib *mib; 1296 1297 mib = &dev->ports[port].mib; 1298 1299 spin_lock(&mib->stats64_lock); 1300 memcpy(s, &mib->stats64, sizeof(*s)); 1301 spin_unlock(&mib->stats64_lock); 1302 } 1303 1304 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 1305 struct ethtool_pause_stats *pause_stats) 1306 { 1307 struct ksz_device *dev = ds->priv; 1308 struct ksz_port_mib *mib; 1309 1310 mib = &dev->ports[port].mib; 1311 1312 spin_lock(&mib->stats64_lock); 1313 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 1314 spin_unlock(&mib->stats64_lock); 1315 } 1316 1317 static void ksz_get_strings(struct dsa_switch *ds, int port, 1318 u32 stringset, uint8_t *buf) 1319 { 1320 struct ksz_device *dev = ds->priv; 1321 int i; 1322 1323 if (stringset != ETH_SS_STATS) 1324 return; 1325 1326 for (i = 0; i < dev->info->mib_cnt; i++) { 1327 memcpy(buf + i * ETH_GSTRING_LEN, 1328 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 1329 } 1330 } 1331 1332 static void ksz_update_port_member(struct ksz_device *dev, int port) 1333 { 1334 struct ksz_port *p = &dev->ports[port]; 1335 struct dsa_switch *ds = dev->ds; 1336 u8 port_member = 0, cpu_port; 1337 const struct dsa_port *dp; 1338 int i, j; 1339 1340 if (!dsa_is_user_port(ds, port)) 1341 return; 1342 1343 dp = dsa_to_port(ds, port); 1344 cpu_port = BIT(dsa_upstream_port(ds, port)); 1345 1346 for (i = 0; i < ds->num_ports; i++) { 1347 const struct dsa_port *other_dp = dsa_to_port(ds, i); 1348 struct ksz_port *other_p = &dev->ports[i]; 1349 u8 val = 0; 1350 1351 if (!dsa_is_user_port(ds, i)) 1352 continue; 1353 if (port == i) 1354 continue; 1355 if (!dsa_port_bridge_same(dp, other_dp)) 1356 continue; 1357 if (other_p->stp_state != BR_STATE_FORWARDING) 1358 continue; 1359 1360 if (p->stp_state == BR_STATE_FORWARDING) { 1361 val |= BIT(port); 1362 port_member |= BIT(i); 1363 } 1364 1365 /* Retain port [i]'s relationship to other ports than [port] */ 1366 for (j = 0; j < ds->num_ports; j++) { 1367 const struct dsa_port *third_dp; 1368 struct ksz_port *third_p; 1369 1370 if (j == i) 1371 continue; 1372 if (j == port) 1373 continue; 1374 if (!dsa_is_user_port(ds, j)) 1375 continue; 1376 third_p = &dev->ports[j]; 1377 if (third_p->stp_state != BR_STATE_FORWARDING) 1378 continue; 1379 third_dp = dsa_to_port(ds, j); 1380 if (dsa_port_bridge_same(other_dp, third_dp)) 1381 val |= BIT(j); 1382 } 1383 1384 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 1385 } 1386 1387 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 1388 } 1389 1390 static int ksz_setup(struct dsa_switch *ds) 1391 { 1392 struct ksz_device *dev = ds->priv; 1393 struct ksz_port *p; 1394 const u16 *regs; 1395 int ret; 1396 1397 regs = dev->info->regs; 1398 1399 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1400 dev->info->num_vlans, GFP_KERNEL); 1401 if (!dev->vlan_cache) 1402 return -ENOMEM; 1403 1404 ret = dev->dev_ops->reset(dev); 1405 if (ret) { 1406 dev_err(ds->dev, "failed to reset switch\n"); 1407 return ret; 1408 } 1409 1410 /* set broadcast storm protection 10% rate */ 1411 regmap_update_bits(dev->regmap[1], regs[S_BROADCAST_CTRL], 1412 BROADCAST_STORM_RATE, 1413 (BROADCAST_STORM_VALUE * 1414 BROADCAST_STORM_PROT_RATE) / 100); 1415 1416 dev->dev_ops->config_cpu_port(ds); 1417 1418 dev->dev_ops->enable_stp_addr(dev); 1419 1420 regmap_update_bits(dev->regmap[0], regs[S_MULTICAST_CTRL], 1421 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 1422 1423 ksz_init_mib_timer(dev); 1424 1425 ds->configure_vlan_while_not_filtering = false; 1426 1427 if (dev->dev_ops->setup) { 1428 ret = dev->dev_ops->setup(ds); 1429 if (ret) 1430 return ret; 1431 } 1432 1433 /* Start with learning disabled on standalone user ports, and enabled 1434 * on the CPU port. In lack of other finer mechanisms, learning on the 1435 * CPU port will avoid flooding bridge local addresses on the network 1436 * in some cases. 1437 */ 1438 p = &dev->ports[dev->cpu_port]; 1439 p->learning = true; 1440 1441 /* start switch */ 1442 regmap_update_bits(dev->regmap[0], regs[S_START_CTRL], 1443 SW_START, SW_START); 1444 1445 return 0; 1446 } 1447 1448 static void ksz_teardown(struct dsa_switch *ds) 1449 { 1450 struct ksz_device *dev = ds->priv; 1451 1452 if (dev->dev_ops->teardown) 1453 dev->dev_ops->teardown(ds); 1454 } 1455 1456 static void port_r_cnt(struct ksz_device *dev, int port) 1457 { 1458 struct ksz_port_mib *mib = &dev->ports[port].mib; 1459 u64 *dropped; 1460 1461 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 1462 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 1463 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 1464 &mib->counters[mib->cnt_ptr]); 1465 ++mib->cnt_ptr; 1466 } 1467 1468 /* last one in storage */ 1469 dropped = &mib->counters[dev->info->mib_cnt]; 1470 1471 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 1472 while (mib->cnt_ptr < dev->info->mib_cnt) { 1473 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 1474 dropped, &mib->counters[mib->cnt_ptr]); 1475 ++mib->cnt_ptr; 1476 } 1477 mib->cnt_ptr = 0; 1478 } 1479 1480 static void ksz_mib_read_work(struct work_struct *work) 1481 { 1482 struct ksz_device *dev = container_of(work, struct ksz_device, 1483 mib_read.work); 1484 struct ksz_port_mib *mib; 1485 struct ksz_port *p; 1486 int i; 1487 1488 for (i = 0; i < dev->info->port_cnt; i++) { 1489 if (dsa_is_unused_port(dev->ds, i)) 1490 continue; 1491 1492 p = &dev->ports[i]; 1493 mib = &p->mib; 1494 mutex_lock(&mib->cnt_mutex); 1495 1496 /* Only read MIB counters when the port is told to do. 1497 * If not, read only dropped counters when link is not up. 1498 */ 1499 if (!p->read) { 1500 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 1501 1502 if (!netif_carrier_ok(dp->slave)) 1503 mib->cnt_ptr = dev->info->reg_mib_cnt; 1504 } 1505 port_r_cnt(dev, i); 1506 p->read = false; 1507 1508 if (dev->dev_ops->r_mib_stat64) 1509 dev->dev_ops->r_mib_stat64(dev, i); 1510 1511 mutex_unlock(&mib->cnt_mutex); 1512 } 1513 1514 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 1515 } 1516 1517 void ksz_init_mib_timer(struct ksz_device *dev) 1518 { 1519 int i; 1520 1521 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 1522 1523 for (i = 0; i < dev->info->port_cnt; i++) { 1524 struct ksz_port_mib *mib = &dev->ports[i].mib; 1525 1526 dev->dev_ops->port_init_cnt(dev, i); 1527 1528 mib->cnt_ptr = 0; 1529 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 1530 } 1531 } 1532 1533 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 1534 { 1535 struct ksz_device *dev = ds->priv; 1536 u16 val = 0xffff; 1537 int ret; 1538 1539 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 1540 if (ret) 1541 return ret; 1542 1543 return val; 1544 } 1545 1546 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 1547 { 1548 struct ksz_device *dev = ds->priv; 1549 int ret; 1550 1551 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 1552 if (ret) 1553 return ret; 1554 1555 return 0; 1556 } 1557 1558 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 1559 { 1560 struct ksz_device *dev = ds->priv; 1561 1562 if (dev->chip_id == KSZ8830_CHIP_ID) { 1563 /* Silicon Errata Sheet (DS80000830A): 1564 * Port 1 does not work with LinkMD Cable-Testing. 1565 * Port 1 does not respond to received PAUSE control frames. 1566 */ 1567 if (!port) 1568 return MICREL_KSZ8_P1_ERRATA; 1569 } 1570 1571 return 0; 1572 } 1573 1574 static void ksz_mac_link_down(struct dsa_switch *ds, int port, 1575 unsigned int mode, phy_interface_t interface) 1576 { 1577 struct ksz_device *dev = ds->priv; 1578 struct ksz_port *p = &dev->ports[port]; 1579 1580 /* Read all MIB counters when the link is going down. */ 1581 p->read = true; 1582 /* timer started */ 1583 if (dev->mib_read_interval) 1584 schedule_delayed_work(&dev->mib_read, 0); 1585 } 1586 1587 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 1588 { 1589 struct ksz_device *dev = ds->priv; 1590 1591 if (sset != ETH_SS_STATS) 1592 return 0; 1593 1594 return dev->info->mib_cnt; 1595 } 1596 1597 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 1598 uint64_t *buf) 1599 { 1600 const struct dsa_port *dp = dsa_to_port(ds, port); 1601 struct ksz_device *dev = ds->priv; 1602 struct ksz_port_mib *mib; 1603 1604 mib = &dev->ports[port].mib; 1605 mutex_lock(&mib->cnt_mutex); 1606 1607 /* Only read dropped counters if no link. */ 1608 if (!netif_carrier_ok(dp->slave)) 1609 mib->cnt_ptr = dev->info->reg_mib_cnt; 1610 port_r_cnt(dev, port); 1611 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 1612 mutex_unlock(&mib->cnt_mutex); 1613 } 1614 1615 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 1616 struct dsa_bridge bridge, 1617 bool *tx_fwd_offload, 1618 struct netlink_ext_ack *extack) 1619 { 1620 /* port_stp_state_set() will be called after to put the port in 1621 * appropriate state so there is no need to do anything. 1622 */ 1623 1624 return 0; 1625 } 1626 1627 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 1628 struct dsa_bridge bridge) 1629 { 1630 /* port_stp_state_set() will be called after to put the port in 1631 * forwarding state so there is no need to do anything. 1632 */ 1633 } 1634 1635 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 1636 { 1637 struct ksz_device *dev = ds->priv; 1638 1639 dev->dev_ops->flush_dyn_mac_table(dev, port); 1640 } 1641 1642 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 1643 const unsigned char *addr, u16 vid, 1644 struct dsa_db db) 1645 { 1646 struct ksz_device *dev = ds->priv; 1647 1648 if (!dev->dev_ops->fdb_add) 1649 return -EOPNOTSUPP; 1650 1651 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 1652 } 1653 1654 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 1655 const unsigned char *addr, 1656 u16 vid, struct dsa_db db) 1657 { 1658 struct ksz_device *dev = ds->priv; 1659 1660 if (!dev->dev_ops->fdb_del) 1661 return -EOPNOTSUPP; 1662 1663 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 1664 } 1665 1666 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 1667 dsa_fdb_dump_cb_t *cb, void *data) 1668 { 1669 struct ksz_device *dev = ds->priv; 1670 1671 if (!dev->dev_ops->fdb_dump) 1672 return -EOPNOTSUPP; 1673 1674 return dev->dev_ops->fdb_dump(dev, port, cb, data); 1675 } 1676 1677 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 1678 const struct switchdev_obj_port_mdb *mdb, 1679 struct dsa_db db) 1680 { 1681 struct ksz_device *dev = ds->priv; 1682 1683 if (!dev->dev_ops->mdb_add) 1684 return -EOPNOTSUPP; 1685 1686 return dev->dev_ops->mdb_add(dev, port, mdb, db); 1687 } 1688 1689 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 1690 const struct switchdev_obj_port_mdb *mdb, 1691 struct dsa_db db) 1692 { 1693 struct ksz_device *dev = ds->priv; 1694 1695 if (!dev->dev_ops->mdb_del) 1696 return -EOPNOTSUPP; 1697 1698 return dev->dev_ops->mdb_del(dev, port, mdb, db); 1699 } 1700 1701 static int ksz_enable_port(struct dsa_switch *ds, int port, 1702 struct phy_device *phy) 1703 { 1704 struct ksz_device *dev = ds->priv; 1705 1706 if (!dsa_is_user_port(ds, port)) 1707 return 0; 1708 1709 /* setup slave port */ 1710 dev->dev_ops->port_setup(dev, port, false); 1711 1712 /* port_stp_state_set() will be called after to enable the port so 1713 * there is no need to do anything. 1714 */ 1715 1716 return 0; 1717 } 1718 1719 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1720 { 1721 struct ksz_device *dev = ds->priv; 1722 struct ksz_port *p; 1723 const u16 *regs; 1724 u8 data; 1725 1726 regs = dev->info->regs; 1727 1728 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 1729 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 1730 1731 p = &dev->ports[port]; 1732 1733 switch (state) { 1734 case BR_STATE_DISABLED: 1735 data |= PORT_LEARN_DISABLE; 1736 break; 1737 case BR_STATE_LISTENING: 1738 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 1739 break; 1740 case BR_STATE_LEARNING: 1741 data |= PORT_RX_ENABLE; 1742 if (!p->learning) 1743 data |= PORT_LEARN_DISABLE; 1744 break; 1745 case BR_STATE_FORWARDING: 1746 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 1747 if (!p->learning) 1748 data |= PORT_LEARN_DISABLE; 1749 break; 1750 case BR_STATE_BLOCKING: 1751 data |= PORT_LEARN_DISABLE; 1752 break; 1753 default: 1754 dev_err(ds->dev, "invalid STP state: %d\n", state); 1755 return; 1756 } 1757 1758 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 1759 1760 p->stp_state = state; 1761 1762 ksz_update_port_member(dev, port); 1763 } 1764 1765 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1766 struct switchdev_brport_flags flags, 1767 struct netlink_ext_ack *extack) 1768 { 1769 if (flags.mask & ~BR_LEARNING) 1770 return -EINVAL; 1771 1772 return 0; 1773 } 1774 1775 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 1776 struct switchdev_brport_flags flags, 1777 struct netlink_ext_ack *extack) 1778 { 1779 struct ksz_device *dev = ds->priv; 1780 struct ksz_port *p = &dev->ports[port]; 1781 1782 if (flags.mask & BR_LEARNING) { 1783 p->learning = !!(flags.val & BR_LEARNING); 1784 1785 /* Make the change take effect immediately */ 1786 ksz_port_stp_state_set(ds, port, p->stp_state); 1787 } 1788 1789 return 0; 1790 } 1791 1792 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 1793 int port, 1794 enum dsa_tag_protocol mp) 1795 { 1796 struct ksz_device *dev = ds->priv; 1797 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 1798 1799 if (dev->chip_id == KSZ8795_CHIP_ID || 1800 dev->chip_id == KSZ8794_CHIP_ID || 1801 dev->chip_id == KSZ8765_CHIP_ID) 1802 proto = DSA_TAG_PROTO_KSZ8795; 1803 1804 if (dev->chip_id == KSZ8830_CHIP_ID || 1805 dev->chip_id == KSZ8563_CHIP_ID || 1806 dev->chip_id == KSZ9893_CHIP_ID) 1807 proto = DSA_TAG_PROTO_KSZ9893; 1808 1809 if (dev->chip_id == KSZ9477_CHIP_ID || 1810 dev->chip_id == KSZ9897_CHIP_ID || 1811 dev->chip_id == KSZ9567_CHIP_ID) 1812 proto = DSA_TAG_PROTO_KSZ9477; 1813 1814 if (is_lan937x(dev)) 1815 proto = DSA_TAG_PROTO_LAN937X_VALUE; 1816 1817 return proto; 1818 } 1819 1820 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 1821 bool flag, struct netlink_ext_ack *extack) 1822 { 1823 struct ksz_device *dev = ds->priv; 1824 1825 if (!dev->dev_ops->vlan_filtering) 1826 return -EOPNOTSUPP; 1827 1828 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 1829 } 1830 1831 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 1832 const struct switchdev_obj_port_vlan *vlan, 1833 struct netlink_ext_ack *extack) 1834 { 1835 struct ksz_device *dev = ds->priv; 1836 1837 if (!dev->dev_ops->vlan_add) 1838 return -EOPNOTSUPP; 1839 1840 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 1841 } 1842 1843 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 1844 const struct switchdev_obj_port_vlan *vlan) 1845 { 1846 struct ksz_device *dev = ds->priv; 1847 1848 if (!dev->dev_ops->vlan_del) 1849 return -EOPNOTSUPP; 1850 1851 return dev->dev_ops->vlan_del(dev, port, vlan); 1852 } 1853 1854 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 1855 struct dsa_mall_mirror_tc_entry *mirror, 1856 bool ingress, struct netlink_ext_ack *extack) 1857 { 1858 struct ksz_device *dev = ds->priv; 1859 1860 if (!dev->dev_ops->mirror_add) 1861 return -EOPNOTSUPP; 1862 1863 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 1864 } 1865 1866 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 1867 struct dsa_mall_mirror_tc_entry *mirror) 1868 { 1869 struct ksz_device *dev = ds->priv; 1870 1871 if (dev->dev_ops->mirror_del) 1872 dev->dev_ops->mirror_del(dev, port, mirror); 1873 } 1874 1875 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 1876 { 1877 struct ksz_device *dev = ds->priv; 1878 1879 if (!dev->dev_ops->change_mtu) 1880 return -EOPNOTSUPP; 1881 1882 return dev->dev_ops->change_mtu(dev, port, mtu); 1883 } 1884 1885 static int ksz_max_mtu(struct dsa_switch *ds, int port) 1886 { 1887 struct ksz_device *dev = ds->priv; 1888 1889 if (!dev->dev_ops->max_mtu) 1890 return -EOPNOTSUPP; 1891 1892 return dev->dev_ops->max_mtu(dev, port); 1893 } 1894 1895 static void ksz_set_xmii(struct ksz_device *dev, int port, 1896 phy_interface_t interface) 1897 { 1898 const u8 *bitval = dev->info->xmii_ctrl1; 1899 struct ksz_port *p = &dev->ports[port]; 1900 const u16 *regs = dev->info->regs; 1901 u8 data8; 1902 1903 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 1904 1905 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 1906 P_RGMII_ID_EG_ENABLE); 1907 1908 switch (interface) { 1909 case PHY_INTERFACE_MODE_MII: 1910 data8 |= bitval[P_MII_SEL]; 1911 break; 1912 case PHY_INTERFACE_MODE_RMII: 1913 data8 |= bitval[P_RMII_SEL]; 1914 break; 1915 case PHY_INTERFACE_MODE_GMII: 1916 data8 |= bitval[P_GMII_SEL]; 1917 break; 1918 case PHY_INTERFACE_MODE_RGMII: 1919 case PHY_INTERFACE_MODE_RGMII_ID: 1920 case PHY_INTERFACE_MODE_RGMII_TXID: 1921 case PHY_INTERFACE_MODE_RGMII_RXID: 1922 data8 |= bitval[P_RGMII_SEL]; 1923 /* On KSZ9893, disable RGMII in-band status support */ 1924 if (dev->chip_id == KSZ9893_CHIP_ID || 1925 dev->chip_id == KSZ8563_CHIP_ID) 1926 data8 &= ~P_MII_MAC_MODE; 1927 break; 1928 default: 1929 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 1930 phy_modes(interface), port); 1931 return; 1932 } 1933 1934 if (p->rgmii_tx_val) 1935 data8 |= P_RGMII_ID_EG_ENABLE; 1936 1937 if (p->rgmii_rx_val) 1938 data8 |= P_RGMII_ID_IG_ENABLE; 1939 1940 /* Write the updated value */ 1941 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 1942 } 1943 1944 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 1945 { 1946 const u8 *bitval = dev->info->xmii_ctrl1; 1947 const u16 *regs = dev->info->regs; 1948 phy_interface_t interface; 1949 u8 data8; 1950 u8 val; 1951 1952 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 1953 1954 val = FIELD_GET(P_MII_SEL_M, data8); 1955 1956 if (val == bitval[P_MII_SEL]) { 1957 if (gbit) 1958 interface = PHY_INTERFACE_MODE_GMII; 1959 else 1960 interface = PHY_INTERFACE_MODE_MII; 1961 } else if (val == bitval[P_RMII_SEL]) { 1962 interface = PHY_INTERFACE_MODE_RGMII; 1963 } else { 1964 interface = PHY_INTERFACE_MODE_RGMII; 1965 if (data8 & P_RGMII_ID_EG_ENABLE) 1966 interface = PHY_INTERFACE_MODE_RGMII_TXID; 1967 if (data8 & P_RGMII_ID_IG_ENABLE) { 1968 interface = PHY_INTERFACE_MODE_RGMII_RXID; 1969 if (data8 & P_RGMII_ID_EG_ENABLE) 1970 interface = PHY_INTERFACE_MODE_RGMII_ID; 1971 } 1972 } 1973 1974 return interface; 1975 } 1976 1977 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, 1978 unsigned int mode, 1979 const struct phylink_link_state *state) 1980 { 1981 struct ksz_device *dev = ds->priv; 1982 1983 if (ksz_is_ksz88x3(dev)) 1984 return; 1985 1986 /* Internal PHYs */ 1987 if (dev->info->internal_phy[port]) 1988 return; 1989 1990 if (phylink_autoneg_inband(mode)) { 1991 dev_err(dev->dev, "In-band AN not supported!\n"); 1992 return; 1993 } 1994 1995 ksz_set_xmii(dev, port, state->interface); 1996 1997 if (dev->dev_ops->phylink_mac_config) 1998 dev->dev_ops->phylink_mac_config(dev, port, mode, state); 1999 2000 if (dev->dev_ops->setup_rgmii_delay) 2001 dev->dev_ops->setup_rgmii_delay(dev, port); 2002 } 2003 2004 bool ksz_get_gbit(struct ksz_device *dev, int port) 2005 { 2006 const u8 *bitval = dev->info->xmii_ctrl1; 2007 const u16 *regs = dev->info->regs; 2008 bool gbit = false; 2009 u8 data8; 2010 bool val; 2011 2012 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2013 2014 val = FIELD_GET(P_GMII_1GBIT_M, data8); 2015 2016 if (val == bitval[P_GMII_1GBIT]) 2017 gbit = true; 2018 2019 return gbit; 2020 } 2021 2022 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 2023 { 2024 const u8 *bitval = dev->info->xmii_ctrl1; 2025 const u16 *regs = dev->info->regs; 2026 u8 data8; 2027 2028 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2029 2030 data8 &= ~P_GMII_1GBIT_M; 2031 2032 if (gbit) 2033 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 2034 else 2035 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 2036 2037 /* Write the updated value */ 2038 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2039 } 2040 2041 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 2042 { 2043 const u8 *bitval = dev->info->xmii_ctrl0; 2044 const u16 *regs = dev->info->regs; 2045 u8 data8; 2046 2047 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 2048 2049 data8 &= ~P_MII_100MBIT_M; 2050 2051 if (speed == SPEED_100) 2052 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 2053 else 2054 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 2055 2056 /* Write the updated value */ 2057 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 2058 } 2059 2060 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 2061 { 2062 if (speed == SPEED_1000) 2063 ksz_set_gbit(dev, port, true); 2064 else 2065 ksz_set_gbit(dev, port, false); 2066 2067 if (speed == SPEED_100 || speed == SPEED_10) 2068 ksz_set_100_10mbit(dev, port, speed); 2069 } 2070 2071 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 2072 bool tx_pause, bool rx_pause) 2073 { 2074 const u8 *bitval = dev->info->xmii_ctrl0; 2075 const u32 *masks = dev->info->masks; 2076 const u16 *regs = dev->info->regs; 2077 u8 mask; 2078 u8 val; 2079 2080 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 2081 masks[P_MII_RX_FLOW_CTRL]; 2082 2083 if (duplex == DUPLEX_FULL) 2084 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 2085 else 2086 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 2087 2088 if (tx_pause) 2089 val |= masks[P_MII_TX_FLOW_CTRL]; 2090 2091 if (rx_pause) 2092 val |= masks[P_MII_RX_FLOW_CTRL]; 2093 2094 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 2095 } 2096 2097 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, 2098 unsigned int mode, 2099 phy_interface_t interface, 2100 struct phy_device *phydev, int speed, 2101 int duplex, bool tx_pause, bool rx_pause) 2102 { 2103 struct ksz_device *dev = ds->priv; 2104 struct ksz_port *p; 2105 2106 p = &dev->ports[port]; 2107 2108 /* Internal PHYs */ 2109 if (dev->info->internal_phy[port]) 2110 return; 2111 2112 p->phydev.speed = speed; 2113 2114 ksz_port_set_xmii_speed(dev, port, speed); 2115 2116 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 2117 2118 if (dev->dev_ops->phylink_mac_link_up) 2119 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface, 2120 phydev, speed, duplex, 2121 tx_pause, rx_pause); 2122 } 2123 2124 static int ksz_switch_detect(struct ksz_device *dev) 2125 { 2126 u8 id1, id2, id4; 2127 u16 id16; 2128 u32 id32; 2129 int ret; 2130 2131 /* read chip id */ 2132 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 2133 if (ret) 2134 return ret; 2135 2136 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 2137 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 2138 2139 switch (id1) { 2140 case KSZ87_FAMILY_ID: 2141 if (id2 == KSZ87_CHIP_ID_95) { 2142 u8 val; 2143 2144 dev->chip_id = KSZ8795_CHIP_ID; 2145 2146 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 2147 if (val & KSZ8_PORT_FIBER_MODE) 2148 dev->chip_id = KSZ8765_CHIP_ID; 2149 } else if (id2 == KSZ87_CHIP_ID_94) { 2150 dev->chip_id = KSZ8794_CHIP_ID; 2151 } else { 2152 return -ENODEV; 2153 } 2154 break; 2155 case KSZ88_FAMILY_ID: 2156 if (id2 == KSZ88_CHIP_ID_63) 2157 dev->chip_id = KSZ8830_CHIP_ID; 2158 else 2159 return -ENODEV; 2160 break; 2161 default: 2162 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 2163 if (ret) 2164 return ret; 2165 2166 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 2167 id32 &= ~0xFF; 2168 2169 switch (id32) { 2170 case KSZ9477_CHIP_ID: 2171 case KSZ9897_CHIP_ID: 2172 case KSZ9567_CHIP_ID: 2173 case LAN9370_CHIP_ID: 2174 case LAN9371_CHIP_ID: 2175 case LAN9372_CHIP_ID: 2176 case LAN9373_CHIP_ID: 2177 case LAN9374_CHIP_ID: 2178 dev->chip_id = id32; 2179 break; 2180 case KSZ9893_CHIP_ID: 2181 ret = ksz_read8(dev, REG_CHIP_ID4, 2182 &id4); 2183 if (ret) 2184 return ret; 2185 2186 if (id4 == SKU_ID_KSZ8563) 2187 dev->chip_id = KSZ8563_CHIP_ID; 2188 else 2189 dev->chip_id = KSZ9893_CHIP_ID; 2190 2191 break; 2192 default: 2193 dev_err(dev->dev, 2194 "unsupported switch detected %x)\n", id32); 2195 return -ENODEV; 2196 } 2197 } 2198 return 0; 2199 } 2200 2201 static const struct dsa_switch_ops ksz_switch_ops = { 2202 .get_tag_protocol = ksz_get_tag_protocol, 2203 .get_phy_flags = ksz_get_phy_flags, 2204 .setup = ksz_setup, 2205 .teardown = ksz_teardown, 2206 .phy_read = ksz_phy_read16, 2207 .phy_write = ksz_phy_write16, 2208 .phylink_get_caps = ksz_phylink_get_caps, 2209 .phylink_mac_config = ksz_phylink_mac_config, 2210 .phylink_mac_link_up = ksz_phylink_mac_link_up, 2211 .phylink_mac_link_down = ksz_mac_link_down, 2212 .port_enable = ksz_enable_port, 2213 .get_strings = ksz_get_strings, 2214 .get_ethtool_stats = ksz_get_ethtool_stats, 2215 .get_sset_count = ksz_sset_count, 2216 .port_bridge_join = ksz_port_bridge_join, 2217 .port_bridge_leave = ksz_port_bridge_leave, 2218 .port_stp_state_set = ksz_port_stp_state_set, 2219 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 2220 .port_bridge_flags = ksz_port_bridge_flags, 2221 .port_fast_age = ksz_port_fast_age, 2222 .port_vlan_filtering = ksz_port_vlan_filtering, 2223 .port_vlan_add = ksz_port_vlan_add, 2224 .port_vlan_del = ksz_port_vlan_del, 2225 .port_fdb_dump = ksz_port_fdb_dump, 2226 .port_fdb_add = ksz_port_fdb_add, 2227 .port_fdb_del = ksz_port_fdb_del, 2228 .port_mdb_add = ksz_port_mdb_add, 2229 .port_mdb_del = ksz_port_mdb_del, 2230 .port_mirror_add = ksz_port_mirror_add, 2231 .port_mirror_del = ksz_port_mirror_del, 2232 .get_stats64 = ksz_get_stats64, 2233 .get_pause_stats = ksz_get_pause_stats, 2234 .port_change_mtu = ksz_change_mtu, 2235 .port_max_mtu = ksz_max_mtu, 2236 }; 2237 2238 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 2239 { 2240 struct dsa_switch *ds; 2241 struct ksz_device *swdev; 2242 2243 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2244 if (!ds) 2245 return NULL; 2246 2247 ds->dev = base; 2248 ds->num_ports = DSA_MAX_PORTS; 2249 ds->ops = &ksz_switch_ops; 2250 2251 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 2252 if (!swdev) 2253 return NULL; 2254 2255 ds->priv = swdev; 2256 swdev->dev = base; 2257 2258 swdev->ds = ds; 2259 swdev->priv = priv; 2260 2261 return swdev; 2262 } 2263 EXPORT_SYMBOL(ksz_switch_alloc); 2264 2265 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 2266 struct device_node *port_dn) 2267 { 2268 phy_interface_t phy_mode = dev->ports[port_num].interface; 2269 int rx_delay = -1, tx_delay = -1; 2270 2271 if (!phy_interface_mode_is_rgmii(phy_mode)) 2272 return; 2273 2274 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 2275 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 2276 2277 if (rx_delay == -1 && tx_delay == -1) { 2278 dev_warn(dev->dev, 2279 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 2280 "please update device tree to specify \"rx-internal-delay-ps\" and " 2281 "\"tx-internal-delay-ps\"", 2282 port_num); 2283 2284 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 2285 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 2286 rx_delay = 2000; 2287 2288 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 2289 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 2290 tx_delay = 2000; 2291 } 2292 2293 if (rx_delay < 0) 2294 rx_delay = 0; 2295 if (tx_delay < 0) 2296 tx_delay = 0; 2297 2298 dev->ports[port_num].rgmii_rx_val = rx_delay; 2299 dev->ports[port_num].rgmii_tx_val = tx_delay; 2300 } 2301 2302 int ksz_switch_register(struct ksz_device *dev) 2303 { 2304 const struct ksz_chip_data *info; 2305 struct device_node *port, *ports; 2306 phy_interface_t interface; 2307 unsigned int port_num; 2308 int ret; 2309 int i; 2310 2311 if (dev->pdata) 2312 dev->chip_id = dev->pdata->chip_id; 2313 2314 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 2315 GPIOD_OUT_LOW); 2316 if (IS_ERR(dev->reset_gpio)) 2317 return PTR_ERR(dev->reset_gpio); 2318 2319 if (dev->reset_gpio) { 2320 gpiod_set_value_cansleep(dev->reset_gpio, 1); 2321 usleep_range(10000, 12000); 2322 gpiod_set_value_cansleep(dev->reset_gpio, 0); 2323 msleep(100); 2324 } 2325 2326 mutex_init(&dev->dev_mutex); 2327 mutex_init(&dev->regmap_mutex); 2328 mutex_init(&dev->alu_mutex); 2329 mutex_init(&dev->vlan_mutex); 2330 2331 ret = ksz_switch_detect(dev); 2332 if (ret) 2333 return ret; 2334 2335 info = ksz_lookup_info(dev->chip_id); 2336 if (!info) 2337 return -ENODEV; 2338 2339 /* Update the compatible info with the probed one */ 2340 dev->info = info; 2341 2342 dev_info(dev->dev, "found switch: %s, rev %i\n", 2343 dev->info->dev_name, dev->chip_rev); 2344 2345 ret = ksz_check_device_id(dev); 2346 if (ret) 2347 return ret; 2348 2349 dev->dev_ops = dev->info->ops; 2350 2351 ret = dev->dev_ops->init(dev); 2352 if (ret) 2353 return ret; 2354 2355 dev->ports = devm_kzalloc(dev->dev, 2356 dev->info->port_cnt * sizeof(struct ksz_port), 2357 GFP_KERNEL); 2358 if (!dev->ports) 2359 return -ENOMEM; 2360 2361 for (i = 0; i < dev->info->port_cnt; i++) { 2362 spin_lock_init(&dev->ports[i].mib.stats64_lock); 2363 mutex_init(&dev->ports[i].mib.cnt_mutex); 2364 dev->ports[i].mib.counters = 2365 devm_kzalloc(dev->dev, 2366 sizeof(u64) * (dev->info->mib_cnt + 1), 2367 GFP_KERNEL); 2368 if (!dev->ports[i].mib.counters) 2369 return -ENOMEM; 2370 2371 dev->ports[i].ksz_dev = dev; 2372 dev->ports[i].num = i; 2373 } 2374 2375 /* set the real number of ports */ 2376 dev->ds->num_ports = dev->info->port_cnt; 2377 2378 /* Host port interface will be self detected, or specifically set in 2379 * device tree. 2380 */ 2381 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 2382 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 2383 if (dev->dev->of_node) { 2384 ret = of_get_phy_mode(dev->dev->of_node, &interface); 2385 if (ret == 0) 2386 dev->compat_interface = interface; 2387 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 2388 if (!ports) 2389 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 2390 if (ports) { 2391 for_each_available_child_of_node(ports, port) { 2392 if (of_property_read_u32(port, "reg", 2393 &port_num)) 2394 continue; 2395 if (!(dev->port_mask & BIT(port_num))) { 2396 of_node_put(port); 2397 of_node_put(ports); 2398 return -EINVAL; 2399 } 2400 of_get_phy_mode(port, 2401 &dev->ports[port_num].interface); 2402 2403 ksz_parse_rgmii_delay(dev, port_num, port); 2404 } 2405 of_node_put(ports); 2406 } 2407 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 2408 "microchip,synclko-125"); 2409 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 2410 "microchip,synclko-disable"); 2411 if (dev->synclko_125 && dev->synclko_disable) { 2412 dev_err(dev->dev, "inconsistent synclko settings\n"); 2413 return -EINVAL; 2414 } 2415 } 2416 2417 ret = dsa_register_switch(dev->ds); 2418 if (ret) { 2419 dev->dev_ops->exit(dev); 2420 return ret; 2421 } 2422 2423 /* Read MIB counters every 30 seconds to avoid overflow. */ 2424 dev->mib_read_interval = msecs_to_jiffies(5000); 2425 2426 /* Start the MIB timer. */ 2427 schedule_delayed_work(&dev->mib_read, 0); 2428 2429 return ret; 2430 } 2431 EXPORT_SYMBOL(ksz_switch_register); 2432 2433 void ksz_switch_remove(struct ksz_device *dev) 2434 { 2435 /* timer started */ 2436 if (dev->mib_read_interval) { 2437 dev->mib_read_interval = 0; 2438 cancel_delayed_work_sync(&dev->mib_read); 2439 } 2440 2441 dev->dev_ops->exit(dev); 2442 dsa_unregister_switch(dev->ds); 2443 2444 if (dev->reset_gpio) 2445 gpiod_set_value_cansleep(dev->reset_gpio, 1); 2446 2447 } 2448 EXPORT_SYMBOL(ksz_switch_remove); 2449 2450 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 2451 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 2452 MODULE_LICENSE("GPL"); 2453