1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/if_hsr.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/of.h> 23 #include <linux/of_mdio.h> 24 #include <linux/of_net.h> 25 #include <linux/micrel_phy.h> 26 #include <net/dsa.h> 27 #include <net/pkt_cls.h> 28 #include <net/switchdev.h> 29 30 #include "ksz_common.h" 31 #include "ksz_ptp.h" 32 #include "ksz8.h" 33 #include "ksz9477.h" 34 #include "lan937x.h" 35 36 #define MIB_COUNTER_NUM 0x20 37 38 struct ksz_stats_raw { 39 u64 rx_hi; 40 u64 rx_undersize; 41 u64 rx_fragments; 42 u64 rx_oversize; 43 u64 rx_jabbers; 44 u64 rx_symbol_err; 45 u64 rx_crc_err; 46 u64 rx_align_err; 47 u64 rx_mac_ctrl; 48 u64 rx_pause; 49 u64 rx_bcast; 50 u64 rx_mcast; 51 u64 rx_ucast; 52 u64 rx_64_or_less; 53 u64 rx_65_127; 54 u64 rx_128_255; 55 u64 rx_256_511; 56 u64 rx_512_1023; 57 u64 rx_1024_1522; 58 u64 rx_1523_2000; 59 u64 rx_2001; 60 u64 tx_hi; 61 u64 tx_late_col; 62 u64 tx_pause; 63 u64 tx_bcast; 64 u64 tx_mcast; 65 u64 tx_ucast; 66 u64 tx_deferred; 67 u64 tx_total_col; 68 u64 tx_exc_col; 69 u64 tx_single_col; 70 u64 tx_mult_col; 71 u64 rx_total; 72 u64 tx_total; 73 u64 rx_discards; 74 u64 tx_discards; 75 }; 76 77 struct ksz88xx_stats_raw { 78 u64 rx; 79 u64 rx_hi; 80 u64 rx_undersize; 81 u64 rx_fragments; 82 u64 rx_oversize; 83 u64 rx_jabbers; 84 u64 rx_symbol_err; 85 u64 rx_crc_err; 86 u64 rx_align_err; 87 u64 rx_mac_ctrl; 88 u64 rx_pause; 89 u64 rx_bcast; 90 u64 rx_mcast; 91 u64 rx_ucast; 92 u64 rx_64_or_less; 93 u64 rx_65_127; 94 u64 rx_128_255; 95 u64 rx_256_511; 96 u64 rx_512_1023; 97 u64 rx_1024_1522; 98 u64 tx; 99 u64 tx_hi; 100 u64 tx_late_col; 101 u64 tx_pause; 102 u64 tx_bcast; 103 u64 tx_mcast; 104 u64 tx_ucast; 105 u64 tx_deferred; 106 u64 tx_total_col; 107 u64 tx_exc_col; 108 u64 tx_single_col; 109 u64 tx_mult_col; 110 u64 rx_discards; 111 u64 tx_discards; 112 }; 113 114 static const struct ksz_mib_names ksz88xx_mib_names[] = { 115 { 0x00, "rx" }, 116 { 0x01, "rx_hi" }, 117 { 0x02, "rx_undersize" }, 118 { 0x03, "rx_fragments" }, 119 { 0x04, "rx_oversize" }, 120 { 0x05, "rx_jabbers" }, 121 { 0x06, "rx_symbol_err" }, 122 { 0x07, "rx_crc_err" }, 123 { 0x08, "rx_align_err" }, 124 { 0x09, "rx_mac_ctrl" }, 125 { 0x0a, "rx_pause" }, 126 { 0x0b, "rx_bcast" }, 127 { 0x0c, "rx_mcast" }, 128 { 0x0d, "rx_ucast" }, 129 { 0x0e, "rx_64_or_less" }, 130 { 0x0f, "rx_65_127" }, 131 { 0x10, "rx_128_255" }, 132 { 0x11, "rx_256_511" }, 133 { 0x12, "rx_512_1023" }, 134 { 0x13, "rx_1024_1522" }, 135 { 0x14, "tx" }, 136 { 0x15, "tx_hi" }, 137 { 0x16, "tx_late_col" }, 138 { 0x17, "tx_pause" }, 139 { 0x18, "tx_bcast" }, 140 { 0x19, "tx_mcast" }, 141 { 0x1a, "tx_ucast" }, 142 { 0x1b, "tx_deferred" }, 143 { 0x1c, "tx_total_col" }, 144 { 0x1d, "tx_exc_col" }, 145 { 0x1e, "tx_single_col" }, 146 { 0x1f, "tx_mult_col" }, 147 { 0x100, "rx_discards" }, 148 { 0x101, "tx_discards" }, 149 }; 150 151 static const struct ksz_mib_names ksz9477_mib_names[] = { 152 { 0x00, "rx_hi" }, 153 { 0x01, "rx_undersize" }, 154 { 0x02, "rx_fragments" }, 155 { 0x03, "rx_oversize" }, 156 { 0x04, "rx_jabbers" }, 157 { 0x05, "rx_symbol_err" }, 158 { 0x06, "rx_crc_err" }, 159 { 0x07, "rx_align_err" }, 160 { 0x08, "rx_mac_ctrl" }, 161 { 0x09, "rx_pause" }, 162 { 0x0A, "rx_bcast" }, 163 { 0x0B, "rx_mcast" }, 164 { 0x0C, "rx_ucast" }, 165 { 0x0D, "rx_64_or_less" }, 166 { 0x0E, "rx_65_127" }, 167 { 0x0F, "rx_128_255" }, 168 { 0x10, "rx_256_511" }, 169 { 0x11, "rx_512_1023" }, 170 { 0x12, "rx_1024_1522" }, 171 { 0x13, "rx_1523_2000" }, 172 { 0x14, "rx_2001" }, 173 { 0x15, "tx_hi" }, 174 { 0x16, "tx_late_col" }, 175 { 0x17, "tx_pause" }, 176 { 0x18, "tx_bcast" }, 177 { 0x19, "tx_mcast" }, 178 { 0x1A, "tx_ucast" }, 179 { 0x1B, "tx_deferred" }, 180 { 0x1C, "tx_total_col" }, 181 { 0x1D, "tx_exc_col" }, 182 { 0x1E, "tx_single_col" }, 183 { 0x1F, "tx_mult_col" }, 184 { 0x80, "rx_total" }, 185 { 0x81, "tx_total" }, 186 { 0x82, "rx_discards" }, 187 { 0x83, "tx_discards" }, 188 }; 189 190 struct ksz_driver_strength_prop { 191 const char *name; 192 int offset; 193 int value; 194 }; 195 196 enum ksz_driver_strength_type { 197 KSZ_DRIVER_STRENGTH_HI, 198 KSZ_DRIVER_STRENGTH_LO, 199 KSZ_DRIVER_STRENGTH_IO, 200 }; 201 202 /** 203 * struct ksz_drive_strength - drive strength mapping 204 * @reg_val: register value 205 * @microamp: microamp value 206 */ 207 struct ksz_drive_strength { 208 u32 reg_val; 209 u32 microamp; 210 }; 211 212 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants 213 * 214 * This values are not documented in KSZ9477 variants but confirmed by 215 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893 216 * and KSZ8563 are using same register (drive strength) settings like KSZ8795. 217 * 218 * Documentation in KSZ8795CLX provides more information with some 219 * recommendations: 220 * - for high speed signals 221 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using 222 * 2.5V or 3.3V VDDIO. 223 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with 224 * using 1.8V VDDIO. 225 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V 226 * or 3.3V VDDIO. 227 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO. 228 * 5. In same interface, the heavy loading should use higher one of the 229 * drive current strength. 230 * - for low speed signals 231 * 1. 3.3V VDDIO, use either 4 mA or 8 mA. 232 * 2. 2.5V VDDIO, use either 8 mA or 12 mA. 233 * 3. 1.8V VDDIO, use either 12 mA or 16 mA. 234 * 4. If it is heavy loading, can use higher drive current strength. 235 */ 236 static const struct ksz_drive_strength ksz9477_drive_strengths[] = { 237 { SW_DRIVE_STRENGTH_2MA, 2000 }, 238 { SW_DRIVE_STRENGTH_4MA, 4000 }, 239 { SW_DRIVE_STRENGTH_8MA, 8000 }, 240 { SW_DRIVE_STRENGTH_12MA, 12000 }, 241 { SW_DRIVE_STRENGTH_16MA, 16000 }, 242 { SW_DRIVE_STRENGTH_20MA, 20000 }, 243 { SW_DRIVE_STRENGTH_24MA, 24000 }, 244 { SW_DRIVE_STRENGTH_28MA, 28000 }, 245 }; 246 247 /* ksz8830_drive_strengths - Drive strength mapping for KSZ8830, KSZ8873, .. 248 * variants. 249 * This values are documented in KSZ8873 and KSZ8863 datasheets. 250 */ 251 static const struct ksz_drive_strength ksz8830_drive_strengths[] = { 252 { 0, 8000 }, 253 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 }, 254 }; 255 256 static const struct ksz_dev_ops ksz8_dev_ops = { 257 .setup = ksz8_setup, 258 .get_port_addr = ksz8_get_port_addr, 259 .cfg_port_member = ksz8_cfg_port_member, 260 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 261 .port_setup = ksz8_port_setup, 262 .r_phy = ksz8_r_phy, 263 .w_phy = ksz8_w_phy, 264 .r_mib_cnt = ksz8_r_mib_cnt, 265 .r_mib_pkt = ksz8_r_mib_pkt, 266 .r_mib_stat64 = ksz88xx_r_mib_stats64, 267 .freeze_mib = ksz8_freeze_mib, 268 .port_init_cnt = ksz8_port_init_cnt, 269 .fdb_dump = ksz8_fdb_dump, 270 .fdb_add = ksz8_fdb_add, 271 .fdb_del = ksz8_fdb_del, 272 .mdb_add = ksz8_mdb_add, 273 .mdb_del = ksz8_mdb_del, 274 .vlan_filtering = ksz8_port_vlan_filtering, 275 .vlan_add = ksz8_port_vlan_add, 276 .vlan_del = ksz8_port_vlan_del, 277 .mirror_add = ksz8_port_mirror_add, 278 .mirror_del = ksz8_port_mirror_del, 279 .get_caps = ksz8_get_caps, 280 .config_cpu_port = ksz8_config_cpu_port, 281 .enable_stp_addr = ksz8_enable_stp_addr, 282 .reset = ksz8_reset_switch, 283 .init = ksz8_switch_init, 284 .exit = ksz8_switch_exit, 285 .change_mtu = ksz8_change_mtu, 286 }; 287 288 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 289 unsigned int mode, 290 phy_interface_t interface, 291 struct phy_device *phydev, int speed, 292 int duplex, bool tx_pause, 293 bool rx_pause); 294 295 static const struct ksz_dev_ops ksz9477_dev_ops = { 296 .setup = ksz9477_setup, 297 .get_port_addr = ksz9477_get_port_addr, 298 .cfg_port_member = ksz9477_cfg_port_member, 299 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 300 .port_setup = ksz9477_port_setup, 301 .set_ageing_time = ksz9477_set_ageing_time, 302 .r_phy = ksz9477_r_phy, 303 .w_phy = ksz9477_w_phy, 304 .r_mib_cnt = ksz9477_r_mib_cnt, 305 .r_mib_pkt = ksz9477_r_mib_pkt, 306 .r_mib_stat64 = ksz_r_mib_stats64, 307 .freeze_mib = ksz9477_freeze_mib, 308 .port_init_cnt = ksz9477_port_init_cnt, 309 .vlan_filtering = ksz9477_port_vlan_filtering, 310 .vlan_add = ksz9477_port_vlan_add, 311 .vlan_del = ksz9477_port_vlan_del, 312 .mirror_add = ksz9477_port_mirror_add, 313 .mirror_del = ksz9477_port_mirror_del, 314 .get_caps = ksz9477_get_caps, 315 .fdb_dump = ksz9477_fdb_dump, 316 .fdb_add = ksz9477_fdb_add, 317 .fdb_del = ksz9477_fdb_del, 318 .mdb_add = ksz9477_mdb_add, 319 .mdb_del = ksz9477_mdb_del, 320 .change_mtu = ksz9477_change_mtu, 321 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 322 .config_cpu_port = ksz9477_config_cpu_port, 323 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc, 324 .enable_stp_addr = ksz9477_enable_stp_addr, 325 .reset = ksz9477_reset_switch, 326 .init = ksz9477_switch_init, 327 .exit = ksz9477_switch_exit, 328 }; 329 330 static const struct ksz_dev_ops lan937x_dev_ops = { 331 .setup = lan937x_setup, 332 .teardown = lan937x_teardown, 333 .get_port_addr = ksz9477_get_port_addr, 334 .cfg_port_member = ksz9477_cfg_port_member, 335 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 336 .port_setup = lan937x_port_setup, 337 .set_ageing_time = lan937x_set_ageing_time, 338 .r_phy = lan937x_r_phy, 339 .w_phy = lan937x_w_phy, 340 .r_mib_cnt = ksz9477_r_mib_cnt, 341 .r_mib_pkt = ksz9477_r_mib_pkt, 342 .r_mib_stat64 = ksz_r_mib_stats64, 343 .freeze_mib = ksz9477_freeze_mib, 344 .port_init_cnt = ksz9477_port_init_cnt, 345 .vlan_filtering = ksz9477_port_vlan_filtering, 346 .vlan_add = ksz9477_port_vlan_add, 347 .vlan_del = ksz9477_port_vlan_del, 348 .mirror_add = ksz9477_port_mirror_add, 349 .mirror_del = ksz9477_port_mirror_del, 350 .get_caps = lan937x_phylink_get_caps, 351 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 352 .fdb_dump = ksz9477_fdb_dump, 353 .fdb_add = ksz9477_fdb_add, 354 .fdb_del = ksz9477_fdb_del, 355 .mdb_add = ksz9477_mdb_add, 356 .mdb_del = ksz9477_mdb_del, 357 .change_mtu = lan937x_change_mtu, 358 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 359 .config_cpu_port = lan937x_config_cpu_port, 360 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 361 .enable_stp_addr = ksz9477_enable_stp_addr, 362 .reset = lan937x_reset_switch, 363 .init = lan937x_switch_init, 364 .exit = lan937x_switch_exit, 365 }; 366 367 static const u16 ksz8795_regs[] = { 368 [REG_SW_MAC_ADDR] = 0x68, 369 [REG_IND_CTRL_0] = 0x6E, 370 [REG_IND_DATA_8] = 0x70, 371 [REG_IND_DATA_CHECK] = 0x72, 372 [REG_IND_DATA_HI] = 0x71, 373 [REG_IND_DATA_LO] = 0x75, 374 [REG_IND_MIB_CHECK] = 0x74, 375 [REG_IND_BYTE] = 0xA0, 376 [P_FORCE_CTRL] = 0x0C, 377 [P_LINK_STATUS] = 0x0E, 378 [P_LOCAL_CTRL] = 0x07, 379 [P_NEG_RESTART_CTRL] = 0x0D, 380 [P_REMOTE_STATUS] = 0x08, 381 [P_SPEED_STATUS] = 0x09, 382 [S_TAIL_TAG_CTRL] = 0x0C, 383 [P_STP_CTRL] = 0x02, 384 [S_START_CTRL] = 0x01, 385 [S_BROADCAST_CTRL] = 0x06, 386 [S_MULTICAST_CTRL] = 0x04, 387 [P_XMII_CTRL_0] = 0x06, 388 [P_XMII_CTRL_1] = 0x06, 389 }; 390 391 static const u32 ksz8795_masks[] = { 392 [PORT_802_1P_REMAPPING] = BIT(7), 393 [SW_TAIL_TAG_ENABLE] = BIT(1), 394 [MIB_COUNTER_OVERFLOW] = BIT(6), 395 [MIB_COUNTER_VALID] = BIT(5), 396 [VLAN_TABLE_FID] = GENMASK(6, 0), 397 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 398 [VLAN_TABLE_VALID] = BIT(12), 399 [STATIC_MAC_TABLE_VALID] = BIT(21), 400 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 401 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 402 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 403 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 404 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 405 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 406 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 407 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 408 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 409 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 410 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 411 [P_MII_TX_FLOW_CTRL] = BIT(5), 412 [P_MII_RX_FLOW_CTRL] = BIT(5), 413 }; 414 415 static const u8 ksz8795_xmii_ctrl0[] = { 416 [P_MII_100MBIT] = 0, 417 [P_MII_10MBIT] = 1, 418 [P_MII_FULL_DUPLEX] = 0, 419 [P_MII_HALF_DUPLEX] = 1, 420 }; 421 422 static const u8 ksz8795_xmii_ctrl1[] = { 423 [P_RGMII_SEL] = 3, 424 [P_GMII_SEL] = 2, 425 [P_RMII_SEL] = 1, 426 [P_MII_SEL] = 0, 427 [P_GMII_1GBIT] = 1, 428 [P_GMII_NOT_1GBIT] = 0, 429 }; 430 431 static const u8 ksz8795_shifts[] = { 432 [VLAN_TABLE_MEMBERSHIP_S] = 7, 433 [VLAN_TABLE] = 16, 434 [STATIC_MAC_FWD_PORTS] = 16, 435 [STATIC_MAC_FID] = 24, 436 [DYNAMIC_MAC_ENTRIES_H] = 3, 437 [DYNAMIC_MAC_ENTRIES] = 29, 438 [DYNAMIC_MAC_FID] = 16, 439 [DYNAMIC_MAC_TIMESTAMP] = 27, 440 [DYNAMIC_MAC_SRC_PORT] = 24, 441 }; 442 443 static const u16 ksz8863_regs[] = { 444 [REG_IND_CTRL_0] = 0x79, 445 [REG_IND_DATA_8] = 0x7B, 446 [REG_IND_DATA_CHECK] = 0x7B, 447 [REG_IND_DATA_HI] = 0x7C, 448 [REG_IND_DATA_LO] = 0x80, 449 [REG_IND_MIB_CHECK] = 0x80, 450 [P_FORCE_CTRL] = 0x0C, 451 [P_LINK_STATUS] = 0x0E, 452 [P_LOCAL_CTRL] = 0x0C, 453 [P_NEG_RESTART_CTRL] = 0x0D, 454 [P_REMOTE_STATUS] = 0x0E, 455 [P_SPEED_STATUS] = 0x0F, 456 [S_TAIL_TAG_CTRL] = 0x03, 457 [P_STP_CTRL] = 0x02, 458 [S_START_CTRL] = 0x01, 459 [S_BROADCAST_CTRL] = 0x06, 460 [S_MULTICAST_CTRL] = 0x04, 461 }; 462 463 static const u32 ksz8863_masks[] = { 464 [PORT_802_1P_REMAPPING] = BIT(3), 465 [SW_TAIL_TAG_ENABLE] = BIT(6), 466 [MIB_COUNTER_OVERFLOW] = BIT(7), 467 [MIB_COUNTER_VALID] = BIT(6), 468 [VLAN_TABLE_FID] = GENMASK(15, 12), 469 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 470 [VLAN_TABLE_VALID] = BIT(19), 471 [STATIC_MAC_TABLE_VALID] = BIT(19), 472 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 473 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 474 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 475 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 476 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 477 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 478 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 479 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 480 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 481 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 482 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 483 }; 484 485 static u8 ksz8863_shifts[] = { 486 [VLAN_TABLE_MEMBERSHIP_S] = 16, 487 [STATIC_MAC_FWD_PORTS] = 16, 488 [STATIC_MAC_FID] = 22, 489 [DYNAMIC_MAC_ENTRIES_H] = 8, 490 [DYNAMIC_MAC_ENTRIES] = 24, 491 [DYNAMIC_MAC_FID] = 16, 492 [DYNAMIC_MAC_TIMESTAMP] = 22, 493 [DYNAMIC_MAC_SRC_PORT] = 20, 494 }; 495 496 static const u16 ksz9477_regs[] = { 497 [REG_SW_MAC_ADDR] = 0x0302, 498 [P_STP_CTRL] = 0x0B04, 499 [S_START_CTRL] = 0x0300, 500 [S_BROADCAST_CTRL] = 0x0332, 501 [S_MULTICAST_CTRL] = 0x0331, 502 [P_XMII_CTRL_0] = 0x0300, 503 [P_XMII_CTRL_1] = 0x0301, 504 }; 505 506 static const u32 ksz9477_masks[] = { 507 [ALU_STAT_WRITE] = 0, 508 [ALU_STAT_READ] = 1, 509 [P_MII_TX_FLOW_CTRL] = BIT(5), 510 [P_MII_RX_FLOW_CTRL] = BIT(3), 511 }; 512 513 static const u8 ksz9477_shifts[] = { 514 [ALU_STAT_INDEX] = 16, 515 }; 516 517 static const u8 ksz9477_xmii_ctrl0[] = { 518 [P_MII_100MBIT] = 1, 519 [P_MII_10MBIT] = 0, 520 [P_MII_FULL_DUPLEX] = 1, 521 [P_MII_HALF_DUPLEX] = 0, 522 }; 523 524 static const u8 ksz9477_xmii_ctrl1[] = { 525 [P_RGMII_SEL] = 0, 526 [P_RMII_SEL] = 1, 527 [P_GMII_SEL] = 2, 528 [P_MII_SEL] = 3, 529 [P_GMII_1GBIT] = 0, 530 [P_GMII_NOT_1GBIT] = 1, 531 }; 532 533 static const u32 lan937x_masks[] = { 534 [ALU_STAT_WRITE] = 1, 535 [ALU_STAT_READ] = 2, 536 [P_MII_TX_FLOW_CTRL] = BIT(5), 537 [P_MII_RX_FLOW_CTRL] = BIT(3), 538 }; 539 540 static const u8 lan937x_shifts[] = { 541 [ALU_STAT_INDEX] = 8, 542 }; 543 544 static const struct regmap_range ksz8563_valid_regs[] = { 545 regmap_reg_range(0x0000, 0x0003), 546 regmap_reg_range(0x0006, 0x0006), 547 regmap_reg_range(0x000f, 0x001f), 548 regmap_reg_range(0x0100, 0x0100), 549 regmap_reg_range(0x0104, 0x0107), 550 regmap_reg_range(0x010d, 0x010d), 551 regmap_reg_range(0x0110, 0x0113), 552 regmap_reg_range(0x0120, 0x012b), 553 regmap_reg_range(0x0201, 0x0201), 554 regmap_reg_range(0x0210, 0x0213), 555 regmap_reg_range(0x0300, 0x0300), 556 regmap_reg_range(0x0302, 0x031b), 557 regmap_reg_range(0x0320, 0x032b), 558 regmap_reg_range(0x0330, 0x0336), 559 regmap_reg_range(0x0338, 0x033e), 560 regmap_reg_range(0x0340, 0x035f), 561 regmap_reg_range(0x0370, 0x0370), 562 regmap_reg_range(0x0378, 0x0378), 563 regmap_reg_range(0x037c, 0x037d), 564 regmap_reg_range(0x0390, 0x0393), 565 regmap_reg_range(0x0400, 0x040e), 566 regmap_reg_range(0x0410, 0x042f), 567 regmap_reg_range(0x0500, 0x0519), 568 regmap_reg_range(0x0520, 0x054b), 569 regmap_reg_range(0x0550, 0x05b3), 570 571 /* port 1 */ 572 regmap_reg_range(0x1000, 0x1001), 573 regmap_reg_range(0x1004, 0x100b), 574 regmap_reg_range(0x1013, 0x1013), 575 regmap_reg_range(0x1017, 0x1017), 576 regmap_reg_range(0x101b, 0x101b), 577 regmap_reg_range(0x101f, 0x1021), 578 regmap_reg_range(0x1030, 0x1030), 579 regmap_reg_range(0x1100, 0x1111), 580 regmap_reg_range(0x111a, 0x111d), 581 regmap_reg_range(0x1122, 0x1127), 582 regmap_reg_range(0x112a, 0x112b), 583 regmap_reg_range(0x1136, 0x1139), 584 regmap_reg_range(0x113e, 0x113f), 585 regmap_reg_range(0x1400, 0x1401), 586 regmap_reg_range(0x1403, 0x1403), 587 regmap_reg_range(0x1410, 0x1417), 588 regmap_reg_range(0x1420, 0x1423), 589 regmap_reg_range(0x1500, 0x1507), 590 regmap_reg_range(0x1600, 0x1612), 591 regmap_reg_range(0x1800, 0x180f), 592 regmap_reg_range(0x1900, 0x1907), 593 regmap_reg_range(0x1914, 0x191b), 594 regmap_reg_range(0x1a00, 0x1a03), 595 regmap_reg_range(0x1a04, 0x1a08), 596 regmap_reg_range(0x1b00, 0x1b01), 597 regmap_reg_range(0x1b04, 0x1b04), 598 regmap_reg_range(0x1c00, 0x1c05), 599 regmap_reg_range(0x1c08, 0x1c1b), 600 601 /* port 2 */ 602 regmap_reg_range(0x2000, 0x2001), 603 regmap_reg_range(0x2004, 0x200b), 604 regmap_reg_range(0x2013, 0x2013), 605 regmap_reg_range(0x2017, 0x2017), 606 regmap_reg_range(0x201b, 0x201b), 607 regmap_reg_range(0x201f, 0x2021), 608 regmap_reg_range(0x2030, 0x2030), 609 regmap_reg_range(0x2100, 0x2111), 610 regmap_reg_range(0x211a, 0x211d), 611 regmap_reg_range(0x2122, 0x2127), 612 regmap_reg_range(0x212a, 0x212b), 613 regmap_reg_range(0x2136, 0x2139), 614 regmap_reg_range(0x213e, 0x213f), 615 regmap_reg_range(0x2400, 0x2401), 616 regmap_reg_range(0x2403, 0x2403), 617 regmap_reg_range(0x2410, 0x2417), 618 regmap_reg_range(0x2420, 0x2423), 619 regmap_reg_range(0x2500, 0x2507), 620 regmap_reg_range(0x2600, 0x2612), 621 regmap_reg_range(0x2800, 0x280f), 622 regmap_reg_range(0x2900, 0x2907), 623 regmap_reg_range(0x2914, 0x291b), 624 regmap_reg_range(0x2a00, 0x2a03), 625 regmap_reg_range(0x2a04, 0x2a08), 626 regmap_reg_range(0x2b00, 0x2b01), 627 regmap_reg_range(0x2b04, 0x2b04), 628 regmap_reg_range(0x2c00, 0x2c05), 629 regmap_reg_range(0x2c08, 0x2c1b), 630 631 /* port 3 */ 632 regmap_reg_range(0x3000, 0x3001), 633 regmap_reg_range(0x3004, 0x300b), 634 regmap_reg_range(0x3013, 0x3013), 635 regmap_reg_range(0x3017, 0x3017), 636 regmap_reg_range(0x301b, 0x301b), 637 regmap_reg_range(0x301f, 0x3021), 638 regmap_reg_range(0x3030, 0x3030), 639 regmap_reg_range(0x3300, 0x3301), 640 regmap_reg_range(0x3303, 0x3303), 641 regmap_reg_range(0x3400, 0x3401), 642 regmap_reg_range(0x3403, 0x3403), 643 regmap_reg_range(0x3410, 0x3417), 644 regmap_reg_range(0x3420, 0x3423), 645 regmap_reg_range(0x3500, 0x3507), 646 regmap_reg_range(0x3600, 0x3612), 647 regmap_reg_range(0x3800, 0x380f), 648 regmap_reg_range(0x3900, 0x3907), 649 regmap_reg_range(0x3914, 0x391b), 650 regmap_reg_range(0x3a00, 0x3a03), 651 regmap_reg_range(0x3a04, 0x3a08), 652 regmap_reg_range(0x3b00, 0x3b01), 653 regmap_reg_range(0x3b04, 0x3b04), 654 regmap_reg_range(0x3c00, 0x3c05), 655 regmap_reg_range(0x3c08, 0x3c1b), 656 }; 657 658 static const struct regmap_access_table ksz8563_register_set = { 659 .yes_ranges = ksz8563_valid_regs, 660 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 661 }; 662 663 static const struct regmap_range ksz9477_valid_regs[] = { 664 regmap_reg_range(0x0000, 0x0003), 665 regmap_reg_range(0x0006, 0x0006), 666 regmap_reg_range(0x0010, 0x001f), 667 regmap_reg_range(0x0100, 0x0100), 668 regmap_reg_range(0x0103, 0x0107), 669 regmap_reg_range(0x010d, 0x010d), 670 regmap_reg_range(0x0110, 0x0113), 671 regmap_reg_range(0x0120, 0x012b), 672 regmap_reg_range(0x0201, 0x0201), 673 regmap_reg_range(0x0210, 0x0213), 674 regmap_reg_range(0x0300, 0x0300), 675 regmap_reg_range(0x0302, 0x031b), 676 regmap_reg_range(0x0320, 0x032b), 677 regmap_reg_range(0x0330, 0x0336), 678 regmap_reg_range(0x0338, 0x033b), 679 regmap_reg_range(0x033e, 0x033e), 680 regmap_reg_range(0x0340, 0x035f), 681 regmap_reg_range(0x0370, 0x0370), 682 regmap_reg_range(0x0378, 0x0378), 683 regmap_reg_range(0x037c, 0x037d), 684 regmap_reg_range(0x0390, 0x0393), 685 regmap_reg_range(0x0400, 0x040e), 686 regmap_reg_range(0x0410, 0x042f), 687 regmap_reg_range(0x0444, 0x044b), 688 regmap_reg_range(0x0450, 0x046f), 689 regmap_reg_range(0x0500, 0x0519), 690 regmap_reg_range(0x0520, 0x054b), 691 regmap_reg_range(0x0550, 0x05b3), 692 regmap_reg_range(0x0604, 0x060b), 693 regmap_reg_range(0x0610, 0x0612), 694 regmap_reg_range(0x0614, 0x062c), 695 regmap_reg_range(0x0640, 0x0645), 696 regmap_reg_range(0x0648, 0x064d), 697 698 /* port 1 */ 699 regmap_reg_range(0x1000, 0x1001), 700 regmap_reg_range(0x1013, 0x1013), 701 regmap_reg_range(0x1017, 0x1017), 702 regmap_reg_range(0x101b, 0x101b), 703 regmap_reg_range(0x101f, 0x1020), 704 regmap_reg_range(0x1030, 0x1030), 705 regmap_reg_range(0x1100, 0x1115), 706 regmap_reg_range(0x111a, 0x111f), 707 regmap_reg_range(0x1120, 0x112b), 708 regmap_reg_range(0x1134, 0x113b), 709 regmap_reg_range(0x113c, 0x113f), 710 regmap_reg_range(0x1400, 0x1401), 711 regmap_reg_range(0x1403, 0x1403), 712 regmap_reg_range(0x1410, 0x1417), 713 regmap_reg_range(0x1420, 0x1423), 714 regmap_reg_range(0x1500, 0x1507), 715 regmap_reg_range(0x1600, 0x1613), 716 regmap_reg_range(0x1800, 0x180f), 717 regmap_reg_range(0x1820, 0x1827), 718 regmap_reg_range(0x1830, 0x1837), 719 regmap_reg_range(0x1840, 0x184b), 720 regmap_reg_range(0x1900, 0x1907), 721 regmap_reg_range(0x1914, 0x191b), 722 regmap_reg_range(0x1920, 0x1920), 723 regmap_reg_range(0x1923, 0x1927), 724 regmap_reg_range(0x1a00, 0x1a03), 725 regmap_reg_range(0x1a04, 0x1a07), 726 regmap_reg_range(0x1b00, 0x1b01), 727 regmap_reg_range(0x1b04, 0x1b04), 728 regmap_reg_range(0x1c00, 0x1c05), 729 regmap_reg_range(0x1c08, 0x1c1b), 730 731 /* port 2 */ 732 regmap_reg_range(0x2000, 0x2001), 733 regmap_reg_range(0x2013, 0x2013), 734 regmap_reg_range(0x2017, 0x2017), 735 regmap_reg_range(0x201b, 0x201b), 736 regmap_reg_range(0x201f, 0x2020), 737 regmap_reg_range(0x2030, 0x2030), 738 regmap_reg_range(0x2100, 0x2115), 739 regmap_reg_range(0x211a, 0x211f), 740 regmap_reg_range(0x2120, 0x212b), 741 regmap_reg_range(0x2134, 0x213b), 742 regmap_reg_range(0x213c, 0x213f), 743 regmap_reg_range(0x2400, 0x2401), 744 regmap_reg_range(0x2403, 0x2403), 745 regmap_reg_range(0x2410, 0x2417), 746 regmap_reg_range(0x2420, 0x2423), 747 regmap_reg_range(0x2500, 0x2507), 748 regmap_reg_range(0x2600, 0x2613), 749 regmap_reg_range(0x2800, 0x280f), 750 regmap_reg_range(0x2820, 0x2827), 751 regmap_reg_range(0x2830, 0x2837), 752 regmap_reg_range(0x2840, 0x284b), 753 regmap_reg_range(0x2900, 0x2907), 754 regmap_reg_range(0x2914, 0x291b), 755 regmap_reg_range(0x2920, 0x2920), 756 regmap_reg_range(0x2923, 0x2927), 757 regmap_reg_range(0x2a00, 0x2a03), 758 regmap_reg_range(0x2a04, 0x2a07), 759 regmap_reg_range(0x2b00, 0x2b01), 760 regmap_reg_range(0x2b04, 0x2b04), 761 regmap_reg_range(0x2c00, 0x2c05), 762 regmap_reg_range(0x2c08, 0x2c1b), 763 764 /* port 3 */ 765 regmap_reg_range(0x3000, 0x3001), 766 regmap_reg_range(0x3013, 0x3013), 767 regmap_reg_range(0x3017, 0x3017), 768 regmap_reg_range(0x301b, 0x301b), 769 regmap_reg_range(0x301f, 0x3020), 770 regmap_reg_range(0x3030, 0x3030), 771 regmap_reg_range(0x3100, 0x3115), 772 regmap_reg_range(0x311a, 0x311f), 773 regmap_reg_range(0x3120, 0x312b), 774 regmap_reg_range(0x3134, 0x313b), 775 regmap_reg_range(0x313c, 0x313f), 776 regmap_reg_range(0x3400, 0x3401), 777 regmap_reg_range(0x3403, 0x3403), 778 regmap_reg_range(0x3410, 0x3417), 779 regmap_reg_range(0x3420, 0x3423), 780 regmap_reg_range(0x3500, 0x3507), 781 regmap_reg_range(0x3600, 0x3613), 782 regmap_reg_range(0x3800, 0x380f), 783 regmap_reg_range(0x3820, 0x3827), 784 regmap_reg_range(0x3830, 0x3837), 785 regmap_reg_range(0x3840, 0x384b), 786 regmap_reg_range(0x3900, 0x3907), 787 regmap_reg_range(0x3914, 0x391b), 788 regmap_reg_range(0x3920, 0x3920), 789 regmap_reg_range(0x3923, 0x3927), 790 regmap_reg_range(0x3a00, 0x3a03), 791 regmap_reg_range(0x3a04, 0x3a07), 792 regmap_reg_range(0x3b00, 0x3b01), 793 regmap_reg_range(0x3b04, 0x3b04), 794 regmap_reg_range(0x3c00, 0x3c05), 795 regmap_reg_range(0x3c08, 0x3c1b), 796 797 /* port 4 */ 798 regmap_reg_range(0x4000, 0x4001), 799 regmap_reg_range(0x4013, 0x4013), 800 regmap_reg_range(0x4017, 0x4017), 801 regmap_reg_range(0x401b, 0x401b), 802 regmap_reg_range(0x401f, 0x4020), 803 regmap_reg_range(0x4030, 0x4030), 804 regmap_reg_range(0x4100, 0x4115), 805 regmap_reg_range(0x411a, 0x411f), 806 regmap_reg_range(0x4120, 0x412b), 807 regmap_reg_range(0x4134, 0x413b), 808 regmap_reg_range(0x413c, 0x413f), 809 regmap_reg_range(0x4400, 0x4401), 810 regmap_reg_range(0x4403, 0x4403), 811 regmap_reg_range(0x4410, 0x4417), 812 regmap_reg_range(0x4420, 0x4423), 813 regmap_reg_range(0x4500, 0x4507), 814 regmap_reg_range(0x4600, 0x4613), 815 regmap_reg_range(0x4800, 0x480f), 816 regmap_reg_range(0x4820, 0x4827), 817 regmap_reg_range(0x4830, 0x4837), 818 regmap_reg_range(0x4840, 0x484b), 819 regmap_reg_range(0x4900, 0x4907), 820 regmap_reg_range(0x4914, 0x491b), 821 regmap_reg_range(0x4920, 0x4920), 822 regmap_reg_range(0x4923, 0x4927), 823 regmap_reg_range(0x4a00, 0x4a03), 824 regmap_reg_range(0x4a04, 0x4a07), 825 regmap_reg_range(0x4b00, 0x4b01), 826 regmap_reg_range(0x4b04, 0x4b04), 827 regmap_reg_range(0x4c00, 0x4c05), 828 regmap_reg_range(0x4c08, 0x4c1b), 829 830 /* port 5 */ 831 regmap_reg_range(0x5000, 0x5001), 832 regmap_reg_range(0x5013, 0x5013), 833 regmap_reg_range(0x5017, 0x5017), 834 regmap_reg_range(0x501b, 0x501b), 835 regmap_reg_range(0x501f, 0x5020), 836 regmap_reg_range(0x5030, 0x5030), 837 regmap_reg_range(0x5100, 0x5115), 838 regmap_reg_range(0x511a, 0x511f), 839 regmap_reg_range(0x5120, 0x512b), 840 regmap_reg_range(0x5134, 0x513b), 841 regmap_reg_range(0x513c, 0x513f), 842 regmap_reg_range(0x5400, 0x5401), 843 regmap_reg_range(0x5403, 0x5403), 844 regmap_reg_range(0x5410, 0x5417), 845 regmap_reg_range(0x5420, 0x5423), 846 regmap_reg_range(0x5500, 0x5507), 847 regmap_reg_range(0x5600, 0x5613), 848 regmap_reg_range(0x5800, 0x580f), 849 regmap_reg_range(0x5820, 0x5827), 850 regmap_reg_range(0x5830, 0x5837), 851 regmap_reg_range(0x5840, 0x584b), 852 regmap_reg_range(0x5900, 0x5907), 853 regmap_reg_range(0x5914, 0x591b), 854 regmap_reg_range(0x5920, 0x5920), 855 regmap_reg_range(0x5923, 0x5927), 856 regmap_reg_range(0x5a00, 0x5a03), 857 regmap_reg_range(0x5a04, 0x5a07), 858 regmap_reg_range(0x5b00, 0x5b01), 859 regmap_reg_range(0x5b04, 0x5b04), 860 regmap_reg_range(0x5c00, 0x5c05), 861 regmap_reg_range(0x5c08, 0x5c1b), 862 863 /* port 6 */ 864 regmap_reg_range(0x6000, 0x6001), 865 regmap_reg_range(0x6013, 0x6013), 866 regmap_reg_range(0x6017, 0x6017), 867 regmap_reg_range(0x601b, 0x601b), 868 regmap_reg_range(0x601f, 0x6020), 869 regmap_reg_range(0x6030, 0x6030), 870 regmap_reg_range(0x6300, 0x6301), 871 regmap_reg_range(0x6400, 0x6401), 872 regmap_reg_range(0x6403, 0x6403), 873 regmap_reg_range(0x6410, 0x6417), 874 regmap_reg_range(0x6420, 0x6423), 875 regmap_reg_range(0x6500, 0x6507), 876 regmap_reg_range(0x6600, 0x6613), 877 regmap_reg_range(0x6800, 0x680f), 878 regmap_reg_range(0x6820, 0x6827), 879 regmap_reg_range(0x6830, 0x6837), 880 regmap_reg_range(0x6840, 0x684b), 881 regmap_reg_range(0x6900, 0x6907), 882 regmap_reg_range(0x6914, 0x691b), 883 regmap_reg_range(0x6920, 0x6920), 884 regmap_reg_range(0x6923, 0x6927), 885 regmap_reg_range(0x6a00, 0x6a03), 886 regmap_reg_range(0x6a04, 0x6a07), 887 regmap_reg_range(0x6b00, 0x6b01), 888 regmap_reg_range(0x6b04, 0x6b04), 889 regmap_reg_range(0x6c00, 0x6c05), 890 regmap_reg_range(0x6c08, 0x6c1b), 891 892 /* port 7 */ 893 regmap_reg_range(0x7000, 0x7001), 894 regmap_reg_range(0x7013, 0x7013), 895 regmap_reg_range(0x7017, 0x7017), 896 regmap_reg_range(0x701b, 0x701b), 897 regmap_reg_range(0x701f, 0x7020), 898 regmap_reg_range(0x7030, 0x7030), 899 regmap_reg_range(0x7200, 0x7203), 900 regmap_reg_range(0x7206, 0x7207), 901 regmap_reg_range(0x7300, 0x7301), 902 regmap_reg_range(0x7400, 0x7401), 903 regmap_reg_range(0x7403, 0x7403), 904 regmap_reg_range(0x7410, 0x7417), 905 regmap_reg_range(0x7420, 0x7423), 906 regmap_reg_range(0x7500, 0x7507), 907 regmap_reg_range(0x7600, 0x7613), 908 regmap_reg_range(0x7800, 0x780f), 909 regmap_reg_range(0x7820, 0x7827), 910 regmap_reg_range(0x7830, 0x7837), 911 regmap_reg_range(0x7840, 0x784b), 912 regmap_reg_range(0x7900, 0x7907), 913 regmap_reg_range(0x7914, 0x791b), 914 regmap_reg_range(0x7920, 0x7920), 915 regmap_reg_range(0x7923, 0x7927), 916 regmap_reg_range(0x7a00, 0x7a03), 917 regmap_reg_range(0x7a04, 0x7a07), 918 regmap_reg_range(0x7b00, 0x7b01), 919 regmap_reg_range(0x7b04, 0x7b04), 920 regmap_reg_range(0x7c00, 0x7c05), 921 regmap_reg_range(0x7c08, 0x7c1b), 922 }; 923 924 static const struct regmap_access_table ksz9477_register_set = { 925 .yes_ranges = ksz9477_valid_regs, 926 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 927 }; 928 929 static const struct regmap_range ksz9896_valid_regs[] = { 930 regmap_reg_range(0x0000, 0x0003), 931 regmap_reg_range(0x0006, 0x0006), 932 regmap_reg_range(0x0010, 0x001f), 933 regmap_reg_range(0x0100, 0x0100), 934 regmap_reg_range(0x0103, 0x0107), 935 regmap_reg_range(0x010d, 0x010d), 936 regmap_reg_range(0x0110, 0x0113), 937 regmap_reg_range(0x0120, 0x0127), 938 regmap_reg_range(0x0201, 0x0201), 939 regmap_reg_range(0x0210, 0x0213), 940 regmap_reg_range(0x0300, 0x0300), 941 regmap_reg_range(0x0302, 0x030b), 942 regmap_reg_range(0x0310, 0x031b), 943 regmap_reg_range(0x0320, 0x032b), 944 regmap_reg_range(0x0330, 0x0336), 945 regmap_reg_range(0x0338, 0x033b), 946 regmap_reg_range(0x033e, 0x033e), 947 regmap_reg_range(0x0340, 0x035f), 948 regmap_reg_range(0x0370, 0x0370), 949 regmap_reg_range(0x0378, 0x0378), 950 regmap_reg_range(0x037c, 0x037d), 951 regmap_reg_range(0x0390, 0x0393), 952 regmap_reg_range(0x0400, 0x040e), 953 regmap_reg_range(0x0410, 0x042f), 954 955 /* port 1 */ 956 regmap_reg_range(0x1000, 0x1001), 957 regmap_reg_range(0x1013, 0x1013), 958 regmap_reg_range(0x1017, 0x1017), 959 regmap_reg_range(0x101b, 0x101b), 960 regmap_reg_range(0x101f, 0x1020), 961 regmap_reg_range(0x1030, 0x1030), 962 regmap_reg_range(0x1100, 0x1115), 963 regmap_reg_range(0x111a, 0x111f), 964 regmap_reg_range(0x1122, 0x1127), 965 regmap_reg_range(0x112a, 0x112b), 966 regmap_reg_range(0x1136, 0x1139), 967 regmap_reg_range(0x113e, 0x113f), 968 regmap_reg_range(0x1400, 0x1401), 969 regmap_reg_range(0x1403, 0x1403), 970 regmap_reg_range(0x1410, 0x1417), 971 regmap_reg_range(0x1420, 0x1423), 972 regmap_reg_range(0x1500, 0x1507), 973 regmap_reg_range(0x1600, 0x1612), 974 regmap_reg_range(0x1800, 0x180f), 975 regmap_reg_range(0x1820, 0x1827), 976 regmap_reg_range(0x1830, 0x1837), 977 regmap_reg_range(0x1840, 0x184b), 978 regmap_reg_range(0x1900, 0x1907), 979 regmap_reg_range(0x1914, 0x1915), 980 regmap_reg_range(0x1a00, 0x1a03), 981 regmap_reg_range(0x1a04, 0x1a07), 982 regmap_reg_range(0x1b00, 0x1b01), 983 regmap_reg_range(0x1b04, 0x1b04), 984 985 /* port 2 */ 986 regmap_reg_range(0x2000, 0x2001), 987 regmap_reg_range(0x2013, 0x2013), 988 regmap_reg_range(0x2017, 0x2017), 989 regmap_reg_range(0x201b, 0x201b), 990 regmap_reg_range(0x201f, 0x2020), 991 regmap_reg_range(0x2030, 0x2030), 992 regmap_reg_range(0x2100, 0x2115), 993 regmap_reg_range(0x211a, 0x211f), 994 regmap_reg_range(0x2122, 0x2127), 995 regmap_reg_range(0x212a, 0x212b), 996 regmap_reg_range(0x2136, 0x2139), 997 regmap_reg_range(0x213e, 0x213f), 998 regmap_reg_range(0x2400, 0x2401), 999 regmap_reg_range(0x2403, 0x2403), 1000 regmap_reg_range(0x2410, 0x2417), 1001 regmap_reg_range(0x2420, 0x2423), 1002 regmap_reg_range(0x2500, 0x2507), 1003 regmap_reg_range(0x2600, 0x2612), 1004 regmap_reg_range(0x2800, 0x280f), 1005 regmap_reg_range(0x2820, 0x2827), 1006 regmap_reg_range(0x2830, 0x2837), 1007 regmap_reg_range(0x2840, 0x284b), 1008 regmap_reg_range(0x2900, 0x2907), 1009 regmap_reg_range(0x2914, 0x2915), 1010 regmap_reg_range(0x2a00, 0x2a03), 1011 regmap_reg_range(0x2a04, 0x2a07), 1012 regmap_reg_range(0x2b00, 0x2b01), 1013 regmap_reg_range(0x2b04, 0x2b04), 1014 1015 /* port 3 */ 1016 regmap_reg_range(0x3000, 0x3001), 1017 regmap_reg_range(0x3013, 0x3013), 1018 regmap_reg_range(0x3017, 0x3017), 1019 regmap_reg_range(0x301b, 0x301b), 1020 regmap_reg_range(0x301f, 0x3020), 1021 regmap_reg_range(0x3030, 0x3030), 1022 regmap_reg_range(0x3100, 0x3115), 1023 regmap_reg_range(0x311a, 0x311f), 1024 regmap_reg_range(0x3122, 0x3127), 1025 regmap_reg_range(0x312a, 0x312b), 1026 regmap_reg_range(0x3136, 0x3139), 1027 regmap_reg_range(0x313e, 0x313f), 1028 regmap_reg_range(0x3400, 0x3401), 1029 regmap_reg_range(0x3403, 0x3403), 1030 regmap_reg_range(0x3410, 0x3417), 1031 regmap_reg_range(0x3420, 0x3423), 1032 regmap_reg_range(0x3500, 0x3507), 1033 regmap_reg_range(0x3600, 0x3612), 1034 regmap_reg_range(0x3800, 0x380f), 1035 regmap_reg_range(0x3820, 0x3827), 1036 regmap_reg_range(0x3830, 0x3837), 1037 regmap_reg_range(0x3840, 0x384b), 1038 regmap_reg_range(0x3900, 0x3907), 1039 regmap_reg_range(0x3914, 0x3915), 1040 regmap_reg_range(0x3a00, 0x3a03), 1041 regmap_reg_range(0x3a04, 0x3a07), 1042 regmap_reg_range(0x3b00, 0x3b01), 1043 regmap_reg_range(0x3b04, 0x3b04), 1044 1045 /* port 4 */ 1046 regmap_reg_range(0x4000, 0x4001), 1047 regmap_reg_range(0x4013, 0x4013), 1048 regmap_reg_range(0x4017, 0x4017), 1049 regmap_reg_range(0x401b, 0x401b), 1050 regmap_reg_range(0x401f, 0x4020), 1051 regmap_reg_range(0x4030, 0x4030), 1052 regmap_reg_range(0x4100, 0x4115), 1053 regmap_reg_range(0x411a, 0x411f), 1054 regmap_reg_range(0x4122, 0x4127), 1055 regmap_reg_range(0x412a, 0x412b), 1056 regmap_reg_range(0x4136, 0x4139), 1057 regmap_reg_range(0x413e, 0x413f), 1058 regmap_reg_range(0x4400, 0x4401), 1059 regmap_reg_range(0x4403, 0x4403), 1060 regmap_reg_range(0x4410, 0x4417), 1061 regmap_reg_range(0x4420, 0x4423), 1062 regmap_reg_range(0x4500, 0x4507), 1063 regmap_reg_range(0x4600, 0x4612), 1064 regmap_reg_range(0x4800, 0x480f), 1065 regmap_reg_range(0x4820, 0x4827), 1066 regmap_reg_range(0x4830, 0x4837), 1067 regmap_reg_range(0x4840, 0x484b), 1068 regmap_reg_range(0x4900, 0x4907), 1069 regmap_reg_range(0x4914, 0x4915), 1070 regmap_reg_range(0x4a00, 0x4a03), 1071 regmap_reg_range(0x4a04, 0x4a07), 1072 regmap_reg_range(0x4b00, 0x4b01), 1073 regmap_reg_range(0x4b04, 0x4b04), 1074 1075 /* port 5 */ 1076 regmap_reg_range(0x5000, 0x5001), 1077 regmap_reg_range(0x5013, 0x5013), 1078 regmap_reg_range(0x5017, 0x5017), 1079 regmap_reg_range(0x501b, 0x501b), 1080 regmap_reg_range(0x501f, 0x5020), 1081 regmap_reg_range(0x5030, 0x5030), 1082 regmap_reg_range(0x5100, 0x5115), 1083 regmap_reg_range(0x511a, 0x511f), 1084 regmap_reg_range(0x5122, 0x5127), 1085 regmap_reg_range(0x512a, 0x512b), 1086 regmap_reg_range(0x5136, 0x5139), 1087 regmap_reg_range(0x513e, 0x513f), 1088 regmap_reg_range(0x5400, 0x5401), 1089 regmap_reg_range(0x5403, 0x5403), 1090 regmap_reg_range(0x5410, 0x5417), 1091 regmap_reg_range(0x5420, 0x5423), 1092 regmap_reg_range(0x5500, 0x5507), 1093 regmap_reg_range(0x5600, 0x5612), 1094 regmap_reg_range(0x5800, 0x580f), 1095 regmap_reg_range(0x5820, 0x5827), 1096 regmap_reg_range(0x5830, 0x5837), 1097 regmap_reg_range(0x5840, 0x584b), 1098 regmap_reg_range(0x5900, 0x5907), 1099 regmap_reg_range(0x5914, 0x5915), 1100 regmap_reg_range(0x5a00, 0x5a03), 1101 regmap_reg_range(0x5a04, 0x5a07), 1102 regmap_reg_range(0x5b00, 0x5b01), 1103 regmap_reg_range(0x5b04, 0x5b04), 1104 1105 /* port 6 */ 1106 regmap_reg_range(0x6000, 0x6001), 1107 regmap_reg_range(0x6013, 0x6013), 1108 regmap_reg_range(0x6017, 0x6017), 1109 regmap_reg_range(0x601b, 0x601b), 1110 regmap_reg_range(0x601f, 0x6020), 1111 regmap_reg_range(0x6030, 0x6030), 1112 regmap_reg_range(0x6100, 0x6115), 1113 regmap_reg_range(0x611a, 0x611f), 1114 regmap_reg_range(0x6122, 0x6127), 1115 regmap_reg_range(0x612a, 0x612b), 1116 regmap_reg_range(0x6136, 0x6139), 1117 regmap_reg_range(0x613e, 0x613f), 1118 regmap_reg_range(0x6300, 0x6301), 1119 regmap_reg_range(0x6400, 0x6401), 1120 regmap_reg_range(0x6403, 0x6403), 1121 regmap_reg_range(0x6410, 0x6417), 1122 regmap_reg_range(0x6420, 0x6423), 1123 regmap_reg_range(0x6500, 0x6507), 1124 regmap_reg_range(0x6600, 0x6612), 1125 regmap_reg_range(0x6800, 0x680f), 1126 regmap_reg_range(0x6820, 0x6827), 1127 regmap_reg_range(0x6830, 0x6837), 1128 regmap_reg_range(0x6840, 0x684b), 1129 regmap_reg_range(0x6900, 0x6907), 1130 regmap_reg_range(0x6914, 0x6915), 1131 regmap_reg_range(0x6a00, 0x6a03), 1132 regmap_reg_range(0x6a04, 0x6a07), 1133 regmap_reg_range(0x6b00, 0x6b01), 1134 regmap_reg_range(0x6b04, 0x6b04), 1135 }; 1136 1137 static const struct regmap_access_table ksz9896_register_set = { 1138 .yes_ranges = ksz9896_valid_regs, 1139 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1140 }; 1141 1142 static const struct regmap_range ksz8873_valid_regs[] = { 1143 regmap_reg_range(0x00, 0x01), 1144 /* global control register */ 1145 regmap_reg_range(0x02, 0x0f), 1146 1147 /* port registers */ 1148 regmap_reg_range(0x10, 0x1d), 1149 regmap_reg_range(0x1e, 0x1f), 1150 regmap_reg_range(0x20, 0x2d), 1151 regmap_reg_range(0x2e, 0x2f), 1152 regmap_reg_range(0x30, 0x39), 1153 regmap_reg_range(0x3f, 0x3f), 1154 1155 /* advanced control registers */ 1156 regmap_reg_range(0x60, 0x6f), 1157 regmap_reg_range(0x70, 0x75), 1158 regmap_reg_range(0x76, 0x78), 1159 regmap_reg_range(0x79, 0x7a), 1160 regmap_reg_range(0x7b, 0x83), 1161 regmap_reg_range(0x8e, 0x99), 1162 regmap_reg_range(0x9a, 0xa5), 1163 regmap_reg_range(0xa6, 0xa6), 1164 regmap_reg_range(0xa7, 0xaa), 1165 regmap_reg_range(0xab, 0xae), 1166 regmap_reg_range(0xaf, 0xba), 1167 regmap_reg_range(0xbb, 0xbc), 1168 regmap_reg_range(0xbd, 0xbd), 1169 regmap_reg_range(0xc0, 0xc0), 1170 regmap_reg_range(0xc2, 0xc2), 1171 regmap_reg_range(0xc3, 0xc3), 1172 regmap_reg_range(0xc4, 0xc4), 1173 regmap_reg_range(0xc6, 0xc6), 1174 }; 1175 1176 static const struct regmap_access_table ksz8873_register_set = { 1177 .yes_ranges = ksz8873_valid_regs, 1178 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), 1179 }; 1180 1181 const struct ksz_chip_data ksz_switch_chips[] = { 1182 [KSZ8563] = { 1183 .chip_id = KSZ8563_CHIP_ID, 1184 .dev_name = "KSZ8563", 1185 .num_vlans = 4096, 1186 .num_alus = 4096, 1187 .num_statics = 16, 1188 .cpu_ports = 0x07, /* can be configured as cpu port */ 1189 .port_cnt = 3, /* total port count */ 1190 .port_nirqs = 3, 1191 .num_tx_queues = 4, 1192 .tc_cbs_supported = true, 1193 .tc_ets_supported = true, 1194 .ops = &ksz9477_dev_ops, 1195 .mib_names = ksz9477_mib_names, 1196 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1197 .reg_mib_cnt = MIB_COUNTER_NUM, 1198 .regs = ksz9477_regs, 1199 .masks = ksz9477_masks, 1200 .shifts = ksz9477_shifts, 1201 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1202 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1203 .supports_mii = {false, false, true}, 1204 .supports_rmii = {false, false, true}, 1205 .supports_rgmii = {false, false, true}, 1206 .internal_phy = {true, true, false}, 1207 .gbit_capable = {false, false, true}, 1208 .wr_table = &ksz8563_register_set, 1209 .rd_table = &ksz8563_register_set, 1210 }, 1211 1212 [KSZ8795] = { 1213 .chip_id = KSZ8795_CHIP_ID, 1214 .dev_name = "KSZ8795", 1215 .num_vlans = 4096, 1216 .num_alus = 0, 1217 .num_statics = 8, 1218 .cpu_ports = 0x10, /* can be configured as cpu port */ 1219 .port_cnt = 5, /* total cpu and user ports */ 1220 .num_tx_queues = 4, 1221 .ops = &ksz8_dev_ops, 1222 .ksz87xx_eee_link_erratum = true, 1223 .mib_names = ksz9477_mib_names, 1224 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1225 .reg_mib_cnt = MIB_COUNTER_NUM, 1226 .regs = ksz8795_regs, 1227 .masks = ksz8795_masks, 1228 .shifts = ksz8795_shifts, 1229 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1230 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1231 .supports_mii = {false, false, false, false, true}, 1232 .supports_rmii = {false, false, false, false, true}, 1233 .supports_rgmii = {false, false, false, false, true}, 1234 .internal_phy = {true, true, true, true, false}, 1235 }, 1236 1237 [KSZ8794] = { 1238 /* WARNING 1239 * ======= 1240 * KSZ8794 is similar to KSZ8795, except the port map 1241 * contains a gap between external and CPU ports, the 1242 * port map is NOT continuous. The per-port register 1243 * map is shifted accordingly too, i.e. registers at 1244 * offset 0x40 are NOT used on KSZ8794 and they ARE 1245 * used on KSZ8795 for external port 3. 1246 * external cpu 1247 * KSZ8794 0,1,2 4 1248 * KSZ8795 0,1,2,3 4 1249 * KSZ8765 0,1,2,3 4 1250 * port_cnt is configured as 5, even though it is 4 1251 */ 1252 .chip_id = KSZ8794_CHIP_ID, 1253 .dev_name = "KSZ8794", 1254 .num_vlans = 4096, 1255 .num_alus = 0, 1256 .num_statics = 8, 1257 .cpu_ports = 0x10, /* can be configured as cpu port */ 1258 .port_cnt = 5, /* total cpu and user ports */ 1259 .num_tx_queues = 4, 1260 .ops = &ksz8_dev_ops, 1261 .ksz87xx_eee_link_erratum = true, 1262 .mib_names = ksz9477_mib_names, 1263 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1264 .reg_mib_cnt = MIB_COUNTER_NUM, 1265 .regs = ksz8795_regs, 1266 .masks = ksz8795_masks, 1267 .shifts = ksz8795_shifts, 1268 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1269 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1270 .supports_mii = {false, false, false, false, true}, 1271 .supports_rmii = {false, false, false, false, true}, 1272 .supports_rgmii = {false, false, false, false, true}, 1273 .internal_phy = {true, true, true, false, false}, 1274 }, 1275 1276 [KSZ8765] = { 1277 .chip_id = KSZ8765_CHIP_ID, 1278 .dev_name = "KSZ8765", 1279 .num_vlans = 4096, 1280 .num_alus = 0, 1281 .num_statics = 8, 1282 .cpu_ports = 0x10, /* can be configured as cpu port */ 1283 .port_cnt = 5, /* total cpu and user ports */ 1284 .num_tx_queues = 4, 1285 .ops = &ksz8_dev_ops, 1286 .ksz87xx_eee_link_erratum = true, 1287 .mib_names = ksz9477_mib_names, 1288 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1289 .reg_mib_cnt = MIB_COUNTER_NUM, 1290 .regs = ksz8795_regs, 1291 .masks = ksz8795_masks, 1292 .shifts = ksz8795_shifts, 1293 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1294 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1295 .supports_mii = {false, false, false, false, true}, 1296 .supports_rmii = {false, false, false, false, true}, 1297 .supports_rgmii = {false, false, false, false, true}, 1298 .internal_phy = {true, true, true, true, false}, 1299 }, 1300 1301 [KSZ8830] = { 1302 .chip_id = KSZ8830_CHIP_ID, 1303 .dev_name = "KSZ8863/KSZ8873", 1304 .num_vlans = 16, 1305 .num_alus = 0, 1306 .num_statics = 8, 1307 .cpu_ports = 0x4, /* can be configured as cpu port */ 1308 .port_cnt = 3, 1309 .num_tx_queues = 4, 1310 .ops = &ksz8_dev_ops, 1311 .mib_names = ksz88xx_mib_names, 1312 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1313 .reg_mib_cnt = MIB_COUNTER_NUM, 1314 .regs = ksz8863_regs, 1315 .masks = ksz8863_masks, 1316 .shifts = ksz8863_shifts, 1317 .supports_mii = {false, false, true}, 1318 .supports_rmii = {false, false, true}, 1319 .internal_phy = {true, true, false}, 1320 .wr_table = &ksz8873_register_set, 1321 .rd_table = &ksz8873_register_set, 1322 }, 1323 1324 [KSZ9477] = { 1325 .chip_id = KSZ9477_CHIP_ID, 1326 .dev_name = "KSZ9477", 1327 .num_vlans = 4096, 1328 .num_alus = 4096, 1329 .num_statics = 16, 1330 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1331 .port_cnt = 7, /* total physical port count */ 1332 .port_nirqs = 4, 1333 .num_tx_queues = 4, 1334 .tc_cbs_supported = true, 1335 .tc_ets_supported = true, 1336 .ops = &ksz9477_dev_ops, 1337 .mib_names = ksz9477_mib_names, 1338 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1339 .reg_mib_cnt = MIB_COUNTER_NUM, 1340 .regs = ksz9477_regs, 1341 .masks = ksz9477_masks, 1342 .shifts = ksz9477_shifts, 1343 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1344 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1345 .supports_mii = {false, false, false, false, 1346 false, true, false}, 1347 .supports_rmii = {false, false, false, false, 1348 false, true, false}, 1349 .supports_rgmii = {false, false, false, false, 1350 false, true, false}, 1351 .internal_phy = {true, true, true, true, 1352 true, false, false}, 1353 .gbit_capable = {true, true, true, true, true, true, true}, 1354 .wr_table = &ksz9477_register_set, 1355 .rd_table = &ksz9477_register_set, 1356 }, 1357 1358 [KSZ9896] = { 1359 .chip_id = KSZ9896_CHIP_ID, 1360 .dev_name = "KSZ9896", 1361 .num_vlans = 4096, 1362 .num_alus = 4096, 1363 .num_statics = 16, 1364 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1365 .port_cnt = 6, /* total physical port count */ 1366 .port_nirqs = 2, 1367 .num_tx_queues = 4, 1368 .ops = &ksz9477_dev_ops, 1369 .mib_names = ksz9477_mib_names, 1370 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1371 .reg_mib_cnt = MIB_COUNTER_NUM, 1372 .regs = ksz9477_regs, 1373 .masks = ksz9477_masks, 1374 .shifts = ksz9477_shifts, 1375 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1376 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1377 .supports_mii = {false, false, false, false, 1378 false, true}, 1379 .supports_rmii = {false, false, false, false, 1380 false, true}, 1381 .supports_rgmii = {false, false, false, false, 1382 false, true}, 1383 .internal_phy = {true, true, true, true, 1384 true, false}, 1385 .gbit_capable = {true, true, true, true, true, true}, 1386 .wr_table = &ksz9896_register_set, 1387 .rd_table = &ksz9896_register_set, 1388 }, 1389 1390 [KSZ9897] = { 1391 .chip_id = KSZ9897_CHIP_ID, 1392 .dev_name = "KSZ9897", 1393 .num_vlans = 4096, 1394 .num_alus = 4096, 1395 .num_statics = 16, 1396 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1397 .port_cnt = 7, /* total physical port count */ 1398 .port_nirqs = 2, 1399 .num_tx_queues = 4, 1400 .ops = &ksz9477_dev_ops, 1401 .mib_names = ksz9477_mib_names, 1402 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1403 .reg_mib_cnt = MIB_COUNTER_NUM, 1404 .regs = ksz9477_regs, 1405 .masks = ksz9477_masks, 1406 .shifts = ksz9477_shifts, 1407 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1408 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1409 .supports_mii = {false, false, false, false, 1410 false, true, true}, 1411 .supports_rmii = {false, false, false, false, 1412 false, true, true}, 1413 .supports_rgmii = {false, false, false, false, 1414 false, true, true}, 1415 .internal_phy = {true, true, true, true, 1416 true, false, false}, 1417 .gbit_capable = {true, true, true, true, true, true, true}, 1418 }, 1419 1420 [KSZ9893] = { 1421 .chip_id = KSZ9893_CHIP_ID, 1422 .dev_name = "KSZ9893", 1423 .num_vlans = 4096, 1424 .num_alus = 4096, 1425 .num_statics = 16, 1426 .cpu_ports = 0x07, /* can be configured as cpu port */ 1427 .port_cnt = 3, /* total port count */ 1428 .port_nirqs = 2, 1429 .num_tx_queues = 4, 1430 .ops = &ksz9477_dev_ops, 1431 .mib_names = ksz9477_mib_names, 1432 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1433 .reg_mib_cnt = MIB_COUNTER_NUM, 1434 .regs = ksz9477_regs, 1435 .masks = ksz9477_masks, 1436 .shifts = ksz9477_shifts, 1437 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1438 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1439 .supports_mii = {false, false, true}, 1440 .supports_rmii = {false, false, true}, 1441 .supports_rgmii = {false, false, true}, 1442 .internal_phy = {true, true, false}, 1443 .gbit_capable = {true, true, true}, 1444 }, 1445 1446 [KSZ9563] = { 1447 .chip_id = KSZ9563_CHIP_ID, 1448 .dev_name = "KSZ9563", 1449 .num_vlans = 4096, 1450 .num_alus = 4096, 1451 .num_statics = 16, 1452 .cpu_ports = 0x07, /* can be configured as cpu port */ 1453 .port_cnt = 3, /* total port count */ 1454 .port_nirqs = 3, 1455 .num_tx_queues = 4, 1456 .tc_cbs_supported = true, 1457 .tc_ets_supported = true, 1458 .ops = &ksz9477_dev_ops, 1459 .mib_names = ksz9477_mib_names, 1460 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1461 .reg_mib_cnt = MIB_COUNTER_NUM, 1462 .regs = ksz9477_regs, 1463 .masks = ksz9477_masks, 1464 .shifts = ksz9477_shifts, 1465 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1466 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1467 .supports_mii = {false, false, true}, 1468 .supports_rmii = {false, false, true}, 1469 .supports_rgmii = {false, false, true}, 1470 .internal_phy = {true, true, false}, 1471 .gbit_capable = {true, true, true}, 1472 }, 1473 1474 [KSZ9567] = { 1475 .chip_id = KSZ9567_CHIP_ID, 1476 .dev_name = "KSZ9567", 1477 .num_vlans = 4096, 1478 .num_alus = 4096, 1479 .num_statics = 16, 1480 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1481 .port_cnt = 7, /* total physical port count */ 1482 .port_nirqs = 3, 1483 .num_tx_queues = 4, 1484 .tc_cbs_supported = true, 1485 .tc_ets_supported = true, 1486 .ops = &ksz9477_dev_ops, 1487 .mib_names = ksz9477_mib_names, 1488 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1489 .reg_mib_cnt = MIB_COUNTER_NUM, 1490 .regs = ksz9477_regs, 1491 .masks = ksz9477_masks, 1492 .shifts = ksz9477_shifts, 1493 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1494 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1495 .supports_mii = {false, false, false, false, 1496 false, true, true}, 1497 .supports_rmii = {false, false, false, false, 1498 false, true, true}, 1499 .supports_rgmii = {false, false, false, false, 1500 false, true, true}, 1501 .internal_phy = {true, true, true, true, 1502 true, false, false}, 1503 .gbit_capable = {true, true, true, true, true, true, true}, 1504 }, 1505 1506 [LAN9370] = { 1507 .chip_id = LAN9370_CHIP_ID, 1508 .dev_name = "LAN9370", 1509 .num_vlans = 4096, 1510 .num_alus = 1024, 1511 .num_statics = 256, 1512 .cpu_ports = 0x10, /* can be configured as cpu port */ 1513 .port_cnt = 5, /* total physical port count */ 1514 .port_nirqs = 6, 1515 .num_tx_queues = 8, 1516 .tc_cbs_supported = true, 1517 .tc_ets_supported = true, 1518 .ops = &lan937x_dev_ops, 1519 .mib_names = ksz9477_mib_names, 1520 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1521 .reg_mib_cnt = MIB_COUNTER_NUM, 1522 .regs = ksz9477_regs, 1523 .masks = lan937x_masks, 1524 .shifts = lan937x_shifts, 1525 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1526 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1527 .supports_mii = {false, false, false, false, true}, 1528 .supports_rmii = {false, false, false, false, true}, 1529 .supports_rgmii = {false, false, false, false, true}, 1530 .internal_phy = {true, true, true, true, false}, 1531 }, 1532 1533 [LAN9371] = { 1534 .chip_id = LAN9371_CHIP_ID, 1535 .dev_name = "LAN9371", 1536 .num_vlans = 4096, 1537 .num_alus = 1024, 1538 .num_statics = 256, 1539 .cpu_ports = 0x30, /* can be configured as cpu port */ 1540 .port_cnt = 6, /* total physical port count */ 1541 .port_nirqs = 6, 1542 .num_tx_queues = 8, 1543 .tc_cbs_supported = true, 1544 .tc_ets_supported = true, 1545 .ops = &lan937x_dev_ops, 1546 .mib_names = ksz9477_mib_names, 1547 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1548 .reg_mib_cnt = MIB_COUNTER_NUM, 1549 .regs = ksz9477_regs, 1550 .masks = lan937x_masks, 1551 .shifts = lan937x_shifts, 1552 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1553 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1554 .supports_mii = {false, false, false, false, true, true}, 1555 .supports_rmii = {false, false, false, false, true, true}, 1556 .supports_rgmii = {false, false, false, false, true, true}, 1557 .internal_phy = {true, true, true, true, false, false}, 1558 }, 1559 1560 [LAN9372] = { 1561 .chip_id = LAN9372_CHIP_ID, 1562 .dev_name = "LAN9372", 1563 .num_vlans = 4096, 1564 .num_alus = 1024, 1565 .num_statics = 256, 1566 .cpu_ports = 0x30, /* can be configured as cpu port */ 1567 .port_cnt = 8, /* total physical port count */ 1568 .port_nirqs = 6, 1569 .num_tx_queues = 8, 1570 .tc_cbs_supported = true, 1571 .tc_ets_supported = true, 1572 .ops = &lan937x_dev_ops, 1573 .mib_names = ksz9477_mib_names, 1574 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1575 .reg_mib_cnt = MIB_COUNTER_NUM, 1576 .regs = ksz9477_regs, 1577 .masks = lan937x_masks, 1578 .shifts = lan937x_shifts, 1579 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1580 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1581 .supports_mii = {false, false, false, false, 1582 true, true, false, false}, 1583 .supports_rmii = {false, false, false, false, 1584 true, true, false, false}, 1585 .supports_rgmii = {false, false, false, false, 1586 true, true, false, false}, 1587 .internal_phy = {true, true, true, true, 1588 false, false, true, true}, 1589 }, 1590 1591 [LAN9373] = { 1592 .chip_id = LAN9373_CHIP_ID, 1593 .dev_name = "LAN9373", 1594 .num_vlans = 4096, 1595 .num_alus = 1024, 1596 .num_statics = 256, 1597 .cpu_ports = 0x38, /* can be configured as cpu port */ 1598 .port_cnt = 5, /* total physical port count */ 1599 .port_nirqs = 6, 1600 .num_tx_queues = 8, 1601 .tc_cbs_supported = true, 1602 .tc_ets_supported = true, 1603 .ops = &lan937x_dev_ops, 1604 .mib_names = ksz9477_mib_names, 1605 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1606 .reg_mib_cnt = MIB_COUNTER_NUM, 1607 .regs = ksz9477_regs, 1608 .masks = lan937x_masks, 1609 .shifts = lan937x_shifts, 1610 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1611 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1612 .supports_mii = {false, false, false, false, 1613 true, true, false, false}, 1614 .supports_rmii = {false, false, false, false, 1615 true, true, false, false}, 1616 .supports_rgmii = {false, false, false, false, 1617 true, true, false, false}, 1618 .internal_phy = {true, true, true, false, 1619 false, false, true, true}, 1620 }, 1621 1622 [LAN9374] = { 1623 .chip_id = LAN9374_CHIP_ID, 1624 .dev_name = "LAN9374", 1625 .num_vlans = 4096, 1626 .num_alus = 1024, 1627 .num_statics = 256, 1628 .cpu_ports = 0x30, /* can be configured as cpu port */ 1629 .port_cnt = 8, /* total physical port count */ 1630 .port_nirqs = 6, 1631 .num_tx_queues = 8, 1632 .tc_cbs_supported = true, 1633 .tc_ets_supported = true, 1634 .ops = &lan937x_dev_ops, 1635 .mib_names = ksz9477_mib_names, 1636 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1637 .reg_mib_cnt = MIB_COUNTER_NUM, 1638 .regs = ksz9477_regs, 1639 .masks = lan937x_masks, 1640 .shifts = lan937x_shifts, 1641 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1642 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1643 .supports_mii = {false, false, false, false, 1644 true, true, false, false}, 1645 .supports_rmii = {false, false, false, false, 1646 true, true, false, false}, 1647 .supports_rgmii = {false, false, false, false, 1648 true, true, false, false}, 1649 .internal_phy = {true, true, true, true, 1650 false, false, true, true}, 1651 }, 1652 }; 1653 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1654 1655 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1656 { 1657 int i; 1658 1659 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1660 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1661 1662 if (chip->chip_id == prod_num) 1663 return chip; 1664 } 1665 1666 return NULL; 1667 } 1668 1669 static int ksz_check_device_id(struct ksz_device *dev) 1670 { 1671 const struct ksz_chip_data *dt_chip_data; 1672 1673 dt_chip_data = of_device_get_match_data(dev->dev); 1674 1675 /* Check for Device Tree and Chip ID */ 1676 if (dt_chip_data->chip_id != dev->chip_id) { 1677 dev_err(dev->dev, 1678 "Device tree specifies chip %s but found %s, please fix it!\n", 1679 dt_chip_data->dev_name, dev->info->dev_name); 1680 return -ENODEV; 1681 } 1682 1683 return 0; 1684 } 1685 1686 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1687 struct phylink_config *config) 1688 { 1689 struct ksz_device *dev = ds->priv; 1690 1691 if (dev->info->supports_mii[port]) 1692 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1693 1694 if (dev->info->supports_rmii[port]) 1695 __set_bit(PHY_INTERFACE_MODE_RMII, 1696 config->supported_interfaces); 1697 1698 if (dev->info->supports_rgmii[port]) 1699 phy_interface_set_rgmii(config->supported_interfaces); 1700 1701 if (dev->info->internal_phy[port]) { 1702 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1703 config->supported_interfaces); 1704 /* Compatibility for phylib's default interface type when the 1705 * phy-mode property is absent 1706 */ 1707 __set_bit(PHY_INTERFACE_MODE_GMII, 1708 config->supported_interfaces); 1709 } 1710 1711 if (dev->dev_ops->get_caps) 1712 dev->dev_ops->get_caps(dev, port, config); 1713 } 1714 1715 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 1716 { 1717 struct ethtool_pause_stats *pstats; 1718 struct rtnl_link_stats64 *stats; 1719 struct ksz_stats_raw *raw; 1720 struct ksz_port_mib *mib; 1721 1722 mib = &dev->ports[port].mib; 1723 stats = &mib->stats64; 1724 pstats = &mib->pause_stats; 1725 raw = (struct ksz_stats_raw *)mib->counters; 1726 1727 spin_lock(&mib->stats64_lock); 1728 1729 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1730 raw->rx_pause; 1731 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1732 raw->tx_pause; 1733 1734 /* HW counters are counting bytes + FCS which is not acceptable 1735 * for rtnl_link_stats64 interface 1736 */ 1737 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 1738 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 1739 1740 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1741 raw->rx_oversize; 1742 1743 stats->rx_crc_errors = raw->rx_crc_err; 1744 stats->rx_frame_errors = raw->rx_align_err; 1745 stats->rx_dropped = raw->rx_discards; 1746 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1747 stats->rx_frame_errors + stats->rx_dropped; 1748 1749 stats->tx_window_errors = raw->tx_late_col; 1750 stats->tx_fifo_errors = raw->tx_discards; 1751 stats->tx_aborted_errors = raw->tx_exc_col; 1752 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1753 stats->tx_aborted_errors; 1754 1755 stats->multicast = raw->rx_mcast; 1756 stats->collisions = raw->tx_total_col; 1757 1758 pstats->tx_pause_frames = raw->tx_pause; 1759 pstats->rx_pause_frames = raw->rx_pause; 1760 1761 spin_unlock(&mib->stats64_lock); 1762 } 1763 1764 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 1765 { 1766 struct ethtool_pause_stats *pstats; 1767 struct rtnl_link_stats64 *stats; 1768 struct ksz88xx_stats_raw *raw; 1769 struct ksz_port_mib *mib; 1770 1771 mib = &dev->ports[port].mib; 1772 stats = &mib->stats64; 1773 pstats = &mib->pause_stats; 1774 raw = (struct ksz88xx_stats_raw *)mib->counters; 1775 1776 spin_lock(&mib->stats64_lock); 1777 1778 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1779 raw->rx_pause; 1780 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1781 raw->tx_pause; 1782 1783 /* HW counters are counting bytes + FCS which is not acceptable 1784 * for rtnl_link_stats64 interface 1785 */ 1786 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 1787 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 1788 1789 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1790 raw->rx_oversize; 1791 1792 stats->rx_crc_errors = raw->rx_crc_err; 1793 stats->rx_frame_errors = raw->rx_align_err; 1794 stats->rx_dropped = raw->rx_discards; 1795 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1796 stats->rx_frame_errors + stats->rx_dropped; 1797 1798 stats->tx_window_errors = raw->tx_late_col; 1799 stats->tx_fifo_errors = raw->tx_discards; 1800 stats->tx_aborted_errors = raw->tx_exc_col; 1801 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1802 stats->tx_aborted_errors; 1803 1804 stats->multicast = raw->rx_mcast; 1805 stats->collisions = raw->tx_total_col; 1806 1807 pstats->tx_pause_frames = raw->tx_pause; 1808 pstats->rx_pause_frames = raw->rx_pause; 1809 1810 spin_unlock(&mib->stats64_lock); 1811 } 1812 1813 static void ksz_get_stats64(struct dsa_switch *ds, int port, 1814 struct rtnl_link_stats64 *s) 1815 { 1816 struct ksz_device *dev = ds->priv; 1817 struct ksz_port_mib *mib; 1818 1819 mib = &dev->ports[port].mib; 1820 1821 spin_lock(&mib->stats64_lock); 1822 memcpy(s, &mib->stats64, sizeof(*s)); 1823 spin_unlock(&mib->stats64_lock); 1824 } 1825 1826 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 1827 struct ethtool_pause_stats *pause_stats) 1828 { 1829 struct ksz_device *dev = ds->priv; 1830 struct ksz_port_mib *mib; 1831 1832 mib = &dev->ports[port].mib; 1833 1834 spin_lock(&mib->stats64_lock); 1835 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 1836 spin_unlock(&mib->stats64_lock); 1837 } 1838 1839 static void ksz_get_strings(struct dsa_switch *ds, int port, 1840 u32 stringset, uint8_t *buf) 1841 { 1842 struct ksz_device *dev = ds->priv; 1843 int i; 1844 1845 if (stringset != ETH_SS_STATS) 1846 return; 1847 1848 for (i = 0; i < dev->info->mib_cnt; i++) { 1849 memcpy(buf + i * ETH_GSTRING_LEN, 1850 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 1851 } 1852 } 1853 1854 static void ksz_update_port_member(struct ksz_device *dev, int port) 1855 { 1856 struct ksz_port *p = &dev->ports[port]; 1857 struct dsa_switch *ds = dev->ds; 1858 u8 port_member = 0, cpu_port; 1859 const struct dsa_port *dp; 1860 int i, j; 1861 1862 if (!dsa_is_user_port(ds, port)) 1863 return; 1864 1865 dp = dsa_to_port(ds, port); 1866 cpu_port = BIT(dsa_upstream_port(ds, port)); 1867 1868 for (i = 0; i < ds->num_ports; i++) { 1869 const struct dsa_port *other_dp = dsa_to_port(ds, i); 1870 struct ksz_port *other_p = &dev->ports[i]; 1871 u8 val = 0; 1872 1873 if (!dsa_is_user_port(ds, i)) 1874 continue; 1875 if (port == i) 1876 continue; 1877 if (!dsa_port_bridge_same(dp, other_dp)) 1878 continue; 1879 if (other_p->stp_state != BR_STATE_FORWARDING) 1880 continue; 1881 1882 if (p->stp_state == BR_STATE_FORWARDING) { 1883 val |= BIT(port); 1884 port_member |= BIT(i); 1885 } 1886 1887 /* Retain port [i]'s relationship to other ports than [port] */ 1888 for (j = 0; j < ds->num_ports; j++) { 1889 const struct dsa_port *third_dp; 1890 struct ksz_port *third_p; 1891 1892 if (j == i) 1893 continue; 1894 if (j == port) 1895 continue; 1896 if (!dsa_is_user_port(ds, j)) 1897 continue; 1898 third_p = &dev->ports[j]; 1899 if (third_p->stp_state != BR_STATE_FORWARDING) 1900 continue; 1901 third_dp = dsa_to_port(ds, j); 1902 if (dsa_port_bridge_same(other_dp, third_dp)) 1903 val |= BIT(j); 1904 } 1905 1906 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 1907 } 1908 1909 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 1910 } 1911 1912 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 1913 { 1914 struct ksz_device *dev = bus->priv; 1915 u16 val; 1916 int ret; 1917 1918 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 1919 if (ret < 0) 1920 return ret; 1921 1922 return val; 1923 } 1924 1925 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 1926 u16 val) 1927 { 1928 struct ksz_device *dev = bus->priv; 1929 1930 return dev->dev_ops->w_phy(dev, addr, regnum, val); 1931 } 1932 1933 static int ksz_irq_phy_setup(struct ksz_device *dev) 1934 { 1935 struct dsa_switch *ds = dev->ds; 1936 int phy; 1937 int irq; 1938 int ret; 1939 1940 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) { 1941 if (BIT(phy) & ds->phys_mii_mask) { 1942 irq = irq_find_mapping(dev->ports[phy].pirq.domain, 1943 PORT_SRC_PHY_INT); 1944 if (irq < 0) { 1945 ret = irq; 1946 goto out; 1947 } 1948 ds->slave_mii_bus->irq[phy] = irq; 1949 } 1950 } 1951 return 0; 1952 out: 1953 while (phy--) 1954 if (BIT(phy) & ds->phys_mii_mask) 1955 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]); 1956 1957 return ret; 1958 } 1959 1960 static void ksz_irq_phy_free(struct ksz_device *dev) 1961 { 1962 struct dsa_switch *ds = dev->ds; 1963 int phy; 1964 1965 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) 1966 if (BIT(phy) & ds->phys_mii_mask) 1967 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]); 1968 } 1969 1970 static int ksz_mdio_register(struct ksz_device *dev) 1971 { 1972 struct dsa_switch *ds = dev->ds; 1973 struct device_node *mdio_np; 1974 struct mii_bus *bus; 1975 int ret; 1976 1977 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 1978 if (!mdio_np) 1979 return 0; 1980 1981 bus = devm_mdiobus_alloc(ds->dev); 1982 if (!bus) { 1983 of_node_put(mdio_np); 1984 return -ENOMEM; 1985 } 1986 1987 bus->priv = dev; 1988 bus->read = ksz_sw_mdio_read; 1989 bus->write = ksz_sw_mdio_write; 1990 bus->name = "ksz slave smi"; 1991 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 1992 bus->parent = ds->dev; 1993 bus->phy_mask = ~ds->phys_mii_mask; 1994 1995 ds->slave_mii_bus = bus; 1996 1997 if (dev->irq > 0) { 1998 ret = ksz_irq_phy_setup(dev); 1999 if (ret) { 2000 of_node_put(mdio_np); 2001 return ret; 2002 } 2003 } 2004 2005 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 2006 if (ret) { 2007 dev_err(ds->dev, "unable to register MDIO bus %s\n", 2008 bus->id); 2009 if (dev->irq > 0) 2010 ksz_irq_phy_free(dev); 2011 } 2012 2013 of_node_put(mdio_np); 2014 2015 return ret; 2016 } 2017 2018 static void ksz_irq_mask(struct irq_data *d) 2019 { 2020 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2021 2022 kirq->masked |= BIT(d->hwirq); 2023 } 2024 2025 static void ksz_irq_unmask(struct irq_data *d) 2026 { 2027 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2028 2029 kirq->masked &= ~BIT(d->hwirq); 2030 } 2031 2032 static void ksz_irq_bus_lock(struct irq_data *d) 2033 { 2034 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2035 2036 mutex_lock(&kirq->dev->lock_irq); 2037 } 2038 2039 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 2040 { 2041 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2042 struct ksz_device *dev = kirq->dev; 2043 int ret; 2044 2045 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked); 2046 if (ret) 2047 dev_err(dev->dev, "failed to change IRQ mask\n"); 2048 2049 mutex_unlock(&dev->lock_irq); 2050 } 2051 2052 static const struct irq_chip ksz_irq_chip = { 2053 .name = "ksz-irq", 2054 .irq_mask = ksz_irq_mask, 2055 .irq_unmask = ksz_irq_unmask, 2056 .irq_bus_lock = ksz_irq_bus_lock, 2057 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 2058 }; 2059 2060 static int ksz_irq_domain_map(struct irq_domain *d, 2061 unsigned int irq, irq_hw_number_t hwirq) 2062 { 2063 irq_set_chip_data(irq, d->host_data); 2064 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 2065 irq_set_noprobe(irq); 2066 2067 return 0; 2068 } 2069 2070 static const struct irq_domain_ops ksz_irq_domain_ops = { 2071 .map = ksz_irq_domain_map, 2072 .xlate = irq_domain_xlate_twocell, 2073 }; 2074 2075 static void ksz_irq_free(struct ksz_irq *kirq) 2076 { 2077 int irq, virq; 2078 2079 free_irq(kirq->irq_num, kirq); 2080 2081 for (irq = 0; irq < kirq->nirqs; irq++) { 2082 virq = irq_find_mapping(kirq->domain, irq); 2083 irq_dispose_mapping(virq); 2084 } 2085 2086 irq_domain_remove(kirq->domain); 2087 } 2088 2089 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 2090 { 2091 struct ksz_irq *kirq = dev_id; 2092 unsigned int nhandled = 0; 2093 struct ksz_device *dev; 2094 unsigned int sub_irq; 2095 u8 data; 2096 int ret; 2097 u8 n; 2098 2099 dev = kirq->dev; 2100 2101 /* Read interrupt status register */ 2102 ret = ksz_read8(dev, kirq->reg_status, &data); 2103 if (ret) 2104 goto out; 2105 2106 for (n = 0; n < kirq->nirqs; ++n) { 2107 if (data & BIT(n)) { 2108 sub_irq = irq_find_mapping(kirq->domain, n); 2109 handle_nested_irq(sub_irq); 2110 ++nhandled; 2111 } 2112 } 2113 out: 2114 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2115 } 2116 2117 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 2118 { 2119 int ret, n; 2120 2121 kirq->dev = dev; 2122 kirq->masked = ~0; 2123 2124 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0, 2125 &ksz_irq_domain_ops, kirq); 2126 if (!kirq->domain) 2127 return -ENOMEM; 2128 2129 for (n = 0; n < kirq->nirqs; n++) 2130 irq_create_mapping(kirq->domain, n); 2131 2132 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2133 IRQF_ONESHOT, kirq->name, kirq); 2134 if (ret) 2135 goto out; 2136 2137 return 0; 2138 2139 out: 2140 ksz_irq_free(kirq); 2141 2142 return ret; 2143 } 2144 2145 static int ksz_girq_setup(struct ksz_device *dev) 2146 { 2147 struct ksz_irq *girq = &dev->girq; 2148 2149 girq->nirqs = dev->info->port_cnt; 2150 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2151 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2152 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2153 2154 girq->irq_num = dev->irq; 2155 2156 return ksz_irq_common_setup(dev, girq); 2157 } 2158 2159 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2160 { 2161 struct ksz_irq *pirq = &dev->ports[p].pirq; 2162 2163 pirq->nirqs = dev->info->port_nirqs; 2164 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2165 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2166 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2167 2168 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2169 if (pirq->irq_num < 0) 2170 return pirq->irq_num; 2171 2172 return ksz_irq_common_setup(dev, pirq); 2173 } 2174 2175 static int ksz_setup(struct dsa_switch *ds) 2176 { 2177 struct ksz_device *dev = ds->priv; 2178 struct dsa_port *dp; 2179 struct ksz_port *p; 2180 const u16 *regs; 2181 int ret; 2182 2183 regs = dev->info->regs; 2184 2185 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2186 dev->info->num_vlans, GFP_KERNEL); 2187 if (!dev->vlan_cache) 2188 return -ENOMEM; 2189 2190 ret = dev->dev_ops->reset(dev); 2191 if (ret) { 2192 dev_err(ds->dev, "failed to reset switch\n"); 2193 return ret; 2194 } 2195 2196 /* set broadcast storm protection 10% rate */ 2197 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2198 BROADCAST_STORM_RATE, 2199 (BROADCAST_STORM_VALUE * 2200 BROADCAST_STORM_PROT_RATE) / 100); 2201 2202 dev->dev_ops->config_cpu_port(ds); 2203 2204 dev->dev_ops->enable_stp_addr(dev); 2205 2206 ds->num_tx_queues = dev->info->num_tx_queues; 2207 2208 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 2209 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2210 2211 ksz_init_mib_timer(dev); 2212 2213 ds->configure_vlan_while_not_filtering = false; 2214 2215 if (dev->dev_ops->setup) { 2216 ret = dev->dev_ops->setup(ds); 2217 if (ret) 2218 return ret; 2219 } 2220 2221 /* Start with learning disabled on standalone user ports, and enabled 2222 * on the CPU port. In lack of other finer mechanisms, learning on the 2223 * CPU port will avoid flooding bridge local addresses on the network 2224 * in some cases. 2225 */ 2226 p = &dev->ports[dev->cpu_port]; 2227 p->learning = true; 2228 2229 if (dev->irq > 0) { 2230 ret = ksz_girq_setup(dev); 2231 if (ret) 2232 return ret; 2233 2234 dsa_switch_for_each_user_port(dp, dev->ds) { 2235 ret = ksz_pirq_setup(dev, dp->index); 2236 if (ret) 2237 goto out_girq; 2238 2239 ret = ksz_ptp_irq_setup(ds, dp->index); 2240 if (ret) 2241 goto out_pirq; 2242 } 2243 } 2244 2245 ret = ksz_ptp_clock_register(ds); 2246 if (ret) { 2247 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret); 2248 goto out_ptpirq; 2249 } 2250 2251 ret = ksz_mdio_register(dev); 2252 if (ret < 0) { 2253 dev_err(dev->dev, "failed to register the mdio"); 2254 goto out_ptp_clock_unregister; 2255 } 2256 2257 /* start switch */ 2258 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 2259 SW_START, SW_START); 2260 2261 return 0; 2262 2263 out_ptp_clock_unregister: 2264 ksz_ptp_clock_unregister(ds); 2265 out_ptpirq: 2266 if (dev->irq > 0) 2267 dsa_switch_for_each_user_port(dp, dev->ds) 2268 ksz_ptp_irq_free(ds, dp->index); 2269 out_pirq: 2270 if (dev->irq > 0) 2271 dsa_switch_for_each_user_port(dp, dev->ds) 2272 ksz_irq_free(&dev->ports[dp->index].pirq); 2273 out_girq: 2274 if (dev->irq > 0) 2275 ksz_irq_free(&dev->girq); 2276 2277 return ret; 2278 } 2279 2280 static void ksz_teardown(struct dsa_switch *ds) 2281 { 2282 struct ksz_device *dev = ds->priv; 2283 struct dsa_port *dp; 2284 2285 ksz_ptp_clock_unregister(ds); 2286 2287 if (dev->irq > 0) { 2288 dsa_switch_for_each_user_port(dp, dev->ds) { 2289 ksz_ptp_irq_free(ds, dp->index); 2290 2291 ksz_irq_free(&dev->ports[dp->index].pirq); 2292 } 2293 2294 ksz_irq_free(&dev->girq); 2295 } 2296 2297 if (dev->dev_ops->teardown) 2298 dev->dev_ops->teardown(ds); 2299 } 2300 2301 static void port_r_cnt(struct ksz_device *dev, int port) 2302 { 2303 struct ksz_port_mib *mib = &dev->ports[port].mib; 2304 u64 *dropped; 2305 2306 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2307 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2308 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2309 &mib->counters[mib->cnt_ptr]); 2310 ++mib->cnt_ptr; 2311 } 2312 2313 /* last one in storage */ 2314 dropped = &mib->counters[dev->info->mib_cnt]; 2315 2316 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2317 while (mib->cnt_ptr < dev->info->mib_cnt) { 2318 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2319 dropped, &mib->counters[mib->cnt_ptr]); 2320 ++mib->cnt_ptr; 2321 } 2322 mib->cnt_ptr = 0; 2323 } 2324 2325 static void ksz_mib_read_work(struct work_struct *work) 2326 { 2327 struct ksz_device *dev = container_of(work, struct ksz_device, 2328 mib_read.work); 2329 struct ksz_port_mib *mib; 2330 struct ksz_port *p; 2331 int i; 2332 2333 for (i = 0; i < dev->info->port_cnt; i++) { 2334 if (dsa_is_unused_port(dev->ds, i)) 2335 continue; 2336 2337 p = &dev->ports[i]; 2338 mib = &p->mib; 2339 mutex_lock(&mib->cnt_mutex); 2340 2341 /* Only read MIB counters when the port is told to do. 2342 * If not, read only dropped counters when link is not up. 2343 */ 2344 if (!p->read) { 2345 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 2346 2347 if (!netif_carrier_ok(dp->slave)) 2348 mib->cnt_ptr = dev->info->reg_mib_cnt; 2349 } 2350 port_r_cnt(dev, i); 2351 p->read = false; 2352 2353 if (dev->dev_ops->r_mib_stat64) 2354 dev->dev_ops->r_mib_stat64(dev, i); 2355 2356 mutex_unlock(&mib->cnt_mutex); 2357 } 2358 2359 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 2360 } 2361 2362 void ksz_init_mib_timer(struct ksz_device *dev) 2363 { 2364 int i; 2365 2366 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 2367 2368 for (i = 0; i < dev->info->port_cnt; i++) { 2369 struct ksz_port_mib *mib = &dev->ports[i].mib; 2370 2371 dev->dev_ops->port_init_cnt(dev, i); 2372 2373 mib->cnt_ptr = 0; 2374 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 2375 } 2376 } 2377 2378 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 2379 { 2380 struct ksz_device *dev = ds->priv; 2381 u16 val = 0xffff; 2382 int ret; 2383 2384 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 2385 if (ret) 2386 return ret; 2387 2388 return val; 2389 } 2390 2391 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 2392 { 2393 struct ksz_device *dev = ds->priv; 2394 int ret; 2395 2396 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 2397 if (ret) 2398 return ret; 2399 2400 return 0; 2401 } 2402 2403 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 2404 { 2405 struct ksz_device *dev = ds->priv; 2406 2407 switch (dev->chip_id) { 2408 case KSZ8830_CHIP_ID: 2409 /* Silicon Errata Sheet (DS80000830A): 2410 * Port 1 does not work with LinkMD Cable-Testing. 2411 * Port 1 does not respond to received PAUSE control frames. 2412 */ 2413 if (!port) 2414 return MICREL_KSZ8_P1_ERRATA; 2415 break; 2416 case KSZ9477_CHIP_ID: 2417 /* KSZ9477 Errata DS80000754C 2418 * 2419 * Module 4: Energy Efficient Ethernet (EEE) feature select must 2420 * be manually disabled 2421 * The EEE feature is enabled by default, but it is not fully 2422 * operational. It must be manually disabled through register 2423 * controls. If not disabled, the PHY ports can auto-negotiate 2424 * to enable EEE, and this feature can cause link drops when 2425 * linked to another device supporting EEE. 2426 */ 2427 return MICREL_NO_EEE; 2428 } 2429 2430 return 0; 2431 } 2432 2433 static void ksz_mac_link_down(struct dsa_switch *ds, int port, 2434 unsigned int mode, phy_interface_t interface) 2435 { 2436 struct ksz_device *dev = ds->priv; 2437 struct ksz_port *p = &dev->ports[port]; 2438 2439 /* Read all MIB counters when the link is going down. */ 2440 p->read = true; 2441 /* timer started */ 2442 if (dev->mib_read_interval) 2443 schedule_delayed_work(&dev->mib_read, 0); 2444 } 2445 2446 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 2447 { 2448 struct ksz_device *dev = ds->priv; 2449 2450 if (sset != ETH_SS_STATS) 2451 return 0; 2452 2453 return dev->info->mib_cnt; 2454 } 2455 2456 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 2457 uint64_t *buf) 2458 { 2459 const struct dsa_port *dp = dsa_to_port(ds, port); 2460 struct ksz_device *dev = ds->priv; 2461 struct ksz_port_mib *mib; 2462 2463 mib = &dev->ports[port].mib; 2464 mutex_lock(&mib->cnt_mutex); 2465 2466 /* Only read dropped counters if no link. */ 2467 if (!netif_carrier_ok(dp->slave)) 2468 mib->cnt_ptr = dev->info->reg_mib_cnt; 2469 port_r_cnt(dev, port); 2470 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 2471 mutex_unlock(&mib->cnt_mutex); 2472 } 2473 2474 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 2475 struct dsa_bridge bridge, 2476 bool *tx_fwd_offload, 2477 struct netlink_ext_ack *extack) 2478 { 2479 /* port_stp_state_set() will be called after to put the port in 2480 * appropriate state so there is no need to do anything. 2481 */ 2482 2483 return 0; 2484 } 2485 2486 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 2487 struct dsa_bridge bridge) 2488 { 2489 /* port_stp_state_set() will be called after to put the port in 2490 * forwarding state so there is no need to do anything. 2491 */ 2492 } 2493 2494 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 2495 { 2496 struct ksz_device *dev = ds->priv; 2497 2498 dev->dev_ops->flush_dyn_mac_table(dev, port); 2499 } 2500 2501 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 2502 { 2503 struct ksz_device *dev = ds->priv; 2504 2505 if (!dev->dev_ops->set_ageing_time) 2506 return -EOPNOTSUPP; 2507 2508 return dev->dev_ops->set_ageing_time(dev, msecs); 2509 } 2510 2511 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 2512 const unsigned char *addr, u16 vid, 2513 struct dsa_db db) 2514 { 2515 struct ksz_device *dev = ds->priv; 2516 2517 if (!dev->dev_ops->fdb_add) 2518 return -EOPNOTSUPP; 2519 2520 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 2521 } 2522 2523 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 2524 const unsigned char *addr, 2525 u16 vid, struct dsa_db db) 2526 { 2527 struct ksz_device *dev = ds->priv; 2528 2529 if (!dev->dev_ops->fdb_del) 2530 return -EOPNOTSUPP; 2531 2532 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 2533 } 2534 2535 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 2536 dsa_fdb_dump_cb_t *cb, void *data) 2537 { 2538 struct ksz_device *dev = ds->priv; 2539 2540 if (!dev->dev_ops->fdb_dump) 2541 return -EOPNOTSUPP; 2542 2543 return dev->dev_ops->fdb_dump(dev, port, cb, data); 2544 } 2545 2546 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 2547 const struct switchdev_obj_port_mdb *mdb, 2548 struct dsa_db db) 2549 { 2550 struct ksz_device *dev = ds->priv; 2551 2552 if (!dev->dev_ops->mdb_add) 2553 return -EOPNOTSUPP; 2554 2555 return dev->dev_ops->mdb_add(dev, port, mdb, db); 2556 } 2557 2558 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 2559 const struct switchdev_obj_port_mdb *mdb, 2560 struct dsa_db db) 2561 { 2562 struct ksz_device *dev = ds->priv; 2563 2564 if (!dev->dev_ops->mdb_del) 2565 return -EOPNOTSUPP; 2566 2567 return dev->dev_ops->mdb_del(dev, port, mdb, db); 2568 } 2569 2570 static int ksz_port_setup(struct dsa_switch *ds, int port) 2571 { 2572 struct ksz_device *dev = ds->priv; 2573 2574 if (!dsa_is_user_port(ds, port)) 2575 return 0; 2576 2577 /* setup slave port */ 2578 dev->dev_ops->port_setup(dev, port, false); 2579 2580 /* port_stp_state_set() will be called after to enable the port so 2581 * there is no need to do anything. 2582 */ 2583 2584 return 0; 2585 } 2586 2587 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 2588 { 2589 struct ksz_device *dev = ds->priv; 2590 struct ksz_port *p; 2591 const u16 *regs; 2592 u8 data; 2593 2594 regs = dev->info->regs; 2595 2596 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 2597 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2598 2599 p = &dev->ports[port]; 2600 2601 switch (state) { 2602 case BR_STATE_DISABLED: 2603 data |= PORT_LEARN_DISABLE; 2604 break; 2605 case BR_STATE_LISTENING: 2606 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2607 break; 2608 case BR_STATE_LEARNING: 2609 data |= PORT_RX_ENABLE; 2610 if (!p->learning) 2611 data |= PORT_LEARN_DISABLE; 2612 break; 2613 case BR_STATE_FORWARDING: 2614 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 2615 if (!p->learning) 2616 data |= PORT_LEARN_DISABLE; 2617 break; 2618 case BR_STATE_BLOCKING: 2619 data |= PORT_LEARN_DISABLE; 2620 break; 2621 default: 2622 dev_err(ds->dev, "invalid STP state: %d\n", state); 2623 return; 2624 } 2625 2626 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 2627 2628 p->stp_state = state; 2629 2630 ksz_update_port_member(dev, port); 2631 } 2632 2633 static void ksz_port_teardown(struct dsa_switch *ds, int port) 2634 { 2635 struct ksz_device *dev = ds->priv; 2636 2637 switch (dev->chip_id) { 2638 case KSZ8563_CHIP_ID: 2639 case KSZ9477_CHIP_ID: 2640 case KSZ9563_CHIP_ID: 2641 case KSZ9567_CHIP_ID: 2642 case KSZ9893_CHIP_ID: 2643 case KSZ9896_CHIP_ID: 2644 case KSZ9897_CHIP_ID: 2645 if (dsa_is_user_port(ds, port)) 2646 ksz9477_port_acl_free(dev, port); 2647 } 2648 } 2649 2650 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 2651 struct switchdev_brport_flags flags, 2652 struct netlink_ext_ack *extack) 2653 { 2654 if (flags.mask & ~BR_LEARNING) 2655 return -EINVAL; 2656 2657 return 0; 2658 } 2659 2660 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 2661 struct switchdev_brport_flags flags, 2662 struct netlink_ext_ack *extack) 2663 { 2664 struct ksz_device *dev = ds->priv; 2665 struct ksz_port *p = &dev->ports[port]; 2666 2667 if (flags.mask & BR_LEARNING) { 2668 p->learning = !!(flags.val & BR_LEARNING); 2669 2670 /* Make the change take effect immediately */ 2671 ksz_port_stp_state_set(ds, port, p->stp_state); 2672 } 2673 2674 return 0; 2675 } 2676 2677 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 2678 int port, 2679 enum dsa_tag_protocol mp) 2680 { 2681 struct ksz_device *dev = ds->priv; 2682 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 2683 2684 if (dev->chip_id == KSZ8795_CHIP_ID || 2685 dev->chip_id == KSZ8794_CHIP_ID || 2686 dev->chip_id == KSZ8765_CHIP_ID) 2687 proto = DSA_TAG_PROTO_KSZ8795; 2688 2689 if (dev->chip_id == KSZ8830_CHIP_ID || 2690 dev->chip_id == KSZ8563_CHIP_ID || 2691 dev->chip_id == KSZ9893_CHIP_ID || 2692 dev->chip_id == KSZ9563_CHIP_ID) 2693 proto = DSA_TAG_PROTO_KSZ9893; 2694 2695 if (dev->chip_id == KSZ9477_CHIP_ID || 2696 dev->chip_id == KSZ9896_CHIP_ID || 2697 dev->chip_id == KSZ9897_CHIP_ID || 2698 dev->chip_id == KSZ9567_CHIP_ID) 2699 proto = DSA_TAG_PROTO_KSZ9477; 2700 2701 if (is_lan937x(dev)) 2702 proto = DSA_TAG_PROTO_LAN937X_VALUE; 2703 2704 return proto; 2705 } 2706 2707 static int ksz_connect_tag_protocol(struct dsa_switch *ds, 2708 enum dsa_tag_protocol proto) 2709 { 2710 struct ksz_tagger_data *tagger_data; 2711 2712 tagger_data = ksz_tagger_data(ds); 2713 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 2714 2715 return 0; 2716 } 2717 2718 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 2719 bool flag, struct netlink_ext_ack *extack) 2720 { 2721 struct ksz_device *dev = ds->priv; 2722 2723 if (!dev->dev_ops->vlan_filtering) 2724 return -EOPNOTSUPP; 2725 2726 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 2727 } 2728 2729 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 2730 const struct switchdev_obj_port_vlan *vlan, 2731 struct netlink_ext_ack *extack) 2732 { 2733 struct ksz_device *dev = ds->priv; 2734 2735 if (!dev->dev_ops->vlan_add) 2736 return -EOPNOTSUPP; 2737 2738 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 2739 } 2740 2741 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 2742 const struct switchdev_obj_port_vlan *vlan) 2743 { 2744 struct ksz_device *dev = ds->priv; 2745 2746 if (!dev->dev_ops->vlan_del) 2747 return -EOPNOTSUPP; 2748 2749 return dev->dev_ops->vlan_del(dev, port, vlan); 2750 } 2751 2752 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 2753 struct dsa_mall_mirror_tc_entry *mirror, 2754 bool ingress, struct netlink_ext_ack *extack) 2755 { 2756 struct ksz_device *dev = ds->priv; 2757 2758 if (!dev->dev_ops->mirror_add) 2759 return -EOPNOTSUPP; 2760 2761 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 2762 } 2763 2764 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 2765 struct dsa_mall_mirror_tc_entry *mirror) 2766 { 2767 struct ksz_device *dev = ds->priv; 2768 2769 if (dev->dev_ops->mirror_del) 2770 dev->dev_ops->mirror_del(dev, port, mirror); 2771 } 2772 2773 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 2774 { 2775 struct ksz_device *dev = ds->priv; 2776 2777 if (!dev->dev_ops->change_mtu) 2778 return -EOPNOTSUPP; 2779 2780 return dev->dev_ops->change_mtu(dev, port, mtu); 2781 } 2782 2783 static int ksz_max_mtu(struct dsa_switch *ds, int port) 2784 { 2785 struct ksz_device *dev = ds->priv; 2786 2787 switch (dev->chip_id) { 2788 case KSZ8795_CHIP_ID: 2789 case KSZ8794_CHIP_ID: 2790 case KSZ8765_CHIP_ID: 2791 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2792 case KSZ8830_CHIP_ID: 2793 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2794 case KSZ8563_CHIP_ID: 2795 case KSZ9477_CHIP_ID: 2796 case KSZ9563_CHIP_ID: 2797 case KSZ9567_CHIP_ID: 2798 case KSZ9893_CHIP_ID: 2799 case KSZ9896_CHIP_ID: 2800 case KSZ9897_CHIP_ID: 2801 case LAN9370_CHIP_ID: 2802 case LAN9371_CHIP_ID: 2803 case LAN9372_CHIP_ID: 2804 case LAN9373_CHIP_ID: 2805 case LAN9374_CHIP_ID: 2806 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2807 } 2808 2809 return -EOPNOTSUPP; 2810 } 2811 2812 static int ksz_validate_eee(struct dsa_switch *ds, int port) 2813 { 2814 struct ksz_device *dev = ds->priv; 2815 2816 if (!dev->info->internal_phy[port]) 2817 return -EOPNOTSUPP; 2818 2819 switch (dev->chip_id) { 2820 case KSZ8563_CHIP_ID: 2821 case KSZ9477_CHIP_ID: 2822 case KSZ9563_CHIP_ID: 2823 case KSZ9567_CHIP_ID: 2824 case KSZ9893_CHIP_ID: 2825 case KSZ9896_CHIP_ID: 2826 case KSZ9897_CHIP_ID: 2827 return 0; 2828 } 2829 2830 return -EOPNOTSUPP; 2831 } 2832 2833 static int ksz_get_mac_eee(struct dsa_switch *ds, int port, 2834 struct ethtool_eee *e) 2835 { 2836 int ret; 2837 2838 ret = ksz_validate_eee(ds, port); 2839 if (ret) 2840 return ret; 2841 2842 /* There is no documented control of Tx LPI configuration. */ 2843 e->tx_lpi_enabled = true; 2844 2845 /* There is no documented control of Tx LPI timer. According to tests 2846 * Tx LPI timer seems to be set by default to minimal value. 2847 */ 2848 e->tx_lpi_timer = 0; 2849 2850 return 0; 2851 } 2852 2853 static int ksz_set_mac_eee(struct dsa_switch *ds, int port, 2854 struct ethtool_eee *e) 2855 { 2856 struct ksz_device *dev = ds->priv; 2857 int ret; 2858 2859 ret = ksz_validate_eee(ds, port); 2860 if (ret) 2861 return ret; 2862 2863 if (!e->tx_lpi_enabled) { 2864 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 2865 return -EINVAL; 2866 } 2867 2868 if (e->tx_lpi_timer) { 2869 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 2870 return -EINVAL; 2871 } 2872 2873 return 0; 2874 } 2875 2876 static void ksz_set_xmii(struct ksz_device *dev, int port, 2877 phy_interface_t interface) 2878 { 2879 const u8 *bitval = dev->info->xmii_ctrl1; 2880 struct ksz_port *p = &dev->ports[port]; 2881 const u16 *regs = dev->info->regs; 2882 u8 data8; 2883 2884 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2885 2886 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 2887 P_RGMII_ID_EG_ENABLE); 2888 2889 switch (interface) { 2890 case PHY_INTERFACE_MODE_MII: 2891 data8 |= bitval[P_MII_SEL]; 2892 break; 2893 case PHY_INTERFACE_MODE_RMII: 2894 data8 |= bitval[P_RMII_SEL]; 2895 break; 2896 case PHY_INTERFACE_MODE_GMII: 2897 data8 |= bitval[P_GMII_SEL]; 2898 break; 2899 case PHY_INTERFACE_MODE_RGMII: 2900 case PHY_INTERFACE_MODE_RGMII_ID: 2901 case PHY_INTERFACE_MODE_RGMII_TXID: 2902 case PHY_INTERFACE_MODE_RGMII_RXID: 2903 data8 |= bitval[P_RGMII_SEL]; 2904 /* On KSZ9893, disable RGMII in-band status support */ 2905 if (dev->chip_id == KSZ9893_CHIP_ID || 2906 dev->chip_id == KSZ8563_CHIP_ID || 2907 dev->chip_id == KSZ9563_CHIP_ID) 2908 data8 &= ~P_MII_MAC_MODE; 2909 break; 2910 default: 2911 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 2912 phy_modes(interface), port); 2913 return; 2914 } 2915 2916 if (p->rgmii_tx_val) 2917 data8 |= P_RGMII_ID_EG_ENABLE; 2918 2919 if (p->rgmii_rx_val) 2920 data8 |= P_RGMII_ID_IG_ENABLE; 2921 2922 /* Write the updated value */ 2923 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2924 } 2925 2926 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 2927 { 2928 const u8 *bitval = dev->info->xmii_ctrl1; 2929 const u16 *regs = dev->info->regs; 2930 phy_interface_t interface; 2931 u8 data8; 2932 u8 val; 2933 2934 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2935 2936 val = FIELD_GET(P_MII_SEL_M, data8); 2937 2938 if (val == bitval[P_MII_SEL]) { 2939 if (gbit) 2940 interface = PHY_INTERFACE_MODE_GMII; 2941 else 2942 interface = PHY_INTERFACE_MODE_MII; 2943 } else if (val == bitval[P_RMII_SEL]) { 2944 interface = PHY_INTERFACE_MODE_RGMII; 2945 } else { 2946 interface = PHY_INTERFACE_MODE_RGMII; 2947 if (data8 & P_RGMII_ID_EG_ENABLE) 2948 interface = PHY_INTERFACE_MODE_RGMII_TXID; 2949 if (data8 & P_RGMII_ID_IG_ENABLE) { 2950 interface = PHY_INTERFACE_MODE_RGMII_RXID; 2951 if (data8 & P_RGMII_ID_EG_ENABLE) 2952 interface = PHY_INTERFACE_MODE_RGMII_ID; 2953 } 2954 } 2955 2956 return interface; 2957 } 2958 2959 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, 2960 unsigned int mode, 2961 const struct phylink_link_state *state) 2962 { 2963 struct ksz_device *dev = ds->priv; 2964 2965 if (ksz_is_ksz88x3(dev)) 2966 return; 2967 2968 /* Internal PHYs */ 2969 if (dev->info->internal_phy[port]) 2970 return; 2971 2972 if (phylink_autoneg_inband(mode)) { 2973 dev_err(dev->dev, "In-band AN not supported!\n"); 2974 return; 2975 } 2976 2977 ksz_set_xmii(dev, port, state->interface); 2978 2979 if (dev->dev_ops->phylink_mac_config) 2980 dev->dev_ops->phylink_mac_config(dev, port, mode, state); 2981 2982 if (dev->dev_ops->setup_rgmii_delay) 2983 dev->dev_ops->setup_rgmii_delay(dev, port); 2984 } 2985 2986 bool ksz_get_gbit(struct ksz_device *dev, int port) 2987 { 2988 const u8 *bitval = dev->info->xmii_ctrl1; 2989 const u16 *regs = dev->info->regs; 2990 bool gbit = false; 2991 u8 data8; 2992 bool val; 2993 2994 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2995 2996 val = FIELD_GET(P_GMII_1GBIT_M, data8); 2997 2998 if (val == bitval[P_GMII_1GBIT]) 2999 gbit = true; 3000 3001 return gbit; 3002 } 3003 3004 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 3005 { 3006 const u8 *bitval = dev->info->xmii_ctrl1; 3007 const u16 *regs = dev->info->regs; 3008 u8 data8; 3009 3010 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3011 3012 data8 &= ~P_GMII_1GBIT_M; 3013 3014 if (gbit) 3015 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 3016 else 3017 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 3018 3019 /* Write the updated value */ 3020 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3021 } 3022 3023 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 3024 { 3025 const u8 *bitval = dev->info->xmii_ctrl0; 3026 const u16 *regs = dev->info->regs; 3027 u8 data8; 3028 3029 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 3030 3031 data8 &= ~P_MII_100MBIT_M; 3032 3033 if (speed == SPEED_100) 3034 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 3035 else 3036 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 3037 3038 /* Write the updated value */ 3039 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 3040 } 3041 3042 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 3043 { 3044 if (speed == SPEED_1000) 3045 ksz_set_gbit(dev, port, true); 3046 else 3047 ksz_set_gbit(dev, port, false); 3048 3049 if (speed == SPEED_100 || speed == SPEED_10) 3050 ksz_set_100_10mbit(dev, port, speed); 3051 } 3052 3053 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 3054 bool tx_pause, bool rx_pause) 3055 { 3056 const u8 *bitval = dev->info->xmii_ctrl0; 3057 const u32 *masks = dev->info->masks; 3058 const u16 *regs = dev->info->regs; 3059 u8 mask; 3060 u8 val; 3061 3062 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 3063 masks[P_MII_RX_FLOW_CTRL]; 3064 3065 if (duplex == DUPLEX_FULL) 3066 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 3067 else 3068 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 3069 3070 if (tx_pause) 3071 val |= masks[P_MII_TX_FLOW_CTRL]; 3072 3073 if (rx_pause) 3074 val |= masks[P_MII_RX_FLOW_CTRL]; 3075 3076 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 3077 } 3078 3079 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 3080 unsigned int mode, 3081 phy_interface_t interface, 3082 struct phy_device *phydev, int speed, 3083 int duplex, bool tx_pause, 3084 bool rx_pause) 3085 { 3086 struct ksz_port *p; 3087 3088 p = &dev->ports[port]; 3089 3090 /* Internal PHYs */ 3091 if (dev->info->internal_phy[port]) 3092 return; 3093 3094 p->phydev.speed = speed; 3095 3096 ksz_port_set_xmii_speed(dev, port, speed); 3097 3098 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 3099 } 3100 3101 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, 3102 unsigned int mode, 3103 phy_interface_t interface, 3104 struct phy_device *phydev, int speed, 3105 int duplex, bool tx_pause, bool rx_pause) 3106 { 3107 struct ksz_device *dev = ds->priv; 3108 3109 if (dev->dev_ops->phylink_mac_link_up) 3110 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface, 3111 phydev, speed, duplex, 3112 tx_pause, rx_pause); 3113 } 3114 3115 static int ksz_switch_detect(struct ksz_device *dev) 3116 { 3117 u8 id1, id2, id4; 3118 u16 id16; 3119 u32 id32; 3120 int ret; 3121 3122 /* read chip id */ 3123 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 3124 if (ret) 3125 return ret; 3126 3127 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 3128 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 3129 3130 switch (id1) { 3131 case KSZ87_FAMILY_ID: 3132 if (id2 == KSZ87_CHIP_ID_95) { 3133 u8 val; 3134 3135 dev->chip_id = KSZ8795_CHIP_ID; 3136 3137 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 3138 if (val & KSZ8_PORT_FIBER_MODE) 3139 dev->chip_id = KSZ8765_CHIP_ID; 3140 } else if (id2 == KSZ87_CHIP_ID_94) { 3141 dev->chip_id = KSZ8794_CHIP_ID; 3142 } else { 3143 return -ENODEV; 3144 } 3145 break; 3146 case KSZ88_FAMILY_ID: 3147 if (id2 == KSZ88_CHIP_ID_63) 3148 dev->chip_id = KSZ8830_CHIP_ID; 3149 else 3150 return -ENODEV; 3151 break; 3152 default: 3153 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 3154 if (ret) 3155 return ret; 3156 3157 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 3158 id32 &= ~0xFF; 3159 3160 switch (id32) { 3161 case KSZ9477_CHIP_ID: 3162 case KSZ9896_CHIP_ID: 3163 case KSZ9897_CHIP_ID: 3164 case KSZ9567_CHIP_ID: 3165 case LAN9370_CHIP_ID: 3166 case LAN9371_CHIP_ID: 3167 case LAN9372_CHIP_ID: 3168 case LAN9373_CHIP_ID: 3169 case LAN9374_CHIP_ID: 3170 dev->chip_id = id32; 3171 break; 3172 case KSZ9893_CHIP_ID: 3173 ret = ksz_read8(dev, REG_CHIP_ID4, 3174 &id4); 3175 if (ret) 3176 return ret; 3177 3178 if (id4 == SKU_ID_KSZ8563) 3179 dev->chip_id = KSZ8563_CHIP_ID; 3180 else if (id4 == SKU_ID_KSZ9563) 3181 dev->chip_id = KSZ9563_CHIP_ID; 3182 else 3183 dev->chip_id = KSZ9893_CHIP_ID; 3184 3185 break; 3186 default: 3187 dev_err(dev->dev, 3188 "unsupported switch detected %x)\n", id32); 3189 return -ENODEV; 3190 } 3191 } 3192 return 0; 3193 } 3194 3195 static int ksz_cls_flower_add(struct dsa_switch *ds, int port, 3196 struct flow_cls_offload *cls, bool ingress) 3197 { 3198 struct ksz_device *dev = ds->priv; 3199 3200 switch (dev->chip_id) { 3201 case KSZ8563_CHIP_ID: 3202 case KSZ9477_CHIP_ID: 3203 case KSZ9563_CHIP_ID: 3204 case KSZ9567_CHIP_ID: 3205 case KSZ9893_CHIP_ID: 3206 case KSZ9896_CHIP_ID: 3207 case KSZ9897_CHIP_ID: 3208 return ksz9477_cls_flower_add(ds, port, cls, ingress); 3209 } 3210 3211 return -EOPNOTSUPP; 3212 } 3213 3214 static int ksz_cls_flower_del(struct dsa_switch *ds, int port, 3215 struct flow_cls_offload *cls, bool ingress) 3216 { 3217 struct ksz_device *dev = ds->priv; 3218 3219 switch (dev->chip_id) { 3220 case KSZ8563_CHIP_ID: 3221 case KSZ9477_CHIP_ID: 3222 case KSZ9563_CHIP_ID: 3223 case KSZ9567_CHIP_ID: 3224 case KSZ9893_CHIP_ID: 3225 case KSZ9896_CHIP_ID: 3226 case KSZ9897_CHIP_ID: 3227 return ksz9477_cls_flower_del(ds, port, cls, ingress); 3228 } 3229 3230 return -EOPNOTSUPP; 3231 } 3232 3233 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 3234 * is converted to Hex-decimal using the successive multiplication method. On 3235 * every step, integer part is taken and decimal part is carry forwarded. 3236 */ 3237 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 3238 { 3239 u32 cinc = 0; 3240 u32 txrate; 3241 u32 rate; 3242 u8 temp; 3243 u8 i; 3244 3245 txrate = idle_slope - send_slope; 3246 3247 if (!txrate) 3248 return -EINVAL; 3249 3250 rate = idle_slope; 3251 3252 /* 24 bit register */ 3253 for (i = 0; i < 6; i++) { 3254 rate = rate * 16; 3255 3256 temp = rate / txrate; 3257 3258 rate %= txrate; 3259 3260 cinc = ((cinc << 4) | temp); 3261 } 3262 3263 *bw = cinc; 3264 3265 return 0; 3266 } 3267 3268 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 3269 u8 shaper) 3270 { 3271 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 3272 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 3273 FIELD_PREP(MTI_SHAPING_M, shaper)); 3274 } 3275 3276 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 3277 struct tc_cbs_qopt_offload *qopt) 3278 { 3279 struct ksz_device *dev = ds->priv; 3280 int ret; 3281 u32 bw; 3282 3283 if (!dev->info->tc_cbs_supported) 3284 return -EOPNOTSUPP; 3285 3286 if (qopt->queue > dev->info->num_tx_queues) 3287 return -EINVAL; 3288 3289 /* Queue Selection */ 3290 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 3291 if (ret) 3292 return ret; 3293 3294 if (!qopt->enable) 3295 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3296 MTI_SHAPING_OFF); 3297 3298 /* High Credit */ 3299 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 3300 qopt->hicredit); 3301 if (ret) 3302 return ret; 3303 3304 /* Low Credit */ 3305 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 3306 qopt->locredit); 3307 if (ret) 3308 return ret; 3309 3310 /* Credit Increment Register */ 3311 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 3312 if (ret) 3313 return ret; 3314 3315 if (dev->dev_ops->tc_cbs_set_cinc) { 3316 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 3317 if (ret) 3318 return ret; 3319 } 3320 3321 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3322 MTI_SHAPING_SRP); 3323 } 3324 3325 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 3326 { 3327 int queue, ret; 3328 3329 /* Configuration will not take effect until the last Port Queue X 3330 * Egress Limit Control Register is written. 3331 */ 3332 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3333 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 3334 KSZ9477_OUT_RATE_NO_LIMIT); 3335 if (ret) 3336 return ret; 3337 } 3338 3339 return 0; 3340 } 3341 3342 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 3343 int band) 3344 { 3345 /* Compared to queues, bands prioritize packets differently. In strict 3346 * priority mode, the lowest priority is assigned to Queue 0 while the 3347 * highest priority is given to Band 0. 3348 */ 3349 return p->bands - 1 - band; 3350 } 3351 3352 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 3353 { 3354 int ret; 3355 3356 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3357 if (ret) 3358 return ret; 3359 3360 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3361 MTI_SHAPING_OFF); 3362 } 3363 3364 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 3365 int weight) 3366 { 3367 int ret; 3368 3369 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3370 if (ret) 3371 return ret; 3372 3373 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3374 MTI_SHAPING_OFF); 3375 if (ret) 3376 return ret; 3377 3378 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 3379 } 3380 3381 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 3382 struct tc_ets_qopt_offload_replace_params *p) 3383 { 3384 int ret, band, tc_prio; 3385 u32 queue_map = 0; 3386 3387 /* In order to ensure proper prioritization, it is necessary to set the 3388 * rate limit for the related queue to zero. Otherwise strict priority 3389 * or WRR mode will not work. This is a hardware limitation. 3390 */ 3391 ret = ksz_disable_egress_rate_limit(dev, port); 3392 if (ret) 3393 return ret; 3394 3395 /* Configure queue scheduling mode for all bands. Currently only strict 3396 * prio mode is supported. 3397 */ 3398 for (band = 0; band < p->bands; band++) { 3399 int queue = ksz_ets_band_to_queue(p, band); 3400 3401 ret = ksz_queue_set_strict(dev, port, queue); 3402 if (ret) 3403 return ret; 3404 } 3405 3406 /* Configure the mapping between traffic classes and queues. Note: 3407 * priomap variable support 16 traffic classes, but the chip can handle 3408 * only 8 classes. 3409 */ 3410 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 3411 int queue; 3412 3413 if (tc_prio > KSZ9477_MAX_TC_PRIO) 3414 break; 3415 3416 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 3417 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3418 } 3419 3420 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3421 } 3422 3423 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 3424 { 3425 int ret, queue, tc_prio, s; 3426 u32 queue_map = 0; 3427 3428 /* To restore the default chip configuration, set all queues to use the 3429 * WRR scheduler with a weight of 1. 3430 */ 3431 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3432 ret = ksz_queue_set_wrr(dev, port, queue, 3433 KSZ9477_DEFAULT_WRR_WEIGHT); 3434 if (ret) 3435 return ret; 3436 } 3437 3438 switch (dev->info->num_tx_queues) { 3439 case 2: 3440 s = 2; 3441 break; 3442 case 4: 3443 s = 1; 3444 break; 3445 case 8: 3446 s = 0; 3447 break; 3448 default: 3449 return -EINVAL; 3450 } 3451 3452 /* Revert the queue mapping for TC-priority to its default setting on 3453 * the chip. 3454 */ 3455 for (tc_prio = 0; tc_prio <= KSZ9477_MAX_TC_PRIO; tc_prio++) { 3456 int queue; 3457 3458 queue = tc_prio >> s; 3459 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3460 } 3461 3462 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3463 } 3464 3465 static int ksz_tc_ets_validate(struct ksz_device *dev, int port, 3466 struct tc_ets_qopt_offload_replace_params *p) 3467 { 3468 int band; 3469 3470 /* Since it is not feasible to share one port among multiple qdisc, 3471 * the user must configure all available queues appropriately. 3472 */ 3473 if (p->bands != dev->info->num_tx_queues) { 3474 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 3475 dev->info->num_tx_queues); 3476 return -EOPNOTSUPP; 3477 } 3478 3479 for (band = 0; band < p->bands; ++band) { 3480 /* The KSZ switches utilize a weighted round robin configuration 3481 * where a certain number of packets can be transmitted from a 3482 * queue before the next queue is serviced. For more information 3483 * on this, refer to section 5.2.8.4 of the KSZ8565R 3484 * documentation on the Port Transmit Queue Control 1 Register. 3485 * However, the current ETS Qdisc implementation (as of February 3486 * 2023) assigns a weight to each queue based on the number of 3487 * bytes or extrapolated bandwidth in percentages. Since this 3488 * differs from the KSZ switches' method and we don't want to 3489 * fake support by converting bytes to packets, it is better to 3490 * return an error instead. 3491 */ 3492 if (p->quanta[band]) { 3493 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 3494 return -EOPNOTSUPP; 3495 } 3496 } 3497 3498 return 0; 3499 } 3500 3501 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 3502 struct tc_ets_qopt_offload *qopt) 3503 { 3504 struct ksz_device *dev = ds->priv; 3505 int ret; 3506 3507 if (!dev->info->tc_ets_supported) 3508 return -EOPNOTSUPP; 3509 3510 if (qopt->parent != TC_H_ROOT) { 3511 dev_err(dev->dev, "Parent should be \"root\"\n"); 3512 return -EOPNOTSUPP; 3513 } 3514 3515 switch (qopt->command) { 3516 case TC_ETS_REPLACE: 3517 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 3518 if (ret) 3519 return ret; 3520 3521 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 3522 case TC_ETS_DESTROY: 3523 return ksz_tc_ets_del(dev, port); 3524 case TC_ETS_STATS: 3525 case TC_ETS_GRAFT: 3526 return -EOPNOTSUPP; 3527 } 3528 3529 return -EOPNOTSUPP; 3530 } 3531 3532 static int ksz_setup_tc(struct dsa_switch *ds, int port, 3533 enum tc_setup_type type, void *type_data) 3534 { 3535 switch (type) { 3536 case TC_SETUP_QDISC_CBS: 3537 return ksz_setup_tc_cbs(ds, port, type_data); 3538 case TC_SETUP_QDISC_ETS: 3539 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 3540 default: 3541 return -EOPNOTSUPP; 3542 } 3543 } 3544 3545 static int ksz_port_set_mac_address(struct dsa_switch *ds, int port, 3546 const unsigned char *addr) 3547 { 3548 struct dsa_port *dp = dsa_to_port(ds, port); 3549 3550 if (dp->hsr_dev) { 3551 dev_err(ds->dev, 3552 "Cannot change MAC address on port %d with active HSR offload\n", 3553 port); 3554 return -EBUSY; 3555 } 3556 3557 return 0; 3558 } 3559 3560 /* Program the switch's MAC address register with the MAC address of the 3561 * requesting user port. This single address is used by the switch for multiple 3562 * features, like HSR self-address filtering and WoL. Other user ports are 3563 * allowed to share ownership of this address as long as their MAC address is 3564 * the same. The user ports' MAC addresses must not change while they have 3565 * ownership of the switch MAC address. 3566 */ 3567 static int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 3568 struct netlink_ext_ack *extack) 3569 { 3570 struct net_device *slave = dsa_to_port(ds, port)->slave; 3571 const unsigned char *addr = slave->dev_addr; 3572 struct ksz_switch_macaddr *switch_macaddr; 3573 struct ksz_device *dev = ds->priv; 3574 const u16 *regs = dev->info->regs; 3575 int i; 3576 3577 /* Make sure concurrent MAC address changes are blocked */ 3578 ASSERT_RTNL(); 3579 3580 switch_macaddr = dev->switch_macaddr; 3581 if (switch_macaddr) { 3582 if (!ether_addr_equal(switch_macaddr->addr, addr)) { 3583 NL_SET_ERR_MSG_FMT_MOD(extack, 3584 "Switch already configured for MAC address %pM", 3585 switch_macaddr->addr); 3586 return -EBUSY; 3587 } 3588 3589 refcount_inc(&switch_macaddr->refcount); 3590 return 0; 3591 } 3592 3593 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL); 3594 if (!switch_macaddr) 3595 return -ENOMEM; 3596 3597 ether_addr_copy(switch_macaddr->addr, addr); 3598 refcount_set(&switch_macaddr->refcount, 1); 3599 dev->switch_macaddr = switch_macaddr; 3600 3601 /* Program the switch MAC address to hardware */ 3602 for (i = 0; i < ETH_ALEN; i++) 3603 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, addr[i]); 3604 3605 return 0; 3606 } 3607 3608 static void ksz_switch_macaddr_put(struct dsa_switch *ds) 3609 { 3610 struct ksz_switch_macaddr *switch_macaddr; 3611 struct ksz_device *dev = ds->priv; 3612 const u16 *regs = dev->info->regs; 3613 int i; 3614 3615 /* Make sure concurrent MAC address changes are blocked */ 3616 ASSERT_RTNL(); 3617 3618 switch_macaddr = dev->switch_macaddr; 3619 if (!refcount_dec_and_test(&switch_macaddr->refcount)) 3620 return; 3621 3622 for (i = 0; i < ETH_ALEN; i++) 3623 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0); 3624 3625 dev->switch_macaddr = NULL; 3626 kfree(switch_macaddr); 3627 } 3628 3629 static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr, 3630 struct netlink_ext_ack *extack) 3631 { 3632 struct ksz_device *dev = ds->priv; 3633 enum hsr_version ver; 3634 int ret; 3635 3636 ret = hsr_get_version(hsr, &ver); 3637 if (ret) 3638 return ret; 3639 3640 if (dev->chip_id != KSZ9477_CHIP_ID) { 3641 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload"); 3642 return -EOPNOTSUPP; 3643 } 3644 3645 /* KSZ9477 can support HW offloading of only 1 HSR device */ 3646 if (dev->hsr_dev && hsr != dev->hsr_dev) { 3647 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR"); 3648 return -EOPNOTSUPP; 3649 } 3650 3651 /* KSZ9477 only supports HSR v0 and v1 */ 3652 if (!(ver == HSR_V0 || ver == HSR_V1)) { 3653 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported"); 3654 return -EOPNOTSUPP; 3655 } 3656 3657 /* Self MAC address filtering, to avoid frames traversing 3658 * the HSR ring more than once. 3659 */ 3660 ret = ksz_switch_macaddr_get(ds, port, extack); 3661 if (ret) 3662 return ret; 3663 3664 ksz9477_hsr_join(ds, port, hsr); 3665 dev->hsr_dev = hsr; 3666 dev->hsr_ports |= BIT(port); 3667 3668 return 0; 3669 } 3670 3671 static int ksz_hsr_leave(struct dsa_switch *ds, int port, 3672 struct net_device *hsr) 3673 { 3674 struct ksz_device *dev = ds->priv; 3675 3676 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID); 3677 3678 ksz9477_hsr_leave(ds, port, hsr); 3679 dev->hsr_ports &= ~BIT(port); 3680 if (!dev->hsr_ports) 3681 dev->hsr_dev = NULL; 3682 3683 ksz_switch_macaddr_put(ds); 3684 3685 return 0; 3686 } 3687 3688 static const struct dsa_switch_ops ksz_switch_ops = { 3689 .get_tag_protocol = ksz_get_tag_protocol, 3690 .connect_tag_protocol = ksz_connect_tag_protocol, 3691 .get_phy_flags = ksz_get_phy_flags, 3692 .setup = ksz_setup, 3693 .teardown = ksz_teardown, 3694 .phy_read = ksz_phy_read16, 3695 .phy_write = ksz_phy_write16, 3696 .phylink_get_caps = ksz_phylink_get_caps, 3697 .phylink_mac_config = ksz_phylink_mac_config, 3698 .phylink_mac_link_up = ksz_phylink_mac_link_up, 3699 .phylink_mac_link_down = ksz_mac_link_down, 3700 .port_setup = ksz_port_setup, 3701 .set_ageing_time = ksz_set_ageing_time, 3702 .get_strings = ksz_get_strings, 3703 .get_ethtool_stats = ksz_get_ethtool_stats, 3704 .get_sset_count = ksz_sset_count, 3705 .port_bridge_join = ksz_port_bridge_join, 3706 .port_bridge_leave = ksz_port_bridge_leave, 3707 .port_hsr_join = ksz_hsr_join, 3708 .port_hsr_leave = ksz_hsr_leave, 3709 .port_set_mac_address = ksz_port_set_mac_address, 3710 .port_stp_state_set = ksz_port_stp_state_set, 3711 .port_teardown = ksz_port_teardown, 3712 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 3713 .port_bridge_flags = ksz_port_bridge_flags, 3714 .port_fast_age = ksz_port_fast_age, 3715 .port_vlan_filtering = ksz_port_vlan_filtering, 3716 .port_vlan_add = ksz_port_vlan_add, 3717 .port_vlan_del = ksz_port_vlan_del, 3718 .port_fdb_dump = ksz_port_fdb_dump, 3719 .port_fdb_add = ksz_port_fdb_add, 3720 .port_fdb_del = ksz_port_fdb_del, 3721 .port_mdb_add = ksz_port_mdb_add, 3722 .port_mdb_del = ksz_port_mdb_del, 3723 .port_mirror_add = ksz_port_mirror_add, 3724 .port_mirror_del = ksz_port_mirror_del, 3725 .get_stats64 = ksz_get_stats64, 3726 .get_pause_stats = ksz_get_pause_stats, 3727 .port_change_mtu = ksz_change_mtu, 3728 .port_max_mtu = ksz_max_mtu, 3729 .get_ts_info = ksz_get_ts_info, 3730 .port_hwtstamp_get = ksz_hwtstamp_get, 3731 .port_hwtstamp_set = ksz_hwtstamp_set, 3732 .port_txtstamp = ksz_port_txtstamp, 3733 .port_rxtstamp = ksz_port_rxtstamp, 3734 .cls_flower_add = ksz_cls_flower_add, 3735 .cls_flower_del = ksz_cls_flower_del, 3736 .port_setup_tc = ksz_setup_tc, 3737 .get_mac_eee = ksz_get_mac_eee, 3738 .set_mac_eee = ksz_set_mac_eee, 3739 }; 3740 3741 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 3742 { 3743 struct dsa_switch *ds; 3744 struct ksz_device *swdev; 3745 3746 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 3747 if (!ds) 3748 return NULL; 3749 3750 ds->dev = base; 3751 ds->num_ports = DSA_MAX_PORTS; 3752 ds->ops = &ksz_switch_ops; 3753 3754 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 3755 if (!swdev) 3756 return NULL; 3757 3758 ds->priv = swdev; 3759 swdev->dev = base; 3760 3761 swdev->ds = ds; 3762 swdev->priv = priv; 3763 3764 return swdev; 3765 } 3766 EXPORT_SYMBOL(ksz_switch_alloc); 3767 3768 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 3769 struct device_node *port_dn) 3770 { 3771 phy_interface_t phy_mode = dev->ports[port_num].interface; 3772 int rx_delay = -1, tx_delay = -1; 3773 3774 if (!phy_interface_mode_is_rgmii(phy_mode)) 3775 return; 3776 3777 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 3778 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 3779 3780 if (rx_delay == -1 && tx_delay == -1) { 3781 dev_warn(dev->dev, 3782 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 3783 "please update device tree to specify \"rx-internal-delay-ps\" and " 3784 "\"tx-internal-delay-ps\"", 3785 port_num); 3786 3787 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 3788 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 3789 rx_delay = 2000; 3790 3791 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 3792 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 3793 tx_delay = 2000; 3794 } 3795 3796 if (rx_delay < 0) 3797 rx_delay = 0; 3798 if (tx_delay < 0) 3799 tx_delay = 0; 3800 3801 dev->ports[port_num].rgmii_rx_val = rx_delay; 3802 dev->ports[port_num].rgmii_tx_val = tx_delay; 3803 } 3804 3805 /** 3806 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding 3807 * register value. 3808 * @array: The array of drive strength values to search. 3809 * @array_size: The size of the array. 3810 * @microamp: The drive strength value in microamp to be converted. 3811 * 3812 * This function searches the array of drive strength values for the given 3813 * microamp value and returns the corresponding register value for that drive. 3814 * 3815 * Returns: If found, the corresponding register value for that drive strength 3816 * is returned. Otherwise, -EINVAL is returned indicating an invalid value. 3817 */ 3818 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array, 3819 size_t array_size, int microamp) 3820 { 3821 int i; 3822 3823 for (i = 0; i < array_size; i++) { 3824 if (array[i].microamp == microamp) 3825 return array[i].reg_val; 3826 } 3827 3828 return -EINVAL; 3829 } 3830 3831 /** 3832 * ksz_drive_strength_error() - Report invalid drive strength value 3833 * @dev: ksz device 3834 * @array: The array of drive strength values to search. 3835 * @array_size: The size of the array. 3836 * @microamp: Invalid drive strength value in microamp 3837 * 3838 * This function logs an error message when an unsupported drive strength value 3839 * is detected. It lists out all the supported drive strength values for 3840 * reference in the error message. 3841 */ 3842 static void ksz_drive_strength_error(struct ksz_device *dev, 3843 const struct ksz_drive_strength *array, 3844 size_t array_size, int microamp) 3845 { 3846 char supported_values[100]; 3847 size_t remaining_size; 3848 int added_len; 3849 char *ptr; 3850 int i; 3851 3852 remaining_size = sizeof(supported_values); 3853 ptr = supported_values; 3854 3855 for (i = 0; i < array_size; i++) { 3856 added_len = snprintf(ptr, remaining_size, 3857 i == 0 ? "%d" : ", %d", array[i].microamp); 3858 3859 if (added_len >= remaining_size) 3860 break; 3861 3862 ptr += added_len; 3863 remaining_size -= added_len; 3864 } 3865 3866 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n", 3867 microamp, supported_values); 3868 } 3869 3870 /** 3871 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477 3872 * chip variants. 3873 * @dev: ksz device 3874 * @props: Array of drive strength properties to be applied 3875 * @num_props: Number of properties in the array 3876 * 3877 * This function configures the drive strength for various KSZ9477 chip variants 3878 * based on the provided properties. It handles chip-specific nuances and 3879 * ensures only valid drive strengths are written to the respective chip. 3880 * 3881 * Return: 0 on successful configuration, a negative error code on failure. 3882 */ 3883 static int ksz9477_drive_strength_write(struct ksz_device *dev, 3884 struct ksz_driver_strength_prop *props, 3885 int num_props) 3886 { 3887 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths); 3888 int i, ret, reg; 3889 u8 mask = 0; 3890 u8 val = 0; 3891 3892 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1) 3893 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 3894 props[KSZ_DRIVER_STRENGTH_IO].name); 3895 3896 if (dev->chip_id == KSZ8795_CHIP_ID || 3897 dev->chip_id == KSZ8794_CHIP_ID || 3898 dev->chip_id == KSZ8765_CHIP_ID) 3899 reg = KSZ8795_REG_SW_CTRL_20; 3900 else 3901 reg = KSZ9477_REG_SW_IO_STRENGTH; 3902 3903 for (i = 0; i < num_props; i++) { 3904 if (props[i].value == -1) 3905 continue; 3906 3907 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths, 3908 array_size, props[i].value); 3909 if (ret < 0) { 3910 ksz_drive_strength_error(dev, ksz9477_drive_strengths, 3911 array_size, props[i].value); 3912 return ret; 3913 } 3914 3915 mask |= SW_DRIVE_STRENGTH_M << props[i].offset; 3916 val |= ret << props[i].offset; 3917 } 3918 3919 return ksz_rmw8(dev, reg, mask, val); 3920 } 3921 3922 /** 3923 * ksz8830_drive_strength_write() - Set the drive strength configuration for 3924 * KSZ8830 compatible chip variants. 3925 * @dev: ksz device 3926 * @props: Array of drive strength properties to be set 3927 * @num_props: Number of properties in the array 3928 * 3929 * This function applies the specified drive strength settings to KSZ8830 chip 3930 * variants (KSZ8873, KSZ8863). 3931 * It ensures the configurations align with what the chip variant supports and 3932 * warns or errors out on unsupported settings. 3933 * 3934 * Return: 0 on success, error code otherwise 3935 */ 3936 static int ksz8830_drive_strength_write(struct ksz_device *dev, 3937 struct ksz_driver_strength_prop *props, 3938 int num_props) 3939 { 3940 size_t array_size = ARRAY_SIZE(ksz8830_drive_strengths); 3941 int microamp; 3942 int i, ret; 3943 3944 for (i = 0; i < num_props; i++) { 3945 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO) 3946 continue; 3947 3948 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 3949 props[i].name); 3950 } 3951 3952 microamp = props[KSZ_DRIVER_STRENGTH_IO].value; 3953 ret = ksz_drive_strength_to_reg(ksz8830_drive_strengths, array_size, 3954 microamp); 3955 if (ret < 0) { 3956 ksz_drive_strength_error(dev, ksz8830_drive_strengths, 3957 array_size, microamp); 3958 return ret; 3959 } 3960 3961 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12, 3962 KSZ8873_DRIVE_STRENGTH_16MA, ret); 3963 } 3964 3965 /** 3966 * ksz_parse_drive_strength() - Extract and apply drive strength configurations 3967 * from device tree properties. 3968 * @dev: ksz device 3969 * 3970 * This function reads the specified drive strength properties from the 3971 * device tree, validates against the supported chip variants, and sets 3972 * them accordingly. An error should be critical here, as the drive strength 3973 * settings are crucial for EMI compliance. 3974 * 3975 * Return: 0 on success, error code otherwise 3976 */ 3977 static int ksz_parse_drive_strength(struct ksz_device *dev) 3978 { 3979 struct ksz_driver_strength_prop of_props[] = { 3980 [KSZ_DRIVER_STRENGTH_HI] = { 3981 .name = "microchip,hi-drive-strength-microamp", 3982 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S, 3983 .value = -1, 3984 }, 3985 [KSZ_DRIVER_STRENGTH_LO] = { 3986 .name = "microchip,lo-drive-strength-microamp", 3987 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S, 3988 .value = -1, 3989 }, 3990 [KSZ_DRIVER_STRENGTH_IO] = { 3991 .name = "microchip,io-drive-strength-microamp", 3992 .offset = 0, /* don't care */ 3993 .value = -1, 3994 }, 3995 }; 3996 struct device_node *np = dev->dev->of_node; 3997 bool have_any_prop = false; 3998 int i, ret; 3999 4000 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4001 ret = of_property_read_u32(np, of_props[i].name, 4002 &of_props[i].value); 4003 if (ret && ret != -EINVAL) 4004 dev_warn(dev->dev, "Failed to read %s\n", 4005 of_props[i].name); 4006 if (ret) 4007 continue; 4008 4009 have_any_prop = true; 4010 } 4011 4012 if (!have_any_prop) 4013 return 0; 4014 4015 switch (dev->chip_id) { 4016 case KSZ8830_CHIP_ID: 4017 return ksz8830_drive_strength_write(dev, of_props, 4018 ARRAY_SIZE(of_props)); 4019 case KSZ8795_CHIP_ID: 4020 case KSZ8794_CHIP_ID: 4021 case KSZ8765_CHIP_ID: 4022 case KSZ8563_CHIP_ID: 4023 case KSZ9477_CHIP_ID: 4024 case KSZ9563_CHIP_ID: 4025 case KSZ9567_CHIP_ID: 4026 case KSZ9893_CHIP_ID: 4027 case KSZ9896_CHIP_ID: 4028 case KSZ9897_CHIP_ID: 4029 return ksz9477_drive_strength_write(dev, of_props, 4030 ARRAY_SIZE(of_props)); 4031 default: 4032 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 4033 if (of_props[i].value == -1) 4034 continue; 4035 4036 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 4037 of_props[i].name); 4038 } 4039 } 4040 4041 return 0; 4042 } 4043 4044 int ksz_switch_register(struct ksz_device *dev) 4045 { 4046 const struct ksz_chip_data *info; 4047 struct device_node *port, *ports; 4048 phy_interface_t interface; 4049 unsigned int port_num; 4050 int ret; 4051 int i; 4052 4053 if (dev->pdata) 4054 dev->chip_id = dev->pdata->chip_id; 4055 4056 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 4057 GPIOD_OUT_LOW); 4058 if (IS_ERR(dev->reset_gpio)) 4059 return PTR_ERR(dev->reset_gpio); 4060 4061 if (dev->reset_gpio) { 4062 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4063 usleep_range(10000, 12000); 4064 gpiod_set_value_cansleep(dev->reset_gpio, 0); 4065 msleep(100); 4066 } 4067 4068 mutex_init(&dev->dev_mutex); 4069 mutex_init(&dev->regmap_mutex); 4070 mutex_init(&dev->alu_mutex); 4071 mutex_init(&dev->vlan_mutex); 4072 4073 ret = ksz_switch_detect(dev); 4074 if (ret) 4075 return ret; 4076 4077 info = ksz_lookup_info(dev->chip_id); 4078 if (!info) 4079 return -ENODEV; 4080 4081 /* Update the compatible info with the probed one */ 4082 dev->info = info; 4083 4084 dev_info(dev->dev, "found switch: %s, rev %i\n", 4085 dev->info->dev_name, dev->chip_rev); 4086 4087 ret = ksz_check_device_id(dev); 4088 if (ret) 4089 return ret; 4090 4091 dev->dev_ops = dev->info->ops; 4092 4093 ret = dev->dev_ops->init(dev); 4094 if (ret) 4095 return ret; 4096 4097 dev->ports = devm_kzalloc(dev->dev, 4098 dev->info->port_cnt * sizeof(struct ksz_port), 4099 GFP_KERNEL); 4100 if (!dev->ports) 4101 return -ENOMEM; 4102 4103 for (i = 0; i < dev->info->port_cnt; i++) { 4104 spin_lock_init(&dev->ports[i].mib.stats64_lock); 4105 mutex_init(&dev->ports[i].mib.cnt_mutex); 4106 dev->ports[i].mib.counters = 4107 devm_kzalloc(dev->dev, 4108 sizeof(u64) * (dev->info->mib_cnt + 1), 4109 GFP_KERNEL); 4110 if (!dev->ports[i].mib.counters) 4111 return -ENOMEM; 4112 4113 dev->ports[i].ksz_dev = dev; 4114 dev->ports[i].num = i; 4115 } 4116 4117 /* set the real number of ports */ 4118 dev->ds->num_ports = dev->info->port_cnt; 4119 4120 /* Host port interface will be self detected, or specifically set in 4121 * device tree. 4122 */ 4123 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 4124 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 4125 if (dev->dev->of_node) { 4126 ret = ksz_parse_drive_strength(dev); 4127 if (ret) 4128 return ret; 4129 4130 ret = of_get_phy_mode(dev->dev->of_node, &interface); 4131 if (ret == 0) 4132 dev->compat_interface = interface; 4133 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 4134 if (!ports) 4135 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 4136 if (ports) { 4137 for_each_available_child_of_node(ports, port) { 4138 if (of_property_read_u32(port, "reg", 4139 &port_num)) 4140 continue; 4141 if (!(dev->port_mask & BIT(port_num))) { 4142 of_node_put(port); 4143 of_node_put(ports); 4144 return -EINVAL; 4145 } 4146 of_get_phy_mode(port, 4147 &dev->ports[port_num].interface); 4148 4149 ksz_parse_rgmii_delay(dev, port_num, port); 4150 } 4151 of_node_put(ports); 4152 } 4153 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 4154 "microchip,synclko-125"); 4155 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 4156 "microchip,synclko-disable"); 4157 if (dev->synclko_125 && dev->synclko_disable) { 4158 dev_err(dev->dev, "inconsistent synclko settings\n"); 4159 return -EINVAL; 4160 } 4161 } 4162 4163 ret = dsa_register_switch(dev->ds); 4164 if (ret) { 4165 dev->dev_ops->exit(dev); 4166 return ret; 4167 } 4168 4169 /* Read MIB counters every 30 seconds to avoid overflow. */ 4170 dev->mib_read_interval = msecs_to_jiffies(5000); 4171 4172 /* Start the MIB timer. */ 4173 schedule_delayed_work(&dev->mib_read, 0); 4174 4175 return ret; 4176 } 4177 EXPORT_SYMBOL(ksz_switch_register); 4178 4179 void ksz_switch_remove(struct ksz_device *dev) 4180 { 4181 /* timer started */ 4182 if (dev->mib_read_interval) { 4183 dev->mib_read_interval = 0; 4184 cancel_delayed_work_sync(&dev->mib_read); 4185 } 4186 4187 dev->dev_ops->exit(dev); 4188 dsa_unregister_switch(dev->ds); 4189 4190 if (dev->reset_gpio) 4191 gpiod_set_value_cansleep(dev->reset_gpio, 1); 4192 4193 } 4194 EXPORT_SYMBOL(ksz_switch_remove); 4195 4196 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 4197 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 4198 MODULE_LICENSE("GPL"); 4199