1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2025 Microchip Technology Inc. 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/iopoll.h> 11 #include <linux/platform_data/microchip-ksz.h> 12 #include <linux/phy.h> 13 #include <linux/if_bridge.h> 14 #include <linux/if_vlan.h> 15 #include <net/dsa.h> 16 #include <net/switchdev.h> 17 18 #include "ksz9477_reg.h" 19 #include "ksz_common.h" 20 #include "ksz9477.h" 21 22 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 23 { 24 regmap_update_bits(ksz_regmap_8(dev), addr, bits, set ? bits : 0); 25 } 26 27 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 28 bool set) 29 { 30 regmap_update_bits(ksz_regmap_8(dev), PORT_CTRL_ADDR(port, offset), 31 bits, set ? bits : 0); 32 } 33 34 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 35 { 36 regmap_update_bits(ksz_regmap_32(dev), addr, bits, set ? bits : 0); 37 } 38 39 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 40 u32 bits, bool set) 41 { 42 regmap_update_bits(ksz_regmap_32(dev), PORT_CTRL_ADDR(port, offset), 43 bits, set ? bits : 0); 44 } 45 46 int ksz9477_change_mtu(struct ksz_device *dev, int port, int mtu) 47 { 48 u16 frame_size; 49 50 if (!dsa_is_cpu_port(dev->ds, port)) 51 return 0; 52 53 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 54 55 return regmap_update_bits(ksz_regmap_16(dev), REG_SW_MTU__2, 56 REG_SW_MTU_MASK, frame_size); 57 } 58 59 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev) 60 { 61 unsigned int val; 62 63 return regmap_read_poll_timeout(ksz_regmap_8(dev), REG_SW_VLAN_CTRL, 64 val, !(val & VLAN_START), 10, 1000); 65 } 66 67 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 68 u32 *vlan_table) 69 { 70 int ret; 71 72 mutex_lock(&dev->vlan_mutex); 73 74 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 75 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 76 77 /* wait to be cleared */ 78 ret = ksz9477_wait_vlan_ctrl_ready(dev); 79 if (ret) { 80 dev_dbg(dev->dev, "Failed to read vlan table\n"); 81 goto exit; 82 } 83 84 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 85 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 86 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 87 88 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 89 90 exit: 91 mutex_unlock(&dev->vlan_mutex); 92 93 return ret; 94 } 95 96 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 97 u32 *vlan_table) 98 { 99 int ret; 100 101 mutex_lock(&dev->vlan_mutex); 102 103 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 104 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 105 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 106 107 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 108 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 109 110 /* wait to be cleared */ 111 ret = ksz9477_wait_vlan_ctrl_ready(dev); 112 if (ret) { 113 dev_dbg(dev->dev, "Failed to write vlan table\n"); 114 goto exit; 115 } 116 117 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 118 119 /* update vlan cache table */ 120 dev->vlan_cache[vid].table[0] = vlan_table[0]; 121 dev->vlan_cache[vid].table[1] = vlan_table[1]; 122 dev->vlan_cache[vid].table[2] = vlan_table[2]; 123 124 exit: 125 mutex_unlock(&dev->vlan_mutex); 126 127 return ret; 128 } 129 130 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 131 { 132 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 133 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 134 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 135 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 136 } 137 138 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 139 { 140 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 141 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 142 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 143 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 144 } 145 146 static int ksz9477_wait_alu_ready(struct ksz_device *dev) 147 { 148 unsigned int val; 149 150 return regmap_read_poll_timeout(ksz_regmap_32(dev), REG_SW_ALU_CTRL__4, 151 val, !(val & ALU_START), 10, 1000); 152 } 153 154 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev) 155 { 156 unsigned int val; 157 158 return regmap_read_poll_timeout(ksz_regmap_32(dev), 159 REG_SW_ALU_STAT_CTRL__4, 160 val, !(val & ALU_STAT_START), 161 10, 1000); 162 } 163 164 static void port_sgmii_s(struct ksz_device *dev, uint port, u16 devid, u16 reg) 165 { 166 u32 data; 167 168 data = (devid & MII_MMD_CTRL_DEVAD_MASK) << 16; 169 data |= reg; 170 ksz_pwrite32(dev, port, REG_PORT_SGMII_ADDR__4, data); 171 } 172 173 static void port_sgmii_r(struct ksz_device *dev, uint port, u16 devid, u16 reg, 174 u16 *buf) 175 { 176 port_sgmii_s(dev, port, devid, reg); 177 ksz_pread16(dev, port, REG_PORT_SGMII_DATA__4 + 2, buf); 178 } 179 180 static void port_sgmii_w(struct ksz_device *dev, uint port, u16 devid, u16 reg, 181 u16 buf) 182 { 183 port_sgmii_s(dev, port, devid, reg); 184 ksz_pwrite32(dev, port, REG_PORT_SGMII_DATA__4, buf); 185 } 186 187 static int ksz9477_pcs_read(struct mii_bus *bus, int phy, int mmd, int reg) 188 { 189 struct ksz_device *dev = bus->priv; 190 int port = ksz_get_sgmii_port(dev); 191 u16 val; 192 193 port_sgmii_r(dev, port, mmd, reg, &val); 194 195 /* Simulate a value to activate special code in the XPCS driver if 196 * supported. 197 */ 198 if (mmd == MDIO_MMD_PMAPMD) { 199 if (reg == MDIO_DEVID1) 200 val = 0x9477; 201 else if (reg == MDIO_DEVID2) 202 val = 0x22 << 10; 203 } else if (mmd == MDIO_MMD_VEND2) { 204 struct ksz_port *p = &dev->ports[port]; 205 206 /* Need to update MII_BMCR register with the exact speed and 207 * duplex mode when running in SGMII mode and this register is 208 * used to detect connected speed in that mode. 209 */ 210 if (reg == MMD_SR_MII_AUTO_NEG_STATUS) { 211 int duplex, speed; 212 213 if (val & SR_MII_STAT_LINK_UP) { 214 speed = (val >> SR_MII_STAT_S) & SR_MII_STAT_M; 215 if (speed == SR_MII_STAT_1000_MBPS) 216 speed = SPEED_1000; 217 else if (speed == SR_MII_STAT_100_MBPS) 218 speed = SPEED_100; 219 else 220 speed = SPEED_10; 221 222 if (val & SR_MII_STAT_FULL_DUPLEX) 223 duplex = DUPLEX_FULL; 224 else 225 duplex = DUPLEX_HALF; 226 227 if (!p->link || p->speed != speed || 228 p->duplex != duplex) { 229 u16 ctrl; 230 231 p->link = true; 232 p->speed = speed; 233 p->duplex = duplex; 234 port_sgmii_r(dev, port, mmd, MII_BMCR, 235 &ctrl); 236 ctrl &= BMCR_ANENABLE; 237 ctrl |= mii_bmcr_encode_fixed(speed, 238 duplex); 239 port_sgmii_w(dev, port, mmd, MII_BMCR, 240 ctrl); 241 } 242 } else { 243 p->link = false; 244 } 245 } else if (reg == MII_BMSR) { 246 p->link = !!(val & BMSR_LSTATUS); 247 } 248 } 249 250 return val; 251 } 252 253 static int ksz9477_pcs_write(struct mii_bus *bus, int phy, int mmd, int reg, 254 u16 val) 255 { 256 struct ksz_device *dev = bus->priv; 257 int port = ksz_get_sgmii_port(dev); 258 259 if (mmd == MDIO_MMD_VEND2) { 260 struct ksz_port *p = &dev->ports[port]; 261 262 if (reg == MMD_SR_MII_AUTO_NEG_CTRL) { 263 u16 sgmii_mode = SR_MII_PCS_SGMII << SR_MII_PCS_MODE_S; 264 265 /* Need these bits for 1000BASE-X mode to work with 266 * AN on. 267 */ 268 if (!(val & sgmii_mode)) 269 val |= SR_MII_SGMII_LINK_UP | 270 SR_MII_TX_CFG_PHY_MASTER; 271 272 /* SGMII interrupt in the port cannot be masked, so 273 * make sure interrupt is not enabled as it is not 274 * handled. 275 */ 276 val &= ~SR_MII_AUTO_NEG_COMPLETE_INTR; 277 } else if (reg == MII_BMCR) { 278 /* The MII_ADVERTISE register needs to write once 279 * before doing auto-negotiation for the correct 280 * config_word to be sent out after reset. 281 */ 282 if ((val & BMCR_ANENABLE) && !p->sgmii_adv_write) { 283 u16 adv; 284 285 /* The SGMII port cannot disable flow control 286 * so it is better to just advertise symmetric 287 * pause. 288 */ 289 port_sgmii_r(dev, port, mmd, MII_ADVERTISE, 290 &adv); 291 adv |= ADVERTISE_1000XPAUSE; 292 adv &= ~ADVERTISE_1000XPSE_ASYM; 293 port_sgmii_w(dev, port, mmd, MII_ADVERTISE, 294 adv); 295 p->sgmii_adv_write = 1; 296 } else if (val & BMCR_RESET) { 297 p->sgmii_adv_write = 0; 298 } 299 } else if (reg == MII_ADVERTISE) { 300 /* XPCS driver writes to this register so there is no 301 * need to update it for the errata. 302 */ 303 p->sgmii_adv_write = 1; 304 } 305 } 306 port_sgmii_w(dev, port, mmd, reg, val); 307 308 return 0; 309 } 310 311 int ksz9477_pcs_create(struct ksz_device *dev) 312 { 313 int port = ksz_get_sgmii_port(dev); 314 struct ksz_port *p = &dev->ports[port]; 315 struct phylink_pcs *pcs; 316 struct mii_bus *bus; 317 int ret; 318 319 bus = devm_mdiobus_alloc(dev->dev); 320 if (!bus) 321 return -ENOMEM; 322 323 bus->name = "ksz_pcs_mdio_bus"; 324 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-pcs", 325 dev_name(dev->dev)); 326 bus->read_c45 = &ksz9477_pcs_read; 327 bus->write_c45 = &ksz9477_pcs_write; 328 bus->parent = dev->dev; 329 bus->phy_mask = ~0; 330 bus->priv = dev; 331 332 ret = devm_mdiobus_register(dev->dev, bus); 333 if (ret) 334 return ret; 335 336 pcs = xpcs_create_pcs_mdiodev(bus, 0); 337 if (IS_ERR(pcs)) 338 return PTR_ERR(pcs); 339 p->pcs = pcs; 340 341 return 0; 342 } 343 344 int ksz9477_reset_switch(struct ksz_device *dev) 345 { 346 u8 data8; 347 u32 data32; 348 349 /* reset switch */ 350 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 351 352 /* turn off SPI DO Edge select */ 353 regmap_update_bits(ksz_regmap_8(dev), REG_SW_GLOBAL_SERIAL_CTRL_0, 354 SPI_AUTO_EDGE_DETECTION, 0); 355 356 /* default configuration */ 357 ksz_write8(dev, REG_SW_LUE_CTRL_1, 358 SW_AGING_ENABLE | SW_LINK_AUTO_AGING | SW_SRC_ADDR_FILTER); 359 360 /* disable interrupts */ 361 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 362 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 363 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 364 365 /* KSZ9893 compatible chips do not support refclk configuration */ 366 if (dev->chip_id == KSZ9893_CHIP_ID || 367 dev->chip_id == KSZ8563_CHIP_ID || 368 dev->chip_id == KSZ9563_CHIP_ID) 369 return 0; 370 371 data8 = SW_ENABLE_REFCLKO; 372 if (dev->synclko_disable) 373 data8 = 0; 374 else if (dev->synclko_125) 375 data8 = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ; 376 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, data8); 377 378 return 0; 379 } 380 381 void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 382 { 383 struct ksz_port *p = &dev->ports[port]; 384 unsigned int val; 385 u32 data; 386 int ret; 387 388 /* retain the flush/freeze bit */ 389 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 390 data |= MIB_COUNTER_READ; 391 data |= (addr << MIB_COUNTER_INDEX_S); 392 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 393 394 ret = regmap_read_poll_timeout(ksz_regmap_32(dev), 395 PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4), 396 val, !(val & MIB_COUNTER_READ), 10, 1000); 397 /* failed to read MIB. get out of loop */ 398 if (ret) { 399 dev_dbg(dev->dev, "Failed to get MIB\n"); 400 return; 401 } 402 403 /* count resets upon read */ 404 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 405 *cnt += data; 406 } 407 408 void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 409 u64 *dropped, u64 *cnt) 410 { 411 addr = dev->info->mib_names[addr].index; 412 ksz9477_r_mib_cnt(dev, port, addr, cnt); 413 } 414 415 void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze) 416 { 417 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 418 struct ksz_port *p = &dev->ports[port]; 419 420 /* enable/disable the port for flush/freeze function */ 421 mutex_lock(&p->mib.cnt_mutex); 422 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); 423 424 /* used by MIB counter reading code to know freeze is enabled */ 425 p->freeze = freeze; 426 mutex_unlock(&p->mib.cnt_mutex); 427 } 428 429 static int ksz9477_half_duplex_monitor(struct ksz_device *dev, int port, 430 u64 tx_late_col) 431 { 432 u8 lue_ctrl; 433 u32 pmavbc; 434 u16 pqm; 435 int ret; 436 437 /* Errata DS80000754 recommends monitoring potential faults in 438 * half-duplex mode. The switch might not be able to communicate anymore 439 * in these states. If you see this message, please read the 440 * errata-sheet for more information: 441 * https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/Errata/KSZ9477S-Errata-DS80000754.pdf 442 * To workaround this issue, half-duplex mode should be avoided. 443 * A software reset could be implemented to recover from this state. 444 */ 445 dev_warn_once(dev->dev, 446 "Half-duplex detected on port %d, transmission halt may occur\n", 447 port); 448 if (tx_late_col != 0) { 449 /* Transmission halt with late collisions */ 450 dev_crit_once(dev->dev, 451 "TX late collisions detected, transmission may be halted on port %d\n", 452 port); 453 } 454 ret = ksz_read8(dev, REG_SW_LUE_CTRL_0, &lue_ctrl); 455 if (ret) 456 return ret; 457 if (lue_ctrl & SW_VLAN_ENABLE) { 458 ret = ksz_pread16(dev, port, REG_PORT_QM_TX_CNT_0__4, &pqm); 459 if (ret) 460 return ret; 461 462 ret = ksz_read32(dev, REG_PMAVBC, &pmavbc); 463 if (ret) 464 return ret; 465 466 if ((FIELD_GET(PMAVBC_MASK, pmavbc) <= PMAVBC_MIN) || 467 (FIELD_GET(PORT_QM_TX_CNT_M, pqm) >= PORT_QM_TX_CNT_MAX)) { 468 /* Transmission halt with Half-Duplex and VLAN */ 469 dev_crit_once(dev->dev, 470 "resources out of limits, transmission may be halted\n"); 471 } 472 } 473 474 return ret; 475 } 476 477 int ksz9477_errata_monitor(struct ksz_device *dev, int port, 478 u64 tx_late_col) 479 { 480 u8 status; 481 int ret; 482 483 ret = ksz_pread8(dev, port, REG_PORT_STATUS_0, &status); 484 if (ret) 485 return ret; 486 487 if (!(FIELD_GET(PORT_INTF_SPEED_MASK, status) 488 == PORT_INTF_SPEED_NONE) && 489 !(status & PORT_INTF_FULL_DUPLEX)) { 490 ret = ksz9477_half_duplex_monitor(dev, port, tx_late_col); 491 } 492 493 return ret; 494 } 495 496 void ksz9477_port_init_cnt(struct ksz_device *dev, int port) 497 { 498 struct ksz_port_mib *mib = &dev->ports[port].mib; 499 500 /* flush all enabled port MIB counters */ 501 mutex_lock(&mib->cnt_mutex); 502 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 503 MIB_COUNTER_FLUSH_FREEZE); 504 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH); 505 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0); 506 mutex_unlock(&mib->cnt_mutex); 507 } 508 509 static void ksz9477_r_phy_quirks(struct ksz_device *dev, u16 addr, u16 reg, 510 u16 *data) 511 { 512 /* KSZ8563R do not have extended registers but BMSR_ESTATEN and 513 * BMSR_ERCAP bits are set. 514 */ 515 if (dev->chip_id == KSZ8563_CHIP_ID && reg == MII_BMSR) 516 *data &= ~(BMSR_ESTATEN | BMSR_ERCAP); 517 } 518 519 int ksz9477_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data) 520 { 521 u16 val = 0xffff; 522 int ret; 523 524 /* No real PHY after this. Simulate the PHY. 525 * A fixed PHY can be setup in the device tree, but this function is 526 * still called for that port during initialization. 527 * For RGMII PHY there is no way to access it so the fixed PHY should 528 * be used. 529 */ 530 if (!dev->info->internal_phy[addr]) { 531 struct ksz_port *p = &dev->ports[addr]; 532 533 switch (reg) { 534 case MII_BMCR: 535 val = 0x1140; 536 break; 537 case MII_BMSR: 538 val = 0x796d; 539 break; 540 case MII_PHYSID1: 541 val = 0x0022; 542 break; 543 case MII_PHYSID2: 544 val = 0x1631; 545 break; 546 case MII_ADVERTISE: 547 val = 0x05e1; 548 break; 549 case MII_LPA: 550 val = 0xc5e1; 551 break; 552 case MII_CTRL1000: 553 val = 0x0700; 554 break; 555 case MII_STAT1000: 556 if (p->speed == SPEED_1000) 557 val = 0x3800; 558 else 559 val = 0; 560 break; 561 } 562 } else { 563 ret = ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 564 if (ret) 565 return ret; 566 567 ksz9477_r_phy_quirks(dev, addr, reg, &val); 568 } 569 570 *data = val; 571 572 return 0; 573 } 574 575 int ksz9477_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val) 576 { 577 u32 mask, val32; 578 579 /* No real PHY after this. */ 580 if (!dev->info->internal_phy[addr]) 581 return 0; 582 583 if (reg < 0x10) 584 return ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 585 586 /* Errata: When using SPI, I2C, or in-band register access, 587 * writes to certain PHY registers should be performed as 588 * 32-bit writes instead of 16-bit writes. 589 */ 590 val32 = val; 591 mask = 0xffff; 592 if ((reg & 1) == 0) { 593 val32 <<= 16; 594 mask <<= 16; 595 } 596 reg &= ~1; 597 return ksz_prmw32(dev, addr, 0x100 + (reg << 1), mask, val32); 598 } 599 600 void ksz9477_cfg_port_member(struct ksz_device *dev, int port, u8 member) 601 { 602 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 603 } 604 605 void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 606 { 607 const u16 *regs = dev->info->regs; 608 u8 data; 609 610 regmap_update_bits(ksz_regmap_8(dev), REG_SW_LUE_CTRL_2, 611 SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S, 612 SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 613 614 if (port < dev->info->port_cnt) { 615 /* flush individual port */ 616 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 617 if (!(data & PORT_LEARN_DISABLE)) 618 ksz_pwrite8(dev, port, regs[P_STP_CTRL], 619 data | PORT_LEARN_DISABLE); 620 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 621 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 622 } else { 623 /* flush all */ 624 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 625 } 626 } 627 628 int ksz9477_port_vlan_filtering(struct ksz_device *dev, int port, 629 bool flag, struct netlink_ext_ack *extack) 630 { 631 if (flag) { 632 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 633 PORT_VLAN_LOOKUP_VID_0, true); 634 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 635 } else { 636 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 637 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 638 PORT_VLAN_LOOKUP_VID_0, false); 639 } 640 641 return 0; 642 } 643 644 int ksz9477_port_vlan_add(struct ksz_device *dev, int port, 645 const struct switchdev_obj_port_vlan *vlan, 646 struct netlink_ext_ack *extack) 647 { 648 u32 vlan_table[3]; 649 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 650 int err; 651 652 err = ksz9477_get_vlan_table(dev, vlan->vid, vlan_table); 653 if (err) { 654 NL_SET_ERR_MSG_MOD(extack, "Failed to get vlan table"); 655 return err; 656 } 657 658 vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M); 659 if (untagged) 660 vlan_table[1] |= BIT(port); 661 else 662 vlan_table[1] &= ~BIT(port); 663 vlan_table[1] &= ~(BIT(dev->cpu_port)); 664 665 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 666 667 err = ksz9477_set_vlan_table(dev, vlan->vid, vlan_table); 668 if (err) { 669 NL_SET_ERR_MSG_MOD(extack, "Failed to set vlan table"); 670 return err; 671 } 672 673 /* change PVID */ 674 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 675 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid); 676 677 return 0; 678 } 679 680 int ksz9477_port_vlan_del(struct ksz_device *dev, int port, 681 const struct switchdev_obj_port_vlan *vlan) 682 { 683 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 684 u32 vlan_table[3]; 685 u16 pvid; 686 687 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 688 pvid = pvid & 0xFFF; 689 690 if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) { 691 dev_dbg(dev->dev, "Failed to get vlan table\n"); 692 return -ETIMEDOUT; 693 } 694 695 vlan_table[2] &= ~BIT(port); 696 697 if (pvid == vlan->vid) 698 pvid = 1; 699 700 if (untagged) 701 vlan_table[1] &= ~BIT(port); 702 703 if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) { 704 dev_dbg(dev->dev, "Failed to set vlan table\n"); 705 return -ETIMEDOUT; 706 } 707 708 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 709 710 return 0; 711 } 712 713 int ksz9477_fdb_add(struct ksz_device *dev, int port, 714 const unsigned char *addr, u16 vid, struct dsa_db db) 715 { 716 u32 alu_table[4]; 717 u32 data; 718 int ret = 0; 719 720 mutex_lock(&dev->alu_mutex); 721 722 /* find any entry with mac & vid */ 723 data = vid << ALU_FID_INDEX_S; 724 data |= ((addr[0] << 8) | addr[1]); 725 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 726 727 data = ((addr[2] << 24) | (addr[3] << 16)); 728 data |= ((addr[4] << 8) | addr[5]); 729 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 730 731 /* start read operation */ 732 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 733 734 /* wait to be finished */ 735 ret = ksz9477_wait_alu_ready(dev); 736 if (ret) { 737 dev_dbg(dev->dev, "Failed to read ALU\n"); 738 goto exit; 739 } 740 741 /* read ALU entry */ 742 ksz9477_read_table(dev, alu_table); 743 744 /* update ALU entry */ 745 alu_table[0] = ALU_V_STATIC_VALID; 746 alu_table[1] |= BIT(port); 747 if (vid) 748 alu_table[1] |= ALU_V_USE_FID; 749 alu_table[2] = (vid << ALU_V_FID_S); 750 alu_table[2] |= ((addr[0] << 8) | addr[1]); 751 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 752 alu_table[3] |= ((addr[4] << 8) | addr[5]); 753 754 ksz9477_write_table(dev, alu_table); 755 756 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 757 758 /* wait to be finished */ 759 ret = ksz9477_wait_alu_ready(dev); 760 if (ret) 761 dev_dbg(dev->dev, "Failed to write ALU\n"); 762 763 exit: 764 mutex_unlock(&dev->alu_mutex); 765 766 return ret; 767 } 768 769 int ksz9477_fdb_del(struct ksz_device *dev, int port, 770 const unsigned char *addr, u16 vid, struct dsa_db db) 771 { 772 u32 alu_table[4]; 773 u32 data; 774 int ret = 0; 775 776 mutex_lock(&dev->alu_mutex); 777 778 /* read any entry with mac & vid */ 779 data = vid << ALU_FID_INDEX_S; 780 data |= ((addr[0] << 8) | addr[1]); 781 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 782 783 data = ((addr[2] << 24) | (addr[3] << 16)); 784 data |= ((addr[4] << 8) | addr[5]); 785 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 786 787 /* start read operation */ 788 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 789 790 /* wait to be finished */ 791 ret = ksz9477_wait_alu_ready(dev); 792 if (ret) { 793 dev_dbg(dev->dev, "Failed to read ALU\n"); 794 goto exit; 795 } 796 797 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 798 if (alu_table[0] & ALU_V_STATIC_VALID) { 799 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 800 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 801 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 802 803 /* clear forwarding port */ 804 alu_table[1] &= ~BIT(port); 805 806 /* if there is no port to forward, clear table */ 807 if ((alu_table[1] & ALU_V_PORT_MAP) == 0) { 808 alu_table[0] = 0; 809 alu_table[1] = 0; 810 alu_table[2] = 0; 811 alu_table[3] = 0; 812 } 813 } else { 814 alu_table[0] = 0; 815 alu_table[1] = 0; 816 alu_table[2] = 0; 817 alu_table[3] = 0; 818 } 819 820 ksz9477_write_table(dev, alu_table); 821 822 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 823 824 /* wait to be finished */ 825 ret = ksz9477_wait_alu_ready(dev); 826 if (ret) 827 dev_dbg(dev->dev, "Failed to write ALU\n"); 828 829 exit: 830 mutex_unlock(&dev->alu_mutex); 831 832 return ret; 833 } 834 835 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 836 { 837 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 838 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 839 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 840 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 841 ALU_V_PRIO_AGE_CNT_M; 842 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 843 844 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 845 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 846 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 847 848 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 849 850 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 851 alu->mac[1] = alu_table[2] & 0xFF; 852 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 853 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 854 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 855 alu->mac[5] = alu_table[3] & 0xFF; 856 } 857 858 int ksz9477_fdb_dump(struct ksz_device *dev, int port, 859 dsa_fdb_dump_cb_t *cb, void *data) 860 { 861 int ret = 0; 862 u32 ksz_data; 863 u32 alu_table[4]; 864 struct alu_struct alu; 865 int timeout; 866 867 mutex_lock(&dev->alu_mutex); 868 869 /* start ALU search */ 870 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 871 872 do { 873 timeout = 1000; 874 do { 875 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 876 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 877 break; 878 usleep_range(1, 10); 879 } while (timeout-- > 0); 880 881 if (!timeout) { 882 dev_dbg(dev->dev, "Failed to search ALU\n"); 883 ret = -ETIMEDOUT; 884 goto exit; 885 } 886 887 if (!(ksz_data & ALU_VALID)) 888 continue; 889 890 /* read ALU table */ 891 ksz9477_read_table(dev, alu_table); 892 893 ksz9477_convert_alu(&alu, alu_table); 894 895 if (alu.port_forward & BIT(port)) { 896 ret = cb(alu.mac, alu.fid, alu.is_static, data); 897 if (ret) 898 goto exit; 899 } 900 } while (ksz_data & ALU_START); 901 902 exit: 903 904 /* stop ALU search */ 905 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 906 907 mutex_unlock(&dev->alu_mutex); 908 909 return ret; 910 } 911 912 int ksz9477_mdb_add(struct ksz_device *dev, int port, 913 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 914 { 915 u32 static_table[4]; 916 const u8 *shifts; 917 const u32 *masks; 918 u32 data; 919 int index; 920 u32 mac_hi, mac_lo; 921 int err = 0; 922 923 shifts = dev->info->shifts; 924 masks = dev->info->masks; 925 926 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 927 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 928 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 929 930 mutex_lock(&dev->alu_mutex); 931 932 for (index = 0; index < dev->info->num_statics; index++) { 933 /* find empty slot first */ 934 data = (index << shifts[ALU_STAT_INDEX]) | 935 masks[ALU_STAT_READ] | ALU_STAT_START; 936 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 937 938 /* wait to be finished */ 939 err = ksz9477_wait_alu_sta_ready(dev); 940 if (err) { 941 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 942 goto exit; 943 } 944 945 /* read ALU static table */ 946 ksz9477_read_table(dev, static_table); 947 948 if (static_table[0] & ALU_V_STATIC_VALID) { 949 /* check this has same vid & mac address */ 950 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 951 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 952 static_table[3] == mac_lo) { 953 /* found matching one */ 954 break; 955 } 956 } else { 957 /* found empty one */ 958 break; 959 } 960 } 961 962 /* no available entry */ 963 if (index == dev->info->num_statics) { 964 err = -ENOSPC; 965 goto exit; 966 } 967 968 /* add entry */ 969 static_table[0] = ALU_V_STATIC_VALID; 970 static_table[1] |= BIT(port); 971 if (mdb->vid) 972 static_table[1] |= ALU_V_USE_FID; 973 static_table[2] = (mdb->vid << ALU_V_FID_S); 974 static_table[2] |= mac_hi; 975 static_table[3] = mac_lo; 976 977 ksz9477_write_table(dev, static_table); 978 979 data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; 980 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 981 982 /* wait to be finished */ 983 if (ksz9477_wait_alu_sta_ready(dev)) 984 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 985 986 exit: 987 mutex_unlock(&dev->alu_mutex); 988 return err; 989 } 990 991 int ksz9477_mdb_del(struct ksz_device *dev, int port, 992 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 993 { 994 u32 static_table[4]; 995 const u8 *shifts; 996 const u32 *masks; 997 u32 data; 998 int index; 999 int ret = 0; 1000 u32 mac_hi, mac_lo; 1001 1002 shifts = dev->info->shifts; 1003 masks = dev->info->masks; 1004 1005 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 1006 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 1007 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 1008 1009 mutex_lock(&dev->alu_mutex); 1010 1011 for (index = 0; index < dev->info->num_statics; index++) { 1012 /* find empty slot first */ 1013 data = (index << shifts[ALU_STAT_INDEX]) | 1014 masks[ALU_STAT_READ] | ALU_STAT_START; 1015 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1016 1017 /* wait to be finished */ 1018 ret = ksz9477_wait_alu_sta_ready(dev); 1019 if (ret) { 1020 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 1021 goto exit; 1022 } 1023 1024 /* read ALU static table */ 1025 ksz9477_read_table(dev, static_table); 1026 1027 if (static_table[0] & ALU_V_STATIC_VALID) { 1028 /* check this has same vid & mac address */ 1029 1030 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 1031 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 1032 static_table[3] == mac_lo) { 1033 /* found matching one */ 1034 break; 1035 } 1036 } 1037 } 1038 1039 /* no available entry */ 1040 if (index == dev->info->num_statics) 1041 goto exit; 1042 1043 /* clear port */ 1044 static_table[1] &= ~BIT(port); 1045 1046 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 1047 /* delete entry */ 1048 static_table[0] = 0; 1049 static_table[1] = 0; 1050 static_table[2] = 0; 1051 static_table[3] = 0; 1052 } 1053 1054 ksz9477_write_table(dev, static_table); 1055 1056 data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; 1057 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1058 1059 /* wait to be finished */ 1060 ret = ksz9477_wait_alu_sta_ready(dev); 1061 if (ret) 1062 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 1063 1064 exit: 1065 mutex_unlock(&dev->alu_mutex); 1066 1067 return ret; 1068 } 1069 1070 int ksz9477_port_mirror_add(struct ksz_device *dev, int port, 1071 struct dsa_mall_mirror_tc_entry *mirror, 1072 bool ingress, struct netlink_ext_ack *extack) 1073 { 1074 u8 data; 1075 int p; 1076 1077 /* Limit to one sniffer port 1078 * Check if any of the port is already set for sniffing 1079 * If yes, instruct the user to remove the previous entry & exit 1080 */ 1081 for (p = 0; p < dev->info->port_cnt; p++) { 1082 /* Skip the current sniffing port */ 1083 if (p == mirror->to_local_port) 1084 continue; 1085 1086 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 1087 1088 if (data & PORT_MIRROR_SNIFFER) { 1089 NL_SET_ERR_MSG_MOD(extack, 1090 "Sniffer port is already configured, delete existing rules & retry"); 1091 return -EBUSY; 1092 } 1093 } 1094 1095 if (ingress) 1096 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 1097 else 1098 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 1099 1100 /* configure mirror port */ 1101 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1102 PORT_MIRROR_SNIFFER, true); 1103 1104 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 1105 1106 return 0; 1107 } 1108 1109 void ksz9477_port_mirror_del(struct ksz_device *dev, int port, 1110 struct dsa_mall_mirror_tc_entry *mirror) 1111 { 1112 bool in_use = false; 1113 u8 data; 1114 int p; 1115 1116 if (mirror->ingress) 1117 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 1118 else 1119 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 1120 1121 1122 /* Check if any of the port is still referring to sniffer port */ 1123 for (p = 0; p < dev->info->port_cnt; p++) { 1124 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 1125 1126 if ((data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) { 1127 in_use = true; 1128 break; 1129 } 1130 } 1131 1132 /* delete sniffing if there are no other mirroring rules */ 1133 if (!in_use) 1134 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1135 PORT_MIRROR_SNIFFER, false); 1136 } 1137 1138 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) 1139 { 1140 phy_interface_t interface; 1141 bool gbit; 1142 1143 if (dev->info->internal_phy[port]) 1144 return PHY_INTERFACE_MODE_NA; 1145 1146 gbit = ksz_get_gbit(dev, port); 1147 1148 interface = ksz_get_xmii(dev, port, gbit); 1149 1150 return interface; 1151 } 1152 1153 void ksz9477_get_caps(struct ksz_device *dev, int port, 1154 struct phylink_config *config) 1155 { 1156 config->mac_capabilities = MAC_10 | MAC_100 | MAC_ASYM_PAUSE | 1157 MAC_SYM_PAUSE; 1158 1159 if (dev->info->gbit_capable[port]) 1160 config->mac_capabilities |= MAC_1000FD; 1161 1162 if (ksz_is_sgmii_port(dev, port)) { 1163 struct ksz_port *p = &dev->ports[port]; 1164 1165 phy_interface_or(config->supported_interfaces, 1166 config->supported_interfaces, 1167 p->pcs->supported_interfaces); 1168 } 1169 } 1170 1171 int ksz9477_set_ageing_time(struct ksz_device *dev, unsigned int msecs) 1172 { 1173 u32 secs = msecs / 1000; 1174 u8 data, mult, value; 1175 u32 max_val; 1176 int ret; 1177 1178 #define MAX_TIMER_VAL ((1 << 8) - 1) 1179 1180 /* The aging timer comprises a 3-bit multiplier and an 8-bit second 1181 * value. Either of them cannot be zero. The maximum timer is then 1182 * 7 * 255 = 1785 seconds. 1183 */ 1184 if (!secs) 1185 secs = 1; 1186 1187 /* Return error if too large. */ 1188 else if (secs > 7 * MAX_TIMER_VAL) 1189 return -EINVAL; 1190 1191 ret = ksz_read8(dev, REG_SW_LUE_CTRL_0, &value); 1192 if (ret < 0) 1193 return ret; 1194 1195 /* Check whether there is need to update the multiplier. */ 1196 mult = FIELD_GET(SW_AGE_CNT_M, value); 1197 max_val = MAX_TIMER_VAL; 1198 if (mult > 0) { 1199 /* Try to use the same multiplier already in the register as 1200 * the hardware default uses multiplier 4 and 75 seconds for 1201 * 300 seconds. 1202 */ 1203 max_val = DIV_ROUND_UP(secs, mult); 1204 if (max_val > MAX_TIMER_VAL || max_val * mult != secs) 1205 max_val = MAX_TIMER_VAL; 1206 } 1207 1208 data = DIV_ROUND_UP(secs, max_val); 1209 if (mult != data) { 1210 value &= ~SW_AGE_CNT_M; 1211 value |= FIELD_PREP(SW_AGE_CNT_M, data); 1212 ret = ksz_write8(dev, REG_SW_LUE_CTRL_0, value); 1213 if (ret < 0) 1214 return ret; 1215 } 1216 1217 value = DIV_ROUND_UP(secs, data); 1218 return ksz_write8(dev, REG_SW_LUE_CTRL_3, value); 1219 } 1220 1221 void ksz9477_port_queue_split(struct ksz_device *dev, int port) 1222 { 1223 u8 data; 1224 1225 if (dev->info->num_tx_queues == 8) 1226 data = PORT_EIGHT_QUEUE; 1227 else if (dev->info->num_tx_queues == 4) 1228 data = PORT_FOUR_QUEUE; 1229 else if (dev->info->num_tx_queues == 2) 1230 data = PORT_TWO_QUEUE; 1231 else 1232 data = PORT_SINGLE_QUEUE; 1233 1234 ksz_prmw8(dev, port, REG_PORT_CTRL_0, PORT_QUEUE_SPLIT_MASK, data); 1235 } 1236 1237 void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1238 { 1239 const u16 *regs = dev->info->regs; 1240 struct dsa_switch *ds = dev->ds; 1241 u16 data16; 1242 u8 member; 1243 1244 /* enable tag tail for host port */ 1245 if (cpu_port) 1246 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 1247 true); 1248 1249 ksz9477_port_queue_split(dev, port); 1250 1251 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 1252 1253 /* set back pressure */ 1254 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 1255 1256 /* enable broadcast storm limit */ 1257 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1258 1259 /* replace priority */ 1260 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 1261 false); 1262 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 1263 MTI_PVID_REPLACE, false); 1264 1265 /* force flow control for non-PHY ports only */ 1266 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1267 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1268 !dev->info->internal_phy[port]); 1269 1270 if (cpu_port) 1271 member = dsa_user_ports(ds); 1272 else 1273 member = BIT(dsa_upstream_port(ds, port)); 1274 1275 ksz9477_cfg_port_member(dev, port, member); 1276 1277 /* clear pending interrupts */ 1278 if (dev->info->internal_phy[port]) 1279 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1280 1281 ksz9477_port_acl_init(dev, port); 1282 1283 /* clear pending wake flags */ 1284 ksz_handle_wake_reason(dev, port); 1285 1286 /* Disable all WoL options by default. Otherwise 1287 * ksz_switch_macaddr_get/put logic will not work properly. 1288 */ 1289 ksz_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 0); 1290 } 1291 1292 void ksz9477_config_cpu_port(struct dsa_switch *ds) 1293 { 1294 struct ksz_device *dev = ds->priv; 1295 struct ksz_port *p; 1296 int i; 1297 1298 for (i = 0; i < dev->info->port_cnt; i++) { 1299 if (dsa_is_cpu_port(ds, i) && 1300 (dev->info->cpu_ports & (1 << i))) { 1301 phy_interface_t interface; 1302 const char *prev_msg; 1303 const char *prev_mode; 1304 1305 dev->cpu_port = i; 1306 p = &dev->ports[i]; 1307 1308 /* Read from XMII register to determine host port 1309 * interface. If set specifically in device tree 1310 * note the difference to help debugging. 1311 */ 1312 interface = ksz9477_get_interface(dev, i); 1313 if (!p->interface) { 1314 if (dev->compat_interface) { 1315 dev_warn(dev->dev, 1316 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1317 "Please update your device tree.\n", 1318 i); 1319 p->interface = dev->compat_interface; 1320 } else { 1321 p->interface = interface; 1322 } 1323 } 1324 if (interface && interface != p->interface) { 1325 prev_msg = " instead of "; 1326 prev_mode = phy_modes(interface); 1327 } else { 1328 prev_msg = ""; 1329 prev_mode = ""; 1330 } 1331 dev_info(dev->dev, 1332 "Port%d: using phy mode %s%s%s\n", 1333 i, 1334 phy_modes(p->interface), 1335 prev_msg, 1336 prev_mode); 1337 1338 /* enable cpu port */ 1339 ksz9477_port_setup(dev, i, true); 1340 } 1341 } 1342 1343 for (i = 0; i < dev->info->port_cnt; i++) { 1344 if (i == dev->cpu_port) 1345 continue; 1346 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1347 1348 /* Power down the internal PHY if port is unused. */ 1349 if (dsa_is_unused_port(ds, i) && dev->info->internal_phy[i]) 1350 ksz_pwrite16(dev, i, 0x100, BMCR_PDOWN); 1351 } 1352 } 1353 1354 #define RESV_MCAST_CNT 8 1355 1356 static u8 reserved_mcast_map[RESV_MCAST_CNT] = { 0, 1, 3, 16, 32, 33, 2, 17 }; 1357 1358 int ksz9477_enable_stp_addr(struct ksz_device *dev) 1359 { 1360 u8 i, ports, update; 1361 const u32 *masks; 1362 bool override; 1363 u32 data; 1364 int ret; 1365 1366 masks = dev->info->masks; 1367 1368 /* Enable Reserved multicast table */ 1369 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_RESV_MCAST_ENABLE, true); 1370 1371 /* The reserved multicast address table has 8 entries. Each entry has 1372 * a default value of which port to forward. It is assumed the host 1373 * port is the last port in most of the switches, but that is not the 1374 * case for KSZ9477 or maybe KSZ9897. For LAN937X family the default 1375 * port is port 5, the first RGMII port. It is okay for LAN9370, a 1376 * 5-port switch, but may not be correct for the other 8-port 1377 * versions. It is necessary to update the whole table to forward to 1378 * the right ports. 1379 * Furthermore PTP messages can use a reserved multicast address and 1380 * the host will not receive them if this table is not correct. 1381 */ 1382 for (i = 0; i < RESV_MCAST_CNT; i++) { 1383 data = reserved_mcast_map[i] << 1384 dev->info->shifts[ALU_STAT_INDEX]; 1385 data |= ALU_STAT_START | 1386 masks[ALU_STAT_DIRECT] | 1387 masks[ALU_RESV_MCAST_ADDR] | 1388 masks[ALU_STAT_READ]; 1389 ret = ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1390 if (ret < 0) 1391 return ret; 1392 1393 /* wait to be finished */ 1394 ret = ksz9477_wait_alu_sta_ready(dev); 1395 if (ret < 0) 1396 return ret; 1397 1398 ret = ksz_read32(dev, REG_SW_ALU_VAL_B, &data); 1399 if (ret < 0) 1400 return ret; 1401 1402 override = false; 1403 ports = data & dev->port_mask; 1404 switch (i) { 1405 case 0: 1406 case 6: 1407 /* Change the host port. */ 1408 update = BIT(dev->cpu_port); 1409 override = true; 1410 break; 1411 case 2: 1412 /* Change the host port. */ 1413 update = BIT(dev->cpu_port); 1414 break; 1415 case 4: 1416 case 5: 1417 case 7: 1418 /* Skip the host port. */ 1419 update = dev->port_mask & ~BIT(dev->cpu_port); 1420 break; 1421 default: 1422 update = ports; 1423 break; 1424 } 1425 if (update != ports || override) { 1426 data &= ~dev->port_mask; 1427 data |= update; 1428 /* Set Override bit to receive frame even when port is 1429 * closed. 1430 */ 1431 if (override) 1432 data |= ALU_V_OVERRIDE; 1433 ret = ksz_write32(dev, REG_SW_ALU_VAL_B, data); 1434 if (ret < 0) 1435 return ret; 1436 1437 data = reserved_mcast_map[i] << 1438 dev->info->shifts[ALU_STAT_INDEX]; 1439 data |= ALU_STAT_START | 1440 masks[ALU_STAT_DIRECT] | 1441 masks[ALU_RESV_MCAST_ADDR] | 1442 masks[ALU_STAT_WRITE]; 1443 ret = ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1444 if (ret < 0) 1445 return ret; 1446 1447 /* wait to be finished */ 1448 ret = ksz9477_wait_alu_sta_ready(dev); 1449 if (ret < 0) 1450 return ret; 1451 } 1452 } 1453 1454 return 0; 1455 } 1456 1457 int ksz9477_setup(struct dsa_switch *ds) 1458 { 1459 struct ksz_device *dev = ds->priv; 1460 const u16 *regs = dev->info->regs; 1461 int ret = 0; 1462 1463 ds->mtu_enforcement_ingress = true; 1464 1465 /* Required for port partitioning. */ 1466 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1467 true); 1468 1469 /* Do not work correctly with tail tagging. */ 1470 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false); 1471 1472 /* Enable REG_SW_MTU__2 reg by setting SW_JUMBO_PACKET */ 1473 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_JUMBO_PACKET, true); 1474 1475 /* Use collision based back pressure mode. */ 1476 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_BACK_PRESSURE, 1477 SW_BACK_PRESSURE_COLLISION); 1478 1479 /* Now we can configure default MTU value */ 1480 ret = regmap_update_bits(ksz_regmap_16(dev), REG_SW_MTU__2, REG_SW_MTU_MASK, 1481 VLAN_ETH_FRAME_LEN + ETH_FCS_LEN); 1482 if (ret) 1483 return ret; 1484 1485 /* queue based egress rate limit */ 1486 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1487 1488 /* enable global MIB counter freeze function */ 1489 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 1490 1491 /* Make sure PME (WoL) is not enabled. If requested, it will 1492 * be enabled by ksz_wol_pre_shutdown(). Otherwise, some PMICs 1493 * do not like PME events changes before shutdown. 1494 */ 1495 return ksz_write8(dev, regs[REG_SW_PME_CTRL], 0); 1496 } 1497 1498 u32 ksz9477_get_port_addr(int port, int offset) 1499 { 1500 return PORT_CTRL_ADDR(port, offset); 1501 } 1502 1503 int ksz9477_tc_cbs_set_cinc(struct ksz_device *dev, int port, u32 val) 1504 { 1505 val = val >> 8; 1506 1507 return ksz_pwrite16(dev, port, REG_PORT_MTI_CREDIT_INCREMENT, val); 1508 } 1509 1510 /* The KSZ9477 provides following HW features to accelerate 1511 * HSR frames handling: 1512 * 1513 * 1. TX PACKET DUPLICATION FROM HOST TO SWITCH 1514 * 2. RX PACKET DUPLICATION DISCARDING 1515 * 3. PREVENTING PACKET LOOP IN THE RING BY SELF-ADDRESS FILTERING 1516 * 1517 * Only one from point 1. has the NETIF_F* flag available. 1518 * 1519 * Ones from point 2 and 3 are "best effort" - i.e. those will 1520 * work correctly most of the time, but it may happen that some 1521 * frames will not be caught - to be more specific; there is a race 1522 * condition in hardware such that, when duplicate packets are received 1523 * on member ports very close in time to each other, the hardware fails 1524 * to detect that they are duplicates. 1525 * 1526 * Hence, the SW needs to handle those special cases. However, the speed 1527 * up gain is considerable when above features are used. 1528 * 1529 * Moreover, the NETIF_F_HW_HSR_FWD feature is also enabled, as HSR frames 1530 * can be forwarded in the switch fabric between HSR ports. 1531 */ 1532 #define KSZ9477_SUPPORTED_HSR_FEATURES (NETIF_F_HW_HSR_DUP | NETIF_F_HW_HSR_FWD) 1533 1534 void ksz9477_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr) 1535 { 1536 struct ksz_device *dev = ds->priv; 1537 struct net_device *user; 1538 struct dsa_port *hsr_dp; 1539 u8 data, hsr_ports = 0; 1540 1541 /* Program which port(s) shall support HSR */ 1542 ksz_rmw32(dev, REG_HSR_PORT_MAP__4, BIT(port), BIT(port)); 1543 1544 /* Forward frames between HSR ports (i.e. bridge together HSR ports) */ 1545 if (dev->hsr_ports) { 1546 dsa_hsr_foreach_port(hsr_dp, ds, hsr) 1547 hsr_ports |= BIT(hsr_dp->index); 1548 1549 hsr_ports |= BIT(dsa_upstream_port(ds, port)); 1550 dsa_hsr_foreach_port(hsr_dp, ds, hsr) 1551 ksz9477_cfg_port_member(dev, hsr_dp->index, hsr_ports); 1552 } 1553 1554 if (!dev->hsr_ports) { 1555 /* Enable discarding of received HSR frames */ 1556 ksz_read8(dev, REG_HSR_ALU_CTRL_0__1, &data); 1557 data |= HSR_DUPLICATE_DISCARD; 1558 data &= ~HSR_NODE_UNICAST; 1559 ksz_write8(dev, REG_HSR_ALU_CTRL_0__1, data); 1560 } 1561 1562 /* Enable per port self-address filtering. 1563 * The global self-address filtering has already been enabled in the 1564 * ksz9477_reset_switch() function. 1565 */ 1566 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, PORT_SRC_ADDR_FILTER, true); 1567 1568 /* Setup HW supported features for lan HSR ports */ 1569 user = dsa_to_port(ds, port)->user; 1570 user->features |= KSZ9477_SUPPORTED_HSR_FEATURES; 1571 } 1572 1573 void ksz9477_hsr_leave(struct dsa_switch *ds, int port, struct net_device *hsr) 1574 { 1575 struct ksz_device *dev = ds->priv; 1576 1577 /* Clear port HSR support */ 1578 ksz_rmw32(dev, REG_HSR_PORT_MAP__4, BIT(port), 0); 1579 1580 /* Disable forwarding frames between HSR ports */ 1581 ksz9477_cfg_port_member(dev, port, BIT(dsa_upstream_port(ds, port))); 1582 1583 /* Disable per port self-address filtering */ 1584 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, PORT_SRC_ADDR_FILTER, false); 1585 } 1586 1587 int ksz9477_switch_init(struct ksz_device *dev) 1588 { 1589 u8 data8; 1590 int ret; 1591 1592 dev->port_mask = (1 << dev->info->port_cnt) - 1; 1593 1594 /* turn off SPI DO Edge select */ 1595 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1596 if (ret) 1597 return ret; 1598 1599 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1600 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1601 if (ret) 1602 return ret; 1603 1604 return 0; 1605 } 1606 1607 void ksz9477_switch_exit(struct ksz_device *dev) 1608 { 1609 ksz9477_reset_switch(dev); 1610 } 1611 1612 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1613 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1614 MODULE_LICENSE("GPL"); 1615